Change in coreboot[master]: mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62924 )

Change subject: mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED
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mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED

Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.

Signed-off-by: Felix Held 
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) 
Reviewed-by: Raul Rangel 
Reviewed-by: Jon Murphy 
---
M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved
  Jon Murphy: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
index 7d4fb7f..03bb55e 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
@@ -47,6 +47,8 @@
    register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR
    register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC

+	register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
+
    device domain 0 on
    	device ref lpc_bridge on
    		chip ec/google/chromeec

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.