[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85559?usp=email

to look at the new patch set (#3).

The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Use _SB.POSC on all platforms
......................................................................

soc/intel/xeon_sp: Use _SB.POSC on all platforms

Reduce ACPI code size by using the existing _SB.POSC instead of
duplicating the method in every PCI/CXL host bridge.

TEST: On ocp/tiogapass the OS still gets granted the PCIe capabilities
      as previously through _OSC. Reduces DSDT size by 1366 bytes.

Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
4 files changed, 9 insertions(+), 139 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85559/3