Change in coreboot[master]: mb/google/poppy/var/nocturne: Relocate devicetree FSP settings
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43878 )
Change subject: mb/google/poppy/var/nocturne: Relocate devicetree FSP settings ......................................................................
mb/google/poppy/var/nocturne: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I3c589b2f9853211054b0ef6ebe4821a04385b7d1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 99 insertions(+), 118 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/43878/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2eb7bd2..38b4a6e 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -37,26 +37,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "1" - register "SaImguEnable" = "1" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -145,28 +131,6 @@ .dc_loadline = 430, }"
- # PCIe Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - - # Root port 9 (x2) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ2# - # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty @@ -182,77 +146,10 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Touchscreen | - #| I2C1 | Trackpad | - #| I2C3 | Camera | - #| I2C4 | Audio | - #| I2C5 | Rear Camera & SAR | - #| pch_thermal_trip | PCH Trip Temperature | - #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 186, - .scl_hcnt = 93, - .sda_hold = 36, - }, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, .pch_thermal_trip = 75, }" - # Touchscreen - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - - # Trackpad - register "i2c_voltage[1]" = "I2C_VOLTAGE_1V8" - - # Front Camera - register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" - - # Audio - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - - # Rear Camera & SAR - register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"
register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -275,6 +172,12 @@ device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device
+ # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + + # FIXME: corresponding device entry is missing + register "SaImguEnable" = "1" + device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -307,23 +210,39 @@ device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "common_soc_config.i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST_PLUS" - register "generic.probed" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" - register "generic.reset_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0a on end end end # I2C #0 - Touchscreen device pci 15.1 on + register "i2c_voltage[1]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[1]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + }, + }" chip drivers/i2c/sx9310 register "desc" = ""Right SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" @@ -356,15 +275,37 @@ end end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 - Camera - device pci 16.0 on end # Management Engine Interface 1 + device pci 15.3 on # I2C #3 - Camera + register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" + end + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA + device pci 17.0 off # SATA + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + end device pci 19.0 on end # UART #2 device pci 19.1 on + register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" chip drivers/i2c/sx9310 register "desc" = ""Left SAR Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" @@ -397,6 +338,16 @@ end end # I2C #5 device pci 19.2 on + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }" chip drivers/i2c/max98373 register "vmon_slot_no" = "4" register "imon_slot_no" = "5" @@ -415,6 +366,12 @@ end end # I2C #4 - Audio device pci 1c.0 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" chip drivers/intel/wifi register "wake" = "GPE0_DW2_01" device pci 00.0 on end @@ -427,13 +384,24 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "2" + register "PcieRpClkSrcNumber[8]" = "3" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on + register "common_soc_config.gspi[0]" = "{ + .speed_mhz = 1, + .early_init = 1, + }" chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" @@ -452,9 +420,14 @@ device spi 0 on end end # FPMCU end # GSPI #1 - device pci 1e.4 on end # eMMC + device pci 1e.4 on # eMMC + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end @@ -462,9 +435,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43878 )
Change subject: mb/google/poppy/var/nocturne: Relocate devicetree FSP settings ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43878
to look at the new patch set (#2).
Change subject: mb/google/poppy/var/nocturne: Relocate devicetree settings ......................................................................
mb/google/poppy/var/nocturne: Relocate devicetree settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I3c589b2f9853211054b0ef6ebe4821a04385b7d1 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 99 insertions(+), 118 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/43878/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43878 )
Change subject: mb/google/poppy/var/nocturne: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)