[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 88:

(2 comments)

File src/soc/intel/pantherlake/chipset.cb:

https://review.coreboot.org/c/coreboot/+/83798/comment/1430fc80_a8925cab?usp... :
PS50, Line 15:
> > I am checking this data from PNP team. […]

Hi,can we take up this to a crosbug, and mark TODO.

File src/soc/intel/pantherlake/pcie_rp.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/6ec77644_6495ea17?usp... :
PS87, Line 22: #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
> > Hi, EDS 1 #815002 section2.3 table 8 lists PTL-U/H 12Xe3 = PCIe #12, while PTL-H […]

Acknowledged