Change in ...coreboot[master]: src/mainboard/pcengines/apu1: Enable LPC TPM

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30354

Change subject: src/mainboard/pcengines/apu1: Enable LPC TPM
......................................................................

src/mainboard/pcengines/apu1: Enable LPC TPM

PC Engines apu1 has a 20 pin LPC header that allows connection of
external TPM module.

Add necessary Kconfig option and devicetree entry for TPM.

Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd
Signed-off-by: Michał Żygowski 
---
M src/mainboard/pcengines/apu1/Kconfig
M src/mainboard/pcengines/apu1/devicetree.cb
2 files changed, 32 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30354/1

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 9d42159..07aaa8c 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -31,6 +31,7 @@
    select BOARD_ROMSIZE_KB_2048
    select GENERIC_SPD_BIN
    select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
+	select MAINBOARD_HAS_LPC_TPM

config MAINBOARD_DIR
    string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..acdabd1 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,35 +43,38 @@
    				device pci 14.1 off end # IDE	0x439c
    				device pci 14.2 off end # HDA	0x4383
    				device pci 14.3 on # LPC		0x439d
-					chip superio/nuvoton/nct5104d
-						register "irq_trigger_type" = "0"
-						device pnp 2e.0 off end
-						device pnp 2e.2 on
-							io 0x60 = 0x3f8
-							irq 0x70 = 4
+						chip superio/nuvoton/nct5104d
+							register "irq_trigger_type" = "0"
+							device pnp 2e.0 off end
+							device pnp 2e.2 on
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 on
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.10 off
+								# UART C is conditionally turned on
+								io 0x60 = 0x3e8
+								irq 0x70 = 4
+							end
+							device pnp 2e.11 off
+								# UART D is conditionally turned on
+								io 0x60 = 0x2e8
+								irq 0x70 = 3
+							end
+							device pnp 2e.8 off end
+							device pnp 2e.f off end
+							# GPIO0 and GPIO1 are conditionally turned on
+							device pnp 2e.007 off end
+							device pnp 2e.107 off end
+							device pnp 2e.607 off end
+							device pnp 2e.e off end
    					end
-						device pnp 2e.3 on
-							io 0x60 = 0x2f8
-							irq 0x70 = 3
-						end
-						device pnp 2e.10 off
-							# UART C is conditionally turned on
-							io 0x60 = 0x3e8
-							irq 0x70 = 4
-						end
-						device pnp 2e.11 off
-							# UART D is conditionally turned on
-							io 0x60 = 0x2e8
-							irq 0x70 = 3
-						end
-						device pnp 2e.8 off end
-						device pnp 2e.f off end
-						# GPIO0 and GPIO1 are conditionally turned on
-						device pnp 2e.007 off end
-						device pnp 2e.107 off end
-						device pnp 2e.607 off end
-						device pnp 2e.e off end
-					end
+						chip drivers/pc80/tpm
+							device pnp 0c31.0 on end
+						end # LPC TPM
    				end #LPC
    				device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
    				device pci 14.5 off end # OHCI FS/LS USB