Alexey Buyanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44051 )
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in.
BUG=none TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov alexey.buyanov@intel.com Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 --- M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/include/soc/bootblock.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c 6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44051/1
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index e7d97c5..96e6268 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9fc5ce1..68a5c53 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -147,7 +147,7 @@ pch_enable_lpc(); }
-void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 783009b..87be0e0 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_pch_early_init(void);
/* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void);
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index bd6096b..baa35c5 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -9,7 +9,7 @@ bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void);
/* Board type */ enum board_type { diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c index 9fd8a1e..d3c2554 100644 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -3,7 +3,7 @@ #include <intelblocks/smbus.h> #include <soc/romstage.h>
-void pch_init(void) +void romstage_pch_init(void) { /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 5463238..db014ea 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44051 )
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44051/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44051/1//COMMIT_MSG@12 PS1, Line 12: BUG=none don't need
Hello build bot (Jenkins), Selma Bensaid, Subrata Banik, Usha P, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44051
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov alexey.buyanov@intel.com Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 --- M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/include/soc/bootblock.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c 6 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44051/2
Alexey Buyanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44051 )
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
Patch Set 2:
(1 comment)
Hi, unnecessary line removed. Thanks.
https://review.coreboot.org/c/coreboot/+/44051/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44051/1//COMMIT_MSG@12 PS1, Line 12: BUG=none
don't need
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44051 )
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44051 )
Change subject: soc/intel/tigerlake: Rename pch_init() code ......................................................................
soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov alexey.buyanov@intel.com Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/bootblock/bootblock.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/include/soc/bootblock.h M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c 6 files changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index e7d97c5..96e6268 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -25,7 +25,7 @@ void bootblock_soc_init(void) { report_platform_info(); - pch_init(); + bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 63beeaa..18ca5e5 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -141,7 +141,7 @@ pch_enable_lpc(); }
-void pch_init(void) +void bootblock_pch_init(void) { /* * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h index 783009b..87be0e0 100644 --- a/src/soc/intel/tigerlake/include/soc/bootblock.h +++ b/src/soc/intel/tigerlake/include/soc/bootblock.h @@ -8,7 +8,7 @@ void bootblock_pch_early_init(void);
/* Bootblock post console init programming */ -void pch_init(void); +void bootblock_pch_init(void); void pch_early_iorange_init(void); void report_platform_info(void);
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h index bd6096b..baa35c5 100644 --- a/src/soc/intel/tigerlake/include/soc/romstage.h +++ b/src/soc/intel/tigerlake/include/soc/romstage.h @@ -9,7 +9,7 @@ bool mainboard_get_dram_part_num(const char **part_num, size_t *len); void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); -void pch_init(void); +void romstage_pch_init(void);
/* Board type */ enum board_type { diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c index 9fd8a1e..d3c2554 100644 --- a/src/soc/intel/tigerlake/romstage/pch.c +++ b/src/soc/intel/tigerlake/romstage/pch.c @@ -3,7 +3,7 @@ #include <intelblocks/smbus.h> #include <soc/romstage.h>
-void pch_init(void) +void romstage_pch_init(void) { /* Program SMBUS_BASE_ADDRESS and Enable it */ smbus_common_init(); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 5463238..db014ea 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -131,7 +131,7 @@ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program PCH init */ - pch_init(); + romstage_pch_init(); /* initialize Heci interface */ heci_init(HECI1_BASE_ADDRESS);