[M] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion

[Mario Scheithauer (Code Review)]

Attention is currently required from: Eric Lai, Felix Singer, Jan Samek, Sean Rhodes, Werner Zeh.

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email )

Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
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Patch Set 5:

(2 comments)

Patchset:

PS5:
> why not ask FSP to fix

I'm afraid Intel will not fix anything for Apollo Lake anymore unless it's security relevant.

File src/soc/intel/apollolake/include/soc/ahci.h:

https://review.coreboot.org/c/coreboot/+/75820/comment/ed98c446_dd39ba4c :
PS5, Line 12:
> extra space

It's a bit field inside AHCI_CAP register, so most other header files mark this with an extra space.