Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon

[Subrata Banik (Code Review)]

Attention is currently required from: Selma Bensaid, Sridhar Siricilla, Rizwan Qureshi, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56073 )

Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
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Patch Set 5:

(5 comments)

File src/mainboard/intel/adlrvp/bootblock.c:

https://review.coreboot.org/c/coreboot/+/56073/comment/1f3eb013_cdfef36f 
PS5, Line 20: X
nit: 0x10?

https://review.coreboot.org/c/coreboot/+/56073/comment/477fcec6_b9ec2f97 
PS5, Line 27: 0xFF0A55A
nit:
#define FLVALSIG 0xFF0A55A

https://review.coreboot.org/c/coreboot/+/56073/comment/bb6761cc_bc93d1f3 
PS5, Line 35: 1
nit: BIT(0)

https://review.coreboot.org/c/coreboot/+/56073/comment/53c90ab0_8e87f9c3 
PS5, Line 62: if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x40) {
if (si_desc_buf[PMC_DESC_7_BYTE3] != 0x40) {
    printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n");
        return;
}

si_desc_buf[PMC_DESC_7_BYTE3] = 0x44;
...

you would save one tab and line 76 which is > 96 would get normalized in that way

https://review.coreboot.org/c/coreboot/+/56073/comment/57a31ce5_6b15db82 
PS5, Line 78: 1
nit: true