Change in coreboot[master]: mb/google/corsola: correct NOR flash configuration in GPIO set

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59945 )

Change subject: mb/google/corsola: correct NOR flash configuration in GPIO set
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mb/google/corsola: correct NOR flash configuration in GPIO set

The reference design has changed to use GPIO SET1 for NOR flash.
There are no devices already built using SET0 so we can safely
change the implementation without conditional configs.

Reference document:
kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11.
crab_proto 0_2021112.pdf, page 11.

BUG=b:202871018
TEST=flash verify pass on kingler on bootblock stage

Signed-off-by: Rex-BC Chen 
Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Paul Menzel 
---
M src/mainboard/google/corsola/bootblock.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/corsola/bootblock.c b/src/mainboard/google/corsola/bootblock.c
index ea36fed..0b03d04 100644
--- a/src/mainboard/google/corsola/bootblock.c
+++ b/src/mainboard/google/corsola/bootblock.c
@@ -10,7 +10,7 @@
 {
    mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
-	mtk_snfc_init(SPI_NOR_GPIO_SET0);
+	mtk_snfc_init(SPI_NOR_GPIO_SET1);
    setup_chromeos_gpios();
    gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING);
 }