[M] Change in coreboot[master]: soc/amd/common/psp_verstage: move post codes to own header
Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75809?usp=email )
Change subject: soc/amd/common/psp_verstage: move post codes to own header ......................................................................
soc/amd/common/psp_verstage: move post codes to own header
In order to clean up the post code macros, move them to a seperate header away from unrelated code.
Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43 Signed-off-by: lilacious yuchenhe126@gmail.com --- A src/soc/amd/common/psp_verstage/include/psp_post_code.h M src/soc/amd/common/psp_verstage/include/psp_verstage.h 2 files changed, 36 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/75809/1
diff --git a/src/soc/amd/common/psp_verstage/include/psp_post_code.h b/src/soc/amd/common/psp_verstage/include/psp_post_code.h new file mode 100644 index 0000000..44464b6 --- /dev/null +++ b/src/soc/amd/common/psp_verstage/include/psp_post_code.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef PSP_POST_CODE_H +#define PSP_POST_CODE_H + +#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00 +#define POSTCODE_CONSOLE_INIT 0x01 +#define POSTCODE_EARLY_INIT 0x02 +#define POSTCODE_LATE_INIT 0x03 +#define POSTCODE_VERSTAGE_MAIN 0x04 +#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 + +#define POSTCODE_SAVE_BUFFERS 0x0E +#define POSTCODE_UPDATE_BOOT_REGION 0x0F + +#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 +#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 +#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 +#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3 +#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4 +#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 +#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6 +#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xC9 +#define POSTCODE_CMOS_RECOVERY 0xCA +#define POSTCODE_EARLY_INIT_ERROR 0xCB +#define POSTCODE_INIT_TPM_FAILED 0xCC +#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD + +#define POSTCODE_UNMAP_SPI_ROM 0xF0 +#define POSTCODE_UNMAP_FCH_DEVICES 0xF1 +#define POSTCODE_LEAVING_VERSTAGE 0xF2 + +#endif diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index 6c5d4c0..0663c4a 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -8,6 +8,7 @@ #include <bl_uapp/bl_syscall_public.h> #include <stdint.h> #include <soc/psp_transfer.h> +#include <psp_post_code.h>
#define EMBEDDED_FW_SIGNATURE 0x55aa55aa #define PSP_COOKIE 0x50535024 /* 'PSP$' */ @@ -15,35 +16,6 @@
#define PSP_VBOOT_ERROR_SUBCODE 0x0D5D0000
-#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00 -#define POSTCODE_CONSOLE_INIT 0x01 -#define POSTCODE_EARLY_INIT 0x02 -#define POSTCODE_LATE_INIT 0x03 -#define POSTCODE_VERSTAGE_MAIN 0x04 -#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05 - -#define POSTCODE_SAVE_BUFFERS 0x0E -#define POSTCODE_UPDATE_BOOT_REGION 0x0F - -#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0 -#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1 -#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2 -#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3 -#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4 -#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 -#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6 -#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 -#define POSTCODE_FMAP_REGION_MISSING 0xC8 -#define POSTCODE_AMD_FW_MISSING 0xC9 -#define POSTCODE_CMOS_RECOVERY 0xCA -#define POSTCODE_EARLY_INIT_ERROR 0xCB -#define POSTCODE_INIT_TPM_FAILED 0xCC -#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD - -#define POSTCODE_UNMAP_SPI_ROM 0xF0 -#define POSTCODE_UNMAP_FCH_DEVICES 0xF1 -#define POSTCODE_LEAVING_VERSTAGE 0xF2 - #define SPI_ADDR_MASK 0x00ffffff #define MIN_TRANSFER_BUFFER_SIZE (8 * KiB) #define MIN_WORKBUF_TRANSFER_SIZE (MIN_TRANSFER_BUFFER_SIZE - TRANSFER_INFO_SIZE)
-
Yuchen He (Code Review)