[M] Change in coreboot[master]: arch/x86/postcar_loader: Don't add postcar to stage cache

[Reka Norman (Code Review)]

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68641 )

Change subject: arch/x86/postcar_loader: Don't add postcar to stage cache
......................................................................

arch/x86/postcar_loader: Don't add postcar to stage cache

In romstage, CBMEM and TSEG are not yet cached, so reading/writing to
the stage cache is slow. This means there isn't really any benefit to
adding postcar to the stage cache:
 - During boot, adding it to the stage cache adds a few ms of boot time,
   since writing to uncached memory is slow.
 - During S3 resume, reading from stage cache takes rougly the same time
   as reading from SPI, so we get little or no savings anyway.

E.g. on nivviks, this change saves 6 ms of boot time and 2 ms of S3
resume time.

Adding postcar to stage cache:
Boot:
  rmodule_stage_load()     - 4 ms
  stage_cache_add()        - 6 ms
S3 resume:
  stage_cache_load_stage() - 6 ms

Not adding postcar to stage cache:
Boot:
  rmodule_stage_load()     - 4 ms
S3 resume:
  rmodule_stage_load()     - 4 ms

Savings:
Boot time      - 6 ms
S3 resume time - 2 ms

------------------------------------
Savings on other devices:

nivviks anahera kindred treeya
rmodule_stage_load()          4.0     1.4     0.8    2.8
stage_cache_add()             6.0     2.8     1.5    2.0
stage_cache_load_stage()      6.0     2.8     1.5    2.0

Boot time savings             6.0     2.8     1.5    2.0
S3 resume time savings        2.0     1.4     0.7   -0.8

BUG=b:247940538
TEST=On nivviks, boot and check S3 resume still works. Add logging to
check postcar is added to stage cache when POSTCAR_IN_STAGE_CACHE is
selected, and not added otherwise.

Change-Id: I3614c0874a6c71d13606b0b782ea445692d88bb1
Signed-off-by: Reka Norman 
---
M src/arch/x86/Kconfig
M src/arch/x86/postcar_loader.c
2 files changed, 67 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/68641/1

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c00eb0c..bba3eba 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -207,6 +207,16 @@
    depends on ARCH_X86
    depends on !RESET_VECTOR_IN_RAM

+config POSTCAR_IN_STAGE_CACHE
+	bool
+	depends on !NO_STAGE_CACHE && POSTCAR_STAGE
+	help
+	  In romstage, CBMEM and TSEG are not yet cached, so reading and
+	  writing to stage cache is slow. This means on most platforms
+	  adding postcar to the stage cache gives little if any S3 resume
+	  time savings, while also adding a few ms of boot time. Therefore
+	  this config is disabled by default.
+
 config VERSTAGE_DEBUG_SPINLOOP
    bool
    default n
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index c6a128b..8987e25 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -110,7 +110,8 @@

finalize_load(rsl.params, (uintptr_t)pcf->mtrr);

-	stage_cache_add(STAGE_POSTCAR, prog);
+	if (CONFIG(POSTCAR_IN_STAGE_CACHE))
+		stage_cache_add(STAGE_POSTCAR, prog);
 }

/*
@@ -141,7 +142,7 @@
    struct prog prog =
    	PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar");

-	if (resume_from_stage_cache()) {
+	if (CONFIG(POSTCAR_IN_STAGE_CACHE) && resume_from_stage_cache()) {
    	stage_cache_load_stage(STAGE_POSTCAR, &prog);
    	/* This is here to allow platforms to pass different stack
    	   parameters between S3 resume and normal boot. On the