Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73125 )
Change subject: mb/google/dedede/var/dibbi: Enable USB2 port 6 ......................................................................
mb/google/dedede/var/dibbi: Enable USB2 port 6
USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the port.
BUG=b:269690930 TEST=kernel can detect a PL2303 USB device BRANCH=dedede
Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05 Signed-off-by: Sam McNally sammc@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Reka Norman rekanorman@chromium.org Reviewed-by: Dtrain Hsu dtrain_hsu@compal.corp-partner.google.com --- M src/mainboard/google/dedede/variants/dibbi/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Dtrain Hsu: Looks good to me, approved Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 1c463b9..69307a3 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -53,6 +53,7 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # PL2303
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
-
Eric Lai (Code Review)