Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 )

Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................

Patch Set 4:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi_def.h:

https://review.coreboot.org/c/coreboot/+/63777/comment/087403fc_43e1ba4b 
PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff)
> I mean since the lower byte was alredy 'hard' coded in this define you could proceed the style with bit 8 as well:
>
> #define SPIBAR_HSFSTS_W1C_BITS		0x1ff
>
> Just a nit, up to you

sure