[S] Change in coreboot[main]: [WIP] soc/amd/glinda: Update MCA banks

[Maximilian Brune (Code Review)]

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84374?usp=email )

Change subject: [WIP] soc/amd/glinda: Update MCA banks
......................................................................

[WIP] soc/amd/glinda: Update MCA banks

TODO commit-msg

Change-Id: I16f5f9db08ab3232caa64fcdc90b8fc062869fcc
Signed-off-by: Maximilian Brune 
---
M src/soc/amd/glinda/mca.c
1 file changed, 21 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84374/1

diff --git a/src/soc/amd/glinda/mca.c b/src/soc/amd/glinda/mca.c
index c843f4e..e89f0c8 100644
--- a/src/soc/amd/glinda/mca.c
+++ b/src/soc/amd/glinda/mca.c
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

-/* TODO: Update for Glinda */
-
 #include <amdblocks/mca.h>
 #include <cpu/x86/msr.h>
 #include <types.h>
@@ -18,12 +16,27 @@
    [8]  = "L3 cache unit",
    [9]  = "L3 cache unit",
    [10] = "L3 cache unit",
-	[11] = "UMC",
-	[12] = "UMC",
-	[13] = "CS",
-	[14] = "CS",
-	[15] = "NBIO",
-	[16] = "PIE",
+	[11] = "L3 cache unit",
+	[12] = "L3 cache unit",
+	[13] = "L3 cache unit",
+	[14] = "L3 cache unit",
+	[15] = "UMC",
+	[16] = "UMC",
+	[17] = "UMC",
+	[18] = "UMC",
+	[19] = "CS",
+	[20] = "CS",
+	[21] = "CS",
+	[22] = "CS",
+	[23] = "",
+	[24] = "",
+	[25] = "",
+	[26] = "",
+	[27] = "PIE",
+	[28] = "NBIO",
+	[29] = "KPX_SERDES",
+	[30] = "KPX_SERDES",
+	[31] = "",
 };

bool mca_has_expected_bank_count(void)