[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable FPS

[Subrata Banik (Code Review)]

Attention is currently required from: Pranava Y N.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85687?usp=email )

Change subject: mb/google/fatcat/var/fatcat: Enable FPS
......................................................................

mb/google/fatcat/var/fatcat: Enable FPS

Lists of changes:
- GPIO programmimg

FPMCU_PWREN -> GPP_E19 -> OUTPUT
SOC_INT_L   -> GPP_D1 -> INPUT
FPMCU_FW_UPDATE -> GPP_E20 -> NF1
FPS_RST_N -> GPP_C15 -> OUTPUT
GPP_F16_GSPI0A_CLK -> GPP_F16 -> SPI CLK -> NF8
GPP_F15_GSPI0A_MISO -> GPP_F15 -> SPI MISO -> NF8
GPP_F14_GPSI0A_MOSI -> GPP_F14 -> SPI MOSI -> NF8
GPP_F18_GSPI0A_CS0 -> GPP_F18 -> SPI CS -> NF8

- ACPI Entry
- Keep ISH (0x12.0) enable for GSPI0A to be operational

BUG=b:377595986
TEST=TBD

Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
2 files changed, 42 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/85687/1

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 47a5c3a..0a524b7 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -130,8 +130,8 @@
    PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
    /* GPP_C14:     CLKREQ5_X1_GEN4_M2_WWAN_N */
    PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
-	/* GPP_C15:     CRD1_CLK_EN */
-	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
    /* GPP_C16:     TBT_LSX0_TXD  */
    PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
    /* GPP_C17:     TBT_LSX0_RXD  */
@@ -151,8 +151,8 @@

/* GPP_D00:     IMGCLKOUT_1 */
    PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
-	/* GPP_D01:     MOD_TCSS1_TYP_A_VBUS_EN */
-	PAD_CFG_GPO(GPP_D01, 1, DEEP),
+	/* GPP_D01 : [] ==> FPS_SOC_INT_L */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT),
    /* GPP_D02:     Not used */
    PAD_NC(GPP_D02, NONE),
    /* GPP_D03:     M.2_WWAN_PERST_GPIO_N */
@@ -234,10 +234,10 @@
    PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3),
    /* GPP_E18:     THC0_SPI1_INT_N_TCH_PNL1 */
    PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
-	/* GPP_E19:     PEG_SLOT_DGPU_SEL_N */
-	PAD_CFG_GPO(GPP_E19, 1, PLTRST),
-	/* GPP_E20:     PEG_SLOT_DGPU_PWR_OK */
-	PAD_CFG_GPI(GPP_E20, NONE, PLTRST),
+	/* GPP_E19:     FPMCU_PWREN */
+	PAD_CFG_GPO(GPP_E19, 1, DEEP),
+	/* GPP_E20:     FPMCU_FW_UPDATE */
+	PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
    /* GPP_E21:     I2C_PMC_PD_INT_N */
    PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
    /* GPP_E22:     THC0_SPI1_DSYNC */
@@ -277,16 +277,16 @@
    PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
    /* GPP_F13:     THC_I2C1_SDA_TCH_PAD */
    PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
-	/* GPP_F14:     Not used */
-	PAD_NC(GPP_F14, NONE),
-	/* GPP_F15:     Not used */
-	PAD_NC(GPP_F15, NONE),
-	/* GPP_F16:     Not used */
-	PAD_NC(GPP_F16, NONE),
+	/* GPP_F14:     GPP_F14_GPSI0A_MOSI */
+	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
+	/* GPP_F15:     GPP_F15_GSPI0A_MISO */
+	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
+	/* GPP_F16:     GPP_F16_GPSI0A_CLK */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8),
    /* GPP_F17:     Not used */
    PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
-	/* GPP_F18:     TCH_PAD_INT_N */
-	PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F18:     GPP_F18_GSPI0A_CS0 */
+	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8),
    /* GPP_F19:     GPP_PRIVACY_LED_CAM2 */
    PAD_CFG_GPO(GPP_F19, 0, PLTRST),
    /* GPP_F20:     GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
@@ -413,6 +413,8 @@
    PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
    /* GPP_C01:     GPP_C1_SMBDATA */
    PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+	/* GPP_C15:     FPS_RST_N */
+	PAD_CFG_GPO(GPP_C15, 0, DEEP),
 };

const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
index 44ea511..9bcdacd 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb
@@ -107,6 +107,12 @@
    	[PchSerialIoIndexI2C5]  = PchSerialIoPci,
    }"

+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI0A] = PchSerialIoPci,
+	}"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |
@@ -357,6 +363,7 @@

device ref ish on
    		probe ISH ISH_ENABLE
+			probe FP FP_PRESENT
    		chip drivers/intel/ish
    			register "add_acpi_dma_property" = "true"
    			device generic 0 on end
@@ -777,5 +784,22 @@
    			end
    		end
    	end
+		device ref gspi0a on
+			chip drivers/spi/acpi
+				register "name" = ""CRFP""
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""google,cros-ec-spi""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
+				register "wake" = "GPE0_DW1_01"
+				register "has_power_resource" = "1"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
+				register "enable_delay_ms" = "3"
+				device spi 0 on
+					probe FP FP_PRESENT
+				end
+			end # FPMCU
+		end
    end
 end