[S] Change in coreboot[main]: soc/intel/common/block/cpu: Use the effective way size for NEM+

[Jérémy Compostella (Code Review)]

Attention is currently required from: Subrata Banik.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )

Change subject: soc/intel/common/block/cpu: Use the effective way size for NEM+
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Patch Set 5:

(1 comment)

File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/83946/comment/258dc692_3031ec0d?usp... :
PS4, Line 498: INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE
> As I learned from the Intel cache team during another hang issue in Ovis with 18MB of cache, when we […]

I am limiting the Way Size to the Effective Way Size allowing me to compute the Max NEM Size. On a SKU with the following LLC.

Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 24576
    Cache size = 18 MiB

I get a way size of  1 * 64 * 24576 = 1572864 = 0x1800000.
Then an effective way size of 0x100000
leading to a NEM size of 12 MB which is aligned with MTL HAS or Alder Lake EDS.