Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/25604
to look at the new patch set (#5).
Change subject: nb/intel/gm45: Put stage cache in TSEG ......................................................................
nb/intel/gm45: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages.
Untested.
Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/stage_cache.c 3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25604/5