Change in coreboot[master]: security/vboot: Interface FSP 2.0 mrc caching

[Philipp Deppenwiese (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/24904

to look at the new patch set (#3).

Change subject: security/vboot: Interface FSP 2.0 mrc caching
......................................................................

security/vboot: Interface FSP 2.0 mrc caching

* Add weak interface for multiple mrc hash and verify implementations.
* Move vboot/tpm specific implementation to vboot.

Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Signed-off-by: Philipp Deppenwiese <[e-mail]>
---
A src/drivers/intel/fsp2_0/include/fsp/memory_init.h
M src/drivers/intel/fsp2_0/memory_init.c
A src/security/vboot/mrc_cache_hash_tpm.c
3 files changed, 148 insertions(+), 95 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/24904/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Gerrit-Change-Number: 24904
Gerrit-PatchSet: 3
Gerrit-Owner: Philipp Deppenwiese <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>