Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44894 )
Change subject: mb/google/zork: update GPIO config for dirinboz ......................................................................
mb/google/zork: update GPIO config for dirinboz
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3.
BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu kevin.chiu@quantatw.com --- M src/mainboard/google/zork/variants/dirinboz/gpio.c 1 file changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44894/1
diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 12b303a..8da85b6 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -8,6 +8,10 @@ #include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), /* TP */ PAD_NC(GPIO_32), /* EN_DEV_BEEP_L */ @@ -16,6 +20,13 @@ PAD_GPO(GPIO_140, HIGH), };
+static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -33,6 +44,6 @@ return bid_1_gpio_set_stage_ram; }
- *size = 0; - return NULL; + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; }
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44894 )
Change subject: mb/google/zork: update GPIO config for dirinboz ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44894 )
Change subject: mb/google/zork: update GPIO config for dirinboz ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44894 )
Change subject: mb/google/zork: update GPIO config for dirinboz ......................................................................
mb/google/zork: update GPIO config for dirinboz
dirinboz does not support stylus, config AGPIO4/5 to NC to prevent unexpected wake event for s3.
BUG=none BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage
Change-Id: I3cfdeb326c3d3775148b2a00732c7d848dab35cb Signed-off-by: Kevin Chiu kevin.chiu@quantatw.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44894 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/zork/variants/dirinboz/gpio.c 1 file changed, 13 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/dirinboz/gpio.c b/src/mainboard/google/zork/variants/dirinboz/gpio.c index 12b303a..8da85b6 100644 --- a/src/mainboard/google/zork/variants/dirinboz/gpio.c +++ b/src/mainboard/google/zork/variants/dirinboz/gpio.c @@ -8,6 +8,10 @@ #include <ec/google/chromeec/ec.h>
static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), /* TP */ PAD_NC(GPIO_32), /* EN_DEV_BEEP_L */ @@ -16,6 +20,13 @@ PAD_GPO(GPIO_140, HIGH), };
+static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = { + /* PEN_DETECT_ODL - no used */ + PAD_NC(GPIO_4), + /* PEN_POWER_EN - no used */ + PAD_NC(GPIO_5), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -33,6 +44,6 @@ return bid_1_gpio_set_stage_ram; }
- *size = 0; - return NULL; + *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram); + return dirinboz_gpio_set_stage_ram; }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44894 )
Change subject: mb/google/zork: update GPIO config for dirinboz ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 6/1/7 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17300 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17299 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/17298 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17297 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/17296 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/17302 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/17301
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aaron Durbin (Code Review)
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Furquan Shaikh (Code Review)
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Kevin Chiu (Code Review)
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Patrick Georgi (Code Review)