Change in coreboot[master]: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans.
Hello Arthur Heymans,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/63024

to review the following change.

Change subject: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields
......................................................................

sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields

Clang complains about this.

Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/i82801ix/chip.h
M src/southbridge/intel/i82801jx/chip.h
2 files changed, 14 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63024/1

diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index 3ec68ae..600025e 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -3,6 +3,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
 #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H

+#include "stddef.h"
 #include <stdint.h>

enum {
@@ -55,17 +56,17 @@

/* IDE configuration */
    uint8_t sata_port_map : 6;
-	int sata_clock_request : 1;
-	int sata_traffic_monitor : 1;
+	unsigned int sata_clock_request : 1;
+	unsigned int sata_traffic_monitor : 1;

-	int c4onc3_enable:1;
-	int c5_enable : 1;
-	int c6_enable : 1;
+	unsigned int c4onc3_enable:1;
+	unsigned int c5_enable : 1;
+	unsigned int c6_enable : 1;

-	int throttle_duty : 3;
+	unsigned int throttle_duty : 3;

/* Bit mask to tell whether a PCIe slot is implemented as slot. */
-	int pcie_slot_implemented : 6;
+	unsigned int pcie_slot_implemented : 6;

/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
    struct {
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
index e9632d2..ae31d4f 100644
--- a/src/southbridge/intel/i82801jx/chip.h
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -42,16 +42,16 @@

/* IDE configuration */
    uint8_t sata_port_map : 6;
-	int sata_clock_request : 1;
+	unsigned int sata_clock_request : 1;

-	int c4onc3_enable:1;
-	int c5_enable : 1;
-	int c6_enable : 1;
+	unsigned int c4onc3_enable:1;
+	unsigned int c5_enable : 1;
+	unsigned int c6_enable : 1;

-	int throttle_duty : 3;
+	unsigned int throttle_duty : 3;

/* Bit mask to tell whether a PCIe slot is implemented as slot. */
-	int pcie_slot_implemented : 6;
+	unsigned int pcie_slot_implemented : 6;

/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
    struct {