Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 )

Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi_def.h:

https://review.coreboot.org/c/coreboot/+/63777/comment/5bc17dcf_dd4d22b1 
PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff)
> BTW: 0x1ff would be valid here, too. This would follow the previous style better.

Sorry Werner, I didn't get this part.

Are you suggesting like this?

#define SPIBAR_HSFSTS_W1C_BITS		(0xff | SPIBAR_HSFSTS_SAF_CE)