Attention is currently required from: Tarun Tuli, Maximilian Brune, Lean Sheng Tan.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73736 )
Change subject: soc/intel/alderlake: Enable early caching of TOM region ......................................................................
Patch Set 3: Verified+1
(4 comments)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/a5e4bf02_22199db8 PS3, Line 12: For further details, please refer to: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit bc8bbeed3b8a ("soc/intel/cmn/tom: Cache TOM region early")'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/da9ee74f_6843e8f6 PS3, Line 13: commit bc8bbee Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 725dd39f5b91 ("soc/intel/cmn/sa: Store TOM into the CMOS")'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/ffe8b3a1_0ad0700c PS3, Line 14: commit 725dd39 Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit dbfbfaf608c3 ("drivers/intel/fsp2_0: Have provision for caching TOM region")'
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-174184): https://review.coreboot.org/c/coreboot/+/73736/comment/e2dd6675_adacf26b PS3, Line 15: commit dbfbfaf Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 01209524f4b3 ("soc/intel/meteorlake: Enable early caching of TOM region")'
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