[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 6:

(1 comment)

File src/soc/intel/pantherlake/include/soc/gpe.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/b7f02175_99588e26?usp... :
PS4, Line 30: 146
> 18 is the bit 18 defined in GPE1_STS_31_0 (0x10) and GPE1_EN_31_0 (0x1C) registers.
>
> 0x80 is GPE0_REG_MAX x sizeof(uint32_t) x 8

i understand that it's bit number but not everyone has EDS access. Hence,

better would be 
```
#define GPE_1_0 0
#define GPE_1_1 1
#define GPE_1_2 3

#define GEP1_OFFSET(blk, n) (GPE_START_NUM + (blk) * 32 + (n))

#define CNVI_BT_PME_B0 18
#define GPE1_CNVI_BT_PME_B0 GEP1_OFFSET(GPE_1_0, CNVI_BT_PME_B0)
```