New patch to review for coreboot: glados: Disable unused USB ports

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11548

-gerrit

commit ea7d9f3ae48fc3d9b29bb3e4256591a773efc9e8
Author: Duncan Laurie 
Date:   Fri Aug 28 17:22:04 2015 -0700

glados: Disable unused USB ports

Enable only the USB ports that are connected on-board or to an
    external port, all others will be disabled.

BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados, ensure expected USB ports still work

Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163
    Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/296035
    Original-Commit-Ready: Aaron Durbin 
    Original-Reviewed-by: Aaron Durbin 
---
 src/mainboard/google/glados/devicetree.cb | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 9bb065d..2c6d997 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,6 +20,18 @@ chip soc/intel/skylake
    	[PchSerialIoIndexUart2] = PchSerialIoPci, \
    }"

+	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
+	register "PortUsb20Enable[4]" = "1"	/* Type-A Port 1 */
+	register "PortUsb20Enable[6]" = "1"	/* Camera */
+	register "PortUsb20Enable[8]" = "1"	/* Type-A Port 2 */
+
+	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
+	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
+	register "PortUsb30Enable[2]" = "1"	/* Type-A Port 1 */
+	register "PortUsb30Enable[3]" = "1"	/* Type-A Port 2 */
+
    # Enable Root port 1 and 5.
    register "PcieRpEnable[0]" = "1"
    register "PcieRpEnable[4]" = "1"