[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Enable IRQ routing

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84328?usp=email )

Change subject: soc/intel/xeon_sp/gnr: Enable IRQ routing
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Patch Set 1:

(1 comment)

File src/soc/intel/xeon_sp/gnr/chip.c:

https://review.coreboot.org/c/coreboot/+/84328/comment/38aa70db_db820bd3?usp... :
PS1, Line 64: pch_pirq_init
that seems to be done as part of espi/lpc init. Would that be possible instead of using a bootstate hook?