Attention is currently required from: Philipp Hug, ron minnich.
Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email )
Change subject: mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE ......................................................................
mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE
Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8
The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM.
Do not compile a separate romstage so that nothing must be decompressed into SRAM. The separate romstage is not needed on the board anyway and probably also gives a little bit of performance improvement.
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81910/1
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index d3ecd2a..f90d2d7 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -5,10 +5,11 @@ #include <console/streams.h> #include <console/uart.h> #include <program_loading.h> +#include <romstage_common.h> #include <soc/clock.h> #include <soc/sdram.h>
-void main(void) +void __noreturn romstage_main(void) { console_init();
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index fb15762..3d1db3b 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -15,6 +15,9 @@ select UART_OVERRIDE_REFCLK select RISCV_HAS_OPENSBI
+config SEPARATE_ROMSTAGE + default n if SOC_SIFIVE_FU540 + if SOC_SIFIVE_FU540
config MEMLAYOUT_LD_FILE