Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Felix Held, Hannah Williams, Jamie Ryu.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions ......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/5e91c719_8cd4bae8?usp... : PS11, Line 241: gpe0_mask
it is gpe0_mask indeed, as all GPE1 events are finer granularity of some GPE0 events, which included TCSS/non-TCSS PME_B0, hot plug, PCIe events. For instance, if GPE0 PME_EN is disabled, the [internal device]_PME_EN bits will also needs to be disabled. Same thing apply to hot plug and PCIe events. There is no additional types of event added in GPE1. The purpose of GPE1 events is for performance matter. Instead of waking up all device and finding out which one is the event source. GPE1 events is checked directly.
I don't agree with this statement, I can't share the EDS2 code snippet but I can confirmly tell CNVI_BT_PME_B0_STS part of GPE1 event but not present anywhere in GPE0_STS_127_96. Hence, I made statememt saying as per my observation looking at EDS, GPE1 event are for all internal IPs those are not covered by GPE0_STS_127_96.