[S] Change in coreboot[master]: [Test] [Do Not Merge] Rex: Move CSE FW sync to RAMSTAGE

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74623 )

Change subject: [Test] [Do Not Merge] Rex: Move CSE FW sync to RAMSTAGE
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[Test] [Do Not Merge] Rex: Move CSE FW sync to RAMSTAGE

Change-Id: I0a5922f40e719e1bc4e6dc58559d820172550dee
---
M src/mainboard/google/rex/Kconfig
M src/soc/intel/meteorlake/romstage/romstage.c
2 files changed, 11 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/74623/1

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 62ece95..575c51e 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -41,6 +41,7 @@
    select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
    select SYSTEM_TYPE_LAPTOP
    select TPM_GOOGLE_TI50
+	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE

if BOARD_GOOGLE_REX_COMMON

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index ebb440c..ea0931d 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -128,7 +128,7 @@
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);

-	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
+	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE)) {
    	timestamp_add_now(TS_CSE_FW_SYNC_START);
    	cse_fw_sync();
    	timestamp_add_now(TS_CSE_FW_SYNC_END);