Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52907 )
Change subject: [WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call ......................................................................
[WIP] soc/amd/cezanne/early_fch: add missing fch_spi_early_init call
Before this can be merged, the mainboard's devicetrees need to be updated to set common_config.spi_config to working value, since the frequencies default to 66MHz in non-EM100 mode which might be too much.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I224b99b1aace3e4220bccec836efee0130ebbfdb --- M src/soc/amd/cezanne/early_fch.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/52907/1
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c index fdfa17a..2da338f 100644 --- a/src/soc/amd/cezanne/early_fch.c +++ b/src/soc/amd/cezanne/early_fch.c @@ -36,6 +36,7 @@ void fch_pre_init(void) { lpc_early_init(); + fch_spi_early_init();
enable_acpimmio_decode_pm04(); fch_smbus_init();