Change in coreboot[master]: nb/intel/ironlake: Print MCH dev/revision IDs and CAPID

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49576 )

Change subject: nb/intel/ironlake: Print MCH dev/revision IDs and CAPID
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nb/intel/ironlake: Print MCH dev/revision IDs and CAPID

Given the lack of documentation for this platform, having this info
in coreboot logs (e.g. from board_status) can be pretty useful.

Change-Id: I6a743c1efc1b6da71589460a69bfe4785e3e77a2
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/raminit.c
1 file changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/49576/1

diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index beb2244..44c6daa 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1480,10 +1480,14 @@
    	info->memory_reserved_for_heci_mb = intel_early_me_uma_size();
    }

-	for (i = 0; i < 3; i++)
-		gav(capid0[i] =
-		    pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)));
-	gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID));
+	for (i = 0; i < 3; i++) {
+		capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2));
+		printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]);
+	}
+	info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID);
+	printk(BIOS_DEBUG, "Revision ID: 0x%x\n", info->revision);
+	printk(BIOS_DEBUG, "Device ID: 0x%x\n", pci_read_config16(NORTHBRIDGE, PCI_DEVICE_ID));
+
    info->max_supported_clock_speed_index = (~capid0[1] & 7);

if ((capid0[1] >> 11) & 1)