Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76097?usp=email )
Change subject: soc/intel/adl: Add power limits for RPL-H 4P+8E 45W ......................................................................
soc/intel/adl: Add power limits for RPL-H 4P+8E 45W
Change-Id: I01ae5a484287d2adb1516e1e4551b185b895fdde Ref: RPL-UPH and RPL-U Refresh Platform Design Guide (#686872, rev 2.1) Signed-off-by: Tim Crawford tcrawford@system76.com --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/vr_config.c 2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/76097/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 699d163..bbe42c8 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -136,6 +136,7 @@ { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, + { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index e24d095..2a272fb 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -129,6 +129,7 @@ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -168,6 +169,7 @@ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, + { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, @@ -207,6 +209,7 @@ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -246,6 +249,7 @@ { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, + { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) },
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Tim Crawford (Code Review)