[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

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Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu.

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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 9:

(5 comments)

Patchset:

PS9: 
I've moved the wrong copying and update ASL to ASL2 syntax, please double check.

File src/soc/intel/snowridge/COPYING-NOTICE:

PS3:
> This probably does not belong here.

Done

File src/soc/intel/snowridge/acpi/pci_irqs.asl:

https://review.coreboot.org/c/coreboot/+/83321/comment/c3c9f8ea_9bafd67e?usp... :
PS2, Line 19: ShiftLeft
> Please use ASL2 syntax

Done

https://review.coreboot.org/c/coreboot/+/83321/comment/d65f1193_d9be8444?usp... :
PS2, Line 26: Decrement (Local0)	\
            : 			Store (Local0, ^^PRC##id)
> Please use ASL2 syntax

Done

https://review.coreboot.org/c/coreboot/+/83321/comment/643bd49d_b01f1d9b?usp... :
PS2, Line 30: \
            : 			If (And (^^PRC##id, ^^IREN))	\
            : 			{	\
            : 				Return (0x9)	\
            : 			}	\
            : 			Else	\
            : 			{	\
            : 				Return (0xb)	\
            : 			}	\
            : 		}	\
            : 		Method (_DIS, 0, Serialized)	\
            : 		{	\
            : 			Or(^^IREN, PRC##id, PRC##id)	\
            : 		}	\
            : 	}
> Please use ASL2 syntax […]

Done