[S] Change in coreboot[main]: soc/intel/snowridge: add CPU and PCIe definitions for SNR - coreboot-gerrit

4 Jul 2024


      Attention is currently required from: Jérémy Compostella, Shuo Liu.
yuchi.chen@intel.com has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email )
Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
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Patch Set 2:
(1 comment)
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/83314/comment/a1143fc3_e91f140b?usp... :
PS1, Line 86: #define CPUID_SNOWRIDGE_A0	0x80660
...
Isn't it missing an extra tab for indentation ?
Yes, I've added it.
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Gerrit-MessageType: comment
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Gerrit-Change-Number: 83314
Gerrit-PatchSet: 2
Gerrit-Owner: yuchi.chen@intel.com
Gerrit-Reviewer: Jérémy Compostella jeremy.compostella@intel.com
Gerrit-Reviewer: Shuo Liu shuo.liu@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
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Gerrit-Comment-Date: Thu, 04 Jul 2024 02:11:36 +0000
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