Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Subrata Banik, Wonkyu Kim.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID and fix vw mapping ......................................................................
Patch Set 5:
(6 comments)
Patchset:
PS5:
can you split this cl into two cls […]
sure. this sounds better. will do.
File src/soc/intel/common/block/gpio/Kconfig:
https://review.coreboot.org/c/coreboot/+/83981/comment/5edf53dc_e71e3b1c?usp... : PS5, Line 66: config SOC_INTEL_COMMON_BLOCK_GPIO_16BIT_CPU_PORTID : bool : default n : help : In newer SOC, port ID has been extended to 16-bit. This must be set to accommodate : the structure to hold the 16-bit value. :
Thx for helping out!
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83981/comment/e0461ed6_b81fc1f3?usp... : PS5, Line 1062: /* Get the community (potentially updating 'comm' if vw_map exists) */ : comm = gpio_get_community(pad);
remove this as line #1060
my bad again. Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/37403f31_e01f4917?usp... : PS5, Line 1064: : /* Find the VW entry containing 'pad' */
same as well
Acknowledged
https://review.coreboot.org/c/coreboot/+/83981/comment/d35d2df9_0c22443d?usp... : PS5, Line 1073: /* Check if we found a valid entry */
u can drop this comment. […]
Acknowledged
File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/c/coreboot/+/83981/comment/c1352eb0_9c2f52ae?usp... : PS5, Line 113: /* virtual-wire mapping base and the starting bit position for a group */ : struct vw_map { : uint8_t base; : uint8_t start_pos; : };
keep this part of the vw cl
will do