[S] Change in coreboot[main]: mb/google/brya/var/trulo: Add PnP descriptions

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83566?usp=email )

Change subject: mb/google/brya/var/trulo: Add PnP descriptions
......................................................................

mb/google/brya/var/trulo: Add PnP descriptions

This patch adds power related entries (FIVR and policy to control
lower power c-state transitioning) to the device tree.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/trulo/overridetree.cb
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/83566/1

diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 22e3606..dff8af2 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -103,6 +103,21 @@
    register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
    register "pch_hda_idisp_codec_enable" = "1"

+	# Configure external V1P05/Vnn/VnnSx Rails
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
+		.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
+		.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
+		.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
+		.v1p05_voltage_mv = 1050,
+		.vnn_voltage_mv = 780,
+		.vnn_sx_voltage_mv = 1050,
+		.v1p05_icc_max_ma = 500,
+		.vnn_icc_max_ma = 500,
+	}"
+
    register "serial_io_i2c_mode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoPci,
@@ -123,6 +138,10 @@
    	[PchSerialIoIndexUART2] = PchSerialIoDisabled,
    }"

+	# FIXME: To be enabled in future based on PNP impact data.
+	# Disable Package C-state demotion for nissa baseboard.
+	register "disable_package_c_state_demotion" = "1"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |