[M] Change in coreboot[master]: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
Attention is currently required from: Stefan Ott, Angel Pons, Werner Zeh, Alexander Couzens.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69297 )
Change subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm ......................................................................
Patch Set 18:
(2 comments)
File src/northbridge/intel/gm45/northbridge.c:
https://review.coreboot.org/c/coreboot/+/69297/comment/d88f6812_12df67c5 PS18, Line 264: __pci_0_00_0
Shall this better be 'pcidev_on_root(0, 0);'?
It's not the same. pcidev_on_root finds a dev at runtime while this is a direct reference to it. If it's missing it won't compile.
File src/southbridge/intel/i82801ix/lpc.c:
https://review.coreboot.org/c/coreboot/+/69297/comment/dbdd0cc5_104b5fd1 PS18, Line 143: __pci_0_1f_0
pcidev_on_root(0x1f, 0)?
See other comment.
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Arthur Heymans (Code Review)