Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4296
-gerrit
commit 05ab6fa0d68d9fd8abcbb0c71ab15eccdd4a6ae2 Author: Vladimir Serbinenko phcoder@gmail.com Date: Thu Nov 28 00:22:54 2013 +0100
src/: Annoy all the whitespace guys
Here is a result of pretty simple script which fixes all whitespaces when tab is more appropriate. Be annoyed.
Change-Id: Ib743a0a619d53b6807e7992f7423c3655dd55a80 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/Kconfig | 16 +- src/arch/armv7/Makefile.inc | 42 +- src/arch/armv7/bootblock.inc | 2 +- src/arch/armv7/cache.c | 4 +- src/arch/armv7/coreboot_ram.ld | 16 +- src/arch/armv7/id.inc | 4 +- src/arch/armv7/include/arch/cache.h | 2 +- src/arch/armv7/include/arch/cpu.h | 6 +- src/arch/armv7/include/assembler.h | 4 +- src/arch/armv7/include/stdint.h | 44 +- src/arch/armv7/interrupts.c | 20 +- src/arch/armv7/memmove.S | 38 +- src/arch/armv7/mmu.c | 8 +- src/arch/armv7/romstage.ld | 2 +- src/arch/x86/Makefile.inc | 66 +- src/arch/x86/acpi/statdef.asl | 44 +- src/arch/x86/boot/acpi.c | 8 +- src/arch/x86/boot/acpigen.c | 98 +- src/arch/x86/boot/boot.c | 2 +- src/arch/x86/boot/mpspec.c | 64 +- src/arch/x86/boot/pirq_routing.c | 6 +- src/arch/x86/boot/smbios.c | 4 +- src/arch/x86/boot/tables.c | 12 +- src/arch/x86/coreboot_ram.ld | 16 +- src/arch/x86/include/arch/acpi.h | 32 +- src/arch/x86/include/arch/cpu.h | 34 +- src/arch/x86/include/arch/io.h | 84 +- src/arch/x86/include/arch/pci_io_cfg.h | 26 +- src/arch/x86/include/arch/smp/mpspec.h | 8 +- src/arch/x86/include/stdint.h | 44 +- src/arch/x86/lib/c_start.S | 10 +- src/arch/x86/lib/cpu.c | 40 +- src/arch/x86/lib/exception.c | 300 +- src/arch/x86/lib/id.inc | 2 +- src/arch/x86/lib/ioapic.c | 14 +- src/arch/x86/lib/pci_ops_conf1.c | 8 +- src/arch/x86/lib/pci_ops_mmconf.c | 8 +- src/arch/x86/lib/rom_media.c | 2 +- src/arch/x86/lib/thread.c | 2 +- src/arch/x86/lib/thread_switch.S | 14 +- src/console/cbmem_console.c | 2 +- src/console/console.c | 2 +- src/console/logbuf_console.c | 2 +- src/console/post.c | 2 +- src/console/qemu_debugcon_console.c | 4 +- src/console/spkmodem_console.c | 2 +- src/console/uart8250_console.c | 2 +- src/console/uart8250mem_console.c | 2 +- src/console/usbdebug_console.c | 2 +- src/cpu/Makefile.inc | 4 +- src/cpu/amd/agesa/family10/Kconfig | 10 +- src/cpu/amd/agesa/family10/model_10_init.c | 10 +- src/cpu/amd/agesa/family12/Makefile.inc | 12 +- src/cpu/amd/agesa/family12/model_12_init.c | 10 +- src/cpu/amd/agesa/family14/model_14_init.c | 10 +- src/cpu/amd/agesa/family15/Kconfig | 10 +- src/cpu/amd/agesa/family15/model_15_init.c | 24 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/agesa/s3_resume.c | 6 +- src/cpu/amd/agesa/s3_resume.h | 4 +- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/car/post_cache_as_ram.c | 4 +- src/cpu/amd/dualcore/amd_sibling.c | 32 +- src/cpu/amd/dualcore/dualcore.c | 18 +- src/cpu/amd/dualcore/dualcore_id.c | 24 +- src/cpu/amd/geode_gx2/cache_as_ram.inc | 22 +- src/cpu/amd/geode_lx/cache_as_ram.inc | 30 +- src/cpu/amd/geode_lx/cpureginit.c | 22 +- src/cpu/amd/model_10xxx/defaults.h | 40 +- src/cpu/amd/model_10xxx/fidvid.c | 330 +- src/cpu/amd/model_10xxx/init_cpus.c | 28 +- src/cpu/amd/model_10xxx/mc_patch_01000086.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_01000095.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_01000096.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_0100009f.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000b6.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000bf.h | 10 +- src/cpu/amd/model_10xxx/mc_patch_010000c4.h | 10 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 18 +- src/cpu/amd/model_10xxx/processor_name.c | 2 +- src/cpu/amd/model_10xxx/update_microcode.c | 32 +- src/cpu/amd/model_fxx/fidvid.c | 44 +- src/cpu/amd/model_fxx/init_cpus.c | 14 +- src/cpu/amd/model_fxx/model_fxx_init.c | 20 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 54 +- src/cpu/amd/model_fxx/powernow_acpi.c | 20 +- src/cpu/amd/sc520/raminit.c | 42 +- src/cpu/amd/sc520/sc520.c | 62 +- src/cpu/amd/socket_S1G1/Kconfig | 2 +- src/cpu/dmp/vortex86ex/biosdata.inc | 20 +- src/cpu/dmp/vortex86ex/biosdata_ex.inc | 62 +- src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc | 1024 ++--- src/cpu/intel/car/cache_as_ram.inc | 2 +- src/cpu/intel/car/cache_as_ram_ht.inc | 2 +- src/cpu/intel/fit/fit.inc | 2 +- src/cpu/intel/haswell/Makefile.inc | 2 +- src/cpu/intel/haswell/acpi.c | 2 +- src/cpu/intel/haswell/cache_as_ram.inc | 28 +- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/haswell/haswell_init.c | 54 +- src/cpu/intel/haswell/microcode_blob.h | 8 +- src/cpu/intel/haswell/mp_init.c | 28 +- src/cpu/intel/haswell/romstage.c | 14 +- src/cpu/intel/haswell/smmrelocate.c | 42 +- src/cpu/intel/microcode/microcode.c | 10 +- src/cpu/intel/microcode/update-microcodes.sh | 24 +- src/cpu/intel/model_1067x/model_1067x_init.c | 14 +- src/cpu/intel/model_106cx/model_106cx_init.c | 12 +- src/cpu/intel/model_2065x/acpi.c | 2 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 22 +- src/cpu/intel/model_2065x/microcode_blob.h | 8 +- src/cpu/intel/model_2065x/model_2065x_init.c | 18 +- src/cpu/intel/model_206ax/acpi.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 28 +- src/cpu/intel/model_206ax/microcode_blob.h | 8 +- src/cpu/intel/model_206ax/model_206ax_init.c | 18 +- src/cpu/intel/model_65x/model_65x_init.c | 4 +- src/cpu/intel/model_67x/microcode-293-MU267114.h | 2 +- src/cpu/intel/model_67x/microcode-530-MU16730e.h | 2 +- src/cpu/intel/model_67x/microcode-531-MU26732e.h | 2 +- src/cpu/intel/model_67x/microcode-539-MU167210.h | 2 +- src/cpu/intel/model_67x/microcode-540-MU267238.h | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 4 +- src/cpu/intel/model_68x/microcode-534-MU16810d.h | 2 +- src/cpu/intel/model_68x/microcode-535-MU16810e.h | 2 +- src/cpu/intel/model_68x/microcode-536-MU16810f.h | 2 +- src/cpu/intel/model_68x/microcode-537-MU268110.h | 2 +- src/cpu/intel/model_68x/microcode-538-MU168111.h | 2 +- src/cpu/intel/model_68x/microcode-550-MU168307.h | 2 +- src/cpu/intel/model_68x/microcode-551-MU168308.h | 2 +- src/cpu/intel/model_68x/microcode-611-MU168607.h | 2 +- src/cpu/intel/model_68x/microcode-612-MU168608.h | 2 +- src/cpu/intel/model_68x/microcode-615-MU16860a.h | 2 +- src/cpu/intel/model_68x/microcode-617-MU16860c.h | 2 +- src/cpu/intel/model_68x/microcode-618-MU268602.h | 2 +- src/cpu/intel/model_68x/microcode-662-MU168a01.h | 2 +- src/cpu/intel/model_68x/microcode-691-MU168a04.h | 2 +- src/cpu/intel/model_68x/microcode-692-MU168a05.h | 2 +- src/cpu/intel/model_68x/microcode-727-MU168313.h | 2 +- src/cpu/intel/model_68x/microcode-728-MU168314.h | 2 +- src/cpu/intel/model_68x/microcode-729-MU268310.h | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 12 +- src/cpu/intel/model_69x/model_69x_init.c | 12 +- src/cpu/intel/model_6bx/model_6bx_init.c | 12 +- src/cpu/intel/model_6dx/model_6dx_init.c | 12 +- src/cpu/intel/model_6ex/model_6ex_init.c | 12 +- src/cpu/intel/model_6fx/model_6fx_init.c | 14 +- src/cpu/intel/model_6xx/model_6xx_init.c | 12 +- src/cpu/intel/model_f0x/model_f0x_init.c | 12 +- src/cpu/intel/model_f1x/model_f1x_init.c | 12 +- src/cpu/intel/model_f2x/model_f2x_init.c | 12 +- src/cpu/intel/model_f3x/model_f3x_init.c | 10 +- src/cpu/intel/model_f4x/model_f4x_init.c | 10 +- src/cpu/intel/slot_1/l2_cache.c | 12 +- src/cpu/intel/socket_LGA771/Kconfig | 2 +- src/cpu/intel/speedstep/acpi.c | 20 +- src/cpu/intel/speedstep/speedstep.c | 4 +- src/cpu/qemu-x86/qemu.c | 2 +- src/cpu/samsung/exynos5250/Makefile.inc | 2 +- src/cpu/samsung/exynos5250/clk.h | 2 +- src/cpu/samsung/exynos5250/clock.c | 8 +- src/cpu/samsung/exynos5250/cpu.c | 12 +- src/cpu/samsung/exynos5250/cpu.h | 2 +- src/cpu/samsung/exynos5250/dmc.h | 2 +- src/cpu/samsung/exynos5250/dmc_common.c | 4 +- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 14 +- src/cpu/samsung/exynos5250/dp.h | 4 +- src/cpu/samsung/exynos5250/dsim.h | 4 +- src/cpu/samsung/exynos5250/fb.c | 26 +- src/cpu/samsung/exynos5250/gpio.c | 2 +- src/cpu/samsung/exynos5250/gpio.h | 8 +- src/cpu/samsung/exynos5250/power.h | 6 +- src/cpu/samsung/exynos5250/setup.h | 224 +- src/cpu/samsung/exynos5250/spi.c | 6 +- src/cpu/samsung/exynos5250/spi.h | 4 +- src/cpu/samsung/exynos5250/uart.c | 2 +- src/cpu/samsung/exynos5250/usb.h | 58 +- src/cpu/samsung/exynos5420/Makefile.inc | 2 +- src/cpu/samsung/exynos5420/clk.h | 2 +- src/cpu/samsung/exynos5420/clock.c | 8 +- src/cpu/samsung/exynos5420/cpu.c | 12 +- src/cpu/samsung/exynos5420/cpu.h | 2 +- src/cpu/samsung/exynos5420/dmc.h | 2 +- src/cpu/samsung/exynos5420/dmc_common.c | 4 +- src/cpu/samsung/exynos5420/dp.h | 4 +- src/cpu/samsung/exynos5420/dsim.h | 4 +- src/cpu/samsung/exynos5420/fb.c | 26 +- src/cpu/samsung/exynos5420/gpio.c | 2 +- src/cpu/samsung/exynos5420/gpio.h | 8 +- src/cpu/samsung/exynos5420/i2c.c | 24 +- src/cpu/samsung/exynos5420/power.h | 6 +- src/cpu/samsung/exynos5420/setup.h | 114 +- src/cpu/samsung/exynos5420/spi.c | 16 +- src/cpu/samsung/exynos5420/spi.h | 4 +- src/cpu/samsung/exynos5420/uart.c | 2 +- src/cpu/samsung/exynos5420/usb.h | 58 +- src/cpu/ti/am335x/Makefile.inc | 4 +- src/cpu/ti/am335x/bootblock_media.c | 2 +- src/cpu/ti/am335x/header.c | 4 +- src/cpu/ti/am335x/nand.c | 2 +- src/cpu/ti/am335x/uart.c | 2 +- src/cpu/via/c3/c3_init.c | 4 +- src/cpu/via/c7/c7_init.c | 16 +- src/cpu/via/car/cache_as_ram.inc | 4 +- src/cpu/via/nano/nano_init.c | 8 +- src/cpu/via/nano/update_ucode.c | 2 +- src/cpu/via/nano/update_ucode.h | 46 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/16bit/reset16.inc | 2 +- src/cpu/x86/16bit/reset16.lds | 2 +- src/cpu/x86/car.c | 6 +- src/cpu/x86/lapic/apic_timer.c | 4 +- src/cpu/x86/lapic/lapic_cpu_init.c | 4 +- src/cpu/x86/lapic/secondary.S | 4 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 62 +- src/cpu/x86/smm/Makefile.inc | 6 +- src/cpu/x86/smm/smihandler.c | 4 +- src/cpu/x86/smm/smm_module_handler.c | 2 +- src/cpu/x86/smm/smm_module_loader.c | 30 +- src/cpu/x86/smm/smm_stub.S | 2 +- src/cpu/x86/smm/smmhandler.S | 56 +- src/cpu/x86/smm/smmhandler_tseg.S | 60 +- src/cpu/x86/smm/smmrelocate.S | 8 +- src/device/agp_device.c | 12 +- src/device/azalia_device.c | 2 +- src/device/cardbus_device.c | 18 +- src/device/device.c | 156 +- src/device/device_util.c | 30 +- src/device/dram/ddr3.c | 68 +- src/device/hypertransport.c | 90 +- src/device/oprom/include/x86emu/fpu_regs.h | 44 +- src/device/oprom/include/x86emu/regs.h | 154 +- src/device/oprom/include/x86emu/types.h | 8 +- src/device/oprom/include/x86emu/x86emu.h | 58 +- src/device/oprom/realmode/x86.c | 8 +- src/device/oprom/realmode/x86_asm.S | 4 +- src/device/oprom/realmode/x86_interrupts.c | 6 +- src/device/oprom/x86emu/LICENSE | 4 +- src/device/oprom/x86emu/debug.c | 260 +- src/device/oprom/x86emu/debug.h | 112 +- src/device/oprom/x86emu/decode.c | 832 ++-- src/device/oprom/x86emu/decode.h | 46 +- src/device/oprom/x86emu/fpu.c | 1096 ++--- src/device/oprom/x86emu/fpu.h | 12 +- src/device/oprom/x86emu/ops.c | 4702 ++++++++++---------- src/device/oprom/x86emu/ops.h | 8 +- src/device/oprom/x86emu/ops2.c | 1926 ++++---- src/device/oprom/x86emu/prim_asm.h | 1246 +++--- src/device/oprom/x86emu/prim_ops.c | 1440 +++--- src/device/oprom/x86emu/prim_ops.h | 188 +- src/device/oprom/x86emu/sys.c | 18 +- src/device/oprom/x86emu/x86emui.h | 12 +- src/device/oprom/yabel/biosemu.c | 10 +- src/device/oprom/yabel/compat/functions.c | 4 +- src/device/oprom/yabel/compat/rtas.h | 14 +- src/device/oprom/yabel/device.c | 12 +- src/device/oprom/yabel/interrupt.c | 86 +- src/device/oprom/yabel/io.c | 84 +- src/device/oprom/yabel/mem.c | 32 +- src/device/oprom/yabel/pmm.c | 52 +- src/device/oprom/yabel/vbe.c | 28 +- src/device/pci_device.c | 88 +- src/device/pci_ops.c | 16 +- src/device/pci_rom.c | 36 +- src/device/pciexp_device.c | 24 +- src/device/pcix_device.c | 14 +- src/device/pnp_device.c | 10 +- src/device/root_device.c | 14 +- src/device/smbus_ops.c | 6 +- src/drivers/ati/ragexl/atyfb.h | 18 +- src/drivers/ati/ragexl/fb.h | 116 +- src/drivers/ati/ragexl/fbcon.h | 48 +- src/drivers/ati/ragexl/mach64.h | 4 +- src/drivers/ati/ragexl/mach64_ct.c | 16 +- src/drivers/ati/ragexl/xlinit.c | 882 ++-- src/drivers/dec/21143/21143.c | 12 +- src/drivers/elog/elog.c | 42 +- src/drivers/elog/elog_internal.h | 2 +- src/drivers/elog/gsmi.c | 8 +- src/drivers/emulation/qemu/bochs.c | 48 +- src/drivers/emulation/qemu/cirrus.c | 26 +- src/drivers/generic/debug/debug_dev.c | 174 +- src/drivers/generic/ioapic/ioapic.c | 16 +- src/drivers/i2c/adm1026/adm1026.c | 14 +- src/drivers/i2c/lm63/lm63.c | 2 +- src/drivers/i2c/w83795/w83795.c | 4 +- src/drivers/ics/954309/ics954309.c | 8 +- src/drivers/ipmi/ipmi_kcs.c | 4 +- src/drivers/oxford/oxpcie/oxpcie.c | 10 +- src/drivers/pc80/i8254.c | 16 +- src/drivers/pc80/i8259.c | 34 +- src/drivers/pc80/isa-dma.c | 18 +- src/drivers/pc80/keyboard.c | 6 +- src/drivers/pc80/mc146818rtc.c | 2 +- src/drivers/pc80/tpm.c | 80 +- src/drivers/pc80/vga/vga.h | 6 +- src/drivers/pc80/vga/vga_font_8x16.c | 6 +- src/drivers/pc80/vga/vga_io.c | 26 +- src/drivers/pc80/vga/vga_palette.c | 498 +-- src/drivers/sil/3114/sil_sata.c | 12 +- src/drivers/spi/eon.c | 20 +- src/drivers/spi/gigadevice.c | 22 +- src/drivers/spi/macronix.c | 2 +- src/drivers/spi/spansion.c | 2 +- src/drivers/spi/spi_flash.c | 2 +- src/drivers/spi/spi_flash_internal.h | 2 +- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 2 +- src/drivers/spi/winbond.c | 2 +- src/drivers/ti/tps65090/tps65090.c | 12 +- src/drivers/ti/tps65090/tps65090.h | 12 +- src/drivers/trident/blade3d/blade3d.c | 40 +- src/ec/acpi/ec.h | 22 +- src/ec/compal/ene932/acpi/battery.asl | 8 +- src/ec/compal/ene932/acpi/ec.asl | 438 +- src/ec/compal/ene932/ec.c | 6 +- src/ec/compal/ene932/ec.h | 10 +- src/ec/google/chromeec/Kconfig | 2 +- src/ec/google/chromeec/acpi/battery.asl | 14 +- src/ec/google/chromeec/acpi/superio.asl | 14 +- src/ec/google/chromeec/crosec_proto.c | 16 +- src/ec/google/chromeec/ec.c | 18 +- src/ec/google/chromeec/ec.h | 4 +- src/ec/google/chromeec/ec_commands.h | 182 +- src/ec/google/chromeec/ec_i2c.c | 20 +- src/ec/google/chromeec/ec_lpc.c | 6 +- src/ec/google/chromeec/ec_spi.c | 2 +- src/ec/kontron/it8516e/acpi/ec.asl | 4 +- src/ec/kontron/it8516e/ec.c | 56 +- src/ec/lenovo/h8/acpi/battery.asl | 4 +- src/ec/lenovo/h8/acpi/ec.asl | 94 +- src/ec/lenovo/h8/acpi/lid.asl | 2 +- src/ec/lenovo/h8/acpi/sleepbutton.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 12 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/quanta/ene_kb3940q/acpi/battery.asl | 10 +- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 158 +- src/ec/quanta/ene_kb3940q/ec.c | 4 +- src/ec/quanta/ene_kb3940q/ec.h | 74 +- src/ec/quanta/it8518/acpi/battery.asl | 32 +- src/ec/quanta/it8518/acpi/ec.asl | 922 ++-- src/ec/quanta/it8518/ec.c | 4 +- src/ec/quanta/it8518/ec.h | 64 +- src/ec/smsc/mec1308/acpi/battery.asl | 12 +- src/ec/smsc/mec1308/ec.c | 2 +- src/ec/smsc/mec1308/ec.h | 8 +- src/include/boot/coreboot_tables.h | 48 +- src/include/bootstate.h | 48 +- src/include/cbfs.h | 10 +- src/include/cbfs_core.h | 18 +- src/include/cbmem.h | 2 +- src/include/console/console.h | 176 +- src/include/console/loglevel.h | 18 +- src/include/cpu/amd/common/cbtypes.h | 2 +- src/include/cpu/amd/gx1def.h | 22 +- src/include/cpu/amd/model_fxx_msr.h | 2 +- src/include/cpu/amd/model_fxx_rev.h | 72 +- src/include/cpu/amd/sc520.h | 8 +- src/include/cpu/amd/vr.h | 148 +- src/include/cpu/intel/l2_cache.h | 22 +- src/include/cpu/intel/speedstep.h | 8 +- src/include/cpu/x86/bist.h | 2 +- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/msr.h | 4 +- src/include/cpu/x86/mtrr.h | 12 +- src/include/cpu/x86/multiboot.h | 14 +- src/include/cpu/x86/post_code.h | 6 +- src/include/cpu/x86/smm.h | 18 +- src/include/device/azalia.h | 130 +- src/include/device/device.h | 12 +- src/include/device/dram/ddr3.h | 44 +- src/include/device/drm_dp_helper.h | 184 +- src/include/device/hypertransport_def.h | 12 +- src/include/device/i915_reg.h | 2820 ++++++------ src/include/device/pci_def.h | 52 +- src/include/device/pci_ids.h | 346 +- src/include/device/pciexp.h | 4 +- src/include/device/pnp.h | 2 +- src/include/ehci.h | 8 +- src/include/elog.h | 148 +- src/include/memrange.h | 20 +- src/include/pc80/i8254.h | 50 +- src/include/pc80/mc146818rtc.h | 18 +- src/include/rmodule.h | 2 +- src/include/sdram_mode.h | 18 +- src/include/smbios.h | 4 +- src/include/spd.h | 184 +- src/include/stdlib.h | 8 +- src/include/string.h | 12 +- src/include/thread.h | 4 +- src/include/timer.h | 14 +- src/include/trace.h | 2 +- src/include/uart8250.h | 110 +- src/include/usb_ch9.h | 100 +- src/include/vbe.h | 8 +- src/lib/cbfs.c | 38 +- src/lib/cbfs_core.c | 32 +- src/lib/cbmem.c | 8 +- src/lib/cbmem_console.c | 2 +- src/lib/cbmem_info.c | 10 +- src/lib/clog2.c | 20 +- src/lib/coreboot_table.c | 22 +- src/lib/dynamic_cbmem.c | 12 +- src/lib/edid.c | 240 +- src/lib/gcov-io.c | 2 +- src/lib/gcov-io.h | 38 +- src/lib/generic_sdram.c | 8 +- src/lib/hardwaremain.c | 42 +- src/lib/jpeg.c | 80 +- src/lib/libgcov.c | 74 +- src/lib/lzmadecode.c | 342 +- src/lib/memrange.c | 44 +- src/lib/ne2k.c | 16 +- src/lib/ns8390.h | 2 +- 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src/mainboard/amd/dinar/gpio.h | 2838 ++++++------ src/mainboard/amd/dinar/mptable.c | 4 +- src/mainboard/amd/dinar/rd890_cfg.c | 4 +- src/mainboard/amd/dinar/rd890_cfg.h | 36 +- src/mainboard/amd/dinar/sb700_cfg.c | 4 +- src/mainboard/amd/dinar/sb700_cfg.h | 64 +- src/mainboard/amd/inagua/BiosCallOuts.c | 68 +- src/mainboard/amd/inagua/BiosCallOuts.h | 18 +- src/mainboard/amd/inagua/Kconfig | 6 +- src/mainboard/amd/inagua/OptionsIds.h | 6 +- src/mainboard/amd/inagua/PlatformGnbPcie.c | 6 +- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 50 +- src/mainboard/amd/inagua/acpi/ide.asl | 8 +- src/mainboard/amd/inagua/agesawrapper.c | 4 +- src/mainboard/amd/inagua/agesawrapper.h | 26 +- src/mainboard/amd/inagua/broadcom.c | 22 +- src/mainboard/amd/inagua/buildOpts.c | 78 +- src/mainboard/amd/inagua/cmos.layout | 160 +- src/mainboard/amd/inagua/dsdt.asl | 2 +- src/mainboard/amd/inagua/get_bus_conf.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 6 +- src/mainboard/amd/inagua/platform_cfg.h | 8 +- src/mainboard/amd/mahogany/acpi/ide.asl | 8 +- src/mainboard/amd/mahogany/acpi_tables.c | 2 +- src/mainboard/amd/mahogany/cmos.layout | 160 +- src/mainboard/amd/mahogany/devicetree.cb | 2 +- src/mainboard/amd/mahogany/dsdt.asl | 84 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 2 +- src/mainboard/amd/mahogany/mptable.c | 8 +- src/mainboard/amd/mahogany_fam10/acpi/ide.asl | 8 +- src/mainboard/amd/mahogany_fam10/cmos.layout | 160 +- src/mainboard/amd/mahogany_fam10/devicetree.cb | 2 +- src/mainboard/amd/mahogany_fam10/dsdt.asl | 84 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 2 +- src/mainboard/amd/mahogany_fam10/mptable.c | 8 +- src/mainboard/amd/mahogany_fam10/resourcemap.c | 190 +- src/mainboard/amd/mahogany_fam10/romstage.c | 4 +- src/mainboard/amd/norwich/cmos.layout | 120 +- src/mainboard/amd/norwich/irq_tables.c | 6 +- src/mainboard/amd/olivehill/BiosCallOuts.c | 28 +- src/mainboard/amd/olivehill/OptionsIds.h | 8 +- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 6 +- src/mainboard/amd/olivehill/acpi/ide.asl | 74 +- src/mainboard/amd/olivehill/acpi_tables.c | 4 +- src/mainboard/amd/olivehill/agesawrapper.c | 154 +- src/mainboard/amd/olivehill/agesawrapper.h | 28 +- src/mainboard/amd/olivehill/buildOpts.c | 460 +- src/mainboard/amd/olivehill/cmos.layout | 160 +- src/mainboard/amd/olivehill/devicetree.cb | 2 +- src/mainboard/amd/olivehill/dsdt.asl | 2 +- src/mainboard/amd/olivehill/get_bus_conf.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 16 +- src/mainboard/amd/parmer/BiosCallOuts.c | 18 +- src/mainboard/amd/parmer/OptionsIds.h | 8 +- src/mainboard/amd/parmer/PlatformGnbPcie.c | 14 +- src/mainboard/amd/parmer/acpi/mainboard.asl | 2 +- src/mainboard/amd/parmer/acpi/routing.asl | 4 +- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 154 +- 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src/mainboard/asus/a8v-e_se/dsdt.asl | 20 +- src/mainboard/asus/a8v-e_se/mptable.c | 2 +- src/mainboard/asus/dsbf/cmos.layout | 154 +- src/mainboard/asus/dsbf/devicetree.cb | 28 +- src/mainboard/asus/dsbf/irq_tables.c | 4 +- src/mainboard/asus/dsbf/romstage.c | 28 +- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 18 +- src/mainboard/asus/f2a85-m/OptionsIds.h | 10 +- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 40 +- src/mainboard/asus/f2a85-m/acpi/mainboard.asl | 2 +- src/mainboard/asus/f2a85-m/acpi/routing.asl | 4 +- src/mainboard/asus/f2a85-m/acpi_tables.c | 2 +- src/mainboard/asus/f2a85-m/agesawrapper.c | 154 +- src/mainboard/asus/f2a85-m/agesawrapper.h | 28 +- src/mainboard/asus/f2a85-m/buildOpts.c | 470 +- src/mainboard/asus/f2a85-m/cmos.layout | 160 +- src/mainboard/asus/f2a85-m/devicetree.cb | 4 +- src/mainboard/asus/f2a85-m/dsdt.asl | 10 +- src/mainboard/asus/f2a85-m/get_bus_conf.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 16 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/cmos.layout | 160 +- src/mainboard/asus/k8v-x/devicetree.cb | 162 +- src/mainboard/asus/k8v-x/dsdt.asl | 20 +- src/mainboard/asus/k8v-x/mptable.c | 2 +- src/mainboard/asus/m2n-e/cmos.layout | 160 +- src/mainboard/asus/m2n-e/devicetree.cb | 164 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 32 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2n-e/resourcemap.c | 190 +- src/mainboard/asus/m2v-mx_se/acpi_tables.c | 10 +- src/mainboard/asus/m2v-mx_se/cmos.layout | 162 +- src/mainboard/asus/m2v-mx_se/devicetree.cb | 116 +- src/mainboard/asus/m2v-mx_se/dsdt.asl | 20 +- src/mainboard/asus/m2v/cmos.layout | 160 +- src/mainboard/asus/m2v/devicetree.cb | 116 +- src/mainboard/asus/m2v/dsdt.asl | 40 +- src/mainboard/asus/m2v/irq_tables.c | 16 +- src/mainboard/asus/m2v/mptable.c | 2 +- src/mainboard/asus/m2v/romstage.c | 12 +- src/mainboard/asus/m4a78-em/acpi/ide.asl | 8 +- src/mainboard/asus/m4a78-em/acpi_tables.c | 2 +- src/mainboard/asus/m4a78-em/cmos.layout | 160 +- src/mainboard/asus/m4a78-em/devicetree.cb | 2 +- src/mainboard/asus/m4a78-em/dsdt.asl | 84 +- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/irq_tables.c | 4 +- src/mainboard/asus/m4a78-em/mptable.c | 8 +- src/mainboard/asus/m4a78-em/resourcemap.c | 190 +- src/mainboard/asus/m4a78-em/romstage.c | 4 +- src/mainboard/asus/m4a785-m/acpi/ide.asl | 8 +- src/mainboard/asus/m4a785-m/acpi_tables.c | 2 +- src/mainboard/asus/m4a785-m/cmos.layout | 160 +- src/mainboard/asus/m4a785-m/devicetree.cb | 2 +- src/mainboard/asus/m4a785-m/dsdt.asl | 84 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/irq_tables.c | 4 +- src/mainboard/asus/m4a785-m/mainboard.c | 2 +- src/mainboard/asus/m4a785-m/mptable.c | 8 +- src/mainboard/asus/m4a785-m/resourcemap.c | 190 +- src/mainboard/asus/m4a785-m/romstage.c | 6 +- src/mainboard/asus/m4a785t-m/acpi/ide.asl | 8 +- src/mainboard/asus/m4a785t-m/cmos.layout | 160 +- src/mainboard/asus/m4a785t-m/devicetree.cb | 2 +- src/mainboard/asus/m4a785t-m/dsdt.asl | 84 +- src/mainboard/asus/m5a88-v/Kconfig | 4 +- src/mainboard/asus/m5a88-v/acpi/ide.asl | 8 +- src/mainboard/asus/m5a88-v/acpi_tables.c | 2 +- src/mainboard/asus/m5a88-v/cmos.layout | 160 +- src/mainboard/asus/m5a88-v/devicetree.cb | 80 +- src/mainboard/asus/m5a88-v/dsdt.asl | 128 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/mptable.c | 8 +- src/mainboard/asus/m5a88-v/platform_cfg.h | 8 +- src/mainboard/asus/m5a88-v/resourcemap.c | 190 +- src/mainboard/asus/m5a88-v/romstage.c | 4 +- src/mainboard/asus/mew-am/devicetree.cb | 72 +- src/mainboard/asus/mew-am/irq_tables.c | 2 +- src/mainboard/asus/mew-vm/cmos.layout | 118 +- src/mainboard/asus/mew-vm/irq_tables.c | 6 +- src/mainboard/asus/p2b-d/devicetree.cb | 66 +- src/mainboard/asus/p2b-d/irq_tables.c | 2 +- src/mainboard/asus/p2b-d/mptable.c | 6 +- src/mainboard/asus/p2b-ds/devicetree.cb | 66 +- src/mainboard/asus/p2b-ds/irq_tables.c | 2 +- src/mainboard/asus/p2b-ds/mptable.c | 8 +- src/mainboard/asus/p2b-f/devicetree.cb | 66 +- src/mainboard/asus/p2b-f/irq_tables.c | 2 +- src/mainboard/asus/p2b-ls/devicetree.cb | 66 +- src/mainboard/asus/p2b-ls/irq_tables.c | 4 +- src/mainboard/asus/p2b/devicetree.cb | 66 +- src/mainboard/asus/p2b/dsdt.asl | 6 +- src/mainboard/asus/p2b/irq_tables.c | 2 +- src/mainboard/asus/p3b-f/devicetree.cb | 66 +- src/mainboard/asus/p3b-f/irq_tables.c | 2 +- src/mainboard/avalue/eax-785e/Kconfig | 8 +- src/mainboard/avalue/eax-785e/acpi/ide.asl | 8 +- src/mainboard/avalue/eax-785e/acpi_tables.c | 2 +- src/mainboard/avalue/eax-785e/cmos.layout | 160 +- src/mainboard/avalue/eax-785e/devicetree.cb | 80 +- src/mainboard/avalue/eax-785e/dsdt.asl | 128 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +- src/mainboard/avalue/eax-785e/mainboard.c | 2 +- src/mainboard/avalue/eax-785e/mptable.c | 8 +- src/mainboard/avalue/eax-785e/platform_cfg.h | 8 +- src/mainboard/avalue/eax-785e/resourcemap.c | 190 +- src/mainboard/avalue/eax-785e/romstage.c | 4 +- src/mainboard/axus/tc320/devicetree.cb | 74 +- src/mainboard/axus/tc320/irq_tables.c | 16 +- src/mainboard/azza/pt-6ibd/devicetree.cb | 66 +- src/mainboard/azza/pt-6ibd/irq_tables.c | 2 +- src/mainboard/bachmann/ot200/cmos.layout | 42 +- src/mainboard/bachmann/ot200/devicetree.cb | 4 +- src/mainboard/bachmann/ot200/irq_tables.c | 6 +- src/mainboard/bcom/winnet100/devicetree.cb | 74 +- src/mainboard/bcom/winnet100/irq_tables.c | 18 +- src/mainboard/bcom/winnetp680/cmos.layout | 118 +- src/mainboard/bcom/winnetp680/devicetree.cb | 56 +- src/mainboard/bcom/winnetp680/irq_tables.c | 2 +- src/mainboard/biostar/m6tba/devicetree.cb | 54 +- src/mainboard/biostar/m6tba/irq_tables.c | 2 +- src/mainboard/broadcom/blast/cmos.layout | 160 +- src/mainboard/broadcom/blast/devicetree.cb | 214 +- src/mainboard/broadcom/blast/get_bus_conf.c | 36 +- src/mainboard/broadcom/blast/irq_tables.c | 32 +- src/mainboard/broadcom/blast/mptable.c | 98 +- src/mainboard/broadcom/blast/resourcemap.c | 190 +- src/mainboard/broadcom/blast/romstage.c | 68 +- .../compaq/deskpro_en_sff_p600/devicetree.cb | 72 +- .../compaq/deskpro_en_sff_p600/irq_tables.c | 2 +- src/mainboard/digitallogic/adl855pc/cmos.layout | 118 +- src/mainboard/digitallogic/adl855pc/devicetree.cb | 48 +- src/mainboard/digitallogic/adl855pc/irq_tables.c | 20 +- src/mainboard/digitallogic/adl855pc/romstage.c | 6 +- src/mainboard/digitallogic/msm586seg/cmos.layout | 118 +- src/mainboard/digitallogic/msm586seg/irq_tables.c | 10 +- src/mainboard/digitallogic/msm586seg/mainboard.c | 2 +- src/mainboard/digitallogic/msm586seg/romstage.c | 48 +- src/mainboard/digitallogic/msm800sev/cmos.layout | 118 +- src/mainboard/digitallogic/msm800sev/devicetree.cb | 6 +- src/mainboard/digitallogic/msm800sev/irq_tables.c | 6 +- src/mainboard/digitallogic/msm800sev/mainboard.c | 4 +- src/mainboard/dmp/vortex86ex/Kconfig | 2 +- src/mainboard/dmp/vortex86ex/hda_verb.h | 6 +- src/mainboard/dmp/vortex86ex/irq_tables.c | 2 +- src/mainboard/dmp/vortex86ex/romstage.c | 10 +- src/mainboard/eaglelion/5bcm/cmos.layout | 118 +- src/mainboard/eaglelion/5bcm/devicetree.cb | 78 +- src/mainboard/eaglelion/5bcm/irq_tables.c | 10 +- src/mainboard/ecs/p6iwp-fe/devicetree.cb | 88 +- src/mainboard/ecs/p6iwp-fe/irq_tables.c | 4 +- src/mainboard/emulation/qemu-armv7/media.c | 2 +- src/mainboard/emulation/qemu-armv7/romstage.c | 2 +- src/mainboard/emulation/qemu-armv7/uart.c | 2 +- .../emulation/qemu-i440fx/acpi/cpu-hotplug.asl | 106 +- src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl | 20 +- src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl | 54 +- src/mainboard/emulation/qemu-i440fx/acpi/isa.asl | 156 +- .../emulation/qemu-i440fx/acpi/pci-crs.asl | 152 +- src/mainboard/emulation/qemu-i440fx/cmos.layout | 118 +- src/mainboard/emulation/qemu-i440fx/dsdt.asl | 480 +- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 22 +- 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| 160 +- src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 124 +- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 32 +- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 100 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 56 +- src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 190 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 140 +- src/mainboard/gigabyte/m57sli/cmos.layout | 160 +- src/mainboard/gigabyte/m57sli/devicetree.cb | 268 +- src/mainboard/gigabyte/m57sli/dsdt.asl | 20 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 32 +- src/mainboard/gigabyte/m57sli/irq_tables.c | 50 +- src/mainboard/gigabyte/m57sli/mptable.c | 56 +- src/mainboard/gigabyte/m57sli/resourcemap.c | 190 +- src/mainboard/gigabyte/m57sli/romstage.c | 132 +- src/mainboard/gigabyte/ma785gm/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma785gm/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma785gm/cmos.layout | 160 +- src/mainboard/gigabyte/ma785gm/devicetree.cb | 2 +- src/mainboard/gigabyte/ma785gm/dsdt.asl | 84 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 2 +- src/mainboard/gigabyte/ma785gm/mptable.c | 8 +- src/mainboard/gigabyte/ma785gm/resourcemap.c | 190 +- src/mainboard/gigabyte/ma785gm/romstage.c | 4 +- src/mainboard/gigabyte/ma785gmt/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma785gmt/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma785gmt/cmos.layout | 160 +- src/mainboard/gigabyte/ma785gmt/devicetree.cb | 2 +- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 84 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 6 +- src/mainboard/gigabyte/ma785gmt/mptable.c | 8 +- src/mainboard/gigabyte/ma785gmt/resourcemap.c | 190 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 4 +- src/mainboard/gigabyte/ma78gm/acpi/ide.asl | 8 +- src/mainboard/gigabyte/ma78gm/acpi_tables.c | 2 +- src/mainboard/gigabyte/ma78gm/cmos.layout | 160 +- src/mainboard/gigabyte/ma78gm/devicetree.cb | 2 +- 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| 150 +- src/mainboard/google/parrot/ec.h | 4 +- src/mainboard/google/parrot/gpio.h | 6 +- src/mainboard/google/parrot/mainboard.c | 6 +- src/mainboard/google/parrot/onboard.h | 6 +- src/mainboard/google/parrot/romstage.c | 10 +- src/mainboard/google/parrot/smihandler.c | 2 +- .../google/peppy/acpi/haswell_pci_irqs.asl | 8 +- src/mainboard/google/peppy/acpi/superio.asl | 8 +- src/mainboard/google/peppy/acpi_tables.c | 2 +- src/mainboard/google/peppy/cmos.layout | 150 +- src/mainboard/google/peppy/ec.c | 4 +- src/mainboard/google/peppy/ec.h | 14 +- src/mainboard/google/peppy/gpio.h | 190 +- src/mainboard/google/peppy/mainboard.c | 8 +- src/mainboard/google/peppy/romstage.c | 32 +- src/mainboard/google/pit/mainboard.c | 2 +- src/mainboard/google/pit/romstage.c | 20 +- .../google/slippy/acpi/haswell_pci_irqs.asl | 8 +- src/mainboard/google/slippy/acpi/superio.asl | 8 +- src/mainboard/google/slippy/acpi_tables.c | 2 +- src/mainboard/google/slippy/cmos.layout | 150 +- src/mainboard/google/slippy/ec.c | 4 +- src/mainboard/google/slippy/ec.h | 14 +- src/mainboard/google/slippy/gpio.h | 186 +- src/mainboard/google/slippy/mainboard.c | 8 +- src/mainboard/google/slippy/romstage.c | 32 +- src/mainboard/google/snow/memory.c | 2 +- src/mainboard/google/snow/romstage.c | 8 +- src/mainboard/google/stout/acpi/superio.asl | 4 +- src/mainboard/google/stout/acpi_tables.c | 2 +- src/mainboard/google/stout/chromeos.c | 6 +- src/mainboard/google/stout/cmos.layout | 150 +- src/mainboard/google/stout/devicetree.cb | 8 +- src/mainboard/google/stout/dsdt.asl | 2 +- src/mainboard/google/stout/ec.c | 2 +- src/mainboard/google/stout/ec.h | 4 +- src/mainboard/google/stout/fadt.c | 10 +- src/mainboard/google/stout/gpio.h | 18 +- src/mainboard/google/stout/i915.c | 8 +- src/mainboard/google/stout/i915_reg.h | 2820 ++++++------ src/mainboard/google/stout/mainboard.c | 6 +- src/mainboard/google/stout/mainboard_smi.c | 2 +- src/mainboard/google/stout/romstage.c | 20 +- src/mainboard/google/stout/thermal.h | 6 +- src/mainboard/hp/dl145_g1/cmos.layout | 160 +- src/mainboard/hp/dl145_g1/devicetree.cb | 6 +- src/mainboard/hp/dl145_g1/resourcemap.c | 4 +- src/mainboard/hp/dl145_g3/cmos.layout | 160 +- src/mainboard/hp/dl145_g3/devicetree.cb | 6 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/irq_tables.c | 72 +- src/mainboard/hp/dl145_g3/mptable.c | 4 +- src/mainboard/hp/dl165_g6_fam10/Kconfig | 2 +- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 4 +- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 160 +- src/mainboard/hp/dl165_g6_fam10/devicetree.cb | 6 +- src/mainboard/hp/dl165_g6_fam10/irq_tables.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 8 +- src/mainboard/hp/e_vectra_p2706t/devicetree.cb | 66 +- src/mainboard/hp/e_vectra_p2706t/irq_tables.c | 2 +- src/mainboard/ibase/mb899/cmos.layout | 232 +- src/mainboard/ibase/mb899/devicetree.cb | 76 +- src/mainboard/ibase/mb899/irq_tables.c | 6 +- src/mainboard/ibase/mb899/mptable.c | 10 +- src/mainboard/ibm/e325/cmos.layout | 160 +- src/mainboard/ibm/e325/devicetree.cb | 2 +- src/mainboard/ibm/e325/irq_tables.c | 4 +- src/mainboard/ibm/e325/mptable.c | 36 +- src/mainboard/ibm/e325/resourcemap.c | 12 +- src/mainboard/ibm/e325/romstage.c | 20 +- src/mainboard/ibm/e326/cmos.layout | 160 +- src/mainboard/ibm/e326/devicetree.cb | 4 +- src/mainboard/ibm/e326/irq_tables.c | 4 +- src/mainboard/ibm/e326/mptable.c | 36 +- src/mainboard/ibm/e326/resourcemap.c | 12 +- src/mainboard/ibm/e326/romstage.c | 20 +- src/mainboard/iei/juki-511p/cmos.layout | 118 +- src/mainboard/iei/juki-511p/devicetree.cb | 76 +- src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl | 8 +- src/mainboard/iei/kino-780am2-fam10/cmos.layout | 160 +- src/mainboard/iei/kino-780am2-fam10/devicetree.cb | 2 +- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 84 +- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 8 +- src/mainboard/iei/kino-780am2-fam10/resourcemap.c | 190 +- src/mainboard/iei/kino-780am2-fam10/romstage.c | 4 +- src/mainboard/iei/nova4899r/cmos.layout | 118 +- src/mainboard/iei/nova4899r/devicetree.cb | 100 +- src/mainboard/iei/nova4899r/irq_tables.c | 12 +- src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c | 2 +- src/mainboard/iei/pm-lx-800-r11/devicetree.cb | 6 +- src/mainboard/intel/baskingridge/acpi/superio.asl | 20 +- src/mainboard/intel/baskingridge/acpi_tables.c | 2 +- src/mainboard/intel/baskingridge/cmos.layout | 146 +- src/mainboard/intel/baskingridge/dsdt.asl | 2 +- src/mainboard/intel/baskingridge/gpio.h | 6 +- src/mainboard/intel/baskingridge/mainboard.c | 8 +- src/mainboard/intel/baskingridge/onboard.h | 16 +- src/mainboard/intel/baskingridge/romstage.c | 14 +- src/mainboard/intel/d810e2cb/devicetree.cb | 84 +- src/mainboard/intel/d810e2cb/gpio.c | 2 +- src/mainboard/intel/d810e2cb/irq_tables.c | 4 +- src/mainboard/intel/d945gclf/cmos.layout | 156 +- src/mainboard/intel/d945gclf/devicetree.cb | 78 +- src/mainboard/intel/d945gclf/irq_tables.c | 6 +- src/mainboard/intel/d945gclf/mptable.c | 8 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/eagleheights/cmos.layout | 140 +- src/mainboard/intel/eagleheights/debug.c | 182 +- src/mainboard/intel/eagleheights/devicetree.cb | 78 +- src/mainboard/intel/eagleheights/dsdt.asl | 68 +- src/mainboard/intel/eagleheights/fadt.c | 32 +- src/mainboard/intel/eagleheights/irq_tables.c | 4 +- src/mainboard/intel/eagleheights/mptable.c | 8 +- src/mainboard/intel/eagleheights/romstage.c | 8 +- src/mainboard/intel/emeraldlake2/acpi/superio.asl | 20 +- src/mainboard/intel/emeraldlake2/acpi_tables.c | 2 +- src/mainboard/intel/emeraldlake2/cmos.layout | 150 +- src/mainboard/intel/emeraldlake2/ec.h | 36 +- src/mainboard/intel/emeraldlake2/gpio.h | 62 +- src/mainboard/intel/emeraldlake2/mainboard.c | 4 +- src/mainboard/intel/emeraldlake2/onboard.h | 16 +- src/mainboard/intel/emeraldlake2/romstage.c | 20 +- src/mainboard/intel/jarrell/cmos.layout | 128 +- src/mainboard/intel/jarrell/debug.c | 186 +- src/mainboard/intel/jarrell/irq_tables.c | 8 +- src/mainboard/intel/jarrell/jarrell_fixups.c | 36 +- src/mainboard/intel/jarrell/mptable.c | 12 +- src/mainboard/intel/jarrell/romstage.c | 18 +- src/mainboard/intel/mtarvon/devicetree.cb | 84 +- src/mainboard/intel/mtarvon/irq_tables.c | 6 +- src/mainboard/intel/truxton/devicetree.cb | 86 +- src/mainboard/intel/truxton/irq_tables.c | 6 +- src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl | 4 +- src/mainboard/intel/wtm2/acpi_tables.c | 2 +- src/mainboard/intel/wtm2/cmos.layout | 150 +- src/mainboard/intel/wtm2/gpio.h | 190 +- src/mainboard/intel/wtm2/i915.c | 8 +- src/mainboard/intel/wtm2/intel_dp.c | 4 +- src/mainboard/intel/wtm2/mainboard.c | 8 +- src/mainboard/intel/wtm2/romstage.c | 8 +- src/mainboard/intel/xe7501devkit/acpi_tables.c | 2 +- src/mainboard/intel/xe7501devkit/cmos.layout | 60 +- src/mainboard/intel/xe7501devkit/irq_tables.c | 10 +- src/mainboard/intel/xe7501devkit/mptable.c | 50 +- src/mainboard/intel/xe7501devkit/romstage.c | 2 +- src/mainboard/iwave/iWRainbowG6/acpi_tables.c | 10 +- src/mainboard/iwave/iWRainbowG6/cmos.layout | 164 +- src/mainboard/iwave/iWRainbowG6/fadt.c | 2 +- src/mainboard/iwave/iWRainbowG6/irq_tables.c | 26 +- src/mainboard/iwave/iWRainbowG6/romstage.c | 14 +- src/mainboard/iwill/dk8_htx/acpi/amd8111.asl | 276 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl | 332 +- src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl | 706 +-- src/mainboard/iwill/dk8_htx/acpi/amd8131.asl | 192 +- src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl | 206 +- src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl | 206 +- src/mainboard/iwill/dk8_htx/acpi/amd8151.asl | 52 +- src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl | 26 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 248 +- src/mainboard/iwill/dk8_htx/cmos.layout | 160 +- src/mainboard/iwill/dk8_htx/devicetree.cb | 78 +- src/mainboard/iwill/dk8_htx/dsdt.asl | 230 +- src/mainboard/iwill/dk8_htx/fadt.c | 6 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 50 +- src/mainboard/iwill/dk8_htx/irq_tables.c | 96 +- src/mainboard/iwill/dk8_htx/mb_sysconf.h | 18 +- src/mainboard/iwill/dk8_htx/mptable.c | 190 +- src/mainboard/iwill/dk8_htx/resourcemap.c | 190 +- src/mainboard/iwill/dk8_htx/romstage.c | 64 +- src/mainboard/iwill/dk8_htx/ssdt2.asl | 40 +- src/mainboard/iwill/dk8_htx/ssdt3.asl | 40 +- src/mainboard/iwill/dk8_htx/ssdt4.asl | 40 +- src/mainboard/iwill/dk8_htx/ssdt5.asl | 40 +- src/mainboard/iwill/dk8s2/cmos.layout | 160 +- src/mainboard/iwill/dk8s2/devicetree.cb | 14 +- src/mainboard/iwill/dk8s2/irq_tables.c | 10 +- src/mainboard/iwill/dk8s2/romstage.c | 72 +- src/mainboard/iwill/dk8x/cmos.layout | 160 +- src/mainboard/iwill/dk8x/irq_tables.c | 4 +- src/mainboard/iwill/dk8x/romstage.c | 64 +- src/mainboard/jetway/j7f24/cmos.layout | 118 +- src/mainboard/jetway/j7f24/devicetree.cb | 46 +- src/mainboard/jetway/j7f24/irq_tables.c | 2 +- src/mainboard/jetway/pa78vm5/acpi/ide.asl | 8 +- src/mainboard/jetway/pa78vm5/acpi_tables.c | 2 +- src/mainboard/jetway/pa78vm5/cmos.layout | 160 +- src/mainboard/jetway/pa78vm5/devicetree.cb | 2 +- src/mainboard/jetway/pa78vm5/dsdt.asl | 84 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 2 +- src/mainboard/jetway/pa78vm5/mptable.c | 8 +- src/mainboard/jetway/pa78vm5/resourcemap.c | 190 +- src/mainboard/jetway/pa78vm5/romstage.c | 4 +- src/mainboard/kontron/986lcd-m/cmos.layout | 242 +- src/mainboard/kontron/986lcd-m/devicetree.cb | 98 +- src/mainboard/kontron/986lcd-m/irq_tables.c | 6 +- src/mainboard/kontron/986lcd-m/mptable.c | 8 +- src/mainboard/kontron/kt690/acpi/ide.asl | 8 +- src/mainboard/kontron/kt690/acpi_tables.c | 2 +- src/mainboard/kontron/kt690/cmos.layout | 160 +- src/mainboard/kontron/kt690/devicetree.cb | 4 +- src/mainboard/kontron/kt690/dsdt.asl | 80 +- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 +- src/mainboard/kontron/kt690/mptable.c | 6 +- .../kontron/ktqm77/acpi/sandybridge_pci_irqs.asl | 20 +- src/mainboard/kontron/ktqm77/acpi_tables.c | 2 +- src/mainboard/kontron/ktqm77/cmos.layout | 206 +- src/mainboard/kontron/ktqm77/gpio.h | 4 +- src/mainboard/kontron/ktqm77/hda_verb.h | 26 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +- src/mainboard/kontron/ktqm77/romstage.c | 60 +- src/mainboard/lanner/em8510/cmos.layout | 118 +- src/mainboard/lanner/em8510/devicetree.cb | 48 +- src/mainboard/lanner/em8510/irq_tables.c | 4 +- src/mainboard/lanner/em8510/romstage.c | 6 +- src/mainboard/lenovo/Kconfig | 2 +- src/mainboard/lenovo/t60/acpi/dock.asl | 2 +- src/mainboard/lenovo/t60/acpi/platform.asl | 14 +- src/mainboard/lenovo/t60/acpi/video.asl | 2 +- src/mainboard/lenovo/t60/cmos.layout | 176 +- src/mainboard/lenovo/t60/irq_tables.c | 20 +- src/mainboard/lenovo/t60/mptable.c | 34 +- src/mainboard/lenovo/x60/acpi/dock.asl | 6 +- src/mainboard/lenovo/x60/acpi/platform.asl | 14 +- src/mainboard/lenovo/x60/acpi/video.asl | 2 +- src/mainboard/lenovo/x60/cmos.layout | 176 +- src/mainboard/lenovo/x60/drm_dp_helper.h | 184 +- src/mainboard/lenovo/x60/i915.c | 8 +- src/mainboard/lenovo/x60/i915_reg.h | 2714 +++++------ src/mainboard/lenovo/x60/intel_dp.c | 6 +- src/mainboard/lenovo/x60/irq_tables.c | 20 +- src/mainboard/lenovo/x60/mainboard.c | 2 +- src/mainboard/lenovo/x60/mptable.c | 36 +- src/mainboard/lenovo/x60/romstage.c | 4 +- .../lippert/frontrunner-af/BiosCallOuts.c | 28 +- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 6 +- src/mainboard/lippert/frontrunner-af/acpi/ide.asl | 8 +- .../lippert/frontrunner-af/agesawrapper.c | 40 +- src/mainboard/lippert/frontrunner-af/cmos.layout | 160 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 126 +- .../lippert/frontrunner-af/get_bus_conf.c | 2 +- src/mainboard/lippert/frontrunner-af/mainboard.c | 38 +- .../lippert/frontrunner-af/platform_cfg.h | 24 +- src/mainboard/lippert/frontrunner/cmos.layout | 118 +- src/mainboard/lippert/frontrunner/devicetree.cb | 10 +- src/mainboard/lippert/frontrunner/irq_tables.c | 10 +- src/mainboard/lippert/frontrunner/romstage.c | 12 +- src/mainboard/lippert/hurricane-lx/devicetree.cb | 114 +- src/mainboard/lippert/hurricane-lx/irq_tables.c | 10 +- src/mainboard/lippert/hurricane-lx/mainboard.c | 14 +- src/mainboard/lippert/literunner-lx/devicetree.cb | 114 +- src/mainboard/lippert/literunner-lx/irq_tables.c | 12 +- src/mainboard/lippert/literunner-lx/mainboard.c | 16 +- src/mainboard/lippert/roadrunner-lx/devicetree.cb | 114 +- src/mainboard/lippert/roadrunner-lx/irq_tables.c | 8 +- src/mainboard/lippert/roadrunner-lx/mainboard.c | 10 +- src/mainboard/lippert/spacerunner-lx/devicetree.cb | 116 +- src/mainboard/lippert/spacerunner-lx/irq_tables.c | 8 +- src/mainboard/lippert/spacerunner-lx/mainboard.c | 16 +- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 28 +- src/mainboard/lippert/toucan-af/OptionsIds.h | 6 +- src/mainboard/lippert/toucan-af/acpi/ide.asl | 8 +- src/mainboard/lippert/toucan-af/agesawrapper.c | 40 +- src/mainboard/lippert/toucan-af/cmos.layout | 160 +- src/mainboard/lippert/toucan-af/dsdt.asl | 126 +- src/mainboard/lippert/toucan-af/get_bus_conf.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 14 +- src/mainboard/lippert/toucan-af/platform_cfg.h | 24 +- src/mainboard/mitac/6513wu/devicetree.cb | 96 +- src/mainboard/mitac/6513wu/irq_tables.c | 26 +- src/mainboard/msi/ms6119/devicetree.cb | 68 +- src/mainboard/msi/ms6119/irq_tables.c | 2 +- src/mainboard/msi/ms6147/devicetree.cb | 68 +- src/mainboard/msi/ms6147/irq_tables.c | 2 +- src/mainboard/msi/ms6156/devicetree.cb | 68 +- src/mainboard/msi/ms6156/irq_tables.c | 2 +- src/mainboard/msi/ms6178/devicetree.cb | 78 +- src/mainboard/msi/ms6178/irq_tables.c | 2 +- src/mainboard/msi/ms7135/cmos.layout | 180 +- src/mainboard/msi/ms7135/devicetree.cb | 114 +- src/mainboard/msi/ms7260/cmos.layout | 160 +- src/mainboard/msi/ms7260/devicetree.cb | 248 +- src/mainboard/msi/ms7260/get_bus_conf.c | 30 +- src/mainboard/msi/ms7260/mptable.c | 20 +- src/mainboard/msi/ms7260/resourcemap.c | 190 +- src/mainboard/msi/ms7260/romstage.c | 12 +- src/mainboard/msi/ms9185/cmos.layout | 160 +- src/mainboard/msi/ms9185/devicetree.cb | 182 +- src/mainboard/msi/ms9185/get_bus_conf.c | 34 +- src/mainboard/msi/ms9185/irq_tables.c | 32 +- src/mainboard/msi/ms9185/mptable.c | 108 +- src/mainboard/msi/ms9185/resourcemap.c | 490 +- src/mainboard/msi/ms9185/romstage.c | 116 +- src/mainboard/msi/ms9282/cmos.layout | 160 +- src/mainboard/msi/ms9282/devicetree.cb | 326 +- src/mainboard/msi/ms9282/get_bus_conf.c | 30 +- src/mainboard/msi/ms9282/irq_tables.c | 66 +- src/mainboard/msi/ms9282/mb_sysconf.h | 4 +- src/mainboard/msi/ms9282/mptable.c | 74 +- src/mainboard/msi/ms9282/resourcemap.c | 490 +- src/mainboard/msi/ms9282/romstage.c | 78 +- src/mainboard/msi/ms9652_fam10/cmos.layout | 160 +- src/mainboard/msi/ms9652_fam10/devicetree.cb | 252 +- src/mainboard/msi/ms9652_fam10/dsdt.asl | 20 +- src/mainboard/msi/ms9652_fam10/resourcemap.c | 190 +- src/mainboard/msi/ms9652_fam10/romstage.c | 4 +- src/mainboard/nec/powermate2000/devicetree.cb | 58 +- src/mainboard/nec/powermate2000/irq_tables.c | 2 +- src/mainboard/newisys/khepri/cmos.layout | 160 +- src/mainboard/newisys/khepri/devicetree.cb | 48 +- src/mainboard/newisys/khepri/irq_tables.c | 20 +- src/mainboard/newisys/khepri/resourcemap.c | 4 +- src/mainboard/newisys/khepri/romstage.c | 44 +- src/mainboard/nokia/ip530/devicetree.cb | 114 +- src/mainboard/nokia/ip530/irq_tables.c | 2 +- src/mainboard/nvidia/l1_2pvv/cmos.layout | 160 +- src/mainboard/nvidia/l1_2pvv/devicetree.cb | 320 +- src/mainboard/nvidia/l1_2pvv/resourcemap.c | 190 +- src/mainboard/pcengines/alix1c/cmos.layout | 118 +- src/mainboard/pcengines/alix1c/devicetree.cb | 6 +- src/mainboard/pcengines/alix1c/irq_tables.c | 20 +- src/mainboard/pcengines/alix2d/cmos.layout | 118 +- src/mainboard/pcengines/alix2d/devicetree.cb | 4 +- src/mainboard/pcengines/alix2d/irq_tables.c | 22 +- src/mainboard/pcengines/alix2d/romstage.c | 18 +- src/mainboard/rca/rm4100/devicetree.cb | 62 +- src/mainboard/rca/rm4100/gpio.c | 2 +- src/mainboard/rca/rm4100/irq_tables.c | 8 +- src/mainboard/rca/rm4100/spd_table.h | 10 +- src/mainboard/roda/rk886ex/acpi/platform.asl | 14 +- src/mainboard/roda/rk886ex/cmos.layout | 166 +- src/mainboard/roda/rk886ex/devicetree.cb | 72 +- src/mainboard/roda/rk886ex/irq_tables.c | 6 +- src/mainboard/roda/rk886ex/m3885.c | 4 +- src/mainboard/roda/rk886ex/mptable.c | 8 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/roda/rk9/acpi/ec.asl | 32 +- src/mainboard/roda/rk9/acpi/platform.asl | 14 +- src/mainboard/roda/rk9/cmos.layout | 152 +- src/mainboard/roda/rk9/fadt.c | 2 +- src/mainboard/roda/rk9/hda_verb.h | 2 +- src/mainboard/roda/rk9/romstage.c | 8 +- src/mainboard/samsung/lumpy/acpi/superio.asl | 18 +- src/mainboard/samsung/lumpy/acpi_tables.c | 2 +- src/mainboard/samsung/lumpy/cmos.layout | 150 +- src/mainboard/samsung/lumpy/devicetree.cb | 10 +- src/mainboard/samsung/lumpy/dsdt.asl | 2 +- src/mainboard/samsung/lumpy/ec.h | 46 +- src/mainboard/samsung/lumpy/gpio.h | 6 +- src/mainboard/samsung/lumpy/mainboard.c | 18 +- src/mainboard/samsung/lumpy/onboard.h | 10 +- src/mainboard/samsung/lumpy/romstage.c | 26 +- src/mainboard/samsung/stumpy/acpi/superio.asl | 20 +- src/mainboard/samsung/stumpy/acpi_tables.c | 2 +- src/mainboard/samsung/stumpy/cmos.layout | 150 +- src/mainboard/samsung/stumpy/gpio.h | 6 +- src/mainboard/samsung/stumpy/mainboard.c | 4 +- src/mainboard/samsung/stumpy/romstage.c | 22 +- src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl | 8 +- src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl | 44 +- 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src/mainboard/supermicro/h8dme/devicetree.cb | 214 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 34 +- src/mainboard/supermicro/h8dme/irq_tables.c | 50 +- src/mainboard/supermicro/h8dme/mptable.c | 56 +- src/mainboard/supermicro/h8dme/resourcemap.c | 190 +- src/mainboard/supermicro/h8dme/romstage.c | 12 +- src/mainboard/supermicro/h8dmr/cmos.layout | 160 +- src/mainboard/supermicro/h8dmr/devicetree.cb | 254 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 34 +- src/mainboard/supermicro/h8dmr/irq_tables.c | 50 +- src/mainboard/supermicro/h8dmr/mptable.c | 58 +- src/mainboard/supermicro/h8dmr/resourcemap.c | 190 +- src/mainboard/supermicro/h8dmr/romstage.c | 122 +- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 160 +- src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 254 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/resourcemap.c | 190 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 58 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 16 +- src/mainboard/supermicro/h8qgi/OptionsIds.h | 8 +- src/mainboard/supermicro/h8qgi/acpi/ide.asl | 8 +- src/mainboard/supermicro/h8qgi/agesawrapper.c | 36 +- src/mainboard/supermicro/h8qgi/agesawrapper.h | 22 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 256 +- src/mainboard/supermicro/h8qgi/cmos.layout | 160 +- src/mainboard/supermicro/h8qgi/devicetree.cb | 2 +- src/mainboard/supermicro/h8qgi/dsdt.asl | 142 +- src/mainboard/supermicro/h8qgi/fadt.c | 2 +- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 4 +- src/mainboard/supermicro/h8qgi/rd890_cfg.h | 36 +- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 4 +- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 64 +- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 160 +- 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src/mainboard/supermicro/x6dhe_g/romstage.c | 12 +- src/mainboard/supermicro/x6dhe_g2/cmos.layout | 124 +- src/mainboard/supermicro/x6dhe_g2/debug.c | 186 +- src/mainboard/supermicro/x6dhe_g2/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhe_g2/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig/cmos.layout | 124 +- src/mainboard/supermicro/x6dhr_ig/debug.c | 186 +- src/mainboard/supermicro/x6dhr_ig/devicetree.cb | 6 +- src/mainboard/supermicro/x6dhr_ig/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 12 +- src/mainboard/supermicro/x6dhr_ig2/cmos.layout | 124 +- src/mainboard/supermicro/x6dhr_ig2/debug.c | 186 +- src/mainboard/supermicro/x6dhr_ig2/devicetree.cb | 6 +- src/mainboard/supermicro/x6dhr_ig2/irq_tables.c | 8 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 12 +- src/mainboard/supermicro/x7db8/cmos.layout | 154 +- src/mainboard/supermicro/x7db8/devicetree.cb | 24 +- src/mainboard/supermicro/x7db8/irq_tables.c | 4 +- src/mainboard/supermicro/x7db8/romstage.c | 2 +- src/mainboard/technexion/tim5690/acpi/ide.asl | 8 +- src/mainboard/technexion/tim5690/acpi_tables.c | 2 +- src/mainboard/technexion/tim5690/cmos.layout | 160 +- src/mainboard/technexion/tim5690/devicetree.cb | 2 +- src/mainboard/technexion/tim5690/dsdt.asl | 80 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 64 +- src/mainboard/technexion/tim5690/mptable.c | 6 +- src/mainboard/technexion/tim5690/tn_post_code.h | 6 +- src/mainboard/technexion/tim5690/vgabios.c | 48 +- src/mainboard/technexion/tim5690/vgabios.h | 6 +- src/mainboard/technexion/tim8690/acpi/ide.asl | 8 +- src/mainboard/technexion/tim8690/acpi_tables.c | 2 +- src/mainboard/technexion/tim8690/cmos.layout | 160 +- src/mainboard/technexion/tim8690/devicetree.cb | 2 +- src/mainboard/technexion/tim8690/dsdt.asl | 80 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 4 +- src/mainboard/technexion/tim8690/mptable.c | 6 +- src/mainboard/technologic/ts5300/cmos.layout | 118 +- src/mainboard/technologic/ts5300/irq_tables.c | 10 +- src/mainboard/technologic/ts5300/mainboard.c | 2 +- src/mainboard/technologic/ts5300/romstage.c | 10 +- src/mainboard/televideo/tc7020/devicetree.cb | 74 +- src/mainboard/thomson/ip1000/devicetree.cb | 62 +- src/mainboard/thomson/ip1000/gpio.c | 2 +- src/mainboard/thomson/ip1000/irq_tables.c | 8 +- src/mainboard/thomson/ip1000/mainboard.c | 4 +- src/mainboard/thomson/ip1000/spd_table.h | 10 +- src/mainboard/ti/beaglebone/Kconfig | 4 +- src/mainboard/traverse/geos/Kconfig | 4 +- src/mainboard/traverse/geos/cmos.layout | 120 +- src/mainboard/traverse/geos/irq_tables.c | 6 +- src/mainboard/tyan/Kconfig | 2 +- src/mainboard/tyan/s1846/devicetree.cb | 58 +- src/mainboard/tyan/s2735/cmos.layout | 132 +- src/mainboard/tyan/s2735/devicetree.cb | 150 +- src/mainboard/tyan/s2735/irq_tables.c | 10 +- src/mainboard/tyan/s2735/mptable.c | 56 +- src/mainboard/tyan/s2735/romstage.c | 20 +- src/mainboard/tyan/s2850/cmos.layout | 160 +- src/mainboard/tyan/s2850/devicetree.cb | 108 +- src/mainboard/tyan/s2850/irq_tables.c | 20 +- src/mainboard/tyan/s2850/mptable.c | 176 +- src/mainboard/tyan/s2850/romstage.c | 28 +- src/mainboard/tyan/s2875/cmos.layout | 160 +- src/mainboard/tyan/s2875/devicetree.cb | 16 +- src/mainboard/tyan/s2875/irq_tables.c | 20 +- src/mainboard/tyan/s2875/mptable.c | 184 +- src/mainboard/tyan/s2875/romstage.c | 28 +- src/mainboard/tyan/s2880/cmos.layout | 160 +- src/mainboard/tyan/s2880/devicetree.cb | 96 +- src/mainboard/tyan/s2880/irq_tables.c | 18 +- src/mainboard/tyan/s2880/mptable.c | 242 +- src/mainboard/tyan/s2880/romstage.c | 30 +- src/mainboard/tyan/s2881/cmos.layout | 160 +- src/mainboard/tyan/s2881/devicetree.cb | 220 +- src/mainboard/tyan/s2881/get_bus_conf.c | 40 +- src/mainboard/tyan/s2881/irq_tables.c | 54 +- src/mainboard/tyan/s2881/mptable.c | 74 +- src/mainboard/tyan/s2881/resourcemap.c | 4 +- src/mainboard/tyan/s2881/romstage.c | 52 +- src/mainboard/tyan/s2882/cmos.layout | 160 +- src/mainboard/tyan/s2882/devicetree.cb | 96 +- src/mainboard/tyan/s2882/irq_tables.c | 394 +- src/mainboard/tyan/s2882/mptable.c | 256 +- src/mainboard/tyan/s2882/romstage.c | 30 +- src/mainboard/tyan/s2885/cmos.layout | 160 +- src/mainboard/tyan/s2885/devicetree.cb | 124 +- src/mainboard/tyan/s2885/get_bus_conf.c | 38 +- src/mainboard/tyan/s2885/irq_tables.c | 56 +- src/mainboard/tyan/s2885/mptable.c | 62 +- src/mainboard/tyan/s2885/resourcemap.c | 190 +- src/mainboard/tyan/s2885/romstage.c | 54 +- src/mainboard/tyan/s2891/acpi_tables.c | 6 +- src/mainboard/tyan/s2891/cmos.layout | 160 +- src/mainboard/tyan/s2891/devicetree.cb | 234 +- src/mainboard/tyan/s2891/get_bus_conf.c | 40 +- src/mainboard/tyan/s2891/resourcemap.c | 190 +- src/mainboard/tyan/s2892/acpi_tables.c | 6 +- src/mainboard/tyan/s2892/cmos.layout | 160 +- src/mainboard/tyan/s2892/devicetree.cb | 240 +- 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src/mainboard/tyan/s4880/resourcemap.c | 4 +- src/mainboard/tyan/s4880/romstage.c | 124 +- src/mainboard/tyan/s4882/cmos.layout | 160 +- src/mainboard/tyan/s4882/devicetree.cb | 282 +- src/mainboard/tyan/s4882/irq_tables.c | 20 +- src/mainboard/tyan/s4882/mptable.c | 246 +- src/mainboard/tyan/s4882/resourcemap.c | 4 +- src/mainboard/tyan/s4882/romstage.c | 98 +- src/mainboard/tyan/s8226/BiosCallOuts.c | 68 +- src/mainboard/tyan/s8226/BiosCallOuts.h | 16 +- src/mainboard/tyan/s8226/OptionsIds.h | 8 +- src/mainboard/tyan/s8226/acpi/ide.asl | 8 +- src/mainboard/tyan/s8226/agesawrapper.c | 40 +- src/mainboard/tyan/s8226/agesawrapper.h | 22 +- src/mainboard/tyan/s8226/buildOpts.c | 256 +- src/mainboard/tyan/s8226/cmos.layout | 160 +- src/mainboard/tyan/s8226/devicetree.cb | 2 +- src/mainboard/tyan/s8226/dsdt.asl | 142 +- src/mainboard/tyan/s8226/fadt.c | 2 +- src/mainboard/tyan/s8226/get_bus_conf.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 4 +- src/mainboard/tyan/s8226/platform_oem.c | 2 +- src/mainboard/tyan/s8226/rd890_cfg.c | 4 +- src/mainboard/tyan/s8226/rd890_cfg.h | 36 +- src/mainboard/tyan/s8226/sb700_cfg.c | 4 +- src/mainboard/tyan/s8226/sb700_cfg.h | 56 +- src/mainboard/via/epia-cn/cmos.layout | 118 +- src/mainboard/via/epia-cn/devicetree.cb | 46 +- src/mainboard/via/epia-cn/irq_tables.c | 2 +- src/mainboard/via/epia-m/acpi_tables.c | 2 +- src/mainboard/via/epia-m/cmos.layout | 118 +- src/mainboard/via/epia-m/devicetree.cb | 2 +- src/mainboard/via/epia-m/dsdt.asl | 50 +- src/mainboard/via/epia-m/irq_tables.c | 10 +- src/mainboard/via/epia-m/romstage.c | 6 +- src/mainboard/via/epia-m700/acpi_tables.c | 8 +- src/mainboard/via/epia-m700/cmos.layout | 118 +- .../via/epia-m700/driving_clk_phase_data.c | 30 +- src/mainboard/via/epia-m700/irq_tables.c | 4 +- src/mainboard/via/epia-m700/romstage.c | 14 +- src/mainboard/via/epia-m700/wakeup.c | 8 +- src/mainboard/via/epia-m850/irq_tables.c | 2 +- src/mainboard/via/epia-m850/mainboard.c | 2 +- src/mainboard/via/epia-n/acpi/irq_links.asl | 416 +- src/mainboard/via/epia-n/acpi/pata_methods.asl | 92 +- src/mainboard/via/epia-n/acpi/pci_init.asl | 2 +- src/mainboard/via/epia-n/acpi/sb_physical.asl | 596 +-- src/mainboard/via/epia-n/acpi_tables.c | 10 +- src/mainboard/via/epia-n/cmos.layout | 118 +- src/mainboard/via/epia-n/devicetree.cb | 80 +- src/mainboard/via/epia-n/dsdt.asl | 550 +-- src/mainboard/via/epia-n/irq_tables.c | 6 +- src/mainboard/via/epia-n/mptable.c | 10 +- src/mainboard/via/epia/cmos.layout | 118 +- src/mainboard/via/epia/devicetree.cb | 34 +- src/mainboard/via/epia/irq_tables.c | 20 +- src/mainboard/via/pc2500e/cmos.layout | 70 +- src/mainboard/via/pc2500e/devicetree.cb | 98 +- src/mainboard/via/pc2500e/irq_tables.c | 2 +- src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl | 2 +- src/mainboard/via/vt8454c/acpi/irq.asl | 8 +- src/mainboard/via/vt8454c/cmos.layout | 64 +- src/mainboard/via/vt8454c/devicetree.cb | 4 +- src/mainboard/via/vt8454c/dsdt.asl | 62 +- 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src/southbridge/amd/sb800/smbus.c | 4 +- src/southbridge/amd/sb800/smbus.h | 8 +- src/southbridge/amd/sr5650/cmn.h | 6 +- src/southbridge/amd/sr5650/early_setup.c | 36 +- src/southbridge/amd/sr5650/ht.c | 28 +- src/southbridge/amd/sr5650/sr5650.c | 48 +- src/southbridge/broadcom/bcm21000/pcie.c | 18 +- src/southbridge/broadcom/bcm5780/nic.c | 22 +- src/southbridge/broadcom/bcm5780/pcie.c | 18 +- src/southbridge/broadcom/bcm5780/pcix.c | 22 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 12 +- src/southbridge/broadcom/bcm5785/chip.h | 8 +- src/southbridge/broadcom/bcm5785/early_setup.c | 236 +- src/southbridge/broadcom/bcm5785/early_smbus.c | 8 +- src/southbridge/broadcom/bcm5785/ide.c | 28 +- src/southbridge/broadcom/bcm5785/lpc.c | 36 +- src/southbridge/broadcom/bcm5785/reset.c | 24 +- src/southbridge/broadcom/bcm5785/sata.c | 42 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 98 +- src/southbridge/broadcom/bcm5785/smbus.h | 106 +- src/southbridge/broadcom/bcm5785/usb.c | 20 +- src/southbridge/dmp/vortex86ex/ide_sd_sata.c | 96 +- src/southbridge/dmp/vortex86ex/southbridge.c | 12 +- src/southbridge/dmp/vortex86ex/southbridge.h | 2 +- src/southbridge/intel/bd82x6x/Kconfig | 2 +- src/southbridge/intel/bd82x6x/Makefile.inc | 12 +- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 6 +- src/southbridge/intel/bd82x6x/azalia.c | 2 +- src/southbridge/intel/bd82x6x/early_me.c | 4 +- src/southbridge/intel/bd82x6x/early_spi.c | 2 +- src/southbridge/intel/bd82x6x/elog.c | 2 +- src/southbridge/intel/bd82x6x/gpio.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 52 +- src/southbridge/intel/bd82x6x/me.h | 48 +- src/southbridge/intel/bd82x6x/me_8.x.c | 84 +- src/southbridge/intel/bd82x6x/me_status.c | 46 +- src/southbridge/intel/bd82x6x/nvs.h | 2 +- src/southbridge/intel/bd82x6x/pch.c | 16 +- src/southbridge/intel/bd82x6x/pch.h | 210 +- src/southbridge/intel/bd82x6x/pcie.c | 10 +- src/southbridge/intel/bd82x6x/reset.c | 4 +- src/southbridge/intel/bd82x6x/sata.c | 2 +- src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/bd82x6x/smi.c | 4 +- src/southbridge/intel/bd82x6x/smihandler.c | 64 +- src/southbridge/intel/bd82x6x/spi.c | 12 +- src/southbridge/intel/esb6300/ac97.c | 14 +- src/southbridge/intel/esb6300/bridge1c.c | 10 +- src/southbridge/intel/esb6300/chip.h | 22 +- src/southbridge/intel/esb6300/ehci.c | 12 +- src/southbridge/intel/esb6300/ide.c | 20 +- src/southbridge/intel/esb6300/lpc.c | 22 +- src/southbridge/intel/esb6300/pci.c | 10 +- src/southbridge/intel/esb6300/pic.c | 12 +- src/southbridge/intel/esb6300/sata.c | 60 +- src/southbridge/intel/esb6300/smbus.c | 14 +- src/southbridge/intel/esb6300/smbus.h | 16 +- src/southbridge/intel/esb6300/uhci.c | 16 +- src/southbridge/intel/i3100/Kconfig | 4 +- src/southbridge/intel/i3100/chip.h | 32 +- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i3100/ehci.c | 14 +- src/southbridge/intel/i3100/i3100.h | 4 +- src/southbridge/intel/i3100/ioapic.c | 10 +- src/southbridge/intel/i3100/lpc.c | 42 +- src/southbridge/intel/i3100/pci.c | 10 +- src/southbridge/intel/i3100/pciexp_portb.c | 18 +- src/southbridge/intel/i3100/sata.c | 18 +- src/southbridge/intel/i3100/smbus.c | 16 +- src/southbridge/intel/i3100/uhci.c | 16 +- src/southbridge/intel/i82371eb/acpi/isabridge.asl | 2 +- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 102 +- src/southbridge/intel/i82371eb/i82371eb.c | 4 +- src/southbridge/intel/i82371eb/i82371eb.h | 62 +- src/southbridge/intel/i82371eb/ide.c | 20 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 14 +- src/southbridge/intel/i82371eb/wakeup.c | 6 +- src/southbridge/intel/i82801ax/ide.c | 4 +- src/southbridge/intel/i82801bx/i82801bx.c | 2 +- src/southbridge/intel/i82801bx/ide.c | 4 +- src/southbridge/intel/i82801cx/ac97.c | 20 +- src/southbridge/intel/i82801cx/i82801cx.h | 34 +- src/southbridge/intel/i82801cx/ide.c | 14 +- src/southbridge/intel/i82801cx/lpc.c | 36 +- src/southbridge/intel/i82801cx/nic.c | 8 +- src/southbridge/intel/i82801cx/pci.c | 8 +- src/southbridge/intel/i82801cx/reset.c | 6 +- src/southbridge/intel/i82801cx/smbus.c | 2 +- src/southbridge/intel/i82801cx/usb.c | 22 +- src/southbridge/intel/i82801dx/ac97.c | 48 +- src/southbridge/intel/i82801dx/early_smbus.c | 4 +- src/southbridge/intel/i82801dx/i82801dx.c | 6 +- src/southbridge/intel/i82801dx/i82801dx.h | 164 +- src/southbridge/intel/i82801dx/smi.c | 10 +- src/southbridge/intel/i82801dx/smihandler.c | 72 +- src/southbridge/intel/i82801ex/ac97.c | 14 +- src/southbridge/intel/i82801ex/chip.h | 38 +- src/southbridge/intel/i82801ex/ehci.c | 12 +- src/southbridge/intel/i82801ex/i82801ex.h | 24 +- src/southbridge/intel/i82801ex/ide.c | 10 +- src/southbridge/intel/i82801ex/lpc.c | 32 +- src/southbridge/intel/i82801ex/pci.c | 10 +- src/southbridge/intel/i82801ex/reset.c | 4 +- src/southbridge/intel/i82801ex/sata.c | 12 +- src/southbridge/intel/i82801ex/smbus.c | 14 +- src/southbridge/intel/i82801ex/smbus.h | 16 +- src/southbridge/intel/i82801ex/uhci.c | 16 +- src/southbridge/intel/i82801ex/watchdog.c | 34 +- src/southbridge/intel/i82801gx/Kconfig | 2 +- src/southbridge/intel/i82801gx/ac97.c | 34 +- src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 2 +- src/southbridge/intel/i82801gx/azalia.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 16 +- src/southbridge/intel/i82801gx/i82801gx.h | 176 +- src/southbridge/intel/i82801gx/ide.c | 2 +- src/southbridge/intel/i82801gx/pci.c | 4 +- src/southbridge/intel/i82801gx/pcie.c | 8 +- src/southbridge/intel/i82801gx/reset.c | 6 +- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801gx/smbus.c | 20 +- src/southbridge/intel/i82801gx/smi.c | 10 +- src/southbridge/intel/i82801gx/smihandler.c | 72 +- src/southbridge/intel/i82801gx/usb.c | 2 +- src/southbridge/intel/i82801ix/Kconfig | 4 +- src/southbridge/intel/i82801ix/Makefile.inc | 2 +- src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 2 +- src/southbridge/intel/i82801ix/bootblock.c | 16 +- src/southbridge/intel/i82801ix/chip.h | 2 +- src/southbridge/intel/i82801ix/dmi_setup.c | 2 +- src/southbridge/intel/i82801ix/early_init.c | 4 +- src/southbridge/intel/i82801ix/early_smbus.c | 2 +- src/southbridge/intel/i82801ix/hdaudio.c | 2 +- src/southbridge/intel/i82801ix/i82801ix.c | 12 +- src/southbridge/intel/i82801ix/i82801ix.h | 24 +- src/southbridge/intel/i82801ix/lpc.c | 12 +- src/southbridge/intel/i82801ix/pcie.c | 2 +- src/southbridge/intel/i82801ix/sata.c | 4 +- src/southbridge/intel/i82801ix/smi.c | 12 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/i82870/ioapic.c | 42 +- src/southbridge/intel/i82870/pci_parity.c | 24 +- src/southbridge/intel/i82870/pcibridge.c | 18 +- src/southbridge/intel/ibexpeak/Kconfig | 2 +- src/southbridge/intel/ibexpeak/Makefile.inc | 10 +- src/southbridge/intel/ibexpeak/azalia.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 52 +- src/southbridge/intel/ibexpeak/me.h | 50 +- src/southbridge/intel/ibexpeak/nvs.h | 2 +- src/southbridge/intel/ibexpeak/pch.h | 214 +- src/southbridge/intel/ibexpeak/sata.c | 6 +- src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/ibexpeak/smbus.h | 12 +- src/southbridge/intel/ibexpeak/smi.c | 4 +- src/southbridge/intel/ibexpeak/smihandler.c | 64 +- src/southbridge/intel/ibexpeak/spi.c | 12 +- src/southbridge/intel/lynxpoint/Makefile.inc | 8 +- src/southbridge/intel/lynxpoint/acpi/globalnvs.asl | 6 +- src/southbridge/intel/lynxpoint/acpi/lpc.asl | 2 +- src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl | 4 +- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 12 +- src/southbridge/intel/lynxpoint/azalia.c | 2 +- src/southbridge/intel/lynxpoint/early_me.c | 4 +- src/southbridge/intel/lynxpoint/early_pch.c | 2 +- src/southbridge/intel/lynxpoint/early_spi.c | 2 +- src/southbridge/intel/lynxpoint/elog.c | 4 +- src/southbridge/intel/lynxpoint/gpio.c | 2 +- src/southbridge/intel/lynxpoint/lp_gpio.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 10 +- src/southbridge/intel/lynxpoint/me.h | 60 +- src/southbridge/intel/lynxpoint/me_9.x.c | 80 +- src/southbridge/intel/lynxpoint/me_status.c | 48 +- src/southbridge/intel/lynxpoint/nvs.h | 2 +- src/southbridge/intel/lynxpoint/pch.c | 24 +- src/southbridge/intel/lynxpoint/pch.h | 230 +- src/southbridge/intel/lynxpoint/pcie.c | 10 +- src/southbridge/intel/lynxpoint/reset.c | 4 +- src/southbridge/intel/lynxpoint/sata.c | 8 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/southbridge/intel/lynxpoint/smihandler.c | 74 +- src/southbridge/intel/lynxpoint/spi.c | 12 +- src/southbridge/intel/pxhd/bridge.c | 74 +- src/southbridge/intel/sch/Kconfig | 4 +- src/southbridge/intel/sch/acpi/globalnvs.asl | 2 +- src/southbridge/intel/sch/acpi/sch.asl | 2 +- src/southbridge/intel/sch/audio.c | 4 +- src/southbridge/intel/sch/smbus.c | 2 +- src/southbridge/intel/sch/smbus.h | 2 +- src/southbridge/intel/sch/smi.c | 38 +- src/southbridge/intel/sch/smihandler.c | 38 +- src/southbridge/nvidia/ck804/Kconfig | 4 +- src/southbridge/nvidia/ck804/ac97.c | 24 +- src/southbridge/nvidia/ck804/ck804.c | 2 +- src/southbridge/nvidia/ck804/early_setup.c | 2 +- src/southbridge/nvidia/ck804/early_setup_car.c | 22 +- src/southbridge/nvidia/ck804/ht.c | 10 +- src/southbridge/nvidia/ck804/ide.c | 12 +- src/southbridge/nvidia/ck804/lpc.c | 28 +- src/southbridge/nvidia/ck804/nic.c | 18 +- src/southbridge/nvidia/ck804/pci.c | 10 +- src/southbridge/nvidia/ck804/pcie.c | 10 +- src/southbridge/nvidia/ck804/sata.c | 14 +- src/southbridge/nvidia/ck804/smbus.c | 14 +- src/southbridge/nvidia/ck804/smbus.h | 6 +- src/southbridge/nvidia/ck804/usb.c | 12 +- src/southbridge/nvidia/ck804/usb2.c | 12 +- src/southbridge/nvidia/mcp55/azalia.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/nvidia/mcp55/early_setup_car.c | 4 +- src/southbridge/nvidia/mcp55/early_smbus.c | 2 +- src/southbridge/nvidia/mcp55/ht.c | 8 +- src/southbridge/nvidia/mcp55/ide.c | 10 +- src/southbridge/nvidia/mcp55/lpc.c | 22 +- src/southbridge/nvidia/mcp55/nic.c | 2 +- src/southbridge/rdc/r8610/bootblock.c | 2 +- src/southbridge/rdc/r8610/r8610.c | 6 +- src/southbridge/ricoh/rl5c476/rl5c476.c | 14 +- src/southbridge/sis/sis966/aza.c | 66 +- src/southbridge/sis/sis966/early_smbus.c | 118 +- src/southbridge/sis/sis966/ide.c | 44 +- src/southbridge/sis/sis966/lpc.c | 60 +- src/southbridge/sis/sis966/nic.c | 160 +- src/southbridge/sis/sis966/sata.c | 50 +- src/southbridge/sis/sis966/sis761.c | 10 +- src/southbridge/sis/sis966/usb.c | 34 +- src/southbridge/sis/sis966/usb2.c | 70 +- src/southbridge/ti/pci1x2x/pci1x2x.c | 16 +- src/southbridge/ti/pci7420/cardbus.c | 12 +- src/southbridge/ti/pci7420/firewire.c | 8 +- src/southbridge/ti/pci7420/pci7420.h | 28 +- src/southbridge/ti/pcixx12/pcixx12.c | 10 +- .../via/common/early_smbus_print_error.c | 2 +- src/southbridge/via/k8t890/Kconfig | 4 +- src/southbridge/via/k8t890/chrome.c | 14 +- src/southbridge/via/k8t890/dram.c | 6 +- src/southbridge/via/k8t890/pcie.c | 4 +- src/southbridge/via/vt8231/acpi.c | 6 +- src/southbridge/via/vt8231/enable_rom.c | 2 +- src/southbridge/via/vt8231/ide.c | 6 +- src/southbridge/via/vt8231/lpc.c | 10 +- src/southbridge/via/vt8231/nic.c | 6 +- src/southbridge/via/vt8235/early_smbus.c | 6 +- src/southbridge/via/vt8235/ide.c | 10 +- src/southbridge/via/vt8235/lpc.c | 16 +- src/southbridge/via/vt8235/nic.c | 10 +- src/southbridge/via/vt8235/usb.c | 10 +- src/southbridge/via/vt8237r/ctrl.c | 10 +- src/southbridge/via/vt8237r/early_smbus.c | 18 +- src/southbridge/via/vt8237r/ide.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 18 +- src/southbridge/via/vt8237r/nvs.h | 2 +- src/southbridge/via/vt8237r/usb.c | 4 +- src/southbridge/via/vt8237r/vt8237r.h | 36 +- src/superio/acpi/pnp_generic.asl | 2 +- src/superio/acpi/pnp_uart.asl | 2 +- src/superio/fintek/f71805f/superio.c | 8 +- src/superio/fintek/f71859/superio.c | 8 +- src/superio/fintek/f71863fg/superio.c | 10 +- src/superio/fintek/f71872/superio.c | 8 +- src/superio/fintek/f71889/superio.c | 8 +- src/superio/fintek/f81865f/superio.c | 8 +- src/superio/intel/i3100/superio.c | 8 +- src/superio/ite/it8661f/it8661f.h | 4 +- src/superio/ite/it8661f/superio.c | 6 +- src/superio/ite/it8671f/early_serial.c | 16 +- src/superio/ite/it8671f/superio.c | 6 +- src/superio/ite/it8673f/early_serial.c | 10 +- src/superio/ite/it8673f/superio.c | 6 +- src/superio/ite/it8705f/early_serial.c | 10 +- src/superio/ite/it8705f/superio.c | 6 +- src/superio/ite/it8712f/early_serial.c | 12 +- src/superio/ite/it8712f/superio.c | 8 +- src/superio/ite/it8716f/early_serial.c | 10 +- src/superio/ite/it8716f/superio.c | 12 +- src/superio/ite/it8718f/early_serial.c | 10 +- src/superio/ite/it8718f/superio.c | 6 +- src/superio/ite/it8721f/early_serial.c | 10 +- src/superio/ite/it8721f/superio.c | 6 +- src/superio/ite/it8728f/it8728f.h | 4 +- src/superio/ite/it8772f/early_serial.c | 12 +- src/superio/ite/it8772f/superio.c | 8 +- src/superio/nsc/pc8374/superio.c | 6 +- src/superio/nsc/pc87309/superio.c | 6 +- src/superio/nsc/pc87351/superio.c | 6 +- src/superio/nsc/pc87360/superio.c | 6 +- src/superio/nsc/pc87366/superio.c | 6 +- src/superio/nsc/pc87382/superio.c | 6 +- src/superio/nsc/pc87384/superio.c | 4 +- src/superio/nsc/pc87392/superio.c | 6 +- src/superio/nsc/pc87417/superio.c | 6 +- src/superio/nsc/pc87427/superio.c | 6 +- src/superio/nsc/pc97307/chip.h | 4 +- src/superio/nsc/pc97307/superio.c | 6 +- src/superio/nsc/pc97317/chip.h | 4 +- src/superio/nsc/pc97317/superio.c | 6 +- src/superio/nuvoton/nct5104d/superio.c | 8 +- src/superio/nuvoton/wpcm450/superio.c | 6 +- src/superio/renesas/m3885x/superio.c | 4 +- src/superio/smsc/fdc37m60x/early_serial.c | 10 +- src/superio/smsc/fdc37m60x/superio.c | 6 +- src/superio/smsc/fdc37n972/fdc37n972.c | 6 +- src/superio/smsc/kbc1100/kbc1100.h | 20 +- src/superio/smsc/kbc1100/kbc1100_early_init.c | 2 +- src/superio/smsc/kbc1100/superio.c | 6 +- src/superio/smsc/lpc47b272/lpc47b272.h | 12 +- src/superio/smsc/lpc47b272/superio.c | 8 +- src/superio/smsc/lpc47b397/superio.c | 20 +- src/superio/smsc/lpc47m10x/lpc47m10x.h | 16 +- src/superio/smsc/lpc47m10x/superio.c | 8 +- src/superio/smsc/lpc47m15x/lpc47m15x.h | 16 +- src/superio/smsc/lpc47m15x/superio.c | 8 +- src/superio/smsc/lpc47n207/early_serial.c | 4 +- src/superio/smsc/lpc47n217/lpc47n217.h | 6 +- src/superio/smsc/lpc47n217/superio.c | 12 +- src/superio/smsc/lpc47n227/lpc47n227.h | 8 +- src/superio/smsc/lpc47n227/superio.c | 10 +- src/superio/smsc/mec1308/superio.c | 8 +- src/superio/smsc/sch4037/sch4037.h | 18 +- src/superio/smsc/sch4037/superio.c | 8 +- src/superio/smsc/sio1036/superio.c | 8 +- src/superio/smsc/sio10n268/sio10n268.c | 6 +- src/superio/smsc/smscsuperio/superio.c | 26 +- src/superio/via/vt1211/vt1211.c | 14 +- src/superio/winbond/w83627dhg/acpi/superio.asl | 2 +- src/superio/winbond/w83627dhg/superio.c | 8 +- src/superio/winbond/w83627dhg/w83627dhg.h | 24 +- src/superio/winbond/w83627ehg/superio.c | 12 +- src/superio/winbond/w83627ehg/w83627ehg.h | 20 +- src/superio/winbond/w83627hf/acpi/superio.asl | 156 +- src/superio/winbond/w83627hf/superio.c | 14 +- src/superio/winbond/w83627hf/w83627hf.h | 20 +- src/superio/winbond/w83627thg/superio.c | 20 +- src/superio/winbond/w83627thg/w83627thg.h | 18 +- src/superio/winbond/w83627uhg/superio.c | 10 +- src/superio/winbond/w83627uhg/w83627uhg.h | 2 +- src/superio/winbond/w83697hf/superio.c | 10 +- src/superio/winbond/w83697hf/w83697hf.h | 20 +- src/superio/winbond/w83977f/superio.c | 8 +- src/superio/winbond/w83977tf/superio.c | 10 +- src/superio/winbond/w83977tf/w83977tf.h | 18 +- 2342 files changed, 71350 insertions(+), 71350 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig index 1c80b8c..e0c0d02 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,16 +159,16 @@ config INCLUDE_CONFIG_FILE
$ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, - offset 0x0 + offset 0x0 Alignment: 64 bytes
- Name Offset Type Size - cmos_layout.bin 0x0 cmos layout 1159 - fallback/romstage 0x4c0 stage 339756 - fallback/coreboot_ram 0x53440 stage 186664 - fallback/payload 0x80dc0 payload 51526 - config 0x8d740 raw 3324 - (empty) 0x8e480 null 3610440 + Name Offset Type Size + cmos_layout.bin 0x0 cmos layout 1159 + fallback/romstage 0x4c0 stage 339756 + fallback/coreboot_ram 0x53440 stage 186664 + fallback/payload 0x80dc0 payload 51526 + config 0x8d740 raw 3324 + (empty) 0x8e480 null 3610440
config EARLY_CBMEM_INIT bool diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 4b1c591..235f1cb 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -52,7 +52,7 @@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuil -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ -o $(CONFIG_CBFS_ROM_OFFSET) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" $(CBFSTOOL) $@.tmp add-stage \ -f $(objcbfs)/romstage.elf -b 0 \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none @@ -66,18 +66,18 @@ $(obj)/coreboot.pre: $(CBFSTOOL) endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" + @printf " PAYLOAD none (as specified by user)\n" endif ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" + @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ @@ -97,11 +97,11 @@ bootsplash.jpg-type := bootsplash # Common recipes for all stages
$(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -O binary $< $@
$(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp $(NM) -n $@.tmp | sort > $(basename $@).map $(OBJCOPY) --strip-debug $@.tmp @@ -112,7 +112,7 @@ stages_c = $(src)/arch/armv7/stages.c stages_o = $(obj)/arch/armv7/stages.o
$(stages_o): $(stages_c) $(obj)/config.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I. $(INCLUDES) -c -o $@ $< -marm
@@ -120,7 +120,7 @@ $(stages_o): $(stages_c) $(obj)/config.h # Build the coreboot_ram (stage 2)
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/armv7/coreboot_ram.ld - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/coreboot_ram.ld else @@ -128,7 +128,7 @@ else endif
$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else @@ -156,7 +156,7 @@ crt0s += $(cpu_incs) crt0s += $(cpu_incs-y)
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" + @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
# Things that appear in every board @@ -235,19 +235,19 @@ bootblock_custom = $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_CPU_INIT)) bootblock_custom += $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_MAINBOARD_INIT))
$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@
$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) $(bootblock-S-ccopts) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) $(bootblock-S-ccopts) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) $(obj)/config.h @@ -258,7 +258,7 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_S $(CC) $(bootblock-c-ccopts) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@
$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) $(obj)/config.h - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -include $(obj)/config.h -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else @@ -269,7 +269,7 @@ endif # Build the romstage
$(objcbfs)/romstage.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage.ld else @@ -277,20 +277,20 @@ else endif
$(objgenerated)/romstage.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@
$(objgenerated)/crt0.romstage.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index b2c993a..919b3d7 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -11,7 +11,7 @@ * Copyright (c) 2003 Richard Woodruff r-woodruff2@ti.com * Copyright (c) 2003 Kshitij kshitij@ti.com * Copyright (c) 2006-2008 Syed Mohammed Khasim x0khasim@ti.com - * Copyright (c) 2013 The Chromium OS Authors + * Copyright (c) 2013 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/arch/armv7/cache.c b/src/arch/armv7/cache.c index 04eaa88..cc88c98 100644 --- a/src/arch/armv7/cache.c +++ b/src/arch/armv7/cache.c @@ -123,9 +123,9 @@ static void dcache_op_set_way(enum dcache_op op) * S: Log2(num_sets) * * The bits are packed as follows: - * 31 31-A B B-1 L L-1 4 3 1 0 + * 31 31-A B B-1 L L-1 4 3 1 0 * |---|-------------|--------|-------|-----|-| - * |Way| zeros | Set | zeros |level|0| + * |Way| zeros | Set | zeros |level|0| * |---|-------------|--------|-------|-----|-| */ for (way = 0; way < associativity; way++) { diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 38eaca3..756d8b4 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -15,7 +15,7 @@
/* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */
@@ -107,13 +107,13 @@ SECTIONS * this line. */
- _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .;
_stack = CONFIG_STACK_BOTTOM; _estack = CONFIG_STACK_TOP; diff --git a/src/arch/armv7/id.inc b/src/arch/armv7/id.inc index ffe547d..476fa3d 100644 --- a/src/arch/armv7/id.inc +++ b/src/arch/armv7/id.inc @@ -10,8 +10,8 @@ part: .asciz CONFIG_MAINBOARD_PART_NUMBER .long __id_end - ver /* Reverse offset to the vendor id */ .long __id_end - vendor /* Reverse offset to the vendor id */ -.long __id_end - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long __id_end - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end
__id_end: diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h index 5166af3..6abd0b8 100644 --- a/src/arch/armv7/include/arch/cache.h +++ b/src/arch/armv7/include/arch/cache.h @@ -54,7 +54,7 @@ /* Bits 20:19 reserved virtualization not supported */ #define SCTLR_WXN (1 << 19) /* Write permission implies XN */ #define SCTLR_UWXN (1 << 20) /* Unprivileged write permission - implies PL1 XN */ + implies PL1 XN */ #define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ #define SCTLR_U (1 << 22) /* Unaligned access behavior */ #define SCTLR_VE (1 << 24) /* Interrupt vectors enable */ diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h index f8b3005..113711f 100644 --- a/src/arch/armv7/include/arch/cpu.h +++ b/src/arch/armv7/include/arch/cpu.h @@ -41,9 +41,9 @@ struct cpu_info { };
struct cpuinfo_arm { - uint8_t arm; /* CPU family */ - uint8_t arm_vendor; /* CPU vendor */ - uint8_t arm_model; + uint8_t arm; /* CPU family */ + uint8_t arm_vendor; /* CPU vendor */ + uint8_t arm_model; };
#endif diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 10363c4..33ae227 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -34,11 +34,11 @@ #define get_byte_0 lsr #24 #define get_byte_1 lsr #16 #define get_byte_2 lsr #8 -#define get_byte_3 lsl #0 +#define get_byte_3 lsl #0 #define put_byte_0 lsl #24 #define put_byte_1 lsl #16 #define put_byte_2 lsl #8 -#define put_byte_3 lsl #0 +#define put_byte_3 lsl #0 #endif
/* diff --git a/src/arch/armv7/include/stdint.h b/src/arch/armv7/include/stdint.h index a8a0230..b805139 100644 --- a/src/arch/armv7/include/stdint.h +++ b/src/arch/armv7/include/stdint.h @@ -8,14 +8,14 @@ #endif
/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed char int8_t;
-typedef unsigned short uint16_t; -typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed short int16_t;
-typedef unsigned int uint32_t; -typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef signed int int32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint64_t; @@ -23,14 +23,14 @@ typedef signed long long int64_t; #endif
/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t;
-typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t;
-typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint_least64_t; @@ -38,14 +38,14 @@ typedef signed long long int_least64_t; #endif
/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t;
-typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t;
-typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; @@ -53,15 +53,15 @@ typedef signed long long int_fast64_t; #endif
/* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef int intptr_t; +typedef unsigned int uintptr_t;
/* Largest integral types */ #if __HAVE_LONG_LONG__ -typedef long long int intmax_t; +typedef long long int intmax_t; typedef unsigned long long uintmax_t; #else -typedef long int intmax_t; +typedef long int intmax_t; typedef unsigned long int uintmax_t; #endif
diff --git a/src/arch/armv7/interrupts.c b/src/arch/armv7/interrupts.c index 7508c69..e8cb834 100644 --- a/src/arch/armv7/interrupts.c +++ b/src/arch/armv7/interrupts.c @@ -57,11 +57,11 @@ void enable_interrupts (void) { unsigned long temp; __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); }
@@ -73,11 +73,11 @@ int disable_interrupts (void) { unsigned long old,temp; __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); return (old & 0x80) == 0; } #else diff --git a/src/arch/armv7/memmove.S b/src/arch/armv7/memmove.S index a2f9ea1..a593d44 100644 --- a/src/arch/armv7/memmove.S +++ b/src/arch/armv7/memmove.S @@ -147,25 +147,25 @@ memmove:
12: PLD( pld [r1, #-128] ) 13: ldmdb r1!, {r7, r8, r9, ip} - mov lr, r3, push #\push - subs r2, r2, #32 - ldmdb r1!, {r3, r4, r5, r6} - orr lr, lr, ip, pull #\pull - mov ip, ip, push #\push - orr ip, ip, r9, pull #\pull - mov r9, r9, push #\push - orr r9, r9, r8, pull #\pull - mov r8, r8, push #\push - orr r8, r8, r7, pull #\pull - mov r7, r7, push #\push - orr r7, r7, r6, pull #\pull - mov r6, r6, push #\push - orr r6, r6, r5, pull #\pull - mov r5, r5, push #\push - orr r5, r5, r4, pull #\pull - mov r4, r4, push #\push - orr r4, r4, r3, pull #\pull - stmdb r0!, {r4 - r9, ip, lr} + mov lr, r3, push #\push + subs r2, r2, #32 + ldmdb r1!, {r3, r4, r5, r6} + orr lr, lr, ip, pull #\pull + mov ip, ip, push #\push + orr ip, ip, r9, pull #\pull + mov r9, r9, push #\push + orr r9, r9, r8, pull #\pull + mov r8, r8, push #\push + orr r8, r8, r7, pull #\pull + mov r7, r7, push #\push + orr r7, r7, r6, pull #\pull + mov r6, r6, push #\push + orr r6, r6, r5, pull #\pull + mov r5, r5, push #\push + orr r5, r5, r4, pull #\pull + mov r4, r4, push #\push + orr r4, r4, r3, pull #\pull + stmdb r0!, {r4 - r9, ip, lr} bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) diff --git a/src/arch/armv7/mmu.c b/src/arch/armv7/mmu.c index 7d6d46a..f51ab57 100644 --- a/src/arch/armv7/mmu.c +++ b/src/arch/armv7/mmu.c @@ -73,11 +73,11 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb, * 15 - APX, 0 for full access * 14:12 - TEX, 0b000 for outer and inner write-back * 11:10 - AP, 0b11 for full access - * 9 - P, ? (FIXME: not described or possibly obsolete?) + * 9 - P, ? (FIXME: not described or possibly obsolete?) * 8: 5 - Domain - * 4 - XN, 1 to set execute-never (and also avoid prefetches) - * 3 - C, 1 for cacheable - * 2 - B, 1 for bufferable + * 4 - XN, 1 to set execute-never (and also avoid prefetches) + * 3 - C, 1 for cacheable + * 2 - B, 1 for bufferable * 1: 0 - 0b10 to indicate section entry */
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0555fc4..81b0a60 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -15,7 +15,7 @@
/* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2e54645..8308bb3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -88,46 +88,46 @@ endif endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB_ELF) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - @printf " PAYLOAD none (as specified by user)\n" + @printf " PAYLOAD none (as specified by user)\n" endif ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) endif ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) - @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif endif ifeq ($(CONFIG_PAYLOAD_FILO),y) - @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif
ifeq ($(CONFIG_PAYLOAD_GRUB2),y) - @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif
ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) - @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) - @printf " CONFIG $(DOTCONFIG)\n" + @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \ echo "# This image was built using git revision" `git rev-parse HEAD` > $(obj)/config.tmp ; \ sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ @@ -167,22 +167,22 @@ bootsplash.jpg-type := bootsplash NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
$(OPTION_TABLE_H): $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" + @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -H $@
$(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout - @printf " OPTION $(subst $(obj)/,,$(@))\n" + @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@
################################################################################ # Common recipes for all stages
$(objcbfs)/%.bin: $(objcbfs)/%.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -O binary $< $@
$(objcbfs)/%.elf: $(objcbfs)/%.debug - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cp $< $@.tmp $(NM) -n $@.tmp | sort > $(basename $@).map $(OBJCOPY) --strip-debug $@.tmp @@ -199,7 +199,7 @@ $(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/corebo else
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld else @@ -209,7 +209,7 @@ endif endif
$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else @@ -251,16 +251,16 @@ else endif
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - printf " ROMCC romstage.inc\n" + printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ else
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" + @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" + @printf " POST romstage.inc\n" sed -e 's/.rodata/.rom.data/g' -e 's/^.text/.section .rom.text/g' \ -e 's/^.section .text/.section .rom.text/g' $^ > $@.tmp mv $@.tmp $@ @@ -312,7 +312,7 @@ endif # Build the final rom image
$(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) - @printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/romstage_xip.elf \ -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ @@ -353,29 +353,29 @@ bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ endif
$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@
$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
$(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) - @printf " ROMCC $(subst $(obj)/,,$(@))\n" + @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(INCLUDES) $< -o $@
$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m elf_i386 -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld else @@ -386,7 +386,7 @@ endif # Build the romstage
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld else @@ -398,7 +398,7 @@ endif else true; fi
$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld - @printf " LINK $(subst $(obj)/,,$(@))\n" + @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld else @@ -406,14 +406,14 @@ else endif
$(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@
$(objgenerated)/romstage_xip.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(objcbfs)/base_xip.txt > $@.tmp sed -e '/ROMSTAGE_BASE/d' $(objgenerated)/romstage_null.ld >> $@.tmp @@ -426,15 +426,15 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin mv $@.tmp $@
$(objgenerated)/crt0.romstage.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" + @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
$(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $@).disasm
$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
seabios: diff --git a/src/arch/x86/acpi/statdef.asl b/src/arch/x86/acpi/statdef.asl index d9f1f83..0c155d5 100644 --- a/src/arch/x86/acpi/statdef.asl +++ b/src/arch/x86/acpi/statdef.asl @@ -20,26 +20,26 @@
/* Status and notification definitions */
-#define STA_MISSING 0x00 -#define STA_PRESENT 0x01 -#define STA_ENABLED 0x03 -#define STA_DISABLED 0x09 -#define STA_INVISIBLE 0x0B +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B #define STA_UNAVAILABLE 0x0D -#define STA_VISIBLE 0x0F +#define STA_VISIBLE 0x0F
/* SMBus status codes */ -#define SMB_OK 0x00 -#define SMB_UnknownFail 0x07 -#define SMB_DevAddrNAK 0x10 -#define SMB_DeviceError 0x11 -#define SMB_DevCmdDenied 0x12 -#define SMB_UnknownErr 0x13 -#define SMB_DevAccDenied 0x17 -#define SMB_Timeout 0x18 -#define SMB_HstUnsuppProtocol 0x19 -#define SMB_Busy 0x1A -#define SMB_PktChkError 0x1F +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F
/* Device Object Notification Values */ #define NOTIFY_BUS_CHECK 0x00 @@ -57,14 +57,14 @@ /* Battery Device Notification Values */ #define NOTIFY_BAT_STATUSCHG 0x80 #define NOTIFY_BAT_INFOCHG 0x81 -#define NOTIFY_BAT_MAINTDATA 0x82 +#define NOTIFY_BAT_MAINTDATA 0x82
/* Power Source Object Notification Values */ #define NOTIFY_PWR_STATUSCHG 0x80
/* Thermal Zone Object Notification Values */ -#define NOTIFY_TZ_STATUSCHG 0x80 -#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 #define NOTIFY_TZ_DEVLISTCHG 0x82 #define NOTIFY_TZ_RELTBLCHG 0x83
@@ -80,7 +80,7 @@ /* Processor Device Notification Values */ #define NOTIFY_CPU_PPCCHG 0x80 #define NOTIFY_CPU_CSTATECHG 0x81 -#define NOTIFY_CPU_THROTLCHG 0x82 +#define NOTIFY_CPU_THROTLCHG 0x82
/* User Presence Device Notification Values */ #define NOTIFY_USR_PRESNCECHG 0x80 @@ -88,6 +88,6 @@ /* Battery Device Notification Values */ #define NOTIFY_ALS_ILLUMCHG 0x80 #define NOTIFY_ALS_COLORTMPCHG 0x81 -#define NOTIFY_ALS_RESPCHG 0x82 +#define NOTIFY_ALS_RESPCHG 0x82
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 96cb270..3e60f90 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -629,7 +629,7 @@ void acpi_resume(void *wake_vec) /* Restore GNVS pointer in SMM if found */ if (gnvs_address && *gnvs_address) { printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n", - *gnvs_address); + *gnvs_address); smm_setup_structures((void *)*gnvs_address, NULL, NULL); } #endif @@ -723,7 +723,7 @@ void *acpi_find_wakeup_vector(void)
if (facs == NULL) { printk(BIOS_DEBUG, "No FACS found, wake up from S3 not " - "possible.\n"); + "possible.\n"); return NULL; }
@@ -757,7 +757,7 @@ void acpi_jump_to_wakeup(void *vector)
if (!acpi_backup_memory) { printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); + "No S3 resume.\n"); return; } #endif @@ -779,7 +779,7 @@ void acpi_jump_to_wakeup(void *vector) #endif
acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + HIGH_MEMORY_SAVE); } #endif
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 121cb22..c706813 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -264,8 +264,8 @@ int acpigen_write_scope(const char *name) int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { /* - Processor (_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) - { + Processor (_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) + { */ char pscope[16]; int len; @@ -290,32 +290,32 @@ int acpigen_write_empty_PCT(void) /* Name (_PCT, Package (0x02) { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } }) */ static char stream[] = { - 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */ - 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */ - 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */ - 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */ - 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ + 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, /* 00000030 "0._PCT.," */ + 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, /* 00000038 "........" */ + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000040 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, /* 00000048 "....y..." */ + 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, /* 00000050 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00000058 "........" */ 0x00, 0x79, 0x00 }; return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); @@ -326,23 +326,23 @@ int acpigen_write_empty_PTC(void) /* Name (_PTC, Package (0x02) { - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - }, - - ResourceTemplate () - { - Register (FFixedHW, - 0x00, // Bit Width - 0x00, // Bit Offset - 0x0000000000000000, // Address - ,) - } + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } }) */ int len, nlen, rlen; @@ -384,7 +384,7 @@ int acpigen_write_PPC(u8 nr) /* Method (_PPC, 0, NotSerialized) { - Return (nr) + Return (nr) } */ int len; @@ -413,7 +413,7 @@ int acpigen_write_PPC_NVS(void) /* Method (_PPC, 0, NotSerialized) { - Return (PPCM) + Return (PPCM) } */ int len; @@ -439,7 +439,7 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) // Sample _TPC method Method (_TPC, 0, NotSerialized) { - Return (\TLVL) + Return (\TLVL) } */ int len; @@ -455,7 +455,7 @@ int acpigen_write_TPC(const char *gnvs_tpc_limit) }
int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, - u32 busmLat, u32 control, u32 status) + u32 busmLat, u32 control, u32 status) { int len; len = acpigen_write_package(6); @@ -469,7 +469,7 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, acpigen_patch_len(len - 1);
printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n", - coreFreq, power, control, status); + coreFreq, power, control, status);
return len; } @@ -532,8 +532,8 @@ int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) Sample _TSS package with 100% and 50% duty cycles Name (_TSS, Package (0x02) { - Package(){100, 1000, 0, 0x00, 0) - Package(){50, 520, 0, 0x18, 0) + Package(){100, 1000, 0, 0x00, 0) + Package(){50, 520, 0, 0x18, 0) }) */ int i, len, plen, nlen; diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 1b28a4c..f36099f 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -49,7 +49,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) " pushl %%ebx\n\t" /* Save the parameters I was passed */ " pushl $0\n\t" /* 20 adjust */ - " pushl %0\n\t" /* 16 lb_start */ + " pushl %0\n\t" /* 16 lb_start */ " pushl %1\n\t" /* 12 buffer */ " pushl %2\n\t" /* 8 lb_size */ " pushl %3\n\t" /* 4 entry */ diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 8c380e5..e9c5598 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -56,26 +56,26 @@ static unsigned char smp_compute_checksum(void *v, int len)
static void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr, unsigned int virtualwire) { - struct intel_mp_floating *mf; - void *v; + struct intel_mp_floating *mf; + void *v;
v = (void *)addr; - mf = v; - mf->mpf_signature[0] = '_'; - mf->mpf_signature[1] = 'M'; - mf->mpf_signature[2] = 'P'; - mf->mpf_signature[3] = '_'; - mf->mpf_physptr = mpf_physptr; - mf->mpf_length = 1; - mf->mpf_specification = 4; - mf->mpf_checksum = 0; - mf->mpf_feature1 = 0; - mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0; - mf->mpf_feature3 = 0; - mf->mpf_feature4 = 0; - mf->mpf_feature5 = 0; - mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); - return v; + mf = v; + mf->mpf_signature[0] = '_'; + mf->mpf_signature[1] = 'M'; + mf->mpf_signature[2] = 'P'; + mf->mpf_signature[3] = '_'; + mf->mpf_physptr = mpf_physptr; + mf->mpf_length = 1; + mf->mpf_specification = 4; + mf->mpf_checksum = 0; + mf->mpf_feature1 = 0; + mf->mpf_feature2 = virtualwire?MP_FEATURE_VIRTUALWIRE:0; + mf->mpf_feature3 = 0; + mf->mpf_feature4 = 0; + mf->mpf_feature5 = 0; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); + return v; }
void *smp_write_floating_table(unsigned long addr, unsigned int virtualwire) @@ -170,7 +170,7 @@ void smp_write_processors(struct mp_config_table *mc) ); break; } - } + } } }
@@ -351,12 +351,12 @@ void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa)
void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, unsigned long apicid, int external_int2) { -/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ +/*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT, - MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0); + MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid, 0x1); smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT, - MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2); + MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid, 0x6); @@ -415,14 +415,14 @@ void *mptable_finalize(struct mp_config_table *mc) unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) { struct drivers_generic_ioapic_config *ioapic_config; - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus, pin, parentpin; device_t dev, parent, oldparent; void *tmp, *v; int isaioapic = -1, have_fixed_entries;
v = smp_write_floating_table(addr, 0); - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
@@ -439,8 +439,8 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) continue; } smp_write_ioapic(mc, dev->path.ioapic.ioapic_id, - ioapic_config->version, - ioapic_config->base); + ioapic_config->version, + ioapic_config->base);
if (ioapic_config->have_isa_interrupts) { if (isaioapic >= 0) @@ -465,9 +465,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr) for (pin = 0; pin < 4; pin++) { if (dev->pci_irq_info[pin].ioapic_dst_id) { printk(BIOS_DEBUG, "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); + pin + 'A', + dev->pci_irq_info[pin].ioapic_dst_id, + dev->pci_irq_info[pin].ioapic_irq_pin); smp_write_intsrc(mc, mp_INT, dev->pci_irq_info[pin].ioapic_flags, dev->bus->secondary, @@ -489,9 +489,9 @@ unsigned long __attribute__((weak)) write_smp_table(unsigned long addr)
if (parent->pci_irq_info[parentpin].ioapic_dst_id) { printk(BIOS_DEBUG, "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - parent->pci_irq_info[parentpin].ioapic_dst_id, - parent->pci_irq_info[parentpin].ioapic_irq_pin); + dev_path(dev), pin + 'A', + parent->pci_irq_info[parentpin].ioapic_dst_id, + parent->pci_irq_info[parentpin].ioapic_irq_pin); smp_write_intsrc(mc, mp_INT, parent->pci_irq_info[parentpin].ioapic_flags, dev->bus->secondary, diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index 86af63f..7586e85 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -33,8 +33,8 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
if (sizeof(struct irq_routing_table) != rt->size) { printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", - (unsigned int) sizeof(struct irq_routing_table), - rt->size + (unsigned int) sizeof(struct irq_routing_table), + rt->size ); rt->size=sizeof(struct irq_routing_table); } @@ -50,7 +50,7 @@ static void check_pirq_routing_table(struct irq_routing_table *rt)
if (sum != rt->checksum) { printk(BIOS_WARNING, "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n", - rt->checksum, sum); + rt->checksum, sum); rt->checksum = sum; }
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 65bf538..02a46f5 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -138,7 +138,7 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); #else #define SPACES \ - " " + " " t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); u32 version_offset = (u32)smbios_string_table_len(t->eos); t->bios_version = smbios_add_string(t->eos, SPACES); @@ -396,7 +396,7 @@ unsigned long smbios_write_tables(unsigned long current) se->struct_table_length = len;
se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10, - sizeof(struct smbios_entry) - 0x10); + sizeof(struct smbios_entry) - 0x10); se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry)); return current; } diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index eea9bf1..f3eeb5a 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -139,7 +139,7 @@ struct lb_memory *write_tables(void) if (new_high_table_pointer > ( high_table_pointer + MAX_ACPI_SIZE)) { printk(BIOS_ERR, "ERROR: Increase ACPI size\n"); } - printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", + printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer);
/* Now we need to create a low table copy of the RSDP. */ @@ -157,7 +157,7 @@ struct lb_memory *write_tables(void) */ if (acpi_start < new_high_table_pointer) { acpi_rsdp_t *low_rsdp = (acpi_rsdp_t *)rom_table_end, - *high_rsdp = (acpi_rsdp_t *)acpi_start; + *high_rsdp = (acpi_rsdp_t *)acpi_start;
acpi_write_rsdp(low_rsdp, (acpi_rsdt_t *)(high_rsdp->rsdt_address), @@ -186,7 +186,7 @@ struct lb_memory *write_tables(void) if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) { printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n"); } - printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", + printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { unsigned long new_rom_table_end = smbios_write_tables(rom_table_end); @@ -238,13 +238,13 @@ struct lb_memory *write_tables(void) __func__, new_high_table_pointer - high_table_pointer);
- printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", + printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n", new_high_table_pointer - high_table_pointer); } else { /* The coreboot table must be in 0-4K or 960K-1M */ rom_table_end = write_coreboot_table( - low_table_start, low_table_end, - rom_table_start, rom_table_end); + low_table_start, low_table_end, + rom_table_start, rom_table_end); }
#if CONFIG_MULTIBOOT diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld index ea32837..e5a8498 100644 --- a/src/arch/x86/coreboot_ram.ld +++ b/src/arch/x86/coreboot_ram.ld @@ -15,7 +15,7 @@
/* * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman + * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */
@@ -101,13 +101,13 @@ SECTIONS } _ebss = .;
- _heap = .; - .heap . : { - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . = CONFIG_HEAP_SIZE ; - . = ALIGN(4); - } - _eheap = .; + _heap = .; + .heap . : { + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . = CONFIG_HEAP_SIZE ; + . = ALIGN(4); + } + _eheap = .;
/* The ram segment. This includes all memory used by the memory * resident copy of coreboot, except the tables that are produced on diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 306f7da..6c24e24 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -34,7 +34,7 @@ #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "CORE " /* Must be exactly 6 bytes long! */ -#define ASLC "CORE" /* Must be exactly 4 bytes long! */ +#define ASLC "CORE" /* Must be exactly 4 bytes long! */
/* RSDP (Root System Description Pointer) */ typedef struct acpi_rsdp { @@ -64,9 +64,9 @@ typedef struct acpi_gen_regaddr { } __attribute__ ((packed)) acpi_addr_t;
#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ -#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ #define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ -#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ #define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ @@ -74,7 +74,7 @@ typedef struct acpi_gen_regaddr { #define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ #define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ #define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ #define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ @@ -88,13 +88,13 @@ typedef struct acpi_gen_regaddr {
/* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ - u32 length; /* Table length in bytes (incl. header) */ - u8 revision; /* Table version (not ACPI version!) */ - u8 checksum; /* To make sum of entire table == 0 */ - char oem_id[6]; /* OEM identification */ - char oem_table_id[8]; /* OEM table identification */ - u32 oem_revision; /* OEM revision number */ + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ char asl_compiler_id[4]; /* ASL compiler vendor ID */ u32 asl_compiler_revision; /* ASL compiler revision number */ } __attribute__ ((packed)) acpi_header_t; @@ -491,7 +491,7 @@ unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); unsigned long acpi_fill_slit(unsigned long current); unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id); + const char *oem_table_id); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt);
@@ -509,7 +509,7 @@ int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags); int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, @@ -519,7 +519,7 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat);
@@ -533,10 +533,10 @@ void acpi_create_facs(acpi_facs_t *facs);
void acpi_create_dmar(acpi_dmar_t *dmar); unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u32 bar); + u16 segment, u32 bar); void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current); unsigned long acpi_create_dmar_drhd_ds_pci(unsigned long current, u8 segment, - u8 dev, u8 fn); + u8 dev, u8 fn);
unsigned long acpi_fill_dmar(unsigned long);
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 3e50be4..e749908 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -131,15 +131,15 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_INVALID 0 #define X86_VENDOR_INTEL 1 #define X86_VENDOR_CYRIX 2 -#define X86_VENDOR_AMD 3 -#define X86_VENDOR_UMC 4 +#define X86_VENDOR_AMD 3 +#define X86_VENDOR_UMC 4 #define X86_VENDOR_NEXGEN 5 #define X86_VENDOR_CENTAUR 6 -#define X86_VENDOR_RISE 7 +#define X86_VENDOR_RISE 7 #define X86_VENDOR_TRANSMETA 8 -#define X86_VENDOR_NSC 9 -#define X86_VENDOR_SIS 10 -#define X86_VENDOR_ANY 0xfe +#define X86_VENDOR_NSC 9 +#define X86_VENDOR_SIS 10 +#define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff
int cpu_phys_address_size(void); @@ -194,21 +194,21 @@ static inline unsigned long cpu_index(void)
#ifndef __ROMCC__ // romcc is segfaulting in some cases struct cpuinfo_x86 { - uint8_t x86; /* CPU family */ - uint8_t x86_vendor; /* CPU vendor */ - uint8_t x86_model; - uint8_t x86_mask; + uint8_t x86; /* CPU family */ + uint8_t x86_vendor; /* CPU vendor */ + uint8_t x86_model; + uint8_t x86_mask; };
static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) { - c->x86 = (tfms >> 8) & 0xf; - c->x86_model = (tfms >> 4) & 0xf; - c->x86_mask = tfms & 0xf; - if (c->x86 == 0xf) - c->x86 += (tfms >> 20) & 0xff; - if (c->x86 >= 0x6) - c->x86_model += ((tfms >> 16) & 0xF) << 4; + c->x86 = (tfms >> 8) & 0xf; + c->x86_model = (tfms >> 4) & 0xf; + c->x86_mask = tfms & 0xf; + if (c->x86 == 0xf) + c->x86 += (tfms >> 20) & 0xff; + if (c->x86 >= 0x6) + c->x86_model += ((tfms >> 16) & 0xF) << 4;
} #endif diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 955d8e2..4f29bc6 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -170,26 +170,26 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui #if defined(__PRE_RAM__) || defined(__SMM__) static inline int log2(int value) { - unsigned int r = 0; - __asm__ volatile ( - "bsrl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; + unsigned int r = 0; + __asm__ volatile ( + "bsrl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r;
} static inline int log2f(int value) { - unsigned int r = 0; - __asm__ volatile ( - "bsfl %1, %0\n\t" - "jnz 1f\n\t" - "movl $-1, %0\n\t" - "1:\n\t" - : "=r" (r) : "r" (value)); - return r; + unsigned int r = 0; + __asm__ volatile ( + "bsfl %1, %0\n\t" + "jnz 1f\n\t" + "movl $-1, %0\n\t" + "1:\n\t" + : "=r" (r) : "r" (value)); + return r;
} #endif @@ -197,15 +197,15 @@ static inline int log2f(int value) #ifdef __SIMPLE_DEVICE__
#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12) | \ - ((WHERE) & 0xFFF)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12) | \ + ((WHERE) & 0xFFF))
#define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12))
#define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) @@ -248,14 +248,14 @@ void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; }
static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) @@ -274,17 +274,17 @@ static inline pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus { pci_devfn_t dev, last;
- dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for(; dev <=last; dev += PCI_DEV(0,0,1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) { - return dev; - } - } - return PCI_DEV_INVALID; + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for(; dev <=last; dev += PCI_DEV(0,0,1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) { + return dev; + } + } + return PCI_DEV_INVALID; }
/* Generic functions for pnp devices */ diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 63e1ac9..e5dea8f 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -38,9 +38,9 @@ uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inw(0xCFC + (addr & 2)); @@ -51,9 +51,9 @@ uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); return inl(0xCFC); @@ -64,9 +64,9 @@ void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outb(value, 0xCFC + (addr & 3)); @@ -75,14 +75,14 @@ void pci_io_write_config8(pci_devfn_t dev, unsigned where, uint8_t value) static inline __attribute__((always_inline)) void pci_io_write_config16(pci_devfn_t dev, unsigned where, uint16_t value) { - unsigned addr; + unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); }
static inline __attribute__((always_inline)) @@ -90,9 +90,9 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; + addr = (dev>>4) | where; #else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); #endif outl(0x80000000 | (addr & ~3), 0xCF8); outl(value, 0xCFC); diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h index e5e6195..49fdb9b 100644 --- a/src/arch/x86/include/arch/smp/mpspec.h +++ b/src/arch/x86/include/arch/smp/mpspec.h @@ -34,7 +34,7 @@ struct intel_mp_floating unsigned char mpf_feature1; /* Standard or configuration ? */ unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ #define MP_FEATURE_VIRTUALWIRE (1 << 7) -#define MP_FEATURE_PIC (0 << 7) +#define MP_FEATURE_PIC (0 << 7) unsigned char mpf_feature3; /* Unused (0) */ unsigned char mpf_feature4; /* Unused (0) */ unsigned char mpf_feature5; /* Unused (0) */ @@ -128,11 +128,11 @@ enum mp_irq_source_types { #define MP_IRQ_POLARITY_DEFAULT 0x0 #define MP_IRQ_POLARITY_HIGH 0x1 #define MP_IRQ_POLARITY_LOW 0x3 -#define MP_IRQ_POLARITY_MASK 0x3 +#define MP_IRQ_POLARITY_MASK 0x3 #define MP_IRQ_TRIGGER_DEFAULT 0x0 #define MP_IRQ_TRIGGER_EDGE 0x4 #define MP_IRQ_TRIGGER_LEVEL 0xc -#define MP_IRQ_TRIGGER_MASK 0xc +#define MP_IRQ_TRIGGER_MASK 0xc
struct mpc_config_lintsrc @@ -186,7 +186,7 @@ struct mp_exten_system_address_space { unsigned char mpe_length; unsigned char mpe_busid; unsigned char mpe_address_type; -#define ADDRESS_TYPE_IO 0 +#define ADDRESS_TYPE_IO 0 #define ADDRESS_TYPE_MEM 1 #define ADDRESS_TYPE_PREFETCH 2 unsigned int mpe_address_base_low; diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index c491f4b..7bfb844 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -8,14 +8,14 @@ #endif
/* Exact integral types */ -typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed char int8_t;
-typedef unsigned short uint16_t; -typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed short int16_t;
-typedef unsigned int uint32_t; -typedef signed int int32_t; +typedef unsigned int uint32_t; +typedef signed int int32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint64_t; @@ -23,14 +23,14 @@ typedef signed long long int64_t; #endif
/* Small types */ -typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef unsigned char uint_least8_t; +typedef signed char int_least8_t;
-typedef unsigned short uint_least16_t; -typedef signed short int_least16_t; +typedef unsigned short uint_least16_t; +typedef signed short int_least16_t;
-typedef unsigned int uint_least32_t; -typedef signed int int_least32_t; +typedef unsigned int uint_least32_t; +typedef signed int int_least32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint_least64_t; @@ -38,14 +38,14 @@ typedef signed long long int_least64_t; #endif
/* Fast Types */ -typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef unsigned char uint_fast8_t; +typedef signed char int_fast8_t;
-typedef unsigned int uint_fast16_t; -typedef signed int int_fast16_t; +typedef unsigned int uint_fast16_t; +typedef signed int int_fast16_t;
-typedef unsigned int uint_fast32_t; -typedef signed int int_fast32_t; +typedef unsigned int uint_fast32_t; +typedef signed int int_fast32_t;
#if __HAVE_LONG_LONG__ typedef unsigned long long uint_fast64_t; @@ -53,15 +53,15 @@ typedef signed long long int_fast64_t; #endif
/* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef int intptr_t; +typedef unsigned int uintptr_t;
/* Largest integral types */ #if __HAVE_LONG_LONG__ -typedef long long int intmax_t; +typedef long long int intmax_t; typedef unsigned long long uintmax_t; #else -typedef long int intmax_t; +typedef long int intmax_t; typedef unsigned long int uintmax_t; #endif
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 01ffa7c..27ff6b7 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -42,7 +42,7 @@ _start: leal _stack, %edi movl $_estack, %ecx subl %edi, %ecx - shrl $2, %ecx /* it is 32 bit aligned, right? */ + shrl $2, %ecx /* it is 32 bit aligned, right? */ movl $0xDEADBEEF, %eax rep stosl @@ -293,12 +293,12 @@ gdt: /* The next two entries are used for executing VGA option ROMs */
/* selgdt 0x28 16 bit 64k code at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x9a, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x9a, 0, 0
/* selgdt 0x30 16 bit 64k data at 0x00000000 */ - .word 0xffff, 0x0000 - .byte 0, 0x92, 0, 0 + .word 0xffff, 0x0000 + .byte 0, 0x92, 0, 0
/* The next two entries are used for ACPI S3 RESUME */
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 4a3bd96..2526306 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -92,30 +92,30 @@ static struct { int vendor; const char *name; } x86_vendors[] = { - { X86_VENDOR_INTEL, "GenuineIntel", }, - { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, - { X86_VENDOR_UMC, "UMC UMC UMC ", }, - { X86_VENDOR_NEXGEN, "NexGenDriven", }, - { X86_VENDOR_CENTAUR, "CentaurHauls", }, - { X86_VENDOR_RISE, "RiseRiseRise", }, - { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, + { X86_VENDOR_INTEL, "GenuineIntel", }, + { X86_VENDOR_CYRIX, "CyrixInstead", }, + { X86_VENDOR_AMD, "AuthenticAMD", }, + { X86_VENDOR_UMC, "UMC UMC UMC ", }, + { X86_VENDOR_NEXGEN, "NexGenDriven", }, + { X86_VENDOR_CENTAUR, "CentaurHauls", }, + { X86_VENDOR_RISE, "RiseRiseRise", }, + { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, - { X86_VENDOR_NSC, "Geode by NSC", }, - { X86_VENDOR_SIS, "SiS SiS SiS ", }, + { X86_VENDOR_NSC, "Geode by NSC", }, + { X86_VENDOR_SIS, "SiS SiS SiS ", }, };
static const char *x86_vendor_name[] = { - [X86_VENDOR_INTEL] = "Intel", - [X86_VENDOR_CYRIX] = "Cyrix", - [X86_VENDOR_AMD] = "AMD", - [X86_VENDOR_UMC] = "UMC", - [X86_VENDOR_NEXGEN] = "NexGen", - [X86_VENDOR_CENTAUR] = "Centaur", - [X86_VENDOR_RISE] = "Rise", + [X86_VENDOR_INTEL] = "Intel", + [X86_VENDOR_CYRIX] = "Cyrix", + [X86_VENDOR_AMD] = "AMD", + [X86_VENDOR_UMC] = "UMC", + [X86_VENDOR_NEXGEN] = "NexGen", + [X86_VENDOR_CENTAUR] = "Centaur", + [X86_VENDOR_RISE] = "Rise", [X86_VENDOR_TRANSMETA] = "Transmeta", - [X86_VENDOR_NSC] = "NSC", - [X86_VENDOR_SIS] = "SiS", + [X86_VENDOR_NSC] = "NSC", + [X86_VENDOR_SIS] = "SiS", };
static const char *cpu_vendor_name(int vendor) @@ -178,7 +178,7 @@ static void identify_cpu(struct device *cpu) int cpuid_level; struct cpuid_result result; result = cpuid(0x00000000); - cpuid_level = result.eax; + cpuid_level = result.eax; vendor_name[ 0] = (result.ebx >> 0) & 0xff; vendor_name[ 1] = (result.ebx >> 8) & 0xff; vendor_name[ 2] = (result.ebx >> 16) & 0xff; diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..0216911 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -17,152 +17,152 @@ enum regnames {
static uint32_t gdb_stub_registers[NUM_REGS];
-#define GDB_SIG0 0 /* Signal 0 */ -#define GDB_SIGHUP 1 /* Hangup */ -#define GDB_SIGINT 2 /* Interrupt */ -#define GDB_SIGQUIT 3 /* Quit */ -#define GDB_SIGILL 4 /* Illegal instruction */ -#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ -#define GDB_SIGABRT 6 /* Aborted */ -#define GDB_SIGEMT 7 /* Emulation trap */ -#define GDB_SIGFPE 8 /* Arithmetic exception */ -#define GDB_SIGKILL 9 /* Killed */ -#define GDB_SIGBUS 10 /* Bus error */ -#define GDB_SIGSEGV 11 /* Segmentation fault */ -#define GDB_SIGSYS 12 /* Bad system call */ -#define GDB_SIGPIPE 13 /* Broken pipe */ -#define GDB_SIGALRM 14 /* Alarm clock */ -#define GDB_SIGTERM 15 /* Terminated */ -#define GDB_SIGURG 16 /* Urgent I/O condition */ -#define GDB_SIGSTOP 17 /* Stopped (signal) */ -#define GDB_SIGTSTP 18 /* Stopped (user) */ -#define GDB_SIGCONT 19 /* Continued */ -#define GDB_SIGCHLD 20 /* Child status changed */ -#define GDB_SIGTTIN 21 /* Stopped (tty input) */ -#define GDB_SIGTTOU 22 /* Stopped (tty output) */ -#define GDB_SIGIO 23 /* I/O possible */ -#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ -#define GDB_SIGXFSZ 25 /* File size limit exceeded */ -#define GDB_SIGVTALRM 26 /* Virtual timer expired */ -#define GDB_SIGPROF 27 /* Profiling timer expired */ -#define GDB_SIGWINCH 28 /* Window size changed */ -#define GDB_SIGLOST 29 /* Resource lost */ -#define GDB_SIGUSR1 30 /* User defined signal 1 */ -#define GDB_SUGUSR2 31 /* User defined signal 2 */ -#define GDB_SIGPWR 32 /* Power fail/restart */ -#define GDB_SIGPOLL 33 /* Pollable event occurred */ -#define GDB_SIGWIND 34 /* SIGWIND */ -#define GDB_SIGPHONE 35 /* SIGPHONE */ -#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ -#define GDB_SIGLWP 37 /* Signal LWP */ -#define GDB_SIGDANGER 38 /* Swap space dangerously low */ -#define GDB_SIGGRANT 39 /* Monitor mode granted */ -#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ -#define GDB_SIGMSG 41 /* Monitor mode data available */ -#define GDB_SIGSOUND 42 /* Sound completed */ -#define GDB_SIGSAK 43 /* Secure attention */ -#define GDB_SIGPRIO 44 /* SIGPRIO */ - -#define GDB_SIG33 45 /* Real-time event 33 */ -#define GDB_SIG34 46 /* Real-time event 34 */ -#define GDB_SIG35 47 /* Real-time event 35 */ -#define GDB_SIG36 48 /* Real-time event 36 */ -#define GDB_SIG37 49 /* Real-time event 37 */ -#define GDB_SIG38 50 /* Real-time event 38 */ -#define GDB_SIG39 51 /* Real-time event 39 */ -#define GDB_SIG40 52 /* Real-time event 40 */ -#define GDB_SIG41 53 /* Real-time event 41 */ -#define GDB_SIG42 54 /* Real-time event 42 */ -#define GDB_SIG43 55 /* Real-time event 43 */ -#define GDB_SIG44 56 /* Real-time event 44 */ -#define GDB_SIG45 57 /* Real-time event 45 */ -#define GDB_SIG46 58 /* Real-time event 46 */ -#define GDB_SIG47 59 /* Real-time event 47 */ -#define GDB_SIG48 60 /* Real-time event 48 */ -#define GDB_SIG49 61 /* Real-time event 49 */ -#define GDB_SIG50 62 /* Real-time event 50 */ -#define GDB_SIG51 63 /* Real-time event 51 */ -#define GDB_SIG52 64 /* Real-time event 52 */ -#define GDB_SIG53 65 /* Real-time event 53 */ -#define GDB_SIG54 66 /* Real-time event 54 */ -#define GDB_SIG55 67 /* Real-time event 55 */ -#define GDB_SIG56 68 /* Real-time event 56 */ -#define GDB_SIG57 69 /* Real-time event 57 */ -#define GDB_SIG58 70 /* Real-time event 58 */ -#define GDB_SIG59 71 /* Real-time event 59 */ -#define GDB_SIG60 72 /* Real-time event 60 */ -#define GDB_SIG61 73 /* Real-time event 61 */ -#define GDB_SIG62 74 /* Real-time event 62 */ -#define GDB_SIG63 75 /* Real-time event 63 */ -#define GDB_SIGCANCEL 76 /* LWP internal signal */ -#define GDB_SIG32 77 /* Real-time event 32 */ -#define GDB_SIG64 78 /* Real-time event 64 */ -#define GDB_SIG65 79 /* Real-time event 65 */ -#define GDB_SIG66 80 /* Real-time event 66 */ -#define GDB_SIG67 81 /* Real-time event 67 */ -#define GDB_SIG68 82 /* Real-time event 68 */ -#define GDB_SIG69 83 /* Real-time event 69 */ -#define GDB_SIG70 84 /* Real-time event 70 */ -#define GDB_SIG71 85 /* Real-time event 71 */ -#define GDB_SIG72 86 /* Real-time event 72 */ -#define GDB_SIG73 87 /* Real-time event 73 */ -#define GDB_SIG74 88 /* Real-time event 74 */ -#define GDB_SIG75 89 /* Real-time event 75 */ -#define GDB_SIG76 90 /* Real-time event 76 */ -#define GDB_SIG77 91 /* Real-time event 77 */ -#define GDB_SIG78 92 /* Real-time event 78 */ -#define GDB_SIG79 93 /* Real-time event 79 */ -#define GDB_SIG80 94 /* Real-time event 80 */ -#define GDB_SIG81 95 /* Real-time event 81 */ -#define GDB_SIG82 96 /* Real-time event 82 */ -#define GDB_SIG83 97 /* Real-time event 83 */ -#define GDB_SIG84 98 /* Real-time event 84 */ -#define GDB_SIG85 99 /* Real-time event 85 */ -#define GDB_SIG86 100 /* Real-time event 86 */ -#define GDB_SIG87 101 /* Real-time event 87 */ -#define GDB_SIG88 102 /* Real-time event 88 */ -#define GDB_SIG89 103 /* Real-time event 89 */ -#define GDB_SIG90 104 /* Real-time event 90 */ -#define GDB_SIG91 105 /* Real-time event 91 */ -#define GDB_SIG92 106 /* Real-time event 92 */ -#define GDB_SIG93 107 /* Real-time event 93 */ -#define GDB_SIG94 108 /* Real-time event 94 */ -#define GDB_SIG95 109 /* Real-time event 95 */ -#define GDB_SIG96 110 /* Real-time event 96 */ -#define GDB_SIG97 111 /* Real-time event 97 */ -#define GDB_SIG98 112 /* Real-time event 98 */ -#define GDB_SIG99 113 /* Real-time event 99 */ -#define GDB_SIG100 114 /* Real-time event 100 */ -#define GDB_SIG101 115 /* Real-time event 101 */ -#define GDB_SIG102 116 /* Real-time event 102 */ -#define GDB_SIG103 117 /* Real-time event 103 */ -#define GDB_SIG104 118 /* Real-time event 104 */ -#define GDB_SIG105 119 /* Real-time event 105 */ -#define GDB_SIG106 120 /* Real-time event 106 */ -#define GDB_SIG107 121 /* Real-time event 107 */ -#define GDB_SIG108 122 /* Real-time event 108 */ -#define GDB_SIG109 123 /* Real-time event 109 */ -#define GDB_SIG110 124 /* Real-time event 110 */ -#define GDB_SIG111 125 /* Real-time event 111 */ -#define GDB_SIG112 126 /* Real-time event 112 */ -#define GDB_SIG113 127 /* Real-time event 113 */ -#define GDB_SIG114 128 /* Real-time event 114 */ -#define GDB_SIG115 129 /* Real-time event 115 */ -#define GDB_SIG116 130 /* Real-time event 116 */ -#define GDB_SIG117 131 /* Real-time event 117 */ -#define GDB_SIG118 132 /* Real-time event 118 */ -#define GDB_SIG119 133 /* Real-time event 119 */ -#define GDB_SIG120 134 /* Real-time event 120 */ -#define GDB_SIG121 135 /* Real-time event 121 */ -#define GDB_SIG122 136 /* Real-time event 122 */ -#define GDB_SIG123 137 /* Real-time event 123 */ -#define GDB_SIG124 138 /* Real-time event 124 */ -#define GDB_SIG125 139 /* Real-time event 125 */ -#define GDB_SIG126 140 /* Real-time event 126 */ -#define GDB_SIG127 141 /* Real-time event 127 */ -#define GDB_SIGINFO 142 /* Information request */ -#define GDB_UNKNOWN 143 /* Unknown signal */ -#define GDB_DEFAULT 144 /* error: default signal */ +#define GDB_SIG0 0 /* Signal 0 */ +#define GDB_SIGHUP 1 /* Hangup */ +#define GDB_SIGINT 2 /* Interrupt */ +#define GDB_SIGQUIT 3 /* Quit */ +#define GDB_SIGILL 4 /* Illegal instruction */ +#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ +#define GDB_SIGABRT 6 /* Aborted */ +#define GDB_SIGEMT 7 /* Emulation trap */ +#define GDB_SIGFPE 8 /* Arithmetic exception */ +#define GDB_SIGKILL 9 /* Killed */ +#define GDB_SIGBUS 10 /* Bus error */ +#define GDB_SIGSEGV 11 /* Segmentation fault */ +#define GDB_SIGSYS 12 /* Bad system call */ +#define GDB_SIGPIPE 13 /* Broken pipe */ +#define GDB_SIGALRM 14 /* Alarm clock */ +#define GDB_SIGTERM 15 /* Terminated */ +#define GDB_SIGURG 16 /* Urgent I/O condition */ +#define GDB_SIGSTOP 17 /* Stopped (signal) */ +#define GDB_SIGTSTP 18 /* Stopped (user) */ +#define GDB_SIGCONT 19 /* Continued */ +#define GDB_SIGCHLD 20 /* Child status changed */ +#define GDB_SIGTTIN 21 /* Stopped (tty input) */ +#define GDB_SIGTTOU 22 /* Stopped (tty output) */ +#define GDB_SIGIO 23 /* I/O possible */ +#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ +#define GDB_SIGXFSZ 25 /* File size limit exceeded */ +#define GDB_SIGVTALRM 26 /* Virtual timer expired */ +#define GDB_SIGPROF 27 /* Profiling timer expired */ +#define GDB_SIGWINCH 28 /* Window size changed */ +#define GDB_SIGLOST 29 /* Resource lost */ +#define GDB_SIGUSR1 30 /* User defined signal 1 */ +#define GDB_SUGUSR2 31 /* User defined signal 2 */ +#define GDB_SIGPWR 32 /* Power fail/restart */ +#define GDB_SIGPOLL 33 /* Pollable event occurred */ +#define GDB_SIGWIND 34 /* SIGWIND */ +#define GDB_SIGPHONE 35 /* SIGPHONE */ +#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ +#define GDB_SIGLWP 37 /* Signal LWP */ +#define GDB_SIGDANGER 38 /* Swap space dangerously low */ +#define GDB_SIGGRANT 39 /* Monitor mode granted */ +#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ +#define GDB_SIGMSG 41 /* Monitor mode data available */ +#define GDB_SIGSOUND 42 /* Sound completed */ +#define GDB_SIGSAK 43 /* Secure attention */ +#define GDB_SIGPRIO 44 /* SIGPRIO */ + +#define GDB_SIG33 45 /* Real-time event 33 */ +#define GDB_SIG34 46 /* Real-time event 34 */ +#define GDB_SIG35 47 /* Real-time event 35 */ +#define GDB_SIG36 48 /* Real-time event 36 */ +#define GDB_SIG37 49 /* Real-time event 37 */ +#define GDB_SIG38 50 /* Real-time event 38 */ +#define GDB_SIG39 51 /* Real-time event 39 */ +#define GDB_SIG40 52 /* Real-time event 40 */ +#define GDB_SIG41 53 /* Real-time event 41 */ +#define GDB_SIG42 54 /* Real-time event 42 */ +#define GDB_SIG43 55 /* Real-time event 43 */ +#define GDB_SIG44 56 /* Real-time event 44 */ +#define GDB_SIG45 57 /* Real-time event 45 */ +#define GDB_SIG46 58 /* Real-time event 46 */ +#define GDB_SIG47 59 /* Real-time event 47 */ +#define GDB_SIG48 60 /* Real-time event 48 */ +#define GDB_SIG49 61 /* Real-time event 49 */ +#define GDB_SIG50 62 /* Real-time event 50 */ +#define GDB_SIG51 63 /* Real-time event 51 */ +#define GDB_SIG52 64 /* Real-time event 52 */ +#define GDB_SIG53 65 /* Real-time event 53 */ +#define GDB_SIG54 66 /* Real-time event 54 */ +#define GDB_SIG55 67 /* Real-time event 55 */ +#define GDB_SIG56 68 /* Real-time event 56 */ +#define GDB_SIG57 69 /* Real-time event 57 */ +#define GDB_SIG58 70 /* Real-time event 58 */ +#define GDB_SIG59 71 /* Real-time event 59 */ +#define GDB_SIG60 72 /* Real-time event 60 */ +#define GDB_SIG61 73 /* Real-time event 61 */ +#define GDB_SIG62 74 /* Real-time event 62 */ +#define GDB_SIG63 75 /* Real-time event 63 */ +#define GDB_SIGCANCEL 76 /* LWP internal signal */ +#define GDB_SIG32 77 /* Real-time event 32 */ +#define GDB_SIG64 78 /* Real-time event 64 */ +#define GDB_SIG65 79 /* Real-time event 65 */ +#define GDB_SIG66 80 /* Real-time event 66 */ +#define GDB_SIG67 81 /* Real-time event 67 */ +#define GDB_SIG68 82 /* Real-time event 68 */ +#define GDB_SIG69 83 /* Real-time event 69 */ +#define GDB_SIG70 84 /* Real-time event 70 */ +#define GDB_SIG71 85 /* Real-time event 71 */ +#define GDB_SIG72 86 /* Real-time event 72 */ +#define GDB_SIG73 87 /* Real-time event 73 */ +#define GDB_SIG74 88 /* Real-time event 74 */ +#define GDB_SIG75 89 /* Real-time event 75 */ +#define GDB_SIG76 90 /* Real-time event 76 */ +#define GDB_SIG77 91 /* Real-time event 77 */ +#define GDB_SIG78 92 /* Real-time event 78 */ +#define GDB_SIG79 93 /* Real-time event 79 */ +#define GDB_SIG80 94 /* Real-time event 80 */ +#define GDB_SIG81 95 /* Real-time event 81 */ +#define GDB_SIG82 96 /* Real-time event 82 */ +#define GDB_SIG83 97 /* Real-time event 83 */ +#define GDB_SIG84 98 /* Real-time event 84 */ +#define GDB_SIG85 99 /* Real-time event 85 */ +#define GDB_SIG86 100 /* Real-time event 86 */ +#define GDB_SIG87 101 /* Real-time event 87 */ +#define GDB_SIG88 102 /* Real-time event 88 */ +#define GDB_SIG89 103 /* Real-time event 89 */ +#define GDB_SIG90 104 /* Real-time event 90 */ +#define GDB_SIG91 105 /* Real-time event 91 */ +#define GDB_SIG92 106 /* Real-time event 92 */ +#define GDB_SIG93 107 /* Real-time event 93 */ +#define GDB_SIG94 108 /* Real-time event 94 */ +#define GDB_SIG95 109 /* Real-time event 95 */ +#define GDB_SIG96 110 /* Real-time event 96 */ +#define GDB_SIG97 111 /* Real-time event 97 */ +#define GDB_SIG98 112 /* Real-time event 98 */ +#define GDB_SIG99 113 /* Real-time event 99 */ +#define GDB_SIG100 114 /* Real-time event 100 */ +#define GDB_SIG101 115 /* Real-time event 101 */ +#define GDB_SIG102 116 /* Real-time event 102 */ +#define GDB_SIG103 117 /* Real-time event 103 */ +#define GDB_SIG104 118 /* Real-time event 104 */ +#define GDB_SIG105 119 /* Real-time event 105 */ +#define GDB_SIG106 120 /* Real-time event 106 */ +#define GDB_SIG107 121 /* Real-time event 107 */ +#define GDB_SIG108 122 /* Real-time event 108 */ +#define GDB_SIG109 123 /* Real-time event 109 */ +#define GDB_SIG110 124 /* Real-time event 110 */ +#define GDB_SIG111 125 /* Real-time event 111 */ +#define GDB_SIG112 126 /* Real-time event 112 */ +#define GDB_SIG113 127 /* Real-time event 113 */ +#define GDB_SIG114 128 /* Real-time event 114 */ +#define GDB_SIG115 129 /* Real-time event 115 */ +#define GDB_SIG116 130 /* Real-time event 116 */ +#define GDB_SIG117 131 /* Real-time event 117 */ +#define GDB_SIG118 132 /* Real-time event 118 */ +#define GDB_SIG119 133 /* Real-time event 119 */ +#define GDB_SIG120 134 /* Real-time event 120 */ +#define GDB_SIG121 135 /* Real-time event 121 */ +#define GDB_SIG122 136 /* Real-time event 122 */ +#define GDB_SIG123 137 /* Real-time event 123 */ +#define GDB_SIG124 138 /* Real-time event 124 */ +#define GDB_SIG125 139 /* Real-time event 125 */ +#define GDB_SIG126 140 /* Real-time event 126 */ +#define GDB_SIG127 141 /* Real-time event 127 */ +#define GDB_SIGINFO 142 /* Information request */ +#define GDB_UNKNOWN 143 /* Unknown signal */ +#define GDB_DEFAULT 144 /* error: default signal */ /* Mach exceptions */ #define GDB_EXC_BAD_ACCESS 145 /* Could not access memory */ #define GDB_EXC_BAD_INSTRCTION 146 /* Illegal instruction/operand */ @@ -404,8 +404,8 @@ void x86_exception(struct eregs *info) case 'G': /* set the value of the CPU registers - return OK */ copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers)); memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); - info->eip = gdb_stub_registers[PC]; - info->cs = gdb_stub_registers[CS]; + info->eip = gdb_stub_registers[PC]; + info->cs = gdb_stub_registers[CS]; info->eflags = gdb_stub_registers[PS]; memcpy(out_buffer, "OK",3); break; @@ -436,8 +436,8 @@ void x86_exception(struct eregs *info) break; case 's': case 'c': - /* cAA..AA Continue at address AA..AA(optional) */ - /* sAA..AA Step one instruction from AA..AA(optional) */ + /* cAA..AA Continue at address AA..AA(optional) */ + /* sAA..AA Step one instruction from AA..AA(optional) */ ptr = &in_buffer[1]; if (parse_ulong(&ptr, &addr)) { info->eip = addr; diff --git a/src/arch/x86/lib/id.inc b/src/arch/x86/lib/id.inc index f8aba0b..389edd8 100644 --- a/src/arch/x86/lib/id.inc +++ b/src/arch/x86/lib/id.inc @@ -11,7 +11,7 @@ part: .long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the vendor id */ .long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the part number */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .globl __id_end
__id_end: diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 7fb25ba..93500f3 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -65,7 +65,7 @@ void clear_ioapic(u32 ioapic_base) io_apic_write(ioapic_base, i * 2 + 0x11, high);
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); + i, high, low); }
if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { @@ -80,9 +80,9 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) int i;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); + ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + bsp_lapicid);
if (ioapic_id) { printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); @@ -95,7 +95,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); for (i = 0; i < 3; i++) printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); + io_apic_read(ioapic_base, i));
}
@@ -114,7 +114,7 @@ static void load_vectors(u32 ioapic_base) */ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); + io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif #if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); @@ -134,7 +134,7 @@ static void load_vectors(u32 ioapic_base) }
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - 0, high, low); + 0, high, low); low = DISABLED; high = NONE; for (i = 1; i < ioapic_interrupts; i++) { @@ -142,7 +142,7 @@ static void load_vectors(u32 ioapic_base) io_apic_write(ioapic_base, i * 2 + 0x11, high);
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); + i, high, low); } }
diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c index 77df4b3..7402c7e 100644 --- a/src/arch/x86/lib/pci_ops_conf1.c +++ b/src/arch/x86/lib/pci_ops_conf1.c @@ -18,7 +18,7 @@ #endif
static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, - int where) + int where) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); return inb(0xCFC + (where & 3)); @@ -39,21 +39,21 @@ static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, }
static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, uint8_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outb(value, 0xCFC + (where & 3)); }
static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, uint16_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outw(value, 0xCFC + (where & 2)); }
static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, uint32_t value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(value, 0xCFC); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4eaf297..1ab069d 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -16,7 +16,7 @@ ((WHERE) & 0xFFF))
static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, - int where) + int where) { return (read8(PCI_MMIO_ADDR(bus, devfn, where))); } @@ -34,19 +34,19 @@ static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, }
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, uint8_t value) { write8(PCI_MMIO_ADDR(bus, devfn, where), value); }
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, uint16_t value) { write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); }
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, uint32_t value) { write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); } diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c index ed2122c..0fd3251 100644 --- a/src/arch/x86/lib/rom_media.c +++ b/src/arch/x86/lib/rom_media.c @@ -85,7 +85,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { #if defined(CONFIG_ROM_SIZE) if (CONFIG_ROM_SIZE != romsize) printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_ROM_SIZE, romsize); + CONFIG_ROM_SIZE, romsize); #endif } media->open = x86_rom_open; diff --git a/src/arch/x86/lib/thread.c b/src/arch/x86/lib/thread.c index 06f8a15..36f2fd7 100644 --- a/src/arch/x86/lib/thread.c +++ b/src/arch/x86/lib/thread.c @@ -42,7 +42,7 @@ static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value) }
void arch_prepare_thread(struct thread *t, - void asmlinkage (*thread_entry)(void *), void *arg) + void asmlinkage (*thread_entry)(void *), void *arg) { uintptr_t stack = t->stack_current;
diff --git a/src/arch/x86/lib/thread_switch.S b/src/arch/x86/lib/thread_switch.S index 8de1948..61a3965 100644 --- a/src/arch/x86/lib/thread_switch.S +++ b/src/arch/x86/lib/thread_switch.S @@ -28,21 +28,21 @@ * +------------+ * | ret addr | <-- esp + 0x20 * +------------+ - * | eax | <-- esp + 0x1c + * | eax | <-- esp + 0x1c * +------------+ - * | ecx | <-- esp + 0x18 + * | ecx | <-- esp + 0x18 * +------------+ - * | edx | <-- esp + 0x14 + * | edx | <-- esp + 0x14 * +------------+ - * | ebx | <-- esp + 0x10 + * | ebx | <-- esp + 0x10 * +------------+ * | orig esp | <-- esp + 0x0c * +------------+ - * | ebp | <-- esp + 0x08 + * | ebp | <-- esp + 0x08 * +------------+ - * | esi | <-- esp + 0x04 + * | esi | <-- esp + 0x04 * +------------+ - * | edi | <-- esp + 0x00 + * | edi | <-- esp + 0x00 * +------------+ */ .globl switch_to_thread diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c index 2c43f5c..b2d42e6 100644 --- a/src/console/cbmem_console.c +++ b/src/console/cbmem_console.c @@ -30,6 +30,6 @@ static void cbmemc_tx_byte_(unsigned char data) }
static const struct console_driver cbmem_console __console = { - .init = cbmemc_init_, + .init = cbmemc_init_, .tx_byte = cbmemc_tx_byte_, }; diff --git a/src/console/console.c b/src/console/console.c index 39a30b5..fe9ef3f 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -97,7 +97,7 @@ int console_tst_byte(void) return 0; }
-#else // __PRE_RAM__ ^^^ NOT defined vvv defined +#else // __PRE_RAM__ ^^^ NOT defined vvv defined
void console_init(void) { diff --git a/src/console/logbuf_console.c b/src/console/logbuf_console.c index a76791d..fb1dd48 100644 --- a/src/console/logbuf_console.c +++ b/src/console/logbuf_console.c @@ -14,7 +14,7 @@ static void logbuf_tx_byte(unsigned char byte) }
static const struct console_driver __console = { - .init = 0, + .init = 0, .tx_byte = logbuf_tx_byte, .rx_byte = 0, .tst_byte = 0, diff --git a/src/console/post.c b/src/console/post.c index 35cc0e8..35c92ba 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -87,7 +87,7 @@ void cmos_post_log(void) break; default: printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); + "in previous boot: 0x%02x\n", code); #if CONFIG_ELOG elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); #if CONFIG_CMOS_POST_EXTRA diff --git a/src/console/qemu_debugcon_console.c b/src/console/qemu_debugcon_console.c index 1d66d87..ee633e9 100644 --- a/src/console/qemu_debugcon_console.c +++ b/src/console/qemu_debugcon_console.c @@ -27,8 +27,8 @@ static void debugcon_init(void) { readback = inb(CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); printk(BIOS_INFO, "QEMU debugcon %s [port 0x%x]\n", - (readback == 0xe9) ? "detected" : "not found", - CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); + (readback == 0xe9) ? "detected" : "not found", + CONFIG_CONSOLE_QEMU_DEBUGCON_PORT); }
static void debugcon_tx_byte(unsigned char data) diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c index 814a1ac..812cd2e 100644 --- a/src/console/spkmodem_console.c +++ b/src/console/spkmodem_console.c @@ -37,7 +37,7 @@ static int spkmodem_tst_byte(void)
static const struct console_driver spkmodem_console __console = { - .init = spkmodem_init, + .init = spkmodem_init, .tx_byte = spkmodem_tx_byte, .tx_flush = spkmodem_tx_flush, .rx_byte = spkmodem_rx_byte, diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..f7dd64c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -47,7 +47,7 @@ static int ttyS0_tst_byte(void) }
static const struct console_driver uart8250_console __console = { - .init = ttyS0_init, + .init = ttyS0_init, .tx_byte = ttyS0_tx_byte, .tx_flush = ttyS0_tx_flush, .rx_byte = ttyS0_rx_byte, diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..340e0b3 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -63,7 +63,7 @@ static int uartmem_tst_byte(void) }
static const struct console_driver uart8250mem_console __console = { - .init = uartmem_init, + .init = uartmem_init, .tx_byte = uartmem_tx_byte, .tx_flush = uartmem_tx_flush, .rx_byte = uartmem_rx_byte, diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index 8df6417..d14ea70 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -53,7 +53,7 @@ static int dbgp_tst_byte(void) }
static const struct console_driver usbdebug_direct_console __console = { - .init = dbgp_init, + .init = dbgp_init, .tx_byte = dbgp_tx_byte, .tx_flush = dbgp_tx_flush, .rx_byte = dbgp_rx_byte, diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index a860f67..b8dc0a9 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -34,13 +34,13 @@ endif # The --entry=0 is just here to suppress the LD warning. It does not affect the # final microcode file. $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) - @printf " LD $(subst $(obj)/,,$(@))\n" + @printf " LD $(subst $(obj)/,,$(@))\n" $(LD) -static --entry=0 $< -o $@
# We have a lot of useless data in the large blob, and we are only interested in # the data section, so we only copy that part to the final microcode file $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o - @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@
ifeq ($(cbfs_include_ucode),y) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..c9006ef 100755 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -50,11 +50,11 @@ config HAVE_INIT_TIMER default y
config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
- Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code.
endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 899a3c4..e929593 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -100,14 +100,14 @@ static struct device_operations cpu_dev_ops = { };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ { 0, 0 }, };
static const struct cpu_driver model_10 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 10d64dd..26b5d20 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -6,13 +6,13 @@ # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. +# notice, this list of conditions and the following disclaimer. # * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. # * Neither the name of Advanced Micro Devices, Inc. nor the names of -# its contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND # ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED @@ -32,7 +32,7 @@ ramstage-y += model_12_init.c
AGESA_ROOT = ../../../../vendorcode/amd/agesa/f12
-agesa_lib_src = $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c +agesa_lib_src = $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 0dae912..fde555e 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -106,14 +106,14 @@ static struct device_operations cpu_dev_ops = { };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */ - { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */ - { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */ - { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */ + { X86_VENDOR_AMD, 0x300f00 }, /* LN1_A0x */ + { X86_VENDOR_AMD, 0x300f01 }, /* LN1_A1x */ + { X86_VENDOR_AMD, 0x300f10 }, /* LN1_B0x */ + { X86_VENDOR_AMD, 0x300f20 }, /* LN2_B0x */ { 0, 0 }, };
static const struct cpu_driver model_12 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 7ae2b24..f3aa6b4 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -126,14 +126,14 @@ static struct device_operations cpu_dev_ops = { };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ { 0, 0 }, };
static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..63b7656 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -71,11 +71,11 @@ config HAVE_INIT_TIMER default y
config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
- Warning: Only enable this option when debuging or tracing AMD AGESA code. + Warning: Only enable this option when debuging or tracing AMD AGESA code.
endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index ea7e663..19a2550 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -107,21 +107,21 @@ static struct device_operations cpu_dev_ops = { };
static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ - { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ - { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ - { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ - { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ - { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ - { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ { 0, 0 }, };
static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index aebc27b..2baee00 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -128,6 +128,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2964b78..041f841 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -128,6 +128,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ef19b53..223c323 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -118,7 +118,7 @@ inline void *backup_resume(void) if (((u32) resume_backup_memory == 0) || ((u32) resume_backup_memory == -1)) { printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", - (u32) resume_backup_memory); + (u32) resume_backup_memory); for (;;) ; }
@@ -135,8 +135,8 @@ void move_stack_high_mem(void)
__asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); + (high_stack - BSP_STACK_BASE_ADDR) + :); }
#ifndef __PRE_RAM__ diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index 5ee4f38..f0d2e28 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -35,8 +35,8 @@ #endif
typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile ///< Volatile Data Type + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type } S3_DATA_TYPE;
void restore_mtrr(void); diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..575eca9 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -194,7 +194,7 @@ clear_fixed_var_mtrr_out: * 0x06 is the WB IO type for a given 4k segment. * 0x1e is the MEM IO type for a given 4k segment (K10 and above). * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. + * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index eca7673..7ea4d22 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -85,7 +85,7 @@ static void post_cache_as_ram(void) /* Check value of esp to verify if we have enough room for stack in Cache as RAM */ unsigned v_esp; __asm__ volatile ( - "movl %%esp, %0\n\t" + "movl %%esp, %0\n\t" : "=a" (v_esp) ); print_debug_pcar("v_esp=", v_esp); @@ -115,7 +115,7 @@ static void post_cache_as_ram(void)
__asm__ volatile ( /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%esp\n\t" + "subl %0, %%esp\n\t" ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) ) /* discard all registers (eax is used for %0), so gcc redoes everything after the stack is moved */ diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index b3df0a3..fb85e8e 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -38,17 +38,17 @@ static int get_max_siblings(int nodes)
static void enable_apic_ext_id(int nodes) { - device_t dev; - int nodeid; - - //enable APIC_EXIT_ID all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ - uint32_t val; - dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); - val = pci_read_config32(dev, 0x68); + device_t dev; + int nodeid; + + //enable APIC_EXIT_ID all the nodes + for(nodeid=0; nodeid<nodes; nodeid++){ + uint32_t val; + dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); + val = pci_read_config32(dev, 0x68); val |= (1<<17)|(1<<18); pci_write_config32(dev, 0x68, val); - } + } }
@@ -59,13 +59,13 @@ unsigned get_apicid_base(unsigned ioapic_num) unsigned apicid_base; int siblings; unsigned nb_cfg_54; - int bsp_apic_id = lapicid(); // bsp apicid + int bsp_apic_id = lapicid(); // bsp apicid
- get_option(&disable_siblings, "multi_core"); + get_option(&disable_siblings, "multi_core");
- //get the nodes number - dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); - nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; + //get the nodes number + dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); + nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
siblings = get_max_siblings(nodes);
@@ -98,9 +98,9 @@ unsigned get_apicid_base(unsigned ioapic_num) and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
- //4:10 for two way 8:12 for four way 16:16 for eight way + //4:10 for two way 8:12 for four way 16:16 for eight way //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency? - apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes; + apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
} else { diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index 69ce56a..7404625 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -18,16 +18,16 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { #if !CONFIG_K8_REV_F_SUPPORT - if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set + if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif
- // set the NB_CFG[54]=1; why the OS will be happy with that ??? - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); + // set the NB_CFG[54]=1; why the OS will be happy with that ??? + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo + wrmsr(NB_CFG_MSR, msr);
- return 1; + return 1; }
static inline void real_start_other_core(unsigned nodeid) @@ -53,9 +53,9 @@ static inline void start_other_cores(void) return; // disable multi_core }
- nodes = get_nodes(); + nodes = get_nodes();
- for(nodeid=0; nodeid<nodes; nodeid++) { + for(nodeid=0; nodeid<nodes; nodeid++) { if( get_core_num_in_bsp(nodeid) > 0) { real_start_other_core(nodeid); } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 5674c49..5924bd8 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -9,9 +9,9 @@ //called by bus_cpu_scan too unsigned int read_nb_cfg_54(void) { - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return ( ( msr.hi >> (54-32)) & 1); + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return ( ( msr.hi >> (54-32)) & 1); }
u32 get_initial_apicid(void) @@ -27,17 +27,17 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) struct node_core_id id; // get the apicid via cpuid(1) ebx[27:24] if( nb_cfg_54) { - // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] - id.coreid = (cpuid_ebx(1) >> 24) & 0xf; - id.nodeid = (id.coreid>>CORE_ID_BIT); - id.coreid &= ((1<<CORE_ID_BIT)-1); - } + // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] + id.coreid = (cpuid_ebx(1) >> 24) & 0xf; + id.nodeid = (id.coreid>>CORE_ID_BIT); + id.coreid &= ((1<<CORE_ID_BIT)-1); + } else { - // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] - id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; - id.coreid = (id.nodeid>>NODE_ID_BIT); - id.nodeid &= ((1<<NODE_ID_BIT)-1); + // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27] + id.nodeid = (cpuid_ebx(1) >> 24) & 0xf; + id.coreid = (id.nodeid>>NODE_ID_BIT); + id.nodeid &= ((1<<NODE_ID_BIT)-1); } return id; } diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..7e3849c 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -39,7 +39,7 @@ /***************************************************************************/ DCacheSetup: /* Save the BIST result */ - movl %eax, %ebx + movl %eax, %ebx
invd /* set cache properties */ @@ -165,22 +165,22 @@ done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
- push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi cld rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi + pop %esi + pop %edi
/* Clear the cache out to ram */ wbinvd /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0
__main: post_code(POST_PREPARE_RAMSTAGE) diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..9441934 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -36,7 +36,7 @@ /***************************************************************************/ DCacheSetup: /* Save the BIST result */ - movl %eax, %ebx + movl %eax, %ebx
invd /* set cache properties */ @@ -189,24 +189,24 @@ DCacheSetupGood: call main done_cache_as_ram_main:
- /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */ + /* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
- push %edi - mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx - push %esi - mov $(CONFIG_DCACHE_RAM_BASE),%edi - mov %edi,%esi - cld - rep movsl %ds:(%esi),%es:(%edi) - pop %esi - pop %edi + push %edi + mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx + push %esi + mov $(CONFIG_DCACHE_RAM_BASE),%edi + mov %edi,%esi + cld + rep movsl %ds:(%esi),%es:(%edi) + pop %esi + pop %edi
/* Clear the cache out to ram */ wbinvd - /* re-enable the cache */ - movl %cr0, %eax - xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ - movl %eax, %cr0 + /* re-enable the cache */ + movl %cr0, %eax + xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */ + movl %eax, %cr0
__main: post_code(POST_PREPARE_RAMSTAGE) diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c index 30d9595..2d2c1c8 100644 --- a/src/cpu/amd/geode_lx/cpureginit.c +++ b/src/cpu/amd/geode_lx/cpureginit.c @@ -49,15 +49,15 @@ static const struct delay_controls { u32 fast_hi; u32 fast_low; } delay_control_table[] = { - /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ - { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, - { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, - { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, - { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, - { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, - { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, - { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, + /* DIMMs Devs Slow (<=333MHz) Fast (>334MHz) */ + { 1, 4, 0x0837100FF, 0x056960004, 0x0827100FF, 0x056960004 }, + { 1, 8, 0x0837100AA, 0x056960004, 0x0827100AA, 0x056960004 }, + { 1, 16, 0x0837100AA, 0x056960004, 0x082710055, 0x056960004 }, + { 2, 8, 0x0837100A5, 0x056960004, 0x082710000, 0x056960004 }, + { 2, 16, 0x0937100A5, 0x056960004, 0x0C27100A5, 0x056960004 }, + { 2, 20, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 24, 0x0B37100A5, 0x056960004, 0x0B27100A5, 0x056960004 }, + { 2, 32, 0x0B37100A5, 0x056960004, 0x0B2710000, 0x056960004 }, };
/* @@ -120,7 +120,7 @@ static void SetDelayControl(u8 dimm0, u8 dimm1, int terminated)
/* Delay Controls based on DIMM loading. UGH! * Number of devices = module width (SPD 6) / device width (SPD 13) - * * physical banks (SPD 5) + * * physical banks (SPD 5) * * Note: We only support a module width of 64. */ @@ -180,7 +180,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated) msr_t msr;
/* Castle 2.0 BTM periodic sync period. */ - /* [40:37] 1 sync record per 256 bytes */ + /* [40:37] 1 sync record per 256 bytes */ print_debug("Castle 2.0 BTM periodic sync period.\n"); msrnum = CPU_PF_CONF; msr = rdmsr(msrnum); diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h index 3d33dda..29edf93 100644 --- a/src/cpu/amd/model_10xxx/defaults.h +++ b/src/cpu/amd/model_10xxx/defaults.h @@ -210,14 +210,14 @@ static const struct {
{ 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1, - [27] NbMcaToMstCpuEn = 1, - [25] DisPciCfgCpuErrRsp = 1, - [21] SyncOnAnyErrEn = 1, - [20] SyncOnWDTEn = 1, - [6] CpuErrDis = 1, - [4] SyncPktPropDis = 1, - [3] SyncPktGenDis = 1, - [2] SyncOnUcEccEn = 1 */ + [27] NbMcaToMstCpuEn = 1, + [25] DisPciCfgCpuErrRsp = 1, + [21] SyncOnAnyErrEn = 1, + [20] SyncOnWDTEn = 1, + [6] CpuErrDis = 1, + [4] SyncPktPropDis = 1, + [3] SyncPktGenDis = 1, + [2] SyncOnUcEccEn = 1 */
/* XBAR buffer settings */ { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL, @@ -306,12 +306,12 @@ static const struct { /* Extended NB MCA Config Register */ { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL, 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7, - [9] SyncOnUncNbAryEn = 1 , - [8] SyncOnProtEn = 1, - [7] SyncFloodOnTgtAbtErr = 1, - [6] SyncFloodOnDatErr = 1, - [5] DisPciCfgCpuMstAbtRsp = 1, - [1] SyncFloodOnUsPwDataErr = 1 */ + [9] SyncOnUncNbAryEn = 1 , + [8] SyncOnProtEn = 1, + [7] SyncFloodOnTgtAbtErr = 1, + [6] SyncFloodOnDatErr = 1, + [5] DisPciCfgCpuMstAbtRsp = 1, + [1] SyncFloodOnUsPwDataErr = 1 */
/* errata 346 - Fam10 C2, C3 * System software should set F3x188[22] to 1b. */ @@ -444,11 +444,11 @@ static const struct {
{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + completeness */
{ 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x00000000, 0x000000FF }, /* Provide clear setting for logical - completeness */ + completeness */
{ 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */ @@ -459,19 +459,19 @@ static const struct { /* Link Phy Receiver Loop Filter Registers */ { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ + [21:14] LfcMin = 10h */
{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3, 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h, - [21:14] LfcMin = 10h */ + [21:14] LfcMin = 10h */
{ 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ + [21:14] LfcMin = 08h */
{ 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1, 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h, - [21:14] LfcMin = 08h */ + [21:14] LfcMin = 08h */
{ 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL, 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h, diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4297c90..e93e9c8 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -31,15 +31,15 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
2.- COF/VID : 2.4.2.9.1 Steps 1,3-6 and warning for 2,7 if they apply - fixPsNbVidBeforeWR(...) + fixPsNbVidBeforeWR(...) 2.4.2.9.1 Step 8 enable_fid_change - We do this for all nodes, I don't understand BKDG 100% on - whether this is or isn't meant by "on the local - processor". Must be OK. + We do this for all nodes, I don't understand BKDG 100% on + whether this is or isn't meant by "on the local + processor". Must be OK. 2.4.2.9.1 Steps 9-10 (repeat 1-7 and reset) romstage.c/init_cpus ? 2.4.2.9.1 Steps 11-12 init_fidvid_stage2 2.4.2.9.2 DualPlane PVI : Not supported, don't know how to detect, - needs specific circuitry. + needs specific circuitry.
3.- 2.4.2.7 dualPlaneOnly(dev)
@@ -52,12 +52,12 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010 b) setVSRamp(), called from prep_fid_change c) prep_fid_change d) improperly, for lack of voltage regulator details?, - F3xA0[PsiVidEn] in defaults.h - F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change) + F3xA0[PsiVidEn] in defaults.h + F3xA0[PsiVid] in init_cpus.c AMD_SetupPSIVID_d (before prep_fid_change)
7.- TODO (Core Performance Boost is only available in revision E cpus, and we - don't seem to support those yet, at least they don't have any - constant in amddefs.h ) + don't seem to support those yet, at least they don't have any + constant in amddefs.h )
8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required @@ -147,7 +147,7 @@ static void enable_fid_change(u8 fid) dword |= 1 << 5; // enable pci_write_config32(dev, 0xd4, dword); printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, - dword); + dword); } }
@@ -161,7 +161,7 @@ static void applyBoostFIDOffset( device_t dev ) { msr_t msr = rdmsr(PS_REG_BASE); u32 cpuFid = msr.lo & PS_CPU_FID_MASK; cpuFid = cpuFid + asymetricBoostThisCore; - msr.lo &= ~PS_CPU_FID_MASK; + msr.lo &= ~PS_CPU_FID_MASK; msr.lo |= cpuFid ; wrmsr(PS_REG_BASE , msr);
@@ -176,10 +176,10 @@ static void enableNbPState1( device_t dev ) { u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; u32 i; for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; msr.lo |= ( nbVid1 << NB_VID_POS); wrmsr(PS_REG_BASE + i, msr); } @@ -191,12 +191,12 @@ static void enableNbPState1( device_t dev ) { static u8 setPStateMaxVal( device_t dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_IDD_VALUE_MASK) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { msr.hi |= PS_EN_MASK ; wrmsr(PS_REG_BASE + i, msr); } - if (msr.hi | PS_EN_MASK) { + if (msr.hi | PS_EN_MASK) { maxpstate = i; } } @@ -217,15 +217,15 @@ static void dualPlaneOnly( device_t dev ) { if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ if (cpuid_edx(0x80000007) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068) ); - wrmsr(0xC0010068,minPstate); + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068) ); + wrmsr(0xC0010068,minPstate); } else { msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr ); + msr.lo=0; msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068) ); + wrmsr(0xC0010068, msr ); }
//FIXME: CPTC2 and HTC_REG should get max per node, not per core ? @@ -254,13 +254,13 @@ static int vidTo100uV(u8 vid)
static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." - * (20 us) ? - * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ - u32 dword; + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." + * (20 us) ? + * Shouldn't it depend on the voltage regulators, mainboard + * or something ? + */ + u32 dword; dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; dword |= VSRAMP_VALUE; @@ -278,12 +278,12 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
/* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() + * (after set AMD MSRs and init ht ) */
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid @@ -299,16 +299,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pviModeFlag = 0;
/* Get P0's voltage */ - /* MSRC001_00[68:64] are not programmed yet when called from + /* MSRC001_00[68:64] are not programmed yet when called from prep_fid_change, one might use F4x1[F0:E0] instead, but theoretically MSRC001_00[68:64] are equal to them after reset. */ msr = rdmsr(0xC0010064); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { + if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) - >> PS_CPU_VID_SHFT) & 0x7F); + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) + >> PS_CPU_VID_SHFT) & 0x7F); }
/* If SVI, we only care about CPU VID. @@ -327,15 +327,15 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue); lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { + if (!(msr.hi & 0x80000000)) { printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue); - lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) - >> PS_CPU_VID_SHFT) & 0x7F); + lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4)) + >> PS_CPU_VID_SHFT) & 0x7F); }
/* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU - * BKDG 2.4.1.7 (a) + * BKDG 2.4.1.7 (a) */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); @@ -351,7 +351,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) if (lowVoltageVid < bValue) lowVoltageVid = bValue;
- u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */
@@ -372,50 +372,50 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) }
static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { - u8 link0isGen3 = 0; - u8 offset; - if (AMD_CpuFindCapability(node, 0, &offset)) { + u8 link0isGen3 = 0; + u8 offset; + if (AMD_CpuFindCapability(node, 0, &offset)) { link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + S1g3 in link Gen3 mode, but I don't know how to tell + package S1g3 from S1g4 */ if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) - && link0isGen3) { + && link0isGen3) { return 5 ; /* divide clk by 128*/ - } else { + } else { return 4 ; /* divide clk by 16 */ - } + } }
static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2));
- if (singleLinkFlag) { + if (singleLinkFlag) { /* - * PowerStepUp=01000b - 50nS + * PowerStepUp=01000b - 50nS * PowerStepDown=01000b - 50ns */ dword |= PW_STP_UP50 | PW_STP_DN50; } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; + u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + u32 isocEn = 0; + int j; for(j=0 ; (j<4) && (!isocEn) ; j++ ) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; } - } + }
- if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { + if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { /* get number of cores for PowerStepUp & PowerStepDown in server 1 core - 400nS - 0000b 2 cores - 200nS - 0010b @@ -439,7 +439,7 @@ static u32 power_up_down(int node, u8 procPkg) { } } } - return dword; + return dword; }
static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { @@ -454,14 +454,14 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { * PowerStepDown= "platform dependent" * LinkPllLink=01b * ClkRampHystCtl=HW default - * ClkRampHystSel=1111b + * ClkRampHystSel=1111b */ - u32 dword= pci_read_config32(dev, 0xd4); + u32 dword= pci_read_config32(dev, 0xd4); dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; - dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT); + dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL; + dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
- dword |= power_up_down(node, procPkg); + dword |= power_up_down(node, procPkg);
pci_write_config32(dev, 0xd4, dword);
@@ -471,32 +471,32 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0);
- /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ - /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */ + /* PllLockTime and PsiVidEn set in ruleset in defaults.h */ if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ dword &= VID_SLAM_OFF ; } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword |= VID_SLAM_ON; - } - /* set the rest of A0 since we're at it... */ + } + /* set the rest of A0 since we're at it... */
- if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { dword |= NB_PSTATE_FORCE_ON; } // else should we clear it ?
- if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { + if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { dword |= BP_INS_TRI_EN_ON ; }
/* TODO: look into C1E state and F3xA0[IdleExitEn]*/ - #if CONFIG_SVI_HIGH_FREQ + #if CONFIG_SVI_HIGH_FREQ if (cpuRev & AMD_FAM10_C3) { dword |= SVI_HIGH_FREQ_ON; - } - #endif + } + #endif pci_write_config32(dev, 0xA0, dword); }
@@ -504,46 +504,46 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ + /* adjust FIFO between nb and core clocks to max allowed + values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; - u8 nbSynPtrAdj; + u8 nbSynPtrAdj; if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { nbSynPtrAdj = 5; } else { - nbSynPtrAdj = 6; + nbSynPtrAdj = 6; }
u32 dword = pci_read_config32(dev, 0xDc); - dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword &= ~ NB_SYN_PTR_ADJ_MASK; dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; - /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); }
static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ - u32 dword; + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + u32 dword; u32 c1= 1; - if (cpuRev & (AMD_DR_Bx)) { - // will coreboot ever enable cache scrubbing ? - // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? - dword = pci_read_config32(dev, 0x58); - u32 scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub + if (cpuRev & (AMD_DR_Bx)) { + // will coreboot ever enable cache scrubbing ? + // if it does, will it be enough to check the current state + // or should we configure for what we'll set up later ? + dword = pci_read_config32(dev, 0x58); + u32 scrubbingCache = dword & + ( (0x1F << 16) // DCacheScrub + | (0x1F << 8) ); // L2Scrub if (scrubbingCache) { - c1 = 0x80; + c1 = 0x80; } else { - c1 = 0xA0; + c1 = 0xA0; } } else { // rev C or later // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xDC); - u32 cacheFlushOnHalt = dword & (7 << 16); - if (!cacheFlushOnHalt) { + dword = pci_read_config32(dev, 0xDC); + u32 cacheFlushOnHalt = dword & (7 << 16); + if (!cacheFlushOnHalt) { c1 = 0x80; } } @@ -551,36 +551,36 @@ static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg pci_write_config32(dev, 0x84, dword);
- /* FIXME: BKDG Table 100 says if the link is at a Gen1 + /* FIXME: BKDG Table 100 says if the link is at a Gen1 frequency and the chipset does not support a 10us minimum LDTSTOP assertion time, then { If ASB2 && SVI then smaf001 = F6h else smaf001=87h. } else ... I hardly know what it means or how to check it from here, so I bluntly assume it is false and code here the else, which is easier */
- u32 smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { + u32 smaf001 = 0xE6; + if (cpuRev & AMD_DR_Bx ) { smaf001 = 0xA6; - } else { - #if CONFIG_SVI_HIGH_FREQ - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; - } - #endif - } - u32 fidvidChange = 0; - if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) + } else { + #if CONFIG_SVI_HIGH_FREQ + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; + } + #endif + } + u32 fidvidChange = 0; + if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) || (cpuRev & AMD_RB_C3) ) { - fidvidChange=0x0B; - } + fidvidChange=0x0B; + } dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; + | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); }
static void prep_fid_change(void) { - u32 dword; + u32 dword; u32 nodes; device_t dev; int i; @@ -592,20 +592,20 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); - u32 cpuRev = mctGetLogicalCPUID(0xFF) ; - u8 procPkg = mctGetProcessorPackageType(); + u32 cpuRev = mctGetLogicalCPUID(0xFF) ; + u8 procPkg = mctGetProcessorPackageType();
setVSRamp(dev); /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev);
- config_clk_power_ctrl_reg0(i,cpuRev,procPkg); + config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
- config_power_ctrl_misc_reg(dev,cpuRev,procPkg); + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev);
- config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); + config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword); @@ -636,7 +636,7 @@ static void waitCurrentPstate(u32 target_pstate){ */ u32 corrected_timeout = ( (pstate_msr.lo==1) && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; + WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; msr_t timeout;
timeout.lo = initial_msr.lo + corrected_timeout ; @@ -650,7 +650,7 @@ static void waitCurrentPstate(u32 target_pstate){ pstate_msr = rdmsr(CUR_PSTATE_MSR); tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); + || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ;
if (pstate_msr.lo != target_pstate) { @@ -673,7 +673,7 @@ static void set_pstate(u32 nonBoostedPState) { wrmsr(0xC0010062, msr);
/* Wait for P0 to set. */ - waitCurrentPstate(nonBoostedPState); + waitCurrentPstate(nonBoostedPState); }
@@ -709,15 +709,15 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) u8 startup_pstate;
/* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. - * Read Pstate register pointed by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems + * Get StartupPstate from MSRC001_0071. + * Read Pstate register pointed by [StartupPstate]. + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. + * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems */
msr = rdmsr(0xc0010071); @@ -731,12 +731,12 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr);
- /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take - * synchronization between cores and we don't think - * PstatMaxVal is going to be 0 on cold reset anyway ? + /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = + * max(1,F3xDC[PstateMaxVal] ) because it would take + * synchronization between cores and we don't think + * PstatMaxVal is going to be 0 on cold reset anyway ? */ - if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); };
@@ -746,13 +746,13 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
if (pviMode) { /* single plane*/ UpdateSinglePlaneNbVid(); - } + }
// Transition to P1 for all APs and P0 for core0. - set_pstate(1); + set_pstate(1);
if (coreid == 0) { - set_pstate(0); + set_pstate(0); }
/* missing step 7 (restore PstateMax to 0 if needed) because @@ -771,11 +771,11 @@ static u32 needs_NB_COF_VID_update(void) nodes = get_nodes(); nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - u32 cpuRev = mctGetLogicalCPUID(i) ; - u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); + u32 cpuRev = mctGetLogicalCPUID(i) ; + u32 nbCofVidUpdateDefined = (cpuRev & (AMD_FAM10_LT_D)); if (nbCofVidUpdateDefined - && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) - & NB_COF_VID_UPDATE_MASK)) { + && (pci_read_config32(NODE_PCI(i, 3), 0x1FC) + & NB_COF_VID_UPDATE_MASK)) { nb_cof_vid_update = 1; break; } @@ -801,11 +801,11 @@ static u32 init_fidvid_core(u32 nodeid, u32 coreid) reg1fc = pci_read_config32(dev, 0x1FC);
if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ; + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT ; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT ;
- if (!pvimode) { /* SVI, dual power plane */ - vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); + if (!pvimode) { /* SVI, dual power plane */ + vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); } /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ @@ -829,7 +829,7 @@ static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid)
printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
- send = init_fidvid_core(nodeid,coreid); + send = init_fidvid_core(nodeid,coreid); send |= (apicid << 24); // ap apicid
// Send signal to BSP about this AP max fid @@ -879,7 +879,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
if (timeout) { printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", - __func__, ap_apicid); + __func__, ap_apicid); return; }
@@ -898,7 +898,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) u8 StartupPstate;
/* BKDG 2.4.2.9.1 11-12 - * This function copies newNbVid to NbVid bits in P-state + * This function copies newNbVid to NbVid bits in P-state * Registers[4:0] if its NbDid bit=0, and IddValue!=0 in case of * NbVidUpdatedAll =0 or copies newNbVid to NbVid bits in * P-state Registers[4:0] if its IddValue!=0 in case of @@ -909,27 +909,27 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ( (msr.hi & PS_IDD_VALUE_MASK) - && (msr.hi & PS_EN_MASK) - &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { + if ( (msr.hi & PS_IDD_VALUE_MASK) + && (msr.hi & PS_EN_MASK) + &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { msr.lo &= PS_NB_VID_M_OFF; msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT; wrmsr(0xC0010064 + i, msr); } }
- /* Not documented. Would overwrite Nb_Vids just copied - * should we just update cpu_vid or nothing at all ? + /* Not documented. Would overwrite Nb_Vids just copied + * should we just update cpu_vid or nothing at all ? */ if (pviMode) { //single plane - UpdateSinglePlaneNbVid(); + UpdateSinglePlaneNbVid(); } /* For each core in the system, transition all cores to StartupPstate */ msr = rdmsr(0xC0010071); StartupPstate = msr.hi & 0x07;
/* Set and wait for StartupPstate to set. */ - set_pstate(StartupPstate); + set_pstate(StartupPstate);
}
@@ -979,9 +979,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp);
- dualPlaneOnly(dev); - applyBoostFIDOffset(dev); - enableNbPState1(dev); + dualPlaneOnly(dev); + applyBoostFIDOffset(dev); + enableNbPState1(dev);
finalPstateChange();
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index eb047b8..fd72881 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -165,8 +165,8 @@ void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { printk(BIOS_DEBUG, - "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, - apicid, id.nodeid, id.coreid); + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); }
static u32 wait_cpu_state(u32 apicid, u32 state) @@ -308,7 +308,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (cpu_init_detectedx) { print_apicid_nodeid_coreid(apicid, id, - "\n\n\nINIT detected from "); + "\n\n\nINIT detected from "); printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); } @@ -339,13 +339,13 @@ static u32 init_cpus(u32 cpu_init_detectedx) // check warm(bios) reset to call stage2 otherwise do stage1 if (warm_reset_detect(id.nodeid)) { printk(BIOS_DEBUG, - "init_fidvid_stage2 apicid: %02x\n", - apicid); + "init_fidvid_stage2 apicid: %02x\n", + apicid); init_fidvid_stage2(apicid, id.nodeid); } else { printk(BIOS_DEBUG, - "init_fidvid_ap(stage1) apicid: %02x\n", - apicid); + "init_fidvid_ap(stage1) apicid: %02x\n", + apicid); init_fidvid_ap(apicid, id.nodeid, id.coreid); } } @@ -357,8 +357,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) STOP_CAR_AND_CPU();
printk(BIOS_DEBUG, - "\nAP %02x should be halted but you are reading this....\n", - apicid); + "\nAP %02x should be halted but you are reading this....\n", + apicid); }
return bsp_apicid; @@ -480,7 +480,7 @@ static void AMD_Errata281(u8 node, u32 revision, u32 platform) if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { for (i = 0; i < nodes; i++) { if (mctGetLogicalCPUID(i) & - (AMD_DR_B0 | AMD_DR_B1)) { + (AMD_DR_B0 | AMD_DR_B1)) { mixed = 1; break; } @@ -822,9 +822,9 @@ static void cpuSetAMDPCI(u8 node) val &= ~fam10_pci_default[i].mask; val |= fam10_pci_default[i].data; pci_write_config32(NODE_PCI(node, - fam10_pci_default[i]. - function), - fam10_pci_default[i].offset, val); + fam10_pci_default[i]. + function), + fam10_pci_default[i].offset, val); } }
@@ -839,7 +839,7 @@ static void cpuSetAMDPCI(u8 node) for (j = 0; j < 4; j++) { if (AMD_CpuFindCapability(node, j, &offset)) { if (AMD_checkLinkType(node, j, offset) - & fam10_htphy_default[i].linktype) { + & fam10_htphy_default[i].linktype) { AMD_SetHtPhyRegister(node, j, i); } diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000086.h b/src/cpu/amd/model_10xxx/mc_patch_01000086.h index d538036..f5f6f67 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000086.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000086.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000095.h b/src/cpu/amd/model_10xxx/mc_patch_01000095.h index bfb2e10..54f27e8 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000095.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000095.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_01000096.h b/src/cpu/amd/model_10xxx/mc_patch_01000096.h index e45bdf5..705e67b 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_01000096.h +++ b/src/cpu/amd/model_10xxx/mc_patch_01000096.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_0100009f.h b/src/cpu/amd/model_10xxx/mc_patch_0100009f.h index d59f138..f20d852 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_0100009f.h +++ b/src/cpu/amd/model_10xxx/mc_patch_0100009f.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000b6.h b/src/cpu/amd/model_10xxx/mc_patch_010000b6.h index 934ef16..e010789 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000b6.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000b6.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h index 9baaa9b..393eabb 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h @@ -6,20 +6,20 @@ Microprocessors. You may copy, view and install the enclosed microcode only for development and deployment of firmware, BIOS, or operating system code for computer - systems that contain AMD processors. You are not + systems that contain AMD processors. You are not authorized to use the enclosed microcode for any other purpose.
THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO - WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. AMD does not assume any responsibility for any errors which - may appear in this microcode or any other related + may appear in this microcode or any other related information provided to you by AMD, or result from use of this microcode. AMD is not obligated to furnish, support, - or make any further information, software, technical + or make any further information, software, technical information, know-how, or show-how available related to this microcode.
@@ -27,7 +27,7 @@ duplication, or disclosure by the U.S. Government is subject to the restrictions as set forth in FAR 52.227-14 and DFAR252.227-7013, et seq., or its successor. Use of the - microcode by the U.S. Government constitutes + microcode by the U.S. Government constitutes acknowledgement of AMD's proprietary rights in them. ============================================================ */ diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000c4.h b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h index 1ff8aa1..3e9c343 100644 --- a/src/cpu/amd/model_10xxx/mc_patch_010000c4.h +++ b/src/cpu/amd/model_10xxx/mc_patch_010000c4.h @@ -7,13 +7,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..18b333e 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -130,18 +130,18 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x100f22 }, { X86_VENDOR_AMD, 0x100f23 }, { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */ - { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ - { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ - { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ - { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ - { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ - { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ - { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ - { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ + { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */ + { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */ + { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */ + { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */ + { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */ + { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100FA0 }, /* PH-E0 */ { 0, 0 }, };
static const struct cpu_driver model_10xxx __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/model_10xxx/processor_name.c b/src/cpu/amd/model_10xxx/processor_name.c index b16e9ba..c7f1d3d 100644 --- a/src/cpu/amd/model_10xxx/processor_name.c +++ b/src/cpu/amd/model_10xxx/processor_name.c @@ -258,7 +258,7 @@ int init_processor_name(void) goto done;
j = strcpymax(program_string, processor_name_string, - sizeof(program_string)); + sizeof(program_string));
/* Translate Model from 01-99 to ASCII and put it on the end. * Numbers less than 10 should include a leading zero, e.g., 09.*/ diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c index cc08cdc..269876d 100644 --- a/src/cpu/amd/model_10xxx/update_microcode.c +++ b/src/cpu/amd/model_10xxx/update_microcode.c @@ -36,22 +36,22 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = { /* From the Revision Guide : * Equivalent Processor Table for AMD Family 10h Processors * - * Installed Processor Equivalent Processor Patch Level - * Revision ID Revision ID - * 00100F00h 1000h 01000020h - * 00100F01h 1000h 01000020h - * 00100F02h 1000h 01000020h - * 00100F20h 1020h 01000096h - * 00100F21h (DR-B1) 1020h 01000096h - * 00100F2Ah (DR-BA) 1020h 01000096h - * 00100F22h (DR-B2) 1022h 01000095h - * 00100F23h (DR-B3) 1022h 01000095h - * 00100F42h (RB-C2) 1041h 01000086h - * 00100F43h (RB-C3) 1043h 010000b6h - * 00100F62h (DA-C2) 1062h 0100009Fh - * 00100F63h (DA-C3) 1043h 010000b6h - * 00100F81h (HY-D1) 1081h 010000c4h - * 00100FA0h (PH-E0) 10A0h 010000bfh + * Installed Processor Equivalent Processor Patch Level + * Revision ID Revision ID + * 00100F00h 1000h 01000020h + * 00100F01h 1000h 01000020h + * 00100F02h 1000h 01000020h + * 00100F20h 1020h 01000096h + * 00100F21h (DR-B1) 1020h 01000096h + * 00100F2Ah (DR-BA) 1020h 01000096h + * 00100F22h (DR-B2) 1022h 01000095h + * 00100F23h (DR-B3) 1022h 01000095h + * 00100F42h (RB-C2) 1041h 01000086h + * 00100F43h (RB-C3) 1043h 010000b6h + * 00100F62h (DA-C2) 1062h 0100009Fh + * 00100F63h (DA-C3) 1043h 010000b6h + * 00100F81h (HY-D1) 1081h 010000c4h + * 00100FA0h (PH-E0) 10A0h 010000bfh */
#include CONFIG_AMD_UCODE_PATCH_FILE diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index e68611b..8584fd3 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -60,7 +60,7 @@ static void enable_fid_change(void) #endif
dword = 0x23070700; /* enable FID/VID change */ -// dword = 0x00070000; /* enable FID/VID change */ +// dword = 0x00070000; /* enable FID/VID change */ pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword);
#if CONFIG_HAVE_ACPI_RESUME @@ -94,14 +94,14 @@ static unsigned set_fidvid_without_init(unsigned fidvid) static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) {
-/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... - * -------------------------------------- +/* CurrentFID--> 4x(00h) 5x(02h) 6x(04h) 7x(06h) ... + * -------------------------------------- * TargetFID | Next_FID, Next_FID, Next_FID, Next_FID ... - * | | Next_FID, Next_FID, Next_FID, Next_FID ... + * | | Next_FID, Next_FID, Next_FID, Next_FID ... * |/ | Next_FID, Next_FID, Next_FID, Next_FID ... */ static const u8 next_fid_200[] = { -/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ +/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 */ /* x4 */ 0, -1, -1, -1, 0, 0, 9, 10, 11, 12, 13, 14, 15, /* 800 */ /* x5 */ -1, 0, -1, -1, -1, 5, 5, 5, 11, 12, 13, 14, 15, /* 1000 */ /* x6 */ -1, -1, 0, -1, -1, -1, -1, 6, 6, 6, 13, 14, 15, /* 1200 */ @@ -134,8 +134,8 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if (apicid != apicidx) { printk(BIOS_ERR, - "wrong apicid, we want change %x, but it is %x\n", - apicid, apicidx); + "wrong apicid, we want change %x, but it is %x\n", + apicid, apicidx); return fidvid; }
@@ -166,12 +166,12 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) /* TODO - make this more correct. Not a big deal for setting max... * BKDG figure 11 * if TargetFID > InitialFID - * TargetVID = FinalVID - RVO + * TargetVID = FinalVID - RVO * else - * if CurrentVID > FinalVID - * TargetVID = FinalVID - RVO - * else - * TargetVID = CurrentVIDD - RVO + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); @@ -205,7 +205,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) */
printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, - fid_max); + fid_max); printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
step_limit = 8; /* max 8 steps just in case... */ @@ -262,7 +262,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
if (fid_temp > fid_max) { printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", - fid_temp, fid_max); + fid_temp, fid_max); break; }
@@ -333,11 +333,11 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage) if (showmessage) { if (vid_new != vid_cur) { printk(BIOS_ERR, "set vid failed for apicid =%02x\n", - apicidx); + apicidx); } if (fid_new != fid_cur) { printk(BIOS_ERR, "set fid failed for apicid =%02x\n", - apicidx); + apicidx); } }
@@ -388,13 +388,13 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) timeout = wait_cpu_state(bsp_apicid, 1); if (timeout) { printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading" - " from BSP on %02x\n", apicid); + " from BSP on %02x\n", apicid); } /* send signal to BSP about this AP max fid and vid */ /* AP at state 1 that sent our fid and vid */ lapic_write(LAPIC_MSG_REG, send | 1);
-// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ +// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ loop = 1000000; while (--loop > 0) { /* remote read BSP signal that include vid/fid that need to set */ @@ -417,7 +417,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) send = (apicid << 24) | (readback & 0x00ffff00); } else { printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", - __func__, apicid); + __func__, apicid); }
lapic_write(LAPIC_MSG_REG, send | 2); @@ -425,7 +425,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) timeout = wait_cpu_state(bsp_apicid, 3); if (timeout) { printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", - __func__, apicid); + __func__, apicid); } }
@@ -466,7 +466,7 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
if (timeout) { printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", - __func__, ap_apicid); + __func__, ap_apicid); return; }
@@ -502,7 +502,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
if (timeout) { printk(BIOS_DEBUG, "%s: time out while reading from ap %02x", - __func__, ap_apicid); + __func__, ap_apicid); return; }
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 7121642..642785c 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -128,8 +128,8 @@ void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) { printk(BIOS_DEBUG, - "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, - apicid, id.nodeid, id.coreid); + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); }
static u32 wait_cpu_state(u32 apicid, u32 state) @@ -221,7 +221,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) }
enable_lapic(); - // init_timer(); // We need TMICT to pass msg for FID/VID change + // init_timer(); // We need TMICT to pass msg for FID/VID change
#if CONFIG_ENABLE_APIC_EXT_ID u32 initial_apicid = get_initial_apicid(); @@ -259,14 +259,14 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (cpu_init_detectedx) { print_apicid_nodeid_coreid(apicid, id, - "\n\n\nINIT detected from "); + "\n\n\nINIT detected from "); printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); }
if (id.coreid == 0) { distinguish_cpu_resets(id.nodeid); -// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set +// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started @@ -288,8 +288,8 @@ static u32 init_cpus(u32 cpu_init_detectedx) } if (timeout) { printk(BIOS_DEBUG, - "while waiting for BSP signal to STOP, timeout in ap %02x\n", - apicid); + "while waiting for BSP signal to STOP, timeout in ap %02x\n", + apicid); } lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 42c6f95..d74c3dc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -32,9 +32,9 @@ void cpus_ready_for_init(void) { #if CONFIG_MEM_TRAIN_SEQ == 1 - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); - // wait for ap memory to trained - wait_all_core0_mem_trained(sysinfox); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); + // wait for ap memory to trained + wait_all_core0_mem_trained(sysinfox); #endif } #endif @@ -129,16 +129,16 @@ static void print_mtrr_state(struct mtrr_state *state) int i; for (i = 0; i < MTRR_COUNT; i++) { printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n", - i, - state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, - state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); + i, + state->mtrrs[i].base.hi, state->mtrrs[i].base.lo, + state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo); } printk(BIOS_DEBUG, "top_mem: %08x%08x\n", - state->top_mem.hi, state->top_mem.lo); + state->top_mem.hi, state->top_mem.lo); printk(BIOS_DEBUG, "top_mem2: %08x%08x\n", - state->top_mem2.hi, state->top_mem2.lo); + state->top_mem2.hi, state->top_mem2.lo); printk(BIOS_DEBUG, "def_type: %08x%08x\n", - state->def_type.hi, state->def_type.lo); + state->def_type.hi, state->def_type.lo); } #endif
@@ -621,6 +621,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver model_fxx __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index f1747d9..082b706 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -36,36 +36,36 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { #if CONFIG_K8_REV_F_SUPPORT // #include "microcode_rev_f.h" #endif - /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) { static unsigned id_mapping_table[] = { #if !CONFIG_K8_REV_F_SUPPORT - 0x0f48, 0x0048, - 0x0f58, 0x0048, - - 0x0f4a, 0x004a, - 0x0f5a, 0x004a, - 0x0f7a, 0x004a, - 0x0f82, 0x004a, - 0x0fc0, 0x004a, - 0x0ff0, 0x004a, - - 0x10f50, 0x0150, - 0x10f70, 0x0150, - 0x10f80, 0x0150, - 0x10fc0, 0x0150, - 0x10ff0, 0x0150, - - 0x20f10, 0x0210, - 0x20f12, 0x0210, - 0x20f32, 0x0210, - 0x20fb1, 0x0210, + 0x0f48, 0x0048, + 0x0f58, 0x0048, + + 0x0f4a, 0x004a, + 0x0f5a, 0x004a, + 0x0f7a, 0x004a, + 0x0f82, 0x004a, + 0x0fc0, 0x004a, + 0x0ff0, 0x004a, + + 0x10f50, 0x0150, + 0x10f70, 0x0150, + 0x10f80, 0x0150, + 0x10fc0, 0x0150, + 0x10ff0, 0x0150, + + 0x20f10, 0x0210, + 0x20f12, 0x0210, + 0x20f32, 0x0210, + 0x20fb1, 0x0210, #endif
#if CONFIG_K8_REV_F_SUPPORT @@ -93,8 +93,8 @@ void model_fxx_update_microcode(unsigned cpu_deviceid) { unsigned equivalent_processor_rev_id;
- /* Update the microcode */ + /* Update the microcode */ equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid ); if(equivalent_processor_rev_id != 0) - amd_update_microcode(microcode_updates, equivalent_processor_rev_id); + amd_update_microcode(microcode_updates, equivalent_processor_rev_id); } diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index af1e24b..b5e5bf6 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -209,9 +209,9 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) fid_multiplier = 100;
/* - * Formula1: CPUFreq = FID * fid_multiplier + 800 - * Formula2: CPUVolt = 1550 - VID * 25 (mv) - * Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2)) + * Formula1: CPUFreq = FID * fid_multiplier + 800 + * Formula2: CPUVolt = 1550 - VID * 25 (mv) + * Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2)) */
/* Construct P0(P[Max]) state */ @@ -310,8 +310,8 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * - Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0] * + Pstate_volt[0]); } Pstate_num++; } @@ -327,7 +327,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0]); Pstate_num++; } else { Pstate_fid[Pstate_num] = Start_fid; @@ -339,7 +339,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) (unsigned long long)Pstate_power[0] * Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] * Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] * - Pstate_volt[0]); + Pstate_volt[0]); Pstate_num++; }
@@ -846,9 +846,9 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
for (i=0;i<Pstate_num;i++) printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, - Pstate_feq[i], - vid_from_reg(Pstate_vid[i]), - Pstate_power[i]); + Pstate_feq[i], + vid_from_reg(Pstate_vid[i]), + Pstate_power[i]);
/* Loop over all CPU's */ for (dev = 0x18; dev < 0x1c; dev++) { diff --git a/src/cpu/amd/sc520/raminit.c b/src/cpu/amd/sc520/raminit.c index f3f7071..fb5d905 100644 --- a/src/cpu/amd/sc520/raminit.c +++ b/src/cpu/amd/sc520/raminit.c @@ -1,22 +1,22 @@ /* this setupcpu function comes from: */ /*==============================================================================*/ -/* FILE : start16.asm*/ +/* FILE : start16.asm*/ /**/ -/* DESC : A 16 bit mode assembly language startup program, intended for*/ -/* use with on Aspen SC520 platforms.*/ +/* DESC : A 16 bit mode assembly language startup program, intended for*/ +/* use with on Aspen SC520 platforms.*/ /**/ /* 11/16/2000 Added support for the NetSC520*/ /* 12/28/2000 Modified to boot linux image*/ /**/ /* =============================================================================*/ -/* */ -/* Copyright 2000 Advanced Micro Devices, Inc. */ -/* */ +/* */ +/* Copyright 2000 Advanced Micro Devices, Inc. */ +/* */ /* This software is the property of Advanced Micro Devices, Inc (AMD) which */ /* specifically grants the user the right to modify, use and distribute this */ /* software provided this COPYRIGHT NOTICE is not removed or altered. All */ -/* other rights are reserved by AMD. */ -/* */ +/* other rights are reserved by AMD. */ +/* */ /* THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY */ /* OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF */ /* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.*/ @@ -36,26 +36,26 @@ /* So that all may benefit from your experience, please report any problems */ /* or suggestions about this software back to AMD. Please include your name, */ /* company, telephone number, AMD product requiring support and question or */ -/* problem encountered. */ -/* */ -/* Advanced Micro Devices, Inc. Worldwide support and contact */ -/* Embedded Processor Division information available at: */ -/* Systems Engineering epd.support@amd.com*/ -/* 5204 E. Ben White Blvd. -or-*/ -/* Austin, TX 78741 http://www.amd.com/html/support/techsup.html*/ +/* problem encountered. */ +/* */ +/* Advanced Micro Devices, Inc. Worldwide support and contact */ +/* Embedded Processor Division information available at: */ +/* Systems Engineering epd.support@amd.com*/ +/* 5204 E. Ben White Blvd. -or-*/ +/* Austin, TX 78741 http://www.amd.com/html/support/techsup.html*/ /* ============================================================================*/
#define OUTC(addr, val) *(unsigned char *)(addr) = (val)
/* sadly, romcc can't quite handle what we want, so we do this ugly thing */ -#define drcctl (( volatile unsigned char *)0xfffef010) -#define drcmctl (( volatile unsigned char *)0xfffef012) -#define drccfg (( volatile unsigned char *)0xfffef014) +#define drcctl (( volatile unsigned char *)0xfffef010) +#define drcmctl (( volatile unsigned char *)0xfffef012) +#define drccfg (( volatile unsigned char *)0xfffef014)
#define drcbendadr (( volatile unsigned long *)0xfffef018) -#define eccctl (( volatile unsigned char *)0xfffef020) -#define dbctl (( volatile unsigned char *)0xfffef040) +#define eccctl (( volatile unsigned char *)0xfffef020) +#define dbctl (( volatile unsigned char *)0xfffef040)
void setupsc520(void) { @@ -341,7 +341,7 @@ int sizemem(void) if (*lp != 0xdeadbeef) { print_err(" no memory at bank "); // print_err_hex8(bank); - // print_err(" value "); print_err_hex32(*lp); + // print_err(" value "); print_err_hex32(*lp); print_err("\n"); // continue; } diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 808c33c..6778fa9 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -37,13 +37,13 @@ static void sc520_enable_resources(struct device *dev) { unsigned char command;
printk(BIOS_SPEW, "%s\n", __func__); - command = pci_read_config8(dev, PCI_COMMAND); - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); - command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); - pci_write_config8(dev, PCI_COMMAND, command); - command = pci_read_config8(dev, PCI_COMMAND); - printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + command = pci_read_config8(dev, PCI_COMMAND); + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR; + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); + pci_write_config8(dev, PCI_COMMAND, command); + command = pci_read_config8(dev, PCI_COMMAND); + printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command); /* */
@@ -70,11 +70,11 @@ static void sc520_read_resources(device_t dev)
static struct device_operations cpu_operations = { .read_resources = sc520_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = sc520_enable_resources, - .init = cpu_init, - .enable = 0, - .ops_pci = 0, + .init = cpu_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver cpu_driver __pci_driver = { @@ -86,9 +86,9 @@ static const struct pci_driver cpu_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); - pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; @@ -150,18 +150,18 @@ void sc520_enable_resources(device_t dev) { #endif
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, /* * If enable_resources is set to the generic enable_resources * function the whole thing will hang in an endless loop on * the ts5300. If this is really needed on another platform, * something is conceptually wrong. */ - .enable_resources = 0, //enable_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .enable_resources = 0, //enable_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
#if 0 @@ -175,28 +175,28 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, }; #endif
static void enable_dev(struct device *dev) { printk(BIOS_SPEW, "%s\n", __func__); - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } #if 0 /* This is never hit as none of the sc520 boards have * an APIC cluster defined */ - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } #endif }
diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig index 2943b91..16047df 100644 --- a/src/cpu/amd/socket_S1G1/Kconfig +++ b/src/cpu/amd/socket_S1G1/Kconfig @@ -1,5 +1,5 @@ config CPU_AMD_SOCKET_S1G1 - bool + bool
if CPU_AMD_SOCKET_S1G1
diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 055fffe..4d8c503 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -19,19 +19,19 @@
.section ".dmp_reserved", "a", @progbits
- .skip 0x3c000 - 0x3bc00, 0xff + .skip 0x3c000 - 0x3bc00, 0xff
.previous
.section ".dmp_kbd_fw_part2", "a", @progbits
- .skip 0x3d000 - 0x3c000, 0xff + .skip 0x3d000 - 0x3c000, 0xff
.previous
.section ".dmp_mtbf_low_cnt", "a", @progbits
- .skip 0x3e000 - 0x3d000, 0xff + .skip 0x3e000 - 0x3d000, 0xff
.previous
@@ -43,42 +43,42 @@
.section ".dmp_spi_flash_disk_driver", "a", @progbits
- .skip 0x3f800 - 0x3f000, 0xff + .skip 0x3f800 - 0x3f000, 0xff
.previous
.section ".dmp_frontdoor", "a", @progbits
- .skip 0x3fd00 - 0x3f800, 0xff + .skip 0x3fd00 - 0x3f800, 0xff
.previous
.section ".dmp_isoinfo", "a", @progbits
- .skip 26 * 16, 0xff + .skip 26 * 16, 0xff
.previous
.section ".dmp_isodata_checksum", "a", @progbits
- .skip 8, 0xff + .skip 8, 0xff
.previous
.section ".dmp_mac", "a", @progbits
- .skip 6, 0xff + .skip 6, 0xff
.previous
.section ".dmp_mtbf_limit", "a", @progbits
- .skip 3, 0xff + .skip 3, 0xff
.previous
.section ".dmp_isodata", "a", @progbits
- .skip 32, 0xff + .skip 32, 0xff
.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc index 4a2478e..02805fb 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.inc @@ -25,27 +25,27 @@ CPU Freq = PLL/(CPU_DIV+2) DRAM Freq = PLL/2(DRAM_DIV+1)
DDR3 -CPU/DRAM/PCI B6 B7 BB BC BD BF -200/200/33 30 03 0F 02 8F 07 -300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable -300/300/100 48 03 23 02 7F 07 -400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing -400/200/100 60 43 23 02 4F 07 -400/400/33 60 03 0F 02 BF 09 -500/250/33 50 42 0F 02 DF 07 -500/500/33 78 03 0F 02 4F 09 -400/300/33 90 53 0F 02 3F 07 -400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable -400/300/100 90 53 23 02 9F 07 -444/333/33 A0 53 0F 02 5F 08 -466/350/33 A8 53 0F 02 DF 09 -500/375/33 B4 53 0F 02 AF 09 +CPU/DRAM/PCI B6 B7 BB BC BD BF +200/200/33 30 03 0F 02 8F 07 +300/300/33 48 03 0F 02 1F 07 +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable +300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/100 48 03 23 02 7F 07 +400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing +400/200/100 60 43 23 02 4F 07 +400/400/33 60 03 0F 02 BF 09 +500/250/33 50 42 0F 02 DF 07 +500/500/33 78 03 0F 02 4F 09 +400/300/33 90 53 0F 02 3F 07 +400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable +400/300/100 90 53 23 02 9F 07 +444/333/33 A0 53 0F 02 5F 08 +466/350/33 A8 53 0F 02 DF 09 +500/375/33 B4 53 0F 02 AF 09 */
#if CONFIG_PLL_200_200_33 - // 200/200/33 30 03 0F 02 8F 07 + // 200/200/33 30 03 0F 02 8F 07 byte_fffb6 = 0x30 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -53,7 +53,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_300_300_33 - // 300/300/33 48 03 0F 02 1F 07 + // 300/300/33 48 03 0F 02 1F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -61,7 +61,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_300_300_100 - // 300/300/100 48 03 23 02 7F 07 + // 300/300/100 48 03 23 02 7F 07 byte_fffb6 = 0x48 byte_fffb7 = 0x03 byte_fffbb = 0x23 @@ -69,7 +69,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_200_33 - // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing + // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing byte_fffb6 = 0x60 byte_fffb7 = 0x43 byte_fffbb = 0x0f @@ -77,7 +77,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_200_100 - // 400/200/100 60 43 23 02 4F 07 + // 400/200/100 60 43 23 02 4F 07 byte_fffb6 = 0x60 byte_fffb7 = 0x43 byte_fffbb = 0x23 @@ -85,7 +85,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_400_33 - // 400/400/33 60 03 0F 02 BF 09 + // 400/400/33 60 03 0F 02 BF 09 byte_fffb6 = 0x60 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -93,7 +93,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_500_250_33 - // 500/250/33 50 42 0F 02 DF 07 + // 500/250/33 50 42 0F 02 DF 07 byte_fffb6 = 0x50 byte_fffb7 = 0x42 byte_fffbb = 0x0f @@ -101,7 +101,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_500_500_33 - // 500/500/33 78 03 0F 02 4F 09 + // 500/500/33 78 03 0F 02 4F 09 byte_fffb6 = 0x78 byte_fffb7 = 0x03 byte_fffbb = 0x0f @@ -109,7 +109,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_400_300_33 - // 400/300/33 90 53 0F 02 3F 07 + // 400/300/33 90 53 0F 02 3F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -117,7 +117,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_400_300_100 - // 400/300/100 90 53 23 02 9F 07 + // 400/300/100 90 53 23 02 9F 07 byte_fffb6 = 0x90 byte_fffb7 = 0x53 byte_fffbb = 0x23 @@ -125,7 +125,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x07 #elif CONFIG_PLL_444_333_33 - // 444/333/33 A0 53 0F 02 5F 08 + // 444/333/33 A0 53 0F 02 5F 08 byte_fffb6 = 0xa0 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -133,7 +133,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x08 #elif CONFIG_PLL_466_350_33 - // 466/350/33 A8 53 0F 02 DF 09 + // 466/350/33 A8 53 0F 02 DF 09 byte_fffb6 = 0xa8 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -141,7 +141,7 @@ CPU/DRAM/PCI B6 B7 BB BC BD BF byte_fffbe = 0xff byte_fffbf = 0x09 #elif CONFIG_PLL_500_375_33 - // 500/375/33 B4 53 0F 02 AF 09 + // 500/375/33 B4 53 0F 02 AF 09 byte_fffb6 = 0xb4 byte_fffb7 = 0x53 byte_fffbb = 0x0f @@ -159,7 +159,7 @@ byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f
.section ".a9123_crossbar_config", "a", @progbits
- .skip 0x3fdf0 - 0x3fd00, 0xff + .skip 0x3fdf0 - 0x3fd00, 0xff
.previous
diff --git a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc index 486bf1b..0d9d64d 100644 --- a/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +++ b/src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc @@ -17,515 +17,515 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
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0xed, 0x80, 0x01, 0xee, 0xf0, 0x44 + .byte 0x20, 0xf0, 0xdc, 0xf1, 0x22, 0x12, 0x0f, 0x04 + .byte 0x8e, 0x39, 0x8f, 0x3a, 0x12, 0x0f, 0x1d, 0x8f + .byte 0x38, 0xe5, 0x38, 0x30, 0xe1, 0x03, 0x43, 0x39 + .byte 0x80, 0xe5, 0x38, 0x13, 0x13, 0x54, 0x3f, 0xf5 + .byte 0x38, 0x22, 0x53, 0x1a, 0xef, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x7f, 0x05, 0x12, 0x0c, 0xd0 + .byte 0x12, 0x0b, 0xd7, 0x43, 0x1a, 0x10, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0xc8 + .byte 0x12, 0x0e, 0xd4, 0x90, 0xd0, 0x00, 0xe0, 0x20 + .byte 0xe1, 0x08, 0x12, 0x03, 0x6c, 0x12, 0x01, 0x05 + .byte 0x80, 0xf1, 0x22, 0x12, 0x0c, 0xed, 0x12, 0x08 + .byte 0xf2, 0xe5, 0x09, 0x70, 0x0b, 0xe5, 0x0a, 0x70 + .byte 0x07, 0xe5, 0x0b, 0x70, 0x03, 0x12, 0x0e, 0xda + .byte 0x22, 0x8d, 0x31, 0x8b, 0x32, 0x12, 0x0c, 0xd0 + .byte 0xaf, 0x31, 0x12, 0x0c, 0xd0, 0xaf, 0x32, 0x12 + .byte 0x0c, 0xd0, 0xaf, 0x33, 0x02, 0x0c, 0xd0, 0x53 + .byte 0x1a, 0xef, 0x90, 0xd0, 0x00, 0xe5, 0x1a, 0xf0 + .byte 0x12, 0x0c, 0xd0, 0x43, 0x1a, 0x10, 0x90, 0xd0 + .byte 0x00, 0xe5, 0x1a, 0xf0, 0x22, 0x12, 0x0e, 0x74 + .byte 0x12, 0x0e, 0xa2, 0xe4, 0xfb, 0x7d, 0xd0, 0xaf + .byte 0x34, 0x12, 0x00, 0xe0, 0x12, 0x0e, 0xa9, 0x02 + .byte 0x0d, 0xea, 0x53, 0x1a, 0xfb, 0x90, 0xd0, 0x00 + .byte 0xe5, 0x1a, 0xf0, 0x53, 0x1a, 0xfd, 0xe5, 0x1a + .byte 0xf0, 0x7f, 0x3c, 0x02, 0x00, 0x06, 0x30, 0x09 + .byte 0x0e, 0x12, 0x0e, 0xb0, 0x40, 0x09, 0xc2, 0x92 + .byte 0xc2, 0x93, 0xc2, 0x09, 0x12, 0x0e, 0x7d, 0x22 + .byte 0xa2, 0x1f, 0x92, 0x21, 0x85, 0x2f, 0x30, 0xa2 + .byte 0x20, 0x92, 0x22, 0xc2, 0x23, 0xc2, 0x24, 0x02 + .byte 0x06, 0xee, 0xef, 0xc4, 0x54, 0x0f, 0x90, 0x03 + .byte 0x53, 0x93, 0xfe, 0xef, 0x54, 0x0f, 0x93, 0x2e + .byte 0xff, 0x22, 0x90, 0xe0, 0x00, 0xe0, 0x44, 0x02 + .byte 0x54, 0xfe, 0xfe, 0xf0, 0x54, 0xfd, 0xf0, 0xee + .byte 0xf0, 0x22, 0x12, 0x0e, 0xa2, 0x12, 0x0c, 0xb3 + .byte 0x92, 0x1b, 0x12, 0x0e, 0xa9, 0x20, 0x1b, 0xf2 + .byte 0x22, 0x30, 0x05, 0x09, 0x20, 0x0e, 0x06, 0x20 + .byte 0x02, 0x03, 0xd3, 0x80, 0x01, 0xc3, 0x22, 0x30 + .byte 0x03, 0x09, 0x20, 0x0a, 0x06, 0x20, 0x02, 0x03 + .byte 0xd3, 0x80, 0x01, 0xc3, 0x22, 0xaa, 0x06, 0xea + .byte 0x24, 0xd0, 0xfd, 0xef, 0xfb, 0xaf, 0x34, 0x12 + .byte 0x0b, 0xb4, 0x22, 0xef, 0x24, 0xfe, 0xfb, 0x7d + .byte 0xef, 0xaf, 0x34, 0x12, 0x0b, 0xb4, 0x22, 0xd2 + .byte 0x02, 0xd2, 0x0d, 0xc2, 0x96, 0xd2, 0x10, 0xc2 + .byte 0x94, 0x22, 0xef, 0x90, 0x02, 0xc9, 0x93, 0x6d + .byte 0x60, 0x02, 0x80, 0xfe, 0x22, 0x12, 0x0d, 0xf9 + .byte 0x50, 0x04, 0xc2, 0x10, 0xd2, 0x94, 0x22, 0x12 + .byte 0x0e, 0x07, 0x50, 0x04, 0xc2, 0x0d, 0xd2, 0x96 + .byte 0x22, 0xe5, 0x89, 0x54, 0xf0, 0x44, 0x01, 0xf5 + .byte 0x89, 0x22, 0x30, 0x8d, 0x04, 0xc2, 0x8c, 0xd3 + .byte 0x22, 0xc3, 0x22, 0x30, 0xcf, 0x04, 0xc2, 0xca + .byte 0xd3, 0x22, 0xc3, 0x22, 0x12, 0x0e, 0xa2, 0x12 + .byte 0x0e, 0xfa, 0x02, 0x0e, 0xa9, 0x12, 0x0e, 0xeb + .byte 0xc2, 0x0e, 0x02, 0x0e, 0x45, 0xc2, 0x02, 0x12 + .byte 0x0e, 0x4f, 0x02, 0x0e, 0x45, 0xc2, 0x05, 0xd2 + .byte 0x10, 0xc2, 0x94, 0x22, 0xc2, 0x03, 0xd2, 0x0d + .byte 0xc2, 0x96, 0x22, 0x90, 0xd0, 0x00, 0xe5, 0x1a + .byte 0xf0, 0x22, 0x30, 0x28, 0x03, 0x12, 0x0b, 0x90 + .byte 0x22, 0x30, 0x28, 0x03, 0x12, 0x0d, 0x92, 0x22 + .byte 0x90, 0xe0, 0x00, 0xe0, 0x13, 0x22, 0x53, 0x1a + .byte 0xfe, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x01, 0x02 + .byte 0x0e, 0x9b, 0x53, 0x1a, 0xfd, 0x02, 0x0e, 0x9b + .byte 0x43, 0x1a, 0x02, 0x02, 0x0e, 0x9b, 0x53, 0x1a + .byte 0xfb, 0x02, 0x0e, 0x9b, 0x43, 0x1a, 0x04, 0x02 + .byte 0x0e, 0x9b, 0x53, 0x1a, 0x7f, 0x02, 0x0e, 0x9b + .byte 0x43, 0x1a, 0x80, 0x02, 0x0e, 0x9b, 0xd2, 0x05 + .byte 0x02, 0x0e, 0x45, 0xc2, 0x0a, 0x02, 0x0e, 0x4f + .byte 0xd2, 0x03, 0x02, 0x0e, 0x4f, 0x8f, 0x1a, 0x02 + .byte 0x0e, 0x9b, 0x7f, 0x06, 0x02, 0x0d, 0x67, 0x7f + .byte 0x04, 0x02, 0x0d, 0x67, 0xae, 0x36, 0xaf, 0x37 + .byte 0x22, 0xe4, 0xf5, 0xc8, 0x22, 0x12, 0x0c, 0x1a + .byte 0x22, 0xc2, 0x0b, 0x22, 0xd2, 0x0b, 0x22, 0xc2 + .byte 0x06, 0x22, 0xd2, 0x06, 0x22, 0xaf, 0x35, 0x22 + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..e322df3 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -169,7 +169,7 @@ clear_fixed_var_mtrr_out: /* * 0x06 is the WB IO type for a given 4k segment. * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. + * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fe1e29a..0fffa39 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -205,7 +205,7 @@ ap_init: post_code(0x27)
/* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0
diff --git a/src/cpu/intel/fit/fit.inc b/src/cpu/intel/fit/fit.inc index e4595c0..f27d2c2 100644 --- a/src/cpu/intel/fit/fit.inc +++ b/src/cpu/intel/fit/fit.inc @@ -11,7 +11,7 @@ fit_pointer: .global fit_table .global fit_table_end fit_table: -/* Address for type 0 is '_FIT_ ' */ +/* Address for type 0 is '_FIT_ ' */ .long 0x5449465f .long 0x2020205f /* diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 60c061d..0001b1c 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -34,6 +34,6 @@ $(SIPI_BIN): $(SIPI_ELF) $(OBJCOPY) -O binary $< $@
$(SIPI_BIN).ramstage.o: $(SIPI_BIN) - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 9e10c75..5c0bd00 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -330,7 +330,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 2d1e86f..bd109a4 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -32,9 +32,9 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1) @@ -102,16 +102,16 @@ clear_mtrrs: wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
/* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr
/* Clear the cache memory region. This will also fill up the cache */ @@ -123,9 +123,9 @@ clear_mtrrs: rep stosl
/* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr
post_code(0x26) @@ -141,8 +141,8 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr
@@ -208,16 +208,16 @@ before_romstage: post_code(0x31)
/* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr
invd
/* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr
#if CONFIG_CACHE_MRC_BIN diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7dfba86..e281c82 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -190,7 +190,7 @@ struct bus; void bsp_init_and_start_aps(struct bus *cpu_bus); /* Returns 0 on success. < 0 on failure. */ int setup_ap_init(struct bus *cpu_bus, int *max_cpus, - const void *microcode_patch); + const void *microcode_patch); /* Returns 0 on success, < 0 on failure. */ int start_aps(struct bus *cpu_bus, int max_cpus); void release_aps_for_smm_relocation(int do_parallel_relocation); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index b2e6eaf..e07d08b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -53,33 +53,33 @@ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \ - (IRTL_1024_NS >> 10)) + (IRTL_1024_NS >> 10))
/* * List of supported C-states in this processor. Only the ULT parts support C8, * C9, and C10. */ enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ NUM_C_STATES };
-#define MWAIT_RES(state, sub_state) \ - { \ +#define MWAIT_RES(state, sub_state) \ + { \ .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ @@ -259,7 +259,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff;
printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", - err_code); + err_code);
/* Read the calibrated value. */ MCHBAR32(BIOS_MAILBOX_INTERFACE) = @@ -271,7 +271,7 @@ static void calibrate_24mhz_bclk(void) }
printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", - MCHBAR32(BIOS_MAILBOX_DATA)); + MCHBAR32(BIOS_MAILBOX_DATA)); }
static u32 pcode_mailbox_read(u32 command) @@ -303,7 +303,7 @@ static void configure_pch_power_sharing(void) pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n", - pch_power, pch_power_ext); + pch_power, pch_power_ext);
pmsync = RCBA32(PMSYNC_CONFIG); pmsync2 = RCBA32(PMSYNC_CONFIG2); @@ -465,19 +465,19 @@ static void configure_c_states(void) /* C-state Interrupt Response Latency Control 3 - package C8 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_3_LIMIT; + C_STATE_LATENCY_CONTROL_3_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
/* C-state Interrupt Response Latency Control 4 - package C9 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_4_LIMIT; + C_STATE_LATENCY_CONTROL_4_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
/* C-state Interrupt Response Latency Control 5 - package C10 */ msr.hi = 0; msr.lo = IRTL_VALID | IRTL_1024_NS | - C_STATE_LATENCY_CONTROL_5_LIMIT; + C_STATE_LATENCY_CONTROL_5_LIMIT; wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } } @@ -567,7 +567,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "haswell: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * HASWELL_BCLK); }
static void set_energy_perf_bias(u8 policy) @@ -587,7 +587,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
printk(BIOS_DEBUG, "haswell: energy policy set to %u\n", - policy); + policy); }
static void configure_mca(void) @@ -694,7 +694,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) * can be mirrored by the APs. */ if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { printk(BIOS_CRIT, "AP setup initialization failed. " - "No APs will be brought up.\n"); + "No APs will be brought up.\n"); return; }
@@ -716,7 +716,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) }
static struct device_operations cpu_dev_ops = { - .init = haswell_init, + .init = haswell_init, };
static struct cpu_device_id cpu_table[] = { @@ -728,7 +728,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/haswell/microcode_blob.h b/src/cpu/intel/haswell/microcode_blob.h index c03a468..858670e 100644 --- a/src/cpu/intel/haswell/microcode_blob.h +++ b/src/cpu/intel/haswell/microcode_blob.h @@ -26,7 +26,7 @@ #include "microcode-M3240660_ffff000b.h" #endif /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..135127d 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -112,7 +112,7 @@ static void (*ap_initiate_smm_relocation)(void) = &smm_initiate_relocation;
/* Returns 1 if timeout waiting for APs. 0 if target aps found. */ static int wait_for_aps(atomic_t *val, int target, int total_delay, - int delay_step) + int delay_step) { int timeout = 0; int delayed = 0; @@ -139,7 +139,7 @@ void release_aps_for_smm_relocation(int do_parallel) release_barrier(&smm_relocation_barrier_begin); /* Wait for CPUs to relocate their SMM handler up to 100ms. */ if (wait_for_aps(&num_aps_relocated_smm, atomic_read(&num_aps), - 100000 /* 100 ms */, 200 /* us */)) + 100000 /* 100 ms */, 200 /* us */)) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); }
@@ -304,7 +304,7 @@ static int load_sipi_vector(const void *microcode_patch)
if (rmodule_load_alignment(&sipi_mod) != 4096) { printk(BIOS_CRIT, "SIPI module load alignment(%d) != 4096.\n", - rmodule_load_alignment(&sipi_mod)); + rmodule_load_alignment(&sipi_mod)); return -1; }
@@ -316,7 +316,7 @@ static int load_sipi_vector(const void *microcode_patch)
if (module_size > loc_size) { printk(BIOS_CRIT, "SIPI module size (%d) > region size (%d).\n", - module_size, loc_size); + module_size, loc_size); return -1; }
@@ -374,13 +374,13 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); + num_cores, num_threads);
max_cpus = num_threads; *total_hw_threads = num_threads; if (num_threads > CONFIG_MAX_CPUS) { printk(BIOS_CRIT, "CPU count(%d) exceeds CONFIG_MAX_CPUS(%d)\n", - num_threads, CONFIG_MAX_CPUS); + num_threads, CONFIG_MAX_CPUS); max_cpus = CONFIG_MAX_CPUS; }
@@ -411,7 +411,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads) }
int setup_ap_init(struct bus *cpu_bus, int *max_cpus, - const void *microcode_patch) + const void *microcode_patch) { int num_cpus; int hw_threads; @@ -427,8 +427,8 @@ int setup_ap_init(struct bus *cpu_bus, int *max_cpus,
if (num_cpus < hw_threads) { printk(BIOS_CRIT, - "ERROR: More HW threads (%d) than support (%d).\n", - hw_threads, num_cpus); + "ERROR: More HW threads (%d) than support (%d).\n", + hw_threads, num_cpus); return -1; }
@@ -465,7 +465,7 @@ int start_aps(struct bus *cpu_bus, int ap_count)
if (sipi_vector > 256) { printk(BIOS_CRIT, "SIPI vector too large! 0x%08x\n", - sipi_vector); + sipi_vector); return -1; }
@@ -483,7 +483,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) /* Send INIT IPI to all but self. */ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_INIT); + LAPIC_DM_INIT); printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); mdelay(10);
@@ -499,7 +499,7 @@ int start_aps(struct bus *cpu_bus, int ap_count)
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 1st SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "timed out.\n"); @@ -522,7 +522,7 @@ int start_aps(struct bus *cpu_bus, int ap_count)
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0)); lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | - LAPIC_DM_STARTUP | sipi_vector); + LAPIC_DM_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for 2nd SIPI to complete..."); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "timed out.\n"); @@ -534,7 +534,7 @@ int start_aps(struct bus *cpu_bus, int ap_count) /* Wait for CPUs to check in. */ if (wait_for_aps(&num_aps, ap_count, 10000 /* 10 ms */, 50 /* us */)) { printk(BIOS_DEBUG, "Not all APs checked in: %d/%d.\n", - atomic_read(&num_aps), ap_count); + atomic_read(&num_aps), ap_count); return -1; }
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 757cc34..e79163b 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -81,7 +81,7 @@ static unsigned long choose_top_of_stack(void) #if CONFIG_DYNAMIC_CBMEM /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - ROMSTAGE_RAM_STACK_SIZE); + ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; #else stack_top = ROMSTAGE_STACK; @@ -172,8 +172,8 @@ void * asmlinkage romstage_main(unsigned long bist) const int num_guards = 4; const u32 stack_guard = 0xdeadbeef; u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE + - CONFIG_DCACHE_RAM_SIZE - - CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE); + CONFIG_DCACHE_RAM_SIZE - + CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
printk(BIOS_DEBUG, "Setting up stack guards.\n"); for (i = 0; i < num_guards; i++) @@ -316,8 +316,8 @@ void romstage_after_car(void)
#if CONFIG_RELOCATABLE_RAMSTAGE void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, - void *entry_point) + const struct cbmem_entry *ramstage, + void *entry_point) { struct ramstage_cache *cache; uint32_t total_size; @@ -333,7 +333,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, total_size = sizeof(*cache) + ramstage_size; if (total_size > RESERVED_SMM_SIZE) { printk(BIOS_DEBUG, "0x%08x > RESERVED_SMM_SIZE (0x%08x)\n", - total_size, RESERVED_SMM_SIZE); + total_size, RESERVED_SMM_SIZE); /* Nuke whatever may be there now just in case. */ cache->magic = ~RAMSTAGE_CACHE_MAGIC; return; @@ -356,7 +356,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, }
void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) + const struct cbmem_entry *ramstage) { struct ramstage_cache *cache;
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3f4f45a..785a18a 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -37,10 +37,10 @@ #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 #define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) +#define SMM_CPU_SAVE_EN (1 << 1) /* SMM save state MSRs */ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 @@ -71,7 +71,7 @@ static struct smm_relocation_params smm_reloc_params; static inline void write_smrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->smrr_base.lo, relo_params->smrr_mask.lo); + relo_params->smrr_base.lo, relo_params->smrr_mask.lo); wrmsr(SMRRphysBase_MSR, relo_params->smrr_base); wrmsr(SMRRphysMask_MSR, relo_params->smrr_mask); } @@ -79,7 +79,7 @@ static inline void write_smrr(struct smm_relocation_params *relo_params) static inline void write_emrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, "Writing EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->emrr_base.lo, relo_params->emrr_mask.lo); + relo_params->emrr_base.lo, relo_params->emrr_mask.lo); wrmsr(EMRRphysBase_MSR, relo_params->emrr_base); wrmsr(EMRRphysMask_MSR, relo_params->emrr_mask); } @@ -87,16 +87,16 @@ static inline void write_emrr(struct smm_relocation_params *relo_params) static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) { printk(BIOS_DEBUG, - "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", - relo_params->uncore_emrr_base.lo, - relo_params->uncore_emrr_mask.lo); + "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", + relo_params->uncore_emrr_base.lo, + relo_params->uncore_emrr_mask.lo); wrmsr(UNCORE_EMRRphysBase_MSR, relo_params->uncore_emrr_base); wrmsr(UNCORE_EMRRphysMask_MSR, relo_params->uncore_emrr_mask); }
static void update_save_state(int cpu, - struct smm_relocation_params *relo_params, - const struct smm_runtime *runtime) + struct smm_relocation_params *relo_params, + const struct smm_runtime *runtime) { u32 smbase; u32 iedbase; @@ -108,7 +108,7 @@ static void update_save_state(int cpu, iedbase = relo_params->ied_base;
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n", - smbase, iedbase); + smbase, iedbase);
/* All threads need to set IEDBASE and SMBASE to the relocated * handler region. However, the save state location depends on the @@ -136,7 +136,7 @@ static void update_save_state(int cpu, em64t101_smm_state_save_area_t *save_state;
save_state = (void *)(runtime->smbase + SMM_DEFAULT_SIZE - - runtime->save_state_size); + runtime->save_state_size);
save_state->smbase = smbase; save_state->iedbase = iedbase; @@ -172,7 +172,7 @@ cpu_smm_do_relocation(void *arg, int cpu, const struct smm_runtime *runtime)
if (cpu >= CONFIG_MAX_CPUS) { printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); + "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; }
@@ -230,7 +230,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) }
static void fill_in_relocation_params(device_t dev, - struct smm_relocation_params *params) + struct smm_relocation_params *params) { u32 tseg_size; u32 tsegmb; @@ -282,7 +282,7 @@ static void fill_in_relocation_params(device_t dev, params->uncore_emrr_base.lo = emrr_base; params->uncore_emrr_base.hi = 0; params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) | - MTRRphysMaskValid; + MTRRphysMaskValid; params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1; }
@@ -303,7 +303,7 @@ static void adjust_apic_id_map(struct smm_loader_params *smm_params) }
static int install_relocation_handler(int num_cpus, - struct smm_relocation_params *relo_params) + struct smm_relocation_params *relo_params) { /* The default SMM entry can happen in parallel or serially. If the * default SMM entry is done in parallel the BSP has already setup @@ -354,7 +354,7 @@ static void setup_ied_area(struct smm_relocation_params *params) }
static int install_permanent_handler(int num_cpus, - struct smm_relocation_params *relo_params) + struct smm_relocation_params *relo_params) { /* There are num_cpus concurrent stacks and num_cpus concurrent save * state areas. Lastly, set the stack size to the save state size. */ @@ -367,9 +367,9 @@ static int install_permanent_handler(int num_cpus, };
printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", - relo_params->smram_base); + relo_params->smram_base); if (smm_load_module((void *)relo_params->smram_base, - relo_params->smram_size, &smm_params)) + relo_params->smram_size, &smm_params)) return -1;
adjust_apic_id_map(&smm_params); @@ -395,8 +395,8 @@ static int cpu_smm_setup(void) num_cpus = msr.lo & 0xffff; if (num_cpus > CONFIG_MAX_CPUS) { printk(BIOS_CRIT, - "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", - num_cpus, CONFIG_MAX_CPUS); + "Error: Hardware CPUs (%d) > MAX_CPUS (%d)\n", + num_cpus, CONFIG_MAX_CPUS); }
if (install_relocation_handler(num_cpus, &smm_reloc_params)) { diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1991ed8..44179be 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -127,8 +127,8 @@ const void *intel_microcode_find(void) microcode_updates = walkcbfs((char *) MICROCODE_CBFS_FILE); #else microcode_updates = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE); + MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE); #endif
if (!microcode_updates) @@ -250,9 +250,9 @@ void intel_update_microcode(const void *microcode_updates)
#if !defined(__ROMCC__) printk(BIOS_DEBUG, "microcode: updated to revision " - "0x%x date=%04x-%02x-%02x\n", new_rev, - m->date & 0xffff, (m->date >> 24) & 0xff, - (m->date >> 16) & 0xff); + "0x%x date=%04x-%02x-%02x\n", new_rev, + m->date & 0xffff, (m->date >> 24) & 0xff, + (m->date >> 16) & 0xff); #endif break; } diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh index febf6f9..17023ab 100755 --- a/src/cpu/intel/microcode/update-microcodes.sh +++ b/src/cpu/intel/microcode/update-microcodes.sh @@ -45,12 +45,12 @@ separate_microcode() { perl -pi -e 's,^,/,g' header.inc perl -pi -e 's,^//*,/*,' header.inc for i in xx????; do - name="`head -1 $i`" - name=${name%??} - name=${name:2} - name=$( echo $name ) - name=microcode-${name%.inc}.h - cat header.inc $i > $name + name="`head -1 $i`" + name=${name%??} + name=${name:2} + name=$( echo $name ) + name=microcode-${name%.inc}.h + cat header.inc $i > $name done rm -f xx???? header.inc } @@ -73,7 +73,7 @@ dump_cpuids() { move_microcode() { printf "Moving microcode...\n" dump_cpuids | sort | while read N; do - ID=$( echo $N | cut -d: -f1 ) + ID=$( echo $N | cut -d: -f1 ) F=$( echo $N | cut -d: -f2 )
if [ -d ../model_$ID ]; then @@ -82,15 +82,15 @@ move_microcode() { else ID2=${ID%?}x if [ -d ../model_$ID2 ]; then - echo "Model: $ID($ID2) Microcode: $F (copied)" + echo "Model: $ID($ID2) Microcode: $F (copied)" mv $F ../model_$ID2/$F - else - ID1=${ID%??}xx + else + ID1=${ID%??}xx if [ -d ../model_$ID1 ]; then - echo "Model: $ID($ID1) Microcode: $F (copied)" + echo "Model: $ID($ID1) Microcode: $F (copied)" mv $F ../model_$ID1/$F else - echo "Model: $ID Microcode: $F (erased)" + echo "Model: $ID Microcode: $F (erased)" rm -f $F fi fi diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 47d87de..f3ee2f7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -48,10 +48,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-mA01067AA0B.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void init_timer(void) @@ -375,7 +375,7 @@ static void model_1067x_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_1067x_init, + .init = model_1067x_init, };
static struct cpu_device_id cpu_table[] = { @@ -386,7 +386,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index e0aa120..d4759d5 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -41,10 +41,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-M10106CA107.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
#define IA32_FEATURE_CONTROL 0x003a @@ -164,7 +164,7 @@ static void model_106cx_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_106cx_init, + .init = model_106cx_init, };
static struct cpu_device_id cpu_table[] = { @@ -173,7 +173,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index fa0dc95..9bf2b6f 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -325,7 +325,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index dce0e39..7a689ed 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -107,16 +107,16 @@ clear_var_mtrrs: wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
/* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr
/* Clear the cache memory region. This will also fill up the cache */ @@ -128,9 +128,9 @@ clear_var_mtrrs: rep stosl
/* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr
post_code(0x26) @@ -146,8 +146,8 @@ clear_var_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr
@@ -198,16 +198,16 @@ before_romstage: post_code(0x31)
/* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr
invd
/* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr
post_code(0x33) diff --git a/src/cpu/intel/model_2065x/microcode_blob.h b/src/cpu/intel/model_2065x/microcode_blob.h index 1da40d9..d1ddd39 100644 --- a/src/cpu/intel/model_2065x/microcode_blob.h +++ b/src/cpu/intel/model_2065x/microcode_blob.h @@ -20,7 +20,7 @@ #include "microcode-m9220655_00000003.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 0fd1bf0..09bc42a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -311,7 +311,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); }
static void set_energy_perf_bias(u8 policy) @@ -326,7 +326,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); + policy); #endif }
@@ -362,8 +362,8 @@ static void intel_cores_init(device_t cpu) return;
printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); + cpu->path.apic.apic_id, threads_per_package/threads_per_core, + threads_per_core);
for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; @@ -384,15 +384,15 @@ static void intel_cores_init(device_t cpu) continue;
printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); + cpu->path.apic.apic_id, + new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* Start the new cpu */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); + new->path.apic.apic_id); } #endif } @@ -452,7 +452,7 @@ static void model_2065x_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_2065x_init, + .init = model_2065x_init, };
static struct cpu_device_id cpu_table[] = { @@ -461,7 +461,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 80ed4ba..acee536 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -328,7 +328,7 @@ void generate_cpu_entries(void) int numcpus = totalcores/cores_per_package;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index b4119cc..88d224b 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -28,9 +28,9 @@ #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
/* Cache 4GB - MRC_SIZE_KB for MRC */ -#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) -#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) -#define CACHE_MRC_MASK (~CACHE_MRC_BYTES) +#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) +#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) +#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
@@ -97,16 +97,16 @@ clear_mtrrs: wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0
/* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $1, %eax - andl $~2, %eax + orl $1, %eax + andl $~2, %eax wrmsr
/* Clear the cache memory region. This will also fill up the cache */ @@ -118,9 +118,9 @@ clear_mtrrs: rep stosl
/* enable the 'no eviction run' state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - orl $3, %eax + orl $3, %eax wrmsr
post_code(0x26) @@ -136,8 +136,8 @@ clear_mtrrs: * IMPORTANT: The following calculation _must_ be done at runtime. See * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr
@@ -200,16 +200,16 @@ before_romstage: post_code(0x31)
/* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx + movl $NoEvictMod_MSR, %ecx rdmsr - andl $~2, %eax + andl $~2, %eax wrmsr
invd
/* Disable the no eviction mode */ rdmsr - andl $~1, %eax + andl $~1, %eax wrmsr
#if CONFIG_CACHE_MRC_BIN diff --git a/src/cpu/intel/model_206ax/microcode_blob.h b/src/cpu/intel/model_206ax/microcode_blob.h index 10865ab..28a4264 100644 --- a/src/cpu/intel/model_206ax/microcode_blob.h +++ b/src/cpu/intel/model_206ax/microcode_blob.h @@ -21,7 +21,7 @@ #include "microcode-m12306a9_00000017.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 6028801..f1e9efd 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -447,7 +447,7 @@ static void set_max_ratio(void) wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); }
static void set_energy_perf_bias(u8 policy) @@ -461,7 +461,7 @@ static void set_energy_perf_bias(u8 policy) wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); + policy); }
static void configure_mca(void) @@ -496,8 +496,8 @@ static void intel_cores_init(device_t cpu) return;
printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); + cpu->path.apic.apic_id, threads_per_package/threads_per_core, + threads_per_core);
for (i = 1; i < threads_per_package; ++i) { struct device_path cpu_path; @@ -518,15 +518,15 @@ static void intel_cores_init(device_t cpu) continue;
printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); + cpu->path.apic.apic_id, + new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* Start the new cpu */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); + new->path.apic.apic_id); } #endif } @@ -591,7 +591,7 @@ static void model_206ax_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_206ax_init, + .init = model_206ax_init, };
static struct cpu_device_id cpu_table[] = { @@ -609,7 +609,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, .cstates = cstate_map, }; diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 285bacd..90423f3 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -73,7 +73,7 @@ static void model_65x_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_65x_init, + .init = model_65x_init, };
/* @@ -95,6 +95,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_67x/microcode-293-MU267114.h b/src/cpu/intel/model_67x/microcode-293-MU267114.h index 39d6c88..838ee63 100644 --- a/src/cpu/intel/model_67x/microcode-293-MU267114.h +++ b/src/cpu/intel/model_67x/microcode-293-MU267114.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-530-MU16730e.h b/src/cpu/intel/model_67x/microcode-530-MU16730e.h index ae070ad..54bc965 100644 --- a/src/cpu/intel/model_67x/microcode-530-MU16730e.h +++ b/src/cpu/intel/model_67x/microcode-530-MU16730e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-531-MU26732e.h b/src/cpu/intel/model_67x/microcode-531-MU26732e.h index 40e7bd2..c6e690d 100644 --- a/src/cpu/intel/model_67x/microcode-531-MU26732e.h +++ b/src/cpu/intel/model_67x/microcode-531-MU26732e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-539-MU167210.h b/src/cpu/intel/model_67x/microcode-539-MU167210.h index 232ad7e..7b11bd9 100644 --- a/src/cpu/intel/model_67x/microcode-539-MU167210.h +++ b/src/cpu/intel/model_67x/microcode-539-MU167210.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/microcode-540-MU267238.h b/src/cpu/intel/model_67x/microcode-540-MU267238.h index aa30219..376828a 100644 --- a/src/cpu/intel/model_67x/microcode-540-MU267238.h +++ b/src/cpu/intel/model_67x/microcode-540-MU267238.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 3ebe361..a4e0a07 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -63,7 +63,7 @@ static void model_67x_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_67x_init, + .init = model_67x_init, };
/* @@ -82,6 +82,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_68x/microcode-534-MU16810d.h b/src/cpu/intel/model_68x/microcode-534-MU16810d.h index 8ecf059..6479ace 100644 --- a/src/cpu/intel/model_68x/microcode-534-MU16810d.h +++ b/src/cpu/intel/model_68x/microcode-534-MU16810d.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-535-MU16810e.h b/src/cpu/intel/model_68x/microcode-535-MU16810e.h index 02da11e..683b42e 100644 --- a/src/cpu/intel/model_68x/microcode-535-MU16810e.h +++ b/src/cpu/intel/model_68x/microcode-535-MU16810e.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-536-MU16810f.h b/src/cpu/intel/model_68x/microcode-536-MU16810f.h index 9d31fc6..013b77d 100644 --- a/src/cpu/intel/model_68x/microcode-536-MU16810f.h +++ b/src/cpu/intel/model_68x/microcode-536-MU16810f.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-537-MU268110.h b/src/cpu/intel/model_68x/microcode-537-MU268110.h index 6acfe79..4490e62 100644 --- a/src/cpu/intel/model_68x/microcode-537-MU268110.h +++ b/src/cpu/intel/model_68x/microcode-537-MU268110.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-538-MU168111.h b/src/cpu/intel/model_68x/microcode-538-MU168111.h index 38558cb..912e6fc 100644 --- a/src/cpu/intel/model_68x/microcode-538-MU168111.h +++ b/src/cpu/intel/model_68x/microcode-538-MU168111.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-550-MU168307.h b/src/cpu/intel/model_68x/microcode-550-MU168307.h index 616c2ef..946a749 100644 --- a/src/cpu/intel/model_68x/microcode-550-MU168307.h +++ b/src/cpu/intel/model_68x/microcode-550-MU168307.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-551-MU168308.h b/src/cpu/intel/model_68x/microcode-551-MU168308.h index 5424136..4701269 100644 --- a/src/cpu/intel/model_68x/microcode-551-MU168308.h +++ b/src/cpu/intel/model_68x/microcode-551-MU168308.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-611-MU168607.h b/src/cpu/intel/model_68x/microcode-611-MU168607.h index 201561a..1202cbd 100644 --- a/src/cpu/intel/model_68x/microcode-611-MU168607.h +++ b/src/cpu/intel/model_68x/microcode-611-MU168607.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-612-MU168608.h b/src/cpu/intel/model_68x/microcode-612-MU168608.h index 905f38f..4aee463 100644 --- a/src/cpu/intel/model_68x/microcode-612-MU168608.h +++ b/src/cpu/intel/model_68x/microcode-612-MU168608.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-615-MU16860a.h b/src/cpu/intel/model_68x/microcode-615-MU16860a.h index a4d1cc2..913eae9 100644 --- a/src/cpu/intel/model_68x/microcode-615-MU16860a.h +++ b/src/cpu/intel/model_68x/microcode-615-MU16860a.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-617-MU16860c.h b/src/cpu/intel/model_68x/microcode-617-MU16860c.h index 09a4cb0..f07cdcf 100644 --- a/src/cpu/intel/model_68x/microcode-617-MU16860c.h +++ b/src/cpu/intel/model_68x/microcode-617-MU16860c.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-618-MU268602.h b/src/cpu/intel/model_68x/microcode-618-MU268602.h index d8a294a..7df8006 100644 --- a/src/cpu/intel/model_68x/microcode-618-MU268602.h +++ b/src/cpu/intel/model_68x/microcode-618-MU268602.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-662-MU168a01.h b/src/cpu/intel/model_68x/microcode-662-MU168a01.h index dd01df9..9d16f87 100644 --- a/src/cpu/intel/model_68x/microcode-662-MU168a01.h +++ b/src/cpu/intel/model_68x/microcode-662-MU168a01.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-691-MU168a04.h b/src/cpu/intel/model_68x/microcode-691-MU168a04.h index 0d0c055..975f181 100644 --- a/src/cpu/intel/model_68x/microcode-691-MU168a04.h +++ b/src/cpu/intel/model_68x/microcode-691-MU168a04.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-692-MU168a05.h b/src/cpu/intel/model_68x/microcode-692-MU168a05.h index d4e39bb..b001374 100644 --- a/src/cpu/intel/model_68x/microcode-692-MU168a05.h +++ b/src/cpu/intel/model_68x/microcode-692-MU168a05.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-727-MU168313.h b/src/cpu/intel/model_68x/microcode-727-MU168313.h index 7531eea..fd3a2d2 100644 --- a/src/cpu/intel/model_68x/microcode-727-MU168313.h +++ b/src/cpu/intel/model_68x/microcode-727-MU168313.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-728-MU168314.h b/src/cpu/intel/model_68x/microcode-728-MU168314.h index f6e4efb..35957f3 100644 --- a/src/cpu/intel/model_68x/microcode-728-MU168314.h +++ b/src/cpu/intel/model_68x/microcode-728-MU168314.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/microcode-729-MU268310.h b/src/cpu/intel/model_68x/microcode-729-MU268310.h index 3f63b40..10e6160 100644 --- a/src/cpu/intel/model_68x/microcode-729-MU268310.h +++ b/src/cpu/intel/model_68x/microcode-729-MU268310.h @@ -1,5 +1,5 @@ //+++ -// Copyright (c) <1995-2010>, Intel Corporation. +// Copyright (c) <1995-2010>, Intel Corporation. // All rights reserved. // // Redistribution. Redistribution and use in binary form, without modification, are diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index c4bd7ac..ae18f59 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -52,10 +52,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-691-MU168a04.h" #include "microcode-692-MU168a05.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_68x_init(device_t cpu) @@ -81,7 +81,7 @@ static void model_68x_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_68x_init, + .init = model_68x_init, };
/* @@ -108,7 +108,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index cb805ae..394c9be 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -15,10 +15,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1374-m2069507.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_69x_init(device_t dev) @@ -36,7 +36,7 @@ static void model_69x_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_69x_init, + .init = model_69x_init, };
static struct cpu_device_id cpu_table[] = { @@ -46,6 +46,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b7affd9..4fb5196 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -38,10 +38,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-875-MU16b401.h" #include "microcode-885-MU16b402.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_6bx_init(device_t cpu) @@ -67,7 +67,7 @@ static void model_6bx_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_6bx_init, + .init = model_6bx_init, };
/* @@ -84,7 +84,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 19b351d..9f5479c 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -13,10 +13,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1355-m206d618.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_6dx_init(device_t dev) @@ -34,7 +34,7 @@ static void model_6dx_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_6dx_init, + .init = model_6dx_init, };
static struct cpu_device_id cpu_table[] = { @@ -44,6 +44,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index e9c63da..ed52af9 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -38,10 +38,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-1729-m206ec54.h" #include "microcode-1869-m806ec59.h" /* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
#define IA32_FEATURE_CONTROL 0x003a @@ -190,7 +190,7 @@ static void model_6ex_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_6ex_init, + .init = model_6ex_init, };
static struct cpu_device_id cpu_table[] = { @@ -201,7 +201,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index faf1277..c438412 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -54,10 +54,10 @@ static const uint32_t microcode_updates[] = { #include "microcode-m806fda4.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
#define IA32_FEATURE_CONTROL 0x003a @@ -105,7 +105,7 @@ static void configure_c_states(void) msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 3); // Dynamic L2
- /* Number of supported C-States */ + /* Number of supported C-States */ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
@@ -230,7 +230,7 @@ static void model_6fx_init(device_t cpu) }
static struct device_operations cpu_dev_ops = { - .init = model_6fx_init, + .init = model_6fx_init, };
static struct cpu_device_id cpu_table[] = { @@ -246,7 +246,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 5724add..795d5a4 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -37,10 +37,10 @@ static uint32_t microcode_updates[] = { #include "microcode-620-MU26a401.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_6xx_init(device_t dev) @@ -58,7 +58,7 @@ static void model_6xx_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_6xx_init, + .init = model_6xx_init, };
/* @@ -113,6 +113,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index ed12b6e..042ffba 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -18,10 +18,10 @@ static uint32_t microcode_updates[] = { #include "microcode-966-m04f0a14.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_f0x_init(device_t dev) @@ -39,7 +39,7 @@ static void model_f0x_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_f0x_init, + .init = model_f0x_init, };
static struct cpu_device_id cpu_table[] = { @@ -49,6 +49,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index feb8410..ad44bff 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -21,10 +21,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1072-m04f1305.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_f1x_init(device_t dev) @@ -42,7 +42,7 @@ static void model_f1x_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = model_f1x_init, + .init = model_f1x_init, };
static struct cpu_device_id cpu_table[] = { @@ -52,6 +52,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 8fd8abc..acbf28f 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -38,10 +38,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1106-m02f241f.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_f2x_init(device_t cpu) @@ -66,7 +66,7 @@ static void model_f2x_init(device_t cpu) };
static struct device_operations cpu_dev_ops = { - .init = model_f2x_init, + .init = model_f2x_init, };
static struct cpu_device_id cpu_table[] = { @@ -80,6 +80,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index 2504ba9..e0882be 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -21,10 +21,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1468-m1df3417.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_f3x_init(device_t cpu) @@ -58,6 +58,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver model_f3x __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index f3f0b2a..71e6093 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -29,10 +29,10 @@ static uint32_t microcode_updates[] = { #include "microcode-1498-m5df4a02.h"
/* Dummy terminator */ - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, };
static void model_f4x_init(device_t cpu) @@ -66,6 +66,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver model_f4x __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index a974d24..7e3f45a 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -64,9 +64,9 @@ Cache latency to be written to L2 -----++++ control register |||| 0000 xx 00 -----> 000 cccc 0 -|||| 00 66MHz -|||| 10 100MHz -|||| 01 133MHz (Katmai "B" only) +|||| 00 66MHz +|||| 10 100MHz +|||| 01 133MHz (Katmai "B" only) ++++------ CPU frequency multiplier
0000 2x @@ -344,7 +344,7 @@ int test_l2_address_alias(u32 address1, u32 address2, /* Calculates the L2 cache size. * * Reference: Intel(R) 64 and IA-32 Architectures Software Developer�s Manual - * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. + * Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172. * */ int calculate_l2_cache_size(void) @@ -696,7 +696,7 @@ int p6_configure_l2_cache(void) if (v >= 0 && (v & 0x20)) { bblctl3 = rdmsr(BBL_CR_CTL3); bblctl3.lo |= (BBLCR3_L2_ADDR_PARITY_ENABLE | - BBLCR3_L2_CRTN_PARITY_ENABLE); + BBLCR3_L2_CRTN_PARITY_ENABLE); wrmsr(BBL_CR_CTL3, bblctl3); }
@@ -756,7 +756,7 @@ int p6_configure_l2_cache(void) */ if (signal_l2(cache_size, 0, 0, v, L2CMD_TWW | L2CMD_MESI_I) != 0) { printk(BIOS_ERR, "Failed on signal_l2(%x, %x)\n", - cache_size, v); + cache_size, v); goto bad; } } diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 62bd17b..1df55e6 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,6 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool - select CPU_INTEL_MODEL_6FX + select CPU_INTEL_MODEL_6FX select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 483e813..9d6bb25 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -78,13 +78,13 @@ static int get_fsb(void) case 6: return 1200; /* / 3 == 400 */ } printk(BIOS_WARNING, - "Warning: No supported FSB frequency. Assuming 200MHz\n"); + "Warning: No supported FSB frequency. Assuming 200MHz\n"); return 600; }
static int gen_pstate_entries(const sst_table_t *const pstates, - const int cpuID, const int cores_per_package, - const uint8_t coordination) + const int cpuID, const int cores_per_package, + const uint8_t coordination) { int i; int len, len_ps; @@ -100,13 +100,13 @@ static int gen_pstate_entries(const sst_table_t *const pstates, pstates->states[pstates->num_states - 1]); const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", - (min_ratio2 * fsb3) + (min_ratio2 * fsb3) / (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6), - (max_ratio2 * fsb3) / 6); + (max_ratio2 * fsb3) / 6);
printk(BIOS_DEBUG, "adding %x P-States between " "busratio %x and %x, ""incl. P0\n", - pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); + pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); len_ps = acpigen_write_package(pstates->num_states); for (i = 0; i < pstates->num_states; ++i) { const sst_state_t *const pstate = &pstates->states[i]; @@ -144,15 +144,15 @@ void generate_cpu_entries(void) int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; int numcpus = totalcores/cores_per_package; /* This assumes that all - CPUs share the same - layout. */ + CPUs share the same + layout. */ int num_cstates; acpi_cstate_t *cstates; sst_table_t pstates; uint8_t coordination;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); + numcpus, cores_per_package);
num_cstates = get_cst_entries(&cstates); speedstep_gen_pstates(&pstates); diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index f2cff04..caf4d33 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -171,9 +171,9 @@ void speedstep_gen_pstates(sst_table_t *const table) /* Now, add all other normal states based on LFM (min). */ const int power_step = (power_diff2 / states) / 2; const int vid_step = (vid_diff2 / states) / 2; - const int ratio_step = step2 / 2; + const int ratio_step = step2 / 2; int power = params.min.power + (states - 1) * power_step; - int vid = params.min.vid + (states - 1) * vid_step; + int vid = params.min.vid + (states - 1) * vid_step; int ratio = params.min.ratio + (states - 1) * ratio_step; for (; states > 0; --states) { table->states[table->num_states++] = diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index c27a1ee..607080b 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -28,7 +28,7 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, };
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 73fd3c5..797d69a 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -55,6 +55,6 @@ ramstage-y += fb.c ramstage-y += usb.c
exynos5250_add_bl1: $(obj)/coreboot.pre - printf " DD Adding Samsung Exynos5250 BL1\n" + printf " DD Adding Samsung Exynos5250 BL1\n" dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index 565cf2b..e82a494 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -43,7 +43,7 @@ enum pll_src_bit { * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { - s8 src_bit; /* offset in register to clock source field */ + s8 src_bit; /* offset in register to clock source field */ s8 n_src_bits; /* number of bits in 'src_bit' field */ s8 div_bit; s8 prediv_bit; diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c index 390fae3..ad1aaae 100644 --- a/src/cpu/samsung/exynos5250/clock.c +++ b/src/cpu/samsung/exynos5250/clock.c @@ -27,7 +27,7 @@ #include "periph.h"
/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_CLK_FREQ 24000000
static struct arm_clk_ratios arm_clk_ratios[] = { { @@ -435,7 +435,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -472,7 +472,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -559,7 +559,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return -1; }
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 61f937b..db759d1 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -116,7 +116,7 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); + "Initializing Exynos VGA, base %p\n", (void *)lcdbase); ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); }
@@ -144,10 +144,10 @@ static void cpu_noop(device_t dev)
static struct device_operations cpu_ops = { .read_resources = cpu_noop, - .set_resources = cpu_noop, + .set_resources = cpu_noop, .enable_resources = cpu_enable, - .init = cpu_init, - .scan_bus = 0, + .init = cpu_init, + .scan_bus = 0, };
static void enable_exynos5250_dev(device_t dev) @@ -165,9 +165,9 @@ void exynos5250_config_l2_cache(void) uint32_t val;
/* - * Bit 9 - L2 tag RAM setup (1 cycle) + * Bit 9 - L2 tag RAM setup (1 cycle) * Bits 8:6 - L2 tag RAM latency (3 cycles) - * Bit 5 - L2 data RAM setup (1 cycle) + * Bit 5 - L2 data RAM setup (1 cycle) * Bits 2:0 - L2 data RAM latency (3 cycles) */ val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index 63f17e2..ba6cd8c 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -52,7 +52,7 @@ #define EXYNOS5_TZPC1_DECPROT1SET 0x10110810 #define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_GPIO_PART4_BASE 0x10D10000 /* V00..V37 */ diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h index acd0abb..436252c 100644 --- a/src/cpu/samsung/exynos5250/dmc.h +++ b/src/cpu/samsung/exynos5250/dmc.h @@ -273,7 +273,7 @@ struct mem_timings { uint8_t bpll_mdiv; uint8_t bpll_pdiv; uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ uint8_t pclk_cdrex_ratio; unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index b506853..5696ced 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -134,14 +134,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + &dmc->directcmd); udelay(100); }
if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + &dmc->directcmd); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 554f4c2..667edee 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -54,7 +54,7 @@ static void reset_phy_ctrl(void) }
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset) + int mem_reset) { unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -76,7 +76,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, /* Set Impedance Output Driver */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n"); printk(BIOS_SPEW, "ddr3_mem_ctrl_init: mem->impedance 0x%x\n", - mem->impedance); + mem->impedance); val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | (mem->impedance << CA_CKE_DRVR_DS_OFFSET) | (mem->impedance << CA_CS_DRVR_DS_OFFSET) | @@ -87,7 +87,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Set Read Latency and Burst Length for PHY0 and PHY1 */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set Read Latency and Burst Length for PHY0 and PHY1\n"); + "Set Read Latency and Burst Length for PHY0 and PHY1\n"); val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT); writel(val, &phy0_ctrl->phy_con42); @@ -141,7 +141,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Memory Channel Interleaving Size */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Memory Channel Interleaving Size\n"); + "Memory Channel Interleaving Size\n"); writel(mem->iv_size, &dmc->ivcontrol);
/* Set DMC MEMCONTROL register */ @@ -161,7 +161,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Power Down mode Configuration */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Power Down mode Configuration\n"); + "Power Down mode Configuration\n"); writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT | mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT, &dmc->pwrdnconfig); @@ -170,7 +170,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, * values as per Memory AC parameters */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "TimingRow, TimingData, TimingPower and Timingaref\n"); + "TimingRow, TimingData, TimingPower and Timingaref\n"); writel(mem->timing_ref, &dmc->timingref); writel(mem->timing_row, &dmc->timingrow); writel(mem->timing_data, &dmc->timingdata); @@ -270,7 +270,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
/* Set DMC Concontrol and enable auto-refresh counter */ printk(BIOS_SPEW, "ddr3_mem_ctrl_init: " - "Set DMC Concontrol and enable auto-refresh counter\n"); + "Set DMC Concontrol and enable auto-refresh counter\n"); writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT) | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol); return 0; diff --git a/src/cpu/samsung/exynos5250/dp.h b/src/cpu/samsung/exynos5250/dp.h index 5c778ba..11b9d00 100644 --- a/src/cpu/samsung/exynos5250/dp.h +++ b/src/cpu/samsung/exynos5250/dp.h @@ -425,8 +425,8 @@ struct exynos5_dp { #define VIDEO_MODE_SLAVE_MODE (1 << 0) #define VIDEO_MODE_MASTER_MODE (0 << 0)
-#define HW_TRAINING_ERROR_CODE (7<<4) -#define HW_TRAINING_EN (1<<0) +#define HW_TRAINING_ERROR_CODE (7<<4) +#define HW_TRAINING_EN (1<<0)
/* I2C EDID Chip ID, Slave Address */ #define I2C_EDID_DEVICE_ADDR 0x50 diff --git a/src/cpu/samsung/exynos5250/dsim.h b/src/cpu/samsung/exynos5250/dsim.h index b9245d3..b2134a9 100644 --- a/src/cpu/samsung/exynos5250/dsim.h +++ b/src/cpu/samsung/exynos5250/dsim.h @@ -103,7 +103,7 @@ struct exynos5_dsim { #define PLL_STABLE (1 << 31)
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10)
#endif diff --git a/src/cpu/samsung/exynos5250/fb.c b/src/cpu/samsung/exynos5250/fb.c index 760f5ee..06e6ae6 100644 --- a/src/cpu/samsung/exynos5250/fb.c +++ b/src/cpu/samsung/exynos5250/fb.c @@ -187,7 +187,7 @@ void exynos_fimd_disable(void) * return status */ static int s5p_dp_config_video(struct s5p_dp_device *dp, - struct video_info *video_info) + struct video_info *video_info) { int timeout = 0; struct exynos5_dp *base = dp->base; @@ -195,9 +195,9 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, s5p_dp_config_video_slave_mode(dp, video_info);
s5p_dp_set_video_color_format(dp, video_info->color_depth, - video_info->color_space, - video_info->dynamic_range, - video_info->ycbcr_coeff); + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff);
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { printk(BIOS_DEBUG, "PLL is not locked yet.\n"); @@ -258,8 +258,8 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) return -ERR_DPCD_READ_ERROR1; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, - DPCD_ENHANCED_FRAME_EN | - (data & DPCD_LANE_COUNT_SET_MASK))) { + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR1; } @@ -280,13 +280,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE);
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - &data)) { + &data)) { printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR2; }
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR2; } @@ -334,7 +334,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) * return status */ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, - int pre_emphasis, int lane) + int pre_emphasis, int lane) { u32 reg; struct exynos5_dp *base = dp->base; @@ -439,7 +439,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) if (s5p_dp_set_lane_lane_pre_emphasis(dp, - PRE_EMPHASIS_LEVEL_0, lane)) { + PRE_EMPHASIS_LEVEL_0, lane)) { printk(BIOS_DEBUG, "Unable to set pre emphasis level\n"); return -ERR_PRE_EMPHASIS_LEVELS; } @@ -457,14 +457,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", - dp->link_train.link_rate); + dp->link_train.link_rate); /* Not Retrying */ return -ERR_LINK_RATE_ABNORMAL; }
if (dp->link_train.lane_count == 0) { printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n", - dp->link_train.lane_count); + dp->link_train.lane_count); /* Not retrying */ return -ERR_MAX_LANE_COUNT_ABNORMAL; } @@ -529,7 +529,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) }
ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + dp->video_info->link_rate); if (ret) { printk(BIOS_ERR, "unable to do link train\n"); return ret; diff --git a/src/cpu/samsung/exynos5250/gpio.c b/src/cpu/samsung/exynos5250/gpio.c index 2a93328..f58d002 100644 --- a/src/cpu/samsung/exynos5250/gpio.c +++ b/src/cpu/samsung/exynos5250/gpio.c @@ -53,7 +53,7 @@ static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { };
/* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) +#define GPIO_BIT(x) ((x) & 0x7)
static struct gpio_bank *gpio_get_bank(unsigned int gpio) { diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h index 0b97526..0cd9e3d 100644 --- a/src/cpu/samsung/exynos5250/gpio.h +++ b/src/cpu/samsung/exynos5250/gpio.h @@ -493,7 +493,7 @@ void gpio_set_rate(int gpio, int mode); * * @param gpio GPIO to read * @return -1 if the value cannot be determined. Otherwise returns - * the corresponding MVL3 enum value. + * the corresponding MVL3 enum value. */ int gpio_read_mvl3(unsigned gpio);
@@ -563,11 +563,11 @@ int gpio_set_value(unsigned gpio, int value); * * Vpd | Vpu | MVL * ----------------- - * 0 | 0 | 0 + * 0 | 0 | 0 * ----------------- - * 0 | 1 | Z <-- floating input will follow internal pull up/down + * 0 | 1 | Z <-- floating input will follow internal pull up/down * ----------------- - * 1 | 1 | 1 + * 1 | 1 | 1 */ enum mvl3 { LOGIC_0, diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h index f349e53..84a3b13 100644 --- a/src/cpu/samsung/exynos5250/power.h +++ b/src/cpu/samsung/exynos5250/power.h @@ -35,9 +35,9 @@ void power_enable_hw_thermal_trip(void); #define DPTX_PHY_ENABLE (1 << 0)
/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ -#define PMU_DEBUG_XXTI 0x1000 +#define PMU_DEBUG_XXTI 0x1000 /* Mask bit[12:8] for xxti clock selection */ -#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
/* Power Management Unit register map */ struct exynos5_power { @@ -55,7 +55,7 @@ struct exynos5_power { uint32_t inform1; /* 0x0804 */ uint8_t reserved6[0x1f8]; uint32_t pmu_debug; /* 0x0A00*/ - uint8_t reserved7[0x2908]; + uint8_t reserved7[0x2908]; uint32_t ps_hold_ctrl; /* 0x330c */ } __attribute__ ((__packed__));
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h index 9f10786..fa258fc 100644 --- a/src/cpu/samsung/exynos5250/setup.h +++ b/src/cpu/samsung/exynos5250/setup.h @@ -42,7 +42,7 @@ struct exynos5_phy_control; #define APLL_CON1_VAL (0x00203800)
/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x00203800) +#define MPLL_CON1_VAL (0x00203800)
/* CPLL_CON1 */ #define CPLL_CON1_VAL (0x00203800) @@ -66,11 +66,11 @@ struct exynos5_phy_control;
/* CLK_SRC_CPU */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 0 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 +#define MUX_HPM_SEL 0 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ | (MUX_CPU_SEL << 16) \ | (MUX_APLL_SEL))
@@ -81,46 +81,46 @@ struct exynos5_phy_control; #define DMC_MEMCONTROL_TP_DISABLE (0 << 4) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) -#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) +#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
-#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
-#define DMC_MEMCONTROL_BL_8 (3 << 20) -#define DMC_MEMCONTROL_BL_4 (2 << 20) +#define DMC_MEMCONTROL_BL_8 (3 << 20) +#define DMC_MEMCONTROL_BL_4 (2 << 20)
-#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) +#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
-#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
/* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) - -#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) -#define DMC_MEMBASECONFIG_VAL(x) ( \ - DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ - DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ +#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) + +#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMBASECONFIG_VAL(x) ( \ + DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ + DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ )
#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
-#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF +#define DMC_PRECHCONFIG_VAL 0xFF000000 +#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 #define DFI_INIT_START (1 << 28) @@ -147,55 +147,55 @@ struct exynos5_phy_control; #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
/* CLK_DIV_CPU0_VAL */ -#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (ACP_RATIO << 8) \ - | (CPUD_RATIO << 4) \ +#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \ + | (APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (ACP_RATIO << 8) \ + | (CPUD_RATIO << 4) \ | (ARM_RATIO))
/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x66666 -#define CLK_DIV_FSYS0_VAL 0x0BB00000 +#define CLK_SRC_FSYS0_VAL 0x66666 +#define CLK_DIV_FSYS0_VAL 0x0BB00000
/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x2 -#define COPY_RATIO 0x0 +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0
/* CLK_DIV_CPU1 = 0x00000003 */ -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ | (COPY_RATIO))
/* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00000000 +#define CLK_SRC_CORE0_VAL 0x00000000
/* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 +#define CLK_SRC_CORE1_VAL 0x100
/* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x00120000 +#define CLK_DIV_CORE0_VAL 0x00120000
/* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 +#define CLK_DIV_CORE1_VAL 0x07070700
/* CLK_DIV_SYSRGT */ -#define CLK_DIV_SYSRGT_VAL 0x00000111 +#define CLK_DIV_SYSRGT_VAL 0x00000111
/* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 +#define CLK_DIV_ACP_VAL 0x12
/* CLK_DIV_SYSLFT */ -#define CLK_DIV_SYSLFT_VAL 0x00000311 +#define CLK_DIV_SYSLFT_VAL 0x00000311
/* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x1 +#define CLK_SRC_CDREX_VAL 0x1
/* CLK_DIV_CDREX */ -#define MCLK_CDREX2_RATIO 0x0 -#define ACLK_EFCON_RATIO 0x1 +#define MCLK_CDREX2_RATIO 0x0 +#define ACLK_EFCON_RATIO 0x1 #define MCLK_DPHY_RATIO 0x1 #define MCLK_CDREX_RATIO 0x1 #define ACLK_C2C_200_RATIO 0x1 @@ -203,20 +203,20 @@ struct exynos5_phy_control; #define PCLK_CDREX_RATIO 0x1 #define ACLK_CDREX_RATIO 0x1
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ +#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \ | (C2C_CLK_400_RATIO << 6) \ | (PCLK_CDREX_RATIO << 4) \ | (ACLK_CDREX_RATIO))
/* CLK_SRC_TOP0 */ -#define MUX_ACLK_300_GSCL_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID_SEL 0x0 -#define MUX_ACLK_400_G3D_MID_SEL 0x0 -#define MUX_ACLK_333_SEL 0x0 -#define MUX_ACLK_300_DISP1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID_SEL 0x0 -#define MUX_ACLK_200_SEL 0x0 -#define MUX_ACLK_166_SEL 0x0 +#define MUX_ACLK_300_GSCL_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID_SEL 0x0 +#define MUX_ACLK_400_G3D_MID_SEL 0x0 +#define MUX_ACLK_333_SEL 0x0 +#define MUX_ACLK_300_DISP1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID_SEL 0x0 +#define MUX_ACLK_200_SEL 0x0 +#define MUX_ACLK_166_SEL 0x0 #define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \ | (MUX_ACLK_300_GSCL_MID_SEL << 24) \ | (MUX_ACLK_400_G3D_MID_SEL << 20) \ @@ -227,50 +227,50 @@ struct exynos5_phy_control; | (MUX_ACLK_166_SEL << 8))
/* CLK_SRC_TOP1 */ -#define MUX_ACLK_400_G3D_SEL 0x1 -#define MUX_ACLK_400_ISP_SEL 0x0 -#define MUX_ACLK_400_IOP_SEL 0x0 -#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 -#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 -#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 -#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ - |(MUX_ACLK_400_ISP_SEL << 24) \ - |(MUX_ACLK_400_IOP_SEL << 20) \ +#define MUX_ACLK_400_G3D_SEL 0x1 +#define MUX_ACLK_400_ISP_SEL 0x0 +#define MUX_ACLK_400_IOP_SEL 0x0 +#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0 +#define MUX_ACLK_300_GSCL_MID1_SEL 0x0 +#define MUX_ACLK_300_DISP1_MID1_SEL 0x0 +#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \ + |(MUX_ACLK_400_ISP_SEL << 24) \ + |(MUX_ACLK_400_IOP_SEL << 20) \ |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \ - |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ + |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \ |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
/* CLK_SRC_TOP2 */ -#define MUX_GPLL_SEL 0x1 -#define MUX_BPLL_USER_SEL 0x0 -#define MUX_MPLL_USER_SEL 0x0 -#define MUX_VPLL_SEL 0x1 -#define MUX_EPLL_SEL 0x1 -#define MUX_CPLL_SEL 0x1 -#define VPLLSRC_SEL 0x0 +#define MUX_GPLL_SEL 0x1 +#define MUX_BPLL_USER_SEL 0x0 +#define MUX_MPLL_USER_SEL 0x0 +#define MUX_VPLL_SEL 0x1 +#define MUX_EPLL_SEL 0x1 +#define MUX_CPLL_SEL 0x1 +#define VPLLSRC_SEL 0x0 #define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \ | (MUX_BPLL_USER_SEL << 24) \ | (MUX_MPLL_USER_SEL << 20) \ - | (MUX_VPLL_SEL << 16) \ - | (MUX_EPLL_SEL << 12) \ - | (MUX_CPLL_SEL << 8) \ + | (MUX_VPLL_SEL << 16) \ + | (MUX_EPLL_SEL << 12) \ + | (MUX_CPLL_SEL << 8) \ | (VPLLSRC_SEL)) /* CLK_SRC_TOP3 */ -#define MUX_ACLK_333_SUB_SEL 0x1 -#define MUX_ACLK_400_SUB_SEL 0x1 -#define MUX_ACLK_266_ISP_SUB_SEL 0x1 -#define MUX_ACLK_266_GPS_SUB_SEL 0x0 -#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 -#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 -#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 -#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ - | (MUX_ACLK_400_SUB_SEL << 20) \ +#define MUX_ACLK_333_SUB_SEL 0x1 +#define MUX_ACLK_400_SUB_SEL 0x1 +#define MUX_ACLK_266_ISP_SUB_SEL 0x1 +#define MUX_ACLK_266_GPS_SUB_SEL 0x0 +#define MUX_ACLK_300_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_266_GSCL_SUB_SEL 0x1 +#define MUX_ACLK_300_DISP1_SUB_SEL 0x1 +#define MUX_ACLK_200_DISP1_SUB_SEL 0x1 +#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \ + | (MUX_ACLK_400_SUB_SEL << 20) \ | (MUX_ACLK_266_ISP_SUB_SEL << 16) \ - | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ - | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ - | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ - | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ + | (MUX_ACLK_266_GPS_SUB_SEL << 12) \ + | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \ + | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \ + | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \ | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
/* CLK_DIV_TOP0 */ @@ -293,11 +293,11 @@ struct exynos5_phy_control; | (ACLK_66_RATIO))
/* CLK_DIV_TOP1 */ -#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 -#define ACLK_66_PRE_RATIO 0x1 -#define ACLK_400_ISP_RATIO 0x1 -#define ACLK_400_IOP_RATIO 0x1 -#define ACLK_300_GSCL_RATIO 0x2 +#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3 +#define ACLK_66_PRE_RATIO 0x1 +#define ACLK_400_ISP_RATIO 0x1 +#define ACLK_400_IOP_RATIO 0x1 +#define ACLK_300_GSCL_RATIO 0x2
#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \ | (ACLK_66_PRE_RATIO << 24) \ @@ -352,10 +352,10 @@ struct exynos5_phy_control; #define UART1_SEL 6 #define UART0_SEL 6 /* SRC_CLOCK = SCLK_MPLL */ -#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ - | (UART3_SEL << 12) \ - | (UART2_SEL << 8) \ - | (UART1_SEL << 4) \ +#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ | (UART0_SEL))
/* CLK_SRC_PERIC1 */ @@ -387,7 +387,7 @@ struct exynos5_phy_control; #define UART1_RATIO 7 #define UART0_RATIO 7
-#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ +#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \ | (UART2_RATIO << 8) \ | (UART1_RATIO << 4) \ | (UART0_RATIO)) @@ -424,25 +424,25 @@ struct exynos5_phy_control; #define MMC3_PRE_RATIO_OFFSET 24
/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP0 */ -#define CLK_DIV_ISP0_VAL 0x31 +#define CLK_DIV_ISP0_VAL 0x31
/* CLK_DIV_ISP1 */ -#define CLK_DIV_ISP1_VAL 0x0 +#define CLK_DIV_ISP1_VAL 0x0
/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_DISP1_0 */ #define CLK_SRC_DISP1_0_VAL 0x6 @@ -701,7 +701,7 @@ void mem_ctrl_init(void); * @return 0 if ok, SETUP_ERR_... if there is a problem */ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size, - int mem_reset); + int mem_reset);
/* * Configure ZQ I/O interface diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c index 1c365dc..9d5c4f7 100644 --- a/src/cpu/samsung/exynos5250/spi.c +++ b/src/cpu/samsung/exynos5250/spi.c @@ -36,7 +36,7 @@ #endif
static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, - void *dinp, void const *doutp, int i) + void *dinp, void const *doutp, int i) { int rx_lvl, tx_lvl; unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024))); @@ -195,8 +195,8 @@ static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, }
int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size) { + void *buffer_address, + size_t buffer_size) { // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; DEBUG_SPI("initialize_exynos_spi_cbfs_media\n"); diff --git a/src/cpu/samsung/exynos5250/spi.h b/src/cpu/samsung/exynos5250/spi.h index 7ca3114..a59574d 100644 --- a/src/cpu/samsung/exynos5250/spi.h +++ b/src/cpu/samsung/exynos5250/spi.h @@ -93,6 +93,6 @@ int exynos_spi_close(struct exynos_spi *regs);
/* Serve as CBFS media source */ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); + void *buffer_address, + size_t buffer_size); #endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dbf7202..f21f373 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -172,7 +172,7 @@ static void exynos5_uart_tx_flush(void) #if !defined(__PRE_RAM__)
static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, + .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, .tx_flush = exynos5_uart_tx_flush, .rx_byte = exynos5_uart_rx_byte, diff --git a/src/cpu/samsung/exynos5250/usb.h b/src/cpu/samsung/exynos5250/usb.h index 45a7b53..3a53bab 100644 --- a/src/cpu/samsung/exynos5250/usb.h +++ b/src/cpu/samsung/exynos5250/usb.h @@ -20,41 +20,41 @@ #ifndef CPU_SAMSUNG_EXYNOS5250_USB_H #define CPU_SAMSUNG_EXYNOS5250_USB_H
-#define CLK_24MHZ 5 +#define CLK_24MHZ 5
-#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0)
-#define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HOST_CTRL0_FSEL_MASK (7 << 16)
-#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26)
/* Register map for PHY control */ struct usb_phy { - uint32_t usbphyctrl0; - uint32_t usbphytune0; - uint32_t reserved1[2]; - uint32_t hsicphyctrl1; - uint32_t hsicphytune1; - uint32_t reserved2[2]; - uint32_t hsicphyctrl2; - uint32_t hsicphytune2; - uint32_t reserved3[2]; - uint32_t ehcictrl; - uint32_t ohcictrl; - uint32_t usbotgsys; - uint32_t reserved4; - uint32_t usbotgtune; + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; };
void usb_init(device_t dev); diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 8540409..bce86ed 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -55,6 +55,6 @@ ramstage-y += fb.c ramstage-y += usb.c
exynos5420_add_bl1: $(obj)/coreboot.pre - printf " DD Adding Samsung Exynos5420 BL1\n" + printf " DD Adding Samsung Exynos5420 BL1\n" dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h index 8e2f9ed..12a9565 100644 --- a/src/cpu/samsung/exynos5420/clk.h +++ b/src/cpu/samsung/exynos5420/clk.h @@ -49,7 +49,7 @@ enum pll_src_bit { * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { - s8 src_bit; /* offset in register to clock source field */ + s8 src_bit; /* offset in register to clock source field */ s8 div_bit; s8 prediv_bit; }; diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 8c4baf8..b860b72 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -27,7 +27,7 @@ #include "periph.h"
/* input clock of PLL: SMDK5420 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_CLK_FREQ 24000000
/* src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { @@ -304,7 +304,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -340,7 +340,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return; } clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); @@ -427,7 +427,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate) break; default: printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__, - periph_id); + periph_id); return -1; }
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 744f7ae..b62627c 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -115,7 +115,7 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, - "Initializing Exynos VGA, base %p\n", (void *)lcdbase); + "Initializing Exynos VGA, base %p\n", (void *)lcdbase); lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); }
@@ -143,10 +143,10 @@ static void cpu_noop(device_t dev)
static struct device_operations cpu_ops = { .read_resources = cpu_noop, - .set_resources = cpu_noop, + .set_resources = cpu_noop, .enable_resources = cpu_enable, - .init = cpu_init, - .scan_bus = 0, + .init = cpu_init, + .scan_bus = 0, };
static void enable_exynos5420_dev(device_t dev) @@ -164,9 +164,9 @@ void exynos5420_config_l2_cache(void) uint32_t val;
/* - * Bit 9 - L2 tag RAM setup (1 cycle) + * Bit 9 - L2 tag RAM setup (1 cycle) * Bits 8:6 - L2 tag RAM latency (3 cycles) - * Bit 5 - L2 data RAM setup (1 cycle) + * Bit 5 - L2 data RAM setup (1 cycle) * Bits 2:0 - L2 data RAM latency (3 cycles) */ val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h index 251abea..495f03c 100644 --- a/src/cpu/samsung/exynos5420/cpu.h +++ b/src/cpu/samsung/exynos5420/cpu.h @@ -52,7 +52,7 @@ #define EXYNOS5_TZPC1_DECPROT1SET 0x10110810 #define EXYNOS5_MULTI_CORE_TIMER_BASE 0x101C0000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 -#define EXYNOS5_ACE_SFR_BASE 0x10830000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index c974db2..c255132 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -323,7 +323,7 @@ struct mem_timings { uint8_t bpll_mdiv; uint8_t bpll_pdiv; uint8_t bpll_sdiv; - uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ + uint8_t use_bpll; /* 1 to use BPLL for cdrex, 0 to use MPLL */ uint8_t pclk_cdrex_ratio; unsigned int direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
diff --git a/src/cpu/samsung/exynos5420/dmc_common.c b/src/cpu/samsung/exynos5420/dmc_common.c index bef76d1..2e07ad0 100644 --- a/src/cpu/samsung/exynos5420/dmc_common.c +++ b/src/cpu/samsung/exynos5420/dmc_common.c @@ -133,14 +133,14 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, - &dmc->directcmd); + &dmc->directcmd); udelay(100); }
if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, - &dmc->directcmd); + &dmc->directcmd); /* * FIXME: This was originally sdelay(10000) * in the imported u-boot code. That may have diff --git a/src/cpu/samsung/exynos5420/dp.h b/src/cpu/samsung/exynos5420/dp.h index 46579b3..e2fe715 100644 --- a/src/cpu/samsung/exynos5420/dp.h +++ b/src/cpu/samsung/exynos5420/dp.h @@ -425,8 +425,8 @@ struct exynos5_dp { #define VIDEO_MODE_SLAVE_MODE (1 << 0) #define VIDEO_MODE_MASTER_MODE (0 << 0)
-#define HW_TRAINING_ERROR_CODE (7<<4) -#define HW_TRAINING_EN (1<<0) +#define HW_TRAINING_ERROR_CODE (7<<4) +#define HW_TRAINING_EN (1<<0)
/* I2C EDID Chip ID, Slave Address */ #define I2C_EDID_DEVICE_ADDR 0x50 diff --git a/src/cpu/samsung/exynos5420/dsim.h b/src/cpu/samsung/exynos5420/dsim.h index 25015a2..b04f98f 100644 --- a/src/cpu/samsung/exynos5420/dsim.h +++ b/src/cpu/samsung/exynos5420/dsim.h @@ -103,7 +103,7 @@ struct exynos5_dsim { #define PLL_STABLE (1 << 31)
#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) -#define DSIM_STOP_STATE_CLK (1 << 8) -#define DSIM_TX_READY_HS_CLK (1 << 10) +#define DSIM_STOP_STATE_CLK (1 << 8) +#define DSIM_TX_READY_HS_CLK (1 << 10)
#endif diff --git a/src/cpu/samsung/exynos5420/fb.c b/src/cpu/samsung/exynos5420/fb.c index 760f5ee..06e6ae6 100644 --- a/src/cpu/samsung/exynos5420/fb.c +++ b/src/cpu/samsung/exynos5420/fb.c @@ -187,7 +187,7 @@ void exynos_fimd_disable(void) * return status */ static int s5p_dp_config_video(struct s5p_dp_device *dp, - struct video_info *video_info) + struct video_info *video_info) { int timeout = 0; struct exynos5_dp *base = dp->base; @@ -195,9 +195,9 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, s5p_dp_config_video_slave_mode(dp, video_info);
s5p_dp_set_video_color_format(dp, video_info->color_depth, - video_info->color_space, - video_info->dynamic_range, - video_info->ycbcr_coeff); + video_info->color_space, + video_info->dynamic_range, + video_info->ycbcr_coeff);
if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { printk(BIOS_DEBUG, "PLL is not locked yet.\n"); @@ -258,8 +258,8 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) return -ERR_DPCD_READ_ERROR1; } if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, - DPCD_ENHANCED_FRAME_EN | - (data & DPCD_LANE_COUNT_SET_MASK))) { + DPCD_ENHANCED_FRAME_EN | + (data & DPCD_LANE_COUNT_SET_MASK))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR1; } @@ -280,13 +280,13 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE);
if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - &data)) { + &data)) { printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR2; }
if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, - (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { + (u8)(data & ~DPCD_SCRAMBLING_DISABLED))) { printk(BIOS_DEBUG, "DPCD write error\n"); return -ERR_DPCD_WRITE_ERROR2; } @@ -334,7 +334,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) * return status */ static int s5p_dp_set_lane_lane_pre_emphasis(struct s5p_dp_device *dp, - int pre_emphasis, int lane) + int pre_emphasis, int lane) { u32 reg; struct exynos5_dp *base = dp->base; @@ -439,7 +439,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) if (s5p_dp_set_lane_lane_pre_emphasis(dp, - PRE_EMPHASIS_LEVEL_0, lane)) { + PRE_EMPHASIS_LEVEL_0, lane)) { printk(BIOS_DEBUG, "Unable to set pre emphasis level\n"); return -ERR_PRE_EMPHASIS_LEVELS; } @@ -457,14 +457,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", - dp->link_train.link_rate); + dp->link_train.link_rate); /* Not Retrying */ return -ERR_LINK_RATE_ABNORMAL; }
if (dp->link_train.lane_count == 0) { printk(BIOS_DEBUG, "Rx Max Lane count is abnormal :%x !\n", - dp->link_train.lane_count); + dp->link_train.lane_count); /* Not retrying */ return -ERR_MAX_LANE_COUNT_ABNORMAL; } @@ -529,7 +529,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) }
ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + dp->video_info->link_rate); if (ret) { printk(BIOS_ERR, "unable to do link train\n"); return ret; diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c index 2a93328..f58d002 100644 --- a/src/cpu/samsung/exynos5420/gpio.c +++ b/src/cpu/samsung/exynos5420/gpio.c @@ -53,7 +53,7 @@ static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = { };
/* This macro gets gpio pin offset from 0..7 */ -#define GPIO_BIT(x) ((x) & 0x7) +#define GPIO_BIT(x) ((x) & 0x7)
static struct gpio_bank *gpio_get_bank(unsigned int gpio) { diff --git a/src/cpu/samsung/exynos5420/gpio.h b/src/cpu/samsung/exynos5420/gpio.h index 0011904..d204cfc 100644 --- a/src/cpu/samsung/exynos5420/gpio.h +++ b/src/cpu/samsung/exynos5420/gpio.h @@ -479,7 +479,7 @@ void gpio_set_rate(int gpio, int mode); * * @param gpio GPIO to read * @return -1 if the value cannot be determined. Otherwise returns - * the corresponding MVL3 enum value. + * the corresponding MVL3 enum value. */ int gpio_read_mvl3(unsigned gpio);
@@ -549,11 +549,11 @@ int gpio_set_value(unsigned gpio, int value); * * Vpd | Vpu | MVL * ----------------- - * 0 | 0 | 0 + * 0 | 0 | 0 * ----------------- - * 0 | 1 | Z <-- floating input will follow internal pull up/down + * 0 | 1 | Z <-- floating input will follow internal pull up/down * ----------------- - * 1 | 1 | 1 + * 1 | 1 | 1 */ enum mvl3 { LOGIC_0, diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index 2268628..7d40b1b 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -186,8 +186,8 @@ static struct s3c24x0_i2c_bus i2c_buses[] = { * * @param i2c- pointer to the appropriate i2c register bank. * @return I2C_OK, if transmission was ACKED - * I2C_NACK, if transmission was NACKED - * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS + * I2C_NACK, if transmission was NACKED + * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS */
static int WaitForXfer(struct s3c24x0_i2c *i2c) @@ -366,19 +366,19 @@ static int hsi2c_check_transfer(struct exynos5_hsi2c *i2c) { uint32_t status = read32(&i2c->usi_trans_status); if (status & (HSI2C_TRANS_ABORT | HSI2C_NO_DEV_ACK | - HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) { + HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) { if (status & HSI2C_TRANS_ABORT) printk(BIOS_ERR, - "%s: Transaction aborted.\n", __func__); + "%s: Transaction aborted.\n", __func__); if (status & HSI2C_NO_DEV_ACK) printk(BIOS_ERR, - "%s: No ack from device.\n", __func__); + "%s: No ack from device.\n", __func__); if (status & HSI2C_NO_DEV) printk(BIOS_ERR, - "%s: No response from device.\n", __func__); + "%s: No response from device.\n", __func__); if (status & HSI2C_TIMEOUT_AUTO) printk(BIOS_ERR, - "%s: Transaction time out.\n", __func__); + "%s: Transaction time out.\n", __func__); return -1; } return !(status & HSI2C_MASTER_BUSY); @@ -556,10 +556,10 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, write32(chip, &i2c->iicds); if ((cmd_type == I2C_WRITE) || (addr && addr_len)) write32(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat); else write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat);
/* Wait for chip address to transmit. */ result = WaitForXfer(i2c); @@ -597,7 +597,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c,
/* Generate a re-START. */ write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); + &i2c->iicstat); ReadWriteByte(i2c); result = WaitForXfer(i2c); if (result != I2C_OK) @@ -608,8 +608,8 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, /* disable ACK for final READ */ if (i == data_len - 1) write32(readl(&i2c->iiccon) - & ~I2CCON_ACKGEN, - &i2c->iiccon); + & ~I2CCON_ACKGEN, + &i2c->iiccon); ReadWriteByte(i2c); result = WaitForXfer(i2c); data[i++] = read32(&i2c->iicds); diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h index 3c019d6..2a6e994 100644 --- a/src/cpu/samsung/exynos5420/power.h +++ b/src/cpu/samsung/exynos5420/power.h @@ -35,9 +35,9 @@ void power_enable_hw_thermal_trip(void); #define DPTX_PHY_ENABLE (1 << 0)
/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ -#define PMU_DEBUG_XXTI 0x1000 +#define PMU_DEBUG_XXTI 0x1000 /* Mask bit[12:8] for xxti clock selection */ -#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00
/* Power Management Unit register map */ struct exynos5_power { @@ -55,7 +55,7 @@ struct exynos5_power { uint32_t inform1; /* 0x0804 */ uint8_t reserved6[0x1f8]; uint32_t pmu_debug; /* 0x0A00*/ - uint8_t reserved7[0x2908]; + uint8_t reserved7[0x2908]; uint32_t ps_hold_ctrl; /* 0x330c */ } __attribute__ ((__packed__));
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index e89ed8e..12f5486 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -49,7 +49,7 @@ struct exynos5_phy_control; #define APLL_CON1_VAL (0x0020f300)
/* MPLL_CON1 */ -#define MPLL_CON1_VAL (0x0020f300) +#define MPLL_CON1_VAL (0x0020f300)
/* CPLL_CON1 */ #define CPLL_CON1_VAL (0x0020f300) @@ -89,11 +89,11 @@ struct exynos5_phy_control;
/* CLK_SRC_CPU */ /* 0 = MOUTAPLL, 1 = SCLKMPLL */ -#define MUX_HPM_SEL 1 -#define MUX_CPU_SEL 0 -#define MUX_APLL_SEL 1 +#define MUX_HPM_SEL 1 +#define MUX_CPU_SEL 0 +#define MUX_APLL_SEL 1
-#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \ | (MUX_CPU_SEL << 16) \ | (MUX_APLL_SEL))
@@ -104,47 +104,47 @@ struct exynos5_phy_control; #define DMC_MEMCONTROL_TP_DISABLE (0 << 4) #define DMC_MEMCONTROL_DSREF_DISABLE (0 << 5) #define DMC_MEMCONTROL_DSREF_ENABLE (1 << 5) -#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6) +#define DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(x) (x << 6)
#define DMC_MEMCONTROL_MEM_TYPE_LPDDR3 (7 << 8) -#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) +#define DMC_MEMCONTROL_MEM_TYPE_DDR3 (6 << 8) #define DMC_MEMCONTROL_MEM_TYPE_LPDDR2 (5 << 8)
#define DMC_MEMCONTROL_MEM_WIDTH_32BIT (2 << 12)
-#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) -#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_1 (0 << 16) +#define DMC_MEMCONTROL_NUM_CHIP_2 (1 << 16)
-#define DMC_MEMCONTROL_BL_8 (3 << 20) -#define DMC_MEMCONTROL_BL_4 (2 << 20) +#define DMC_MEMCONTROL_BL_8 (3 << 20) +#define DMC_MEMCONTROL_BL_4 (2 << 20)
-#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24) +#define DMC_MEMCONTROL_PZQ_DISABLE (0 << 24)
-#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) -#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_7_0 (0 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_15_8 (1 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_23_16 (2 << 25) +#define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)
/* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) #define DMC_MEMCONFIG_CHIP_MAP_SPLIT (2 << 12) -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) - -#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) -#define DMC_MEMBASECONFIG_VAL(x) ( \ - DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ - DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ +#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0) + +#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMBASECONFIG_VAL(x) ( \ + DMC_MEMBASECONFIGx_CHIP_BASE(x) | \ + DMC_MEMBASECONFIGx_CHIP_MASK(0x780) \ )
#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) #define DMC_MEMBASECONFIG1_VAL DMC_MEMBASECONFIG_VAL(0x80)
-#define DMC_PRECHCONFIG_VAL 0xFF000000 -#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF +#define DMC_PRECHCONFIG_VAL 0xFF000000 +#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
#define DMC_CONCONTROL_RESET_VAL 0x0FFF0000 #define DFI_INIT_START (1 << 28) @@ -171,46 +171,46 @@ struct exynos5_phy_control; #define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
/* CLK_FSYS */ -#define CLK_SRC_FSYS0_VAL 0x33033300 -#define CLK_DIV_FSYS0_VAL 0x0 -#define CLK_DIV_FSYS1_VAL 0x04f13c4f -#define CLK_DIV_FSYS2_VAL 0x041d0000 +#define CLK_SRC_FSYS0_VAL 0x33033300 +#define CLK_DIV_FSYS0_VAL 0x0 +#define CLK_DIV_FSYS1_VAL 0x04f13c4f +#define CLK_DIV_FSYS2_VAL 0x041d0000
/* CLK_DIV_CPU1 */ -#define HPM_RATIO 0x2 -#define COPY_RATIO 0x0 +#define HPM_RATIO 0x2 +#define COPY_RATIO 0x0
/* CLK_DIV_CPU1 = 0x00000003 */ -#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \ | (COPY_RATIO))
/* CLK_SRC_CORE0 */ -#define CLK_SRC_CORE0_VAL 0x00000000 +#define CLK_SRC_CORE0_VAL 0x00000000
/* CLK_SRC_CORE1 */ -#define CLK_SRC_CORE1_VAL 0x100 +#define CLK_SRC_CORE1_VAL 0x100
/* CLK_DIV_CORE0 */ -#define CLK_DIV_CORE0_VAL 0x00120000 +#define CLK_DIV_CORE0_VAL 0x00120000
/* CLK_DIV_CORE1 */ -#define CLK_DIV_CORE1_VAL 0x07070700 +#define CLK_DIV_CORE1_VAL 0x07070700
/* CLK_DIV_SYSRGT */ -#define CLK_DIV_SYSRGT_VAL 0x00000111 +#define CLK_DIV_SYSRGT_VAL 0x00000111
/* CLK_DIV_ACP */ -#define CLK_DIV_ACP_VAL 0x12 +#define CLK_DIV_ACP_VAL 0x12
/* CLK_DIV_SYSLFT */ -#define CLK_DIV_SYSLFT_VAL 0x00000311 +#define CLK_DIV_SYSLFT_VAL 0x00000311
/* CLK_SRC_CDREX */ -#define CLK_SRC_CDREX_VAL 0x00000001 +#define CLK_SRC_CDREX_VAL 0x00000001 #define MUX_MCLK_CDR_MSPLL (1 << 4) -#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) -#define BPLL_SEL_MASK 0x7 -#define FOUTBPLL 2 +#define MUX_BPLL_SEL_FOUTBPLL (1 << 0) +#define BPLL_SEL_MASK 0x7 +#define FOUTBPLL 2
/* CLK_DIV_CDREX */ #define CLK_DIV_CDREX0_VAL 0x30010100 @@ -282,19 +282,19 @@ struct exynos5_phy_control; #define TOP2_VAL 0x0110000
/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_KFC */ #define SRC_KFC_HPM_SEL (1 << 15) @@ -421,19 +421,19 @@ struct exynos5_phy_control; #define MMC3_PRE_RATIO_OFFSET 24
/* CLK_SRC_LEX */ -#define CLK_SRC_LEX_VAL 0x0 +#define CLK_SRC_LEX_VAL 0x0
/* CLK_DIV_LEX */ -#define CLK_DIV_LEX_VAL 0x10 +#define CLK_DIV_LEX_VAL 0x10
/* CLK_DIV_R0X */ -#define CLK_DIV_R0X_VAL 0x10 +#define CLK_DIV_R0X_VAL 0x10
/* CLK_DIV_L0X */ -#define CLK_DIV_R1X_VAL 0x10 +#define CLK_DIV_R1X_VAL 0x10
/* CLK_DIV_ISP2 */ -#define CLK_DIV_ISP2_VAL 0x1 +#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_DISP1_0 */ #define CLK_SRC_DISP1_0_VAL 0x10666600 diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c index 1c60378..8413b31 100644 --- a/src/cpu/samsung/exynos5420/spi.c +++ b/src/cpu/samsung/exynos5420/spi.c @@ -125,12 +125,12 @@ static inline void exynos_spi_flush_fifo(struct exynos_spi *regs) }
static void exynos_spi_request_bytes(struct exynos_spi *regs, int count, - int width) + int width) { uint32_t mode_word = SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD, swap_word = (SPI_TX_SWAP_EN | SPI_RX_SWAP_EN | - SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | - SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP); + SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP | + SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
/* For word address we need to swap bytes */ if (width == sizeof(uint32_t)) { @@ -170,7 +170,7 @@ static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, step = 1; } else if ((rx_bytes | tx_bytes | (uintptr_t)rxp |(uintptr_t)txp) & 3) { printk(BIOS_CRIT, "%s: WARNING: tranfer mode decreased to 1B\n", - __func__); + __func__); step = 1; } else { step = sizeof(uint32_t); @@ -190,7 +190,7 @@ static int spi_rx_tx(struct spi_slave *slave, uint8_t *rxp, int rx_bytes, int rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK, tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK; int min_tx = ((tx_bytes || !espi->half_duplex) ? - (espi->fifo_size / 2) : 1); + (espi->fifo_size / 2) : 1);
// TODO(hungte) Abort if timeout happens in half-duplex mode.
@@ -334,7 +334,7 @@ void spi_release_bus(struct spi_slave *slave) /* Reset swap mode to make sure no one relying on default values (Ex, * payload or kernel) will go wrong. */ clrbits_le32(®s->mode_cfg, (SPI_MODE_CH_WIDTH_WORD | - SPI_MODE_BUS_WIDTH_WORD)); + SPI_MODE_BUS_WIDTH_WORD)); writel(0, ®s->swap_cfg); exynos_spi_flush_fifo(regs); } @@ -386,8 +386,8 @@ static void *exynos_spi_cbfs_unmap(struct cbfs_media *media, }
int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size) { + void *buffer_address, + size_t buffer_size) { // TODO Replace static variable to support multiple streams. static struct exynos_spi_media context; static struct exynos_spi_slave eslave = { diff --git a/src/cpu/samsung/exynos5420/spi.h b/src/cpu/samsung/exynos5420/spi.h index 94b4fda..445ebf0 100644 --- a/src/cpu/samsung/exynos5420/spi.h +++ b/src/cpu/samsung/exynos5420/spi.h @@ -88,6 +88,6 @@ struct exynos_spi {
/* Serve as CBFS media source */ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media, - void *buffer_address, - size_t buffer_size); + void *buffer_address, + size_t buffer_size); #endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index de71b80..f9c227d 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -165,7 +165,7 @@ static void exynos5_uart_tx_byte(unsigned char data) #if !defined(__PRE_RAM__)
static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, + .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, // .tx_flush = exynos5_uart_tx_flush, .rx_byte = exynos5_uart_rx_byte, diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h index 1b7d635..87b785b 100644 --- a/src/cpu/samsung/exynos5420/usb.h +++ b/src/cpu/samsung/exynos5420/usb.h @@ -20,41 +20,41 @@ #ifndef CPU_SAMSUNG_EXYNOS5420_USB_H #define CPU_SAMSUNG_EXYNOS5420_USB_H
-#define CLK_24MHZ 5 +#define CLK_24MHZ 5
-#define HOST_CTRL0_PHYSWRSTALL (1 << 31) -#define HOST_CTRL0_COMMONON_N (1 << 9) -#define HOST_CTRL0_SIDDQ (1 << 6) -#define HOST_CTRL0_FORCESLEEP (1 << 5) -#define HOST_CTRL0_FORCESUSPEND (1 << 4) -#define HOST_CTRL0_WORDINTERFACE (1 << 3) -#define HOST_CTRL0_UTMISWRST (1 << 2) -#define HOST_CTRL0_LINKSWRST (1 << 1) -#define HOST_CTRL0_PHYSWRST (1 << 0) +#define HOST_CTRL0_PHYSWRSTALL (1 << 31) +#define HOST_CTRL0_COMMONON_N (1 << 9) +#define HOST_CTRL0_SIDDQ (1 << 6) +#define HOST_CTRL0_FORCESLEEP (1 << 5) +#define HOST_CTRL0_FORCESUSPEND (1 << 4) +#define HOST_CTRL0_WORDINTERFACE (1 << 3) +#define HOST_CTRL0_UTMISWRST (1 << 2) +#define HOST_CTRL0_LINKSWRST (1 << 1) +#define HOST_CTRL0_PHYSWRST (1 << 0)
-#define HOST_CTRL0_FSEL_MASK (7 << 16) +#define HOST_CTRL0_FSEL_MASK (7 << 16)
-#define EHCICTRL_ENAINCRXALIGN (1 << 29) -#define EHCICTRL_ENAINCR4 (1 << 28) -#define EHCICTRL_ENAINCR8 (1 << 27) -#define EHCICTRL_ENAINCR16 (1 << 26) +#define EHCICTRL_ENAINCRXALIGN (1 << 29) +#define EHCICTRL_ENAINCR4 (1 << 28) +#define EHCICTRL_ENAINCR8 (1 << 27) +#define EHCICTRL_ENAINCR16 (1 << 26)
/* Register map for PHY control */ struct usb_phy { - uint32_t usbphyctrl0; - uint32_t usbphytune0; - uint32_t reserved1[2]; - uint32_t hsicphyctrl1; - uint32_t hsicphytune1; - uint32_t reserved2[2]; - uint32_t hsicphyctrl2; - uint32_t hsicphytune2; - uint32_t reserved3[2]; - uint32_t ehcictrl; - uint32_t ohcictrl; - uint32_t usbotgsys; - uint32_t reserved4; - uint32_t usbotgtune; + uint32_t usbphyctrl0; + uint32_t usbphytune0; + uint32_t reserved1[2]; + uint32_t hsicphyctrl1; + uint32_t hsicphytune1; + uint32_t reserved2[2]; + uint32_t hsicphyctrl2; + uint32_t hsicphytune2; + uint32_t reserved3[2]; + uint32_t ehcictrl; + uint32_t ohcictrl; + uint32_t usbotgsys; + uint32_t reserved4; + uint32_t usbotgtune; };
void usb_init(device_t dev); diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..c036a4e 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -24,7 +24,7 @@ get_header_size= \ $(word 4,$(omap_header_info)))))
$(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom - @printf " CC $(subst $(obj)/,,$(@))\n" + @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -include $(obj)/config.h \ -Wl,--defsym,header_load_size=$(strip \ $(call get_header_size,$(obj)/coreboot.rom, \ @@ -35,7 +35,7 @@ $(obj)/omap-header.bin: $$(omap-header-objs) $$(header_ld) $(obj)/coreboot.rom $(OBJCOPY) --only-section=".header" -O binary $@.tmp $@
$(obj)/MLO: $(obj)/coreboot.rom $(obj)/omap-header.bin - @printf " HEADER $(subst $(obj)/,,$(@))\n" + @printf " HEADER $(subst $(obj)/,,$(@))\n" $(Q)cat $(obj)/omap-header.bin $(obj)/coreboot.rom > $@
omap-header-y += header.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c index 553fe42..09fe077 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -55,7 +55,7 @@ int init_default_cbfs_media(struct cbfs_media *media) { struct cbfs_header *header = (struct cbfs_header *)((uintptr_t)CONFIG_BOOTBLOCK_BASE + - CONFIG_CBFS_HEADER_ROM_OFFSET); + CONFIG_CBFS_HEADER_ROM_OFFSET);
if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 5ed943e..7d40872 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -57,8 +57,8 @@ struct omap_image_headers headers __attribute__((section(".header"))) = { .size = 0xffffffff, .reserved = { 0xffffffff, 0xffffffff, 0xffffffff }, .filename = { 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff } + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff } }, .chsettings = { .key = 0xc0c0c0c1, diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c index ddab389..5203d09e 100644 --- a/src/cpu/ti/am335x/nand.c +++ b/src/cpu/ti/am335x/nand.c @@ -21,6 +21,6 @@
int init_default_cbfs_media(struct cbfs_media *media) { - /* FIXME: add support for reading coreboot from NAND */ + /* FIXME: add support for reading coreboot from NAND */ return 0; } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index bd2ff44..cfcf2db 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -180,7 +180,7 @@ uint32_t uartmem_getbaseaddr(void)
#if !defined(__PRE_RAM__) static const struct console_driver exynos5_uart_console __console = { - .init = am335x_uart_init_dev, + .init = am335x_uart_init_dev, .tx_byte = am335x_uart_tx_byte, .rx_byte = am335x_uart_rx_byte, }; diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 7d94384..ad65165 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -37,7 +37,7 @@ static void c3_init(device_t dev) };
static struct device_operations cpu_dev_ops = { - .init = c3_init, + .init = c3_init, };
static struct cpu_device_id cpu_table[] = { @@ -48,6 +48,6 @@ static struct cpu_device_id cpu_table[] = { };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 510e66d..2eecd73 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -34,28 +34,28 @@ #define MSR_IA32_MISC_ENABLE 0x000001a0
static int c7a_speed_translation[] = { -// LFM HFM - 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M +// LFM HFM + 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV + 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV };
static int c7d_speed_translation[] = { -// LFM HFM - 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M +// LFM HFM + 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V - 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV + 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV @@ -107,7 +107,7 @@ static void set_c7_speed(int model) { for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) { if ((c7a_speed_translation[i] == current) && ((c7a_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { + (msr.hi & 0xff00))) { new = c7a_speed_translation[i + 1]; } } @@ -116,7 +116,7 @@ static void set_c7_speed(int model) { for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) { if ((c7d_speed_translation[i] == current) && ((c7d_speed_translation[i + 1] & 0xff00) == - (msr.hi & 0xff00))) { + (msr.hi & 0xff00))) { new = c7d_speed_translation[i + 1]; } } diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..327a745 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -212,8 +212,8 @@ testok:
/* * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we - * get STACK up, we restore that. It is only needed if we - * want to go back. + * get STACK up, we restore that. It is only needed if we + * want to go back. */
/* We don't need CAR from now on. */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 417119f..ec5602a 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -48,7 +48,7 @@ static void nano_finish_fid_vid_transition(void) cnt++; if (cnt > 128) { printk(BIOS_WARNING, - "Error while updating multiplier and voltage\n"); + "Error while updating multiplier and voltage\n"); break; } } while (msr.lo & ((1 << 16) | (1 << 17))); @@ -73,9 +73,9 @@ static void nano_set_max_fid_vid(void) u8 cur_fid = (msr.lo >> 8) & 0xff;
printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", - cur_fid, min_fid, max_fid); - printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", - cur_vid, min_vid, max_vid); + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid);
if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { /* Set highest frequency and VID */ diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7471928..5b9fd36 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -48,7 +48,7 @@ static void nano_print_ucode_info(const nano_ucode_header *ucode) printk(BIOS_SPEW, "Microcode update information:\n"); printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, - ucode->day, ucode->year ); + ucode->day, ucode->year ); }
static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h index ae58fb2..e4c25d7 100644 --- a/src/cpu/via/nano/update_ucode.h +++ b/src/cpu/via/nano/update_ucode.h @@ -22,21 +22,21 @@ #include <console/console.h> #include <cpu/cpu.h>
-#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 -#define MSR_IA32_BIOS_SIGN_ID 0x0000008b -#define MSR_UCODE_UPDATE_STATUS 0x00001205 +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205
-#define NANO_UCODE_SIGNATURE 0x53415252 -#define NANO_UCODE_HEADER_SIZE 0x30 +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30
/* These are values returned by the CPU after we attempt microcode updates. * We care what these values are exactly, so we define them to be sure */ typedef enum { - UCODE_UPDATE_NOT_ATTEMPTED = 0x0, - UCODE_UPDATE_SUCCESS = 0x1, - UCODE_UPDATE_FAIL = 0x2, - UCODE_UPDATE_WRONG_CPU = 0x3, - UCODE_INVALID_UPDATE_BLOCK = 0x4, + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, } ucode_update_status;
@@ -48,19 +48,19 @@ typedef enum { } ucode_validity;
typedef struct { - u32 signature; /* NANO_UCODE_SIGNATURE */ - u32 update_revision; /* Revision of the update header */ - u16 year; /* Year of patch release */ - u8 day; /* Day of patch release */ - u8 month; /* Month of patch release */ - u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ - u32 checksum; /* Two's complement checksum of ucode+header */ - u32 loader_revision; /* Revision of hardware ucode update loader*/ - u32 rfu_1; /* Reserved for future use */ - u32 payload_size; /* Size of the ucode payload only */ - u32 total_size; /* Size of the ucode, including header */ - char name[8]; /* ASCII string of ucode filename */ - u32 rfu_2; /* Reserved for future use */ + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reserved for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reserved for future use */ /* First double-word of the ucode payload * Its address represents the beginning of the ucode update we need to * send to the CPU */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e4613bf..7f609b1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -20,7 +20,7 @@ * it with the version available from LANL. * * Copyright (C) 2000, Ron Minnich rminnich@lanl.gov - * Advanced Computing Lab, LANL + * Advanced Computing Lab, LANL */
diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index 1be0e3a..62ca1e8 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -3,7 +3,7 @@ .globl reset_vector reset_vector: .byte 0xe9 - .int _start - ( . + 2 ) + .int _start - ( . + 2 ) /* Note: The above jump is hand coded to work around bugs in binutils. * 5 byte are used for a 3 byte instruction. This works because x86 * is little endian and allows us to use supported 32bit relocations diff --git a/src/cpu/x86/16bit/reset16.lds b/src/cpu/x86/16bit/reset16.lds index a31a580..8f7388c 100644 --- a/src/cpu/x86/16bit/reset16.lds +++ b/src/cpu/x86/16bit/reset16.lds @@ -1,5 +1,5 @@ /* - * _ROMTOP : The top of the rom used where we + * _ROMTOP : The top of the rom used where we * need to put the reset vector. */
diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 481153d..7bd623e 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -36,7 +36,7 @@ extern char _car_data_end[]; * been migrated to real RAM. It does this by assuming the following things: * 1. cache-as-ram space is zero'd out once it is set up. * 2. Either the cache-as-ram space is memory-backed after getting torn down - * or the space returns 0xff's for each byte read. + * or the space returns 0xff's for each byte read. * Based on these 2 attributes there is the ability to tell when the * cache-as-ram region has been migrated. */ @@ -57,8 +57,8 @@ void *car_get_var_ptr(void *var)
if (var < _car_start || var >= _car_end) { printk(BIOS_ERR, - "Requesting CAR variable outside of CAR region: %p\n", - var); + "Requesting CAR variable outside of CAR region: %p\n", + var); return var; }
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 868fb92..c6c70bc 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -133,8 +133,8 @@ void timer_monotonic_get(struct mono_time *mt) * around occurs. */ if (timer_fsb > 200) printk(BIOS_WARNING, - "apic timer freq (%d) may be too fast.\n", - timer_fsb); + "apic timer freq (%d) may be too fast.\n", + timer_fsb); mono_counter.last_value = lapic_read(LAPIC_TMCCT); mono_counter.initialized = 1; } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 555187f..40b3106 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -536,11 +536,11 @@ void initialize_cpus(struct bus *cpu_bus) enable_lapic();
/* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_APIC; + cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else /* Get the device path of the boot cpu */ - cpu_path.type = DEVICE_PATH_CPU; + cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; #endif
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index 6edcd0a..a9a2119 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -31,8 +31,8 @@ _secondary_start: /* This will get filled in by C code. */ _secondary_gdt_addr: gdtaddr: - .word 0 /* the table limit */ - .long 0 /* we know the offset */ + .word 0 /* the table limit */ + .long 0 /* we know the offset */
_secondary_start_end:
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index f16da27..2bad816 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -57,7 +57,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) * Determine address by calculating the XIP_ROM_SIZE sized area with * XIP_ROM_SIZE alignment that contains the global variable defined above; */ - unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); + unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d168978..3ae7fce 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -48,7 +48,7 @@ /* 2 MTRRS are reserved for the operating system */ #define BIOS_MTRRS 6 #define OS_MTRRS 2 -#define MTRRS (BIOS_MTRRS + OS_MTRRS) +#define MTRRS (BIOS_MTRRS + OS_MTRRS)
static int total_mtrrs = MTRRS; static int bios_mtrrs = BIOS_MTRRS; @@ -88,9 +88,9 @@ static inline unsigned int fms(unsigned int x) int r;
__asm__("bsrl %1,%0\n\t" - "jnz 1f\n\t" - "movl $0,%0\n" - "1:" : "=r" (r) : "g" (x)); + "jnz 1f\n\t" + "movl $0,%0\n" + "1:" : "=r" (r) : "g" (x)); return r; }
@@ -100,9 +100,9 @@ static inline unsigned int fls(unsigned int x) int r;
__asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $32,%0\n" - "1:" : "=r" (r) : "g" (x)); + "jnz 1f\n\t" + "movl $32,%0\n" + "1:" : "=r" (r) : "g" (x)); return r; }
@@ -175,7 +175,7 @@ static struct memranges *get_physical_address_space(void) * regions. */ memranges_init(addr_space, mask, mask, MTRR_TYPE_WRBACK); memranges_add_resources(addr_space, mask, 0, - MTRR_TYPE_UNCACHEABLE); + MTRR_TYPE_UNCACHEABLE);
/* Handle any write combining resources. Only prefetchable * resources with the IORESOURCE_WRCOMB flag are appropriate @@ -183,7 +183,7 @@ static struct memranges *get_physical_address_space(void) match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; mask |= match; memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + MTRR_TYPE_WRCOMB);
#if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size @@ -192,7 +192,7 @@ static struct memranges *get_physical_address_space(void) resource_t rom_base = RANGE_TO_PHYS_ADDR( RANGE_4GB - PHYS_TO_RANGE_ADDR(CONFIG_ROM_SIZE)); memranges_insert(addr_space, rom_base, CONFIG_ROM_SIZE, - MTRR_TYPE_WRPROT); + MTRR_TYPE_WRPROT); #endif
/* The address space below 4GiB is special. It needs to be @@ -201,15 +201,15 @@ static struct memranges *get_physical_address_space(void) * Therefore, ensure holes are filled up to 4GiB as * uncacheable */ memranges_fill_holes_up_to(addr_space, - RANGE_TO_PHYS_ADDR(RANGE_4GB), - MTRR_TYPE_UNCACHEABLE); + RANGE_TO_PHYS_ADDR(RANGE_4GB), + MTRR_TYPE_UNCACHEABLE);
printk(BIOS_DEBUG, "MTRR: Physical address space:\n"); memranges_each_entry(r, addr_space) printk(BIOS_DEBUG, - "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", - range_entry_base(r), range_entry_end(r), - range_entry_size(r), range_entry_tag(r)); + "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", + range_entry_base(r), range_entry_end(r), + range_entry_size(r), range_entry_tag(r)); }
return addr_space; @@ -284,8 +284,8 @@ static void calc_fixed_mtrrs(void)
type = range_entry_tag(r); printk(MTRR_VERBOSE_LEVEL, - "MTRR addr 0x%x-0x%x set to %d type @ %d\n", - begin, begin + desc->step, type, type_index); + "MTRR addr 0x%x-0x%x set to %d type @ %d\n", + begin, begin + desc->step, type, type_index); if (type == MTRR_TYPE_WRBACK) type |= MTRR_FIXED_WRBACK_BITS; fixed_mtrr_types[type_index] = type; @@ -345,7 +345,7 @@ static void commit_fixed_mtrrs(void)
for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) { printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", - msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); + msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); wrmsr(msr_index[i], fixed_msrs[i]); }
@@ -415,9 +415,9 @@ static void disable_cache_rom(void *unused)
BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), + disable_cache_rom, NULL), BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), + disable_cache_rom, NULL), }; #endif
@@ -440,7 +440,7 @@ static void clear_var_mtrr(int index) }
static void write_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint32_t base, uint32_t size, int mtrr_type) { msr_t msr_val; unsigned long msr_index; @@ -480,7 +480,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, #endif
printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", - var_state->mtrr_index, rbase, rsize, mtrr_type); + var_state->mtrr_index, rbase, rsize, mtrr_type);
msr_val.lo = rbase; msr_val.lo |= mtrr_type; @@ -497,7 +497,7 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, }
static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + uint32_t base, uint32_t size, int mtrr_type) { while (size != 0) { uint32_t addr_lsb; @@ -525,7 +525,7 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, }
static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, - struct range_entry *r) + struct range_entry *r) { uint32_t a1, a2, b1, b2; int mtrr_type; @@ -536,7 +536,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, * +------------------+ b2 = ALIGN_UP(end) * | 0 or more bytes | <-- hole is carved out between b1 and b2 * +------------------+ a2 = b1 = end - * | | + * | | * +------------------+ a1 = begin * * Thus, there are 3 sub-ranges to configure variable MTRRs for. @@ -603,7 +603,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, }
static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, - struct range_entry *r) + struct range_entry *r) { uint32_t a1, a2, b1, b2, c1, c2; int mtrr_type; @@ -614,7 +614,7 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, * +------------------+ c2 = end * | 0 or more bytes | * +------------------+ b2 = c1 = ALIGN_DOWN(end) - * | | + * | | * +------------------+ b1 = a2 = ALIGN_UP(begin) * | 0 or more bytes | * +------------------+ a1 = begin @@ -662,7 +662,7 @@ static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, }
static int calc_var_mtrrs(struct memranges *addr_space, - int above4gb, int address_bits) + int above4gb, int address_bits) { int wb_deftype_count; int uc_deftype_count; @@ -740,7 +740,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, }
printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", - wb_deftype_count, uc_deftype_count); + wb_deftype_count, uc_deftype_count);
if (wb_deftype_count < uc_deftype_count) { printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); @@ -751,7 +751,7 @@ static int calc_var_mtrrs(struct memranges *addr_space, }
static void commit_var_mtrrs(struct memranges *addr_space, int def_type, - int above4gb, int address_bits) + int above4gb, int address_bits) { struct range_entry *r; struct var_mtrr_state var_state; @@ -797,7 +797,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
disable_cache(); commit_var_mtrrs(addr_space, mtrr_default_type, !!above4gb, - address_bits); + address_bits); enable_var_mtrr(mtrr_default_type); enable_cache(); } diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index b595a36..14de34a 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -42,7 +42,7 @@ $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf $(OBJCOPY) -O binary $< $@
$(obj)/cpu/x86/smm/smmstub.ramstage.o: $(obj)/cpu/x86/smm/smmstub - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
# C-based SMM handler. @@ -57,7 +57,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf $(OBJCOPY) -O binary $< $@
$(obj)/cpu/x86/smm/smm.ramstage.o: $(obj)/cpu/x86/smm/smm - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(dir $@); $(OBJCOPY) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@)
else # CONFIG_SMM_MODULES @@ -92,7 +92,7 @@ $(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_L # change to the target path because objcopy will use the path name in its # ELF symbol names. $(obj)/cpu/x86/smm/smm_wrap.ramstage.o: $(obj)/cpu/x86/smm/smm_wrap - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" cd $(obj)/cpu/x86/smm; $(OBJCOPY) -I binary smm -O elf32-i386 -B i386 smm_wrap.ramstage.o
endif # CONFIG_SMM_MODULES diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index fc30909..6cf1450 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -69,7 +69,7 @@ void io_trap_handler(int smif) /* If a handler function handled a given IO trap, it * shall return a non-zero value */ - printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif); + printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
if (southbridge_io_trap_handler(smif)) return; @@ -167,7 +167,7 @@ void smi_handler(u32 smm_revision) state_save.type = EM64T101; state_save.em64t101_state_save = smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); + SMM_EM64T101_ARCH_OFFSET, node); break; case 0x00030064: state_save.type = AMD64; diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 444e335..f778dd4 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -123,7 +123,7 @@ void smm_handler_start(void *arg, int cpu, const struct smm_runtime *runtime) if (cpu >= CONFIG_MAX_CPUS) { console_init(); printk(BIOS_CRIT, - "Invalid CPU number assigned in SMM stub: %d\n", cpu); + "Invalid CPU number assigned in SMM stub: %d\n", cpu); return; }
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 478ae8c..6c24e99 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -72,7 +72,7 @@ struct smm_entry_ins { * other entry points are stride size below the previous. */ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, - void *jmp_target) + void *jmp_target) { int i; char *cur; @@ -91,8 +91,8 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num,
disp -= sizeof(entry) + (uint32_t)cur; printk(BIOS_DEBUG, - "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", - cur, disp); + "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", + cur, disp); entry.rel16 = disp; memcpy(cur, &entry, sizeof(entry)); cur -= stride; @@ -102,7 +102,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, /* Place stacks in base -> base + size region, but ensure the stacks don't * overlap the staggered entry points. */ static void *smm_stub_place_stacks(char *base, int size, - struct smm_loader_params *params) + struct smm_loader_params *params) { int total_stack_size; char *stacks_top; @@ -113,7 +113,7 @@ static void *smm_stub_place_stacks(char *base, int size, /* If stack space is requested assume the space lives in the lower * half of SMRAM. */ total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; + params->num_concurrent_stacks;
/* There has to be at least one stack user. */ if (params->num_concurrent_stacks < 1) @@ -153,9 +153,9 @@ static void smm_stub_place_staggered_entry_points(char *base, num_entries--; } smm_place_jmp_instructions(base, - params->per_cpu_save_state_size, - num_entries, - rmodule_entry(smm_stub)); + params->per_cpu_save_state_size, + num_entries, + rmodule_entry(smm_stub)); } }
@@ -197,7 +197,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params)
/* Adjust remaining size to account for save state. */ total_save_state_size = params->per_cpu_save_state_size * - params->num_concurrent_save_states; + params->num_concurrent_save_states; size -= total_save_state_size;
/* The save state size encroached over the first SMM entry point. */ @@ -272,7 +272,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) params->runtime = &stub_params->runtime;
printk(BIOS_DEBUG, "SMM Module: stub loaded at %p. Will call %p(%p)\n", - smm_stub_loc, params->handler, params->handler_arg); + smm_stub_loc, params->handler, params->handler_arg);
return 0; } @@ -307,13 +307,13 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) /* The SMM module is placed within the provided region in the following * manner: * +-----------------+ <- smram + size - * | stacks | + * | stacks | * +-----------------+ <- smram + size - total_stack_size - * | ... | + * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE - * | handler | + * | handler | * +-----------------+ <- smram + SMM_DEFAULT_SIZE - * | stub code | + * | stub code | * +-----------------+ <- smram * * It should be noted that this algorithm will not work for @@ -338,7 +338,7 @@ int smm_load_module(void *smram, int size, struct smm_loader_params *params) return -1;
total_stack_size = params->per_cpu_stack_size * - params->num_concurrent_stacks; + params->num_concurrent_stacks;
/* Stacks start at the top of the region. */ base = smram; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 07eb5dc..adc92ea 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -67,7 +67,7 @@ smm_handler_start:
movl %cr0, %eax andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ + orl $0x1, %eax /* PE = 1 */ movl %eax, %cr0
/* Enable protected mode */ diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..f94cfd8 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -28,26 +28,26 @@
/* * +--------------------------------+ 0xaffff - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | * +--------------------------------+ 0xaf000 - * | | - * | | - * | | + * | | + * | | + * | | * +--------------------------------+ 0xa8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0xa8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | * +--------------------------------+ 0xa7400 - * | | - * | SMM Handler | - * | | + * | | + * | SMM Handler | + * | | * +--------------------------------+ 0xa0000 * */ @@ -76,16 +76,16 @@ * All the bad magic is not all that bad after all. */ smm_handler_start: - movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx + movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx)
- movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 + movl %cr0, %eax + andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x60000001, %eax /* CD, NW, PE = 1 */ + movl %eax, %cr0
/* Enable protected mode */ - data32 ljmp $0x08, $1f + data32 ljmp $0x08, $1f
.code32 1: @@ -93,12 +93,12 @@ smm_handler_start: wbinvd
/* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs
/* Get this CPU's LAPIC ID */ movl $LAPIC_ID, %esi diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index fdc5053..6b52ba3 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -21,30 +21,30 @@
/* * +--------------------------------+ - * | SMM Handler C Code | + * | SMM Handler C Code | * +--------------------------------+ 0x14000 - * | SMM Handler Heap | + * | SMM Handler Heap | * +--------------------------------+ 0x10000 - * | Save State Map Node 0 | - * | Save State Map Node 1 | - * | Save State Map Node 2 | - * | Save State Map Node 3 | - * | ... | + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | * +--------------------------------+ 0xf000 - * | | - * | | - * | EARLY DATA (lock, vectors) | + * | | + * | | + * | EARLY DATA (lock, vectors) | * +--------------------------------+ 0x8400 - * | SMM Entry Node 0 (+ stack) | + * | SMM Entry Node 0 (+ stack) | * +--------------------------------+ 0x8000 - * | SMM Entry Node 1 (+ stack) | - * | SMM Entry Node 2 (+ stack) | - * | SMM Entry Node 3 (+ stack) | - * | ... | + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | * +--------------------------------+ 0x7400 - * | | - * | SMM Handler Assembly Stub | - * | | + * | | + * | SMM Handler Assembly Stub | + * | | * +--------------------------------+ TSEG * */ @@ -132,14 +132,14 @@ smm_check_gdt_vector: addr32 movl %ebx, (%eax)
smm_load_gdt: - movl $(smm_gdt_vector), %ebx - addl %edx, %ebx /* TSEG base in %edx */ + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ data32 lgdt (%ebx)
- movl %cr0, %eax - andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ - orl $0x1, %eax /* PE = 1 */ - movl %eax, %cr0 + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0
/* Enable protected mode */ movl $(smm_prot_vector), %eax @@ -149,12 +149,12 @@ smm_load_gdt: .code32 smm_prot_start: /* Use flat data segment */ - movw $0x10, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs
/* Get this CPU's LAPIC ID */ movl $LAPIC_ID, %esi diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index a0a5d18..93c0b30 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -100,9 +100,9 @@ * 13 0x9cc00 0xa4c00 0xac900 * 14 0x9c800 0xa4800 0xac500 * 15 0x9c400 0xa4400 0xac100 - * . . . . - * . . . . - * . . . . + * . . . . + * . . . . + * . . . . * 31 0x98400 0xa0400 0xa8100 * * With 32 cores, the SMM handler would need to fit between @@ -123,7 +123,7 @@ smm_relocation_start: * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 * Intel SandyBridge: 0x30101 - * AMD64: 0x3XX64 + * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. */ diff --git a/src/device/agp_device.c b/src/device/agp_device.c index 550297a..6465c3a 100644 --- a/src/device/agp_device.c +++ b/src/device/agp_device.c @@ -65,11 +65,11 @@ static struct pci_operations agp_bus_ops_pci = {
struct device_operations default_agp_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = agp_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &agp_bus_ops_pci, + .init = 0, + .scan_bus = agp_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &agp_bus_ops_pci, }; diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index cbc878d..95d86d6 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -257,7 +257,7 @@ void azalia_audio_init(struct device *dev)
if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", - codec_mask); + codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index f25f96c..0613b69 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -106,7 +106,7 @@ void cardbus_read_resources(device_t dev)
/* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_0, IORESOURCE_IO); + PCI_CB_IO_BASE_0, IORESOURCE_IO); cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
/* See which bridge I/O resources are implemented. */ @@ -116,7 +116,7 @@ void cardbus_read_resources(device_t dev)
/* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, - PCI_CB_IO_BASE_1, IORESOURCE_IO); + PCI_CB_IO_BASE_1, IORESOURCE_IO);
/* If I can, enable prefetch for mem0. */ ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); @@ -136,7 +136,7 @@ void cardbus_read_resources(device_t dev) if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) type |= IORESOURCE_PREFETCH; cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_0, type); + PCI_CB_MEMORY_BASE_0, type); if (type & IORESOURCE_PREFETCH) cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
@@ -147,7 +147,7 @@ void cardbus_read_resources(device_t dev)
/* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, - PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); + PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
compact_resources(dev); @@ -175,10 +175,10 @@ void cardbus_enable_resources(device_t dev)
struct device_operations default_cardbus_ops_bus = { .read_resources = cardbus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, }; diff --git a/src/device/device.c b/src/device/device.c index 8bde663..d5142e8 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -16,7 +16,7 @@ */
/* - * (c) 1999--2000 Martin Mares mj@suse.cz + * (c) 1999--2000 Martin Mares mj@suse.cz */
/* @@ -201,7 +201,7 @@ static void read_resources(struct bus *bus) struct device *curdev;
printk(BIOS_SPEW, "%s %s bus %x link: %d\n", dev_path(bus->dev), - __func__, bus->secondary, bus->link_num); + __func__, bus->secondary, bus->link_num);
/* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -212,7 +212,7 @@ static void read_resources(struct bus *bus)
if (!curdev->ops || !curdev->ops->read_resources) { printk(BIOS_ERR, "%s missing read_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } curdev->ops->read_resources(curdev); @@ -222,7 +222,7 @@ static void read_resources(struct bus *bus) read_resources(link); } printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num); }
struct pick_largest_state { @@ -249,9 +249,9 @@ static void pick_largest_resource(void *gp, struct device *dev, return; /* Skip it. */ if (last && ((last->align < resource->align) || ((last->align == resource->align) && - (last->size < resource->size)) || + (last->size < resource->size)) || ((last->align == resource->align) && - (last->size == resource->size) && (!state->seen_last)))) { + (last->size == resource->size) && (!state->seen_last)))) { return; } if (!state->result || @@ -264,9 +264,9 @@ static void pick_largest_resource(void *gp, struct device *dev, }
static struct device *largest_resource(struct bus *bus, - struct resource **result_res, - unsigned long type_mask, - unsigned long type) + struct resource **result_res, + unsigned long type_mask, + unsigned long type) { struct pick_largest_state state;
@@ -276,7 +276,7 @@ static struct device *largest_resource(struct bus *bus, state.seen_last = 0;
search_bus_resources(bus, type_mask, type, pick_largest_resource, - &state); + &state);
*result_res = state.result; return state.result_dev; @@ -316,7 +316,7 @@ static struct device *largest_resource(struct bus *bus, * @return TODO */ static void compute_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) + unsigned long type_mask, unsigned long type) { struct device *dev; struct resource *resource; @@ -324,10 +324,10 @@ static void compute_resources(struct bus *bus, struct resource *bridge, base = round(bridge->base, bridge->align);
printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, - bridge->gran, bridge->limit); + " limit: %llx\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", base, bridge->size, bridge->align, + bridge->gran, bridge->limit);
/* For each child which is a bridge, compute the resource needs. */ for (dev = bus->children; dev; dev = dev->sibling) { @@ -359,8 +359,8 @@ static void compute_resources(struct bus *bus, struct resource *bridge,
if (link == NULL) { printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); + IOINDEX_LINK(child_bridge->index), + dev_path(dev)); }
compute_resources(link, child_bridge, @@ -396,9 +396,9 @@ static void compute_resources(struct bus *bus, struct resource *bridge, if ((resource->limit == 0xffffffff) && (resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, - "Resource limit looks wrong! (no APIC?)\n"); + "Resource limit looks wrong! (no APIC?)\n"); printk(BIOS_ERR, "%s %02lx limit %08llx\n", - dev_path(dev), resource->index, resource->limit); + dev_path(dev), resource->index, resource->limit); }
if (resource->flags & IORESOURCE_IO) { @@ -426,11 +426,11 @@ static void compute_resources(struct bus *bus, struct resource *bridge, base += resource->size;
printk(BIOS_SPEW, "%s %02lx * [0x%llx - 0x%llx] %s\n", - dev_path(dev), resource->index, resource->base, - resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" : - (resource->flags & IORESOURCE_PREFETCH) ? - "prefmem" : "mem"); + dev_path(dev), resource->index, resource->base, + resource->base + resource->size - 1, + (resource->flags & IORESOURCE_IO) ? "io" : + (resource->flags & IORESOURCE_PREFETCH) ? + "prefmem" : "mem"); }
/* @@ -440,13 +440,13 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * address positively decoded by the bridge. */ bridge->size = round(base, bridge->gran) - - round(bridge->base, bridge->align); + round(bridge->base, bridge->align);
printk(BIOS_SPEW, "%s %s_%s: base: %llx size: %llx align: %d gran: %d" - " limit: %llx done\n", dev_path(bus->dev), __func__, - (bridge->flags & IORESOURCE_IO) ? "io" : - (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran, bridge->limit); + " limit: %llx done\n", dev_path(bus->dev), __func__, + (bridge->flags & IORESOURCE_IO) ? "io" : + (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit); }
/** @@ -464,7 +464,7 @@ static void compute_resources(struct bus *bus, struct resource *bridge, * @see compute_resources */ static void allocate_resources(struct bus *bus, struct resource *bridge, - unsigned long type_mask, unsigned long type) + unsigned long type_mask, unsigned long type) { struct device *dev; struct resource *resource; @@ -472,10 +472,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, base = bridge->base;
printk(BIOS_SPEW, "%s %s_%s: base:%llx size:%llx align:%d gran:%d " - "limit:%llx\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", - base, bridge->size, bridge->align, bridge->gran, bridge->limit); + "limit:%llx\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", + base, bridge->size, bridge->align, bridge->gran, bridge->limit);
/* Remember we haven't found anything yet. */ resource = NULL; @@ -528,29 +528,29 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, base += resource->size; } else { printk(BIOS_ERR, "!! Resource didn't fit !!\n"); - printk(BIOS_ERR, " aligned base %llx size %llx " - "limit %llx\n", round(base, resource->align), - resource->size, resource->limit); - printk(BIOS_ERR, " %llx needs to be <= %llx " - "(limit)\n", (round(base, resource->align) + + printk(BIOS_ERR, " aligned base %llx size %llx " + "limit %llx\n", round(base, resource->align), + resource->size, resource->limit); + printk(BIOS_ERR, " %llx needs to be <= %llx " + "(limit)\n", (round(base, resource->align) + resource->size) - 1, resource->limit); - printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" - " %s\n", (resource->flags & IORESOURCE_ASSIGNED) - ? "Assigned: " : "", dev_path(dev), - resource->index, resource->base, - resource->base + resource->size - 1, - (resource->flags & IORESOURCE_IO) ? "io" - : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + printk(BIOS_ERR, " %s%s %02lx * [0x%llx - 0x%llx]" + " %s\n", (resource->flags & IORESOURCE_ASSIGNED) + ? "Assigned: " : "", dev_path(dev), + resource->index, resource->base, + resource->base + resource->size - 1, + (resource->flags & IORESOURCE_IO) ? "io" + : (resource->flags & IORESOURCE_PREFETCH) + ? "prefmem" : "mem"); }
printk(BIOS_SPEW, "%s%s %02lx * [0x%llx - 0x%llx] %s\n", - (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " - : "", dev_path(dev), resource->index, resource->base, - resource->size ? resource->base + resource->size - 1 : - resource->base, (resource->flags & IORESOURCE_IO) - ? "io" : (resource->flags & IORESOURCE_PREFETCH) - ? "prefmem" : "mem"); + (resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: " + : "", dev_path(dev), resource->index, resource->base, + resource->size ? resource->base + resource->size - 1 : + resource->base, (resource->flags & IORESOURCE_IO) + ? "io" : (resource->flags & IORESOURCE_PREFETCH) + ? "prefmem" : "mem"); }
/* @@ -563,10 +563,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, bridge->flags |= IORESOURCE_ASSIGNED;
printk(BIOS_SPEW, "%s %s_%s: next_base: %llx size: %llx align: %d " - "gran: %d done\n", dev_path(bus->dev), __func__, - (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? - "prefmem" : "mem", base, bridge->size, bridge->align, - bridge->gran); + "gran: %d done\n", dev_path(bus->dev), __func__, + (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ? + "prefmem" : "mem", base, bridge->size, bridge->align, + bridge->gran);
/* For each child which is a bridge, allocate_resources. */ for (dev = bus->children; dev; dev = dev->sibling) { @@ -593,17 +593,17 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, */ link = dev->link_list; while (link && link->link_num != - IOINDEX_LINK(child_bridge->index)) + IOINDEX_LINK(child_bridge->index)) link = link->next; if (link == NULL) printk(BIOS_ERR, "link %ld not found on %s\n", - IOINDEX_LINK(child_bridge->index), - dev_path(dev)); + IOINDEX_LINK(child_bridge->index), + dev_path(dev));
allocate_resources(link, child_bridge, - type_mask | IORESOURCE_PREFETCH, - type | (child_bridge->flags & - IORESOURCE_PREFETCH)); + type_mask | IORESOURCE_PREFETCH, + type | (child_bridge->flags & + IORESOURCE_PREFETCH)); } } } @@ -614,10 +614,10 @@ static void allocate_resources(struct bus *bus, struct resource *bridge, #define MEM_MASK (IORESOURCE_MEM) #endif
-#define IO_MASK (IORESOURCE_IO) +#define IO_MASK (IORESOURCE_IO) #define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM) #define MEM_TYPE (IORESOURCE_MEM) -#define IO_TYPE (IORESOURCE_IO) +#define IO_TYPE (IORESOURCE_IO)
struct constraints { struct resource pref, io, mem; @@ -639,7 +639,7 @@ static void constrain_resources(struct device *dev, struct constraints* limits) if (!res->size) { /* It makes no sense to have 0-sized, fixed resources.*/ printk(BIOS_ERR, "skipping %s@%lx fixed resource, " - "size=0!\n", dev_path(dev), res->index); + "size=0!\n", dev_path(dev), res->index); continue; }
@@ -703,7 +703,7 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & IORESOURCE_FIXED)) continue; printk(BIOS_SPEW, "%s:@%s %02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); + dev_path(dev), res->index, res->limit); if ((res->flags & MEM_MASK) == PREF_TYPE && (res->limit < limits.pref.limit)) limits.pref.limit = res->limit; @@ -736,9 +736,9 @@ static void avoid_fixed_resources(struct device *dev) continue;
printk(BIOS_SPEW, "%s2: %s@%02lx limit %08llx\n", __func__, - dev_path(dev), res->index, res->limit); + dev_path(dev), res->index, res->limit); printk(BIOS_SPEW, "\tlim->base %08llx lim->limit %08llx\n", - lim->base, lim->limit); + lim->base, lim->limit);
/* Is the resource outside the limits? */ if (lim->base > res->base) @@ -808,7 +808,7 @@ static void set_vga_bridge_bits(void) /* Now walk up the bridges setting the VGA enable. */ while (bus) { printk(BIOS_DEBUG, "Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", - dev_path(bus->dev)); + dev_path(bus->dev)); bus->bridge_ctrl |= PCI_BRIDGE_CTL_VGA; bus = (bus == bus->dev->bus) ? 0 : bus->dev->bus; } @@ -832,7 +832,7 @@ void assign_resources(struct bus *bus) struct device *curdev;
printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num);
for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -840,7 +840,7 @@ void assign_resources(struct bus *bus)
if (!curdev->ops || !curdev->ops->set_resources) { printk(BIOS_ERR, "%s missing set_resources\n", - dev_path(curdev)); + dev_path(curdev)); continue; } post_log_path(curdev); @@ -848,7 +848,7 @@ void assign_resources(struct bus *bus) } post_log_clear(); printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n", - dev_path(bus->dev), bus->secondary, bus->link_num); + dev_path(bus->dev), bus->secondary, bus->link_num); }
/** @@ -1078,17 +1078,17 @@ void dev_configure(void) continue; if (res->flags & IORESOURCE_PREFETCH) { allocate_resources(child->link_list, - res, MEM_MASK, PREF_TYPE); + res, MEM_MASK, PREF_TYPE); continue; } if (res->flags & IORESOURCE_MEM) { allocate_resources(child->link_list, - res, MEM_MASK, MEM_TYPE); + res, MEM_MASK, MEM_TYPE); continue; } if (res->flags & IORESOURCE_IO) { allocate_resources(child->link_list, - res, IO_MASK, IO_TYPE); + res, IO_MASK, IO_TYPE); continue; } } @@ -1142,7 +1142,7 @@ static void init_dev(struct device *dev) #endif if (dev->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(dev->bus->dev), dev->bus->link_num); + dev_path(dev->bus->dev), dev->bus->link_num); }
printk(BIOS_DEBUG, "%s init\n", dev_path(dev)); @@ -1151,7 +1151,7 @@ static void init_dev(struct device *dev) #if CONFIG_HAVE_MONOTONIC_TIMER dev_init_time = current_time_from(&start_time); printk(BIOS_DEBUG, "%s init %ld usecs\n", dev_path(dev), - rela_time_in_microseconds(&dev_init_time)); + rela_time_in_microseconds(&dev_init_time)); #endif } } diff --git a/src/device/device_util.c b/src/device/device_util.c index cad2a06..74a5f82 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -35,7 +35,7 @@ * @param parent The bus to find the device on. * @param path The relative path from the bus to the appropriate device. * @return Pointer to a device structure for the device on bus at path - * or 0/NULL if no device is found. + * or 0/NULL if no device is found. */ device_t find_dev_path(struct bus *parent, struct device_path *path) { @@ -119,8 +119,8 @@ device_t dev_find_lapic(unsigned apic_id) * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel). * @param device A PCI device ID. * @param from Pointer to the device structure, used as a starting point in - * the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices). + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). * @return Pointer to the device struct. */ struct device *dev_find_device(u16 vendor, u16 device, struct device *from) @@ -141,8 +141,8 @@ struct device *dev_find_device(u16 vendor, u16 device, struct device *from) * * @param class Class of the device. * @param from Pointer to the device structure, used as a starting point in - * the linked list of all_devices, which can be 0 to start at the - * head of the list (i.e. all_devices). + * the linked list of all_devices, which can be 0 to start at the + * head of the list (i.e. all_devices). * @return Pointer to the device struct. */ struct device *dev_find_class(unsigned int class, struct device *from) @@ -276,7 +276,7 @@ const char *dev_path(device_t dev) break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", - dev->path.type); + dev->path.type); break; } } @@ -497,7 +497,7 @@ struct resource *find_resource(device_t dev, unsigned index) resource = probe_resource(dev, index); if (!resource) { printk(BIOS_EMERG, "%s missing resource: %02x\n", - dev_path(dev), index); + dev_path(dev), index); die(""); } return resource; @@ -625,7 +625,7 @@ void report_resource_stored(device_t dev, struct resource *resource, #endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " - "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, + "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, resource->size, resource->gran, buf, resource_type(resource), comment); } @@ -652,14 +652,14 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, if (res->flags & IORESOURCE_SUBTRACTIVE) { struct bus * subbus; for (subbus = curdev->link_list; subbus; - subbus = subbus->next) + subbus = subbus->next) if (subbus->link_num == IOINDEX_SUBTRACTIVE_LINK(res->index)) break; if (!subbus) /* Why can subbus be NULL? */ break; search_bus_resources(subbus, type_mask, type, - search, gp); + search, gp); continue; } search(gp, curdev, res); @@ -668,7 +668,7 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask, }
void search_global_resources(unsigned long type_mask, unsigned long type, - resource_search_t search, void *gp) + resource_search_t search, void *gp) { struct device *curdev;
@@ -760,7 +760,7 @@ void print_resource_tree(struct device *root, int debug_level, const char *msg)
/* Bail if not printing to screen. */ if (!do_printk(debug_level, "Show resources in subtree (%s)...%s\n", - dev_path(root), msg)) + dev_path(root), msg)) return;
resource_tree(root, debug_level, 0); @@ -799,7 +799,7 @@ void show_devs_subtree(struct device *root, int debug_level, const char *msg) { /* Bail if not printing to screen. */ if (!do_printk(debug_level, "Show all devs in subtree %s...%s\n", - dev_path(root), msg)) + dev_path(root), msg)) return; do_printk(debug_level, "%s\n", msg); show_devs_tree(root, debug_level, 0, -1); @@ -819,7 +819,7 @@ void show_all_devs(int debug_level, const char *msg) }
void show_one_resource(int debug_level, struct device *dev, - struct resource *resource, const char *comment) + struct resource *resource, const char *comment) { char buf[10]; unsigned long long base, end; @@ -896,7 +896,7 @@ u32 find_pci_tolm(struct bus *bus) u32 tolm;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, - tolm_test, &min); + tolm_test, &min);
tolm = 0xffffffffUL;
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index d98de91..404eba8 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -56,7 +56,7 @@ int dimm_is_registered(enum spd_dimm_type type) * array, and passed to this function. * * @param dimm pointer to @ref dimm_attr structure where the decoded data is to - * be stored + * be stored * @param spd array of raw data previously read from the SPD. * * @return @ref spd_status enumerator @@ -207,7 +207,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) ret = SPD_STATUS_INVALID_FIELD; } bus_width = 8 << val; - printram(" Bus width : %u\n", bus_width); + printram(" Bus width : %u\n", bus_width);
/* We have all the info we need to compute the dimm size */ /* Capacity is 256Mbit multiplied by the power of 2 specified in @@ -345,12 +345,12 @@ void dram_print_spd_ddr3(const dimm_attr * dimm)
printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); - printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); - printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb);
/* CAS Latencies Supported */ val16 = dimm->cas_supported; - printk(BIOS_INFO, " CAS latencies :"); + printk(BIOS_INFO, " CAS latencies :"); i = 0; do { if (val16 & 1) @@ -360,18 +360,18 @@ void dram_print_spd_ddr3(const dimm_attr * dimm) } while (val16); printk(BIOS_INFO, "\n");
- print_ns(" tCKmin : ", dimm->tCK); - print_ns(" tAAmin : ", dimm->tAA); - print_ns(" tWRmin : ", dimm->tWR); - print_ns(" tRCDmin : ", dimm->tRCD); - print_ns(" tRRDmin : ", dimm->tRRD); - print_ns(" tRPmin : ", dimm->tRP); - print_ns(" tRASmin : ", dimm->tRAS); - print_ns(" tRCmin : ", dimm->tRC); - print_ns(" tRFCmin : ", dimm->tRFC); - print_ns(" tWTRmin : ", dimm->tWTR); - print_ns(" tRTPmin : ", dimm->tRTP); - print_ns(" tFAWmin : ", dimm->tFAW); + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tAAmin : ", dimm->tAA); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tFAWmin : ", dimm->tFAW); }
/*============================================================================== @@ -430,12 +430,12 @@ static u16 ddr3_cas_to_mr0_map(u8 cas) * @param cas CAS latency in clock cycles. */ mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type burst_type, - enum ddr3_mr0_burst_length burst_length) + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type burst_type, + enum ddr3_mr0_burst_length burst_length) { mrs_cmd_t cmd = 0 << 16;
@@ -493,12 +493,12 @@ static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) * \brief Get command address for a DDR3 MR1 command */ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods ods, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable) + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods ods, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable) { mrs_cmd_t cmd = 1 << 16;
@@ -532,8 +532,8 @@ mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, * @param cas_cwl CAS write latency in clock cycles. */ mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl) + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, u8 cas_cwl) { mrs_cmd_t cmd = 2 << 16;
@@ -554,7 +554,7 @@ mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, * \brief Get command address for a DDR3 MR3 command * * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read - * leveling mode. Zero for normal operation. + * leveling mode. Zero for normal operation. */ mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) { @@ -578,8 +578,8 @@ mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) { u32 downshift, upshift; - /* High bits= A4 | A6 | A8 | BA1 */ - /* Low bits = A3 | A5 | A7 | BA0 */ + /* High bits= A4 | A6 | A8 | BA1 */ + /* Low bits = A3 | A5 | A7 | BA0 */ u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); downshift = (cmd & (lowbits << 1)); upshift = (cmd & lowbits); diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index d9ab486..cb96dd4 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -53,8 +53,8 @@ static device_t ht_scan_get_devs(device_t *old_devices) * hypertransport device. */ while (last && last->sibling && - (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.pci.devfn > last->path.pci.devfn)) + (last->sibling->path.type == DEVICE_PATH_PCI) && + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } @@ -154,14 +154,14 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
if (!linkb_to_host) { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; + cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0; cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; + cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0; cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0; } else { - cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; + cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1; cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1; - cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; + cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1; cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1; }
@@ -207,8 +207,8 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) new_freq &= 0x0f; if (new_freq != freq) { printk(BIOS_ERR, "%s Hypertransport frequency would " - "not set. Wanted: %x, got: %x\n", - dev_path(dev), freq, new_freq); + "not set. Wanted: %x, got: %x\n", + dev_path(dev), freq, new_freq); } } old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1); @@ -218,13 +218,13 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) present_width); reset_needed = 1; printk(BIOS_SPEW, "HyperT widthP old %x new %x\n", - old_width, present_width); + old_width, present_width); new_width = pci_read_config8(cur->dev, - cur->pos + cur->config_off + 1); + cur->pos + cur->config_off + 1); if (new_width != present_width) { printk(BIOS_ERR, "%s Hypertransport width would not " - "set. Wanted: %x, got: %x\n", - dev_path(dev), present_width, new_width); + "set. Wanted: %x, got: %x\n", + dev_path(dev), present_width, new_width); } }
@@ -236,14 +236,14 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq); reset_needed = 1; printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", - old_freq, freq); + old_freq, freq); new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off); new_freq &= 0x0f; if (new_freq != freq) { printk(BIOS_ERR, "%s Hypertransport frequency would " - "not set. Wanted: %x, got: %x\n", - dev_path(prev->dev), freq, new_freq); + "not set. Wanted: %x, got: %x\n", + dev_path(prev->dev), freq, new_freq); } } old_width = @@ -254,13 +254,13 @@ static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos) upstream_width); reset_needed = 1; printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, - upstream_width); + upstream_width); new_width = pci_read_config8(prev->dev, - prev->pos + prev->config_off + 1); + prev->pos + prev->config_off + 1); if (new_width != upstream_width) { printk(BIOS_ERR, "%s Hypertransport width would not " - "set. Wanted: %x, got: %x\n", - dev_path(prev->dev), upstream_width, new_width); + "set. Wanted: %x, got: %x\n", + dev_path(prev->dev), upstream_width, new_width); } } #endif @@ -317,9 +317,9 @@ static void ht_collapse_early_enumeration(struct bus *bus, /* Initialize the hypertransport enumeration state. */ prev.dev = bus->dev; prev.pos = bus->cap; - prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; + prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; + prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* Wait until the link initialization is complete. */ @@ -339,12 +339,12 @@ static void ht_collapse_early_enumeration(struct bus *bus, */ ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */ pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, - ctrl); + ctrl); ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { printk(BIOS_ALERT, "Detected error on " - "Hypertransport link\n"); + "Hypertransport link\n"); return; } } @@ -405,14 +405,14 @@ static void ht_collapse_early_enumeration(struct bus *bus, flags &= ~0x1f; pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags); printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n", - dev_path(&dummy), dummy.vendor, dummy.device); + dev_path(&dummy), dummy.vendor, dummy.device); } }
unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max, - unsigned *ht_unitid_base, - unsigned offset_unitid) + unsigned max_devfn, unsigned int max, + unsigned *ht_unitid_base, + unsigned offset_unitid) { /* * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this @@ -427,7 +427,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - /* + /* * Let's record the device of last HT device, so we can set the unitid * to CONFIG_HT_CHAIN_END_UNITID_BASE. */ @@ -447,9 +447,9 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, prev.dev = bus->dev; prev.pos = bus->cap;
- prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; + prev.ctrl_off = PCI_HT_CAP_HOST_CTRL; prev.config_off = PCI_HT_CAP_HOST_WIDTH; - prev.freq_off = PCI_HT_CAP_HOST_FREQ; + prev.freq_off = PCI_HT_CAP_HOST_FREQ; prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* If present, assign unitid to a hypertransport chain. */ @@ -485,7 +485,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, prev.pos + prev.ctrl_off); if (ctrl & ((1 << 4) | (1 << 8))) { printk(BIOS_ALERT, "Detected error on " - "hypertransport link\n"); + "hypertransport link\n"); goto end_of_chain; } } @@ -504,7 +504,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, pos = ht_lookup_slave_capability(dev); if (pos == 0) { printk(BIOS_ERR, "%s Hypertransport link capability " - "not found", dev_path(dev)); + "not found", dev_path(dev)); break; }
@@ -528,7 +528,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */ if (next_unitid > (max_devfn >> 3)) { if (!end_used) { - next_unitid = + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { @@ -546,13 +546,13 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, for (func = dev; func; func = func->sibling) { func->path.pci.devfn += (next_unitid << 3); static_count = (func->path.pci.devfn >> 3) - - (dev->path.pci.devfn >> 3) + 1; + - (dev->path.pci.devfn >> 3) + 1; last_func = func; }
/* Compute the number of unitids consumed. */ printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n", - dev_path(dev), count, static_count); + dev_path(dev), count, static_count); if (count < static_count) count = static_count;
@@ -575,8 +575,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, bus->reset_needed |= ht_setup_link(&prev, dev, pos);
printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n", - dev_path(dev), dev->vendor, dev->device, - (dev->enabled? "enabled" : "disabled"), next_unitid); + dev_path(dev), dev->vendor, dev->device, + (dev->enabled? "enabled" : "disabled"), next_unitid);
} while (last_unitid != next_unitid);
@@ -611,7 +611,7 @@ end_of_chain: ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE;
printk(BIOS_DEBUG, " unitid: %04x --> %04x\n", - real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); + real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE); } #endif next_unitid = max_unitid; @@ -632,7 +632,7 @@ end_of_chain: printk(BIOS_DEBUG, "%s\n", dev_path(left));
printk(BIOS_ERR, "HT: Leftover static devices. " - "Check your devicetree.cb\n"); + "Check your devicetree.cb\n");
/* * Put back the leftover static device, and let pci_scan_bus() @@ -682,11 +682,11 @@ static struct pci_operations ht_bus_ops_pci = {
struct device_operations default_ht_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = ht_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &ht_bus_ops_pci, + .init = 0, + .scan_bus = ht_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &ht_bus_ops_pci, }; diff --git a/src/device/oprom/include/x86emu/fpu_regs.h b/src/device/oprom/include/x86emu/fpu_regs.h index 7c7df85..4085e61 100644 --- a/src/device/oprom/include/x86emu/fpu_regs.h +++ b/src/device/oprom/include/x86emu/fpu_regs.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for FPU register definitions. * @@ -46,16 +46,16 @@ /* Basic 8087 register can hold any of the following values: */
union x86_fpu_reg_u { - s8 tenbytes[10]; - double dval; - float fval; - s16 sval; - s32 lval; + s8 tenbytes[10]; + double dval; + float fval; + s16 sval; + s32 lval; };
struct x86_fpu_reg { union x86_fpu_reg_u reg; - char tag; + char tag; };
/* @@ -67,24 +67,24 @@ struct x86_fpu_reg { * attempt the conversion. */
-#define X86_FPU_VALID 0x80 -#define X86_FPU_REGTYP(r) ((r) & 0x7F) +#define X86_FPU_VALID 0x80 +#define X86_FPU_REGTYP(r) ((r) & 0x7F)
-#define X86_FPU_WORD 0x0 -#define X86_FPU_SHORT 0x1 -#define X86_FPU_LONG 0x2 -#define X86_FPU_FLOAT 0x3 -#define X86_FPU_DOUBLE 0x4 -#define X86_FPU_LDBL 0x5 -#define X86_FPU_BSD 0x6 +#define X86_FPU_WORD 0x0 +#define X86_FPU_SHORT 0x1 +#define X86_FPU_LONG 0x2 +#define X86_FPU_FLOAT 0x3 +#define X86_FPU_DOUBLE 0x4 +#define X86_FPU_LDBL 0x5 +#define X86_FPU_BSD 0x6
#define X86_FPU_STKTOP 0
struct x86_fpu_registers { struct x86_fpu_reg x86_fpu_stack[8]; - int x86_fpu_flags; - int x86_fpu_config; /* rounding modes, etc. */ - short x86_fpu_tos, x86_fpu_bos; + int x86_fpu_flags; + int x86_fpu_config; /* rounding modes, etc. */ + short x86_fpu_tos, x86_fpu_bos; };
#pragma pack() diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h index 4bf1294..eb2b75e 100644 --- a/src/device/oprom/include/x86emu/regs.h +++ b/src/device/oprom/include/x86emu/regs.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for x86 register definitions. * @@ -170,18 +170,18 @@ struct i386_segment_regs { #define R_GS seg.GS
/* flag conditions */ -#define FB_CF 0x0001 /* CARRY flag */ -#define FB_PF 0x0004 /* PARITY flag */ -#define FB_AF 0x0010 /* AUX flag */ -#define FB_ZF 0x0040 /* ZERO flag */ -#define FB_SF 0x0080 /* SIGN flag */ -#define FB_TF 0x0100 /* TRAP flag */ -#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define FB_DF 0x0400 /* DIR flag */ -#define FB_OF 0x0800 /* OVERFLOW flag */ +#define FB_CF 0x0001 /* CARRY flag */ +#define FB_PF 0x0004 /* PARITY flag */ +#define FB_AF 0x0010 /* AUX flag */ +#define FB_ZF 0x0040 /* ZERO flag */ +#define FB_SF 0x0080 /* SIGN flag */ +#define FB_TF 0x0100 /* TRAP flag */ +#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define FB_DF 0x0400 /* DIR flag */ +#define FB_OF 0x0800 /* OVERFLOW flag */
/* 80286 and above always have bit#1 set */ -#define F_ALWAYS_ON (0x0002) /* flag bits always on */ +#define F_ALWAYS_ON (0x0002) /* flag bits always on */
/* * Define a mask for only those flag bits we will ever pass back @@ -191,18 +191,18 @@ struct i386_segment_regs {
/* following bits masked in to a 16bit quantity */
-#define F_CF 0x0001 /* CARRY flag */ -#define F_PF 0x0004 /* PARITY flag */ -#define F_AF 0x0010 /* AUX flag */ -#define F_ZF 0x0040 /* ZERO flag */ -#define F_SF 0x0080 /* SIGN flag */ -#define F_TF 0x0100 /* TRAP flag */ -#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ -#define F_DF 0x0400 /* DIR flag */ -#define F_OF 0x0800 /* OVERFLOW flag */ +#define F_CF 0x0001 /* CARRY flag */ +#define F_PF 0x0004 /* PARITY flag */ +#define F_AF 0x0010 /* AUX flag */ +#define F_ZF 0x0040 /* ZERO flag */ +#define F_SF 0x0080 /* SIGN flag */ +#define F_TF 0x0100 /* TRAP flag */ +#define F_IF 0x0200 /* INTERRUPT ENABLE flag */ +#define F_DF 0x0400 /* DIR flag */ +#define F_OF 0x0800 /* OVERFLOW flag */
#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) -#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) @@ -210,42 +210,42 @@ struct i386_segment_regs { #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
-#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ -#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ -#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */
-#define F_ALL_CALC 0xff0000 /* All have been calced */ +#define F_ALL_CALC 0xff0000 /* All have been calced */
/* * Emulator machine state. * Segment usage control. */ -#define SYSMODE_SEG_DS_SS 0x00000001 -#define SYSMODE_SEGOVR_CS 0x00000002 -#define SYSMODE_SEGOVR_DS 0x00000004 -#define SYSMODE_SEGOVR_ES 0x00000008 -#define SYSMODE_SEGOVR_FS 0x00000010 -#define SYSMODE_SEGOVR_GS 0x00000020 -#define SYSMODE_SEGOVR_SS 0x00000040 -#define SYSMODE_PREFIX_REPE 0x00000080 -#define SYSMODE_PREFIX_REPNE 0x00000100 -#define SYSMODE_PREFIX_DATA 0x00000200 -#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 //phueper: for REP(E|NE) Instructions, we need to decide whether it should be //using the 32bit ECX register as or the 16bit CX register as count register -#define SYSMODE_32BIT_REP 0x00000800 -#define SYSMODE_INTR_PENDING 0x10000000 -#define SYSMODE_EXTRN_INTR 0x20000000 -#define SYSMODE_HALTED 0x40000000 +#define SYSMODE_32BIT_REP 0x00000800 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000
-#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ SYSMODE_SEGOVR_FS | \ SYSMODE_SEGOVR_GS | \ SYSMODE_SEGOVR_SS) -#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ SYSMODE_SEGOVR_CS | \ SYSMODE_SEGOVR_DS | \ SYSMODE_SEGOVR_ES | \ @@ -256,40 +256,40 @@ struct i386_segment_regs { SYSMODE_PREFIX_ADDR | \ SYSMODE_32BIT_REP)
-#define INTR_SYNCH 0x1 -#define INTR_ASYNCH 0x2 -#define INTR_HALTED 0x4 +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4
typedef struct { - struct i386_general_regs gen; - struct i386_special_regs spc; - struct i386_segment_regs seg; + struct i386_general_regs gen; + struct i386_special_regs spc; + struct i386_segment_regs seg; /* * MODE contains information on: - * REPE prefix 2 bits repe,repne - * SEGMENT overrides 5 bits normal,DS,SS,CS,ES - * Delayed flag set 3 bits (zero, signed, parity) - * reserved 6 bits - * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits - * Extern interrupt 1 bits - * Halted 1 bits + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits */ - u32 mode; - volatile int intr; /* mask of pending interrupts */ - volatile int debug; + u32 mode; + volatile int intr; /* mask of pending interrupts */ + volatile int debug; #if CONFIG_X86EMU_DEBUG - int check; - u16 saved_ip; - u16 saved_cs; - int enc_pos; - int enc_str_pos; - char decode_buf[32]; /* encoded byte stream */ - char decoded_buf[256]; /* disassembled strings */ + int check; + u16 saved_ip; + u16 saved_cs; + int enc_pos; + int enc_str_pos; + char decode_buf[32]; /* encoded byte stream */ + char decoded_buf[256]; /* disassembled strings */ #endif - u8 intno; - u8 __pad[3]; + u8 intno; + u8 __pad[3]; } X86EMU_regs;
/**************************************************************************** @@ -307,7 +307,7 @@ typedef struct { unsigned long mem_base; unsigned long mem_size; unsigned long abseg; - void* private; + void* private; X86EMU_regs x86; } X86EMU_sysEnv;
@@ -316,7 +316,7 @@ typedef struct { /*----------------------------- Global Variables --------------------------*/
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
/* Global emulator machine state. @@ -324,8 +324,8 @@ extern "C" { /* Use "C" linkage when in C++ mode */ * We keep it global to avoid pointer dereferences in the code for speed. */
-extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +extern X86EMU_sysEnv _X86EMU_env; +#define M _X86EMU_env
#define X86_EAX M.x86.R_EAX #define X86_EBX M.x86.R_EBX @@ -366,7 +366,7 @@ extern X86EMU_sysEnv _X86EMU_env; #define X86_DH M.x86.R_DH
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_REGS_H */ diff --git a/src/device/oprom/include/x86emu/types.h b/src/device/oprom/include/x86emu/types.h index bb6dab44..61de104 100644 --- a/src/device/oprom/include/x86emu/types.h +++ b/src/device/oprom/include/x86emu/types.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for x86 emulator type definitions. * diff --git a/src/device/oprom/include/x86emu/x86emu.h b/src/device/oprom/include/x86emu/x86emu.h index b912bd2..7ee1483 100644 --- a/src/device/oprom/include/x86emu/x86emu.h +++ b/src/device/oprom/include/x86emu/x86emu.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,11 +30,11 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for public specific functions. -* Any application linking against us should only -* include this header +* Any application linking against us should only +* include this header * ****************************************************************************/ /* $XFree86: xc/extras/x86emu/include/x86emu.h,v 1.2 2000/11/21 23:10:25 tsi Exp $ */ @@ -73,10 +73,10 @@ x86emu.h MEMBERS: inb - Function to read a byte from an I/O port inw - Function to read a word from an I/O port -inl - Function to read a dword from an I/O port +inl - Function to read a dword from an I/O port outb - Function to write a byte to an I/O port -outw - Function to write a word to an I/O port -outl - Function to write a dword to an I/O port +outw - Function to write a word to an I/O port +outl - Function to write a dword to an I/O port ****************************************************************************/ typedef struct { u8 (X86APIP inb)(X86EMU_pioAddr addr); @@ -104,7 +104,7 @@ x86emu.h MEMBERS: rdb - Function to read a byte from an address rdw - Function to read a word from an address -rdl - Function to read a dword from an address +rdl - Function to read a dword from an address wrb - Function to write a byte to an address wrw - Function to write a word to an address wrl - Function to write a dword to an address @@ -139,7 +139,7 @@ extern X86EMU_intrFuncs _X86EMU_intrTab[256]; /*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
void X86EMU_setupMemFuncs(X86EMU_memFuncs *funcs); @@ -164,25 +164,25 @@ void X86EMU_halt_sys(void);
/* Debug options */
-#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ -#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ -#define DEBUG_STEP_F 0x000004 -#define DEBUG_DISASSEMBLE_F 0x000008 -#define DEBUG_BREAK_F 0x000010 -#define DEBUG_SVC_F 0x000020 -#define DEBUG_FS_F 0x000080 -#define DEBUG_PROC_F 0x000100 -#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ -#define DEBUG_TRACECALL_F 0x000400 -#define DEBUG_INSTRUMENT_F 0x000800 -#define DEBUG_MEM_TRACE_F 0x001000 -#define DEBUG_IO_TRACE_F 0x002000 +#define DEBUG_DECODE_F 0x000001 /* print decoded instruction */ +#define DEBUG_TRACE_F 0x000002 /* dump regs before/after execution */ +#define DEBUG_STEP_F 0x000004 +#define DEBUG_DISASSEMBLE_F 0x000008 +#define DEBUG_BREAK_F 0x000010 +#define DEBUG_SVC_F 0x000020 +#define DEBUG_FS_F 0x000080 +#define DEBUG_PROC_F 0x000100 +#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */ +#define DEBUG_TRACECALL_F 0x000400 +#define DEBUG_INSTRUMENT_F 0x000800 +#define DEBUG_MEM_TRACE_F 0x001000 +#define DEBUG_IO_TRACE_F 0x002000 #define DEBUG_TRACECALL_REGS_F 0x004000 #define DEBUG_DECODE_NOPRINT_F 0x008000 -#define DEBUG_SAVE_IP_CS_F 0x010000 -#define DEBUG_TRACEJMP_F 0x020000 -#define DEBUG_TRACEJMP_REGS_F 0x040000 -#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F) +#define DEBUG_SAVE_IP_CS_F 0x010000 +#define DEBUG_TRACEJMP_F 0x020000 +#define DEBUG_TRACEJMP_REGS_F 0x040000 +#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F)
void X86EMU_trace_regs(void); void X86EMU_trace_xregs(void); @@ -191,7 +191,7 @@ int X86EMU_trace_on(void); int X86EMU_trace_off(void);
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_X86EMU_H */ diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 4385c03..b23f97b 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -272,8 +272,8 @@ void vbe_set_graphics(void) struct jpeg_decdata *decdata; decdata = malloc(sizeof(*decdata)); unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + "bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; @@ -458,10 +458,10 @@ int asmlinkage interrupt_handler(u32 intnumber, #if CONFIG_REALMODE_DEBUG printk(BIOS_DEBUG, "oprom: INT# 0x%x\n", intnumber); printk(BIOS_DEBUG, "oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n", - eax, ebx, ecx, edx); + eax, ebx, ecx, edx); printk(BIOS_DEBUG, "oprom: ebp: %08x esp: %08x edi: %08x esi: %08x\n", ebp, esp, edi, esi); - printk(BIOS_DEBUG, "oprom: ip: %04x cs: %04x flags: %08x\n", + printk(BIOS_DEBUG, "oprom: ip: %04x cs: %04x flags: %08x\n", ip, cs, flags); #endif
diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index 54cf374..aee895b 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -343,12 +343,12 @@ __interrupt_handler_16bit = RELOCATED(.) pushl %eax /* ... and make it the first parameter */
/* Switch to protected mode */ - movl %cr0, %eax + movl %cr0, %eax orl $PE, %eax movl %eax, %cr0
/* ... and jump to a 32 bit code segment. */ - data32 ljmp $0x10, $RELOCATED(1f) + data32 ljmp $0x10, $RELOCATED(1f) 1: .code32 mov $0x18, %ax diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 383c736..32a5e9e 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -81,7 +81,7 @@ int int10_handler(void) X86_EBX &= 0x00ff; res = 1; break; - default: + default: printk(BIOS_WARNING, "Unknown INT10 function %04x!\n", X86_EAX & 0xffff); break; @@ -107,7 +107,7 @@ int int16_handler(void) X86_EFLAGS |= 1<<6; // Zero Flag set (no key available) res = 1; break; - default: + default: printk(BIOS_WARNING, "Unknown INT16 function %04x!\n", X86_EAX & 0xffff); break; @@ -216,7 +216,7 @@ int int1a_handler(void)
#if CONFIG_REALMODE_DEBUG printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n", - func, bus, devfn, reg, X86_ECX); + func, bus, devfn, reg, X86_ECX); #endif X86_EAX &= 0xffff00ff; /* Clear AH */ X86_EAX |= PCIBIOS_SUCCESSFUL; diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index a3ede4a..39e5842 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -1,5 +1,5 @@ - License information - ------------------- + License information + -------------------
The x86emu library is under a BSD style license, comaptible with the XFree86 and X licenses used by XFree86. The diff --git a/src/device/oprom/x86emu/debug.c b/src/device/oprom/x86emu/debug.c index b3f4b6e..c80b3d0 100644 --- a/src/device/oprom/x86emu/debug.c +++ b/src/device/oprom/x86emu/debug.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file contains the code to handle debugging of the -* emulator. +* emulator. * ****************************************************************************/
@@ -43,31 +43,31 @@
#ifdef DEBUG
-static void print_encoded_bytes (u16 s, u16 o); -static void print_decoded_instruction (void); -int parse_line (char *s, int *ps, int *n); +static void print_encoded_bytes (u16 s, u16 o); +static void print_decoded_instruction (void); +int parse_line (char *s, int *ps, int *n);
/* should look something like debug's output. */ void X86EMU_trace_regs (void) { if (DEBUG_TRACE()) { if (M.x86.mode & (SYSMODE_PREFIX_DATA | SYSMODE_PREFIX_ADDR)) { - x86emu_dump_xregs(); + x86emu_dump_xregs(); } else { - x86emu_dump_regs(); + x86emu_dump_regs(); } } if (DEBUG_DECODE() && ! DEBUG_DECODE_NOPRINT()) { - printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); - print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); - print_decoded_instruction(); + printf("%04x:%04x ",M.x86.saved_cs, M.x86.saved_ip); + print_encoded_bytes( M.x86.saved_cs, M.x86.saved_ip); + print_decoded_instruction(); } }
void X86EMU_trace_xregs (void) { if (DEBUG_TRACE()) { - x86emu_dump_xregs(); + x86emu_dump_xregs(); } }
@@ -97,8 +97,8 @@ void disassemble_forward (u16 seg, u16 off, int n) * the preprocessor. The TRACE_REGS macro expands to: * * if (debug&DEBUG_DISASSEMBLE) - * {just_disassemble(); goto EndOfInstruction;} - * if (debug&DEBUG_TRACE) trace_regs(r,m); + * {just_disassemble(); goto EndOfInstruction;} + * if (debug&DEBUG_TRACE) trace_regs(r,m); * * ...... and at the last line of the routine. * @@ -131,8 +131,8 @@ void disassemble_forward (u16 seg, u16 off, int n) * Note the use of a copy of the register structure... */ for (i=0; i<n; i++) { - op1 = (*sys_rdb)(((u32)M.x86.R_CS<<4) + (M.x86.R_IP++)); - (x86emu_optab[op1])(op1); + op1 = (*sys_rdb)(((u32)M.x86.R_CS<<4) + (M.x86.R_IP++)); + (x86emu_optab[op1])(op1); } /* end major hack mode. */ } @@ -186,7 +186,7 @@ static void print_encoded_bytes (u16 s, u16 o) int i; char buf1[64]; for (i=0; i< M.x86.enc_pos; i++) { - sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); + sprintf(buf1+2*i,"%02x", fetch_data_byte_abs(s,o+i)); } printf("%-20s ",buf1); } @@ -201,8 +201,8 @@ void x86emu_print_int_vect (u16 iv) u16 seg,off;
if (iv > 256) return; - seg = fetch_data_word_abs(0,iv*4); - off = fetch_data_word_abs(0,iv*4+2); + seg = fetch_data_word_abs(0,iv*4); + off = fetch_data_word_abs(0,iv*4+2); printf("%04x:%04x ", seg, off); }
@@ -215,14 +215,14 @@ void X86EMU_dump_memory (u16 seg, u16 off, u32 amt)
current = start; while (end <= off + amt) { - printf("%04x:%04x ", seg, start); - for (i=start; i< off; i++) - printf(" "); - for ( ; i< end; i++) - printf("%02x ", fetch_data_byte_abs(seg,i)); - printf("\n"); - start = end; - end = start + 16; + printf("%04x:%04x ", seg, start); + for (i=start; i< off; i++) + printf(" "); + for ( ; i< end; i++) + printf("%02x ", fetch_data_byte_abs(seg,i)); + printf("\n"); + start = end; + end = start + 16; } }
@@ -234,88 +234,88 @@ void x86emu_single_step (void) int ntok; int cmd; int done; - int segment; + int segment; int offset; static int breakpoint; static int noDecode = 1;
char *p;
- if (DEBUG_BREAK()) { - if (M.x86.saved_ip != breakpoint) { - return; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - M.x86.debug |= DEBUG_TRACE_F; - M.x86.debug &= ~DEBUG_BREAK_F; - print_decoded_instruction (); - X86EMU_trace_regs(); - } - } + if (DEBUG_BREAK()) { + if (M.x86.saved_ip != breakpoint) { + return; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + M.x86.debug |= DEBUG_TRACE_F; + M.x86.debug &= ~DEBUG_BREAK_F; + print_decoded_instruction (); + X86EMU_trace_regs(); + } + } done=0; offset = M.x86.saved_ip; while (!done) { - printf("-"); - p = fgets(s, 1023, stdin); - cmd = parse_line(s, ps, &ntok); - switch(cmd) { - case 'u': - disassemble_forward(M.x86.saved_cs,(u16)offset,10); - break; - case 'd': - if (ntok == 2) { - segment = M.x86.saved_cs; - offset = ps[1]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else if (ntok == 3) { - segment = ps[1]; - offset = ps[2]; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } else { - segment = M.x86.saved_cs; - X86EMU_dump_memory(segment,(u16)offset,16); - offset += 16; - } - break; - case 'c': - M.x86.debug ^= DEBUG_TRACECALL_F; - break; - case 's': - M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; - break; - case 'r': - X86EMU_trace_regs(); - break; - case 'x': - X86EMU_trace_xregs(); - break; - case 'g': - if (ntok == 2) { - breakpoint = ps[1]; - if (noDecode) { - M.x86.debug |= DEBUG_DECODE_NOPRINT_F; - } else { - M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; - } - M.x86.debug &= ~DEBUG_TRACE_F; - M.x86.debug |= DEBUG_BREAK_F; - done = 1; - } - break; - case 'q': - M.x86.debug |= DEBUG_EXIT; - return; + printf("-"); + p = fgets(s, 1023, stdin); + cmd = parse_line(s, ps, &ntok); + switch(cmd) { + case 'u': + disassemble_forward(M.x86.saved_cs,(u16)offset,10); + break; + case 'd': + if (ntok == 2) { + segment = M.x86.saved_cs; + offset = ps[1]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else if (ntok == 3) { + segment = ps[1]; + offset = ps[2]; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } else { + segment = M.x86.saved_cs; + X86EMU_dump_memory(segment,(u16)offset,16); + offset += 16; + } + break; + case 'c': + M.x86.debug ^= DEBUG_TRACECALL_F; + break; + case 's': + M.x86.debug ^= DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F; + break; + case 'r': + X86EMU_trace_regs(); + break; + case 'x': + X86EMU_trace_xregs(); + break; + case 'g': + if (ntok == 2) { + breakpoint = ps[1]; + if (noDecode) { + M.x86.debug |= DEBUG_DECODE_NOPRINT_F; + } else { + M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F; + } + M.x86.debug &= ~DEBUG_TRACE_F; + M.x86.debug |= DEBUG_BREAK_F; + done = 1; + } + break; + case 'q': + M.x86.debug |= DEBUG_EXIT; + return; case 'P': - noDecode = (noDecode)?0:1; - printf("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); - break; - case 't': + noDecode = (noDecode)?0:1; + printf("Toggled decoding to %s\n",(noDecode)?"FALSE":"TRUE"); + break; + case 't': case 0: - done = 1; - break; - } + done = 1; + break; + } } #endif } @@ -340,23 +340,23 @@ int parse_line (char *s, int *ps, int *n) ps[*n] = *s; switch (*s) { case '\n': - *n += 1; - return 0; + *n += 1; + return 0; default: - cmd = *s; - *n += 1; + cmd = *s; + *n += 1; }
while (1) { - while (*s != ' ' && *s != '\t' && *s != '\n') s++; + while (*s != ' ' && *s != '\t' && *s != '\n') s++;
- if (*s == '\n') - return cmd; + if (*s == '\n') + return cmd;
- while(*s == ' ' || *s == '\t') s++; + while(*s == ' ' || *s == '\t') s++;
- sscanf(s,"%x",&ps[*n]); - *n += 1; + sscanf(s,"%x",&ps[*n]); + *n += 1; } #else return 0; @@ -380,22 +380,22 @@ void x86emu_dump_regs (void) printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("IP=%04x ", M.x86.R_IP ); - if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ - else printf("NV "); + if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ + else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); - else printf("UP "); + else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); - else printf("DI "); + else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); - else printf("PL "); + else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); - else printf("NZ "); + else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); - else printf("NA "); + else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); - else printf("PO "); + else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); - else printf("NC "); + else printf("NC "); printf("\n"); }
@@ -414,21 +414,21 @@ void x86emu_dump_xregs (void) printf("SS=%04x ", M.x86.R_SS ); printf("CS=%04x ", M.x86.R_CS ); printf("EIP=%08x\n\t", M.x86.R_EIP ); - if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ - else printf("NV "); + if (ACCESS_FLAG(F_OF)) printf("OV "); /* CHECKED... */ + else printf("NV "); if (ACCESS_FLAG(F_DF)) printf("DN "); - else printf("UP "); + else printf("UP "); if (ACCESS_FLAG(F_IF)) printf("EI "); - else printf("DI "); + else printf("DI "); if (ACCESS_FLAG(F_SF)) printf("NG "); - else printf("PL "); + else printf("PL "); if (ACCESS_FLAG(F_ZF)) printf("ZR "); - else printf("NZ "); + else printf("NZ "); if (ACCESS_FLAG(F_AF)) printf("AC "); - else printf("NA "); + else printf("NA "); if (ACCESS_FLAG(F_PF)) printf("PE "); - else printf("PO "); + else printf("PO "); if (ACCESS_FLAG(F_CF)) printf("CY "); - else printf("NC "); + else printf("NC "); printf("\n"); } diff --git a/src/device/oprom/x86emu/debug.h b/src/device/oprom/x86emu/debug.h index 6858f15..3d497d4 100644 --- a/src/device/oprom/x86emu/debug.h +++ b/src/device/oprom/x86emu/debug.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for debug definitions. * @@ -49,16 +49,16 @@
/* checks to be enabled for "runtime" */
-#define CHECK_IP_FETCH_F 0x1 -#define CHECK_SP_ACCESS_F 0x2 -#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ -#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/ +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset*/
#ifdef DEBUG -# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) -# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) -# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) -# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) #else # define CHECK_IP_FETCH() # define CHECK_SP_ACCESS() @@ -68,42 +68,42 @@
#ifdef DEBUG # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) -# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) -# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) -# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) # define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) -# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) -# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) -# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_IP_CS_F)
-# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) -# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) -# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) # define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) # define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) -# define DEBUG_TRACEJMP() (M.x86.debug & DEBUG_TRACEJMP_F) -# define DEBUG_TRACEJMPREGS() (M.x86.debug & DEBUG_TRACEJMP_REGS_F) -# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_TRACEJMP() (M.x86.debug & DEBUG_TRACEJMP_F) +# define DEBUG_TRACEJMPREGS() (M.x86.debug & DEBUG_TRACEJMP_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) # define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) # define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) #else # define DEBUG_INSTRUMENT() 0 -# define DEBUG_DECODE() 0 -# define DEBUG_TRACE() 0 -# define DEBUG_STEP() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 # define DEBUG_DISASSEMBLE() 0 -# define DEBUG_BREAK() 0 -# define DEBUG_SVC() 0 -# define DEBUG_SAVE_IP_CS() 0 -# define DEBUG_FS() 0 -# define DEBUG_PROC() 0 -# define DEBUG_SYSINT() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 # define DEBUG_TRACECALL() 0 # define DEBUG_TRACECALLREGS() 0 -# define DEBUG_TRACEJMP() 0 -# define DEBUG_TRACEJMPREGS() 0 -# define DEBUG_SYS() 0 +# define DEBUG_TRACEJMP() 0 +# define DEBUG_TRACEJMPREGS() 0 +# define DEBUG_SYS() 0 # define DEBUG_MEM_TRACE() 0 # define DEBUG_IO_TRACE() 0 # define DEBUG_DECODE_NOPRINT() 0 @@ -122,15 +122,15 @@ * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ -#define INC_DECODED_INST_LEN(x) \ - if (DEBUG_DECODE()) \ +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ x86emu_inc_decoded_inst_len(x)
-#define SAVE_IP_CS(x,y) \ +#define SAVE_IP_CS(x,y) \ if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ - | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ - M.x86.saved_cs = x; \ - M.x86.saved_ip = y; \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ } #else # define INC_DECODED_INST_LEN(x) @@ -140,11 +140,11 @@ #endif
#ifdef DEBUG -#define TRACE_REGS() \ - if (DEBUG_DISASSEMBLE()) { \ - x86emu_just_disassemble(); \ - goto EndOfTheInstructionProcedure; \ - } \ +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() #else # define TRACE_REGS() @@ -171,17 +171,17 @@ #endif
#ifdef DEBUG -# define CALL_TRACE(u,v,w,x,s) \ +# define CALL_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ printf("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); -# define RETURN_TRACE(u,v,w,x,s) \ +# define RETURN_TRACE(u,v,w,x,s) \ if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ printf("%04x:%04x: RET %s %04x:%04x\n",u,v,s,w,x); -# define JMP_TRACE(u,v,w,x,s) \ +# define JMP_TRACE(u,v,w,x,s) \ if (DEBUG_TRACEJMPREGS()) \ x86emu_dump_regs(); \ if (DEBUG_TRACEJMP()) \ @@ -207,7 +207,7 @@ /*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
void x86emu_inc_decoded_inst_len (int x); @@ -228,7 +228,7 @@ void x86emu_check_data_access (uint s, uint o); void disassemble_forward (u16 seg, u16 off, int n);
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_DEBUG_H */ diff --git a/src/device/oprom/x86emu/decode.c b/src/device/oprom/x86emu/decode.c index 3d3f77d..cc5e22c 100644 --- a/src/device/oprom/x86emu/decode.c +++ b/src/device/oprom/x86emu/decode.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines which are related to -* instruction decoding and accesses of immediate data via IP. etc. +* instruction decoding and accesses of immediate data via IP. etc. * ****************************************************************************/
@@ -50,19 +50,19 @@ static void x86emu_intr_handle(void) u8 intno;
if (M.x86.intr & INTR_SYNCH) { - intno = M.x86.intno; - if (_X86EMU_intrTab[intno]) { - (*_X86EMU_intrTab[intno])(intno); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intno * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intno * 4); - M.x86.intr = 0; - } + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } } }
@@ -97,34 +97,34 @@ void X86EMU_exec(void) DB(x86emu_end_instr();)
for (;;) { -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - /* If debugging, save the IP and CS values. */ - SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); - INC_DECODED_INST_LEN(1); - if (M.x86.intr) { - if (M.x86.intr & INTR_HALTED) { -DB( if (M.x86.R_SP != 0) { - printf("halted\n"); - X86EMU_trace_regs(); - } - else { - if (M.x86.debug) - printf("Service completed successfully\n"); - }) - return; - } - if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || - !ACCESS_FLAG(F_IF)) { - x86emu_intr_handle(); - } - } - op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - (*x86emu_optab[op1])(op1); - //if (M.x86.debug & DEBUG_EXIT) { - // M.x86.debug &= ~DEBUG_EXIT; - // return; - //} +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + printf("halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + printf("Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + //if (M.x86.debug & DEBUG_EXIT) { + // M.x86.debug &= ~DEBUG_EXIT; + // return; + //} } }
@@ -139,9 +139,9 @@ void X86EMU_halt_sys(void)
/**************************************************************************** PARAMETERS: -mod - Mod value from decoded byte -regh - Reg h value from decoded byte -regl - Reg l value from decoded byte +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte
REMARKS: Raise the specified interrupt to be handled before the execution of the @@ -157,7 +157,7 @@ void fetch_decode_modrm( int fetched;
DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); *mod = (fetched >> 6) & 0x03; @@ -180,7 +180,7 @@ u8 fetch_byte_imm(void) u8 fetched;
DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); return fetched; @@ -201,7 +201,7 @@ u16 fetch_word_imm(void) u16 fetched;
DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 2; INC_DECODED_INST_LEN(2); @@ -223,7 +223,7 @@ u32 fetch_long_imm(void) u32 fetched;
DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 4; INC_DECODED_INST_LEN(4); @@ -263,33 +263,33 @@ _INLINE u32 get_data_segment(void) { #define GET_SEGMENT(segment) switch (M.x86.mode & SYSMODE_SEGMASK) { - case 0: /* default case: use ds register */ + case 0: /* default case: use ds register */ case SYSMODE_SEGOVR_DS: case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: - return M.x86.R_DS; - case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ - return M.x86.R_SS; + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; case SYSMODE_SEGOVR_CS: case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: - return M.x86.R_CS; + return M.x86.R_CS; case SYSMODE_SEGOVR_ES: case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: - return M.x86.R_ES; + return M.x86.R_ES; case SYSMODE_SEGOVR_FS: case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: - return M.x86.R_FS; + return M.x86.R_FS; case SYSMODE_SEGOVR_GS: case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: - return M.x86.R_GS; + return M.x86.R_GS; case SYSMODE_SEGOVR_SS: case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: - return M.x86.R_SS; + return M.x86.R_SS; default: #ifdef DEBUG - printf("error: should not happen: multiple overrides.\n"); + printf("error: should not happen: multiple overrides.\n"); #endif - HALT_SYS(); - return 0; + HALT_SYS(); + return 0; } }
@@ -307,7 +307,7 @@ u8 fetch_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdb)((get_data_segment() << 4) + offset); } @@ -326,7 +326,7 @@ u16 fetch_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdw)((get_data_segment() << 4) + offset); } @@ -345,7 +345,7 @@ u32 fetch_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdl)((get_data_segment() << 4) + offset); } @@ -366,7 +366,7 @@ u8 fetch_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdb)(((u32)segment << 4) + offset); } @@ -387,7 +387,7 @@ u16 fetch_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdw)(((u32)segment << 4) + offset); } @@ -408,7 +408,7 @@ u32 fetch_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdl)(((u32)segment << 4) + offset); } @@ -416,7 +416,7 @@ u32 fetch_data_long_abs( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -430,7 +430,7 @@ void store_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrb)((get_data_segment() << 4) + offset, val); } @@ -438,7 +438,7 @@ void store_data_byte( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -452,7 +452,7 @@ void store_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrw)((get_data_segment() << 4) + offset, val); } @@ -460,7 +460,7 @@ void store_data_word( /**************************************************************************** PARAMETERS: offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a long value to an segmented memory location. The segment used is @@ -474,7 +474,7 @@ void store_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrl)((get_data_segment() << 4) + offset, val); } @@ -483,7 +483,7 @@ void store_data_long( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a byte value to an absolute memory location. @@ -497,7 +497,7 @@ void store_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrb)(((u32)segment << 4) + offset, val); } @@ -506,7 +506,7 @@ void store_data_byte_abs( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a word value to an absolute memory location. @@ -520,7 +520,7 @@ void store_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrw)(((u32)segment << 4) + offset, val); } @@ -529,7 +529,7 @@ void store_data_word_abs( PARAMETERS: segment - Segment to store data at offset - Offset to store data at -val - Value to store +val - Value to store
REMARKS: Writes a long value to an absolute memory location. @@ -543,7 +543,7 @@ void store_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrl)(((u32)segment << 4) + offset, val); } @@ -564,32 +564,32 @@ u8* decode_rm_byte_register( { switch (reg) { case 0: - DECODE_PRINTF("AL"); - return &M.x86.R_AL; + DECODE_PRINTF("AL"); + return &M.x86.R_AL; case 1: - DECODE_PRINTF("CL"); - return &M.x86.R_CL; + DECODE_PRINTF("CL"); + return &M.x86.R_CL; case 2: - DECODE_PRINTF("DL"); - return &M.x86.R_DL; + DECODE_PRINTF("DL"); + return &M.x86.R_DL; case 3: - DECODE_PRINTF("BL"); - return &M.x86.R_BL; + DECODE_PRINTF("BL"); + return &M.x86.R_BL; case 4: - DECODE_PRINTF("AH"); - return &M.x86.R_AH; + DECODE_PRINTF("AH"); + return &M.x86.R_AH; case 5: - DECODE_PRINTF("CH"); - return &M.x86.R_CH; + DECODE_PRINTF("CH"); + return &M.x86.R_CH; case 6: - DECODE_PRINTF("DH"); - return &M.x86.R_DH; + DECODE_PRINTF("DH"); + return &M.x86.R_DH; case 7: - DECODE_PRINTF("BH"); - return &M.x86.R_BH; + DECODE_PRINTF("BH"); + return &M.x86.R_BH; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ }
/**************************************************************************** @@ -608,32 +608,32 @@ u16* decode_rm_word_register( { switch (reg) { case 0: - DECODE_PRINTF("AX"); - return &M.x86.R_AX; + DECODE_PRINTF("AX"); + return &M.x86.R_AX; case 1: - DECODE_PRINTF("CX"); - return &M.x86.R_CX; + DECODE_PRINTF("CX"); + return &M.x86.R_CX; case 2: - DECODE_PRINTF("DX"); - return &M.x86.R_DX; + DECODE_PRINTF("DX"); + return &M.x86.R_DX; case 3: - DECODE_PRINTF("BX"); - return &M.x86.R_BX; + DECODE_PRINTF("BX"); + return &M.x86.R_BX; case 4: - DECODE_PRINTF("SP"); - return &M.x86.R_SP; + DECODE_PRINTF("SP"); + return &M.x86.R_SP; case 5: - DECODE_PRINTF("BP"); - return &M.x86.R_BP; + DECODE_PRINTF("BP"); + return &M.x86.R_BP; case 6: - DECODE_PRINTF("SI"); - return &M.x86.R_SI; + DECODE_PRINTF("SI"); + return &M.x86.R_SI; case 7: - DECODE_PRINTF("DI"); - return &M.x86.R_DI; + DECODE_PRINTF("DI"); + return &M.x86.R_DI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ }
/**************************************************************************** @@ -652,32 +652,32 @@ u32* decode_rm_long_register( { switch (reg) { case 0: - DECODE_PRINTF("EAX"); - return &M.x86.R_EAX; + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; case 1: - DECODE_PRINTF("ECX"); - return &M.x86.R_ECX; + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; case 2: - DECODE_PRINTF("EDX"); - return &M.x86.R_EDX; + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; case 3: - DECODE_PRINTF("EBX"); - return &M.x86.R_EBX; + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; case 4: - DECODE_PRINTF("ESP"); - return &M.x86.R_ESP; + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; case 5: - DECODE_PRINTF("EBP"); - return &M.x86.R_EBP; + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; case 6: - DECODE_PRINTF("ESI"); - return &M.x86.R_ESI; + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; case 7: - DECODE_PRINTF("EDI"); - return &M.x86.R_EDI; + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ }
/**************************************************************************** @@ -697,30 +697,30 @@ u16* decode_rm_seg_register( { switch (reg) { case 0: - DECODE_PRINTF("ES"); - return &M.x86.R_ES; + DECODE_PRINTF("ES"); + return &M.x86.R_ES; case 1: - DECODE_PRINTF("CS"); - return &M.x86.R_CS; + DECODE_PRINTF("CS"); + return &M.x86.R_CS; case 2: - DECODE_PRINTF("SS"); - return &M.x86.R_SS; + DECODE_PRINTF("SS"); + return &M.x86.R_SS; case 3: - DECODE_PRINTF("DS"); - return &M.x86.R_DS; + DECODE_PRINTF("DS"); + return &M.x86.R_DS; case 4: - DECODE_PRINTF("FS"); - return &M.x86.R_FS; + DECODE_PRINTF("FS"); + return &M.x86.R_FS; case 5: - DECODE_PRINTF("GS"); - return &M.x86.R_GS; + DECODE_PRINTF("GS"); + return &M.x86.R_GS; case 6: case 7: - DECODE_PRINTF("ILLEGAL SEGREG"); - break; + DECODE_PRINTF("ILLEGAL SEGREG"); + break; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ }
/**************************************************************************** @@ -741,38 +741,38 @@ static unsigned decode_sib_si( { scale = 1 << scale; if (scale > 1) { - DECODE_PRINTF2("[%d*", scale); + DECODE_PRINTF2("[%d*", scale); } else { - DECODE_PRINTF("["); + DECODE_PRINTF("["); } switch (index) { case 0: - DECODE_PRINTF("EAX]"); - return M.x86.R_EAX * index; + DECODE_PRINTF("EAX]"); + return M.x86.R_EAX * index; case 1: - DECODE_PRINTF("ECX]"); - return M.x86.R_ECX * index; + DECODE_PRINTF("ECX]"); + return M.x86.R_ECX * index; case 2: - DECODE_PRINTF("EDX]"); - return M.x86.R_EDX * index; + DECODE_PRINTF("EDX]"); + return M.x86.R_EDX * index; case 3: - DECODE_PRINTF("EBX]"); - return M.x86.R_EBX * index; + DECODE_PRINTF("EBX]"); + return M.x86.R_EBX * index; case 4: - DECODE_PRINTF("0]"); - return 0; + DECODE_PRINTF("0]"); + return 0; case 5: - DECODE_PRINTF("EBP]"); - return M.x86.R_EBP * index; + DECODE_PRINTF("EBP]"); + return M.x86.R_EBP * index; case 6: - DECODE_PRINTF("ESI]"); - return M.x86.R_ESI * index; + DECODE_PRINTF("ESI]"); + return M.x86.R_ESI * index; case 7: - DECODE_PRINTF("EDI]"); - return M.x86.R_EDI * index; + DECODE_PRINTF("EDI]"); + return M.x86.R_EDI * index; } HALT_SYS(); - return 0; /* NOT REACHED OR REACHED ON ERROR */ + return 0; /* NOT REACHED OR REACHED ON ERROR */ }
/**************************************************************************** @@ -797,58 +797,58 @@ static unsigned decode_sib_address(
switch (base) { case 0: - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 1: - DECODE_PRINTF("[ECX]"); - offset = M.x86.R_ECX; - break; + DECODE_PRINTF("[ECX]"); + offset = M.x86.R_ECX; + break; case 2: - DECODE_PRINTF("[EDX]"); - offset = M.x86.R_EDX; - break; + DECODE_PRINTF("[EDX]"); + offset = M.x86.R_EDX; + break; case 3: - DECODE_PRINTF("[EBX]"); - offset = M.x86.R_EBX; - break; + DECODE_PRINTF("[EBX]"); + offset = M.x86.R_EBX; + break; case 4: - DECODE_PRINTF("[ESP]"); - offset = M.x86.R_ESP; - break; + DECODE_PRINTF("[ESP]"); + offset = M.x86.R_ESP; + break; case 5: - switch (mod) { - case 0: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - offset = displacement; - break; - case 1: - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - case 2: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - default: - HALT_SYS(); - } - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + switch (mod) { + case 0: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + offset = displacement; + break; + case 1: + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + case 2: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + default: + HALT_SYS(); + } + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 6: - DECODE_PRINTF("[ESI]"); - offset = M.x86.R_ESI; - break; + DECODE_PRINTF("[ESI]"); + offset = M.x86.R_ESI; + break; case 7: - DECODE_PRINTF("[EDI]"); - offset = M.x86.R_EDI; - break; + DECODE_PRINTF("[EDI]"); + offset = M.x86.R_EDI; + break; default: - HALT_SYS(); + HALT_SYS(); } offset += decode_sib_si(ss, index); return offset; @@ -865,14 +865,14 @@ REMARKS: Return the offset given by mod=00 addressing. Also enables the decoding of instructions.
-NOTE: The code which specifies the corresponding segment (ds vs ss) - below in the case of [BP+..]. The assumption here is that at the - point that this subroutine is called, the bit corresponding to - SYSMODE_SEG_DS_SS will be zero. After every instruction - except the segment override instructions, this bit (as well - as any bits indicating segment overrides) will be clear. So - if a SS access is needed, set this bit. Otherwise, DS access - occurs (unless any of the segment override bits are set). +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). ****************************************************************************/ unsigned decode_rm00_address( int rm) @@ -880,64 +880,64 @@ unsigned decode_rm00_address( unsigned offset;
if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[EAX]"); - return M.x86.R_EAX; - case 1: - DECODE_PRINTF("[ECX]"); - return M.x86.R_ECX; - case 2: - DECODE_PRINTF("[EDX]"); - return M.x86.R_EDX; - case 3: - DECODE_PRINTF("[EBX]"); - return M.x86.R_EBX; - case 4: - return decode_sib_address(0); - case 5: - offset = fetch_long_imm(); - DECODE_PRINTF2("[%08x]", offset); - return offset; - case 6: - DECODE_PRINTF("[ESI]"); - return M.x86.R_ESI; - case 7: - DECODE_PRINTF("[EDI]"); - return M.x86.R_EDI; - } + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + return decode_sib_address(0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } } else { - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[BX+SI]"); - return (M.x86.R_BX + M.x86.R_SI) & 0xffff; - case 1: - DECODE_PRINTF("[BX+DI]"); - return (M.x86.R_BX + M.x86.R_DI) & 0xffff; - case 2: - DECODE_PRINTF("[BP+SI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI) & 0xffff; - case 3: - DECODE_PRINTF("[BP+DI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI) & 0xffff; - case 4: - DECODE_PRINTF("[SI]"); - return M.x86.R_SI; - case 5: - DECODE_PRINTF("[DI]"); - return M.x86.R_DI; - case 6: - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]", offset); - return offset; - case 7: - DECODE_PRINTF("[BX]"); - return M.x86.R_BX; - } + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } } HALT_SYS(); return 0; @@ -960,76 +960,76 @@ unsigned decode_rm01_address( int displacement;
if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - if (rm != 4) - displacement = (s8)fetch_byte_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(1); - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + /* 32-bit addressing */ + if (rm != 4) + displacement = (s8)fetch_byte_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(1); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - /* 16-bit addressing */ - displacement = (s8)fetch_byte_imm(); - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + /* 16-bit addressing */ + displacement = (s8)fetch_byte_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ }
/**************************************************************************** @@ -1047,79 +1047,79 @@ unsigned decode_rm10_address( int rm) { if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - int displacement; - - /* 32-bit addressing */ - if (rm != 4) - displacement = (s32)fetch_long_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(2); - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + int displacement; + + /* 32-bit addressing */ + if (rm != 4) + displacement = (s32)fetch_long_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(2); + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - int displacement = (s16)fetch_word_imm(); - - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + int displacement = (s16)fetch_word_imm(); + + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ }
diff --git a/src/device/oprom/x86emu/decode.h b/src/device/oprom/x86emu/decode.h index 99ed7f6..80ed1a4 100644 --- a/src/device/oprom/x86emu/decode.h +++ b/src/device/oprom/x86emu/decode.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for instruction decoding logic. * @@ -47,31 +47,31 @@ #define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r) #define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r) #define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r) -#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK +#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK
/*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
void x86emu_intr_raise (u8 type); -void fetch_decode_modrm (int *mod,int *regh,int *regl); -u8 fetch_byte_imm (void); -u16 fetch_word_imm (void); -u32 fetch_long_imm (void); -u8 fetch_data_byte (uint offset); -u8 fetch_data_byte_abs (uint segment, uint offset); -u16 fetch_data_word (uint offset); -u16 fetch_data_word_abs (uint segment, uint offset); -u32 fetch_data_long (uint offset); -u32 fetch_data_long_abs (uint segment, uint offset); -void store_data_byte (uint offset, u8 val); -void store_data_byte_abs (uint segment, uint offset, u8 val); -void store_data_word (uint offset, u16 val); -void store_data_word_abs (uint segment, uint offset, u16 val); -void store_data_long (uint offset, u32 val); -void store_data_long_abs (uint segment, uint offset, u32 val); +void fetch_decode_modrm (int *mod,int *regh,int *regl); +u8 fetch_byte_imm (void); +u16 fetch_word_imm (void); +u32 fetch_long_imm (void); +u8 fetch_data_byte (uint offset); +u8 fetch_data_byte_abs (uint segment, uint offset); +u16 fetch_data_word (uint offset); +u16 fetch_data_word_abs (uint segment, uint offset); +u32 fetch_data_long (uint offset); +u32 fetch_data_long_abs (uint segment, uint offset); +void store_data_byte (uint offset, u8 val); +void store_data_byte_abs (uint segment, uint offset, u8 val); +void store_data_word (uint offset, u16 val); +void store_data_word_abs (uint segment, uint offset, u16 val); +void store_data_long (uint offset, u32 val); +void store_data_long_abs (uint segment, uint offset, u32 val); u8* decode_rm_byte_register(int reg); u16* decode_rm_word_register(int reg); u32* decode_rm_long_register(int reg); @@ -82,7 +82,7 @@ unsigned decode_rm10_address(int rm); unsigned decode_rmXX_address(int mod, int rm);
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_DECODE_H */ diff --git a/src/device/oprom/x86emu/fpu.c b/src/device/oprom/x86emu/fpu.c index 7edebd4..2896023 100644 --- a/src/device/oprom/x86emu/fpu.c +++ b/src/device/oprom/x86emu/fpu.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file contains the code to implement the decoding and -* emulation of the FPU instructions. +* emulation of the FPU instructions. * ****************************************************************************/
@@ -108,192 +108,192 @@ void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); + DECODE_PRINTINSTR32(x86emu_fpu_op_d9_tab, mod, rh, rl); } else { - DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); + DECODE_PRINTF(x86emu_fpu_op_d9_tab1[(rh << 3) + rl]); } #endif switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - if (rh < 4) { - DECODE_PRINTF2("ST(%d)\n", stkelem); - } else { - DECODE_PRINTF("\n"); - } - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + if (rh < 4) { + DECODE_PRINTF2("ST(%d)\n", stkelem); + } else { + DECODE_PRINTF("\n"); + } + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); - break; - case 1: - x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); - break; - case 2: - switch (rl) { - case 0: - x86emu_fpu_R_nop(); - break; - default: - x86emu_fpu_illegal(); - break; - } - case 3: - x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); - break; - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); - break; - default: - /* 2,3,6,7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 5: - switch (rl) { - case 0: - x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); - break; - default: - /* 7 */ - x86emu_fpu_illegal(); - break; - } - break; - - case 6: - switch (rl) { - case 0: - x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_R_decstp(); - break; - case 7: - x86emu_fpu_R_incstp(); - break; - } - break; - - case 7: - switch (rl) { - case 0: - x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); - break; - case 6: - case 7: - default: - x86emu_fpu_illegal(); - break; - } - break; - - default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); - break; - case 4: - x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); - break; - } - } + switch (rh) { + case 0: + x86emu_fpu_R_fld(X86EMU_FPU_STKTOP, stkelem); + break; + case 1: + x86emu_fpu_R_fxch(X86EMU_FPU_STKTOP, stkelem); + break; + case 2: + switch (rl) { + case 0: + x86emu_fpu_R_nop(); + break; + default: + x86emu_fpu_illegal(); + break; + } + case 3: + x86emu_fpu_R_fstp(X86EMU_FPU_STKTOP, stkelem); + break; + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_fchs(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fabs(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_ftst(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fxam(X86EMU_FPU_STKTOP); + break; + default: + /* 2,3,6,7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 5: + switch (rl) { + case 0: + x86emu_fpu_R_fld1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fldl2t(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fldl2e(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fldpi(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fldlg2(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fldln2(X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fldz(X86EMU_FPU_STKTOP); + break; + default: + /* 7 */ + x86emu_fpu_illegal(); + break; + } + break; + + case 6: + switch (rl) { + case 0: + x86emu_fpu_R_f2xm1(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2x(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fptan(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fpatan(X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fxtract(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_R_decstp(); + break; + case 7: + x86emu_fpu_R_incstp(); + break; + } + break; + + case 7: + switch (rl) { + case 0: + x86emu_fpu_R_fprem(X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fyl2xp1(X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fsqrt(X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_frndint(X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fscale(X86EMU_FPU_STKTOP); + break; + case 6: + case 7: + default: + x86emu_fpu_illegal(); + break; + } + break; + + default: + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_FLOAT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_FLOAT, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_FLOAT, destoffset); + break; + case 4: + x86emu_fpu_M_fldenv(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fldcw(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fstenv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstcw(X86EMU_FPU_WORD, destoffset); + break; + } + } } #endif /* X86EMU_FPU_PRESENT */ DECODE_CLEAR_SEGOVR(); @@ -319,7 +319,7 @@ static const char *x86emu_fpu_op_da_tab[] = { "FIDIVR\tDWORD PTR ",
"ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", - "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", + "ESC_DA ", "ESC_DA ", "ESC_DA ", "ESC_DA ", };
#endif /* DEBUG */ @@ -336,54 +336,54 @@ void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_da_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - x86emu_fpu_illegal(); - break; + x86emu_fpu_illegal(); + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); - break; - case 2: - x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); - break; - case 5: - x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); - break; - case 6: - x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); - break; - case 7: - x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_iadd(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_M_imul(X86EMU_FPU_SHORT, destoffset); + break; + case 2: + x86emu_fpu_M_icom(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_icomp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_M_isub(X86EMU_FPU_SHORT, destoffset); + break; + case 5: + x86emu_fpu_M_isubr(X86EMU_FPU_SHORT, destoffset); + break; + case 6: + x86emu_fpu_M_idiv(X86EMU_FPU_SHORT, destoffset); + break; + case 7: + x86emu_fpu_M_idivr(X86EMU_FPU_SHORT, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -415,95 +415,95 @@ void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (mod != 3) { - DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); - } else if (rh == 4) { /* === 11 10 0 nnn */ - switch (rl) { - case 0: - DECODE_PRINTF("FENI\n"); - break; - case 1: - DECODE_PRINTF("FDISI\n"); - break; - case 2: - DECODE_PRINTF("FCLEX\n"); - break; - case 3: - DECODE_PRINTF("FINIT\n"); - break; - } + DECODE_PRINTINSTR32(x86emu_fpu_op_db_tab, mod, rh, rl); + } else if (rh == 4) { /* === 11 10 0 nnn */ + switch (rl) { + case 0: + DECODE_PRINTF("FENI\n"); + break; + case 1: + DECODE_PRINTF("FDISI\n"); + break; + case 2: + DECODE_PRINTF("FCLEX\n"); + break; + case 3: + DECODE_PRINTF("FINIT\n"); + break; + } } else { - DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); + DECODE_PRINTF2("ESC_DB %0x\n", (mod << 6) + (rh << 3) + (rl)); } #endif /* DEBUG */ switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - break; + destoffset = decode_rm00_address(rl); + break; case 1: - destoffset = decode_rm01_address(rl); - break; + destoffset = decode_rm01_address(rl); + break; case 2: - destoffset = decode_rm10_address(rl); - break; - case 3: /* register to register */ - break; + destoffset = decode_rm10_address(rl); + break; + case 3: /* register to register */ + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 4: - switch (rl) { - case 0: - x86emu_fpu_R_feni(); - break; - case 1: - x86emu_fpu_R_fdisi(); - break; - case 2: - x86emu_fpu_R_fclex(); - break; - case 3: - x86emu_fpu_R_finit(); - break; - default: - x86emu_fpu_illegal(); - break; - } - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 4: + switch (rl) { + case 0: + x86emu_fpu_R_feni(); + break; + case 1: + x86emu_fpu_R_fdisi(); + break; + case 2: + x86emu_fpu_R_fclex(); + break; + case 3: + x86emu_fpu_R_finit(); + break; + default: + x86emu_fpu_illegal(); + break; + } + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); - break; - case 4: - x86emu_fpu_illegal(); - break; - case 5: - x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); - break; - case 6: - x86emu_fpu_illegal(); - break; - case 7: - x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_SHORT, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_SHORT, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_SHORT, destoffset); + break; + case 4: + x86emu_fpu_illegal(); + break; + case 5: + x86emu_fpu_M_fld(X86EMU_FPU_LDBL, destoffset); + break; + case 6: + x86emu_fpu_illegal(); + break; + case 7: + x86emu_fpu_M_fstp(X86EMU_FPU_LDBL, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -544,80 +544,80 @@ void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_dc_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT /* execute */ switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 4: - x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_fadd(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmul(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcom(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 4: + x86emu_fpu_R_fsubr(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsub(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivr(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdiv(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); - break; - case 2: - x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); - break; - case 5: - x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); - break; - case 6: - x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); - break; - case 7: - x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fadd(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_M_fmul(X86EMU_FPU_DOUBLE, destoffset); + break; + case 2: + x86emu_fpu_M_fcom(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fcomp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_fsub(X86EMU_FPU_DOUBLE, destoffset); + break; + case 5: + x86emu_fpu_M_fsubr(X86EMU_FPU_DOUBLE, destoffset); + break; + case 6: + x86emu_fpu_M_fdiv(X86EMU_FPU_DOUBLE, destoffset); + break; + case 7: + x86emu_fpu_M_fdivr(X86EMU_FPU_DOUBLE, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -654,70 +654,70 @@ void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_dd_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); - break; - case 3: - x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); - break; - case 4: - x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_illegal(); - break; - case 6: - x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fld(X86EMU_FPU_DOUBLE, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fst(X86EMU_FPU_DOUBLE, destoffset); + break; + case 3: + x86emu_fpu_M_fstp(X86EMU_FPU_DOUBLE, destoffset); + break; + case 4: + x86emu_fpu_M_frstor(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_illegal(); + break; + case 6: + x86emu_fpu_M_fsave(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fstsw(X86EMU_FPU_WORD, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -761,82 +761,82 @@ void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_de_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d),ST\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d),ST\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); - break; - case 1: - x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); - break; - case 2: - x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); - break; - case 3: - if (stkelem == 1) - x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); - else - x86emu_fpu_illegal(); - break; - case 4: - x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 5: - x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); - break; - case 6: - x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); - break; - case 7: - x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_faddp(stkelem, X86EMU_FPU_STKTOP); + break; + case 1: + x86emu_fpu_R_fmulp(stkelem, X86EMU_FPU_STKTOP); + break; + case 2: + x86emu_fpu_R_fcomp(stkelem, X86EMU_FPU_STKTOP); + break; + case 3: + if (stkelem == 1) + x86emu_fpu_R_fcompp(stkelem, X86EMU_FPU_STKTOP); + else + x86emu_fpu_illegal(); + break; + case 4: + x86emu_fpu_R_fsubrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 5: + x86emu_fpu_R_fsubp(stkelem, X86EMU_FPU_STKTOP); + break; + case 6: + x86emu_fpu_R_fdivrp(stkelem, X86EMU_FPU_STKTOP); + break; + case 7: + x86emu_fpu_R_fdivp(stkelem, X86EMU_FPU_STKTOP); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); - break; - case 2: - x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); - break; - case 5: - x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); - break; - case 6: - x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); - break; - case 7: - x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fiadd(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_M_fimul(X86EMU_FPU_WORD, destoffset); + break; + case 2: + x86emu_fpu_M_ficom(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_ficomp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fisub(X86EMU_FPU_WORD, destoffset); + break; + case 5: + x86emu_fpu_M_fisubr(X86EMU_FPU_WORD, destoffset); + break; + case 6: + x86emu_fpu_M_fidiv(X86EMU_FPU_WORD, destoffset); + break; + case 7: + x86emu_fpu_M_fidivr(X86EMU_FPU_WORD, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); @@ -880,70 +880,70 @@ void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1)) DECODE_PRINTINSTR32(x86emu_fpu_op_df_tab, mod, rh, rl); switch (mod) { case 0: - destoffset = decode_rm00_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm00_address(rl); + DECODE_PRINTF("\n"); + break; case 1: - destoffset = decode_rm01_address(rl); - DECODE_PRINTF("\n"); - break; + destoffset = decode_rm01_address(rl); + DECODE_PRINTF("\n"); + break; case 2: - destoffset = decode_rm10_address(rl); - DECODE_PRINTF("\n"); - break; - case 3: /* register to register */ - stkelem = (u8)rl; - DECODE_PRINTF2("\tST(%d)\n", stkelem); - break; + destoffset = decode_rm10_address(rl); + DECODE_PRINTF("\n"); + break; + case 3: /* register to register */ + stkelem = (u8)rl; + DECODE_PRINTF2("\tST(%d)\n", stkelem); + break; } #ifdef X86EMU_FPU_PRESENT switch (mod) { case 3: - switch (rh) { - case 0: - x86emu_fpu_R_ffree(stkelem); - break; - case 1: - x86emu_fpu_R_fxch(stkelem); - break; - case 2: - x86emu_fpu_R_fst(stkelem); /* register version */ - break; - case 3: - x86emu_fpu_R_fstp(stkelem); /* register version */ - break; - default: - x86emu_fpu_illegal(); - break; - } - break; + switch (rh) { + case 0: + x86emu_fpu_R_ffree(stkelem); + break; + case 1: + x86emu_fpu_R_fxch(stkelem); + break; + case 2: + x86emu_fpu_R_fst(stkelem); /* register version */ + break; + case 3: + x86emu_fpu_R_fstp(stkelem); /* register version */ + break; + default: + x86emu_fpu_illegal(); + break; + } + break; default: - switch (rh) { - case 0: - x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); - break; - case 1: - x86emu_fpu_illegal(); - break; - case 2: - x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); - break; - case 3: - x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); - break; - case 4: - x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); - break; - case 5: - x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); - break; - case 6: - x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); - break; - case 7: - x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); - break; - } + switch (rh) { + case 0: + x86emu_fpu_M_fild(X86EMU_FPU_WORD, destoffset); + break; + case 1: + x86emu_fpu_illegal(); + break; + case 2: + x86emu_fpu_M_fist(X86EMU_FPU_WORD, destoffset); + break; + case 3: + x86emu_fpu_M_fistp(X86EMU_FPU_WORD, destoffset); + break; + case 4: + x86emu_fpu_M_fbld(X86EMU_FPU_BSD, destoffset); + break; + case 5: + x86emu_fpu_M_fild(X86EMU_FPU_LONG, destoffset); + break; + case 6: + x86emu_fpu_M_fbstp(X86EMU_FPU_BSD, destoffset); + break; + case 7: + x86emu_fpu_M_fistp(X86EMU_FPU_LONG, destoffset); + break; + } } #endif DECODE_CLEAR_SEGOVR(); diff --git a/src/device/oprom/x86emu/fpu.h b/src/device/oprom/x86emu/fpu.h index 5fb2714..1a866c7 100644 --- a/src/device/oprom/x86emu/fpu.h +++ b/src/device/oprom/x86emu/fpu.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for FPU instruction decoding. * @@ -40,7 +40,7 @@ #define __X86EMU_FPU_H
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
/* these have to be defined, whether 8087 support compiled in or not. */ @@ -55,7 +55,7 @@ extern void x86emuOp_esc_coprocess_de (u8 op1); extern void x86emuOp_esc_coprocess_df (u8 op1);
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_FPU_H */ diff --git a/src/device/oprom/x86emu/ops.c b/src/device/oprom/x86emu/ops.c index c805b58..e334672 100644 --- a/src/device/oprom/x86emu/ops.c +++ b/src/device/oprom/x86emu/ops.c @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,10 +30,10 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 processor instructions. +* and emulation of all the x86 processor instructions. * * There are approximately 250 subroutines in here, which correspond * to the 256 byte-"opcodes" found on the 8086. The table which @@ -84,38 +84,38 @@ static const char *x86emu_GenOpName[8] = { /* used by several opcodes */ static u8 (*genop_byte_operation[])(u8 d, u8 s) = { - add_byte, /* 00 */ - or_byte, /* 01 */ - adc_byte, /* 02 */ - sbb_byte, /* 03 */ - and_byte, /* 04 */ - sub_byte, /* 05 */ - xor_byte, /* 06 */ - cmp_byte, /* 07 */ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ };
static u16 (*genop_word_operation[])(u16 d, u16 s) = { - add_word, /*00 */ - or_word, /*01 */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ - sub_word, /*05 */ - xor_word, /*06 */ - cmp_word, /*07 */ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ };
static u32 (*genop_long_operation[])(u32 d, u32 s) = { - add_long, /*00 */ - or_long, /*01 */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ - sub_long, /*05 */ - xor_long, /*06 */ - cmp_long, /*07 */ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ };
/* used by opcodes 80, c0, d0, and d2. */ @@ -127,7 +127,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) = rcr_byte, shl_byte, shr_byte, - shl_byte, /* sal_byte === shl_byte by definition */ + shl_byte, /* sal_byte === shl_byte by definition */ sar_byte, };
@@ -140,7 +140,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) = rcr_word, shl_word, shr_word, - shl_word, /* sal_byte === shl_byte by definition */ + shl_word, /* sal_byte === shl_byte by definition */ sar_word, };
@@ -153,7 +153,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) = rcr_long, shl_long, shr_long, - shl_long, /* sal_byte === shl_byte by definition */ + shl_long, /* sal_byte === shl_byte by definition */ sar_long, };
@@ -176,21 +176,21 @@ static void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); - TRACE_REGS(); - DB( printf("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-1,op1)); - HALT_SYS(); - } + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( printf("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1)); + HALT_SYS(); + } else { - /* If we get here, it means the stack pointer is back to zero - * so we are just returning from an emulator service call - * so therte is no need to display an error message. We trap - * the emulator with an 0xF1 opcode to finish the service - * call. - */ - X86EMU_halt_sys(); - } + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } END_OF_INSTR(); }
@@ -212,25 +212,25 @@ static void x86emuOp_genop_byte_RM_R(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) - { destoffset = decode_rmXX_address(mod,rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_byte_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_byte(destoffset, destval); - } + { destoffset = decode_rmXX_address(mod,rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_byte_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_byte(destoffset, destval); + } else - { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_byte_operation[op1](*destreg, *srcreg); - } + { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, *srcreg); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -252,52 +252,52 @@ static void x86emuOp_genop_word_RM_R(u8 op1) FETCH_DECODE_MODRM(mod, rh, rl);
if(mod<3) { - destoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_long_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_word_operation[op1](destval, *srcreg); - if (op1 != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_long_operation[op1](*destreg, *srcreg); - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_long_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_word_operation[op1](destval, *srcreg); + if (op1 != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_long_operation[op1](*destreg, *srcreg); + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -321,15 +321,15 @@ static void x86emuOp_genop_byte_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod,rl); - srcval = fetch_data_byte(srcoffset); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - srcval = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod,rl); + srcval = fetch_data_byte(srcoffset); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + srcval = *srcreg; } DECODE_PRINTF("\n"); TRACE_AND_STEP(); @@ -357,40 +357,40 @@ static void x86emuOp_genop_word_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, srcval); - } else { - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, srcval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); - } else { - u16 *srcreg; - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + srcoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, srcval); + } else { + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, srcval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); + } else { + u16 *srcreg; + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -429,20 +429,20 @@ static void x86emuOp_genop_word_AX_IMM(u8 op1)
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); + M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); } else { - M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); + M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -682,17 +682,17 @@ static void x86emuOp_inc_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("INC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -708,17 +708,17 @@ static void x86emuOp_dec_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("DEC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -734,17 +734,17 @@ static void x86emuOp_push_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("PUSH\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -760,17 +760,17 @@ static void x86emuOp_pop_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("POP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_long(); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_long(); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_word(); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -784,33 +784,33 @@ static void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHAD\n"); + DECODE_PRINTF("PUSHAD\n"); } else { - DECODE_PRINTF("PUSHA\n"); + DECODE_PRINTF("PUSHA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 old_sp = M.x86.R_ESP; - - push_long(M.x86.R_EAX); - push_long(M.x86.R_ECX); - push_long(M.x86.R_EDX); - push_long(M.x86.R_EBX); - push_long(old_sp); - push_long(M.x86.R_EBP); - push_long(M.x86.R_ESI); - push_long(M.x86.R_EDI); + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); } else { - u16 old_sp = M.x86.R_SP; - - push_word(M.x86.R_AX); - push_word(M.x86.R_CX); - push_word(M.x86.R_DX); - push_word(M.x86.R_BX); - push_word(old_sp); - push_word(M.x86.R_BP); - push_word(M.x86.R_SI); - push_word(M.x86.R_DI); + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -824,36 +824,36 @@ static void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPAD\n"); + DECODE_PRINTF("POPAD\n"); } else { - DECODE_PRINTF("POPA\n"); + DECODE_PRINTF("POPA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - M.x86.R_ESI = pop_long(); - M.x86.R_EBP = pop_long(); - M.x86.R_ESP += 4; /* skip ESP */ - M.x86.R_EBX = pop_long(); - M.x86.R_EDX = pop_long(); - M.x86.R_ECX = pop_long(); - M.x86.R_EAX = pop_long(); + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); } else { - M.x86.R_DI = pop_word(); - M.x86.R_SI = pop_word(); - M.x86.R_BP = pop_word(); - M.x86.R_SP += 2; /* skip SP */ - M.x86.R_BX = pop_word(); - M.x86.R_DX = pop_word(); - M.x86.R_CX = pop_word(); - M.x86.R_AX = pop_word(); + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); }
-/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ -/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */
/**************************************************************************** REMARKS: @@ -927,16 +927,16 @@ static void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - imm = fetch_long_imm(); + imm = fetch_long_imm(); } else { - imm = fetch_word_imm(); + imm = fetch_word_imm(); } DECODE_PRINTF2("PUSH\t%x\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word((u16)imm); + push_word((u16)imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -955,95 +955,95 @@ static void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1062,9 +1062,9 @@ static void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("PUSH\t%d\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word(imm); + push_word(imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1084,92 +1084,92 @@ static void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1197,11 +1197,11 @@ static void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INSD\n"); - ins(4); + DECODE_PRINTF("INSD\n"); + ins(4); } else { - DECODE_PRINTF("INSW\n"); - ins(2); + DECODE_PRINTF("INSW\n"); + ins(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1230,11 +1230,11 @@ static void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUTSD\n"); - outs(4); + DECODE_PRINTF("OUTSD\n"); + outs(4); } else { - DECODE_PRINTF("OUTSW\n"); - outs(2); + DECODE_PRINTF("OUTSW\n"); + outs(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1259,7 +1259,7 @@ static void x86emuOp_jump_near_cond(u8 op1) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (cond) { - M.x86.R_IP = target; + M.x86.R_IP = target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R_IP, " NEAR COND "); } DECODE_CLEAR_SEGOVR(); @@ -1287,59 +1287,59 @@ static void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_byte_operation[rh]) (*destreg, imm); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_byte_operation[rh]) (*destreg, imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1363,37 +1363,37 @@ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* @@ -1401,51 +1401,51 @@ static void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) * mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_long_operation[rh]) (*destreg, imm); - } else { - u16 *destreg, imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_word_operation[rh]) (*destreg, imm); - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_long_operation[rh]) (*destreg, imm); + } else { + u16 *destreg, imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_word_operation[rh]) (*destreg, imm); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1473,56 +1473,56 @@ static void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_byte_operation[rh]) (*destreg, imm); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_byte_operation[rh]) (*destreg, imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1547,83 +1547,83 @@ static void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod,rl); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_long_operation[rh]) (*destreg, imm); - } else { - u16 *destreg, imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = (*genop_word_operation[rh]) (*destreg, imm); - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod,rl); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_long_operation[rh]) (*destreg, imm); + } else { + u16 *destreg, imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = (*genop_word_operation[rh]) (*destreg, imm); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1644,20 +1644,20 @@ static void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(*destreg, *srcreg); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1676,48 +1676,48 @@ static void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1739,25 +1739,25 @@ static void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1776,59 +1776,59 @@ static void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 tmp; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } else { - u16 *destreg,*srcreg; - u16 tmp; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1848,19 +1848,19 @@ static void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1879,44 +1879,44 @@ static void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1937,20 +1937,20 @@ static void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1969,49 +1969,49 @@ static void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2032,20 +2032,20 @@ static void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2064,21 +2064,21 @@ static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u32)destoffset; + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; } else { - u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - } + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } } /* else { undefined. Do nothing. } */ DECODE_CLEAR_SEGOVR(); @@ -2100,20 +2100,20 @@ static void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } /* * Clean up, and reset all the R_xSP pointers to the correct @@ -2138,42 +2138,42 @@ static void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_long(); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_word(); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2205,23 +2205,23 @@ static void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - DECODE_PRINTF("XCHG\tEAX,"); - reg32 = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_EAX; - M.x86.R_EAX = *reg32; - *reg32 = tmp; + u32 *reg32; + DECODE_PRINTF("XCHG\tEAX,"); + reg32 = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_EAX; + M.x86.R_EAX = *reg32; + *reg32 = tmp; } else { - u16 *reg16; - DECODE_PRINTF("XCHG\tAX,"); - reg16 = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_AX; - M.x86.R_AX = *reg16; - *reg16 = (u16)tmp; + u16 *reg16; + DECODE_PRINTF("XCHG\tAX,"); + reg16 = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_AX; + M.x86.R_AX = *reg16; + *reg16 = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2235,23 +2235,23 @@ static void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CWDE\n"); + DECODE_PRINTF("CWDE\n"); } else { - DECODE_PRINTF("CBW\n"); + DECODE_PRINTF("CBW\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_AX & 0x8000) { - M.x86.R_EAX |= 0xffff0000; - } else { - M.x86.R_EAX &= 0x0000ffff; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } } else { - if (M.x86.R_AL & 0x80) { - M.x86.R_AH = 0xff; - } else { - M.x86.R_AH = 0x0; - } + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2265,24 +2265,24 @@ static void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CDQ\n"); + DECODE_PRINTF("CDQ\n"); } else { - DECODE_PRINTF("CWD\n"); + DECODE_PRINTF("CWD\n"); } DECODE_PRINTF("CWD\n"); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_EAX & 0x80000000) { - M.x86.R_EDX = 0xffffffff; - } else { - M.x86.R_EDX = 0x0; - } + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } } else { - if (M.x86.R_AX & 0x8000) { - M.x86.R_DX = 0xffff; - } else { - M.x86.R_DX = 0x0; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2299,11 +2299,11 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - faroff = fetch_long_imm(); - farseg = fetch_word_imm(); + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); } else { - faroff = fetch_word_imm(); - farseg = fetch_word_imm(); + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); } DECODE_PRINTF2("%04x:", farseg); DECODE_PRINTF2("%04x\n", faroff); @@ -2319,9 +2319,9 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_CS); M.x86.R_CS = farseg; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EIP); + push_long(M.x86.R_EIP); } else { - push_word(M.x86.R_IP); + push_word(M.x86.R_IP); } M.x86.R_EIP = faroff & 0xffff; DECODE_CLEAR_SEGOVR(); @@ -2352,18 +2352,18 @@ static void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHFD\n"); + DECODE_PRINTF("PUSHFD\n"); } else { - DECODE_PRINTF("PUSHF\n"); + DECODE_PRINTF("PUSHF\n"); } TRACE_AND_STEP();
/* clear out *all* bits not representing flags, and turn on real bits */ flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(flags); + push_long(flags); } else { - push_word((u16)flags); + push_word((u16)flags); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2377,15 +2377,15 @@ static void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPFD\n"); + DECODE_PRINTF("POPFD\n"); } else { - DECODE_PRINTF("POPF\n"); + DECODE_PRINTF("POPF\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EFLG = pop_long(); + M.x86.R_EFLG = pop_long(); } else { - M.x86.R_FLG = pop_word(); + M.x86.R_FLG = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2454,15 +2454,15 @@ static void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); } else { - DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(offset); + M.x86.R_EAX = fetch_data_long(offset); } else { - M.x86.R_AX = fetch_data_word(offset); + M.x86.R_AX = fetch_data_word(offset); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2497,15 +2497,15 @@ static void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); } else { - DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long(offset, M.x86.R_EAX); + store_data_long(offset, M.x86.R_EAX); } else { - store_data_word(offset, M.x86.R_AX); + store_data_word(offset, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2524,27 +2524,27 @@ static void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOVS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - val = fetch_data_byte(M.x86.R_SI); - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2562,41 +2562,41 @@ static void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOVS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("MOVS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long(M.x86.R_SI); - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); - } else { - val = fetch_data_word(M.x86.R_SI); - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2615,35 +2615,35 @@ static void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("CMPS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2660,53 +2660,53 @@ static void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMPS\tDWORD\n"); - inc = 4; + DECODE_PRINTF("CMPS\tDWORD\n"); + inc = 4; } else { - DECODE_PRINTF("CMPS\tWORD\n"); - inc = 2; + DECODE_PRINTF("CMPS\tWORD\n"); + inc = 2; } if (ACCESS_FLAG(F_DF)) /* down */ - inc = -inc; + inc = -inc;
TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2740,18 +2740,18 @@ static void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("TEST\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF("TEST\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - test_long(M.x86.R_EAX, srcval); + test_long(M.x86.R_EAX, srcval); } else { - test_word(M.x86.R_AX, (u16)srcval); + test_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2768,27 +2768,27 @@ static void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("STOS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_DI += inc; + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2805,38 +2805,38 @@ static void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("STOS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("STOS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); - } else { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); - } - M.x86.R_DI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2854,26 +2854,26 @@ static void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LODS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_SI += inc; + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2890,38 +2890,38 @@ static void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("LODS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("LODS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* move them until (E)CX is ZERO. */ - count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; - M.x86.R_CX = 0; + /* don't care whether REPE or REPNE */ + /* move them until (E)CX is ZERO. */ + count = (M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX; + M.x86.R_CX = 0; if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + M.x86.R_ECX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(M.x86.R_SI); - } else { - M.x86.R_AX = fetch_data_word(M.x86.R_SI); - } - M.x86.R_SI += inc; - if (M.x86.intr & INTR_HALTED) - break; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; + if (M.x86.intr & INTR_HALTED) + break; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2940,47 +2940,47 @@ static void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("SCAS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_DI += inc; + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2997,72 +2997,72 @@ static void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SCAS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("SCAS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until (E)CX is ZERO. */ - while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - if (M.x86.mode & SYSMODE_32BIT_REP) - M.x86.R_ECX -= 1; - else - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - if (M.x86.intr & INTR_HALTED) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until (E)CX is ZERO. */ + while (((M.x86.mode & SYSMODE_32BIT_REP) ? M.x86.R_ECX : M.x86.R_CX) != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + if (M.x86.mode & SYSMODE_32BIT_REP) + M.x86.R_ECX -= 1; + else + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + if (M.x86.intr & INTR_HALTED) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3101,19 +3101,19 @@ static void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOV\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - reg32 = DECODE_RM_LONG_REGISTER(op1); - srcval = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg32 = srcval; + u32 *reg32; + reg32 = DECODE_RM_LONG_REGISTER(op1); + srcval = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg32 = srcval; } else { - u16 *reg16; - reg16 = DECODE_RM_WORD_REGISTER(op1); - srcval = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg16 = (u16)srcval; + u16 *reg16; + reg16 = DECODE_RM_WORD_REGISTER(op1); + srcval = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg16 = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3140,57 +3140,57 @@ static void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3215,83 +3215,83 @@ static void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3346,15 +3346,15 @@ static void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LES\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); } - /* else UNDEFINED! register to register */ + /* else UNDEFINED! register to register */
DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3374,13 +3374,13 @@ static void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LDS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); } /* else UNDEFINED! */ DECODE_CLEAR_SEGOVR(); @@ -3402,22 +3402,22 @@ static void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); } if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3436,49 +3436,49 @@ static void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 imm;
- destreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { u16 *destreg; u16 imm;
- destreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3503,12 +3503,12 @@ static void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_BP); frame_pointer = M.x86.R_SP; if (nesting > 0) { - for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); - } - push_word(frame_pointer); - } + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); @@ -3583,13 +3583,13 @@ static void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[3]) { (*_X86EMU_intrTab[3])(3); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(3 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(3 * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3613,13 +3613,13 @@ static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[intnum]) { (*_X86EMU_intrTab[intnum])(intnum); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intnum * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intnum * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3637,18 +3637,18 @@ static void x86emuOp_into(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("INTO\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) { - tmp = mem_access_word(4 * 4 + 2); + tmp = mem_access_word(4 * 4 + 2); if (_X86EMU_intrTab[4]) { (*_X86EMU_intrTab[4])(4); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(4 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(4 * 4); - } + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3692,54 +3692,54 @@ static void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, 1); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3763,82 +3763,82 @@ static void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *destreg;
- destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (*destreg, 1); - *destreg = destval; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { u16 destval; u16 *destreg;
- destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (*destreg, 1); - *destreg = destval; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3865,55 +3865,55 @@ static void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3938,79 +3938,79 @@ static void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4028,9 +4028,9 @@ static void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); - TRACE_REGS(); - HALT_SYS(); + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); } TRACE_AND_STEP(); /* note the type change here --- returning AL and AH in AX. */ @@ -4092,11 +4092,11 @@ static void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && !ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and !ZF */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && !ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and !ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4116,11 +4116,11 @@ static void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and ZF */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0 && ACCESS_FLAG(F_ZF)) /* (E)CX != 0 and ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4140,11 +4140,11 @@ static void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.R_ECX -= 1; + M.x86.R_ECX -= 1; else - M.x86.R_CX -= 1; - if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0) /* (E)CX != 0 */ - M.x86.R_IP = ip; + M.x86.R_CX -= 1; + if (((M.x86.mode & SYSMODE_PREFIX_ADDR) ? M.x86.R_ECX : M.x86.R_CX) != 0) /* (E)CX != 0 */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4166,7 +4166,7 @@ static void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (M.x86.R_CX == 0) { - M.x86.R_IP = target; + M.x86.R_IP = target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R_IP, " CXZ "); } DECODE_CLEAR_SEGOVR(); @@ -4203,15 +4203,15 @@ static void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("EAX,%x\n", port); + DECODE_PRINTF2("EAX,%x\n", port); } else { - DECODE_PRINTF2("AX,%x\n", port); + DECODE_PRINTF2("AX,%x\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(port); + M.x86.R_EAX = (*sys_inl)(port); } else { - M.x86.R_AX = (*sys_inw)(port); + M.x86.R_AX = (*sys_inw)(port); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4247,15 +4247,15 @@ static void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("%x,EAX\n", port); + DECODE_PRINTF2("%x,EAX\n", port); } else { - DECODE_PRINTF2("%x,AX\n", port); + DECODE_PRINTF2("%x,AX\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(port, M.x86.R_EAX); + (*sys_outl)(port, M.x86.R_EAX); } else { - (*sys_outw)(port, M.x86.R_AX); + (*sys_outw)(port, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4273,23 +4273,23 @@ static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip32 = (s32) fetch_long_imm(); - ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", (u16)ip32); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); } else { - ip16 = (s16) fetch_word_imm(); - ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip16); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(M.x86.R_EIP); - M.x86.R_EIP = ip32 & 0xffff; + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; } else { - push_word(M.x86.R_IP); - M.x86.R_EIP = ip16; + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4306,19 +4306,19 @@ static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("JMP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip = (u32)fetch_long_imm(); + ip = (u32)fetch_long_imm(); ip += (u32)M.x86.R_EIP; DECODE_PRINTF2("%08x\n", (u32)ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); TRACE_AND_STEP(); M.x86.R_EIP = (u32)ip; } else { - ip = (s16)fetch_word_imm(); - ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", (u16)ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); - TRACE_AND_STEP(); - M.x86.R_IP = (u16)ip; + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4336,9 +4336,9 @@ static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("JMP\tFAR "); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - ip = fetch_long_imm(); + ip = fetch_long_imm(); } else { - ip = fetch_word_imm(); + ip = fetch_word_imm(); } cs = fetch_word_imm(); DECODE_PRINTF2("%04x:", cs); @@ -4394,15 +4394,15 @@ static void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("IN\tEAX,DX\n"); + DECODE_PRINTF("IN\tEAX,DX\n"); } else { - DECODE_PRINTF("IN\tAX,DX\n"); + DECODE_PRINTF("IN\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); } else { - M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4430,15 +4430,15 @@ static void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUT\tDX,EAX\n"); + DECODE_PRINTF("OUT\tDX,EAX\n"); } else { - DECODE_PRINTF("OUT\tDX,AX\n"); + DECODE_PRINTF("OUT\tDX,AX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); } else { - (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4470,7 +4470,7 @@ static void x86emuOp_repne(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPNE; if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.mode |= SYSMODE_32BIT_REP; + M.x86.mode |= SYSMODE_32BIT_REP; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4486,7 +4486,7 @@ static void x86emuOp_repe(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.mode |= SYSMODE_PREFIX_REPE; if (M.x86.mode & SYSMODE_PREFIX_ADDR) - M.x86.mode |= SYSMODE_32BIT_REP; + M.x86.mode |= SYSMODE_32BIT_REP; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4537,100 +4537,100 @@ static void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(destval); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - } else { /* mod=11 */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_byte(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_byte(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(*destreg); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(*destreg); - break; - } + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(destval); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + } else { /* mod=11 */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4650,213 +4650,213 @@ static void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF(opF6_names[rh]); if (mod < 3) {
- if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval, srcval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_long(destoffset); - - switch (rh) { - case 0: - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(destval); - break; - } - } else { - u16 destval, srcval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_word(destoffset); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(destval); - break; - } - } - - } else { /* mod=11 */ - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_long(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_long(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(*destreg); - break; - } - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_word(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_word(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(*destreg); - break; - } - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval, srcval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_long(destoffset); + + switch (rh) { + case 0: + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(destval); + break; + } + } else { + u16 destval, srcval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_word(destoffset); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(destval); + break; + } + } + + } else { /* mod=11 */ + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + break; + } + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4968,49 +4968,49 @@ static void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("INC\t"); - break; - case 1: - DECODE_PRINTF("DEC\t"); - break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - if (rh == 0) - destval = inc_byte(destval); - else - destval = dec_byte(destval); - store_data_byte(destoffset, destval); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + if (rh == 0) + destval = inc_byte(destval); + else + destval = dec_byte(destval); + store_data_byte(destoffset, destval); } else { - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - if (rh == 0) - *destreg = inc_byte(*destreg); - else - *destreg = dec_byte(*destreg); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + if (rh == 0) + *destreg = inc_byte(*destreg); + else + *destreg = dec_byte(*destreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -5034,185 +5034,185 @@ static void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tDWORD PTR "); - } else { - DECODE_PRINTF("INC\tWORD PTR "); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tDWORD PTR "); - } else { - DECODE_PRINTF("DEC\tWORD PTR "); - } - break; - case 2: - DECODE_PRINTF("CALL\t "); - break; - case 3: - DECODE_PRINTF("CALL\tFAR "); - break; - case 4: - DECODE_PRINTF("JMP\t"); - break; - case 5: - DECODE_PRINTF("JMP\tFAR "); - break; - case 6: - DECODE_PRINTF("PUSH\t"); - break; - case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval32 = inc_long(destval32); - store_data_long(destoffset, destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: /* dec word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval32 = dec_long(destval32); - store_data_long(destoffset, destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, destval, " WORD "); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, destval2, destval, " FAR "); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destval32 = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval32); - } else { - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval32 = inc_long(destval32); + store_data_long(destoffset, destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval32 = dec_long(destval32); + store_data_long(destoffset, destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, destval, " WORD "); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, destval2, destval, " FAR "); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destval32 = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval32); + } else { + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } } else { - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = inc_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_word(*destreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = dec_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_word(*destreg); - } - break; - case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; - break; - case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - - case 4: /* jmp ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); - break; - case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*destreg32); - } else { - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*destreg); - } - break; - } + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = inc_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = dec_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg32); + } else { + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); diff --git a/src/device/oprom/x86emu/ops.h b/src/device/oprom/x86emu/ops.h index 825b9ea..a5129fe 100644 --- a/src/device/oprom/x86emu/ops.h +++ b/src/device/oprom/x86emu/ops.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for operand decoding functions. * diff --git a/src/device/oprom/x86emu/ops2.c b/src/device/oprom/x86emu/ops2.c index 95ec09a..efb7e90 100644 --- a/src/device/oprom/x86emu/ops2.c +++ b/src/device/oprom/x86emu/ops2.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,13 +28,13 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 extended two-byte processor -* instructions. +* and emulation of all the x86 extended two-byte processor +* instructions. * ****************************************************************************/
@@ -55,7 +55,7 @@ static void x86emuOp2_illegal_op(u8 op2) DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printf("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2, op2); + M.x86.R_CS, M.x86.R_IP-2, op2); HALT_SYS(); END_OF_INSTR(); } @@ -76,8 +76,8 @@ static void x86emuOp2_opc_01(u8 op2)
switch(rh) { case 4: // SMSW (Store Machine Status Word) - // Decode the mod byte to find the addressing - // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1) + // Decode the mod byte to find the addressing + // Dummy implementation: Always returns 0x10 (initial value as per intel manual volume 3, figure 8-1) #define SMSW_INITIAL_VALUE 0x10 DECODE_PRINTF("SMSW\t"); switch (mod) { @@ -106,7 +106,7 @@ static void x86emuOp2_opc_01(u8 op2) DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE IN 0F 01\n"); TRACE_REGS(); printf("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2, op2); + M.x86.R_CS, M.x86.R_IP-2, op2); HALT_SYS(); break; } @@ -216,69 +216,69 @@ int x86emu_check_jump_condition(u8 op) { switch (op) { case 0x0: - DECODE_PRINTF("JO\t"); - return ACCESS_FLAG(F_OF); + DECODE_PRINTF("JO\t"); + return ACCESS_FLAG(F_OF); case 0x1: - DECODE_PRINTF("JNO\t"); - return !ACCESS_FLAG(F_OF); - break; + DECODE_PRINTF("JNO\t"); + return !ACCESS_FLAG(F_OF); + break; case 0x2: - DECODE_PRINTF("JB\t"); - return ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JB\t"); + return ACCESS_FLAG(F_CF); + break; case 0x3: - DECODE_PRINTF("JNB\t"); - return !ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JNB\t"); + return !ACCESS_FLAG(F_CF); + break; case 0x4: - DECODE_PRINTF("JZ\t"); - return ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JZ\t"); + return ACCESS_FLAG(F_ZF); + break; case 0x5: - DECODE_PRINTF("JNZ\t"); - return !ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JNZ\t"); + return !ACCESS_FLAG(F_ZF); + break; case 0x6: - DECODE_PRINTF("JBE\t"); - return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JBE\t"); + return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x7: - DECODE_PRINTF("JNBE\t"); - return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JNBE\t"); + return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x8: - DECODE_PRINTF("JS\t"); - return ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JS\t"); + return ACCESS_FLAG(F_SF); + break; case 0x9: - DECODE_PRINTF("JNS\t"); - return !ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JNS\t"); + return !ACCESS_FLAG(F_SF); + break; case 0xa: - DECODE_PRINTF("JP\t"); - return ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JP\t"); + return ACCESS_FLAG(F_PF); + break; case 0xb: - DECODE_PRINTF("JNP\t"); - return !ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JNP\t"); + return !ACCESS_FLAG(F_PF); + break; case 0xc: - DECODE_PRINTF("JL\t"); - return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JL\t"); + return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xd: - DECODE_PRINTF("JNL\t"); - return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JNL\t"); + return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xe: - DECODE_PRINTF("JLE\t"); - return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JLE\t"); + return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; default: - DECODE_PRINTF("JNLE\t"); - return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); + DECODE_PRINTF("JNLE\t"); + return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); } }
@@ -295,7 +295,7 @@ static void x86emuOp2_long_jump(u8 op2) DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) { - M.x86.R_IP = (u16)target; + M.x86.R_IP = (u16)target; JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, M.x86.R_IP, " LONG COND "); } DECODE_CLEAR_SEGOVR(); @@ -311,9 +311,9 @@ static s32 x86emu_bswap(s32 reg) // perform the byte swap s32 temp = reg; reg = (temp & 0xFF000000) >> 24 | - (temp & 0xFF0000) >> 8 | - (temp & 0xFF00) << 8 | - (temp & 0xFF) << 24; + (temp & 0xFF0000) >> 8 | + (temp & 0xFF00) << 8 | + (temp & 0xFF) << 24; return reg; }
@@ -324,37 +324,37 @@ static void x86emuOp2_bswap(u8 op2) DECODE_PRINTF("BSWAP\t"); switch (op2) { case 0xc8: - DECODE_PRINTF("EAX\n"); - M.x86.R_EAX = x86emu_bswap(M.x86.R_EAX); - break; + DECODE_PRINTF("EAX\n"); + M.x86.R_EAX = x86emu_bswap(M.x86.R_EAX); + break; case 0xc9: - DECODE_PRINTF("ECX\n"); - M.x86.R_ECX = x86emu_bswap(M.x86.R_ECX); - break; + DECODE_PRINTF("ECX\n"); + M.x86.R_ECX = x86emu_bswap(M.x86.R_ECX); + break; case 0xca: - DECODE_PRINTF("EDX\n"); - M.x86.R_EDX = x86emu_bswap(M.x86.R_EDX); - break; + DECODE_PRINTF("EDX\n"); + M.x86.R_EDX = x86emu_bswap(M.x86.R_EDX); + break; case 0xcb: - DECODE_PRINTF("EBX\n"); - M.x86.R_EBX = x86emu_bswap(M.x86.R_EBX); - break; + DECODE_PRINTF("EBX\n"); + M.x86.R_EBX = x86emu_bswap(M.x86.R_EBX); + break; case 0xcc: - DECODE_PRINTF("ESP\n"); - M.x86.R_ESP = x86emu_bswap(M.x86.R_ESP); - break; + DECODE_PRINTF("ESP\n"); + M.x86.R_ESP = x86emu_bswap(M.x86.R_ESP); + break; case 0xcd: - DECODE_PRINTF("EBP\n"); - M.x86.R_EBP = x86emu_bswap(M.x86.R_EBP); - break; + DECODE_PRINTF("EBP\n"); + M.x86.R_EBP = x86emu_bswap(M.x86.R_EBP); + break; case 0xce: - DECODE_PRINTF("ESI\n"); - M.x86.R_ESI = x86emu_bswap(M.x86.R_ESI); - break; + DECODE_PRINTF("ESI\n"); + M.x86.R_ESI = x86emu_bswap(M.x86.R_ESI); + break; case 0xcf: - DECODE_PRINTF("EDI\n"); - M.x86.R_EDI = x86emu_bswap(M.x86.R_EDI); - break; + DECODE_PRINTF("EDI\n"); + M.x86.R_EDI = x86emu_bswap(M.x86.R_EDI); + break; } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -376,82 +376,82 @@ static void x86emuOp2_set_byte(u8 op2) START_OF_INSTR(); switch (op2) { case 0x90: - name = "SETO\t"; - cond = ACCESS_FLAG(F_OF); - break; + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; case 0x91: - name = "SETNO\t"; - cond = !ACCESS_FLAG(F_OF); - break; + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; case 0x92: - name = "SETB\t"; - cond = ACCESS_FLAG(F_CF); - break; + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; case 0x93: - name = "SETNB\t"; - cond = !ACCESS_FLAG(F_CF); - break; + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; case 0x94: - name = "SETZ\t"; - cond = ACCESS_FLAG(F_ZF); - break; + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; case 0x95: - name = "SETNZ\t"; - cond = !ACCESS_FLAG(F_ZF); - break; + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; case 0x96: - name = "SETBE\t"; - cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x97: - name = "SETNBE\t"; - cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x98: - name = "SETS\t"; - cond = ACCESS_FLAG(F_SF); - break; + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; case 0x99: - name = "SETNS\t"; - cond = !ACCESS_FLAG(F_SF); - break; + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; case 0x9a: - name = "SETP\t"; - cond = ACCESS_FLAG(F_PF); - break; + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; case 0x9b: - name = "SETNP\t"; - cond = !ACCESS_FLAG(F_PF); - break; + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; case 0x9c: - name = "SETL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9d: - name = "SETNL\t"; - cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9e: - name = "SETLE\t"; - cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; case 0x9f: - name = "SETNLE\t"; - cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; } DECODE_PRINTF(name); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - TRACE_AND_STEP(); - *destreg = cond ? 0x01 : 0x00; + destoffset = decode_rmXX_address(mod, rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -513,50 +513,50 @@ static void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BT\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } else { - u16 *srcreg,*shiftreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -576,58 +576,58 @@ static void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -646,50 +646,50 @@ static void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -737,60 +737,60 @@ static void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -810,58 +810,58 @@ static void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -880,49 +880,49 @@ static void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -941,80 +941,80 @@ static void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - res = (s16)*destreg * (s16)*srcreg; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1034,16 +1034,16 @@ static void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LSS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1063,59 +1063,59 @@ static void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTR\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1135,16 +1135,16 @@ static void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LFS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1164,16 +1164,16 @@ static void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LGS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1192,51 +1192,51 @@ static void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1258,20 +1258,20 @@ static void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1292,122 +1292,122 @@ static void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) FETCH_DECODE_MODRM(mod, rh, rl); switch (rh) { case 4: - DECODE_PRINTF("BT\t"); - break; + DECODE_PRINTF("BT\t"); + break; case 5: - DECODE_PRINTF("BTS\t"); - break; + DECODE_PRINTF("BTS\t"); + break; case 6: - DECODE_PRINTF("BTR\t"); - break; + DECODE_PRINTF("BTR\t"); + break; case 7: - DECODE_PRINTF("BTC\t"); - break; + DECODE_PRINTF("BTC\t"); + break; default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); - TRACE_REGS(); - printf("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", - M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printf("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); } if (mod < 3) {
- srcoffset = decode_rmXX_address(mod, rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_long(srcoffset, srcval | mask); - break; - case 6: - store_data_long(srcoffset, srcval & ~mask); - break; - case 7: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_word(srcoffset, srcval | mask); - break; - case 6: - store_data_word(srcoffset, srcval & ~mask); - break; - case 7: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } else { - u16 *srcreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0xF; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } + srcoffset = decode_rmXX_address(mod, rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1427,59 +1427,59 @@ static void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTC\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1498,49 +1498,49 @@ static void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSF\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcval = *DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcval = *DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1559,49 +1559,49 @@ static void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSR\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - srcval = *DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - srcval = *DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + srcval = *DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + srcval = *DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1620,51 +1620,51 @@ static void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s8)*srcreg); - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s16)((s8)*srcreg); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1686,20 +1686,20 @@ static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s16)*srcreg); + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1711,15 +1711,15 @@ static void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ -/* 0x01 */ x86emuOp2_opc_01, /* Group G (ring 0 PM) */ -/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ -/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x01 */ x86emuOp2_opc_01, /* Group G (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_invd, /* invd (ring 0 PM) */ -/* 0x09 */ x86emuOp2_wbinvd, /* wbinvd (ring 0 PM) */ +/* 0x08 */ x86emuOp2_invd, /* invd (ring 0 PM) */ +/* 0x09 */ x86emuOp2_wbinvd, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, /* 0x0c */ x86emuOp2_illegal_op, diff --git a/src/device/oprom/x86emu/prim_asm.h b/src/device/oprom/x86emu/prim_asm.h index 4fa8d55..76fd728 100644 --- a/src/device/oprom/x86emu/prim_asm.h +++ b/src/device/oprom/x86emu/prim_asm.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: Watcom C++ 10.6 or later * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Inline assembler versions of the primitive operand * functions for faster performance. At the moment this is @@ -52,843 +52,843 @@
u32 get_flags_asm(void); #pragma aux get_flags_asm = \ - "pushf" \ - "pop eax" \ - value [eax] \ + "pushf" \ + "pop eax" \ + value [eax] \ modify exact [eax];
-u16 aaa_word_asm(u32 *flags,u16 d); +u16 aaa_word_asm(u32 *flags,u16 d); #pragma aux aaa_word_asm = \ - "push [edi]" \ - "popf" \ - "aaa" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "aaa" \ + "pushf" \ + "pop [edi]" \ parm [edi] [ax] \ - value [ax] \ + value [ax] \ modify exact [ax];
-u16 aas_word_asm(u32 *flags,u16 d); +u16 aas_word_asm(u32 *flags,u16 d); #pragma aux aas_word_asm = \ - "push [edi]" \ - "popf" \ - "aas" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "aas" \ + "pushf" \ + "pop [edi]" \ parm [edi] [ax] \ - value [ax] \ + value [ax] \ modify exact [ax];
-u16 aad_word_asm(u32 *flags,u16 d); +u16 aad_word_asm(u32 *flags,u16 d); #pragma aux aad_word_asm = \ - "push [edi]" \ - "popf" \ - "aad" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "aad" \ + "pushf" \ + "pop [edi]" \ parm [edi] [ax] \ - value [ax] \ + value [ax] \ modify exact [ax];
-u16 aam_word_asm(u32 *flags,u8 d); +u16 aam_word_asm(u32 *flags,u8 d); #pragma aux aam_word_asm = \ - "push [edi]" \ - "popf" \ - "aam" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "aam" \ + "pushf" \ + "pop [edi]" \ parm [edi] [al] \ - value [ax] \ + value [ax] \ modify exact [ax];
-u8 adc_byte_asm(u32 *flags,u8 d, u8 s); +u8 adc_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux adc_byte_asm = \ - "push [edi]" \ - "popf" \ - "adc al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "adc al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 adc_word_asm(u32 *flags,u16 d, u16 s); +u16 adc_word_asm(u32 *flags,u16 d, u16 s); #pragma aux adc_word_asm = \ - "push [edi]" \ - "popf" \ - "adc ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "adc ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 adc_long_asm(u32 *flags,u32 d, u32 s); +u32 adc_long_asm(u32 *flags,u32 d, u32 s); #pragma aux adc_long_asm = \ - "push [edi]" \ - "popf" \ - "adc eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "adc eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 add_byte_asm(u32 *flags,u8 d, u8 s); +u8 add_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux add_byte_asm = \ - "push [edi]" \ - "popf" \ - "add al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "add al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 add_word_asm(u32 *flags,u16 d, u16 s); +u16 add_word_asm(u32 *flags,u16 d, u16 s); #pragma aux add_word_asm = \ - "push [edi]" \ - "popf" \ - "add ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "add ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 add_long_asm(u32 *flags,u32 d, u32 s); +u32 add_long_asm(u32 *flags,u32 d, u32 s); #pragma aux add_long_asm = \ - "push [edi]" \ - "popf" \ - "add eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "add eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 and_byte_asm(u32 *flags,u8 d, u8 s); +u8 and_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux and_byte_asm = \ - "push [edi]" \ - "popf" \ - "and al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "and al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 and_word_asm(u32 *flags,u16 d, u16 s); +u16 and_word_asm(u32 *flags,u16 d, u16 s); #pragma aux and_word_asm = \ - "push [edi]" \ - "popf" \ - "and ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "and ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 and_long_asm(u32 *flags,u32 d, u32 s); +u32 and_long_asm(u32 *flags,u32 d, u32 s); #pragma aux and_long_asm = \ - "push [edi]" \ - "popf" \ - "and eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "and eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); +u8 cmp_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux cmp_byte_asm = \ - "push [edi]" \ - "popf" \ - "cmp al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "cmp al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 cmp_word_asm(u32 *flags,u16 d, u16 s); +u16 cmp_word_asm(u32 *flags,u16 d, u16 s); #pragma aux cmp_word_asm = \ - "push [edi]" \ - "popf" \ - "cmp ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "cmp ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 cmp_long_asm(u32 *flags,u32 d, u32 s); +u32 cmp_long_asm(u32 *flags,u32 d, u32 s); #pragma aux cmp_long_asm = \ - "push [edi]" \ - "popf" \ - "cmp eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "cmp eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 daa_byte_asm(u32 *flags,u8 d); +u8 daa_byte_asm(u32 *flags,u8 d); #pragma aux daa_byte_asm = \ - "push [edi]" \ - "popf" \ - "daa" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "daa" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u8 das_byte_asm(u32 *flags,u8 d); +u8 das_byte_asm(u32 *flags,u8 d); #pragma aux das_byte_asm = \ - "push [edi]" \ - "popf" \ - "das" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "das" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u8 dec_byte_asm(u32 *flags,u8 d); +u8 dec_byte_asm(u32 *flags,u8 d); #pragma aux dec_byte_asm = \ - "push [edi]" \ - "popf" \ - "dec al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "dec al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u16 dec_word_asm(u32 *flags,u16 d); +u16 dec_word_asm(u32 *flags,u16 d); #pragma aux dec_word_asm = \ - "push [edi]" \ - "popf" \ - "dec ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "dec ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ modify exact [ax];
-u32 dec_long_asm(u32 *flags,u32 d); +u32 dec_long_asm(u32 *flags,u32 d); #pragma aux dec_long_asm = \ - "push [edi]" \ - "popf" \ - "dec eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "dec eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ modify exact [eax];
-u8 inc_byte_asm(u32 *flags,u8 d); +u8 inc_byte_asm(u32 *flags,u8 d); #pragma aux inc_byte_asm = \ - "push [edi]" \ - "popf" \ - "inc al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "inc al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u16 inc_word_asm(u32 *flags,u16 d); +u16 inc_word_asm(u32 *flags,u16 d); #pragma aux inc_word_asm = \ - "push [edi]" \ - "popf" \ - "inc ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "inc ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ modify exact [ax];
-u32 inc_long_asm(u32 *flags,u32 d); +u32 inc_long_asm(u32 *flags,u32 d); #pragma aux inc_long_asm = \ - "push [edi]" \ - "popf" \ - "inc eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "inc eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ modify exact [eax];
-u8 or_byte_asm(u32 *flags,u8 d, u8 s); +u8 or_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux or_byte_asm = \ - "push [edi]" \ - "popf" \ - "or al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "or al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 or_word_asm(u32 *flags,u16 d, u16 s); +u16 or_word_asm(u32 *flags,u16 d, u16 s); #pragma aux or_word_asm = \ - "push [edi]" \ - "popf" \ - "or ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "or ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 or_long_asm(u32 *flags,u32 d, u32 s); +u32 or_long_asm(u32 *flags,u32 d, u32 s); #pragma aux or_long_asm = \ - "push [edi]" \ - "popf" \ - "or eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "or eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 neg_byte_asm(u32 *flags,u8 d); +u8 neg_byte_asm(u32 *flags,u8 d); #pragma aux neg_byte_asm = \ - "push [edi]" \ - "popf" \ - "neg al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "neg al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u16 neg_word_asm(u32 *flags,u16 d); +u16 neg_word_asm(u32 *flags,u16 d); #pragma aux neg_word_asm = \ - "push [edi]" \ - "popf" \ - "neg ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "neg ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ modify exact [ax];
-u32 neg_long_asm(u32 *flags,u32 d); +u32 neg_long_asm(u32 *flags,u32 d); #pragma aux neg_long_asm = \ - "push [edi]" \ - "popf" \ - "neg eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "neg eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ modify exact [eax];
-u8 not_byte_asm(u32 *flags,u8 d); +u8 not_byte_asm(u32 *flags,u8 d); #pragma aux not_byte_asm = \ - "push [edi]" \ - "popf" \ - "not al" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] \ - value [al] \ + "push [edi]" \ + "popf" \ + "not al" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] \ + value [al] \ modify exact [al];
-u16 not_word_asm(u32 *flags,u16 d); +u16 not_word_asm(u32 *flags,u16 d); #pragma aux not_word_asm = \ - "push [edi]" \ - "popf" \ - "not ax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "not ax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] \ + value [ax] \ modify exact [ax];
-u32 not_long_asm(u32 *flags,u32 d); +u32 not_long_asm(u32 *flags,u32 d); #pragma aux not_long_asm = \ - "push [edi]" \ - "popf" \ - "not eax" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "not eax" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] \ + value [eax] \ modify exact [eax];
-u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); +u8 rcl_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rcl_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "rcl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 rcl_word_asm(u32 *flags,u16 d, u8 s); +u16 rcl_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rcl_word_asm = \ - "push [edi]" \ - "popf" \ - "rcl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "rcl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 rcl_long_asm(u32 *flags,u32 d, u8 s); +u32 rcl_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rcl_long_asm = \ - "push [edi]" \ - "popf" \ - "rcl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "rcl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); +u8 rcr_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rcr_byte_asm = \ - "push [edi]" \ - "popf" \ - "rcr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "rcr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 rcr_word_asm(u32 *flags,u16 d, u8 s); +u16 rcr_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rcr_word_asm = \ - "push [edi]" \ - "popf" \ - "rcr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "rcr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 rcr_long_asm(u32 *flags,u32 d, u8 s); +u32 rcr_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rcr_long_asm = \ - "push [edi]" \ - "popf" \ - "rcr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "rcr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 rol_byte_asm(u32 *flags,u8 d, u8 s); +u8 rol_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux rol_byte_asm = \ - "push [edi]" \ - "popf" \ - "rol al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "rol al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 rol_word_asm(u32 *flags,u16 d, u8 s); +u16 rol_word_asm(u32 *flags,u16 d, u8 s); #pragma aux rol_word_asm = \ - "push [edi]" \ - "popf" \ - "rol ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "rol ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 rol_long_asm(u32 *flags,u32 d, u8 s); +u32 rol_long_asm(u32 *flags,u32 d, u8 s); #pragma aux rol_long_asm = \ - "push [edi]" \ - "popf" \ - "rol eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "rol eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 ror_byte_asm(u32 *flags,u8 d, u8 s); +u8 ror_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux ror_byte_asm = \ - "push [edi]" \ - "popf" \ - "ror al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "ror al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 ror_word_asm(u32 *flags,u16 d, u8 s); +u16 ror_word_asm(u32 *flags,u16 d, u8 s); #pragma aux ror_word_asm = \ - "push [edi]" \ - "popf" \ - "ror ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "ror ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 ror_long_asm(u32 *flags,u32 d, u8 s); +u32 ror_long_asm(u32 *flags,u32 d, u8 s); #pragma aux ror_long_asm = \ - "push [edi]" \ - "popf" \ - "ror eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "ror eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 shl_byte_asm(u32 *flags,u8 d, u8 s); +u8 shl_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux shl_byte_asm = \ - "push [edi]" \ - "popf" \ - "shl al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "shl al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 shl_word_asm(u32 *flags,u16 d, u8 s); +u16 shl_word_asm(u32 *flags,u16 d, u8 s); #pragma aux shl_word_asm = \ - "push [edi]" \ - "popf" \ - "shl ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "shl ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 shl_long_asm(u32 *flags,u32 d, u8 s); +u32 shl_long_asm(u32 *flags,u32 d, u8 s); #pragma aux shl_long_asm = \ - "push [edi]" \ - "popf" \ - "shl eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "shl eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 shr_byte_asm(u32 *flags,u8 d, u8 s); +u8 shr_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux shr_byte_asm = \ - "push [edi]" \ - "popf" \ - "shr al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "shr al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 shr_word_asm(u32 *flags,u16 d, u8 s); +u16 shr_word_asm(u32 *flags,u16 d, u8 s); #pragma aux shr_word_asm = \ - "push [edi]" \ - "popf" \ - "shr ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "shr ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 shr_long_asm(u32 *flags,u32 d, u8 s); +u32 shr_long_asm(u32 *flags,u32 d, u8 s); #pragma aux shr_long_asm = \ - "push [edi]" \ - "popf" \ - "shr eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "shr eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
-u8 sar_byte_asm(u32 *flags,u8 d, u8 s); +u8 sar_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sar_byte_asm = \ - "push [edi]" \ - "popf" \ - "sar al,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [cl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "sar al,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [cl] \ + value [al] \ modify exact [al cl];
-u16 sar_word_asm(u32 *flags,u16 d, u8 s); +u16 sar_word_asm(u32 *flags,u16 d, u8 s); #pragma aux sar_word_asm = \ - "push [edi]" \ - "popf" \ - "sar ax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "sar ax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [cl] \ + value [ax] \ modify exact [ax cl];
-u32 sar_long_asm(u32 *flags,u32 d, u8 s); +u32 sar_long_asm(u32 *flags,u32 d, u8 s); #pragma aux sar_long_asm = \ - "push [edi]" \ - "popf" \ - "sar eax,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "sar eax,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [cl] \ + value [eax] \ modify exact [eax cl];
u16 shld_word_asm(u32 *flags,u16 d, u16 fill, u8 s); #pragma aux shld_word_asm = \ - "push [edi]" \ - "popf" \ - "shld ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "shld ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ modify exact [ax dx cl];
-u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +u32 shld_long_asm(u32 *flags,u32 d, u32 fill, u8 s); #pragma aux shld_long_asm = \ - "push [edi]" \ - "popf" \ - "shld eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "shld eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ modify exact [eax edx cl];
u16 shrd_word_asm(u32 *flags,u16 d, u16 fill, u8 s); #pragma aux shrd_word_asm = \ - "push [edi]" \ - "popf" \ - "shrd ax,dx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [dx] [cl] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "shrd ax,dx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [dx] [cl] \ + value [ax] \ modify exact [ax dx cl];
-u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); +u32 shrd_long_asm(u32 *flags,u32 d, u32 fill, u8 s); #pragma aux shrd_long_asm = \ - "push [edi]" \ - "popf" \ - "shrd eax,edx,cl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [edx] [cl] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "shrd eax,edx,cl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [edx] [cl] \ + value [eax] \ modify exact [eax edx cl];
-u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); +u8 sbb_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sbb_byte_asm = \ - "push [edi]" \ - "popf" \ - "sbb al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "sbb al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 sbb_word_asm(u32 *flags,u16 d, u16 s); +u16 sbb_word_asm(u32 *flags,u16 d, u16 s); #pragma aux sbb_word_asm = \ - "push [edi]" \ - "popf" \ - "sbb ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "sbb ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 sbb_long_asm(u32 *flags,u32 d, u32 s); +u32 sbb_long_asm(u32 *flags,u32 d, u32 s); #pragma aux sbb_long_asm = \ - "push [edi]" \ - "popf" \ - "sbb eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "sbb eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-u8 sub_byte_asm(u32 *flags,u8 d, u8 s); +u8 sub_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux sub_byte_asm = \ - "push [edi]" \ - "popf" \ - "sub al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "sub al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 sub_word_asm(u32 *flags,u16 d, u16 s); +u16 sub_word_asm(u32 *flags,u16 d, u16 s); #pragma aux sub_word_asm = \ - "push [edi]" \ - "popf" \ - "sub ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "sub ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 sub_long_asm(u32 *flags,u32 d, u32 s); +u32 sub_long_asm(u32 *flags,u32 d, u32 s); #pragma aux sub_long_asm = \ - "push [edi]" \ - "popf" \ - "sub eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "sub eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
void test_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux test_byte_asm = \ - "push [edi]" \ - "popf" \ - "test al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ + "push [edi]" \ + "popf" \ + "test al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ modify exact [al bl];
void test_word_asm(u32 *flags,u16 d, u16 s); #pragma aux test_word_asm = \ - "push [edi]" \ - "popf" \ - "test ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ + "push [edi]" \ + "popf" \ + "test ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ modify exact [ax bx];
void test_long_asm(u32 *flags,u32 d, u32 s); #pragma aux test_long_asm = \ - "push [edi]" \ - "popf" \ - "test eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ + "push [edi]" \ + "popf" \ + "test eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ modify exact [eax ebx];
-u8 xor_byte_asm(u32 *flags,u8 d, u8 s); +u8 xor_byte_asm(u32 *flags,u8 d, u8 s); #pragma aux xor_byte_asm = \ - "push [edi]" \ - "popf" \ - "xor al,bl" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [al] [bl] \ - value [al] \ + "push [edi]" \ + "popf" \ + "xor al,bl" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [al] [bl] \ + value [al] \ modify exact [al bl];
-u16 xor_word_asm(u32 *flags,u16 d, u16 s); +u16 xor_word_asm(u32 *flags,u16 d, u16 s); #pragma aux xor_word_asm = \ - "push [edi]" \ - "popf" \ - "xor ax,bx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [ax] [bx] \ - value [ax] \ + "push [edi]" \ + "popf" \ + "xor ax,bx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [ax] [bx] \ + value [ax] \ modify exact [ax bx];
-u32 xor_long_asm(u32 *flags,u32 d, u32 s); +u32 xor_long_asm(u32 *flags,u32 d, u32 s); #pragma aux xor_long_asm = \ - "push [edi]" \ - "popf" \ - "xor eax,ebx" \ - "pushf" \ - "pop [edi]" \ - parm [edi] [eax] [ebx] \ - value [eax] \ + "push [edi]" \ + "popf" \ + "xor eax,ebx" \ + "pushf" \ + "pop [edi]" \ + parm [edi] [eax] [ebx] \ + value [eax] \ modify exact [eax ebx];
-void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +void imul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); #pragma aux imul_byte_asm = \ - "push [edi]" \ - "popf" \ - "imul bl" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "imul bl" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ + parm [edi] [esi] [al] [bl] \ modify exact [esi ax bl];
-void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +void imul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); #pragma aux imul_word_asm = \ - "push [edi]" \ - "popf" \ - "imul bx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "imul bx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [bx]\ modify exact [esi edi ax bx dx];
-void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +void imul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); #pragma aux imul_long_asm = \ - "push [edi]" \ - "popf" \ - "imul ebx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "imul ebx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [ebx] \ modify exact [esi edi eax ebx edx];
-void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); +void mul_byte_asm(u32 *flags,u16 *ax,u8 d,u8 s); #pragma aux mul_byte_asm = \ - "push [edi]" \ - "popf" \ - "mul bl" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "mul bl" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ - parm [edi] [esi] [al] [bl] \ + parm [edi] [esi] [al] [bl] \ modify exact [esi ax bl];
-void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); +void mul_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 d,u16 s); #pragma aux mul_word_asm = \ - "push [edi]" \ - "popf" \ - "mul bx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "mul bx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [bx]\ modify exact [esi edi ax bx dx];
-void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); +void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s); #pragma aux mul_long_asm = \ - "push [edi]" \ - "popf" \ - "mul ebx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "mul ebx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [ebx] \ @@ -896,11 +896,11 @@ void mul_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 d,u32 s);
void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); #pragma aux idiv_byte_asm = \ - "push [edi]" \ - "popf" \ - "idiv bl" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "idiv bl" \ + "pushf" \ + "pop [edi]" \ "mov [esi],al" \ "mov [ecx],ah" \ parm [edi] [esi] [ecx] [ax] [bl]\ @@ -908,11 +908,11 @@ void idiv_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); #pragma aux idiv_word_asm = \ - "push [edi]" \ - "popf" \ - "idiv bx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "idiv bx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [dx] [bx]\ @@ -920,11 +920,11 @@ void idiv_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); #pragma aux idiv_long_asm = \ - "push [edi]" \ - "popf" \ - "idiv ebx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "idiv ebx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ @@ -932,11 +932,11 @@ void idiv_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s);
void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s); #pragma aux div_byte_asm = \ - "push [edi]" \ - "popf" \ - "div bl" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "div bl" \ + "pushf" \ + "pop [edi]" \ "mov [esi],al" \ "mov [ecx],ah" \ parm [edi] [esi] [ecx] [ax] [bl]\ @@ -944,11 +944,11 @@ void div_byte_asm(u32 *flags,u8 *al,u8 *ah,u16 d,u8 s);
void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s); #pragma aux div_word_asm = \ - "push [edi]" \ - "popf" \ - "div bx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "div bx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],ax" \ "mov [ecx],dx" \ parm [edi] [esi] [ecx] [ax] [dx] [bx]\ @@ -956,11 +956,11 @@ void div_word_asm(u32 *flags,u16 *ax,u16 *dx,u16 dlo,u16 dhi,u16 s);
void div_long_asm(u32 *flags,u32 *eax,u32 *edx,u32 dlo,u32 dhi,u32 s); #pragma aux div_long_asm = \ - "push [edi]" \ - "popf" \ - "div ebx" \ - "pushf" \ - "pop [edi]" \ + "push [edi]" \ + "popf" \ + "div ebx" \ + "pushf" \ + "pop [edi]" \ "mov [esi],eax" \ "mov [ecx],edx" \ parm [edi] [esi] [ecx] [eax] [edx] [ebx]\ diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c index e73f217..434aa87 100644 --- a/src/device/oprom/x86emu/prim_ops.c +++ b/src/device/oprom/x86emu/prim_ops.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C +* Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file contains the code to implement the primitive -* machine operations used by the emulation code in ops.c +* machine operations used by the emulation code in ops.c * * Carry Chain Calculation * @@ -48,23 +48,23 @@ * So, given the following table, which represents the addition of two * bits, we can derive a formula for the carry chain. * -* a b cin r cout -* 0 0 0 0 0 -* 0 0 1 1 0 -* 0 1 0 1 0 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 1 -* 1 1 0 0 1 -* 1 1 1 1 1 +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 1 1 -* 1 | 0 0 1 0 +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 * * By inspection, one gets: cc = ab + r'(a + b) * @@ -75,23 +75,23 @@ * The following table represents the subtraction of two bits, from * which we can derive a formula for the borrow chain. * -* a b bin r bout -* 0 0 0 0 0 -* 0 0 1 1 1 -* 0 1 0 1 1 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 0 -* 1 1 0 0 0 -* 1 1 1 1 1 +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 0 0 -* 1 | 1 1 1 0 +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 * * By inspection, one gets: bc = a'b + r(a' + b) * @@ -100,15 +100,15 @@ #define PRIM_OPS_NO_REDEFINE_ASM #include "x86emui.h"
-#define abs(x) ({ \ - int __x = (x); \ - (__x < 0) ? -__x : __x; \ - }) +#define abs(x) ({ \ + int __x = (x); \ + (__x < 0) ? -__x : __x; \ + })
-#define labs(x) ({ \ - long __x = (x); \ - (__x < 0) ? -__x : __x; \ - }) +#define labs(x) ({ \ + long __x = (x); \ + (__x < 0) ? -__x : __x; \ + })
/*------------------------- Global Variables ------------------------------*/
@@ -125,7 +125,7 @@ static u32 x86emu_parity_tab[8] = };
#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) -#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1)
/*----------------------------- Implementation ----------------------------*/
@@ -195,7 +195,7 @@ static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); + CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); } }
@@ -207,7 +207,7 @@ static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); + CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); } }
@@ -219,13 +219,13 @@ u16 aaa_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d += 0x6; - d += 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -240,13 +240,13 @@ u16 aas_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d -= 0x6; - d -= 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -313,7 +313,7 @@ u16 adc_word(u16 d, u16 s)
res = d + s; if (ACCESS_FLAG(F_CF)) - res++; + res++;
set_szp_flags_16((u16)res); calc_carry_chain(16,s,d,res,1); @@ -335,8 +335,8 @@ u32 adc_long(u32 d, u32 s) res = d + s;
if (ACCESS_FLAG(F_CF)) { - lo++; - res++; + lo++; + res++; }
hi = (lo >> 16) + (d >> 16) + (s >> 16); @@ -490,12 +490,12 @@ u8 daa_byte(u8 d) { u32 res = d; if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - res += 6; - SET_FLAG(F_AF); + res += 6; + SET_FLAG(F_AF); } if (res > 0x9F || ACCESS_FLAG(F_CF)) { - res += 0x60; - SET_FLAG(F_CF); + res += 0x60; + SET_FLAG(F_CF); } set_szp_flags_8((u8)res); return (u8)res; @@ -508,12 +508,12 @@ Implements the DAS instruction and side effects. u8 das_byte(u8 d) { if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - d -= 6; - SET_FLAG(F_AF); + d -= 6; + SET_FLAG(F_AF); } if (d > 0x9F || ACCESS_FLAG(F_CF)) { - d -= 0x60; - SET_FLAG(F_CF); + d -= 0x60; + SET_FLAG(F_CF); } set_szp_flags_8(d); return d; @@ -761,38 +761,38 @@ u8 rcl_byte(u8 d, u8 s) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(8-n) */ - cf = (d >> (8 - cnt)) & 0x1; - - /* get the low stuff which rotated - into the range B_7 .. B_cnt */ - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ - /* note that the right hand side done by the mask */ - res = (d << cnt) & 0xff; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (9 - cnt)) & mask; - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(n-1) <- cf */ - res |= 1 << (cnt - 1); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized this expression since it appears to - be causing OF to be missed */ - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), - F_OF); + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be missed */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF);
} return (u8)res; @@ -808,16 +808,16 @@ u16 rcl_word(u16 d, u8 s)
res = d; if ((cnt = s % 17) != 0) { - cf = (d >> (16 - cnt)) & 0x1; - res = (d << cnt) & 0xffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (17 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), - F_OF); + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); } return (u16)res; } @@ -832,16 +832,16 @@ u32 rcl_long(u32 d, u8 s)
res = d; if ((cnt = s % 33) != 0) { - cf = (d >> (32 - cnt)) & 0x1; - res = (d << cnt) & 0xffffffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (33 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), - F_OF); + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); } return res; } @@ -879,53 +879,53 @@ u8 rcr_byte(u8 d, u8 s) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(n-1) */ - if (cnt == 1) { - cf = d & 0x1; - /* note hackery here. Access_flag(..) evaluates to either - 0 if flag not set - non-zero if flag is set. - doing access_flag(..) != 0 casts that into either - 0..1 in any representation of the flags register - (i.e. packed bit array or unpacked.) - */ - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ - /* note that the right hand side done by the mask - This is effectively done by shifting the - object to the right. The result must be masked, - in case the object came in and was treated - as a negative number. Needed??? */ - - mask = (1 << (8 - cnt)) - 1; - res = (d >> cnt) & mask; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - res |= (d << (9 - cnt)); - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(8-n) <- cf */ - res |= 1 << (8 - cnt); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized... */ - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), - F_OF); - } + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } } return (u8)res; } @@ -942,22 +942,22 @@ u16 rcr_word(u16 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 17) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (16 - cnt)) - 1; - res = (d >> cnt) & mask; - res |= (d << (17 - cnt)); - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (16 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } } return (u16)res; } @@ -974,23 +974,23 @@ u32 rcr_long(u32 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 33) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (32 - cnt)) - 1; - res = (d >> cnt) & mask; - if (cnt != 1) - res |= (d << (33 - cnt)); - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (32 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } } return res; } @@ -1021,25 +1021,25 @@ u8 rol_byte(u8 d, u8 s) */ res = d; if ((cnt = s % 8) != 0) { - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ - res = (d << cnt); - - /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ - mask = (1 << cnt) - 1; - res |= (d >> (8 - cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of CF and the most significant bit. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 6) & 0x2)), - F_OF); + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u8)res; } @@ -1054,17 +1054,17 @@ u16 rol_word(u16 d, u8 s)
res = d; if ((cnt = s % 16) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (16 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 14) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u16)res; } @@ -1079,17 +1079,17 @@ u32 rol_long(u32 d, u8 s)
res = d; if ((cnt = s % 32) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (32 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 30) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return res; } @@ -1118,24 +1118,24 @@ u8 ror_byte(u8 d, u8 s) 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ res = d; - if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ - /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ - res = (d << (8 - cnt)); - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ - mask = (1 << (8 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of the two most significant bits. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); } return (u8)res; } @@ -1150,15 +1150,15 @@ u16 ror_word(u16 d, u8 s)
res = d; if ((cnt = s % 16) != 0) { - res = (d << (16 - cnt)); - mask = (1 << (16 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); } return (u16)res; } @@ -1173,15 +1173,15 @@ u32 ror_long(u32 d, u8 s)
res = d; if ((cnt = s % 32) != 0) { - res = (d << (32 - cnt)); - mask = (1 << (32 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); } return res; } @@ -1195,35 +1195,35 @@ u8 shl_byte(u8 d, u8 s) unsigned int cnt, res, cf;
if (s < 8) { - cnt = s % 8; - - /* last bit shifted out goes into carry flag */ - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (8 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - /* Needs simplification. */ - CONDITIONAL_SET_FLAG( - (((res & 0x80) == 0x80) ^ - (ACCESS_FLAG(F_CF) != 0)), - /* was (M.x86.R_FLG&F_CF)==F_CF)), */ - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1237,31 +1237,31 @@ u16 shl_word(u16 d, u8 s) unsigned int cnt, res, cf;
if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = (u16) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG( - (((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1275,28 +1275,28 @@ u32 shl_long(u32 d, u8 s) unsigned int cnt, res, cf;
if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1310,28 +1310,28 @@ u8 shr_byte(u8 d, u8 s) unsigned int cnt, res, cf;
if (s < 8) { - cnt = s % 8; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1345,28 +1345,28 @@ u16 shr_word(u16 d, u8 s) unsigned int cnt, res, cf;
if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1380,27 +1380,27 @@ u32 shr_long(u32 d, u8 s) unsigned int cnt, res, cf;
if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1417,28 +1417,28 @@ u8 sar_byte(u8 d, u8 s) sf = d & 0x80; cnt = s % 8; if (cnt > 0 && cnt < 8) { - mask = (1 << (8 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_8((u8)res); + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_8((u8)res); } else if (cnt >= 8) { - if (sf) { - res = 0xff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u8)res; } @@ -1455,28 +1455,28 @@ u16 sar_word(u16 d, u8 s) cnt = s % 16; res = d; if (cnt > 0 && cnt < 16) { - mask = (1 << (16 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_16((u16)res); + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_16((u16)res); } else if (cnt >= 16) { - if (sf) { - res = 0xffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u16)res; } @@ -1493,28 +1493,28 @@ u32 sar_long(u32 d, u8 s) cnt = s % 32; res = d; if (cnt > 0 && cnt < 32) { - mask = (1 << (32 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_32(res); + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_32(res); } else if (cnt >= 32) { - if (sf) { - res = 0xffffffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return res; } @@ -1528,28 +1528,28 @@ u16 shld_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf;
if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = (d << cnt) | (fill >> (16-cnt)); - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1563,28 +1563,28 @@ u32 shld_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf;
if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = (d << cnt) | (fill >> (32-cnt)); - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1598,28 +1598,28 @@ u16 shrd_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf;
if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1633,27 +1633,27 @@ u32 shrd_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf;
if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1668,9 +1668,9 @@ u8 sbb_byte(u8 d, u8 s) u32 bc;
if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_8((u8)res);
/* calculate the borrow chain. See note at top */ @@ -1691,9 +1691,9 @@ u16 sbb_word(u16 d, u16 s) u32 bc;
if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_16((u16)res);
/* calculate the borrow chain. See note at top */ @@ -1714,9 +1714,9 @@ u32 sbb_long(u32 d, u32 s) u32 bc;
if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s;
set_szp_flags_32(res);
@@ -1885,12 +1885,12 @@ void imul_byte(u8 s)
M.x86.R_AX = res; if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || - ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -1905,12 +1905,12 @@ void imul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) || - ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -1931,11 +1931,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) u32 rlo_lo,rlo_hi,rhi_lo;
if ((d_sign = d & 0x80000000) != 0) - d = -d; + d = -d; d_lo = d & 0xFFFF; d_hi = d >> 16; if ((s_sign = s & 0x80000000) != 0) - s = -s; + s = -s; s_lo = s & 0xFFFF; s_hi = s >> 16; rlo_lo = d_lo * s_lo; @@ -1944,11 +1944,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); *res_hi = rhi_lo; if (d_sign != s_sign) { - d = ~*res_lo; - s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); - *res_lo = ~*res_lo+1; - *res_hi = ~*res_hi+(s >> 16); - } + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } #endif }
@@ -1960,12 +1960,12 @@ void imul_long(u32 s) { imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) || - ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -1979,11 +1979,11 @@ void mul_byte(u8 s)
M.x86.R_AX = res; if (M.x86.R_AH == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -1998,11 +1998,11 @@ void mul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (M.x86.R_DX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -2034,11 +2034,11 @@ void mul_long(u32 s) M.x86.R_EDX = rhi_lo; #endif if (M.x86.R_EDX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } }
@@ -2052,14 +2052,14 @@ void idiv_byte(u8 s)
dvd = (s16)M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s8)s; mod = dvd % (s8)s; if (abs(div) > 0x7f) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (s8) div; M.x86.R_AH = (s8) mod; @@ -2075,14 +2075,14 @@ void idiv_word(u16 s)
dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s16)s; mod = dvd % (s16)s; if (abs(div) > 0x7fff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2104,14 +2104,14 @@ void idiv_long(u32 s)
dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s32)s; mod = dvd % (s32)s; if (abs(div) > 0x7fffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2125,32 +2125,32 @@ void idiv_long(u32 s) int carry;
if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (abs_h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = abs_s << (--counter); - continue; - } else { - abs_h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = abs_s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + }
} while (counter > -1); /* overflow */ if (abs_h_dvd || (l_dvd > abs_s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } /* sign */ div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); @@ -2177,14 +2177,14 @@ void div_byte(u8 s)
dvd = M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u8)s; mod = dvd % (u8)s; if (abs(div) > 0xff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (u8)div; M.x86.R_AH = (u8)mod; @@ -2200,14 +2200,14 @@ void div_word(u16 s)
dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u16)s; mod = dvd % (u16)s; if (abs(div) > 0xffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2229,14 +2229,14 @@ void div_long(u32 s)
dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u32)s; mod = dvd % (u32)s; if (abs(div) > 0xffffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2249,32 +2249,32 @@ void div_long(u32 s) int carry;
if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = s << (--counter); - continue; - } else { - h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + }
} while (counter > -1); /* overflow */ if (h_dvd || (l_dvd > s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } mod = l_dvd; #endif @@ -2296,11 +2296,11 @@ Implements the IN string instruction and side effects. static void single_in(int size) { if(size == 1) - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); else if (size == 2) - store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); else - store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); }
void ins(int size) @@ -2308,25 +2308,25 @@ void ins(int size) int inc = size;
if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* in until (E)CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? - M.x86.R_ECX : M.x86.R_CX); - while (count--) { - single_in(size); - M.x86.R_DI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_32BIT_REP) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* in until (E)CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? + M.x86.R_ECX : M.x86.R_CX); + while (count--) { + single_in(size); + M.x86.R_DI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_32BIT_REP) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_in(size); - M.x86.R_DI += inc; + single_in(size); + M.x86.R_DI += inc; } }
@@ -2350,31 +2350,31 @@ void outs(int size) int inc = size;
if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* don't care whether REPE or REPNE */ - /* out until (E)CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? - M.x86.R_ECX : M.x86.R_CX); - while (count--) { - single_out(size); - M.x86.R_SI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_32BIT_REP) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* don't care whether REPE or REPNE */ + /* out until (E)CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_32BIT_REP) ? + M.x86.R_ECX : M.x86.R_CX); + while (count--) { + single_out(size); + M.x86.R_SI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_32BIT_REP) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_out(size); - M.x86.R_SI += inc; + single_out(size); + M.x86.R_SI += inc; } }
/**************************************************************************** PARAMETERS: -addr - Address to fetch word from +addr - Address to fetch word from
REMARKS: Fetches a word from emulator memory using an absolute address. @@ -2458,39 +2458,39 @@ void x86emu_cpuid(void)
switch (feature) { case 0: - /* Regardless if we have real data from the hardware, the emulator - * will only support upto feature 1, which we set in register EAX. - * Registers EBX:EDX:ECX contain a string identifying the CPU. - */ - M.x86.R_EAX = 1; - /* EBX:EDX:ECX = "GenuineIntel" */ - M.x86.R_EBX = 0x756e6547; - M.x86.R_EDX = 0x49656e69; - M.x86.R_ECX = 0x6c65746e; - break; + /* Regardless if we have real data from the hardware, the emulator + * will only support upto feature 1, which we set in register EAX. + * Registers EBX:EDX:ECX contain a string identifying the CPU. + */ + M.x86.R_EAX = 1; + /* EBX:EDX:ECX = "GenuineIntel" */ + M.x86.R_EBX = 0x756e6547; + M.x86.R_EDX = 0x49656e69; + M.x86.R_ECX = 0x6c65746e; + break; case 1: - /* If we don't have x86 compatible hardware, we return values from an - * Intel 486dx4; which was one of the first processors to have CPUID. - */ - M.x86.R_EAX = 0x00000480; - M.x86.R_EBX = 0x00000000; - M.x86.R_ECX = 0x00000000; - M.x86.R_EDX = 0x00000002; /* VME */ - /* In the case that we have hardware CPUID instruction, we make sure - * that the features reported are limited to TSC and VME. - */ - M.x86.R_EDX &= 0x00000012; - break; + /* If we don't have x86 compatible hardware, we return values from an + * Intel 486dx4; which was one of the first processors to have CPUID. + */ + M.x86.R_EAX = 0x00000480; + M.x86.R_EBX = 0x00000000; + M.x86.R_ECX = 0x00000000; + M.x86.R_EDX = 0x00000002; /* VME */ + /* In the case that we have hardware CPUID instruction, we make sure + * that the features reported are limited to TSC and VME. + */ + M.x86.R_EDX &= 0x00000012; + break; default: - /* Finally, we don't support any additional features. Most CPUs - * return all zeros when queried for invalid or unsupported feature - * numbers. - */ - M.x86.R_EAX = 0; - M.x86.R_EBX = 0; - M.x86.R_ECX = 0; - M.x86.R_EDX = 0; - break; + /* Finally, we don't support any additional features. Most CPUs + * return all zeros when queried for invalid or unsupported feature + * numbers. + */ + M.x86.R_EAX = 0; + M.x86.R_EBX = 0; + M.x86.R_ECX = 0; + M.x86.R_EDX = 0; + break; } }
diff --git a/src/device/oprom/x86emu/prim_ops.h b/src/device/oprom/x86emu/prim_ops.h index 7230a71..e4591e9 100644 --- a/src/device/oprom/x86emu/prim_ops.h +++ b/src/device/oprom/x86emu/prim_ops.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for primitive operation functions. * @@ -42,98 +42,98 @@ #include "prim_asm.h"
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
-u16 aaa_word (u16 d); -u16 aas_word (u16 d); -u16 aad_word (u16 d); -u16 aam_word (u8 d); -u8 adc_byte (u8 d, u8 s); -u16 adc_word (u16 d, u16 s); -u32 adc_long (u32 d, u32 s); -u8 add_byte (u8 d, u8 s); -u16 add_word (u16 d, u16 s); -u32 add_long (u32 d, u32 s); -u8 and_byte (u8 d, u8 s); -u16 and_word (u16 d, u16 s); -u32 and_long (u32 d, u32 s); -u8 cmp_byte (u8 d, u8 s); -u16 cmp_word (u16 d, u16 s); -u32 cmp_long (u32 d, u32 s); -u8 daa_byte (u8 d); -u8 das_byte (u8 d); -u8 dec_byte (u8 d); -u16 dec_word (u16 d); -u32 dec_long (u32 d); -u8 inc_byte (u8 d); -u16 inc_word (u16 d); -u32 inc_long (u32 d); -u8 or_byte (u8 d, u8 s); -u16 or_word (u16 d, u16 s); -u32 or_long (u32 d, u32 s); -u8 neg_byte (u8 s); -u16 neg_word (u16 s); -u32 neg_long (u32 s); -u8 not_byte (u8 s); -u16 not_word (u16 s); -u32 not_long (u32 s); -u8 rcl_byte (u8 d, u8 s); -u16 rcl_word (u16 d, u8 s); -u32 rcl_long (u32 d, u8 s); -u8 rcr_byte (u8 d, u8 s); -u16 rcr_word (u16 d, u8 s); -u32 rcr_long (u32 d, u8 s); -u8 rol_byte (u8 d, u8 s); -u16 rol_word (u16 d, u8 s); -u32 rol_long (u32 d, u8 s); -u8 ror_byte (u8 d, u8 s); -u16 ror_word (u16 d, u8 s); -u32 ror_long (u32 d, u8 s); -u8 shl_byte (u8 d, u8 s); -u16 shl_word (u16 d, u8 s); -u32 shl_long (u32 d, u8 s); -u8 shr_byte (u8 d, u8 s); -u16 shr_word (u16 d, u8 s); -u32 shr_long (u32 d, u8 s); -u8 sar_byte (u8 d, u8 s); -u16 sar_word (u16 d, u8 s); -u32 sar_long (u32 d, u8 s); -u16 shld_word (u16 d, u16 fill, u8 s); -u32 shld_long (u32 d, u32 fill, u8 s); -u16 shrd_word (u16 d, u16 fill, u8 s); -u32 shrd_long (u32 d, u32 fill, u8 s); -u8 sbb_byte (u8 d, u8 s); -u16 sbb_word (u16 d, u16 s); -u32 sbb_long (u32 d, u32 s); -u8 sub_byte (u8 d, u8 s); -u16 sub_word (u16 d, u16 s); -u32 sub_long (u32 d, u32 s); -void test_byte (u8 d, u8 s); -void test_word (u16 d, u16 s); -void test_long (u32 d, u32 s); -u8 xor_byte (u8 d, u8 s); -u16 xor_word (u16 d, u16 s); -u32 xor_long (u32 d, u32 s); -void imul_byte (u8 s); -void imul_word (u16 s); -void imul_long (u32 s); +u16 aaa_word (u16 d); +u16 aas_word (u16 d); +u16 aad_word (u16 d); +u16 aam_word (u8 d); +u8 adc_byte (u8 d, u8 s); +u16 adc_word (u16 d, u16 s); +u32 adc_long (u32 d, u32 s); +u8 add_byte (u8 d, u8 s); +u16 add_word (u16 d, u16 s); +u32 add_long (u32 d, u32 s); +u8 and_byte (u8 d, u8 s); +u16 and_word (u16 d, u16 s); +u32 and_long (u32 d, u32 s); +u8 cmp_byte (u8 d, u8 s); +u16 cmp_word (u16 d, u16 s); +u32 cmp_long (u32 d, u32 s); +u8 daa_byte (u8 d); +u8 das_byte (u8 d); +u8 dec_byte (u8 d); +u16 dec_word (u16 d); +u32 dec_long (u32 d); +u8 inc_byte (u8 d); +u16 inc_word (u16 d); +u32 inc_long (u32 d); +u8 or_byte (u8 d, u8 s); +u16 or_word (u16 d, u16 s); +u32 or_long (u32 d, u32 s); +u8 neg_byte (u8 s); +u16 neg_word (u16 s); +u32 neg_long (u32 s); +u8 not_byte (u8 s); +u16 not_word (u16 s); +u32 not_long (u32 s); +u8 rcl_byte (u8 d, u8 s); +u16 rcl_word (u16 d, u8 s); +u32 rcl_long (u32 d, u8 s); +u8 rcr_byte (u8 d, u8 s); +u16 rcr_word (u16 d, u8 s); +u32 rcr_long (u32 d, u8 s); +u8 rol_byte (u8 d, u8 s); +u16 rol_word (u16 d, u8 s); +u32 rol_long (u32 d, u8 s); +u8 ror_byte (u8 d, u8 s); +u16 ror_word (u16 d, u8 s); +u32 ror_long (u32 d, u8 s); +u8 shl_byte (u8 d, u8 s); +u16 shl_word (u16 d, u8 s); +u32 shl_long (u32 d, u8 s); +u8 shr_byte (u8 d, u8 s); +u16 shr_word (u16 d, u8 s); +u32 shr_long (u32 d, u8 s); +u8 sar_byte (u8 d, u8 s); +u16 sar_word (u16 d, u8 s); +u32 sar_long (u32 d, u8 s); +u16 shld_word (u16 d, u16 fill, u8 s); +u32 shld_long (u32 d, u32 fill, u8 s); +u16 shrd_word (u16 d, u16 fill, u8 s); +u32 shrd_long (u32 d, u32 fill, u8 s); +u8 sbb_byte (u8 d, u8 s); +u16 sbb_word (u16 d, u16 s); +u32 sbb_long (u32 d, u32 s); +u8 sub_byte (u8 d, u8 s); +u16 sub_word (u16 d, u16 s); +u32 sub_long (u32 d, u32 s); +void test_byte (u8 d, u8 s); +void test_word (u16 d, u16 s); +void test_long (u32 d, u32 s); +u8 xor_byte (u8 d, u8 s); +u16 xor_word (u16 d, u16 s); +u32 xor_long (u32 d, u32 s); +void imul_byte (u8 s); +void imul_word (u16 s); +void imul_long (u32 s); void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s); -void mul_byte (u8 s); -void mul_word (u16 s); -void mul_long (u32 s); -void idiv_byte (u8 s); -void idiv_word (u16 s); -void idiv_long (u32 s); -void div_byte (u8 s); -void div_word (u16 s); -void div_long (u32 s); -void ins (int size); -void outs (int size); -u16 mem_access_word (int addr); -void push_word (u16 w); -void push_long (u32 w); -u16 pop_word (void); +void mul_byte (u8 s); +void mul_word (u16 s); +void mul_long (u32 s); +void idiv_byte (u8 s); +void idiv_word (u16 s); +void idiv_long (u32 s); +void div_byte (u8 s); +void div_word (u16 s); +void div_long (u32 s); +void ins (int size); +void outs (int size); +u16 mem_access_word (int addr); +void push_word (u16 w); +void push_long (u32 w); +u16 pop_word (void); u32 pop_long (void); void x86emu_cpuid (void);
@@ -226,7 +226,7 @@ void x86emu_cpuid (void); #endif
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_PRIM_OPS_H */ diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 9785a9d..8c5fda9 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: This file includes subroutines which are related to * programmed I/O and memory access. Included in this module @@ -71,7 +71,7 @@ static u8 *mem_ptr(u32 addr, int size) } if (addr < 0x200) { //printf("%x:%x updating int vector 0x%x\n", - // M.x86.R_CS, M.x86.R_IP, addr >> 2); + // M.x86.R_CS, M.x86.R_IP, addr >> 2); } retaddr = (u8 *) (M.mem_base + addr);
@@ -253,7 +253,7 @@ static u32 X86API p_inl(X86EMU_pioAddr addr) /**************************************************************************** PARAMETERS: addr - PIO address to write -val - Value to store +val - Value to store REMARKS: Default PIO byte write function. Doesn't perform real outb. ****************************************************************************/ @@ -268,7 +268,7 @@ static void X86API p_outb(X86EMU_pioAddr addr, u8 val) /**************************************************************************** PARAMETERS: addr - PIO address to write -val - Value to store +val - Value to store REMARKS: Default PIO word write function. Doesn't perform real outw. ****************************************************************************/ @@ -283,14 +283,14 @@ static void X86API p_outw(X86EMU_pioAddr addr, u16 val) /**************************************************************************** PARAMETERS: addr - PIO address to write -val - Value to store +val - Value to store REMARKS: Default PIO ;ong write function. Doesn't perform real outl. ****************************************************************************/ static void X86API p_outl(X86EMU_pioAddr addr, u32 val) { DB(if (DEBUG_IO_TRACE()) - printf("outl %#08x -> %#04x \n", val, addr);) + printf("outl %#08x -> %#04x \n", val, addr);)
outl(val, addr); return; diff --git a/src/device/oprom/x86emu/x86emui.h b/src/device/oprom/x86emu/x86emui.h index 37339d5..9e8f0ca 100644 --- a/src/device/oprom/x86emu/x86emui.h +++ b/src/device/oprom/x86emu/x86emui.h @@ -2,9 +2,9 @@ * * Realmode X86 Emulator Library * -* Copyright (C) 1996-1999 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -30,7 +30,7 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * * Description: Header file for system specific functions. These functions * are always compiled and linked in the OS dependent libraries, @@ -79,7 +79,7 @@ /*--------------------------- Inline Functions ----------------------------*/
#ifdef __cplusplus -extern "C" { /* Use "C" linkage when in C++ mode */ +extern "C" { /* Use "C" linkage when in C++ mode */ #endif
extern u8 (X86APIP sys_rdb)(u32 addr); @@ -97,7 +97,7 @@ extern void (X86APIP sys_outw)(X86EMU_pioAddr addr,u16 val); extern void (X86APIP sys_outl)(X86EMU_pioAddr addr,u32 val);
#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +} /* End of "C" linkage for C++ */ #endif
#endif /* __X86EMU_X86EMUI_H */ diff --git a/src/device/oprom/yabel/biosemu.c b/src/device/oprom/yabel/biosemu.c index d27a5f1..0c9419f 100644 --- a/src/device/oprom/yabel/biosemu.c +++ b/src/device/oprom/yabel/biosemu.c @@ -110,7 +110,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
if (biosmem_size < MIN_REQUIRED_VMEM_SIZE) { printf("Error: Not enough virtual memory: %x, required: %x!\n", - biosmem_size, MIN_REQUIRED_VMEM_SIZE); + biosmem_size, MIN_REQUIRED_VMEM_SIZE); return -1; } if (biosemu_dev_init(dev) != 0) { @@ -164,9 +164,9 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad if (c != *(rom_image + i)) { clr_ci(); printf("Copy failed at: %x/%x\n", i, - bios_device.img_size); + bios_device.img_size); printf("rom_image(%x): %x, mem_img(%x): %x\n", - i, *(rom_image + i), i, *(mem_img + i)); + i, *(rom_image + i), i, *(mem_img + i)); break; } clr_ci(); @@ -392,8 +392,8 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad } else { printf("Stack unclean, initialization probably NOT COMPLETE!\n"); DEBUG_PRINTF("SS:SP = %04x:%04x, expected: %04x:%04x\n", - M.x86.R_SS, M.x86.R_SP, STACK_SEGMENT, - STACK_START_OFFSET); + M.x86.R_SS, M.x86.R_SP, STACK_SEGMENT, + STACK_START_OFFSET); }
// TODO: according to the BIOS Boot Spec initializations may be ended using INT18h and setting diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index 2c3dc33..b28c472 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -53,8 +53,8 @@ u64 get_time(void)
__asm__ __volatile__( "rdtsc" - : "=a"(eax), "=d"(edx) - : /* no inputs, no clobber */); + : "=a"(eax), "=d"(edx) + : /* no inputs, no clobber */); act = ((u64) edx << 32) | eax; #endif return act; diff --git a/src/device/oprom/yabel/compat/rtas.h b/src/device/oprom/yabel/compat/rtas.h index 25cabf4..d49390a 100644 --- a/src/device/oprom/yabel/compat/rtas.h +++ b/src/device/oprom/yabel/compat/rtas.h @@ -17,13 +17,13 @@ #include "of.h"
typedef struct dtime { - unsigned int year; - unsigned int month; - unsigned int day; - unsigned int hour; - unsigned int minute; - unsigned int second; - unsigned int nano; + unsigned int year; + unsigned int month; + unsigned int day; + unsigned int hour; + unsigned int minute; + unsigned int second; + unsigned int nano; } dtime;
typedef void (*thread_t) (int); diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 2f41847..7a511cf 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -141,7 +141,7 @@ biosemu_dev_get_addr_info(void) assigned_address_t buf[11]; len = of_getprop(bios_device.phandle, "assigned-addresses", buf, - sizeof(buf)); + sizeof(buf)); bios_device.bus = buf[0].bus; bios_device.devfn = buf[0].devfn; DEBUG_PRINTF("bus: %x, devfn: %x\n", bios_device.bus, @@ -340,7 +340,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) if (rom_signature != 0xaa55) { printf ("Error: invalid Expansion ROM signature: %02x!\n", - *((u16 *) rom_base_addr)); + *((u16 *) rom_base_addr)); return -1; } set_ci(); @@ -348,11 +348,11 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) pci_ds_offset = in16le((void *) (rom_base_addr + 0x18)); //copy the PCI Data Structure memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset), - sizeof(pci_ds)); + sizeof(pci_ds)); clr_ci(); #if CONFIG_X86EMU_DEBUG DEBUG_PRINTF("PCI Data Structure @%lx:\n", - rom_base_addr + pci_ds_offset); + rom_base_addr + pci_ds_offset); dump((void *) &pci_ds, sizeof(pci_ds)); #endif if (strncmp((const char *) pci_ds.signature, "PCIR", 4) != 0) { @@ -368,13 +368,13 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr) if (pci_ds.vendor_id != bios_device.pci_vendor_id) { printf ("Image has invalid Vendor ID: %04x, expected: %04x\n", - pci_ds.vendor_id, bios_device.pci_vendor_id); + pci_ds.vendor_id, bios_device.pci_vendor_id); break; } if (pci_ds.device_id != bios_device.pci_device_id) { printf ("Image has invalid Device ID: %04x, expected: %04x\n", - pci_ds.device_id, bios_device.pci_device_id); + pci_ds.device_id, bios_device.pci_device_id); break; } #endif diff --git a/src/device/oprom/yabel/interrupt.c b/src/device/oprom/yabel/interrupt.c index cf430be..5e7f36c 100644 --- a/src/device/oprom/yabel/interrupt.c +++ b/src/device/oprom/yabel/interrupt.c @@ -145,7 +145,7 @@ handleInt10(void) printf("%c", M.x86.R_AL); // for debugging, to read all lines //if (M.x86.R_AL == 0xd) // carriage return - // printf("\n"); + // printf("\n"); } } break; @@ -160,7 +160,7 @@ handleInt10(void) break; default: printf("%s(): unknown function (%x) for int10 handler.\n", - __func__, M.x86.R_AH); + __func__, M.x86.R_AH); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); @@ -224,7 +224,7 @@ translate_keycode(u64 * keycode) break; default: printf("%s(): unknown multibyte keycode: %llx\n", - __func__, *keycode); + __func__, *keycode); break; } } @@ -290,11 +290,11 @@ handleInt16(void) while ((c = -1 /*getchar()*/) != -1) { *keycode = (*keycode << 8) | c; DEBUG_PRINTF(" key read: %0llx\n", - *keycode); + *keycode); } translate_keycode(keycode); DEBUG_PRINTF(" translated key: %0llx\n", - *keycode); + *keycode); if (*keycode == 0) { //not found SET_FLAG(F_ZF); @@ -309,7 +309,7 @@ handleInt16(void) break; default: printf("%s(): unknown function (%x) for int16 handler.\n", - __func__, M.x86.R_AH); + __func__, M.x86.R_AH); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); @@ -348,7 +348,7 @@ handleInt1a(void) if (dev != 0) { DEBUG_PRINTF_INTR ("%s(): function %x: PCI Find Device --> 0x%04x\n", - __func__, M.x86.R_AX, M.x86.R_BX); + __func__, M.x86.R_AX, M.x86.R_BX);
M.x86.R_BH = dev->bus->secondary; M.x86.R_BL = dev->path.pci.devfn; @@ -361,16 +361,16 @@ handleInt1a(void) // device index must be 0 && (M.x86.R_SI == 0)) { CLEAR_FLAG(F_CF); - M.x86.R_AH = 0x00; // return code: success + M.x86.R_AH = 0x00; // return code: success M.x86.R_BH = bios_device.bus; M.x86.R_BL = bios_device.devfn; #endif } else { DEBUG_PRINTF_INTR ("%s(): function %x: invalid device/vendor/device index! (%04x/%04x/%02x expected: %04x/%04x/00) \n", - __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, - M.x86.R_SI, bios_device.pci_device_id, - bios_device.pci_vendor_id); + __func__, M.x86.R_AX, M.x86.R_CX, M.x86.R_DX, + M.x86.R_SI, bios_device.pci_device_id, + bios_device.pci_vendor_id);
SET_FLAG(F_CF); M.x86.R_AH = 0x86; // return code: device not found @@ -398,8 +398,8 @@ handleInt1a(void) #endif printf ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", - __func__, bus, bios_device.bus, devfn, - bios_device.devfn, offs); + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); SET_FLAG(F_CF); M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); @@ -411,45 +411,45 @@ handleInt1a(void) #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config8(dev, offs); #else - (u8) rtas_pci_config_read(bios_device. + (u8) rtas_pci_config_read(bios_device. puid, 1, bus, devfn, offs); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); + ("%s(): function %x: PCI Config Read @%02x --> 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); break; case 0xb109: M.x86.R_CX = #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config16(dev, offs); #else - (u16) rtas_pci_config_read(bios_device. + (u16) rtas_pci_config_read(bios_device. puid, 2, bus, devfn, offs); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); + ("%s(): function %x: PCI Config Read @%02x --> 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); break; case 0xb10a: M.x86.R_ECX = #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_read_config32(dev, offs); #else - (u32) rtas_pci_config_read(bios_device. + (u32) rtas_pci_config_read(bios_device. puid, 4, bus, devfn, offs); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); + ("%s(): function %x: PCI Config Read @%02x --> 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); break; } CLEAR_FLAG(F_CF); @@ -467,8 +467,8 @@ handleInt1a(void) // fail accesses to any device but ours... printf ("%s(): Config read access invalid! bus: %x (%x), devfn: %x (%x), offs: %x\n", - __func__, bus, bios_device.bus, devfn, - bios_device.devfn, offs); + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); SET_FLAG(F_CF); M.x86.R_AH = 0x87; //return code: bad pci register HALT_SYS(); @@ -480,36 +480,36 @@ handleInt1a(void) pci_write_config8(bios_device.dev, offs, M.x86.R_CL); #else rtas_pci_config_write(bios_device.puid, 1, bus, - devfn, offs, M.x86.R_CL); + devfn, offs, M.x86.R_CL); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CL); + ("%s(): function %x: PCI Config Write @%02x <-- 0x%02x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CL); break; case 0xb10c: #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config16(bios_device.dev, offs, M.x86.R_CX); #else rtas_pci_config_write(bios_device.puid, 2, bus, - devfn, offs, M.x86.R_CX); + devfn, offs, M.x86.R_CX); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_CX); + ("%s(): function %x: PCI Config Write @%02x <-- 0x%04x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_CX); break; case 0xb10d: #if CONFIG_PCI_OPTION_ROM_RUN_YABEL pci_write_config32(bios_device.dev, offs, M.x86.R_ECX); #else rtas_pci_config_write(bios_device.puid, 4, bus, - devfn, offs, M.x86.R_ECX); + devfn, offs, M.x86.R_ECX); #endif DEBUG_PRINTF_INTR - ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", - __func__, M.x86.R_AX, offs, - M.x86.R_ECX); + ("%s(): function %x: PCI Config Write @%02x <-- 0x%08x\n", + __func__, M.x86.R_AX, offs, + M.x86.R_ECX); break; } CLEAR_FLAG(F_CF); @@ -518,7 +518,7 @@ handleInt1a(void) break; default: printf("%s(): unknown function (%x) for int1a handler.\n", - __func__, M.x86.R_AX); + __func__, M.x86.R_AX); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); @@ -554,8 +554,8 @@ handleInterrupt(int intNum) #if 0 // ignore interrupt... DEBUG_PRINTF_INTR - ("%s(%x): invalid interrupt Vector (%08x) found, interrupt ignored...\n", - __func__, intNum, my_rdl(intNum * 4)); + ("%s(%x): invalid interrupt Vector (%08x) found, interrupt ignored...\n", + __func__, intNum, my_rdl(intNum * 4)); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); @@ -585,7 +585,7 @@ handleInterrupt(int intNum) break; default: printf("Interrupt %#x (Vector: %x) not implemented\n", intNum, - my_rdl(intNum * 4)); + my_rdl(intNum * 4)); DEBUG_PRINTF_INTR("AX=%04x BX=%04x CX=%04x DX=%04x\n", M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); diff --git a/src/device/oprom/yabel/io.c b/src/device/oprom/yabel/io.c index 94f610d..174948f 100644 --- a/src/device/oprom/yabel/io.c +++ b/src/device/oprom/yabel/io.c @@ -134,47 +134,47 @@ void my_outl(X86EMU_pioAddr addr, u32 val) static unsigned int read_io(void *addr, size_t sz) { - unsigned int ret; + unsigned int ret; /* since we are using inb instructions, we need the port number as 16bit value */ u16 port = (u16)(u32) addr;
- switch (sz) { - case 1: + switch (sz) { + case 1: ret = inb(port); - break; - case 2: + break; + case 2: ret = inw(port); - break; - case 4: + break; + case 4: ret = inl(port); - break; - default: - ret = 0; - } + break; + default: + ret = 0; + }
- return ret; + return ret; }
static int write_io(void *addr, unsigned int value, size_t sz) { u16 port = (u16)(u32) addr; - switch (sz) { + switch (sz) { /* since we are using inb instructions, we need the port number as 16bit value */ - case 1: + case 1: outb(value, port); - break; - case 2: + break; + case 2: outw(value, port); - break; - case 4: + break; + case 4: outl(value, port); - break; - default: - return -1; - } + break; + default: + return -1; + }
- return 0; + return 0; }
u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size); @@ -222,7 +222,7 @@ my_inb(X86EMU_pioAddr addr) default: DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", - __func__, addr); + __func__, addr); rval = *((u8 *) (bios_device.io_buffer + addr)); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %02x\n", __func__, addr, rval); @@ -266,7 +266,7 @@ my_inw(X86EMU_pioAddr addr) default: DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", - __func__, addr); + __func__, addr); u16 rval = in16le((void *) bios_device.io_buffer + addr); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %04x\n", @@ -312,7 +312,7 @@ my_inl(X86EMU_pioAddr addr) default: DEBUG_PRINTF_IO ("%s(%04x) reading from bios_device.io_buffer\n", - __func__, addr); + __func__, addr); u32 rval = in32le((void *) bios_device.io_buffer + addr); DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %08x\n", @@ -348,7 +348,7 @@ my_outb(X86EMU_pioAddr addr, u8 val) default: DEBUG_PRINTF_IO ("%s(%04x,%02x) writing to bios_device.io_buffer\n", - __func__, addr, val); + __func__, addr, val); *((u8 *) (bios_device.io_buffer + addr)) = val; break; } @@ -389,7 +389,7 @@ my_outw(X86EMU_pioAddr addr, u16 val) default: DEBUG_PRINTF_IO ("%s(%04x,%04x) writing to bios_device.io_buffer\n", - __func__, addr, val); + __func__, addr, val); out16le((void *) bios_device.io_buffer + addr, val); break; } @@ -433,7 +433,7 @@ my_outl(X86EMU_pioAddr addr, u32 val) default: DEBUG_PRINTF_IO ("%s(%04x,%08x) writing to bios_device.io_buffer\n", - __func__, addr, val); + __func__, addr, val); out32le((void *) bios_device.io_buffer + addr, val); break; } @@ -468,13 +468,13 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) #else dev = bios_device.dev; if ((bus != bios_device.bus) - || (devfn != bios_device.devfn)) { + || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... #endif printf - ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", - __func__, bus, bios_device.bus, devfn, - bios_device.devfn, offs); + ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", + __func__, bus, bios_device.bus, devfn, + bios_device.devfn, offs); SET_FLAG(F_CF); HALT_SYS(); return 0; @@ -493,14 +493,14 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size) } #else rval = - (u32) rtas_pci_config_read(bios_device. + (u32) rtas_pci_config_read(bios_device. puid, size, bus, devfn, offs); #endif DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", - __func__, addr, offs, size, rval); + ("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n", + __func__, addr, offs, size, rval); } } } @@ -526,8 +526,8 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) || (devfn != bios_device.devfn)) { // fail accesses to any device but ours... printf - ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", - bus, devfn >> 3, devfn & 7, offs); + ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", + bus, devfn >> 3, devfn & 7, offs); #if !CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG HALT_SYS(); #endif @@ -546,12 +546,12 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) } #else rtas_pci_config_write(bios_device.puid, - size, bus, devfn, offs, - val); + size, bus, devfn, offs, + val); #endif DEBUG_PRINTF_IO - ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", - __func__, addr, offs, size, val); + ("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n", + __func__, addr, offs, size, val); } } } diff --git a/src/device/oprom/yabel/mem.c b/src/device/oprom/yabel/mem.c index a7d0289..bc6d370 100644 --- a/src/device/oprom/yabel/mem.c +++ b/src/device/oprom/yabel/mem.c @@ -214,7 +214,7 @@ my_rdb(u32 addr) return rval; } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { @@ -256,7 +256,7 @@ my_rdw(u32 addr) // unaligned access, read single bytes set_ci(); rval = (*((u8 *) translated_addr)) | - (*((u8 *) translated_addr + 1) << 8); + (*((u8 *) translated_addr + 1) << 8); clr_ci(); } } @@ -265,7 +265,7 @@ my_rdw(u32 addr) return rval; } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { @@ -309,9 +309,9 @@ my_rdl(u32 addr) // unaligned access, read single bytes set_ci(); rval = (*((u8 *) translated_addr)) | - (*((u8 *) translated_addr + 1) << 8) | - (*((u8 *) translated_addr + 2) << 16) | - (*((u8 *) translated_addr + 3) << 24); + (*((u8 *) translated_addr + 1) << 8) | + (*((u8 *) translated_addr + 2) << 16) | + (*((u8 *) translated_addr + 3) << 24); clr_ci(); } } @@ -321,7 +321,7 @@ my_rdl(u32 addr) return rval; } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { @@ -356,7 +356,7 @@ my_wrb(u32 addr, u8 val) clr_ci(); } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { @@ -394,15 +394,15 @@ my_wrw(u32 addr, u16 val) // unaligned access, write single bytes set_ci(); *((u8 *) translated_addr) = - (u8) (val & 0x00FF); + (u8) (val & 0x00FF); *((u8 *) translated_addr + 1) = - (u8) ((val & 0xFF00) >> 8); + (u8) ((val & 0xFF00) >> 8); clr_ci(); } } } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { @@ -441,19 +441,19 @@ my_wrl(u32 addr, u32 val) // unaligned access, write single bytes set_ci(); *((u8 *) translated_addr) = - (u8) (val & 0x000000FF); + (u8) (val & 0x000000FF); *((u8 *) translated_addr + 1) = - (u8) ((val & 0x0000FF00) >> 8); + (u8) ((val & 0x0000FF00) >> 8); *((u8 *) translated_addr + 2) = - (u8) ((val & 0x00FF0000) >> 16); + (u8) ((val & 0x00FF0000) >> 16); *((u8 *) translated_addr + 3) = - (u8) ((val & 0xFF000000) >> 24); + (u8) ((val & 0xFF000000) >> 24); clr_ci(); } } } else if (addr > M.mem_size) { DEBUG_PRINTF("%s(%08x): Memory Access out of range!\n", - __func__, addr); + __func__, addr); //disassemble_forward(M.x86.saved_cs, M.x86.saved_ip, 1); HALT_SYS(); } else { diff --git a/src/device/oprom/yabel/pmm.c b/src/device/oprom/yabel/pmm.c index d6c528d..e96c7d3 100644 --- a/src/device/oprom/yabel/pmm.c +++ b/src/device/oprom/yabel/pmm.c @@ -114,8 +114,8 @@ void pmm_handleInt() /* request to allocate in conventional memory */ if (curr_pmm_allocation_index >= MAX_PMM_AREAS) { printf - ("%s: pmmAllocate: Maximum Number of allocatable areas reached (%d), cannot allocate more memory!\n", - __func__, MAX_PMM_AREAS); + ("%s: pmmAllocate: Maximum Number of allocatable areas reached (%d), cannot allocate more memory!\n", + __func__, MAX_PMM_AREAS); rval = 0; goto exit; } @@ -127,10 +127,10 @@ void pmm_handleInt() /* we have already allocated... get the new next_offset * from the previous pmm_allocation_t */ next_offset = - pmm_allocation_array - [curr_pmm_allocation_index - 1].offset + - pmm_allocation_array - [curr_pmm_allocation_index - 1].length; + pmm_allocation_array + [curr_pmm_allocation_index - 1].offset + + pmm_allocation_array + [curr_pmm_allocation_index - 1].length; } DEBUG_PRINTF_PMM("%s: next_offset: 0x%x\n", __func__, next_offset); @@ -168,8 +168,8 @@ void pmm_handleInt() if ((next_offset + length) > 0xFFFF) { rval = 0; printf - ("%s: pmmAllocate: Not enough memory available for allocation!\n", - __func__); + ("%s: pmmAllocate: Not enough memory available for allocation!\n", + __func__); goto exit; } curr_pmm_allocation_index++; @@ -181,12 +181,12 @@ void pmm_handleInt() rval = ((u32) (PMM_CONV_SEGMENT << 16)) | next_offset; DEBUG_PRINTF_PMM ("%s: pmmAllocate: allocated memory at %x\n", - __func__, rval); + __func__, rval); } else { rval = 0; printf ("%s: pmmAllocate: allocation in extended memory not supported!\n", - __func__); + __func__); } goto exit; case 1: @@ -198,18 +198,18 @@ void pmm_handleInt() for (i = 0; i < curr_pmm_allocation_index; i++) { if (pmm_allocation_array[i].handle == handle) { DEBUG_PRINTF_PMM - ("%s: pmmFind: found allocated memory at %x\n", - __func__, rval); + ("%s: pmmFind: found allocated memory at %x\n", + __func__, rval); /* return the 32bit "physical" address, i.e. combination of segment and offset */ rval = - ((u32) (PMM_CONV_SEGMENT << 16)) | - pmm_allocation_array[i].offset; + ((u32) (PMM_CONV_SEGMENT << 16)) | + pmm_allocation_array[i].offset; } } if (rval == 0) { DEBUG_PRINTF_PMM ("%s: pmmFind: handle (%x) not found!\n", - __func__, handle); + __func__, handle); } goto exit; case 2: @@ -233,36 +233,36 @@ void pmm_handleInt() /* we found the requested buffer, rval = 0 */ rval = 0; DEBUG_PRINTF_PMM - ("%s: pmmDeallocate: found allocated memory at index: %d\n", - __func__, i); + ("%s: pmmDeallocate: found allocated memory at index: %d\n", + __func__, i); /* copy the remaining elements in pmm_allocation_array one position up */ j = i; for (; j < curr_pmm_allocation_index; j++) { pmm_allocation_array[j] = - pmm_allocation_array[j + 1]; + pmm_allocation_array[j + 1]; } /* move curr_pmm_allocation_index one up, too */ curr_pmm_allocation_index--; /* finally clean last element */ pmm_allocation_array[curr_pmm_allocation_index]. - handle = 0; + handle = 0; pmm_allocation_array[curr_pmm_allocation_index]. - offset = 0; + offset = 0; pmm_allocation_array[curr_pmm_allocation_index]. - length = 0; + length = 0; break; } } if (rval != 0) { DEBUG_PRINTF_PMM ("%s: pmmDeallocate: offset (%x) not found, cannot deallocate!\n", - __func__, buffer); + __func__, buffer); } goto exit; default: /* invalid/unimplemented function */ printf("%s: invalid PMM function (0x%04x) called!\n", - __func__, function); + __func__, function); /* PMM spec says if function is invalid, return 0xFFFFFFFF */ rval = 0xFFFFFFFF; goto exit; @@ -278,9 +278,9 @@ exit: for (i = 0; i < MAX_PMM_AREAS; i++) { DEBUG_PRINTF_PMM ("%d:\n\thandle: %x\n\toffset: %x\n\tlength: %x\n", - i, pmm_allocation_array[i].handle, - pmm_allocation_array[i].offset, - pmm_allocation_array[i].length); + i, pmm_allocation_array[i].handle, + pmm_allocation_array[i].offset, + pmm_allocation_array[i].length); } } return; diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 8658b77..49051ca 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -106,7 +106,7 @@ vbe_info(vbe_info_t * info) // offset 6: 32bit le containing segment:offset of OEM String in virtual Mem. info->oem_string_ptr = biosmem + ((in16le(vbe_info_buffer + 8) << 4) + - in16le(vbe_info_buffer + 6)); + in16le(vbe_info_buffer + 6));
// offset 10: 32bit le capabilities info->capabilities = in32le(vbe_info_buffer + 10); @@ -125,7 +125,7 @@ vbe_info(vbe_info_t * info) while ((i < (sizeof(info->video_mode_list) / sizeof(info->video_mode_list[0]))) - && (info->video_mode_list[i - 1] != 0xFFFF)); + && (info->video_mode_list[i - 1] != 0xFFFF));
//offset 18: 16bit le total memory in 64KB blocks info->total_memory = in16le(vbe_info_buffer + 18); @@ -172,8 +172,8 @@ vbe_get_mode_info(vbe_mode_info_t * mode_info)
//pointer to mode_info_block is in ES:DI memcpy(mode_info->mode_info_block, - biosmem + ((M.x86.R_ES << 4) + M.x86.R_DI), - sizeof(mode_info->mode_info_block)); + biosmem + ((M.x86.R_ES << 4) + M.x86.R_DI), + sizeof(mode_info->mode_info_block)); mode_info_valid = 1;
//printf("Mode Info Dump:"); @@ -410,8 +410,8 @@ vbe_get_ddc_info(vbe_ddc_info_t * ddc_info) }
memcpy(ddc_info->edid_block_zero, - biosmem + (M.x86.R_ES << 4) + M.x86.R_DI, - sizeof(ddc_info->edid_block_zero)); + biosmem + (M.x86.R_ES << 4) + M.x86.R_DI, + sizeof(ddc_info->edid_block_zero));
return 0; } @@ -457,8 +457,8 @@ vbe_get_info(void) // as input, it must contain a screen_info_input_t with the following content: // byte[0:3] = "DDC\0" (zero-terminated signature header) // byte[4:5] = reserved space for the return struct... just in case we ever change - // the struct and don't have reserved enough memory (and let's hope the struct - // never gets larger than 64KB) + // the struct and don't have reserved enough memory (and let's hope the struct + // never gets larger than 64KB) // byte[6] = monitor port number for DDC requests ("only" one byte... so lets hope we never have more than 255 monitors... // byte[7:8] = max. screen width (OF may want to limit this) // byte[9] = required color depth in bpp @@ -514,7 +514,7 @@ vbe_get_info(void) } DEBUG_PRINTF_VBE("DDC: found display type %d\n", output->display_type); memcpy(output->edid_block_zero, ddc_info.edid_block_zero, - sizeof(ddc_info.edid_block_zero)); + sizeof(ddc_info.edid_block_zero)); i = 0; vbe_mode_info_t mode_info; vbe_mode_info_t best_mode_info; @@ -621,14 +621,14 @@ vbe_get_info(void) for (g = 0; g < mc_size; g++) { for (b = 0; b < mc_size; b++) { curr_color_index = - (r * mc_size * mc_size) + - (g * mc_size) + b; + (r * mc_size * mc_size) + + (g * mc_size) + b; curr_color = 0; curr_color |= ((u32) mixed_color_values[r]) << 16; //red value curr_color |= ((u32) mixed_color_values[g]) << 8; //green value curr_color |= (u32) mixed_color_values[b]; //blue value vbe_set_color(curr_color_index, - curr_color); + curr_color); } } } @@ -726,8 +726,8 @@ void vbe_set_graphics(void) // int imagesize = 1024*768*2;
unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + "bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 1d998ca..65cdca0 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -147,7 +147,7 @@ unsigned pci_find_next_capability(struct device *dev, unsigned cap, pos &= ~3; this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", - this_cap, pos); + this_cap, pos); if (this_cap == 0xff) break;
@@ -244,8 +244,8 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) if (moving == 0) { if (value != 0) { printk(BIOS_DEBUG, "%s register %02lx(%08lx), " - "read-only ignoring it\n", - dev_path(dev), index, value); + "read-only ignoring it\n", + dev_path(dev), index, value); } resource->flags = 0; } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) { @@ -275,7 +275,7 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index) /* Invalid value. */ printk(BIOS_ERR, "Broken BAR with value %lx\n", attr); printk(BIOS_ERR, " on dev %s at index %02lx\n", - dev_path(dev), index); + dev_path(dev), index); resource->flags = 0; } } @@ -330,8 +330,8 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index) } else { if (value != 0) { printk(BIOS_DEBUG, "%s register %02lx(%08lx), " - "read-only ignoring it\n", - dev_path(dev), index, value); + "read-only ignoring it\n", + dev_path(dev), index, value); } resource->flags = 0; } @@ -359,7 +359,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) }
static void pci_record_bridge_resource(struct device *dev, resource_t moving, - unsigned index, unsigned long type) + unsigned index, unsigned long type) { struct resource *resource; unsigned long gran; @@ -470,8 +470,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource) /* Make certain the resource has actually been assigned a value. */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " - "assigned\n", dev_path(dev), resource->index, - resource_type(resource), resource->size); + "assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); return; }
@@ -555,7 +555,7 @@ static void pci_set_resource(struct device *dev, struct resource *resource) /* Don't let me think I stored the resource. */ resource->flags &= ~IORESOURCE_STORED; printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n", - resource->index); + resource->index); }
report_resource_stored(dev, resource, ""); @@ -717,12 +717,12 @@ static struct pci_operations pci_dev_ops_pci = {
struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = &pci_dev_ops_pci, + .init = pci_dev_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &pci_dev_ops_pci, };
/** Default device operations for PCI bridges */ @@ -732,13 +732,13 @@ static struct pci_operations pci_bus_ops_pci = {
struct device_operations default_pci_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &pci_bus_ops_pci, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pci_bus_ops_pci, };
/** @@ -776,7 +776,7 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) if ((flags >> 13) == 1) { /* Host or Secondary Interface */ printk(BIOS_DEBUG, "%s subordinate bus HT\n", - dev_path(dev)); + dev_path(dev)); return &default_ht_ops_bus; } } @@ -792,11 +792,11 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n", - dev_path(dev)); + dev_path(dev)); return &default_pciexp_ops_bus; case PCI_EXP_TYPE_PCI_BRIDGE: printk(BIOS_DEBUG, "%s subordinate PCI\n", - dev_path(dev)); + dev_path(dev)); return &default_pci_ops_bus; default: break; @@ -853,8 +853,8 @@ static void set_pci_ops(struct device *dev) device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", - dev_path(dev), driver->vendor, driver->device, - (driver->ops->scan_bus ? "bus " : "")); + dev_path(dev), driver->vendor, driver->device, + (driver->ops->scan_bus ? "bus " : "")); return; } } @@ -880,9 +880,9 @@ default: bad: if (dev->enabled) { printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown " - "header type %02x, ignoring.\n", dev_path(dev), - dev->vendor, dev->device, - dev->class >> 8, dev->hdr_type); + "header type %02x, ignoring.\n", dev_path(dev), + dev->vendor, dev->device, + dev->class >> 8, dev->hdr_type); } } } @@ -907,7 +907,7 @@ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn) for (; *list; list = &(*list)->sibling) { if ((*list)->path.type != DEVICE_PATH_PCI) { printk(BIOS_ERR, "child %s not a PCI device\n", - dev_path(*list)); + dev_path(*list)); continue; } if ((*list)->path.pci.devfn == devfn) { @@ -977,7 +977,7 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) if ((id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { printk(BIOS_SPEW, "%s, bad id 0x%x\n", - dev_path(&dummy), id); + dev_path(&dummy), id); return NULL; } dev = alloc_dev(bus, &dummy.path); @@ -1011,7 +1011,7 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) (id == 0x0000ffff) || (id == 0xffff0000)) { if (dev->enabled) { printk(BIOS_INFO, "PCI: Static device %s not " - "found, disabling it.\n", dev_path(dev)); + "found, disabling it.\n", dev_path(dev)); dev->enabled = 0; } return dev; @@ -1047,8 +1047,8 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
/* Display the device. */ printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev), - dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled", - dev->ops ? "" : " No operations"); + dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled", + dev->ops ? "" : " No operations");
return dev; } @@ -1090,7 +1090,7 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
#if CONFIG_PCI_BUS_SEGN_BITS printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n", - bus->secondary >> 8, bus->secondary & 0xff); + bus->secondary >> 8, bus->secondary & 0xff); #else printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); #endif @@ -1098,9 +1098,9 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, /* Maximum sane devfn is 0xFF. */ if (max_devfn > 0xff) { printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - " - "devfn %x\n", min_devfn, max_devfn); + "devfn %x\n", min_devfn, max_devfn); printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. " - "Using 0xff.\n"); + "Using 0xff.\n"); max_devfn=0xff; }
@@ -1180,9 +1180,9 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, */ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, unsigned int (*do_scan_bus) (struct bus * bus, - unsigned min_devfn, - unsigned max_devfn, - unsigned int max)) + unsigned min_devfn, + unsigned max_devfn, + unsigned int max)) { struct bus *bus; u32 buses; @@ -1293,8 +1293,8 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) * @param bus Pointer to the bus structure. * @param slot TODO * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD - * of this slot. The particular IRQ #s that are passed in depend on the - * routing inside your southbridge and on your board. + * of this slot. The particular IRQ #s that are passed in depend on the + * routing inside your southbridge and on your board. */ void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]) @@ -1319,7 +1319,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, irq = pIntAtoD[line - 1];
printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n", - irq, bus, slot, funct); + irq, bus, slot, funct);
pci_write_config8(pdev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); @@ -1332,7 +1332,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot, #if CONFIG_PC80_SYSTEM /* Change to level triggered. */ i8259_configure_irq_trigger(pIntAtoD[line - 1], - IRQ_LEVEL_TRIGGERED); + IRQ_LEVEL_TRIGGERED); #endif } } diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 5b633c8..55d4baa 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -62,8 +62,8 @@ static struct bus *get_pbus(device_t dev) while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) { if (pbus == pbus->dev->bus) { printk(BIOS_ALERT, "%s in endless loop looking for a " - "parent bus with pci_bus_ops for %s, breaking " - "out.\n", __func__, dev_path(dev)); + "parent bus with pci_bus_ops for %s, breaking " + "out.\n", __func__, dev_path(dev)); break; } pbus = pbus->dev->bus; @@ -129,42 +129,42 @@ u8 pci_mmio_read_config8(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read8(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); + dev->path.pci.devfn, where); }
u16 pci_mmio_read_config16(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read16(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); + dev->path.pci.devfn, where); }
u32 pci_mmio_read_config32(device_t dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return pci_ops_mmconf.read32(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); + dev->path.pci.devfn, where); }
void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); + where, val); }
void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); + where, val); }
void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); + where, val); }
#endif diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 1bdccf0..3d0905e 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -55,7 +55,7 @@ struct rom_header *pci_rom_probe(struct device *dev)
if (rom_header) { printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", - dev_path(dev), rom_header); + dev_path(dev), rom_header); } else { u32 rom_address;
@@ -71,12 +71,12 @@ struct rom_header *pci_rom_probe(struct device *dev) } else { /* Enable expansion ROM address decoding. */ pci_write_config32(dev, PCI_ROM_ADDRESS, - rom_address|PCI_ROM_ADDRESS_ENABLE); + rom_address|PCI_ROM_ADDRESS_ENABLE); }
#if CONFIG_ON_DEVICE_ROM_RUN printk(BIOS_DEBUG, "Option ROM address for %s = %lx\n", - dev_path(dev), (unsigned long)rom_address); + dev_path(dev), (unsigned long)rom_address); rom_header = (struct rom_header *)rom_address; #else printk(BIOS_DEBUG, "Option ROM execution disabled " @@ -86,37 +86,37 @@ struct rom_header *pci_rom_probe(struct device *dev) }
printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, " - "INIT size 0x%04x, data ptr 0x%04x\n", - le32_to_cpu(rom_header->signature), - rom_header->size * 512, le32_to_cpu(rom_header->data)); + "INIT size 0x%04x, data ptr 0x%04x\n", + le32_to_cpu(rom_header->signature), + rom_header->size * 512, le32_to_cpu(rom_header->data));
if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { printk(BIOS_ERR, "Incorrect expansion ROM header " - "signature %04x\n", le32_to_cpu(rom_header->signature)); + "signature %04x\n", le32_to_cpu(rom_header->signature)); return NULL; }
rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n", - rom_data->vendor, rom_data->device); + rom_data->vendor, rom_data->device); /* If the device id is mapped, a mismatch is expected */ if ((dev->vendor != rom_data->vendor || dev->device != rom_data->device) && (vendev == mapped_vendev)) { printk(BIOS_ERR, "ID mismatch: vendor ID %04x, " - "device ID %04x\n", rom_data->vendor, rom_data->device); + "device ID %04x\n", rom_data->vendor, rom_data->device); return NULL; }
printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, " - "Code Type %02x\n", rom_data->class_hi, rom_data->class_lo, - rom_data->type); + "Code Type %02x\n", rom_data->class_hi, rom_data->class_lo, + rom_data->type);
if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { printk(BIOS_DEBUG, "Class Code mismatch ROM %08x, dev %08x\n", - (rom_data->class_hi << 8) | rom_data->class_lo, - dev->class); + (rom_data->class_hi << 8) | rom_data->class_lo, + dev->class); // return NULL; }
@@ -135,7 +135,7 @@ struct rom_header *pci_rom_load(struct device *dev, do { /* Get next image. */ rom_header = (struct rom_header *)((void *) rom_header - + image_size); + + image_size);
rom_data = (struct pci_data *)((void *) rom_header + le32_to_cpu(rom_header->data)); @@ -160,16 +160,16 @@ struct rom_header *pci_rom_load(struct device *dev, #endif if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); + "0x%x, 0x%x bytes\n", rom_header, + PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, - rom_size); + rom_size); } return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); }
printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " - "bytes\n", rom_header, pci_ram_image_start, rom_size); + "bytes\n", rom_header, pci_ram_image_start, rom_size);
memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 87aea67..2c0d7ed 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -58,7 +58,7 @@ static int pciexp_retrain_link(device_t dev, unsigned cap) * enabled the link must be retrained. */ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, - device_t endp, unsigned endp_cap) + device_t endp, unsigned endp_cap) { u16 root_scc, endp_scc, lnkctl;
@@ -97,8 +97,8 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, * the highest latency value. */ static int pciexp_aspm_latency(device_t root, unsigned root_cap, - device_t endp, unsigned endp_cap, - enum aspm_type type) + device_t endp, unsigned endp_cap, + enum aspm_type type) { int root_lat = 0, endp_lat = 0; u32 root_lnkcap, endp_lnkcap; @@ -154,14 +154,14 @@ static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap, /* Enable L0s if it is within endpoint acceptable limit */ ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6; exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, - PCIE_ASPM_L0S); + PCIE_ASPM_L0S); if (exit_latency >= 0 && exit_latency <= ok_latency) apmc |= PCIE_ASPM_L0S;
/* Enable L1 if it is within endpoint acceptable limit */ ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9; exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap, - PCIE_ASPM_L1); + PCIE_ASPM_L1); if (exit_latency >= 0 && exit_latency <= ok_latency) apmc |= PCIE_ASPM_L1;
@@ -214,7 +214,7 @@ static void pciexp_tune_dev(device_t dev) }
unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max) + unsigned int max_devfn, unsigned int max) { device_t child;
@@ -242,11 +242,11 @@ static struct pci_operations pciexp_bus_ops_pci = {
struct device_operations default_pciexp_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pciexp_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &pciexp_bus_ops_pci, + .init = 0, + .scan_bus = pciexp_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pciexp_bus_ops_pci, }; diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index a20c3bf..4c54d3d 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -128,7 +128,7 @@ unsigned int pcix_scan_bridge(device_t dev, unsigned int max)
/* Print the PCI-X bus speed. */ printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, - pcix_speed(sstatus)); + pcix_speed(sstatus));
return max; } @@ -140,11 +140,11 @@ static struct pci_operations pcix_bus_ops_pci = {
struct device_operations default_pcix_ops_bus = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pcix_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &pcix_bus_ops_pci, + .init = 0, + .scan_bus = pcix_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &pcix_bus_ops_pci, }; diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 987a253..0e9e6c2 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -122,8 +122,8 @@ static void pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, - resource_type(resource), resource->size); + "not assigned\n", dev_path(dev), resource->index, + resource_type(resource), resource->size); return; }
@@ -136,7 +136,7 @@ static void pnp_set_resource(device_t dev, struct resource *resource) pnp_set_irq(dev, resource->index, resource->base); } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; @@ -188,9 +188,9 @@ void pnp_alt_enable(device_t dev)
struct device_operations pnp_ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, + .enable = pnp_enable, };
/* PNP chip operations */ diff --git a/src/device/root_device.c b/src/device/root_device.c index 49fa711..a3436b9 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -99,11 +99,11 @@ unsigned int scan_static_bus(device_t bus, unsigned int max)
if (child->path.type == DEVICE_PATH_I2C) { printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), - child->bus->link_num); + dev_path(child->bus->dev), + child->bus->link_num); } printk(BIOS_DEBUG, "%s %s\n", dev_path(child), - child->enabled ? "enabled" : "disabled"); + child->enabled ? "enabled" : "disabled"); } }
@@ -158,9 +158,9 @@ static void root_dev_reset(struct bus *bus) */ struct device_operations default_dev_ops_root = { .read_resources = root_dev_read_resources, - .set_resources = root_dev_set_resources, + .set_resources = root_dev_set_resources, .enable_resources = root_dev_enable_resources, - .init = root_dev_init, - .scan_bus = root_dev_scan_bus, - .reset_bus = root_dev_reset, + .init = root_dev_init, + .scan_bus = root_dev_scan_bus, + .reset_bus = root_dev_reset, }; diff --git a/src/device/smbus_ops.c b/src/device/smbus_ops.c index bcef4cd..a80d228 100644 --- a/src/device/smbus_ops.c +++ b/src/device/smbus_ops.c @@ -35,7 +35,7 @@ struct bus *get_pbus_smbus(device_t dev) if (!pbus || !pbus->dev || !pbus->dev->ops || !pbus->dev->ops->ops_smbus_bus) { printk(BIOS_ALERT, "%s Cannot find SMBus bus operations", - dev_path(dev)); + dev_path(dev)); die(""); }
@@ -127,11 +127,11 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data) int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) { return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, - bytes, buffer); + bytes, buffer); }
int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer) { return ops_smbus_bus(get_pbus_smbus(dev))->block_write(dev, cmd, - bytes, buffer); + bytes, buffer); } diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h index 557ead7..b7c707c 100644 --- a/src/drivers/ati/ragexl/atyfb.h +++ b/src/drivers/ati/ragexl/atyfb.h @@ -46,7 +46,7 @@ struct pll_ct { u8 pll_ref_div; u8 pll_gen_cntl; u8 mclk_fb_div; - u8 mclk_fb_mult; /* 2 or 4 */ + u8 mclk_fb_mult; /* 2 or 4 */ u8 sclk_fb_div; u8 pll_vclk_cntl; u8 vclk_post_div; @@ -87,7 +87,7 @@ struct aty_cursor { int blink_rate; u32 offset; struct { - u16 x, y; + u16 x, y; } pos, hot, size; u32 color[2]; u8 bits[8][64]; @@ -204,7 +204,7 @@ struct fb_info_aty { */
static inline u32 aty_ld_le32(int regindex, - const struct fb_info_aty *info) + const struct fb_info_aty *info) { /* Hack for bloc 1, should be cleanly optimized by compiler */ if (regindex >= 0x400) @@ -218,7 +218,7 @@ static inline u32 aty_ld_le32(int regindex, }
static inline void aty_st_le32(int regindex, u32 val, - const struct fb_info_aty *info) + const struct fb_info_aty *info) { /* Hack for bloc 1, should be cleanly optimized by compiler */ if (regindex >= 0x400) @@ -232,7 +232,7 @@ static inline void aty_st_le32(int regindex, u32 val, }
static inline u16 aty_ld_le16(int regindex, - const struct fb_info_aty *info) + const struct fb_info_aty *info) { /* Hack for bloc 1, should be cleanly optimized by compiler */ if (regindex >= 0x400) @@ -246,7 +246,7 @@ static inline u16 aty_ld_le16(int regindex, }
static inline void aty_st_le16(int regindex, u16 val, - const struct fb_info_aty *info) + const struct fb_info_aty *info) { /* Hack for bloc 1, should be cleanly optimized by compiler */ if (regindex >= 0x400) @@ -302,7 +302,7 @@ static inline u8 aty_ld_pll(int offset, const struct fb_info_aty *info) * CT family only. */ static inline void aty_st_pll(int offset, u8 val, - const struct fb_info_aty *info) + const struct fb_info_aty *info) { /* write addr byte */ aty_st_8(CLOCK_CNTL + 1, (offset << 2) | PLL_WR_EN, info); @@ -337,10 +337,10 @@ static struct aty_dac_ops aty_dac_ct; /* Integrated */ #if 0 struct aty_pll_ops { int (*var_to_pll)(const struct fb_info_aty *info, u32 vclk_per, u8 bpp, - union aty_pll *pll); + union aty_pll *pll); #if 0 u32 (*pll_to_var)(const struct fb_info_aty *info, - const union aty_pll *pll); + const union aty_pll *pll); void (*set_pll)(const struct fb_info_aty *info, const union aty_pll *pll); #endif }; diff --git a/src/drivers/ati/ragexl/fb.h b/src/drivers/ati/ragexl/fb.h index 48d0f01..8a41e97 100644 --- a/src/drivers/ati/ragexl/fb.h +++ b/src/drivers/ati/ragexl/fb.h @@ -27,12 +27,12 @@ #define FBIOPUT_CON2FBMAP 0x4610 #define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */ #define FBIOGET_VBLANK _IOR('F', 0x12, struct fb_vblank) -#define FBIO_ALLOC 0x4613 -#define FBIO_FREE 0x4614 -#define FBIOGET_GLYPH 0x4615 -#define FBIOGET_HWCINFO 0x4616 -#define FBIOPUT_MODEINFO 0x4617 -#define FBIOGET_DISPINFO 0x4618 +#define FBIO_ALLOC 0x4613 +#define FBIO_FREE 0x4614 +#define FBIOGET_GLYPH 0x4615 +#define FBIOGET_HWCINFO 0x4616 +#define FBIOPUT_MODEINFO 0x4617 +#define FBIOGET_DISPINFO 0x4618
#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ @@ -45,7 +45,7 @@ #define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */ #define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */ #define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */ -#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */ +#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */ #define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */ @@ -60,9 +60,9 @@
#define FB_ACCEL_NONE 0 /* no hardware accelerator */ #define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */ -#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ +#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */ #define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */ -#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ +#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */ #define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */ #define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */ #define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */ @@ -85,7 +85,7 @@ #define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */ #define FB_ACCEL_SUN_TCX 25 /* Sun tcx */ #define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */ -#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ +#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */ #define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */ #define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */ #define FB_ACCEL_CT_6555x 30 /* C&T 6555x */ @@ -94,21 +94,21 @@ #define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */ #define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */ #define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */ -#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ +#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */ #define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */ #define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */ #define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */ #define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
-#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ -#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ -#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ -#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ -#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ -#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ -#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ -#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ -#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */ +#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */ +#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */ +#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */ +#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */ +#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */ +#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */ +#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */ +#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */ +#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
#if 0
@@ -122,8 +122,8 @@ struct fb_fix_screeninfo { u32 visual; /* see FB_VISUAL_* */ u16 xpanstep; /* zero if no hardware panning */ u16 ypanstep; /* zero if no hardware panning */ - u16 ywrapstep; /* zero if no hardware ywrap */ - u32 line_length; /* length of a line in bytes */ + u16 ywrapstep; /* zero if no hardware ywrap */ + u32 line_length; /* length of a line in bytes */ unsigned long mmio_start; /* Start of Memory Mapped I/O */ /* (physical address) */ u32 mmio_len; /* Length of Memory Mapped I/O */ @@ -146,7 +146,7 @@ struct fb_bitfield { /* right */ };
-#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */ +#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/ #define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */ @@ -162,8 +162,8 @@ struct fb_bitfield { #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ #define FB_SYNC_EXT 4 /* external sync */ -#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ -#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ +#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ +#define FB_SYNC_BROADCAST 16 /* broadcast video timings */ /* vtotal = 144d/288n/576i => PAL */ /* vtotal = 121d/242n/484i => NTSC */ #define FB_SYNC_ON_GREEN 32 /* sync on green */ @@ -173,7 +173,7 @@ struct fb_bitfield { #define FB_VMODE_DOUBLE 2 /* double scan */ #define FB_VMODE_MASK 255
-#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
@@ -198,7 +198,7 @@ struct fb_var_screeninfo { u32 activate; /* see FB_ACTIVATE_* */
u32 height; /* height of picture in mm */ - u32 width; /* width of picture in mm */ + u32 width; /* width of picture in mm */
u32 accel_flags; /* acceleration flags (hints) */
@@ -230,10 +230,10 @@ struct fb_con2fbmap { };
/* VESA Blanking Levels */ -#define VESA_NO_BLANKING 0 -#define VESA_VSYNC_SUSPEND 1 -#define VESA_HSYNC_SUSPEND 2 -#define VESA_POWERDOWN 3 +#define VESA_NO_BLANKING 0 +#define VESA_VSYNC_SUSPEND 1 +#define VESA_HSYNC_SUSPEND 2 +#define VESA_POWERDOWN 3
struct fb_monspecs { u32 hfmin; /* hfreq lower limit (Hz) */ @@ -272,14 +272,14 @@ struct fb_vblank {
/* - * Hardware Cursor + * Hardware Cursor */
-#define FBIOGET_FCURSORINFO 0x4607 -#define FBIOGET_VCURSORINFO 0x4608 -#define FBIOPUT_VCURSORINFO 0x4609 -#define FBIOGET_CURSORSTATE 0x460A -#define FBIOPUT_CURSORSTATE 0x460B +#define FBIOGET_FCURSORINFO 0x4607 +#define FBIOGET_VCURSORINFO 0x4608 +#define FBIOPUT_VCURSORINFO 0x4609 +#define FBIOGET_CURSORSTATE 0x460A +#define FBIOPUT_CURSORSTATE 0x460B
struct fb_fix_cursorinfo { @@ -296,7 +296,7 @@ struct fb_var_cursorinfo { u16 height; u16 xspot; u16 yspot; - u8 data[1]; /* field with [height][width] */ + u8 data[1]; /* field with [height][width] */ };
struct fb_cursorstate { @@ -307,36 +307,36 @@ struct fb_cursorstate {
struct fb_info { - char modename[40]; /* default video mode */ + char modename[40]; /* default video mode */ // kdev_t node; int flags; - int open; /* Has this been open already ? */ - struct fb_var_screeninfo var; /* Current var */ + int open; /* Has this been open already ? */ + struct fb_var_screeninfo var; /* Current var */ #if 0 - struct fb_fix_screeninfo fix; /* Current fix */ + struct fb_fix_screeninfo fix; /* Current fix */ #endif - struct fb_monspecs monspecs; /* Current Monitor specs */ - struct fb_cmap cmap; /* Current cmap */ + struct fb_monspecs monspecs; /* Current Monitor specs */ + struct fb_cmap cmap; /* Current cmap */ // struct fb_ops *fbops; - char *screen_base; /* Virtual address */ - struct display *disp; /* initial display variable */ -// struct vc_data *display_fg; /* Console visible on this display */ - char fontname[40]; /* default font name */ + char *screen_base; /* Virtual address */ + struct display *disp; /* initial display variable */ +// struct vc_data *display_fg; /* Console visible on this display */ + char fontname[40]; /* default font name */ #if 0 - devfs_handle_t devfs_handle; /* Devfs handle for new name */ - devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ - int (*changevar)(int); /* tell console var has changed */ + devfs_handle_t devfs_handle; /* Devfs handle for new name */ + devfs_handle_t devfs_lhandle; /* Devfs handle for compat. symlink */ + int (*changevar)(int); /* tell console var has changed */ int (*switch_con)(int, struct fb_info*); - /* tell fb to switch consoles */ + /* tell fb to switch consoles */ int (*updatevar)(int, struct fb_info*); - /* tell fb to update the vars */ + /* tell fb to update the vars */ void (*blank)(int, struct fb_info*); /* tell fb to (un)blank the screen */ - /* arg = 0: unblank */ - /* arg > 0: VESA level (arg-1) */ + /* arg = 0: unblank */ + /* arg > 0: VESA level (arg-1) */ #endif - void *pseudo_palette; /* Fake palette of 16 colors and - the cursor's color for non - palette mode */ + void *pseudo_palette; /* Fake palette of 16 colors and + the cursor's color for non + palette mode */ /* From here on everything is device dependent */ void *par; }; diff --git a/src/drivers/ati/ragexl/fbcon.h b/src/drivers/ati/ragexl/fbcon.h index d6f122c..6e57ca1 100644 --- a/src/drivers/ati/ragexl/fbcon.h +++ b/src/drivers/ati/ragexl/fbcon.h @@ -14,39 +14,39 @@ struct display { /* Filled in by the frame buffer device */ struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ - /* are updated by fbcon.c */ - struct fb_cmap cmap; /* colormap */ - char *screen_base; /* pointer to top of virtual screen */ - /* (virtual address) */ + /* are updated by fbcon.c */ + struct fb_cmap cmap; /* colormap */ + char *screen_base; /* pointer to top of virtual screen */ + /* (virtual address) */ int visual; - int type; /* see FB_TYPE_* */ - int type_aux; /* Interleave for interleaved Planes */ - u16 ypanstep; /* zero if no hardware ypan */ - u16 ywrapstep; /* zero if no hardware ywrap */ - u32 line_length; /* length of a line in bytes */ - u16 can_soft_blank; /* zero if no hardware blanking */ - u16 inverse; /* != 0 text black on white as default */ + int type; /* see FB_TYPE_* */ + int type_aux; /* Interleave for interleaved Planes */ + u16 ypanstep; /* zero if no hardware ypan */ + u16 ywrapstep; /* zero if no hardware ywrap */ + u32 line_length; /* length of a line in bytes */ + u16 can_soft_blank; /* zero if no hardware blanking */ + u16 inverse; /* != 0 text black on white as default */
/* Filled in by the low-level console driver */
- struct vc_data *conp; /* pointer to console data */ - int vrows; /* number of virtual rows */ - unsigned short cursor_x; /* current cursor position */ + struct vc_data *conp; /* pointer to console data */ + int vrows; /* number of virtual rows */ + unsigned short cursor_x; /* current cursor position */ unsigned short cursor_y; - int fgcol; /* text colors */ + int fgcol; /* text colors */ int bgcol; - u32 next_line; /* offset to one line below */ - u32 next_plane; /* offset to next plane */ - u8 *fontdata; /* Font associated to this display */ + u32 next_line; /* offset to one line below */ + u32 next_plane; /* offset to next plane */ + u8 *fontdata; /* Font associated to this display */ unsigned short _fontheightlog; unsigned short _fontwidthlog; unsigned short _fontheight; unsigned short _fontwidth; - int userfont; /* != 0 if fontdata kmalloc()ed */ - u16 scrollmode; /* Scroll Method */ - short yscroll; /* Hardware scrolling */ + int userfont; /* != 0 if fontdata kmalloc()ed */ + u16 scrollmode; /* Scroll Method */ + short yscroll; /* Hardware scrolling */ unsigned char fgshift, bgshift; - unsigned short charmask; /* 0xff or 0x1ff */ + unsigned short charmask; /* 0xff or 0x1ff */ };
@@ -80,9 +80,9 @@ struct display { */
/* Color */ -#define attr_fgcol(p,s) \ +#define attr_fgcol(p,s) \ (((s) >> ((p)->fgshift)) & 0x0f) -#define attr_bgcol(p,s) \ +#define attr_bgcol(p,s) \ (((s) >> ((p)->bgshift)) & 0x0f) #define attr_bgcol_ec(p,conp) \ ((conp) ? (((conp)->vc_video_erase_char >> ((p)->bgshift)) & 0x0f) : 0) diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h index 3acbef4..ad48c21 100644 --- a/src/drivers/ati/ragexl/mach64.h +++ b/src/drivers/ati/ragexl/mach64.h @@ -858,8 +858,8 @@ #define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */
#define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \ - (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ - (id)==GO_CHIP_ID || (id)==GL_CHIP_ID) + (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \ + (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
#define GT_CHIP_ID 0x4754 /* RAGE (GT) */ #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */ diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c index 9b45f2a..8f25abf 100644 --- a/src/drivers/ati/ragexl/mach64_ct.c +++ b/src/drivers/ati/ragexl/mach64_ct.c @@ -11,12 +11,12 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per, struct pll_ct *pll); static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, - struct pll_ct *pll); + struct pll_ct *pll); static int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - u8 bpp, union aty_pll *pll); + u8 bpp, union aty_pll *pll); #if PLL_CRTC_DECODE==1 static u32 aty_pll_ct_to_var(const struct fb_info_aty *info, - const union aty_pll *pll); + const union aty_pll *pll); #endif
/* ------------------------------------------------------------------------- */ @@ -25,7 +25,7 @@ static u32 aty_pll_ct_to_var(const struct fb_info_aty *info, * PLL programming (Mach64 CT family) */ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, - struct pll_ct *pll) + struct pll_ct *pll) { u32 dsp_xclks_per_row, dsp_loop_latency, dsp_precision, dsp_off, dsp_on; u32 xclks_per_row, fifo_off, fifo_on, y, fifo_size; @@ -111,8 +111,8 @@ static int aty_dsp_gt(const struct fb_info_aty *info, u32 bpp, dsp_off = fifo_off>>dsp_precision;
pll->dsp_config = (dsp_xclks_per_row & 0x3fff) | - ((dsp_loop_latency & 0xf)<<16) | - ((dsp_precision & 7)<<20); + ((dsp_loop_latency & 0xf)<<16) | + ((dsp_precision & 7)<<20); pll->dsp_on_off = (dsp_off & 0x7ff) | ((dsp_on & 0x7ff)<<16); return 0; } @@ -274,7 +274,7 @@ static void aty_calc_pll_ct(const struct fb_info_aty *info, struct pll_ct *pll) }
int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, - u8 bpp, union aty_pll *pll) + u8 bpp, union aty_pll *pll) { int err; if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct))) @@ -287,7 +287,7 @@ int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per, #if CONFIG_CONSOLE_BTEXT #if PLL_CRTC_DECODE==1 u32 aty_pll_ct_to_var(const struct fb_info_aty *info, - const union aty_pll *pll) + const union aty_pll *pll) { u32 ref_clk_per = info->ref_clk_per; u8 pll_ref_div = pll->ct.pll_ref_div; diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 36a0619..727d4d9 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -4,9 +4,9 @@ * * Copyright (C) 2002 MontaVista Software Inc. * Author: MontaVista Software, Inc. - * stevel@mvista.com or source@mvista.com + * stevel@mvista.com or source@mvista.com * Copyright (C) 2004 Tyan Computer. - * Auther: Yinghai Lu yhlu@tyan.com + * Auther: Yinghai Lu yhlu@tyan.com * move to coreboot * This code is distributed without warranty under the GPL v2 (see COPYING) * */ @@ -54,8 +54,8 @@ struct aty_cmap_regs {
#include "mach64_ct.c"
-#define MPLL_GAIN 0xad -#define VPLL_GAIN 0xd5 +#define MPLL_GAIN 0xad +#define VPLL_GAIN 0xd5
#define HAS_VICTORIA 0
@@ -132,7 +132,7 @@ static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info) }
static inline void aty_st_lcd(u8 lcd_reg, u32 val, - struct fb_info_aty *info) + struct fb_info_aty *info) { aty_st_8(LCD_INDEX, lcd_reg, info); aty_st_le32(LCD_DATA, val, info); @@ -155,12 +155,12 @@ static void reset_sdram(struct fb_info_aty *info) temp |= 0x02; aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b temp |= 0x08; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 10b + aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 10b temp |= 0x0c; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 11b + aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 11b mdelay(5); temp &= 0xf3; - aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 00b + aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST = 00b temp &= 0xfd; aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST = 0b mdelay(5); @@ -236,7 +236,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) * isn't programmed until later. */ if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err; -// if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err; +// if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
aty_st_pll(LVDS_CNTL0, 0x00, info); @@ -395,24 +395,24 @@ static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
#if CONFIG_CONSOLE_BTEXT static void aty_set_crtc(const struct fb_info_aty *info, - const struct crtc *crtc); + const struct crtc *crtc); static int aty_var_to_crtc(const struct fb_info_aty *info, - const struct fb_var_screeninfo *var, - struct crtc *crtc); + const struct fb_var_screeninfo *var, + struct crtc *crtc); #if PLL_CRTC_DECODE==1 static int aty_crtc_to_var(const struct crtc *crtc, - struct fb_var_screeninfo *var); + struct fb_var_screeninfo *var); #endif
static void atyfb_set_par(const struct atyfb_par *par, - struct fb_info_aty *info); + struct fb_info_aty *info); static int atyfb_decode_var(const struct fb_var_screeninfo *var, - struct atyfb_par *par, - const struct fb_info_aty *info); + struct atyfb_par *par, + const struct fb_info_aty *info); #if PLL_CRTC_DECODE==1 static int atyfb_encode_var(struct fb_var_screeninfo *var, - const struct atyfb_par *par, - const struct fb_info_aty *info); + const struct atyfb_par *par, + const struct fb_info_aty *info); #endif
static void do_install_cmap(int con, struct fb_info_aty *info); @@ -422,7 +422,7 @@ static u32 default_vram = 0; #endif
unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7, - 8,12,10,14, 9,13,11,15 }; + 8,12,10,14, 9,13,11,15 }; #if 0 /* the default colour table, for VGA+ colour systems */ int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa, @@ -458,43 +458,43 @@ static struct { #if CONFIG_CONSOLE_BTEXT static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) { - int i, size; + int i, size; #if 0 - const int ragepro_tbl[] = { - 44, 50, 55, 66, 75, 80, 100 - }; + const int ragepro_tbl[] = { + 44, 50, 55, 66, 75, 80, 100 + }; #endif - const int ragexl_tbl[] = { - 50, 66, 75, 83, 90, 95, 100, 105, - 110, 115, 120, 125, 133, 143, 166 - }; - const int *refresh_tbl; + const int ragexl_tbl[] = { + 50, 66, 75, 83, 90, 95, 100, 105, + 110, 115, 120, 125, 133, 143, 166 + }; + const int *refresh_tbl; #if 0 - if (IS_XL(id)) { + if (IS_XL(id)) { #endif - refresh_tbl = ragexl_tbl; - size = sizeof(ragexl_tbl)/sizeof(int); + refresh_tbl = ragexl_tbl; + size = sizeof(ragexl_tbl)/sizeof(int); #if 0 - } else { - refresh_tbl = ragepro_tbl; - size = sizeof(ragepro_tbl)/sizeof(int); - } + } else { + refresh_tbl = ragepro_tbl; + size = sizeof(ragepro_tbl)/sizeof(int); + } #endif
- for (i=0; i < size; i++) { - if (xclk < refresh_tbl[i]) - break; - } + for (i=0; i < size; i++) { + if (xclk < refresh_tbl[i]) + break; + }
- info->mem_refresh_rate = i; + info->mem_refresh_rate = i; } #endif /*CONFIG_CONSOLE_BTEXT */ static void ati_ragexl_init(device_t dev) { - u32 chip_id; + u32 chip_id; int j; u16 type; - u8 rev; + u8 rev; const char *chipname = NULL; #if CONFIG_CONSOLE_BTEXT u32 i; @@ -508,9 +508,9 @@ static void ati_ragexl_init(device_t dev) int gtb_memsize, k; #endif
- struct fb_var_screeninfo var; + struct fb_var_screeninfo var; #if 0 - struct display *disp; + struct display *disp; #endif
#if 0 @@ -519,10 +519,10 @@ static void ati_ragexl_init(device_t dev)
#endif /*CONFIG_CONSOLE_BTEXT==1 */
- struct fb_info_aty *info; - struct fb_info_aty info_t; - struct resource *res; - info = &info_t; + struct fb_info_aty *info; + struct fb_info_aty info_t; + struct resource *res; + info = &info_t;
#define USE_AUX_REG 1
@@ -537,19 +537,19 @@ static void ati_ragexl_init(device_t dev) #endif /* CONFIG_CONSOLE_BTEXT */
#if USE_AUX_REG==0 - info->ati_regbase = res->base+0x7ff000+0xc00; + info->ati_regbase = res->base+0x7ff000+0xc00; #else /* Fix this to look for the correct index. */ //if (dev->resource_list && dev->resource_list->next) - res = dev->resource_list->next->next; - if(res->flags & IORESOURCE_MEM) { - info->ati_regbase = res->base+0x400; //using auxiliary register - } + res = dev->resource_list->next->next; + if(res->flags & IORESOURCE_MEM) { + info->ati_regbase = res->base+0x400; //using auxiliary register + }
#endif
#if CONFIG_CONSOLE_BTEXT - info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0); + info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0); #endif
#if 0 @@ -560,15 +560,15 @@ static void ati_ragexl_init(device_t dev) type = chip_id & CFG_CHIP_TYPE; rev = (chip_id & CFG_CHIP_REV)>>24; for (j = 0; j < ARRAY_SIZE(aty_chips); j++) - if (type == aty_chips[j].chip_type && - (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) { - chipname = aty_chips[j].name; - pll = aty_chips[j].pll; - mclk = aty_chips[j].mclk; - xclk = aty_chips[j].xclk; - info->features = aty_chips[j].features; - goto found; - } + if (type == aty_chips[j].chip_type && + (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) { + chipname = aty_chips[j].name; + pll = aty_chips[j].pll; + mclk = aty_chips[j].mclk; + xclk = aty_chips[j].xclk; + info->features = aty_chips[j].features; + goto found; + } printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev); return ;
@@ -576,22 +576,22 @@ found: printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev); #if 0 if (M64_HAS(INTEGRATED)) { - /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ - if (mclk == 67 && info->ram_type < SDRAM) - mclk = 63; + /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */ + if (mclk == 67 && info->ram_type < SDRAM) + mclk = 63; } #endif #if CONFIG_CONSOLE_BTEXT - aty_calc_mem_refresh(info, type, xclk); + aty_calc_mem_refresh(info, type, xclk); #endif /* CONFIG_CONSOLE_BTEXT */
info->pll_per = 1000000/pll; info->mclk_per = 1000000/mclk; info->xclk_per = 1000000/xclk;
-// info->dac_ops = &aty_dac_ct; -// info->pll_ops = &aty_pll_ct; - info->bus_type = PCI; +// info->dac_ops = &aty_dac_ct; +// info->pll_ops = &aty_pll_ct; + info->bus_type = PCI;
atyfb_xl_init(info); @@ -600,21 +600,21 @@ found:
info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
- info->ref_clk_per = 1000000000000ULL/14318180; + info->ref_clk_per = 1000000000000ULL/14318180; xtal = "14.31818"; #if 0 if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) { - int diff1, diff2; - diff1 = 510*14/pll_ref_div-pll; - diff2 = 510*29/pll_ref_div-pll; - if (diff1 < 0) - diff1 = -diff1; - if (diff2 < 0) - diff2 = -diff2; - if (diff2 < diff1) { - info->ref_clk_per = 1000000000000ULL/29498928; - xtal = "29.498928"; - } + int diff1, diff2; + diff1 = 510*14/pll_ref_div-pll; + diff2 = 510*29/pll_ref_div-pll; + if (diff1 < 0) + diff1 = -diff1; + if (diff2 < 0) + diff2 = -diff2; + if (diff2 < diff1) { + info->ref_clk_per = 1000000000000ULL/29498928; + xtal = "29.498928"; + } } #endif
@@ -623,75 +623,75 @@ found: gtb_memsize = M64_HAS(GTB_DSP); if (gtb_memsize) // We have #endif - switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */ - case MEM_SIZE_512K: - info->total_vram = 0x80000; - break; - case MEM_SIZE_1M: - info->total_vram = 0x100000; - break; - case MEM_SIZE_2M_GTB: - info->total_vram = 0x200000; - break; - case MEM_SIZE_4M_GTB: - info->total_vram = 0x400000; - break; - case MEM_SIZE_6M_GTB: - info->total_vram = 0x600000; - break; - case MEM_SIZE_8M_GTB: - info->total_vram = 0x800000; - break; - default: - info->total_vram = 0x80000; - } + switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */ + case MEM_SIZE_512K: + info->total_vram = 0x80000; + break; + case MEM_SIZE_1M: + info->total_vram = 0x100000; + break; + case MEM_SIZE_2M_GTB: + info->total_vram = 0x200000; + break; + case MEM_SIZE_4M_GTB: + info->total_vram = 0x400000; + break; + case MEM_SIZE_6M_GTB: + info->total_vram = 0x600000; + break; + case MEM_SIZE_8M_GTB: + info->total_vram = 0x800000; + break; + default: + info->total_vram = 0x80000; + } #if 0 else - switch (i & MEM_SIZE_ALIAS) { - case MEM_SIZE_512K: - info->total_vram = 0x80000; - break; - case MEM_SIZE_1M: - info->total_vram = 0x100000; - break; - case MEM_SIZE_2M: - info->total_vram = 0x200000; - break; - case MEM_SIZE_4M: - info->total_vram = 0x400000; - break; - case MEM_SIZE_6M: - info->total_vram = 0x600000; - break; - case MEM_SIZE_8M: - info->total_vram = 0x800000; - break; - default: - info->total_vram = 0x80000; + switch (i & MEM_SIZE_ALIAS) { + case MEM_SIZE_512K: + info->total_vram = 0x80000; + break; + case MEM_SIZE_1M: + info->total_vram = 0x100000; + break; + case MEM_SIZE_2M: + info->total_vram = 0x200000; + break; + case MEM_SIZE_4M: + info->total_vram = 0x400000; + break; + case MEM_SIZE_6M: + info->total_vram = 0x600000; + break; + case MEM_SIZE_8M: + info->total_vram = 0x800000; + break; + default: + info->total_vram = 0x80000; } #endif
if (M64_HAS(MAGIC_VRAM_SIZE)) { - if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000) - info->total_vram += 0x400000; + if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000) + info->total_vram += 0x400000; } #if 0 if (default_vram) { - info->total_vram = default_vram*1024; - i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS); - if (info->total_vram <= 0x80000) - i |= MEM_SIZE_512K; - else if (info->total_vram <= 0x100000) - i |= MEM_SIZE_1M; - else if (info->total_vram <= 0x200000) - i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M; - else if (info->total_vram <= 0x400000) - i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M; - else if (info->total_vram <= 0x600000) - i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M; - else - i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M; - aty_st_le32(MEM_CNTL, i, info); + info->total_vram = default_vram*1024; + i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS); + if (info->total_vram <= 0x80000) + i |= MEM_SIZE_512K; + else if (info->total_vram <= 0x100000) + i |= MEM_SIZE_1M; + else if (info->total_vram <= 0x200000) + i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M; + else if (info->total_vram <= 0x400000) + i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M; + else if (info->total_vram <= 0x600000) + i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M; + else + i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M; + aty_st_le32(MEM_CNTL, i, info); } #endif
@@ -715,76 +715,76 @@ found:
#if 0 if (noaccel) // We has noaccel in default - var.accel_flags &= ~FB_ACCELF_TEXT; + var.accel_flags &= ~FB_ACCELF_TEXT; else - var.accel_flags |= FB_ACCELF_TEXT; + var.accel_flags |= FB_ACCELF_TEXT; #endif
if (var.yres == var.yres_virtual) { - u32 vram = info->total_vram ; - var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual; - if (var.yres_virtual < var.yres) - var.yres_virtual = var.yres; + u32 vram = info->total_vram ; + var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual; + if (var.yres_virtual < var.yres) + var.yres_virtual = var.yres; }
if (atyfb_decode_var(&var, &info->default_par, info)) { #if 0 - printk(BIOS_DEBUG, "atyfb: can't set default video mode\n"); + printk(BIOS_DEBUG, "atyfb: can't set default video mode\n"); #endif - return ; + return ; } #if 0 for (j = 0; j < 16; j++) { - k = color_table[j]; - info->palette[j].red = default_red[k]; - info->palette[j].green = default_grn[k]; - info->palette[j].blue = default_blu[k]; + k = color_table[j]; + info->palette[j].red = default_red[k]; + info->palette[j].green = default_grn[k]; + info->palette[j].blue = default_blu[k]; } #endif
#if 0 if (curblink && M64_HAS(INTEGRATED)) { - info->cursor = aty_init_cursor(info); - if (info->cursor) { - info->dispsw.cursor = atyfb_cursor; - info->dispsw.set_font = atyfb_set_font; - } + info->cursor = aty_init_cursor(info); + if (info->cursor) { + info->dispsw.cursor = atyfb_cursor; + info->dispsw.set_font = atyfb_set_font; + } } #endif
#if PLL_CRTC_DECODE==1 atyfb_set_var(&var, -1, &info->fb_info); #else - atyfb_set_par(&info->default_par, info); -// do_install_cmap(-1, &info->fb_info); + atyfb_set_par(&info->default_par, info); +// do_install_cmap(-1, &info->fb_info); do_install_cmap(-1, info); #endif
#if PLL_CRTC_DECODE==1
printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer, - (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->current_par.crtc.bpp, - info->current_par.crtc.vxres*info->default_par.crtc.bpp/8 - ); + (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, + ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, + info->current_par.crtc.bpp, + info->current_par.crtc.vxres*info->default_par.crtc.bpp/8 + ); btext_setup_display( - (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->current_par.crtc.bpp, - info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer); + (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, + ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1, + info->current_par.crtc.bpp, + info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer); #else printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer, - (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->default_par.crtc.bpp, - info->default_par.crtc.vxres*info->default_par.crtc.bpp/8 - ); + (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, + ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, + info->default_par.crtc.bpp, + info->default_par.crtc.vxres*info->default_par.crtc.bpp/8 + ); btext_setup_display( - (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, - ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, - info->default_par.crtc.bpp, - info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer); + (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8, + ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1, + info->default_par.crtc.bpp, + info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer); #endif
btext_clearscreen(); @@ -806,41 +806,41 @@ found: #if CONFIG_CONSOLE_BTEXT
static int atyfb_decode_var(const struct fb_var_screeninfo *var, - struct atyfb_par *par, - const struct fb_info_aty *info) + struct atyfb_par *par, + const struct fb_info_aty *info) { int err;
if ((err = aty_var_to_crtc(info, var, &par->crtc)) || - (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp, - &par->pll))) - return err; + (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp, + &par->pll))) + return err;
#if 0 if (var->accel_flags & FB_ACCELF_TEXT) - par->accel_flags = FB_ACCELF_TEXT; + par->accel_flags = FB_ACCELF_TEXT; else #endif - par->accel_flags = 0; + par->accel_flags = 0;
#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */ if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info)) - return -EINVAL; + return -EINVAL; #endif
return 0; } #if PLL_CRTC_DECODE==1 static int atyfb_encode_var(struct fb_var_screeninfo *var, - const struct atyfb_par *par, - const struct fb_info_aty *info) + const struct atyfb_par *par, + const struct fb_info_aty *info) { int err;
memset(var, 0, sizeof(struct fb_var_screeninfo));
if ((err = aty_crtc_to_var(&par->crtc, var))) - return err; + return err; var->pixclock = aty_pll_ct_to_var(info, &par->pll);
var->height = -1; @@ -851,7 +851,7 @@ static int atyfb_encode_var(struct fb_var_screeninfo *var, } #endif static void aty_set_crtc(const struct fb_info_aty *info, - const struct crtc *crtc) + const struct crtc *crtc) { aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info); aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info); @@ -863,8 +863,8 @@ static void aty_set_crtc(const struct fb_info_aty *info, }
static int aty_var_to_crtc(const struct fb_info_aty *info, - const struct fb_var_screeninfo *var, - struct crtc *crtc) + const struct fb_var_screeninfo *var, + struct crtc *crtc) { u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; u32 left, right, upper, lower, hslen, vslen, sync, vmode; @@ -894,73 +894,73 @@ static int aty_var_to_crtc(const struct fb_info_aty *info, xoffset = (xoffset+7) & ~7; vxres = (vxres+7) & ~7; if (vxres < xres+xoffset) - vxres = xres+xoffset; + vxres = xres+xoffset; h_disp = xres/8-1; if (h_disp > 0xff) - FAIL("h_disp too large"); + FAIL("h_disp too large"); h_sync_strt = h_disp+(right/8); if (h_sync_strt > 0x1ff) - FAIL("h_sync_start too large"); + FAIL("h_sync_start too large"); h_sync_dly = right & 7; h_sync_wid = (hslen+7)/8; if (h_sync_wid > 0x1f) - FAIL("h_sync_wid too large"); + FAIL("h_sync_wid too large"); h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8; if (h_total > 0x1ff) FAIL("h_total too large"); h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
if (vyres < yres+yoffset) - vyres = yres+yoffset; + vyres = yres+yoffset; v_disp = yres-1; if (v_disp > 0x7ff) - FAIL("v_disp too large"); + FAIL("v_disp too large"); v_sync_strt = v_disp+lower; if (v_sync_strt > 0x7ff) - FAIL("v_sync_strt too large"); + FAIL("v_sync_strt too large"); v_sync_wid = vslen; if (v_sync_wid > 0x1f) - FAIL("v_sync_wid too large"); + FAIL("v_sync_wid too large"); v_total = v_sync_strt+v_sync_wid+upper; if (v_total > 0x7ff) - FAIL("v_total too large"); + FAIL("v_total too large"); v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
if (bpp <= 8) { - bpp = 8; - pix_width = CRTC_PIX_WIDTH_8BPP; - dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; + bpp = 8; + pix_width = CRTC_PIX_WIDTH_8BPP; + dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; + dp_chain_mask = 0x8080; } #if SUPPORT_8_BPP_ABOVE==1 else if (bpp <= 16) { - bpp = 16; - pix_width = CRTC_PIX_WIDTH_15BPP; - dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP | - BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x4210; + bpp = 16; + pix_width = CRTC_PIX_WIDTH_15BPP; + dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP | + BYTE_ORDER_LSB_TO_MSB; + dp_chain_mask = 0x4210; } else if (bpp <= 24 && M64_HAS(INTEGRATED)) { - bpp = 24; - pix_width = CRTC_PIX_WIDTH_24BPP; - dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; + bpp = 24; + pix_width = CRTC_PIX_WIDTH_24BPP; + dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB; + dp_chain_mask = 0x8080; } else if (bpp <= 32) { - bpp = 32; - pix_width = CRTC_PIX_WIDTH_32BPP; - dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | - BYTE_ORDER_LSB_TO_MSB; - dp_chain_mask = 0x8080; + bpp = 32; + pix_width = CRTC_PIX_WIDTH_32BPP; + dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP | + BYTE_ORDER_LSB_TO_MSB; + dp_chain_mask = 0x8080; } #endif else - FAIL("invalid bpp"); + FAIL("invalid bpp");
if (vxres*vyres*bpp/8 > info->total_vram) - FAIL("not enough video RAM"); + FAIL("not enough video RAM"); if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) - FAIL("invalid vmode"); + FAIL("invalid vmode");
/* output */ crtc->vxres = vxres; @@ -970,16 +970,16 @@ else crtc->bpp = bpp; crtc->h_tot_disp = h_total | (h_disp<<16); crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) | - ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | - (h_sync_pol<<21); + ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | + (h_sync_pol<<21); crtc->v_tot_disp = v_total | (v_disp<<16); crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21); crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19); crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE; if (M64_HAS(MAGIC_FIFO)) { - /* Not VTB/GTB */ - /* FIXME: magic FIFO values */ - crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000; + /* Not VTB/GTB */ + /* FIXME: magic FIFO values */ + crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000; } crtc->dp_pix_width = dp_pix_width; crtc->dp_chain_mask = dp_chain_mask; @@ -988,7 +988,7 @@ else } #if PLL_CRTC_DECODE==1 static int aty_crtc_to_var(const struct crtc *crtc, - struct fb_var_screeninfo *var) + struct fb_var_screeninfo *var) { u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync; u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; @@ -999,7 +999,7 @@ static int aty_crtc_to_var(const struct crtc *crtc, h_total = crtc->h_tot_disp & 0x1ff; h_disp = (crtc->h_tot_disp>>16) & 0xff; h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | - ((crtc->h_sync_strt_wid>>4) & 0x100); + ((crtc->h_sync_strt_wid>>4) & 0x100); h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7; h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f; h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1; @@ -1021,82 +1021,82 @@ static int aty_crtc_to_var(const struct crtc *crtc, lower = v_sync_strt-v_disp; vslen = v_sync_wid; sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | - (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | - (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); + (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | + (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
switch (pix_width) { #if 0 - case CRTC_PIX_WIDTH_4BPP: - bpp = 4; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; + case CRTC_PIX_WIDTH_4BPP: + bpp = 4; + var->red.offset = 0; + var->red.length = 8; + var->green.offset = 0; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->transp.offset = 0; + var->transp.length = 0; + break; #endif - case CRTC_PIX_WIDTH_8BPP: - bpp = 8; - var->red.offset = 0; - var->red.length = 8; - var->green.offset = 0; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; + case CRTC_PIX_WIDTH_8BPP: + bpp = 8; + var->red.offset = 0; + var->red.length = 8; + var->green.offset = 0; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->transp.offset = 0; + var->transp.length = 0; + break; #if SUPPORT_8_BPP_ABOVE==1 - case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */ - bpp = 16; - var->red.offset = 10; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 5; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */ - bpp = 16; - var->red.offset = 11; - var->red.length = 5; - var->green.offset = 5; - var->green.length = 6; - var->blue.offset = 0; - var->blue.length = 5; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */ - bpp = 24; - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 0; - var->transp.length = 0; - break; - case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */ - bpp = 32; - var->red.offset = 16; - var->red.length = 8; - var->green.offset = 8; - var->green.length = 8; - var->blue.offset = 0; - var->blue.length = 8; - var->transp.offset = 24; - var->transp.length = 8; - break; + case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */ + bpp = 16; + var->red.offset = 10; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 5; + var->blue.offset = 0; + var->blue.length = 5; + var->transp.offset = 0; + var->transp.length = 0; + break; + case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */ + bpp = 16; + var->red.offset = 11; + var->red.length = 5; + var->green.offset = 5; + var->green.length = 6; + var->blue.offset = 0; + var->blue.length = 5; + var->transp.offset = 0; + var->transp.length = 0; + break; + case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */ + bpp = 24; + var->red.offset = 16; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->transp.offset = 0; + var->transp.length = 0; + break; + case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */ + bpp = 32; + var->red.offset = 16; + var->red.length = 8; + var->green.offset = 8; + var->green.length = 8; + var->blue.offset = 0; + var->blue.length = 8; + var->transp.offset = 24; + var->transp.length = 8; + break; #endif - default: - FAIL("Invalid pixel width"); + default: + FAIL("Invalid pixel width"); }
/* output */ @@ -1122,8 +1122,8 @@ static int aty_crtc_to_var(const struct crtc *crtc,
#if 0 static int encode_fix(struct fb_fix_screeninfo *fix, - const struct atyfb_par *par, - const struct fb_info_aty *info) + const struct atyfb_par *par, + const struct fb_info_aty *info) { memset(fix, 0, sizeof(struct fb_fix_screeninfo));
@@ -1137,27 +1137,27 @@ static int encode_fix(struct fb_fix_screeninfo *fix, * Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400 */ if (M64_HAS(GX)) { - fix->mmio_start = info->ati_regbase; - fix->mmio_len = 0x400; - fix->accel = FB_ACCEL_ATI_MACH64GX; + fix->mmio_start = info->ati_regbase; + fix->mmio_len = 0x400; + fix->accel = FB_ACCEL_ATI_MACH64GX; } else if (M64_HAS(CT)) { - fix->mmio_start = info->ati_regbase; - fix->mmio_len = 0x400; - fix->accel = FB_ACCEL_ATI_MACH64CT; + fix->mmio_start = info->ati_regbase; + fix->mmio_len = 0x400; + fix->accel = FB_ACCEL_ATI_MACH64CT; } else if (M64_HAS(VT)) { - fix->mmio_start = info->ati_regbase-0x400; - fix->mmio_len = 0x800; - fix->accel = FB_ACCEL_ATI_MACH64VT; + fix->mmio_start = info->ati_regbase-0x400; + fix->mmio_len = 0x800; + fix->accel = FB_ACCEL_ATI_MACH64VT; } else /* if (M64_HAS(GT)) */ { - fix->mmio_start = info->ati_regbase-0x400; - fix->mmio_len = 0x800; - fix->accel = FB_ACCEL_ATI_MACH64GT; + fix->mmio_start = info->ati_regbase-0x400; + fix->mmio_len = 0x800; + fix->accel = FB_ACCEL_ATI_MACH64GT; } fix->type = FB_TYPE_PACKED_PIXELS; fix->type_aux = 0; fix->line_length = par->crtc.vxres*par->crtc.bpp/8; fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR - : FB_VISUAL_DIRECTCOLOR; + : FB_VISUAL_DIRECTCOLOR; fix->ywrapstep = 0; fix->xpanstep = 8; fix->ypanstep = 1; @@ -1170,7 +1170,7 @@ static int encode_fix(struct fb_fix_screeninfo *fix, */ #if PLL_CRTC_DECODE==1 static int atyfb_set_var(struct fb_var_screeninfo *var, int con, - struct fb_info *fb) + struct fb_info *fb) { struct fb_info_aty *info = (struct fb_info_aty *)fb; struct atyfb_par par; @@ -1183,15 +1183,15 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
#if 0 if (con >= 0) - display = &fb_display[con]; + display = &fb_display[con]; else #endif #if 0 - display = fb->disp; /* used during initialization */ + display = fb->disp; /* used during initialization */ #endif
if ((err = atyfb_decode_var(var, &par, info))) - return err; + return err;
atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
@@ -1201,56 +1201,56 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) { #if 0 - oldxres = display->var.xres; - oldyres = display->var.yres; - oldvxres = display->var.xres_virtual; - oldvyres = display->var.yres_virtual; - oldbpp = display->var.bits_per_pixel; - oldaccel = display->var.accel_flags; - display->var = *var; - accel = var->accel_flags & FB_ACCELF_TEXT; - if (oldxres != var->xres || oldyres != var->yres || - oldvxres != var->xres_virtual || oldvyres != var->yres_virtual || - oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) { - struct fb_fix_screeninfo fix; - - encode_fix(&fix, &par, info); - display->screen_base = (char *)info->frame_buffer; - display->visual = fix.visual; - display->type = fix.type; - display->type_aux = fix.type_aux; - display->ypanstep = fix.ypanstep; - display->ywrapstep = fix.ywrapstep; - display->line_length = fix.line_length; - display->can_soft_blank = 1; - display->inverse = 0; + oldxres = display->var.xres; + oldyres = display->var.yres; + oldvxres = display->var.xres_virtual; + oldvyres = display->var.yres_virtual; + oldbpp = display->var.bits_per_pixel; + oldaccel = display->var.accel_flags; + display->var = *var; + accel = var->accel_flags & FB_ACCELF_TEXT; + if (oldxres != var->xres || oldyres != var->yres || + oldvxres != var->xres_virtual || oldvyres != var->yres_virtual || + oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) { + struct fb_fix_screeninfo fix; + + encode_fix(&fix, &par, info); + display->screen_base = (char *)info->frame_buffer; + display->visual = fix.visual; + display->type = fix.type; + display->type_aux = fix.type_aux; + display->ypanstep = fix.ypanstep; + display->ywrapstep = fix.ywrapstep; + display->line_length = fix.line_length; + display->can_soft_blank = 1; + display->inverse = 0; #if 0 - if (accel) - display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0; - else + if (accel) + display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0; + else #endif - display->scrollmode = SCROLL_YREDRAW; + display->scrollmode = SCROLL_YREDRAW; #if 0 - if (info->fb_info.changevar) - (*info->fb_info.changevar)(con); + if (info->fb_info.changevar) + (*info->fb_info.changevar)(con); #endif - } + } #endif -// if (!info->fb_info.display_fg || -// info->fb_info.display_fg->vc_num == con) { - atyfb_set_par(&par, info); +// if (!info->fb_info.display_fg || +// info->fb_info.display_fg->vc_num == con) { + atyfb_set_par(&par, info); #if 0 - atyfb_set_dispsw(display, info, par.crtc.bpp, accel); + atyfb_set_dispsw(display, info, par.crtc.bpp, accel); #endif -// } +// } #if 0 - if (oldbpp != var->bits_per_pixel) { - if ((err = fb_alloc_cmap(&display->cmap, 0, 0))) - return err; + if (oldbpp != var->bits_per_pixel) { + if ((err = fb_alloc_cmap(&display->cmap, 0, 0))) + return err; #endif - do_install_cmap(con, info); + do_install_cmap(con, info); #if 0 - } + } #endif }
@@ -1261,7 +1261,7 @@ static int atyfb_set_var(struct fb_var_screeninfo *var, int con, /* ------------------------------------------------------------------------- */
static void atyfb_set_par(const struct atyfb_par *par, - struct fb_info_aty *info) + struct fb_info_aty *info) { u32 i; int accelmode; @@ -1274,11 +1274,11 @@ static void atyfb_set_par(const struct atyfb_par *par, #endif
if (info->blitter_may_be_busy) - wait_for_idle(info); + wait_for_idle(info); tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info); aty_set_crtc(info, &par->crtc); aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info); - /* better call aty_StrobeClock ?? */ + /* better call aty_StrobeClock ?? */ aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
//info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode); @@ -1287,67 +1287,67 @@ static void atyfb_set_par(const struct atyfb_par *par,
if (!M64_HAS(INTEGRATED)) { - /* Don't forget MEM_CNTL */ - i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff; - switch (par->crtc.bpp) { - case 8: - i |= 0x02000000; - break; + /* Don't forget MEM_CNTL */ + i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff; + switch (par->crtc.bpp) { + case 8: + i |= 0x02000000; + break; #if SUPPORT_8_BPP_ABOVE==1 - case 16: - i |= 0x03000000; - break; - case 32: - i |= 0x06000000; - break; + case 16: + i |= 0x03000000; + break; + case 32: + i |= 0x06000000; + break; #endif - } - aty_st_le32(MEM_CNTL, i, info); + } + aty_st_le32(MEM_CNTL, i, info); } else { - i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff; - if (!M64_HAS(MAGIC_POSTDIV)) - i |= info->mem_refresh_rate << 20; - switch (par->crtc.bpp) { - case 8: + i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff; + if (!M64_HAS(MAGIC_POSTDIV)) + i |= info->mem_refresh_rate << 20; + switch (par->crtc.bpp) { + case 8: #if SUPPORT_8_BPP_ABOVE==1 - case 24: + case 24: #endif - i |= 0x00000000; - break; + i |= 0x00000000; + break; #if SUPPORT_8_BPP_ABOVE==1 - case 16: - i |= 0x04000000; - break; - case 32: - i |= 0x08000000; - break; + case 16: + i |= 0x04000000; + break; + case 32: + i |= 0x08000000; + break; #endif - } - if (M64_HAS(CT_BUS)) { - aty_st_le32(DAC_CNTL, 0x87010184, info); - aty_st_le32(BUS_CNTL, 0x680000f9, info); - } else if (M64_HAS(VT_BUS)) { - aty_st_le32(DAC_CNTL, 0x87010184, info); - aty_st_le32(BUS_CNTL, 0x680000f9, info); - } else if (M64_HAS(MOBIL_BUS)) { - aty_st_le32(DAC_CNTL, 0x80010102, info); - aty_st_le32(BUS_CNTL, 0x7b33a040, info); - } else { - /* GT */ - aty_st_le32(DAC_CNTL, 0x86010102, info); - aty_st_le32(BUS_CNTL, 0x7b23a040, info); - aty_st_le32(EXT_MEM_CNTL, - aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info); - } - - aty_st_le32(MEM_CNTL, i, info); + } + if (M64_HAS(CT_BUS)) { + aty_st_le32(DAC_CNTL, 0x87010184, info); + aty_st_le32(BUS_CNTL, 0x680000f9, info); + } else if (M64_HAS(VT_BUS)) { + aty_st_le32(DAC_CNTL, 0x87010184, info); + aty_st_le32(BUS_CNTL, 0x680000f9, info); + } else if (M64_HAS(MOBIL_BUS)) { + aty_st_le32(DAC_CNTL, 0x80010102, info); + aty_st_le32(BUS_CNTL, 0x7b33a040, info); + } else { + /* GT */ + aty_st_le32(DAC_CNTL, 0x86010102, info); + aty_st_le32(BUS_CNTL, 0x7b23a040, info); + aty_st_le32(EXT_MEM_CNTL, + aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info); + } + + aty_st_le32(MEM_CNTL, i, info); } aty_st_8(DAC_MASK, 0xff, info);
/* Initialize the graphics engine */ #if 0 if (par->accel_flags & FB_ACCELF_TEXT) - aty_init_engine(par, info); + aty_init_engine(par, info); #endif
@@ -1413,12 +1413,12 @@ static struct fb_cmap default_16_colors = {
static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, - u_int transp, struct fb_info_aty *info) + u_int transp, struct fb_info_aty *info) { int i, scale;
if (regno > 255) - return 1; + return 1; red >>= 8; green >>= 8; blue >>= 8; @@ -1430,7 +1430,7 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, #endif i = aty_ld_8(DAC_CNTL, info) & 0xfc; if (M64_HAS(EXTRA_BRIGHT)) - i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/ + i |= 0x2; /*DAC_CNTL|0x2 turns off the extra brightness for gt*/ aty_st_8(DAC_CNTL, i, info); aty_st_8(DAC_MASK, 0xff, info); #if PLL_CRTC_DECODE==1 @@ -1446,9 +1446,9 @@ static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, }
int fb_set_cmap(struct fb_cmap *cmap, int kspc, - int (*setcolreg)(u_int, u_int, u_int, u_int, u_int, - struct fb_info_aty *), - struct fb_info_aty *info) + int (*setcolreg)(u_int, u_int, u_int, u_int, u_int, + struct fb_info_aty *), + struct fb_info_aty *info) { int i, start; u16 *red, *green, *blue, *transp; @@ -1461,19 +1461,19 @@ int fb_set_cmap(struct fb_cmap *cmap, int kspc, start = cmap->start;
if (start < 0) - return -EINVAL; + return -EINVAL; for (i = 0; i < cmap->len; i++) { - hred = *red; - hgreen = *green; - hblue = *blue; - htransp = transp ? *transp : 0; - red++; - green++; - blue++; - if (transp) - transp++; - if (setcolreg(start++, hred, hgreen, hblue, htransp, info)) - return 0; + hred = *red; + hgreen = *green; + hblue = *blue; + htransp = transp ? *transp : 0; + red++; + green++; + blue++; + if (transp) + transp++; + if (setcolreg(start++, hred, hgreen, hblue, htransp, info)) + return 0; } return 0; } @@ -1482,11 +1482,11 @@ struct fb_cmap *fb_default_cmap(int len) { #if 0 if (len <= 2) - return &default_2_colors; + return &default_2_colors; if (len <= 4) - return &default_4_colors; + return &default_4_colors; if (len <= 8) - return &default_8_colors; + return &default_8_colors; #endif return &default_16_colors; } @@ -1494,27 +1494,27 @@ struct fb_cmap *fb_default_cmap(int len) static void do_install_cmap(int con, struct fb_info_aty *info) { #if PLL_CRTC_DECODE==1 - int size = info->current_par.crtc.bpp == 16 ? 32 : 256; + int size = info->current_par.crtc.bpp == 16 ? 32 : 256; #else int size = 256; #endif - fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); + fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); }
#endif /*CONFIG_CONSOLE_BTEXT */
static struct device_operations ati_ragexl_graph_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ati_ragexl_init, - .scan_bus = 0, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ati_ragexl_init, + .scan_bus = 0, };
static const struct pci_driver ati_ragexl_graph_driver __pci_driver = { - .ops = &ati_ragexl_graph_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_215XL, + .ops = &ati_ragexl_graph_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_215XL, };
diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c index 7ce3d6b..cc68743 100644 --- a/src/drivers/dec/21143/21143.c +++ b/src/drivers/dec/21143/21143.c @@ -34,25 +34,25 @@ static void dec_21143_enable(device_t dev) /* Command and status configuration (offset 0x04) */ pci_write_config32(dev, 0x04, 0x02800107); printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", - pci_read_config32(dev, 0x04)); + pci_read_config32(dev, 0x04));
/* Cache line size (offset 0x0C) */ pci_write_config8(dev, 0x0C, 0x00); printk(BIOS_DEBUG, "0x0c = %08x (00)\n", - pci_read_config8(dev, 0x0C)); + pci_read_config8(dev, 0x0C)); #endif }
static struct device_operations dec_21143_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = dec_21143_enable, - .scan_bus = 0, + .init = dec_21143_enable, + .scan_bus = 0, };
static const struct pci_driver dec_21143_driver __pci_driver = { - .ops = &dec_21143_ops, + .ops = &dec_21143_ops, .vendor = PCI_VENDOR_ID_DEC, .device = PCI_DEVICE_ID_DEC_21142, // FIXME wrong ID? }; diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index bc72e97..b6a7385 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -201,17 +201,17 @@ static int elog_is_header_valid(struct elog_header *header)
if (header->magic != ELOG_SIGNATURE) { printk(BIOS_ERR, "ELOG: header magic 0x%X != 0x%X\n", - header->magic, ELOG_SIGNATURE); + header->magic, ELOG_SIGNATURE); return 0; } if (header->version != ELOG_VERSION) { printk(BIOS_ERR, "ELOG: header version %u != %u\n", - header->version, ELOG_VERSION); + header->version, ELOG_VERSION); return 0; } if (header->header_size != sizeof(*header)) { printk(BIOS_ERR, "ELOG: header size mismatch %u != %zu\n", - header->header_size, sizeof(*header)); + header->header_size, sizeof(*header)); return 0; } return 1; @@ -430,7 +430,7 @@ static void elog_reinit_descriptor(struct elog_descriptor *elog) { elog_debug("elog_reinit_descriptor()\n"); elog_init_descriptor(elog, elog->type, elog->backing_store, - elog->total_size, elog->staging_header); + elog->total_size, elog->staging_header); }
/* @@ -463,7 +463,7 @@ static int elog_setup_descriptors(u32 flash_base, u32 area_size) } elog_get_flash()->flash_base = flash_base; elog_init_descriptor(elog_get_flash(), ELOG_DESCRIPTOR_FLASH, - area, area_size, staging_header); + area, area_size, staging_header);
/* Initialize the memory area to look like a cleared flash area */ area = malloc(area_size); @@ -473,7 +473,7 @@ static int elog_setup_descriptors(u32 flash_base, u32 area_size) } memset(area, ELOG_TYPE_EOL, area_size); elog_init_descriptor(elog_get_mem(), ELOG_DESCRIPTOR_MEMORY, - area, area_size, (struct elog_header *)area); + area, area_size, (struct elog_header *)area);
return 0; } @@ -490,7 +490,7 @@ static void elog_flash_erase_area(void) }
static void elog_prepare_empty(struct elog_descriptor *elog, - u8 *data, u32 data_size) + u8 *data, u32 data_size) { struct elog_header *header;
@@ -532,11 +532,11 @@ static int elog_sync_flash_to_mem(void)
/* Read the header from SPI to memory */ elog_spi->read(elog_spi, flash->flash_base, - sizeof(struct elog_header), mem->backing_store); + sizeof(struct elog_header), mem->backing_store);
/* Read the valid flash contents from SPI to memory */ elog_spi->read(elog_spi, flash->flash_base + sizeof(struct elog_header), - flash->next_event_offset, mem->data); + flash->next_event_offset, mem->data);
elog_reinit_descriptor(mem);
@@ -799,7 +799,7 @@ int elog_init(void) flash_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr); if (flash_size < 0) { printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP, " - "using CONFIG_ELOG_FLASH_BASE instead\n"); + "using CONFIG_ELOG_FLASH_BASE instead\n"); flash_size = CONFIG_ELOG_AREA_SIZE; } else { flash_base = elog_flash_address_to_offset(flash_base_ptr); @@ -831,17 +831,17 @@ int elog_init(void) elog_initialized = 1;
printk(BIOS_INFO, "ELOG: MEM @0x%p FLASH @0x%p [SPI 0x%08x]\n", - elog_get_mem()->backing_store, - elog_get_flash()->backing_store, elog_get_flash()->flash_base); + elog_get_mem()->backing_store, + elog_get_flash()->backing_store, elog_get_flash()->flash_base);
printk(BIOS_INFO, "ELOG: areas are %d bytes, full threshold %d," - " shrink size %d\n", CONFIG_ELOG_AREA_SIZE, - CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE); + " shrink size %d\n", CONFIG_ELOG_AREA_SIZE, + CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE);
/* Log a clear event if necessary */ if (elog_get_flash()->event_count == 0) elog_add_event_word(ELOG_TYPE_LOG_CLEAR, - elog_get_flash()->total_size); + elog_get_flash()->total_size);
/* Shrink the log if we are getting too full */ if (elog_get_mem()->next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD) @@ -877,10 +877,10 @@ static void elog_fill_timestamp(struct event_header *event) /* Basic sanity check of expected ranges */ if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 || event->minute > 0x59 || event->second > 0x59) { - event->year = 0; + event->year = 0; event->month = 0; - event->day = 0; - event->hour = 0; + event->day = 0; + event->hour = 0; event->minute = 0; event->second = 0; } @@ -905,14 +905,14 @@ static int elog_add_event_mem(u8 event_type, void *data, u8 data_size) event_size = sizeof(*event) + data_size + 1; if (event_size > MAX_EVENT_SIZE) { printk(BIOS_ERR, "ELOG: Event(%X) data size too " - "big (%d)\n", event_type, event_size); + "big (%d)\n", event_type, event_size); return -1; }
/* Make sure event data can fit */ if ((mem->next_event_offset + event_size) >= mem->data_size) { printk(BIOS_ERR, "ELOG: Event(%X) does not fit\n", - event_type); + event_type); return -1; }
@@ -936,7 +936,7 @@ static int elog_add_event_mem(u8 event_type, void *data, u8 data_size) mem->next_event_offset += event_size;
printk(BIOS_INFO, "ELOG: Event(%X) added with size %d\n", - event_type, event_size); + event_type, event_size); return 0; }
diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index f6aa051..0fef721 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -81,7 +81,7 @@ struct elog_descriptor { void *backing_store; u8 *data; u32 flash_base; - u16 total_size; + u16 total_size; u16 data_size; u16 next_event_offset; u16 last_event_offset; diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c index b8bc253..f7bc9c8 100644 --- a/src/drivers/elog/gsmi.c +++ b/src/drivers/elog/gsmi.c @@ -81,13 +81,13 @@ u32 gsmi_exec(u8 command, u32 *param) break;
printk(BIOS_DEBUG, "GSMI Set Event Log " - "(type=0x%x instance=0x%x)\n", - type1->type, type1->instance); + "(type=0x%x instance=0x%x)\n", + type1->type, type1->instance);
if (type1->type == GSMI_LOG_ENTRY_TYPE_KERNEL) { /* Special case for linux kernel shutdown reason */ elog_add_event_dword(ELOG_TYPE_OS_EVENT, - type1->instance); + type1->instance); } else { /* Add other events that may be used for testing */ elog_add_event_dword(type1->type, type1->instance); @@ -102,7 +102,7 @@ u32 gsmi_exec(u8 command, u32 *param) break;
printk(BIOS_DEBUG, "GSMI Clear Event Log (%u%% type=%u)\n", - cel->percentage, cel->data_type); + cel->percentage, cel->data_type);
if (elog_clear() == 0) ret = GSMI_RET_SUCCESS; diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index b4acfef..c55f486 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -13,31 +13,31 @@ #include <device/pci_ops.h>
/* VGA init. We use the Bochs VESA VBE extensions */ -#define VBE_DISPI_IOPORT_INDEX 0x01CE -#define VBE_DISPI_IOPORT_DATA 0x01CF - -#define VBE_DISPI_INDEX_ID 0x0 -#define VBE_DISPI_INDEX_XRES 0x1 -#define VBE_DISPI_INDEX_YRES 0x2 -#define VBE_DISPI_INDEX_BPP 0x3 -#define VBE_DISPI_INDEX_ENABLE 0x4 -#define VBE_DISPI_INDEX_BANK 0x5 -#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 -#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 -#define VBE_DISPI_INDEX_X_OFFSET 0x8 -#define VBE_DISPI_INDEX_Y_OFFSET 0x9 +#define VBE_DISPI_IOPORT_INDEX 0x01CE +#define VBE_DISPI_IOPORT_DATA 0x01CF + +#define VBE_DISPI_INDEX_ID 0x0 +#define VBE_DISPI_INDEX_XRES 0x1 +#define VBE_DISPI_INDEX_YRES 0x2 +#define VBE_DISPI_INDEX_BPP 0x3 +#define VBE_DISPI_INDEX_ENABLE 0x4 +#define VBE_DISPI_INDEX_BANK 0x5 +#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 +#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 +#define VBE_DISPI_INDEX_X_OFFSET 0x8 +#define VBE_DISPI_INDEX_Y_OFFSET 0x9 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
-#define VBE_DISPI_ID0 0xB0C0 -#define VBE_DISPI_ID1 0xB0C1 -#define VBE_DISPI_ID2 0xB0C2 -#define VBE_DISPI_ID4 0xB0C4 -#define VBE_DISPI_ID5 0xB0C5 +#define VBE_DISPI_ID0 0xB0C0 +#define VBE_DISPI_ID1 0xB0C1 +#define VBE_DISPI_ID2 0xB0C2 +#define VBE_DISPI_ID4 0xB0C4 +#define VBE_DISPI_ID5 0xB0C5
-#define VBE_DISPI_DISABLED 0x00 -#define VBE_DISPI_ENABLED 0x01 -#define VBE_DISPI_LFB_ENABLED 0x40 -#define VBE_DISPI_NOCLEARMEM 0x80 +#define VBE_DISPI_DISABLED 0x00 +#define VBE_DISPI_ENABLED 0x01 +#define VBE_DISPI_LFB_ENABLED 0x40 +#define VBE_DISPI_NOCLEARMEM 0x80
static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; @@ -84,9 +84,9 @@ static void bochs_init(device_t dev) return;
printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, " - "%d MiB video memory\n", mem / ( 1024 * 1024)); + "%d MiB video memory\n", mem / ( 1024 * 1024)); printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n", - addr, bar); + addr, bar);
/* setup video mode */ bochs_write(VBE_DISPI_INDEX_ENABLE, 0); diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 9f79d31..9598e48 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -38,7 +38,7 @@
static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; -static u32 addr = 0; +static u32 addr = 0;
enum { @@ -194,7 +194,7 @@ enum #define CIRRUS_SR_EXTENDED_MODE 7 #define CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE 0xf0 #define CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT 0x01 -#define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08 +#define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08 #define CIRRUS_HIDDEN_DAC_888COLOR 0xc5
static void @@ -233,19 +233,19 @@ static void cirrus_init(device_t dev) addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); addr &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; printk(BIOS_DEBUG, "QEMU VGA: cirrus framebuffer @ %x (pci bar 0)\n", - addr); + addr);
vga_misc_write (VGA_IO_MISC_COLOR);
vga_sr_write (VGA_SR_MEMORY_MODE, - VGA_SR_MEMORY_MODE_NORMAL); + VGA_SR_MEMORY_MODE_NORMAL);
vga_sr_write (VGA_SR_MAP_MASK_REGISTER, - (1 << VGA_TEXT_TEXT_PLANE) - | (1 << VGA_TEXT_ATTR_PLANE)); + (1 << VGA_TEXT_TEXT_PLANE) + | (1 << VGA_TEXT_ATTR_PLANE));
vga_sr_write (VGA_SR_CLOCKING_MODE, - VGA_SR_CLOCKING_MODE_8_DOT_CLOCK); + VGA_SR_CLOCKING_MODE_8_DOT_CLOCK);
vga_palette_disable();
@@ -280,9 +280,9 @@ static void cirrus_init(device_t dev) vga_cr_write (VGA_CR_HBLANK_START, horizontal_blank_start - 1); vga_cr_write (VGA_CR_HBLANK_END, horizontal_blank_end); vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_START, - horizontal_sync_pulse_start); + horizontal_sync_pulse_start); vga_cr_write (VGA_CR_HORIZ_SYNC_PULSE_END, - horizontal_sync_pulse_end); + horizontal_sync_pulse_end); vga_cr_write (VGA_CR_VERT_TOTAL, vertical_total & 0xff); vga_cr_write (VGA_CR_OVERFLOW, overflow); vga_cr_write (VGA_CR_CELL_HEIGHT, cell_height_reg); @@ -300,12 +300,12 @@ static void cirrus_init(device_t dev) vga_sr_write (VGA_SR_MEMORY_MODE, VGA_SR_MEMORY_MODE_NORMAL);
vga_cr_write (CIRRUS_CR_EXTENDED_DISPLAY, - (pitch >> CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT) - & CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK); + (pitch >> CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT) + & CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK);
vga_cr_write (VGA_CR_MODE, VGA_CR_MODE_TIMING_ENABLE - | VGA_CR_MODE_BYTE_MODE - | VGA_CR_MODE_NO_HERCULES | VGA_CR_MODE_NO_CGA); + | VGA_CR_MODE_BYTE_MODE + | VGA_CR_MODE_NO_HERCULES | VGA_CR_MODE_NO_CGA);
vga_cr_write (VGA_CR_START_ADDR_LOW_REGISTER, 0); vga_cr_write (VGA_CR_START_ADDR_HIGH_REGISTER, 0); diff --git a/src/drivers/generic/debug/debug_dev.c b/src/drivers/generic/debug/debug_dev.c index b523ca7..5dc1096 100644 --- a/src/drivers/generic/debug/debug_dev.c +++ b/src/drivers/generic/debug/debug_dev.c @@ -24,18 +24,18 @@ static void print_pci_regs(struct device *dev)
static void print_mem(void) { - unsigned int i; + unsigned int i; unsigned int start = 0xfffff000; for(i=start;i<0xffffffff;i++) { - if((i & 0xf)==0) printk(BIOS_DEBUG, "\n %08x:",i); - printk(BIOS_DEBUG, " %02x",(unsigned char)*((unsigned char *)i)); - } + if((i & 0xf)==0) printk(BIOS_DEBUG, "\n %08x:",i); + printk(BIOS_DEBUG, " %02x",(unsigned char)*((unsigned char *)i)); + } printk(BIOS_DEBUG, " %02x\n",(unsigned char)*((unsigned char *)i));
} static void print_pci_regs_all(void) { - struct device *dev; + struct device *dev; unsigned bus, device, function;
for(bus=0; bus<256; bus++) { @@ -50,7 +50,7 @@ static void print_pci_regs_all(void) if(!dev->enabled) { continue; } - printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", + printk(BIOS_DEBUG, "\n%02x:%02x:%02x aka %s", bus, device, function, dev_path(dev)); print_pci_regs(dev); } @@ -94,9 +94,9 @@ static void print_smbus_regs(struct device *dev) // printk(BIOS_DEBUG, "bad device status= %08x\n", status); break; } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ", j); - } + if ((j & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%02x: ", j); + } byte = status & 0xff; printk(BIOS_DEBUG, "%02x ", byte); } @@ -123,38 +123,38 @@ static void print_smbus_regs_all(struct device *dev) for(link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { print_smbus_regs_all(child); - } + } } } static void print_msr_dualcore(void) { - msr_t msr; - unsigned index; - unsigned eax, ebx, ecx, edx; - index = 0x80000008; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", - index, eax, ebx, ecx, edx); - - printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); - - index = 0xc001001f; - printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); - msr = rdmsr(index); - printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x bit 54 is %d\n", - index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1); + msr_t msr; + unsigned index; + unsigned eax, ebx, ecx, edx; + index = 0x80000008; + printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk(BIOS_DEBUG, "cpuid[%08x]: %08x %08x %08x %08x\n", + index, eax, ebx, ecx, edx); + + printk(BIOS_DEBUG, "core number %d\n", ecx & 0xff); + + index = 0xc001001f; + printk(BIOS_DEBUG, "Reading msr: 0x%08x\n", index); + msr = rdmsr(index); + printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x bit 54 is %d\n", + index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1); #if 0 - msr.hi |= (1<<(54-32)); - wrmsr(index, msr); + msr.hi |= (1<<(54-32)); + wrmsr(index, msr);
- msr = rdmsr(index); - printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n", - index, msr.hi, msr.lo); + msr = rdmsr(index); + printk(BIOS_DEBUG, "msr[0x%08x]: 0x%08x%08x\n", + index, msr.hi, msr.lo); #endif
} @@ -164,67 +164,67 @@ static void print_cache_size(void) unsigned index; unsigned int n, eax, ebx, ecx, edx;
- index = 0x80000000; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - n = eax; - - if (n >= 0x80000005) { - index = 0x80000005; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", - edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); - } - - if (n >= 0x80000006) { - index = 0x80000006; - printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); - asm volatile( - "cpuid" - : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) - : "a" (index) - ); - printk(BIOS_DEBUG, "CPU: L2 Cache: %dK (%d bytes/line)\n", - ecx >> 16, ecx & 0xFF); - } + index = 0x80000000; + printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + n = eax; + + if (n >= 0x80000005) { + index = 0x80000005; + printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk(BIOS_DEBUG, "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n", + edx>>24, edx&0xFF, ecx>>24, ecx&0xFF); + } + + if (n >= 0x80000006) { + index = 0x80000006; + printk(BIOS_DEBUG, "calling cpuid 0x%08x\n", index); + asm volatile( + "cpuid" + : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) + : "a" (index) + ); + printk(BIOS_DEBUG, "CPU: L2 Cache: %dK (%d bytes/line)\n", + ecx >> 16, ecx & 0xFF); + }
}
struct tsc_struct { - unsigned lo; - unsigned hi; + unsigned lo; + unsigned hi; }; typedef struct tsc_struct tsc_t;
static tsc_t rdtsc(void) { - tsc_t res; - asm volatile( - "rdtsc" - : "=a" (res.lo), "=d"(res.hi) /* outputs */ - ); - return res; + tsc_t res; + asm volatile( + "rdtsc" + : "=a" (res.lo), "=d"(res.hi) /* outputs */ + ); + return res; }
static void print_tsc(void) {
tsc_t tsc; tsc = rdtsc(); - printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n", - tsc.hi, tsc.lo); + printk(BIOS_DEBUG, "tsc: 0x%08x%08x\n", + tsc.hi, tsc.lo); udelay(1); - tsc = rdtsc(); - printk(BIOS_DEBUG, "tsc: 0x%08x%08x after udelay(1) \n", - tsc.hi, tsc.lo); + tsc = rdtsc(); + printk(BIOS_DEBUG, "tsc: 0x%08x%08x after udelay(1) \n", + tsc.hi, tsc.lo);
}
@@ -252,9 +252,9 @@ static void debug_init(device_t dev) case 4: print_smbus_regs_all(&dev_root); break; - case 5: - print_msr_dualcore(); - break; + case 5: + print_msr_dualcore(); + break; case 6: print_cache_size(); break; @@ -272,10 +272,10 @@ static void debug_noop(device_t dummy) }
static struct device_operations debug_operations = { - .read_resources = debug_noop, - .set_resources = debug_noop, - .enable_resources = debug_noop, - .init = debug_init, + .read_resources = debug_noop, + .set_resources = debug_noop, + .enable_resources = debug_noop, + .init = debug_init, };
static void enable_dev(struct device *dev) diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c index 42b2f07..cad7443 100644 --- a/src/drivers/generic/ioapic/ioapic.c +++ b/src/drivers/generic/ioapic/ioapic.c @@ -27,9 +27,9 @@ static void ioapic_init(device_t dev) ioapic_id = config->apicid;
printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); + ioapic_base); printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + bsp_lapicid);
if (ioapic_id) { printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); @@ -52,7 +52,7 @@ static void ioapic_init(device_t dev) */ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); + io_apic_read(ioapic_base, 0x03) | (1 << 0)); } else { printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); @@ -82,7 +82,7 @@ static void ioapic_init(device_t dev) io_apic_write(ioapic_base, i * 2 + 0x11, high);
printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", - i, high, low); + i, high, low); } }
@@ -106,10 +106,10 @@ static void ioapic_read_resources(device_t dev) }
static struct device_operations ioapic_operations = { - .read_resources = ioapic_read_resources, - .set_resources = ioapic_nop, - .enable_resources = ioapic_enable_resources, - .init = ioapic_init, + .read_resources = ioapic_read_resources, + .set_resources = ioapic_nop, + .enable_resources = ioapic_enable_resources, + .init = ioapic_init, };
static void enable_dev(struct device *dev) diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c index ab85eb5..2c19614 100644 --- a/src/drivers/i2c/adm1026/adm1026.c +++ b/src/drivers/i2c/adm1026/adm1026.c @@ -8,14 +8,14 @@
#define ADM1026_DEVICE 0x2d /* Either 0x2c or 0x2d or 0x2e */ #define ADM1026_REG_CONFIG1 0x00 -#define CFG1_MONITOR 0x01 +#define CFG1_MONITOR 0x01 #define CFG1_INT_ENABLE 0x02 -#define CFG1_INT_CLEAR 0x04 -#define CFG1_AIN8_9 0x08 -#define CFG1_THERM_HOT 0x10 -#define CFT1_DAC_AFC 0x20 -#define CFG1_PWM_AFC 0x40 -#define CFG1_RESET 0x80 +#define CFG1_INT_CLEAR 0x04 +#define CFG1_AIN8_9 0x08 +#define CFG1_THERM_HOT 0x10 +#define CFT1_DAC_AFC 0x20 +#define CFG1_PWM_AFC 0x40 +#define CFG1_RESET 0x80 #define ADM1026_REG_CONFIG2 0x01 #define ADM1026_REG_CONFIG3 0x07
diff --git a/src/drivers/i2c/lm63/lm63.c b/src/drivers/i2c/lm63/lm63.c index 47a5489..764ae9f 100644 --- a/src/drivers/i2c/lm63/lm63.c +++ b/src/drivers/i2c/lm63/lm63.c @@ -14,7 +14,7 @@ static void lm63_init(device_t dev) if (dev->bus->dev->path.type == DEVICE_PATH_I2C) smbus_set_link(dev); // it is under mux result = smbus_read_byte(dev, 0x03); -// result &= ~0x04; +// result &= ~0x04; result |= 0x04; smbus_write_byte(dev, 0x03, result & 0xff); // config lm63 } diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 9c51fff..542d51b 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -206,12 +206,12 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) w83795_dts_enable(dts_src); w83795_set_fan(mode);
- printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); for (i = 0; i < 6; i++) { val = w83795_read(W83795_REG_CTFS(i)); printk(BIOS_INFO, " %x %d", i, val); val = w83795_read(W83795_REG_TTTI(i)); - printk(BIOS_INFO, " %d\n", val); + printk(BIOS_INFO, " %d\n", val); }
/* Temperature ReadOut */ diff --git a/src/drivers/ics/954309/ics954309.c b/src/drivers/ics/954309/ics954309.c index ef62879..0012ecc 100644 --- a/src/drivers/ics/954309/ics954309.c +++ b/src/drivers/ics/954309/ics954309.c @@ -60,10 +60,10 @@ static void ics954309_noop(device_t dummy) }
static struct device_operations ics954309_operations = { - .read_resources = ics954309_noop, - .set_resources = ics954309_noop, - .enable_resources = ics954309_noop, - .init = ics954309_init, + .read_resources = ics954309_noop, + .set_resources = ics954309_noop, + .enable_resources = ics954309_noop, + .init = ics954309_init, };
static void enable_dev(struct device *dev) diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 9be1433..140ab9c 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -90,7 +90,7 @@ static int ipmi_kcs_send_data_byte(int port, const unsigned char byte) if (wait_ibf_timeout(port)) return 1;
- status = ipmi_kcs_status(port); + status = ipmi_kcs_status(port); if ((status & IPMI_KCS_OBF) && IPMI_KCS_STATE(status) != IPMI_KCS_STATE_WRITE) { printk(BIOS_ERR, "%s: status %02x\n", __func__, status); @@ -111,7 +111,7 @@ static int ipmi_kcs_send_last_data_byte(int port, const unsigned char byte) if (wait_ibf_timeout(port)) return 1;
- status = ipmi_kcs_status(port); + status = ipmi_kcs_status(port); if ((status & IPMI_KCS_OBF) && IPMI_KCS_STATE(status) != IPMI_KCS_STATE_WRITE) { printk(BIOS_ERR, "%s: status %02x\n", __func__, status); diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..e4aaa5f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -54,20 +54,20 @@ static void oxford_oxpcie_set_resources(struct device *dev)
static struct device_operations oxford_oxpcie_ops = { .read_resources = pci_dev_read_resources, - .set_resources = oxford_oxpcie_set_resources, + .set_resources = oxford_oxpcie_set_resources, .enable_resources = pci_dev_enable_resources, - .init = oxford_oxpcie_enable, - .scan_bus = 0, + .init = oxford_oxpcie_enable, + .scan_bus = 0, };
static const struct pci_driver oxford_oxpcie_driver __pci_driver = { - .ops = &oxford_oxpcie_ops, + .ops = &oxford_oxpcie_ops, .vendor = 0x1415, .device = 0xc158, };
static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { - .ops = &oxford_oxpcie_ops, + .ops = &oxford_oxpcie_ops, .vendor = 0x1415, .device = 0xc11b, }; diff --git a/src/drivers/pc80/i8254.c b/src/drivers/pc80/i8254.c index 22ca809..4af4a43 100644 --- a/src/drivers/pc80/i8254.c +++ b/src/drivers/pc80/i8254.c @@ -38,18 +38,18 @@ void setup_i8254(void) #if CONFIG_UDELAY_TIMER2 static void load_timer2(unsigned int ticks) { - /* Set up the timer gate, turn off the speaker */ - outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); - outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT); - outb(ticks & 0xFF, TIMER2_PORT); - outb(ticks >> 8, TIMER2_PORT); + /* Set up the timer gate, turn off the speaker */ + outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB); + outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT); + outb(ticks & 0xFF, TIMER2_PORT); + outb(ticks >> 8, TIMER2_PORT); }
void udelay(int usecs) { - load_timer2((usecs*TICKS_PER_MS)/1000); - while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) - ; + load_timer2((usecs*TICKS_PER_MS)/1000); + while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0) + ; } #endif diff --git a/src/drivers/pc80/i8259.c b/src/drivers/pc80/i8259.c index 6f97c56..36aa28c 100644 --- a/src/drivers/pc80/i8259.c +++ b/src/drivers/pc80/i8259.c @@ -23,35 +23,35 @@
#define MASTER_PIC_ICW1 0x20 #define SLAVE_PIC_ICW1 0xa0 -#define ICW_SELECT (1 << 4) -#define OCW_SELECT (0 << 4) -#define ADI (1 << 2) -#define SNGL (1 << 1) -#define IC4 (1 << 0) +#define ICW_SELECT (1 << 4) +#define OCW_SELECT (0 << 4) +#define ADI (1 << 2) +#define SNGL (1 << 1) +#define IC4 (1 << 0)
#define MASTER_PIC_ICW2 0x21 #define SLAVE_PIC_ICW2 0xa1 -#define INT_VECTOR_MASTER 0x20 -#define IRQ0 0x00 -#define IRQ1 0x01 -#define INT_VECTOR_SLAVE 0x28 -#define IRQ8 0x00 -#define IRQ9 0x01 +#define INT_VECTOR_MASTER 0x20 +#define IRQ0 0x00 +#define IRQ1 0x01 +#define INT_VECTOR_SLAVE 0x28 +#define IRQ8 0x00 +#define IRQ9 0x01
#define MASTER_PIC_ICW3 0x21 -#define CASCADED_PIC (1 << 2) +#define CASCADED_PIC (1 << 2)
#define MASTER_PIC_ICW4 0x21 #define SLAVE_PIC_ICW4 0xa1 -#define MICROPROCESSOR_MODE (1 << 0) +#define MICROPROCESSOR_MODE (1 << 0)
#define SLAVE_PIC_ICW3 0xa1 -#define SLAVE_ID 0x02 +#define SLAVE_ID 0x02
#define MASTER_PIC_OCW1 0x21 #define SLAVE_PIC_OCW1 0xa1 -#define IRQ2 (1 << 2) -#define ALL_IRQS 0xff +#define IRQ2 (1 << 2) +#define ALL_IRQS 0xff
#define ELCR1 0x4d0 #define ELCR2 0x4d1 @@ -107,7 +107,7 @@ void setup_i8259(void) * * @param int_num legacy interrupt number (3-7, 9-15) * @param is_level_triggered 1 for level triggered interrupt, 0 for edge - * triggered interrupt + * triggered interrupt */ void i8259_configure_irq_trigger(int int_num, int is_level_triggered) { diff --git a/src/drivers/pc80/isa-dma.c b/src/drivers/pc80/isa-dma.c index b64f125..a3c9b93 100644 --- a/src/drivers/pc80/isa-dma.c +++ b/src/drivers/pc80/isa-dma.c @@ -4,29 +4,29 @@ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 2888bcf..efe5f6e 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -29,8 +29,8 @@ #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
// Keyboard Controller Commands #define KBC_CMD_READ_COMMAND 0x20 // Read command byte @@ -59,7 +59,7 @@ // #define KBD_REPLY_POR 0xAA // Power on reset #define KBD_REPLY_ACK 0xFA // Command ACK -#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again +#define KBD_REPLY_RESEND 0xFE // Command NACK, send command again
/* Wait 400ms for keyboard controller answers */ #define KBC_TIMEOUT_IN_MS 400 diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index bd94bd2..15710bb 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -136,7 +136,7 @@ void rtc_init(int invalid)
/* Make certain we have a valid checksum */ rtc_set_checksum(PC_CKS_RANGE_START, - PC_CKS_RANGE_END,PC_CKS_LOC); + PC_CKS_RANGE_END,PC_CKS_LOC); #endif
/* Clear any pending interrupts */ diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c index b8ed3f1..ca0e051 100644 --- a/src/drivers/pc80/tpm.c +++ b/src/drivers/pc80/tpm.c @@ -56,7 +56,7 @@
#ifndef CONFIG_TPM_TIS_BASE_ADDRESS /* Base TPM address standard for x86 systems */ -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 +#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 #endif
/* the macro accepts the locality value, but only locality 0 is operational */ @@ -64,30 +64,30 @@ (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
/* hardware registers' offsets */ -#define TIS_REG_ACCESS 0x0 -#define TIS_REG_INT_ENABLE 0x8 -#define TIS_REG_INT_VECTOR 0xc -#define TIS_REG_INT_STATUS 0x10 -#define TIS_REG_INTF_CAPABILITY 0x14 -#define TIS_REG_STS 0x18 -#define TIS_REG_DATA_FIFO 0x24 -#define TIS_REG_DID_VID 0xf00 -#define TIS_REG_RID 0xf04 +#define TIS_REG_ACCESS 0x0 +#define TIS_REG_INT_ENABLE 0x8 +#define TIS_REG_INT_VECTOR 0xc +#define TIS_REG_INT_STATUS 0x10 +#define TIS_REG_INTF_CAPABILITY 0x14 +#define TIS_REG_STS 0x18 +#define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_DID_VID 0xf00 +#define TIS_REG_RID 0xf04
/* Some registers' bit field definitions */ -#define TIS_STS_VALID (1 << 7) /* 0x80 */ -#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ -#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ -#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ -#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ -#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */ +#define TIS_STS_VALID (1 << 7) /* 0x80 */ +#define TIS_STS_COMMAND_READY (1 << 6) /* 0x40 */ +#define TIS_STS_TPM_GO (1 << 5) /* 0x20 */ +#define TIS_STS_DATA_AVAILABLE (1 << 4) /* 0x10 */ +#define TIS_STS_EXPECT (1 << 3) /* 0x08 */ +#define TIS_STS_RESPONSE_RETRY (1 << 1) /* 0x02 */
#define TIS_ACCESS_TPM_REG_VALID_STS (1 << 7) /* 0x80 */ #define TIS_ACCESS_ACTIVE_LOCALITY (1 << 5) /* 0x20 */ -#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ -#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ +#define TIS_ACCESS_BEEN_SEIZED (1 << 4) /* 0x10 */ +#define TIS_ACCESS_SEIZE (1 << 3) /* 0x08 */ #define TIS_ACCESS_PENDING_REQUEST (1 << 2) /* 0x04 */ -#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ +#define TIS_ACCESS_REQUEST_USE (1 << 1) /* 0x02 */ #define TIS_ACCESS_TPM_ESTABLISHMENT (1 << 0) /* 0x01 */
#define TIS_STS_BURST_COUNT_MASK (0xffff) @@ -258,7 +258,7 @@ static int tis_command_ready(u8 locality)
/* Wait for command ready to get set */ status = tis_wait_reg(TIS_REG_STS, locality, - TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY); + TIS_STS_COMMAND_READY, TIS_STS_COMMAND_READY);
return (status == TPM_TIMEOUT_ERR) ? TPM_TIMEOUT_ERR : 0; } @@ -334,10 +334,10 @@ static u32 tis_senddata(const u8 * const data, u32 len) u32 value;
value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY, - TIS_STS_COMMAND_READY); + TIS_STS_COMMAND_READY); if (value == TPM_TIMEOUT_ERR) { printf("%s:%d - failed to get 'command_ready' status\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; } burst = BURST_COUNT(value); @@ -349,7 +349,7 @@ static u32 tis_senddata(const u8 * const data, u32 len) while (!burst) { if (max_cycles++ == MAX_DELAY_US) { printf("%s:%d failed to feed %d bytes of %d\n", - __FILE__, __LINE__, len - offset, len); + __FILE__, __LINE__, len - offset, len); return TPM_DRIVER_ERR; } udelay(1); @@ -372,11 +372,11 @@ static u32 tis_senddata(const u8 * const data, u32 len) tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
value = tis_wait_reg(TIS_REG_STS, locality, - TIS_STS_VALID, TIS_STS_VALID); + TIS_STS_VALID, TIS_STS_VALID);
if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) { printf("%s:%d TPM command feed overflow\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; }
@@ -398,10 +398,10 @@ static u32 tis_senddata(const u8 * const data, u32 len) * command. */ value = tis_wait_reg(TIS_REG_STS, locality, - TIS_STS_VALID, TIS_STS_VALID); + TIS_STS_VALID, TIS_STS_VALID); if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) { printf("%s:%d unexpected TPM status 0x%x\n", - __FILE__, __LINE__, value); + __FILE__, __LINE__, value); return TPM_DRIVER_ERR; }
@@ -437,7 +437,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data); if (status == TPM_TIMEOUT_ERR) { printf("%s:%d failed processing command\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; }
@@ -445,7 +445,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) while ((burst_count = BURST_COUNT(status)) == 0) { if (max_cycles++ == MAX_DELAY_US) { printf("%s:%d TPM stuck on read\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; } udelay(1); @@ -467,15 +467,15 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) */ u32 real_length; memcpy(&real_length, - buffer + 2, - sizeof(real_length)); + buffer + 2, + sizeof(real_length)); expected_count = be32_to_cpu(real_length);
if ((expected_count < offset) || - (expected_count > *len)) { + (expected_count > *len)) { printf("%s:%d bad response size %d\n", - __FILE__, __LINE__, - expected_count); + __FILE__, __LINE__, + expected_count); return TPM_DRIVER_ERR; } } @@ -483,10 +483,10 @@ static u32 tis_readresponse(u8 *buffer, size_t *len)
/* Wait for the next portion */ status = tis_wait_reg(TIS_REG_STS, locality, - TIS_STS_VALID, TIS_STS_VALID); + TIS_STS_VALID, TIS_STS_VALID); if (status == TPM_TIMEOUT_ERR) { printf("%s:%d failed to read response\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; }
@@ -501,7 +501,7 @@ static u32 tis_readresponse(u8 *buffer, size_t *len) */ if (status & TIS_STS_DATA_AVAILABLE) { printf("%s:%d wrong receive status %x\n", - __FILE__, __LINE__, status); + __FILE__, __LINE__, status); return TPM_DRIVER_ERR; }
@@ -549,7 +549,7 @@ int tis_open(void) TIS_ACCESS_ACTIVE_LOCALITY, TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) { printf("%s:%d - failed to lock locality %d\n", - __FILE__, __LINE__, locality); + __FILE__, __LINE__, locality); return TPM_DRIVER_ERR; }
@@ -580,7 +580,7 @@ int tis_close(void) TIS_ACCESS_ACTIVE_LOCALITY, 0) == TPM_TIMEOUT_ERR) { printf("%s:%d - failed to release locality %d\n", - __FILE__, __LINE__, locality); + __FILE__, __LINE__, locality); return TPM_DRIVER_ERR; } } @@ -605,7 +605,7 @@ int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, { if (tis_senddata(sendbuf, send_size)) { printf("%s:%d failed sending data to TPM\n", - __FILE__, __LINE__); + __FILE__, __LINE__); return TPM_DRIVER_ERR; }
diff --git a/src/drivers/pc80/vga/vga.h b/src/drivers/pc80/vga/vga.h index 1e6e750..a6fb2b4 100644 --- a/src/drivers/pc80/vga/vga.h +++ b/src/drivers/pc80/vga/vga.h @@ -5,9 +5,9 @@ * Basic palette. */ struct palette { - unsigned char red; - unsigned char green; - unsigned char blue; + unsigned char red; + unsigned char green; + unsigned char blue; };
extern const struct palette default_vga_palette[0x100]; diff --git a/src/drivers/pc80/vga/vga_font_8x16.c b/src/drivers/pc80/vga/vga_font_8x16.c index d98bbee..c32a473 100644 --- a/src/drivers/pc80/vga/vga_font_8x16.c +++ b/src/drivers/pc80/vga/vga_font_8x16.c @@ -19,9 +19,9 @@ #include "vga.h"
/**********************************************/ -/* */ -/* Font file generated by cpi2fnt */ -/* */ +/* */ +/* Font file generated by cpi2fnt */ +/* */ /**********************************************/
const unsigned char diff --git a/src/drivers/pc80/vga/vga_io.c b/src/drivers/pc80/vga/vga_io.c index c31287a..819269e 100644 --- a/src/drivers/pc80/vga/vga_io.c +++ b/src/drivers/pc80/vga/vga_io.c @@ -23,29 +23,29 @@
#include <arch/io.h>
-#define VGA_CR_INDEX 0x3D4 -#define VGA_CR_VALUE 0x3D5 +#define VGA_CR_INDEX 0x3D4 +#define VGA_CR_VALUE 0x3D5
-#define VGA_SR_INDEX 0x3C4 -#define VGA_SR_VALUE 0x3C5 +#define VGA_SR_INDEX 0x3C4 +#define VGA_SR_VALUE 0x3C5
-#define VGA_GR_INDEX 0x3CE -#define VGA_GR_VALUE 0x3CF +#define VGA_GR_INDEX 0x3CE +#define VGA_GR_VALUE 0x3CF
-#define VGA_AR_INDEX 0x3C0 +#define VGA_AR_INDEX 0x3C0 #define VGA_AR_VALUE_READ 0x3C1 #define VGA_AR_VALUE_WRITE VGA_AR_INDEX
-#define VGA_MISC_WRITE 0x3C2 -#define VGA_MISC_READ 0x3CC +#define VGA_MISC_WRITE 0x3C2 +#define VGA_MISC_READ 0x3CC
-#define VGA_ENABLE 0x3C3 -#define VGA_STAT1 0x3DA +#define VGA_ENABLE 0x3C3 +#define VGA_STAT1 0x3DA
-#define VGA_DAC_MASK 0x3C6 +#define VGA_DAC_MASK 0x3C6 #define VGA_DAC_READ_ADDRESS 0x3C7 #define VGA_DAC_WRITE_ADDRESS 0x3C8 -#define VGA_DAC_DATA 0x3C9 +#define VGA_DAC_DATA 0x3C9
/* * VGA enable. Poke this to have the PCI IO enabled device accept VGA IO. diff --git a/src/drivers/pc80/vga/vga_palette.c b/src/drivers/pc80/vga/vga_palette.c index 5f69728..4431053 100644 --- a/src/drivers/pc80/vga/vga_palette.c +++ b/src/drivers/pc80/vga/vga_palette.c @@ -23,254 +23,254 @@ */ const struct palette default_vga_palette[0x100] = { - { 0x00, 0x00, 0x00}, - { 0x00, 0x00, 0x2A}, - { 0x00, 0x2A, 0x00}, - { 0x00, 0x2A, 0x2A}, - { 0x2A, 0x00, 0x00}, - { 0x2A, 0x00, 0x2A}, - { 0x2A, 0x15, 0x00}, - { 0x2A, 0x2A, 0x2A}, - { 0x15, 0x15, 0x15}, - { 0x15, 0x15, 0x3F}, - { 0x15, 0x3F, 0x15}, - { 0x15, 0x3F, 0x3F}, - { 0x3F, 0x15, 0x15}, - { 0x3F, 0x15, 0x3F}, - { 0x3F, 0x3F, 0x15}, - { 0x3F, 0x3F, 0x3F}, - { 0x00, 0x00, 0x00}, - { 0x05, 0x05, 0x05}, - { 0x08, 0x08, 0x08}, - { 0x0B, 0x0B, 0x0B}, - { 0x0E, 0x0E, 0x0E}, - { 0x11, 0x11, 0x11}, - { 0x16, 0x16, 0x16}, - { 0x18, 0x18, 0x18}, - { 0x1C, 0x1C, 0x1C}, - { 0x20, 0x20, 0x20}, - { 0x24, 0x24, 0x24}, - { 0x28, 0x28, 0x28}, - { 0x2D, 0x2D, 0x2D}, - { 0x32, 0x32, 0x32}, - { 0x38, 0x38, 0x38}, - { 0x3F, 0x3F, 0x3F}, - { 0x00, 0x00, 0x3F}, - { 0x20, 0x00, 0x3F}, - { 0x1F, 0x00, 0x3F}, - { 0x2F, 0x00, 0x3F}, - { 0x3F, 0x00, 0x3F}, - { 0x3F, 0x00, 0x2F}, - { 0x3F, 0x00, 0x1F}, - { 0x3F, 0x00, 0x20}, - { 0x3F, 0x00, 0x00}, - { 0x3F, 0x20, 0x00}, - { 0x3F, 0x1F, 0x00}, - { 0x3F, 0x2F, 0x00}, - { 0x3F, 0x3F, 0x00}, - { 0x2F, 0x3F, 0x00}, - { 0x1F, 0x3F, 0x00}, - { 0x20, 0x3F, 0x00}, - { 0x00, 0x3F, 0x00}, - { 0x00, 0x3F, 0x20}, - { 0x00, 0x3F, 0x1F}, - { 0x00, 0x3F, 0x2F}, - { 0x00, 0x3F, 0x3F}, - { 0x00, 0x2F, 0x3F}, - { 0x00, 0x1F, 0x3F}, - { 0x00, 0x20, 0x3F}, - { 0x1F, 0x1F, 0x3F}, - { 0x27, 0x1F, 0x3F}, - { 0x2F, 0x1F, 0x3F}, - { 0x37, 0x1F, 0x3F}, - { 0x3F, 0x1F, 0x3F}, - { 0x3F, 0x1F, 0x37}, - { 0x3F, 0x1F, 0x2F}, - { 0x3F, 0x1F, 0x27}, - { 0x3F, 0x1F, 0x1F}, - { 0x3F, 0x27, 0x1F}, - { 0x3F, 0x2F, 0x1F}, - { 0x3F, 0x37, 0x1F}, - { 0x3F, 0x3F, 0x1F}, - { 0x37, 0x3F, 0x1F}, - { 0x2F, 0x3F, 0x1F}, - { 0x27, 0x3F, 0x1F}, - { 0x1F, 0x3F, 0x1F}, - { 0x1F, 0x3F, 0x27}, - { 0x1F, 0x3F, 0x2F}, - { 0x1F, 0x3F, 0x37}, - { 0x1F, 0x3F, 0x3F}, - { 0x1F, 0x37, 0x3F}, - { 0x1F, 0x2F, 0x3F}, - { 0x1F, 0x27, 0x3F}, - { 0x2D, 0x2D, 0x3F}, - { 0x31, 0x2D, 0x3F}, - { 0x36, 0x2D, 0x3F}, - { 0x3A, 0x2D, 0x3F}, - { 0x3F, 0x2D, 0x3F}, - { 0x3F, 0x2D, 0x3A}, - { 0x3F, 0x2D, 0x36}, - { 0x3F, 0x2D, 0x31}, - { 0x3F, 0x2D, 0x2D}, - { 0x3F, 0x31, 0x2D}, - { 0x3F, 0x36, 0x2D}, - { 0x3F, 0x3A, 0x2D}, - { 0x3F, 0x3F, 0x2D}, - { 0x3A, 0x3F, 0x2D}, - { 0x36, 0x3F, 0x2D}, - { 0x31, 0x3F, 0x2D}, - { 0x2D, 0x3F, 0x2D}, - { 0x2D, 0x3F, 0x31}, - { 0x2D, 0x3F, 0x36}, - { 0x2D, 0x3F, 0x3A}, - { 0x2D, 0x3F, 0x3F}, - { 0x2D, 0x3A, 0x3F}, - { 0x2D, 0x36, 0x3F}, - { 0x2D, 0x31, 0x3F}, - { 0x00, 0x00, 0x1C}, - { 0x07, 0x00, 0x1C}, - { 0x0E, 0x00, 0x1C}, - { 0x15, 0x00, 0x1C}, - { 0x1C, 0x00, 0x1C}, - { 0x1C, 0x00, 0x15}, - { 0x1C, 0x00, 0x0E}, - { 0x1C, 0x00, 0x07}, - { 0x1C, 0x00, 0x00}, - { 0x1C, 0x07, 0x00}, - { 0x1C, 0x0E, 0x00}, - { 0x1C, 0x15, 0x00}, - { 0x1C, 0x1C, 0x00}, - { 0x15, 0x1C, 0x00}, - { 0x0E, 0x1C, 0x00}, - { 0x07, 0x1C, 0x00}, - { 0x00, 0x1C, 0x00}, - { 0x00, 0x1C, 0x07}, - { 0x00, 0x1C, 0x0E}, - { 0x00, 0x1C, 0x15}, - { 0x00, 0x1C, 0x1C}, - { 0x00, 0x15, 0x1C}, - { 0x00, 0x0E, 0x1C}, - { 0x00, 0x07, 0x1C}, - { 0x0E, 0x0E, 0x1C}, - { 0x11, 0x0E, 0x1C}, - { 0x15, 0x0E, 0x1C}, - { 0x18, 0x0E, 0x1C}, - { 0x1C, 0x0E, 0x1C}, - { 0x1C, 0x0E, 0x18}, - { 0x1C, 0x0E, 0x15}, - { 0x1C, 0x0E, 0x11}, - { 0x1C, 0x0E, 0x0E}, - { 0x1C, 0x11, 0x0E}, - { 0x1C, 0x15, 0x0E}, - { 0x1C, 0x18, 0x0E}, - { 0x1C, 0x1C, 0x0E}, - { 0x18, 0x1C, 0x0E}, - { 0x15, 0x1C, 0x0E}, - { 0x11, 0x1C, 0x0E}, - { 0x0E, 0x1C, 0x0E}, - { 0x0E, 0x1C, 0x11}, - { 0x0E, 0x1C, 0x15}, - { 0x0E, 0x1C, 0x18}, - { 0x0E, 0x1C, 0x1C}, - { 0x0E, 0x18, 0x1C}, - { 0x0E, 0x15, 0x1C}, - { 0x0E, 0x11, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x18, 0x16, 0x1C}, - { 0x1A, 0x16, 0x1C}, - { 0x1C, 0x16, 0x1C}, - { 0x1C, 0x16, 0x1A}, - { 0x1C, 0x16, 0x18}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x18, 0x16}, - { 0x1C, 0x1A, 0x16}, - { 0x1C, 0x1C, 0x16}, - { 0x1A, 0x1C, 0x16}, - { 0x18, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x18}, - { 0x16, 0x1C, 0x1A}, - { 0x16, 0x1C, 0x1C}, - { 0x16, 0x1A, 0x1C}, - { 0x16, 0x18, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x00, 0x00, 0x20}, - { 0x04, 0x00, 0x20}, - { 0x08, 0x00, 0x20}, - { 0x0C, 0x00, 0x20}, - { 0x20, 0x00, 0x20}, - { 0x20, 0x00, 0x0C}, - { 0x20, 0x00, 0x08}, - { 0x20, 0x00, 0x04}, - { 0x20, 0x00, 0x00}, - { 0x20, 0x04, 0x00}, - { 0x20, 0x08, 0x00}, - { 0x20, 0x0C, 0x00}, - { 0x20, 0x20, 0x00}, - { 0x0C, 0x20, 0x00}, - { 0x08, 0x20, 0x00}, - { 0x04, 0x20, 0x00}, - { 0x00, 0x20, 0x00}, - { 0x00, 0x20, 0x04}, - { 0x00, 0x20, 0x08}, - { 0x00, 0x20, 0x0C}, - { 0x00, 0x20, 0x20}, - { 0x00, 0x0C, 0x20}, - { 0x00, 0x08, 0x20}, - { 0x00, 0x04, 0x20}, - { 0x08, 0x08, 0x20}, - { 0x0A, 0x08, 0x20}, - { 0x0C, 0x08, 0x20}, - { 0x0E, 0x08, 0x20}, - { 0x20, 0x08, 0x20}, - { 0x20, 0x08, 0x0E}, - { 0x20, 0x08, 0x0C}, - { 0x20, 0x08, 0x0A}, - { 0x20, 0x08, 0x08}, - { 0x20, 0x0A, 0x08}, - { 0x20, 0x0C, 0x08}, - { 0x20, 0x0E, 0x08}, - { 0x20, 0x20, 0x08}, - { 0x0E, 0x20, 0x08}, - { 0x0C, 0x20, 0x08}, - { 0x0A, 0x20, 0x08}, - { 0x08, 0x20, 0x08}, - { 0x08, 0x20, 0x0A}, - { 0x08, 0x20, 0x0C}, - { 0x08, 0x20, 0x0E}, - { 0x08, 0x20, 0x20}, - { 0x08, 0x0E, 0x20}, - { 0x08, 0x0C, 0x20}, - { 0x08, 0x0A, 0x20}, - { 0x0B, 0x0B, 0x20}, - { 0x0C, 0x0B, 0x20}, - { 0x0D, 0x0B, 0x20}, - { 0x0F, 0x0B, 0x20}, - { 0x20, 0x0B, 0x20}, - { 0x20, 0x0B, 0x0F}, - { 0x20, 0x0B, 0x0D}, - { 0x20, 0x0B, 0x0C}, - { 0x20, 0x0B, 0x0B}, - { 0x20, 0x0C, 0x0B}, - { 0x20, 0x0D, 0x0B}, - { 0x20, 0x0F, 0x0B}, - { 0x20, 0x20, 0x0B}, - { 0x0F, 0x20, 0x0B}, - { 0x0D, 0x20, 0x0B}, - { 0x0C, 0x20, 0x0B}, - { 0x0B, 0x20, 0x0B}, - { 0x0B, 0x20, 0x0C}, - { 0x0B, 0x20, 0x0D}, - { 0x0B, 0x20, 0x0F}, - { 0x0B, 0x20, 0x20}, - { 0x0B, 0x0F, 0x20}, - { 0x0B, 0x0D, 0x20}, - { 0x0B, 0x0C, 0x20}, - /* Pad with NULL */ + { 0x00, 0x00, 0x00}, + { 0x00, 0x00, 0x2A}, + { 0x00, 0x2A, 0x00}, + { 0x00, 0x2A, 0x2A}, + { 0x2A, 0x00, 0x00}, + { 0x2A, 0x00, 0x2A}, + { 0x2A, 0x15, 0x00}, + { 0x2A, 0x2A, 0x2A}, + { 0x15, 0x15, 0x15}, + { 0x15, 0x15, 0x3F}, + { 0x15, 0x3F, 0x15}, + { 0x15, 0x3F, 0x3F}, + { 0x3F, 0x15, 0x15}, + { 0x3F, 0x15, 0x3F}, + { 0x3F, 0x3F, 0x15}, + { 0x3F, 0x3F, 0x3F}, + { 0x00, 0x00, 0x00}, + { 0x05, 0x05, 0x05}, + { 0x08, 0x08, 0x08}, + { 0x0B, 0x0B, 0x0B}, + { 0x0E, 0x0E, 0x0E}, + { 0x11, 0x11, 0x11}, + { 0x16, 0x16, 0x16}, + { 0x18, 0x18, 0x18}, + { 0x1C, 0x1C, 0x1C}, + { 0x20, 0x20, 0x20}, + { 0x24, 0x24, 0x24}, + { 0x28, 0x28, 0x28}, + { 0x2D, 0x2D, 0x2D}, + { 0x32, 0x32, 0x32}, + { 0x38, 0x38, 0x38}, + { 0x3F, 0x3F, 0x3F}, + { 0x00, 0x00, 0x3F}, + { 0x20, 0x00, 0x3F}, + { 0x1F, 0x00, 0x3F}, + { 0x2F, 0x00, 0x3F}, + { 0x3F, 0x00, 0x3F}, + { 0x3F, 0x00, 0x2F}, + { 0x3F, 0x00, 0x1F}, + { 0x3F, 0x00, 0x20}, + { 0x3F, 0x00, 0x00}, + { 0x3F, 0x20, 0x00}, + { 0x3F, 0x1F, 0x00}, + { 0x3F, 0x2F, 0x00}, + { 0x3F, 0x3F, 0x00}, + { 0x2F, 0x3F, 0x00}, + { 0x1F, 0x3F, 0x00}, + { 0x20, 0x3F, 0x00}, + { 0x00, 0x3F, 0x00}, + { 0x00, 0x3F, 0x20}, + { 0x00, 0x3F, 0x1F}, + { 0x00, 0x3F, 0x2F}, + { 0x00, 0x3F, 0x3F}, + { 0x00, 0x2F, 0x3F}, + { 0x00, 0x1F, 0x3F}, + { 0x00, 0x20, 0x3F}, + { 0x1F, 0x1F, 0x3F}, + { 0x27, 0x1F, 0x3F}, + { 0x2F, 0x1F, 0x3F}, + { 0x37, 0x1F, 0x3F}, + { 0x3F, 0x1F, 0x3F}, + { 0x3F, 0x1F, 0x37}, + { 0x3F, 0x1F, 0x2F}, + { 0x3F, 0x1F, 0x27}, + { 0x3F, 0x1F, 0x1F}, + { 0x3F, 0x27, 0x1F}, + { 0x3F, 0x2F, 0x1F}, + { 0x3F, 0x37, 0x1F}, + { 0x3F, 0x3F, 0x1F}, + { 0x37, 0x3F, 0x1F}, + { 0x2F, 0x3F, 0x1F}, + { 0x27, 0x3F, 0x1F}, + { 0x1F, 0x3F, 0x1F}, + { 0x1F, 0x3F, 0x27}, + { 0x1F, 0x3F, 0x2F}, + { 0x1F, 0x3F, 0x37}, + { 0x1F, 0x3F, 0x3F}, + { 0x1F, 0x37, 0x3F}, + { 0x1F, 0x2F, 0x3F}, + { 0x1F, 0x27, 0x3F}, + { 0x2D, 0x2D, 0x3F}, + { 0x31, 0x2D, 0x3F}, + { 0x36, 0x2D, 0x3F}, + { 0x3A, 0x2D, 0x3F}, + { 0x3F, 0x2D, 0x3F}, + { 0x3F, 0x2D, 0x3A}, + { 0x3F, 0x2D, 0x36}, + { 0x3F, 0x2D, 0x31}, + { 0x3F, 0x2D, 0x2D}, + { 0x3F, 0x31, 0x2D}, + { 0x3F, 0x36, 0x2D}, + { 0x3F, 0x3A, 0x2D}, + { 0x3F, 0x3F, 0x2D}, + { 0x3A, 0x3F, 0x2D}, + { 0x36, 0x3F, 0x2D}, + { 0x31, 0x3F, 0x2D}, + { 0x2D, 0x3F, 0x2D}, + { 0x2D, 0x3F, 0x31}, + { 0x2D, 0x3F, 0x36}, + { 0x2D, 0x3F, 0x3A}, + { 0x2D, 0x3F, 0x3F}, + { 0x2D, 0x3A, 0x3F}, + { 0x2D, 0x36, 0x3F}, + { 0x2D, 0x31, 0x3F}, + { 0x00, 0x00, 0x1C}, + { 0x07, 0x00, 0x1C}, + { 0x0E, 0x00, 0x1C}, + { 0x15, 0x00, 0x1C}, + { 0x1C, 0x00, 0x1C}, + { 0x1C, 0x00, 0x15}, + { 0x1C, 0x00, 0x0E}, + { 0x1C, 0x00, 0x07}, + { 0x1C, 0x00, 0x00}, + { 0x1C, 0x07, 0x00}, + { 0x1C, 0x0E, 0x00}, + { 0x1C, 0x15, 0x00}, + { 0x1C, 0x1C, 0x00}, + { 0x15, 0x1C, 0x00}, + { 0x0E, 0x1C, 0x00}, + { 0x07, 0x1C, 0x00}, + { 0x00, 0x1C, 0x00}, + { 0x00, 0x1C, 0x07}, + { 0x00, 0x1C, 0x0E}, + { 0x00, 0x1C, 0x15}, + { 0x00, 0x1C, 0x1C}, + { 0x00, 0x15, 0x1C}, + { 0x00, 0x0E, 0x1C}, + { 0x00, 0x07, 0x1C}, + { 0x0E, 0x0E, 0x1C}, + { 0x11, 0x0E, 0x1C}, + { 0x15, 0x0E, 0x1C}, + { 0x18, 0x0E, 0x1C}, + { 0x1C, 0x0E, 0x1C}, + { 0x1C, 0x0E, 0x18}, + { 0x1C, 0x0E, 0x15}, + { 0x1C, 0x0E, 0x11}, + { 0x1C, 0x0E, 0x0E}, + { 0x1C, 0x11, 0x0E}, + { 0x1C, 0x15, 0x0E}, + { 0x1C, 0x18, 0x0E}, + { 0x1C, 0x1C, 0x0E}, + { 0x18, 0x1C, 0x0E}, + { 0x15, 0x1C, 0x0E}, + { 0x11, 0x1C, 0x0E}, + { 0x0E, 0x1C, 0x0E}, + { 0x0E, 0x1C, 0x11}, + { 0x0E, 0x1C, 0x15}, + { 0x0E, 0x1C, 0x18}, + { 0x0E, 0x1C, 0x1C}, + { 0x0E, 0x18, 0x1C}, + { 0x0E, 0x15, 0x1C}, + { 0x0E, 0x11, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x18, 0x16, 0x1C}, + { 0x1A, 0x16, 0x1C}, + { 0x1C, 0x16, 0x1C}, + { 0x1C, 0x16, 0x1A}, + { 0x1C, 0x16, 0x18}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x18, 0x16}, + { 0x1C, 0x1A, 0x16}, + { 0x1C, 0x1C, 0x16}, + { 0x1A, 0x1C, 0x16}, + { 0x18, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x18}, + { 0x16, 0x1C, 0x1A}, + { 0x16, 0x1C, 0x1C}, + { 0x16, 0x1A, 0x1C}, + { 0x16, 0x18, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x00, 0x00, 0x20}, + { 0x04, 0x00, 0x20}, + { 0x08, 0x00, 0x20}, + { 0x0C, 0x00, 0x20}, + { 0x20, 0x00, 0x20}, + { 0x20, 0x00, 0x0C}, + { 0x20, 0x00, 0x08}, + { 0x20, 0x00, 0x04}, + { 0x20, 0x00, 0x00}, + { 0x20, 0x04, 0x00}, + { 0x20, 0x08, 0x00}, + { 0x20, 0x0C, 0x00}, + { 0x20, 0x20, 0x00}, + { 0x0C, 0x20, 0x00}, + { 0x08, 0x20, 0x00}, + { 0x04, 0x20, 0x00}, + { 0x00, 0x20, 0x00}, + { 0x00, 0x20, 0x04}, + { 0x00, 0x20, 0x08}, + { 0x00, 0x20, 0x0C}, + { 0x00, 0x20, 0x20}, + { 0x00, 0x0C, 0x20}, + { 0x00, 0x08, 0x20}, + { 0x00, 0x04, 0x20}, + { 0x08, 0x08, 0x20}, + { 0x0A, 0x08, 0x20}, + { 0x0C, 0x08, 0x20}, + { 0x0E, 0x08, 0x20}, + { 0x20, 0x08, 0x20}, + { 0x20, 0x08, 0x0E}, + { 0x20, 0x08, 0x0C}, + { 0x20, 0x08, 0x0A}, + { 0x20, 0x08, 0x08}, + { 0x20, 0x0A, 0x08}, + { 0x20, 0x0C, 0x08}, + { 0x20, 0x0E, 0x08}, + { 0x20, 0x20, 0x08}, + { 0x0E, 0x20, 0x08}, + { 0x0C, 0x20, 0x08}, + { 0x0A, 0x20, 0x08}, + { 0x08, 0x20, 0x08}, + { 0x08, 0x20, 0x0A}, + { 0x08, 0x20, 0x0C}, + { 0x08, 0x20, 0x0E}, + { 0x08, 0x20, 0x20}, + { 0x08, 0x0E, 0x20}, + { 0x08, 0x0C, 0x20}, + { 0x08, 0x0A, 0x20}, + { 0x0B, 0x0B, 0x20}, + { 0x0C, 0x0B, 0x20}, + { 0x0D, 0x0B, 0x20}, + { 0x0F, 0x0B, 0x20}, + { 0x20, 0x0B, 0x20}, + { 0x20, 0x0B, 0x0F}, + { 0x20, 0x0B, 0x0D}, + { 0x20, 0x0B, 0x0C}, + { 0x20, 0x0B, 0x0B}, + { 0x20, 0x0C, 0x0B}, + { 0x20, 0x0D, 0x0B}, + { 0x20, 0x0F, 0x0B}, + { 0x20, 0x20, 0x0B}, + { 0x0F, 0x20, 0x0B}, + { 0x0D, 0x20, 0x0B}, + { 0x0C, 0x20, 0x0B}, + { 0x0B, 0x20, 0x0B}, + { 0x0B, 0x20, 0x0C}, + { 0x0B, 0x20, 0x0D}, + { 0x0B, 0x20, 0x0F}, + { 0x0B, 0x20, 0x20}, + { 0x0B, 0x0F, 0x20}, + { 0x0B, 0x0D, 0x20}, + { 0x0B, 0x0C, 0x20}, + /* Pad with NULL */ };
diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index 1285726..91c2d1f 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -34,14 +34,14 @@ static void si_sata_init(struct device *dev)
static struct device_operations si_sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = si_sata_init, - .scan_bus = 0, + .init = si_sata_init, + .scan_bus = 0, };
static const struct pci_driver si_sata_driver __pci_driver = { - .ops = &si_sata_ops, - .vendor = 0x1095, - .device = 0x3114, + .ops = &si_sata_ops, + .vendor = 0x1095, + .device = 0x3114, }; diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 21103ae..f9b8ab7 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -9,17 +9,17 @@ #include "spi_flash_internal.h"
/* EN25Q128-specific commands */ -#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ -#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ -#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ +#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ +#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ #define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25Q128_PP 0x02 /* Page Program */ -#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ -#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ -#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ +#define CMD_EN25Q128_PP 0x02 /* Page Program */ +#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ +#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ +#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */
#define EON_ID_EN25Q128 0x18
diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 5a8f82f..948b334 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -135,7 +135,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, ret = spi_claim_bus(flash->spi); if (ret) { printk(BIOS_WARNING, - "SF gigadevice.c: Unable to claim SPI bus\n"); + "SF gigadevice.c: Unable to claim SPI bus\n"); return ret; }
@@ -145,7 +145,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0); if (ret < 0) { printk(BIOS_WARNING, - "SF gigadevice.c: Enabling Write failed\n"); + "SF gigadevice.c: Enabling Write failed\n"); goto out; }
@@ -155,16 +155,16 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, cmd[3] = offset & 0xff; #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, - "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" - " chunk_len = %zu\n", buf + actual, - cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif
ret = spi_flash_cmd_write(flash->spi, cmd, 4, buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, - "SF gigadevice.c: Page Program failed\n"); + "SF gigadevice.c: Page Program failed\n"); goto out; }
@@ -178,8 +178,8 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset,
#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, - "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n", - len, (unsigned int)(offset - len)); + "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n", + len, (unsigned int)(offset - len)); #endif
ret = 0; @@ -209,15 +209,15 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) { printk(BIOS_WARNING, - "SF gigadevice.c: Unsupported ID %#02x%02x\n", - idcode[1], idcode[2]); + "SF gigadevice.c: Unsupported ID %#02x%02x\n", + idcode[1], idcode[2]); return NULL; }
stm = malloc(sizeof(struct gigadevice_spi_flash)); if (!stm) { printk(BIOS_WARNING, - "SF gigadevice.c: Failed to allocate memory\n"); + "SF gigadevice.c: Failed to allocate memory\n"); return NULL; }
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index bbc3704..ebe811a 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -64,7 +64,7 @@ struct macronix_spi_flash { };
static inline struct macronix_spi_flash *to_macronix_spi_flash(struct spi_flash - *flash) + *flash) { return container_of(flash, struct macronix_spi_flash, flash); } diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 6dd6df9..dd5d53f 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -67,7 +67,7 @@ struct spansion_spi_flash { };
static inline struct spansion_spi_flash *to_spansion_spi_flash(struct spi_flash - *flash) + *flash) { return container_of(flash, struct spansion_spi_flash, flash); } diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1a9504..851e9ad 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -166,7 +166,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd,
#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], - cmd[2], cmd[3], offset); + cmd[2], cmd[3], offset); #endif ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); if (ret) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..198b70e 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -79,5 +79,5 @@ struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, - u8 *idcode); + u8 *idcode); struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 8cf3f96..71dadcf 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -187,7 +187,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) #endif
ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, - buf + actual, 2); + buf + actual, 2); if (ret) { printk(BIOS_WARNING, "SF: SST word program failed\n"); break; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index af23853..121f0a1 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -68,7 +68,7 @@ struct stmicro_spi_flash { };
static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash - *flash) + *flash) { return container_of(flash, struct stmicro_spi_flash, flash); } diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index c44afea..88a3ba4 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -133,7 +133,7 @@ static int winbond_write(struct spi_flash *flash, cmd[3] = offset & 0xff; #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" - " chunk_len = %zu\n", buf + actual, + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif
diff --git a/src/drivers/ti/tps65090/tps65090.c b/src/drivers/ti/tps65090/tps65090.c index 653d20d..46a7bc7 100644 --- a/src/drivers/ti/tps65090/tps65090.c +++ b/src/drivers/ti/tps65090/tps65090.c @@ -7,14 +7,14 @@ * met: * * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT diff --git a/src/drivers/ti/tps65090/tps65090.h b/src/drivers/ti/tps65090/tps65090.h index b38db59..e7fd216 100644 --- a/src/drivers/ti/tps65090/tps65090.h +++ b/src/drivers/ti/tps65090/tps65090.h @@ -7,14 +7,14 @@ * met: * * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following - * disclaimer in the documentation and/or other materials provided - * with the distribution. + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT diff --git a/src/drivers/trident/blade3d/blade3d.c b/src/drivers/trident/blade3d/blade3d.c index 1d79766..1c65929 100644 --- a/src/drivers/trident/blade3d/blade3d.c +++ b/src/drivers/trident/blade3d/blade3d.c @@ -24,12 +24,12 @@ #define inp inb #define outp(port,val) outb(val, port)
-#define WORD unsigned int -#define BYTE unsigned char -#define DWORD unsigned long +#define WORD unsigned int +#define BYTE unsigned char +#define DWORD unsigned long
#define SGRAMTimg 0x27 -#define CHIPREV 0x3 //1,RA 2,RB,3,RC +#define CHIPREV 0x3 //1,RA 2,RB,3,RC
#define Port_SRX 0x3c4 #define Port_CRX 0x3d4 @@ -37,7 +37,7 @@ #define Port_BRX 0x3c0
static BYTE Mem_Clk_Table[][2] = { - //For EDO, 3x5.2a.3:2=01 3x4.28.2:0 + //For EDO, 3x5.2a.3:2=01 3x4.28.2:0 { 0x50, 0x46 }, //000, F_78 { 0xCF, 0x51 }, //001, F_81 = 81.011Mhz { 0x30, 0x83 }, //010, F_40 = 40.006Mhz @@ -69,7 +69,7 @@ typedef Def_Reg_struct* lpDef_Reg_struct; // , *pDef_Reg_struct, far * lpDef_Reg_struct;
static Def_Reg_struct Mode3_temp[] = { //mode3 temp - //port index value mask + //port index value mask {Port_CRX, 0x00, 0x5F, 0x00}, {Port_CRX, 0x01, 0x4F, 0x00}, {Port_CRX, 0x02, 0x50, 0x00}, @@ -100,7 +100,7 @@ static Def_Reg_struct Mode3_temp[] = { //mode3 temp WORD Length_Mode3_temp = sizeof(Mode3_temp) / sizeof(Def_Reg_struct);
Def_Reg_struct Mode3_reg[] = { //mode3 - //port index value mask + //port index value mask {Port_CRX, 0x00, 0x5F, 0x00}, //3d5 {Port_CRX, 0x01, 0x4F, 0x00}, {Port_CRX, 0x02, 0x50, 0x00}, @@ -187,7 +187,7 @@ Def_Reg_struct Mode3_reg[] = { //mode3 static WORD Length_Mode3_reg = sizeof(Mode3_reg) / sizeof(Def_Reg_struct);
static Def_Reg_struct Init_reg[] = { - //port index value mask + //port index value mask {Port_GRX, 0x25, 0x00, 0x00}, {Port_GRX, 0x21, 0x00, 0x00}, {Port_GRX, 0x22, 0x00, 0x00}, @@ -856,7 +856,7 @@ static void config_OEM_regs(void) Old_value = inp(lpMode3_temp[i].rPort + 1); outp(lpMode3_temp[i].rPort + 1, lpMode3_temp[i].rValue | (Old_value & lpMode3_temp[i]. - rMask)); + rMask)); } //screen off outp(Port_SRX, 0x01); @@ -867,7 +867,7 @@ static void config_OEM_regs(void) Old_value = inp(lpInit_reg[i].rPort + 1); outp(lpInit_reg[i].rPort + 1, lpInit_reg[i].rValue | (Old_value & lpInit_reg[i]. - rMask)); + rMask)); } delay(10); init_SGRAM(); @@ -933,7 +933,7 @@ static void init_SGRAM(void) for (i = 0; i < 10; i++) { outp(Port_CRX, 0x1c); outp(Port_CRX + 1, - inp(Port_CRX + 1) | 0x40); + inp(Port_CRX + 1) | 0x40); } delay(100); outp(Port_CRX, 0x1c); @@ -971,8 +971,8 @@ static void set_video_mode(void) outp(lpMode3_reg[i].rPort, lpMode3_reg[i].rIndex); Old_value = inp(lpMode3_reg[i].rPort + 1); outp(lpMode3_reg[i].rPort + 1, - lpMode3_reg[i]. - rValue | (Old_value & lpMode3_reg[i].rMask)); + lpMode3_reg[i]. + rValue | (Old_value & lpMode3_reg[i].rMask)); } } //set_font(); @@ -1002,7 +1002,7 @@ static void clear_MEM(void) "pop %di\n\t" "pop %cx\n\t" "pop %ax\n\t" - ); + ); }
@@ -1014,15 +1014,15 @@ static void trident_blade3d_init(struct device *dev)
static struct device_operations trident_blade3d_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = trident_blade3d_init, - .scan_bus = 0, + .init = trident_blade3d_init, + .scan_bus = 0, };
static const struct pci_driver trident_blade3d_driver __pci_driver = { - .ops = &trident_blade3d_ops, - .vendor = 0x1023, - .device = 0x9880, + .ops = &trident_blade3d_ops, + .vendor = 0x1023, + .device = 0x9880, };
diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h index 8fc88d2..5917e14 100644 --- a/src/ec/acpi/ec.h +++ b/src/ec/acpi/ec.h @@ -24,19 +24,19 @@ #define EC_SC 0x66
/* EC_SC input */ -#define EC_SMI_EVT (1 << 6) // 1: SMI event pending -#define EC_SCI_EVT (1 << 5) // 1: SCI event pending -#define EC_BURST (1 << 4) // controller is in burst mode -#define EC_CMD (1 << 3) // 1: byte in data register is command +#define EC_SMI_EVT (1 << 6) // 1: SMI event pending +#define EC_SCI_EVT (1 << 5) // 1: SCI event pending +#define EC_BURST (1 << 4) // controller is in burst mode +#define EC_CMD (1 << 3) // 1: byte in data register is command // 0: byte in data register is data -#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) /* EC_SC output */ -#define RD_EC 0x80 // Read Embedded Controller -#define WR_EC 0x81 // Write Embedded Controller -#define BE_EC 0x82 // Burst Enable Embedded Controller -#define BD_EC 0x83 // Burst Disable Embedded Controller -#define QR_EC 0x84 // Query Embedded Controller +#define RD_EC 0x80 // Read Embedded Controller +#define WR_EC 0x81 // Write Embedded Controller +#define BE_EC 0x82 // Burst Enable Embedded Controller +#define BD_EC 0x83 // Burst Disable Embedded Controller +#define QR_EC 0x84 // Query Embedded Controller
int send_ec_command(u8 command); int send_ec_data(u8 data); diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl index 90d8adb..577dd15 100644 --- a/src/ec/compal/ene932/acpi/battery.asl +++ b/src/ec/compal/ene932/acpi/battery.asl @@ -37,10 +37,10 @@ Device (BATX) 0xFFFFFFFF, // Design Capacity of Low 0x00000001, // Capacity Granularity 1 0x00000001, // Capacity Granularity 2 - "", // Model Number - "", // Serial Number + "", // Model Number + "", // Serial Number "LION", // Battery Type - "" // OEM Information + "" // OEM Information })
Name (PBST, Package () { @@ -136,7 +136,7 @@ Device (BATX) // See if within ~3% of full ShiftRight (Local2, 5, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + LLess (Local1, Add (Local2, Local3)))) { Store (Local2, Local1) } diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl index cb50a21..6664373 100644 --- a/src/ec/compal/ene932/acpi/ec.asl +++ b/src/ec/compal/ene932/acpi/ec.asl @@ -34,227 +34,227 @@ Device (EC0) { // EC Name Space Configuration Offset(0x00), - , 1, // Reserved ; 00h.0 - LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 - , 6, // Reserved ; 00h.2 ~ 00h.6 - HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function - HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function - LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage - , 7, // Reserved ; 03h.1 ~ 03h.7 - ADAP, 2, // Adaptor Type ; 04h.0 ~ 1 - // 0x00 = default(65w) - // 0x01 = 65w - // 0x02 = 90w - // 0x03 = 120w - , 6, // Reserved ; 04h.2 ~ 04h.7 - Offset(0x08), // Project Common Name space definition ; 08h - 2Ch + , 1, // Reserved ; 00h.0 + LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1 + , 6, // Reserved ; 00h.2 ~ 00h.6 + HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function + HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function + LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage + , 7, // Reserved ; 03h.1 ~ 03h.7 + ADAP, 2, // Adaptor Type ; 04h.0 ~ 1 + // 0x00 = default(65w) + // 0x01 = 65w + // 0x02 = 90w + // 0x03 = 120w + , 6, // Reserved ; 04h.2 ~ 04h.7 + Offset(0x08), // Project Common Name space definition ; 08h - 2Ch Offset(0x2D), - DSPM, 1, // Display Mode.(0=dGPU, 1=iGPU ) ; 2Dh.0 + DSPM, 1, // Display Mode.(0=dGPU, 1=iGPU ) ; 2Dh.0 Offset(0x2E), - EFP1, 4, // Turbo Off P-State ; 2Eh.3-0 - Offset(0x40), // ABO Common Name space definition ; 2F - 5Ch + EFP1, 4, // Turbo Off P-State ; 2Eh.3-0 + Offset(0x40), // ABO Common Name space definition ; 2F - 5Ch Offset(0x5D), - ENIB, 16, // Ext_NameSpace_Index ; 5Dh - // Ext_NameSpace_Bank ; 5Eh - ENDD, 8, // Ext_NameSpace_Data ; 5Fh + ENIB, 16, // Ext_NameSpace_Index ; 5Dh + // Ext_NameSpace_Bank ; 5Eh + ENDD, 8, // Ext_NameSpace_Data ; 5Fh Offset(0x60), - SMPR, 8, // SMBus protocol register ; 60h - SMST, 8, // SMBus status register ; 61h - SMAD, 8, // SMBus address register ; 62h - SMCM, 8, // SMBus command register ; 63h - SMD0, 0x100, // SMBus data regs (32) ; 64h - 83h - BCNT, 8, // SMBus Block Count ; 84h - SMAA, 24, // SMBus Alarm Address ; 85h - 87h + SMPR, 8, // SMBus protocol register ; 60h + SMST, 8, // SMBus status register ; 61h + SMAD, 8, // SMBus address register ; 62h + SMCM, 8, // SMBus command register ; 63h + SMD0, 0x100, // SMBus data regs (32) ; 64h - 83h + BCNT, 8, // SMBus Block Count ; 84h + SMAA, 24, // SMBus Alarm Address ; 85h - 87h Offset(0x90), - BMFN, 72, // Battery Manufacture name ; 90h - 98h - BATD, 56, // Battery Device name ; 99h - 9fh + BMFN, 72, // Battery Manufacture name ; 90h - 98h + BATD, 56, // Battery Device name ; 99h - 9fh Offset(0xA1), - , 1, // Reserve ; A1h.0 - VIDO, 1, // Video Out Button (1=Pressed) ; A1h.1 - TOUP, 1, // Touch Pad Button (0=On, 1=Off) ; A1h.2 + , 1, // Reserve ; A1h.0 + VIDO, 1, // Video Out Button (1=Pressed) ; A1h.1 + TOUP, 1, // Touch Pad Button (0=On, 1=Off) ; A1h.2 Offset(0xA2), - ODTS, 8, // OS Shutdown Temp2 (DTS) ; A2h + ODTS, 8, // OS Shutdown Temp2 (DTS) ; A2h Offset(0xA3), - OSTY, 3, // OSTYPE : 000- XP ; A3h.0-2 - // 001- Vista - // 010- Linux - // 011- Win7 - , 4, // Reserve ; A3h.3-6 - ADPT, 1, // AC Adapter (0=OffLine, 1=OnLine) ; A3h.7 + OSTY, 3, // OSTYPE : 000- XP ; A3h.0-2 + // 001- Vista + // 010- Linux + // 011- Win7 + , 4, // Reserve ; A3h.3-6 + ADPT, 1, // AC Adapter (0=OffLine, 1=OnLine) ; A3h.7 Offset(0xA4), - PWAK, 1, // PME Wake Enable(0=Disable, 1=Enable) ; A4h.0 - MWAK, 1, // Modem Wake Enable(0/1=Disable/Enable); A4h.1 - LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); A4h.2 - RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; A4h.3 - WWAK, 1, // WLAN wake Enable (0=Disable,1=Enable); A4h.4 - UWAK, 1, // USB WAKE(0=Disable, 1=Enable) ; A4h.5 - KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; A4h.6 - TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; A4h.7 + PWAK, 1, // PME Wake Enable(0=Disable, 1=Enable) ; A4h.0 + MWAK, 1, // Modem Wake Enable(0/1=Disable/Enable); A4h.1 + LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); A4h.2 + RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; A4h.3 + WWAK, 1, // WLAN wake Enable (0=Disable,1=Enable); A4h.4 + UWAK, 1, // USB WAKE(0=Disable, 1=Enable) ; A4h.5 + KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; A4h.6 + TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; A4h.7 Offset(0xA5), - CCAC, 1, // Charge Current (1=AC OFF) ; A5h.0 - AOAC, 1, // Adapter OVP (1=AC OFF) ; A5h.1 - BLAC, 1, // Batt learning (1=AC OFF) ; A5h.2 - PSRC, 1, // Command (1=AC OFF) ; A5h.3 - BOAC, 1, // Batt OVP (1=AC OFF) ; A5h.4 - LCAC, 1, // Leak Current (1=AC OFF) ; A5h.5 - AAAC, 1, // Air Adapter (1=AC OFF) ; A5h.6 - ACAC, 1, // AC Off (1=AC OFF) ; A5h.7 + CCAC, 1, // Charge Current (1=AC OFF) ; A5h.0 + AOAC, 1, // Adapter OVP (1=AC OFF) ; A5h.1 + BLAC, 1, // Batt learning (1=AC OFF) ; A5h.2 + PSRC, 1, // Command (1=AC OFF) ; A5h.3 + BOAC, 1, // Batt OVP (1=AC OFF) ; A5h.4 + LCAC, 1, // Leak Current (1=AC OFF) ; A5h.5 + AAAC, 1, // Air Adapter (1=AC OFF) ; A5h.6 + ACAC, 1, // AC Off (1=AC OFF) ; A5h.7 Offset(0xA6), - S3ST, 1, // System entry S3 State : A6.0 - S3RM, 1, // System resume from S3 State : A6.1 - S4ST, 1, // System entry S4 State : A6.2 - S4RM, 1, // System resume from S4 State : A6.3 - S5ST, 1, // System entry S4 State : A6.4 - S5RM, 1, // System resume from S4 State : A6.5 - , 2, // Reserve ; A6h.6-7 + S3ST, 1, // System entry S3 State : A6.0 + S3RM, 1, // System resume from S3 State : A6.1 + S4ST, 1, // System entry S4 State : A6.2 + S4RM, 1, // System resume from S4 State : A6.3 + S5ST, 1, // System entry S4 State : A6.4 + S5RM, 1, // System resume from S4 State : A6.5 + , 2, // Reserve ; A6h.6-7 Offset(0xA7), - OSTT, 8, // OS Throttling Temp ; A7h - OSST, 8, // OS Shutdown Temp ; A8h - THLT, 8, // Throttling Temp ; A9h - TCNL, 8, // Tcontrol Temp ; AAh - MODE, 1, // Mode(0=Local, 1=Remote) ; ABh.0 - , 2, // Reserve ; ABh.1-2 - INIT, 1, // INITOK(0/1=Controlled by OS/EC) ; ABh.3 - FAN1, 1, // FAN1 Active ; ABh.4 - FAN2, 1, // FAN2 Active ; ABh.5 - FANT, 1, // FAN Speed Time OK ; ABh.6 - SKNM, 1, // Skin Mode (0/1=Skin Address 90/92) ; ABh.7 - SDTM, 8, // Shutdown Thermal Temperature ; ACh - FSSN, 4, // Fan Speed Step Number ; ADh.0-3 - // 00 : Fan Off - // 01 : Fan On Speed 1 - // 10 : Fan On Speed 2 - // 11 : Fan On Speed 3 - FANU, 4, // Machine Fan's number ; ADh.4-7 - PCVL, 4, // Throttling Level ; AEh.0-3 - // 0000 : Nothing - // 0001 : Clock throttling 12.5% - // 0010 : Clock throttling 25% - // 0011 : Clock throttling 37.5% - // 0100 : Clock throttling 50% - , 2, // Reserved ; AEh.4-5 - SWTO, 1, // SW Throttling (1=Active) ; AEh.6 - TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 - TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 - THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 - , 2, // Reserved ; AFh.2-3 - NPST, 4, // Number of P-State level ; AFh.4-7 - CTMP, 8, // Current CPU Temperature ; B0h - CTML, 8, // CPU local temperature ; B1h - SKTA, 8, // Skin Temperature A ; B2h - SKTB, 8, // GPU Temperature ; B3h - SKTC, 8, // Skin Temperature C ; B4h - , 8, // Reserved ; B5h - NTMP, 8, // North Bridge Diode Temp ; B6h + OSTT, 8, // OS Throttling Temp ; A7h + OSST, 8, // OS Shutdown Temp ; A8h + THLT, 8, // Throttling Temp ; A9h + TCNL, 8, // Tcontrol Temp ; AAh + MODE, 1, // Mode(0=Local, 1=Remote) ; ABh.0 + , 2, // Reserve ; ABh.1-2 + INIT, 1, // INITOK(0/1=Controlled by OS/EC) ; ABh.3 + FAN1, 1, // FAN1 Active ; ABh.4 + FAN2, 1, // FAN2 Active ; ABh.5 + FANT, 1, // FAN Speed Time OK ; ABh.6 + SKNM, 1, // Skin Mode (0/1=Skin Address 90/92) ; ABh.7 + SDTM, 8, // Shutdown Thermal Temperature ; ACh + FSSN, 4, // Fan Speed Step Number ; ADh.0-3 + // 00 : Fan Off + // 01 : Fan On Speed 1 + // 10 : Fan On Speed 2 + // 11 : Fan On Speed 3 + FANU, 4, // Machine Fan's number ; ADh.4-7 + PCVL, 4, // Throttling Level ; AEh.0-3 + // 0000 : Nothing + // 0001 : Clock throttling 12.5% + // 0010 : Clock throttling 25% + // 0011 : Clock throttling 37.5% + // 0100 : Clock throttling 50% + , 2, // Reserved ; AEh.4-5 + SWTO, 1, // SW Throttling (1=Active) ; AEh.6 + TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7 + TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0 + THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1 + , 2, // Reserved ; AFh.2-3 + NPST, 4, // Number of P-State level ; AFh.4-7 + CTMP, 8, // Current CPU Temperature ; B0h + CTML, 8, // CPU local temperature ; B1h + SKTA, 8, // Skin Temperature A ; B2h + SKTB, 8, // GPU Temperature ; B3h + SKTC, 8, // Skin Temperature C ; B4h + , 8, // Reserved ; B5h + NTMP, 8, // North Bridge Diode Temp ; B6h Offset(0xB7), - , 1, // Reserved ; B7h.0 - SKEY, 1, // Security key event ; B7h.1 - DIGM, 1, // Digital Mode (1=Selected) ; B7h.2 - CDLE, 1, // CD lock mode enable ; B7h.3 - , 4, // Reserved ; B7h.4-7 - , 1, // Reserved ; B8h.0 - LIDF, 1, // LID flag (1=Closed, 0=Opened) ; B8h.1 - PMEE, 1, // PME event (0=off, 1=On) ; B8h.2 - PWBE, 1, // Power button event (0=off, 1=On) ; B8h.3 - RNGE, 1, // Ring in event (0=off, 1=On) ; B8h.4 - BTWE, 1, // Bluetooth wake event (0=off, 1=On) ; B8h.5 - , 2, // Reserved ; B8h.6-7 + , 1, // Reserved ; B7h.0 + SKEY, 1, // Security key event ; B7h.1 + DIGM, 1, // Digital Mode (1=Selected) ; B7h.2 + CDLE, 1, // CD lock mode enable ; B7h.3 + , 4, // Reserved ; B7h.4-7 + , 1, // Reserved ; B8h.0 + LIDF, 1, // LID flag (1=Closed, 0=Opened) ; B8h.1 + PMEE, 1, // PME event (0=off, 1=On) ; B8h.2 + PWBE, 1, // Power button event (0=off, 1=On) ; B8h.3 + RNGE, 1, // Ring in event (0=off, 1=On) ; B8h.4 + BTWE, 1, // Bluetooth wake event (0=off, 1=On) ; B8h.5 + , 2, // Reserved ; B8h.6-7 Offset(0xB9), - BRTS, 8, // Brightness Value ; B9h - S35M, 1, // S3.5 HotKey test mode ; BAh.0 - S35S, 1, // S3.5 function status ; BAh.1 - , 2, // Reserved ; BAh.2-3 - FFEN, 1, // IRST support bit (1= Support) ; BAh.4 - FFST, 1, // IRST status flag ; BAh.5 - , 2, // Reserved ; BAh.6-7 - WLAT, 1, // Wireless LAN (0=Inactive, 1=Active) ; BBh.0 - BTAT, 1, // BlueTooth (0=Inactive, 1=Active) ; BBh.1 - WLEX, 1, // Wireless LAN (0=Not Exist, 1=Exist) ; BBh.2 - BTEX, 1, // BlueTooth (0=Not Exist, 1=Exist) ; BBh.3 - KLSW, 1, // Kill Switch (0=Off, 1=On) ; BBh.4 - WLOK, 1, // Wireless LAN Initialize OK ; BBh.5 - AT3G, 1, // 3G (0=non-active, 1=active) ; BBh.6 - EX3G, 1, // 3G (0=Not Exist, 1=Exist) ; BBh.7 - PJID, 8, // Project ID ; BCh - CPUJ, 3, // CPU Type ; BDh.0-2 - // 00, Tj85, - // 01, Tj90, - // 02, Tj100, - // 03, Tj105, - // 04 - 07, Reserved - CPNM, 3, // CPU Core number ; BDh.3-5 - // 00, Single Core - // 01, Dual Core - // 02, Quad Core - // 03 - 07, Reserved - GATY, 2, // VGA Type ; BDh.6-7 - // 00, UMA - // 01. Discrete - // 02 - 03, Reserved + BRTS, 8, // Brightness Value ; B9h + S35M, 1, // S3.5 HotKey test mode ; BAh.0 + S35S, 1, // S3.5 function status ; BAh.1 + , 2, // Reserved ; BAh.2-3 + FFEN, 1, // IRST support bit (1= Support) ; BAh.4 + FFST, 1, // IRST status flag ; BAh.5 + , 2, // Reserved ; BAh.6-7 + WLAT, 1, // Wireless LAN (0=Inactive, 1=Active) ; BBh.0 + BTAT, 1, // BlueTooth (0=Inactive, 1=Active) ; BBh.1 + WLEX, 1, // Wireless LAN (0=Not Exist, 1=Exist) ; BBh.2 + BTEX, 1, // BlueTooth (0=Not Exist, 1=Exist) ; BBh.3 + KLSW, 1, // Kill Switch (0=Off, 1=On) ; BBh.4 + WLOK, 1, // Wireless LAN Initialize OK ; BBh.5 + AT3G, 1, // 3G (0=non-active, 1=active) ; BBh.6 + EX3G, 1, // 3G (0=Not Exist, 1=Exist) ; BBh.7 + PJID, 8, // Project ID ; BCh + CPUJ, 3, // CPU Type ; BDh.0-2 + // 00, Tj85, + // 01, Tj90, + // 02, Tj100, + // 03, Tj105, + // 04 - 07, Reserved + CPNM, 3, // CPU Core number ; BDh.3-5 + // 00, Single Core + // 01, Dual Core + // 02, Quad Core + // 03 - 07, Reserved + GATY, 2, // VGA Type ; BDh.6-7 + // 00, UMA + // 01. Discrete + // 02 - 03, Reserved Offset(0xBE), - BOL0, 1, // Batt0 (0=OffLine, 1=OnLine) ; BEh.0 - BOL1, 1, // Batt1 (0=OffLine, 1=OnLine) ; BEh.1 - , 2, // Reserved ; BEh.2-3 - BCC0, 1, // Batt0 be charging (1=Charging) ; BEh.4 - BCC1, 1, // Batt1 be charging (1=Charging) ; BEh.5 - , 2, // Reserved ; BEh.6-7 - BPU0, 1, // Batt0 (1=PowerUp) ; BFh.0 - BPU1, 1, // Batt1 (1=PowerUp) ; BFh.1 - , 2, // Reserved ; BFh.2-3 - BOS0, 1, // Batt0 (1=OnSMBUS) ; BFh.4 - BOS1, 1, // Batt1 (1=OnSMBUS) ; BFh.5 - , 2, // Reserved ; BFh.6-7 + BOL0, 1, // Batt0 (0=OffLine, 1=OnLine) ; BEh.0 + BOL1, 1, // Batt1 (0=OffLine, 1=OnLine) ; BEh.1 + , 2, // Reserved ; BEh.2-3 + BCC0, 1, // Batt0 be charging (1=Charging) ; BEh.4 + BCC1, 1, // Batt1 be charging (1=Charging) ; BEh.5 + , 2, // Reserved ; BEh.6-7 + BPU0, 1, // Batt0 (1=PowerUp) ; BFh.0 + BPU1, 1, // Batt1 (1=PowerUp) ; BFh.1 + , 2, // Reserved ; BFh.2-3 + BOS0, 1, // Batt0 (1=OnSMBUS) ; BFh.4 + BOS1, 1, // Batt1 (1=OnSMBUS) ; BFh.5 + , 2, // Reserved ; BFh.6-7 Offset(0xC0), - BTY0, 1, // Batt Type (0=NiMh, 1=LiIon) ; C0h.0 - BAM0, 1, // Battery mode (0=mA, 1=mW) ; C0h.1 - BAL0, 1, // Low Battery ; C0h.2 - , 1, // Reserved ; C0h.3 - BMF0, 3, // Battery Manufacturer ; C0h.4-6 - // 001 : Sanyo - // 010 : Sony - // 100 : Pansonic - // 101 : CPT - , 1, // Reserved ; C0h.7 - BST0, 8, // Battery Status ; C1h - // Bit0 : Discharging - // Bit1 : Charging - // Bit2 : Discharg and Critical Low - // Bit3-7 : Reserved - BRC0, 16, // Batt Remaining Capacity ; C2h, C3h - BSN0, 16, // Batt Serial Number ; C4h, C5h - BPV0, 16, // Batt Present Voltage ; C6h, C7h - BDV0, 16, // Batt Design Voltage ; C8h, C9h - BDC0, 16, // Batt Design Capacity ; CAh, CBh - BFC0, 16, // Batt Last Full Charge Capacity ; CCh, CDh - GAU0, 8, // Batt Gasgauge ; CEh - CYC0, 8, // Batt Cycle Counter ; CFh - BPC0, 16, // Batt Current ; D0h, D1h - BAC0, 16, // Batt Average Current ; D2h, D3h - BTW0, 8, // Batt Comsuption ; D4h - BVL0, 8, // Batt Battery Volt ; D5h - BTM0, 8, // Batt Battery Temp ; D6h - BAT0, 8, // Batt Average Temp (Degree C) ; D7h - BCG0, 16, // Batt charge current ; D8h, D9h - BCT0, 8, // Batt Current Temp Semple counter ; DAh - BCI0, 8, // BATT CMD Index for read BATT(SMB) ; DBh - BCM0, 8, // Count up to Communicate BATT ; DCh - BOT0, 8, // Count up if BATT over Temp ; DDh - BSSB, 16, // BATT Battery Status SMB ; DEh, DFh - BOV0, 8, // BATT Over Voltage Count ; E0h - BCF0, 8, // BATT Communication Fail Counter ; E1h - BAD0, 8, // Battery Voltage of ADC ; E2h - BCV1, 16, // Cell Voltage 1 (mV) ; E3h, E4h - BCV2, 16, // Cell Voltage 2 (mV) ; E5h, E6h - BCV3, 16, // Cell Voltage 3 (mV) ; E7h, E8h - BCV4, 16, // Cell Voltage 4 (mV) ; E9h, EAh + BTY0, 1, // Batt Type (0=NiMh, 1=LiIon) ; C0h.0 + BAM0, 1, // Battery mode (0=mA, 1=mW) ; C0h.1 + BAL0, 1, // Low Battery ; C0h.2 + , 1, // Reserved ; C0h.3 + BMF0, 3, // Battery Manufacturer ; C0h.4-6 + // 001 : Sanyo + // 010 : Sony + // 100 : Pansonic + // 101 : CPT + , 1, // Reserved ; C0h.7 + BST0, 8, // Battery Status ; C1h + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharg and Critical Low + // Bit3-7 : Reserved + BRC0, 16, // Batt Remaining Capacity ; C2h, C3h + BSN0, 16, // Batt Serial Number ; C4h, C5h + BPV0, 16, // Batt Present Voltage ; C6h, C7h + BDV0, 16, // Batt Design Voltage ; C8h, C9h + BDC0, 16, // Batt Design Capacity ; CAh, CBh + BFC0, 16, // Batt Last Full Charge Capacity ; CCh, CDh + GAU0, 8, // Batt Gasgauge ; CEh + CYC0, 8, // Batt Cycle Counter ; CFh + BPC0, 16, // Batt Current ; D0h, D1h + BAC0, 16, // Batt Average Current ; D2h, D3h + BTW0, 8, // Batt Comsuption ; D4h + BVL0, 8, // Batt Battery Volt ; D5h + BTM0, 8, // Batt Battery Temp ; D6h + BAT0, 8, // Batt Average Temp (Degree C) ; D7h + BCG0, 16, // Batt charge current ; D8h, D9h + BCT0, 8, // Batt Current Temp Semple counter ; DAh + BCI0, 8, // BATT CMD Index for read BATT(SMB) ; DBh + BCM0, 8, // Count up to Communicate BATT ; DCh + BOT0, 8, // Count up if BATT over Temp ; DDh + BSSB, 16, // BATT Battery Status SMB ; DEh, DFh + BOV0, 8, // BATT Over Voltage Count ; E0h + BCF0, 8, // BATT Communication Fail Counter ; E1h + BAD0, 8, // Battery Voltage of ADC ; E2h + BCV1, 16, // Cell Voltage 1 (mV) ; E3h, E4h + BCV2, 16, // Cell Voltage 2 (mV) ; E5h, E6h + BCV3, 16, // Cell Voltage 3 (mV) ; E7h, E8h + BCV4, 16, // Cell Voltage 4 (mV) ; E9h, EAh Offset(0xF4), - BMD0, 16, // Manufacture Date ; F4h, F5h - // Batt Day ; BIT[4:0] (Day) - // Batt Month ; BIT[9:5] (Month) - // Batt Year ; BIT[15:10] (Year) - BACV, 16, // Charging Voltage ; F6h, F7h - BDN0, 8, // Battery Cell Number ; F8h - , 8 // Last byte for Reserved. + BMD0, 16, // Manufacture Date ; F4h, F5h + // Batt Day ; BIT[4:0] (Day) + // Batt Month ; BIT[9:5] (Month) + // Batt Year ; BIT[15:10] (Year) + BACV, 16, // Charging Voltage ; F6h, F7h + BDN0, 8, // Battery Cell Number ; F8h + , 8 // Last byte for Reserved. }
Method (_CRS, 0, NotSerialized) @@ -286,25 +286,25 @@ Device (EC0) * DTS temperature update 10h * Decrease brightness event 11h * Increase brightness event 12h - * Cover lid open 15h - * Cover lid close 16h + * Cover lid open 15h + * Cover lid close 16h * External device plugged 17h * External device removed 18h * Bluetooth wake up event 19h - * Scr expand event 1Bh - * Display toggle 1Ch - * CPU fast/slow event 1Dh + * Scr expand event 1Bh + * Display toggle 1Ch + * CPU fast/slow event 1Dh * Battery in critical low 22h - * Battery in low state 23h - * Battery pack plug in 25h - * Docking in 2Ah - * Undock 2Bh - * Power button pressed 32h - * AC plug in 37h - * AC removed 38h - * Modem ring in 3Ah - * PME signal active 3Eh - * Hotkey make Function 45h + * Battery in low state 23h + * Battery pack plug in 25h + * Docking in 2Ah + * Undock 2Bh + * Power button pressed 32h + * AC plug in 37h + * AC removed 38h + * Modem ring in 3Ah + * PME signal active 3Eh + * Hotkey make Function 45h * Hotkey break Function 46h */
diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 3f4d1b9..ad485d0 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -41,7 +41,7 @@ static int kbc_input_buffer_empty(void)
if (!timeout) { printk(BIOS_WARNING, - "Unexpected Keyboard controller input buffer full\n"); + "Unexpected Keyboard controller input buffer full\n"); } return !!timeout; } @@ -157,13 +157,13 @@ static void ene932_enable_resources(device_t dev) }
static struct device_operations ops = { - .init = ene932_init, + .init = ene932_init, .read_resources = ene932_read_resources, .enable_resources = ene932_enable_resources };
static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } };
static void enable_dev(device_t dev) diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h index 879925f..11a641e 100644 --- a/src/ec/compal/ene932/ec.h +++ b/src/ec/compal/ene932/ec.h @@ -30,19 +30,19 @@ #define EC_IO_DATA EC_IO + 3
/* ENE EC internal address space */ -#define REG_SPI_DATA 0xfeab +#define REG_SPI_DATA 0xfeab #define REG_SPI_COMMAND 0xfeac #define REG_SPI_CONFIG 0xfead -#define CFG_CSn_FORCE_LOW (1 << 4) +#define CFG_CSn_FORCE_LOW (1 << 4) #define CFG_COMMAND_WRITE_ENABLE (1 << 3) -#define CFG_STATUS (1 << 1) +#define CFG_STATUS (1 << 1)
#define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
/* Wait 400ms for keyboard controller answers */ diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 342db3e..05a8eb1 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -21,7 +21,7 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP default 0x1e
config EC_GOOGLE_CHROMEEC_LPC - depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y help Google Chrome EC via LPC bus. diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 341911c..cb0fa59 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -37,10 +37,10 @@ Device (BAT0) 0xFFFFFFFF, // 0x06: Design Capacity of Low 0x00000001, // 0x07: Capacity Granularity 1 0x00000001, // 0x08: Capacity Granularity 2 - "", // 0x09: Model Number - "", // 0x0a: Serial Number + "", // 0x09: Model Number + "", // 0x0a: Serial Number "LION", // 0x0b: Battery Type - "" // 0x0c: OEM Information + "" // 0x0c: OEM Information })
Name (PBIX, Package () { @@ -60,10 +60,10 @@ Device (BAT0) 0xFFFFFFFF, // 0x0d: Min Averaging Interval 0x00000001, // 0x0e: Capacity Granularity 1 0x00000001, // 0x0f: Capacity Granularity 2 - "", // 0x10 Model Number - "", // 0x11: Serial Number + "", // 0x10 Model Number + "", // 0x11: Serial Number "LION", // 0x12: Battery Type - "" // 0x13: OEM Information + "" // 0x13: OEM Information })
Name (PBST, Package () { @@ -213,7 +213,7 @@ Device (BAT0) // See if within ~3% of full ShiftRight (Local2, 5, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + LLess (Local1, Add (Local2, Local3)))) { Store (Local2, Local1) } diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 39ddd29..851bdfe 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -22,15 +22,15 @@ * * Constants that should be defined: * - * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources - * EC_LPC_ADDR_MEMMAP : Base address of memory map range - * EC_MEMMAP_SIZE : Size of memory map range + * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources + * EC_LPC_ADDR_MEMMAP : Base address of memory map range + * EC_MEMMAP_SIZE : Size of memory map range * - * SIO_EC_HOST_ENABLE : Enable EC host command interface resources + * SIO_EC_HOST_ENABLE : Enable EC host command interface resources * EC_LPC_ADDR_HOST_DATA : EC host command interface data port - * EC_LPC_ADDR_HOST_CMD : EC host command interface command port - * EC_HOST_CMD_REGION0 : EC host command buffer - * EC_HOST_CMD_REGION1 : EC host command buffer + * EC_LPC_ADDR_HOST_CMD : EC host command interface command port + * EC_HOST_CMD_REGION0 : EC host command buffer + * EC_HOST_CMD_REGION1 : EC host command buffer * EC_HOST_CMD_REGION_SIZE : EC host command buffer size */
diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 42c7c2e..7cca2fe 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -36,7 +36,7 @@ * @param len Length of data. */ static void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, - int len) + int len) { int i;
@@ -91,7 +91,7 @@ static int create_proto3_request(const struct chromeec_command *cec_command, /* Fail if output size is too big */ if (out_bytes > sizeof(*cmd)) { printk(BIOS_ERR, "%s: Cannot send %d bytes\n", __func__, - cec_command->cmd_size_in); + cec_command->cmd_size_in); return -EC_RES_REQUEST_TRUNCATED; }
@@ -132,7 +132,7 @@ static int prepare_proto3_response_buffer( /* Fail if input size is too big */ if (in_bytes > sizeof(*resp)) { printk(BIOS_ERR, "%s: Cannot receive %d bytes\n", __func__, - cec_command->cmd_size_out); + cec_command->cmd_size_out); return -EC_RES_RESPONSE_TOO_BIG; }
@@ -184,7 +184,7 @@ static int handle_proto3_response(struct ec_response_v3 *resp, csum = cros_ec_calc_checksum((const uint8_t *)resp, in_bytes); if (csum) { printk(BIOS_ERR, "%s: EC response checksum invalid: 0x%02x\n", - __func__, csum); + __func__, csum); return -EC_RES_INVALID_CHECKSUM; }
@@ -196,7 +196,7 @@ static int handle_proto3_response(struct ec_response_v3 *resp, /* Return error result, if any */ if (rs->result) { printk(BIOS_ERR, "%s: EC response with error code: %d\n", - __func__, rs->result); + __func__, rs->result); return -(int)rs->result; }
@@ -204,7 +204,7 @@ static int handle_proto3_response(struct ec_response_v3 *resp, }
static int send_command_proto3(struct chromeec_command *cec_command, - crosec_io_t crosec_io, void *context) + crosec_io_t crosec_io, void *context) { int out_bytes, in_bytes; int rv; @@ -224,10 +224,10 @@ static int send_command_proto3(struct chromeec_command *cec_command, }
rv = crosec_io((uint8_t *)&cmd, out_bytes, (uint8_t *)&resp, in_bytes, - context); + context); if (rv != 0) { printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.", - __func__, rv >= 0 ? rv : -rv); + __func__, rv >= 0 ? rv : -rv); return -EC_RES_ERROR; }
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 7546a82..dbd2e6a 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -58,7 +58,7 @@ int google_chromeec_kbbacklight(int percent) cec_cmd.cmd_size_out = sizeof(rsp_backlight); google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n", - rsp_backlight.percent, cec_cmd.cmd_code); + rsp_backlight.percent, cec_cmd.cmd_code); return cec_cmd.cmd_code;
} @@ -137,7 +137,7 @@ void google_chromeec_early_init(void) #ifndef __PRE_RAM__
int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, - uint8_t *buffer, int len, int is_read) + uint8_t *buffer, int len, int is_read) { union { struct ec_params_i2c_passthru p; @@ -209,7 +209,7 @@ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, /* Parse response */ if (r->i2c_status & EC_I2C_STATUS_ERROR) { printk(BIOS_ERR, "Transfer failed with status=0x%x\n", - r->i2c_status); + r->i2c_status); return -1; }
@@ -299,7 +299,7 @@ void google_chromeec_log_events(u32 mask) /* Log the last post code only if it is abornmal */ if (code > 0 && code != POST_OS_BOOT && code != POST_OS_RESUME) printk(BIOS_DEBUG, "Chrome EC: Last POST code was 0x%02x\n", - code); + code);
while ((event = google_chromeec_get_event()) != 0) { if (EC_HOST_EVENT_MASK(event) & mask) @@ -360,7 +360,7 @@ int google_chromeec_hello(void) cec_cmd.cmd_size_out = sizeof(rsp_hello.out_data); google_chromeec_command(&cec_cmd); printk(BIOS_DEBUG, "Google Chrome EC: Hello got back %x status (%x)\n", - rsp_hello.out_data, cec_cmd.cmd_code); + rsp_hello.out_data, cec_cmd.cmd_code); return cec_cmd.cmd_code; }
@@ -384,13 +384,13 @@ void google_chromeec_init(void)
if (cec_cmd.cmd_code) { printk(BIOS_DEBUG, - "Google Chrome EC: version command failed!\n"); + "Google Chrome EC: version command failed!\n"); } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); + printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", - cec_resp.current_image); + cec_resp.current_image); ec_image_type = cec_resp.current_image; }
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f661d31..8f9a33f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -26,7 +26,7 @@
#ifndef __PRE_RAM__ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, - uint8_t *buffer, int len, int is_read); + uint8_t *buffer, int len, int is_read); u32 google_chromeec_get_wake_mask(void); int google_chromeec_set_sci_mask(u32 mask); int google_chromeec_set_smi_mask(u32 mask); @@ -58,7 +58,7 @@ struct chromeec_command { uint16_t cmd_code; /* command code in, status out */ uint8_t cmd_version; /* command version */ const void* cmd_data_in; /* command data, if any */ - void* cmd_data_out; /* command response, if any */ + void* cmd_data_out; /* command response, if any */ uint16_t cmd_size_in; /* size of command data */ uint16_t cmd_size_out; /* expected size of command response in, * actual received size out */ diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index baf16d3..b0bdc54 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -15,12 +15,12 @@ * response: ERR [ P0 P1 P2 ... Pn S ] * * where the bytes are defined as follow : - * - CMD is the command code. (defined by EC_CMD_ constants) - * - ERR is the error code. (defined by EC_RES_ constants) - * - Px is the optional payload. - * it is not sent if the error code is not success. - * (defined by ec_params_ and ec_response_ structures) - * - S is the checksum which is the sum of all payload bytes. + * - CMD is the command code. (defined by EC_CMD_ constants) + * - ERR is the error code. (defined by EC_RES_ constants) + * - Px is the optional payload. + * it is not sent if the error code is not success. + * (defined by ec_params_ and ec_response_ structures) + * - S is the checksum which is the sum of all payload bytes. * * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM. @@ -29,7 +29,7 @@
/* Current version of this protocol */ /* TODO: This is effectively useless; protocol is determined in other ways */ -#define EC_PROTO_VERSION 0x00000002 +#define EC_PROTO_VERSION 0x00000002
/* Command version mask */ #define EC_VER_MASK(version) (1UL << (version)) @@ -43,11 +43,11 @@ #define EC_LPC_ADDR_HOST_CMD 0x204
/* I/O addresses for host command args and params */ -#define EC_LPC_ADDR_HOST_ARGS 0x800 /* and 0x801, 0x802, 0x803 */ +#define EC_LPC_ADDR_HOST_ARGS 0x800 /* and 0x801, 0x802, 0x803 */ #define EC_LPC_ADDR_HOST_PARAM 0x804 #define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */ #define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */ -#define EC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */ +#define EC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff * and they tell the kernel that so we have to think of it as two parts. */ @@ -64,38 +64,38 @@ #define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */ #define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */
-#define EC_LPC_ADDR_MEMMAP 0x900 -#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ +#define EC_LPC_ADDR_MEMMAP 0x900 +#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */ #define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
/* The offset address of each type of data in mapped memory. */ -#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */ -#define EC_MEMMAP_FAN 0x10 /* Fan speeds */ -#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */ -#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */ -#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ +#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */ +#define EC_MEMMAP_FAN 0x10 /* Fan speeds */ +#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */ +#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */ +#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */ #define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */ #define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */ #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */ #define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */ #define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */ -#define EC_MEMMAP_SWITCHES 0x30 -#define EC_MEMMAP_HOST_EVENTS 0x34 -#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ -#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ -#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ -#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */ -#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ -#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ -#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ -#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ -#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ -#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ -#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ -#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */ +#define EC_MEMMAP_SWITCHES 0x30 +#define EC_MEMMAP_HOST_EVENTS 0x34 +#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */ +#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */ +#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */ +#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */ +#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */ +#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */ +#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */ +#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */ +#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */ +#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */ +#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */ +#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */ -#define EC_TEMP_SENSOR_ENTRIES 16 +#define EC_TEMP_SENSOR_ENTRIES 16 /* * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B. * @@ -103,36 +103,36 @@ */ #define EC_TEMP_SENSOR_B_ENTRIES 8 #define EC_TEMP_SENSOR_NOT_PRESENT 0xff -#define EC_TEMP_SENSOR_ERROR 0xfe +#define EC_TEMP_SENSOR_ERROR 0xfe #define EC_TEMP_SENSOR_NOT_POWERED 0xfd #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc /* * The offset of temperature value stored in mapped memory. This allows * reporting a temperature range of 200K to 454K = -73C to 181C. */ -#define EC_TEMP_SENSOR_OFFSET 200 +#define EC_TEMP_SENSOR_OFFSET 200
-#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ +#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */ #define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */ -#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */ +#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */ -#define EC_BATT_FLAG_AC_PRESENT 0x01 +#define EC_BATT_FLAG_AC_PRESENT 0x01 #define EC_BATT_FLAG_BATT_PRESENT 0x02 #define EC_BATT_FLAG_DISCHARGING 0x04 -#define EC_BATT_FLAG_CHARGING 0x08 +#define EC_BATT_FLAG_CHARGING 0x08 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
/* Switch flags at EC_MEMMAP_SWITCHES */ -#define EC_SWITCH_LID_OPEN 0x01 -#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 +#define EC_SWITCH_LID_OPEN 0x01 +#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04 /* Was recovery requested via keyboard; now unused. */ #define EC_SWITCH_IGNORE1 0x08 /* Recovery requested via dedicated signal (from servo board) */ -#define EC_SWITCH_DEDICATED_RECOVERY 0x10 +#define EC_SWITCH_DEDICATED_RECOVERY 0x10 /* Was fake developer mode switch; now unused. Remove in next refactor. */ -#define EC_SWITCH_IGNORE0 0x20 +#define EC_SWITCH_IGNORE0 0x20
/* Host command interface flags */ /* Host command interface supports LPC args (LPC interface only) */ @@ -141,9 +141,9 @@ #define EC_HOST_CMD_FLAG_VERSION_3 0x02
/* Wireless switch flags */ -#define EC_WIRELESS_SWITCH_WLAN 0x01 +#define EC_WIRELESS_SWITCH_WLAN 0x01 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 -#define EC_WIRELESS_SWITCH_WWAN 0x04 +#define EC_WIRELESS_SWITCH_WWAN 0x04
/* * This header file is used in coreboot both in C and ACPI code. The ACPI code @@ -162,13 +162,13 @@
/* LPC command status byte masks */ /* EC has written a byte in the data register and host hasn't read it yet */ -#define EC_LPC_STATUS_TO_HOST 0x01 +#define EC_LPC_STATUS_TO_HOST 0x01 /* Host has written a command/data byte and the EC hasn't read it yet */ -#define EC_LPC_STATUS_FROM_HOST 0x02 +#define EC_LPC_STATUS_FROM_HOST 0x02 /* EC is processing a command */ #define EC_LPC_STATUS_PROCESSING 0x04 /* Last write to EC was a command, not data */ -#define EC_LPC_STATUS_LAST_CMD 0x08 +#define EC_LPC_STATUS_LAST_CMD 0x08 /* EC is in burst mode. Unsupported by Chrome EC, so this bit is never set */ #define EC_LPC_STATUS_BURST_MODE 0x10 /* SCI event is pending (requesting SCI query) */ @@ -176,7 +176,7 @@ /* SMI event is pending (requesting SMI query) */ #define EC_LPC_STATUS_SMI_PENDING 0x40 /* (reserved) */ -#define EC_LPC_STATUS_RESERVED 0x80 +#define EC_LPC_STATUS_RESERVED 0x80
/* * EC is busy. This covers both the EC processing a command, and the host has @@ -199,9 +199,9 @@ enum ec_status { EC_RES_UNAVAILABLE = 9, /* No response available */ EC_RES_TIMEOUT = 10, /* We got a timeout */ EC_RES_OVERFLOW = 11, /* Table / data overflow */ - EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ + EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */ EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */ - EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */ + EC_RES_RESPONSE_TOO_BIG = 14 /* Response was too big to handle */ };
/* @@ -396,7 +396,7 @@ struct ec_response_get_version { /* Null-terminated version strings for RO, RW */ char version_string_ro[32]; char version_string_rw[32]; - char reserved[32]; /* Was previously RW-B string */ + char reserved[32]; /* Was previously RW-B string */ uint32_t current_image; /* One of ec_current_image */ } __packed;
@@ -405,7 +405,7 @@ struct ec_response_get_version {
struct ec_params_read_test { uint32_t offset; /* Starting value for read buffer */ - uint32_t size; /* Size to read in bytes */ + uint32_t size; /* Size to read in bytes */ } __packed;
struct ec_response_read_test { @@ -448,14 +448,14 @@ struct ec_response_board_version {
struct ec_params_read_memmap { uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */ - uint8_t size; /* Size to read in bytes */ + uint8_t size; /* Size to read in bytes */ } __packed;
/* Read versions supported for a command */ #define EC_CMD_GET_CMD_VERSIONS 0x08
struct ec_params_get_cmd_versions { - uint8_t cmd; /* Command to check */ + uint8_t cmd; /* Command to check */ } __packed;
struct ec_response_get_cmd_versions { @@ -520,7 +520,7 @@ struct ec_response_flash_info {
struct ec_params_flash_read { uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ + uint32_t size; /* Size to read in bytes */ } __packed;
/* Write flash */ @@ -528,7 +528,7 @@ struct ec_params_flash_read {
struct ec_params_flash_write { uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ + uint32_t size; /* Size to write in bytes */ /* * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to * use a power of 2 so writes stay aligned. @@ -541,7 +541,7 @@ struct ec_params_flash_write {
struct ec_params_flash_erase { uint32_t offset; /* Byte offset to erase */ - uint32_t size; /* Size to erase in bytes */ + uint32_t size; /* Size to erase in bytes */ } __packed;
/* @@ -559,18 +559,18 @@ struct ec_params_flash_erase {
/* Flags for flash protection */ /* RO flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) +#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0) /* * RO flash code protected now. If this bit is set, at-boot status cannot * be changed. */ -#define EC_FLASH_PROTECT_RO_NOW (1 << 1) +#define EC_FLASH_PROTECT_RO_NOW (1 << 1) /* Entire flash code protected now, until reboot. */ -#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) +#define EC_FLASH_PROTECT_ALL_NOW (1 << 2) /* Flash write protect GPIO is asserted now */ -#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) +#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3) /* Error - at least one bank of flash is stuck locked, and cannot be unlocked */ -#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) +#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4) /* * Error - flash protection is in inconsistent state. At least one bank of * flash which should be protected is not protected. Usually fixed by @@ -578,10 +578,10 @@ struct ec_params_flash_erase { */ #define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5) /* Entile flash code protected when the EC boots */ -#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6) +#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6)
struct ec_params_flash_protect { - uint32_t mask; /* Bits in flags to apply */ + uint32_t mask; /* Bits in flags to apply */ uint32_t flags; /* New flags to apply */ } __packed;
@@ -738,7 +738,7 @@ struct lightbar_params { } __packed;
struct ec_params_lightbar { - uint8_t cmd; /* Command (see enum lightbar_command) */ + uint8_t cmd; /* Command (see enum lightbar_command) */ union { struct { /* no args */ @@ -826,7 +826,7 @@ enum ec_led_colors {
struct ec_params_led_control { uint8_t led_id; /* Which LED to control */ - uint8_t flags; /* Control flags */ + uint8_t flags; /* Control flags */
uint8_t brightness[EC_LED_COLOR_COUNT]; } __packed; @@ -854,27 +854,27 @@ struct ec_response_led_control { #define EC_CMD_VBOOT_HASH 0x2A
struct ec_params_vboot_hash { - uint8_t cmd; /* enum ec_vboot_hash_cmd */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t nonce_size; /* Nonce size; may be 0 */ - uint8_t reserved0; /* Reserved; set 0 */ - uint32_t offset; /* Offset in flash to hash */ - uint32_t size; /* Number of bytes to hash */ + uint8_t cmd; /* enum ec_vboot_hash_cmd */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t nonce_size; /* Nonce size; may be 0 */ + uint8_t reserved0; /* Reserved; set 0 */ + uint32_t offset; /* Offset in flash to hash */ + uint32_t size; /* Number of bytes to hash */ uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */ } __packed;
struct ec_response_vboot_hash { - uint8_t status; /* enum ec_vboot_hash_status */ - uint8_t hash_type; /* enum ec_vboot_hash_type */ - uint8_t digest_size; /* Size of hash digest in bytes */ - uint8_t reserved0; /* Ignore; will be 0 */ - uint32_t offset; /* Offset in flash which was hashed */ - uint32_t size; /* Number of bytes hashed */ + uint8_t status; /* enum ec_vboot_hash_status */ + uint8_t hash_type; /* enum ec_vboot_hash_type */ + uint8_t digest_size; /* Size of hash digest in bytes */ + uint8_t reserved0; /* Ignore; will be 0 */ + uint32_t offset; /* Offset in flash which was hashed */ + uint32_t size; /* Number of bytes hashed */ uint8_t hash_digest[64]; /* Hash digest data */ } __packed;
enum ec_vboot_hash_cmd { - EC_VBOOT_HASH_GET = 0, /* Get current hash status */ + EC_VBOOT_HASH_GET = 0, /* Get current hash status */ EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */ EC_VBOOT_HASH_START = 2, /* Start computing a new hash */ EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */ @@ -934,7 +934,7 @@ struct ec_response_pstore_info {
struct ec_params_pstore_read { uint32_t offset; /* Byte offset to read */ - uint32_t size; /* Size to read in bytes */ + uint32_t size; /* Size to read in bytes */ } __packed;
/* Write persistent storage */ @@ -942,7 +942,7 @@ struct ec_params_pstore_read {
struct ec_params_pstore_write { uint32_t offset; /* Byte offset to write */ - uint32_t size; /* Size to write in bytes */ + uint32_t size; /* Size to write in bytes */ uint8_t data[EC_PSTORE_SIZE_MAX]; } __packed;
@@ -1203,7 +1203,7 @@ struct ec_response_host_event_mask { } __packed;
/* These all use ec_response_host_event_mask */ -#define EC_CMD_HOST_EVENT_GET_B 0x87 +#define EC_CMD_HOST_EVENT_GET_B 0x87 #define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x88 #define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x89 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x8d @@ -1211,9 +1211,9 @@ struct ec_response_host_event_mask { /* These all use ec_params_host_event_mask */ #define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x8a #define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x8b -#define EC_CMD_HOST_EVENT_CLEAR 0x8c +#define EC_CMD_HOST_EVENT_CLEAR 0x8c #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x8e -#define EC_CMD_HOST_EVENT_CLEAR_B 0x8f +#define EC_CMD_HOST_EVENT_CLEAR_B 0x8f
/*****************************************************************************/ /* Switch commands */ @@ -1486,11 +1486,11 @@ struct ec_params_sb_wr_block {
/* Command */ enum ec_reboot_cmd { - EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ - EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ - EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */ + EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */ + EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */ + EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */ /* (command 3 was jump to RW-B) */ - EC_REBOOT_COLD = 4, /* Cold-reboot */ + EC_REBOOT_COLD = 4, /* Cold-reboot */ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */ EC_REBOOT_HIBERNATE = 6 /* Hibernate EC */ }; @@ -1500,8 +1500,8 @@ enum ec_reboot_cmd { #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */
struct ec_params_reboot_ec { - uint8_t cmd; /* enum ec_reboot_cmd */ - uint8_t flags; /* See EC_REBOOT_FLAG_* */ + uint8_t cmd; /* enum ec_reboot_cmd */ + uint8_t flags; /* See EC_REBOOT_FLAG_* */ } __packed;
/* @@ -1560,12 +1560,12 @@ struct ec_params_reboot_ec {
/* Valid addresses in ACPI memory space, for read/write commands */ /* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */ -#define EC_ACPI_MEM_VERSION 0x00 +#define EC_ACPI_MEM_VERSION 0x00 /* * Test location; writing value here updates test compliment byte to (0xff - * value). */ -#define EC_ACPI_MEM_TEST 0x01 +#define EC_ACPI_MEM_TEST 0x01 /* Test compliment; writes here are ignored. */ #define EC_ACPI_MEM_TEST_COMPLIMENT 0x02 /* Keyboard backlight brightness percent (0 - 100) */ diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index a13dde6..5888441 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -57,7 +57,7 @@ static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) { #ifdef TRACE_CHROMEEC printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, - size); + size); while (size-- > 0) { printk(BIOS_INFO, "%02X ", *data++); } @@ -73,7 +73,7 @@ static int ec_verify_checksum(const EcResponseI2c *resp) uint8_t received = resp->data[resp->length]; if (calculated != received) { printk(BIOS_ERR, "%s: Unmatch (rx: %#02x, calc: %#02x)\n", - __func__, received, calculated); + __func__, received, calculated); return 0; } return 1; @@ -93,15 +93,15 @@ int google_chromeec_command(struct chromeec_command *cec_command) int bus = CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS; int chip = CONFIG_EC_GOOGLE_CHROMEEC_I2C_CHIP; size_t size_i2c_cmd = (sizeof(cmd) - sizeof(cmd.data) + - cec_command->cmd_size_in + 1), - size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + + cec_command->cmd_size_in + 1), + size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + cec_command->cmd_size_out + 1);
if (cec_command->cmd_size_in > MAX_I2C_DATA_SIZE || cec_command->cmd_size_out > MAX_I2C_DATA_SIZE) { printk(BIOS_ERR, "%s: Command data size too large (%d,%d)\n", - __func__, cec_command->cmd_size_in, - cec_command->cmd_size_out); + __func__, cec_command->cmd_size_in, + cec_command->cmd_size_out); cec_command->cmd_code = EC_RES_INVALID_PARAM; return 1; } @@ -117,13 +117,13 @@ int google_chromeec_command(struct chromeec_command *cec_command) i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) { printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", - __func__, bus, chip); + __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; return 1; } if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) { printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", - __func__, bus, chip); + __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; return 1; } @@ -132,12 +132,12 @@ int google_chromeec_command(struct chromeec_command *cec_command) cec_command->cmd_code = resp.response; if (resp.response != EC_RES_SUCCESS) { printk(BIOS_DEBUG, "%s: Received bad result code %d\n", - __func__, (int)resp.response); + __func__, (int)resp.response); return 1; } if (resp.length > cec_command->cmd_size_out) { printk(BIOS_ERR, "%s: Received len %#02x too large\n", - __func__, (int)resp.length); + __func__, (int)resp.length); cec_command->cmd_code = EC_RES_INVALID_RESPONSE; return 1; } diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index a445da8..6c49abf 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -41,7 +41,7 @@ static int google_chromeec_wait_ready(u16 port) #define MAX_EC_TIMEOUT_US 1000000
while (ec_status & - (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { + (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { udelay(1); if (time_count++ == MAX_EC_TIMEOUT_US) return -1; @@ -85,7 +85,7 @@ int google_chromeec_command(struct chromeec_command *cec_command)
if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", - cec_command->cmd_code); + cec_command->cmd_code); return 1; }
@@ -157,7 +157,7 @@ static void lpc_ec_enable_resources(device_t dev) }
static struct device_operations ops = { - .init = lpc_ec_init, + .init = lpc_ec_init, .read_resources = lpc_ec_read_resources, .enable_resources = lpc_ec_enable_resources }; diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 5525e31..da60fb6 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -33,7 +33,7 @@ static int crosec_spi_io(uint8_t *write_bytes, size_t write_size,
spi_claim_bus(slave); rv = spi_xfer(slave, write_bytes, write_size * 8, read_bytes, - read_size * 8); + read_size * 8); spi_release_bus(slave);
if (rv != 0) { diff --git a/src/ec/kontron/it8516e/acpi/ec.asl b/src/ec/kontron/it8516e/acpi/ec.asl index bdae967..22bb111 100644 --- a/src/ec/kontron/it8516e/acpi/ec.asl +++ b/src/ec/kontron/it8516e/acpi/ec.asl @@ -53,8 +53,8 @@ Device(IT8516E_EC_DEV) { OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) Field (CREG, ByteAcc, NoLock, Preserve) { - ADDR, 8, - DATA, 8 + ADDR, 8, + DATA, 8 } IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) { diff --git a/src/ec/kontron/it8516e/ec.c b/src/ec/kontron/it8516e/ec.c index 925b7ea..a739ac3 100644 --- a/src/ec/kontron/it8516e/ec.c +++ b/src/ec/kontron/it8516e/ec.c @@ -161,30 +161,30 @@ static void it8516e_set_fan_from_options(const config_t *const config, switch (fan_mode) { case IT8516E_MODE_AUTO: printk(BIOS_DEBUG, - "Setting it8516e fan%d " - "control to auto.\n", - fan_idx + 1); + "Setting it8516e fan%d " + "control to auto.\n", + fan_idx + 1); break; case IT8516E_MODE_PWM: printk(BIOS_DEBUG, - "Setting it8516e fan%d " - "control to %d%% PWM.\n", - fan_idx + 1, fan_target); + "Setting it8516e fan%d " + "control to %d%% PWM.\n", + fan_idx + 1, fan_target); if (fan_target > 100) /* Constrain to 100% */ fan_target = 100; it8516e_set_fan_pwm(fan_idx, (fan_target * 255) / 100); break; case IT8516E_MODE_SPEED: printk(BIOS_DEBUG, - "Setting it8516e fan%d " - "control to %d RPMs.\n", - fan_idx + 1, fan_target); + "Setting it8516e fan%d " + "control to %d RPMs.\n", + fan_idx + 1, fan_target); it8516e_set_fan_speed(fan_idx, fan_target); break; case IT8516E_MODE_THERMAL: printk(BIOS_DEBUG, - "Setting it8516e fan%d control to %d C.\n", - fan_idx + 1, fan_target); + "Setting it8516e fan%d control to %d C.\n", + fan_idx + 1, fan_target); if (fan_target > 1024) /* Constrain to 1K */ fan_target = 1024; it8516e_set_fan_temperature(fan_idx, fan_target * 64); @@ -199,13 +199,13 @@ static void it8516e_set_fan_from_options(const config_t *const config, if (fan_min >= 100) /* Constrain fan_min to 99% */ fan_min = 99; if (fan_max <= fan_min) /* If fan_min is the higher of the two, - it's safer for the hardware to keep - its value. Therefore, update fan_max. */ + it's safer for the hardware to keep + its value. Therefore, update fan_max. */ fan_max = fan_min + 1;
printk(BIOS_DEBUG, - "Setting it8516e fan%d limits to %d%% - %d%% PWM.\n", - fan_idx + 1, fan_min, fan_max); + "Setting it8516e fan%d limits to %d%% - %d%% PWM.\n", + fan_idx + 1, fan_min, fan_max); it8516e_set_fan_limits(fan_idx, fan_min, fan_max); break; } @@ -232,23 +232,23 @@ static void it8516e_pm2_init(const device_t dev)
static struct device_operations it8516e_pm2_ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = it8516e_pm2_init + .enable = pnp_enable, + .init = it8516e_pm2_init };
static struct pnp_info it8516e_dev_infos[] = { - { NULL, IT8516E_LDN_UART1, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, - { NULL, IT8516E_LDN_UART2, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, - { NULL, IT8516E_LDN_SWUC, PNP_IO0 | PNP_IRQ0, { 0xff7e0, }, }, - { NULL, IT8516E_LDN_MOUSE, PNP_IRQ0, }, - { NULL, IT8516E_LDN_KBD, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, - { NULL, IT8516E_LDN_SMFI, PNP_IO0 | PNP_IRQ0, { 0xfff0, }, }, - { NULL, IT8516E_LDN_BRAM, PNP_IO0 | PNP_IO1, { 0xfffe, }, { 0xfffe, }, }, - { NULL, IT8516E_LDN_PM1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, - { &it8516e_pm2_ops, IT8516E_LDN_PM2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, - { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, + { NULL, IT8516E_LDN_UART1, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, + { NULL, IT8516E_LDN_UART2, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, + { NULL, IT8516E_LDN_SWUC, PNP_IO0 | PNP_IRQ0, { 0xff7e0, }, }, + { NULL, IT8516E_LDN_MOUSE, PNP_IRQ0, }, + { NULL, IT8516E_LDN_KBD, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, + { NULL, IT8516E_LDN_SMFI, PNP_IO0 | PNP_IRQ0, { 0xfff0, }, }, + { NULL, IT8516E_LDN_BRAM, PNP_IO0 | PNP_IO1, { 0xfffe, }, { 0xfffe, }, }, + { NULL, IT8516E_LDN_PM1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, + { &it8516e_pm2_ops, IT8516E_LDN_PM2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, + { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, };
static void it8516e_enable(const device_t dev) diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 7dd49fe..122ec67 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -31,7 +31,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve) B1ST, 4, /* Battery 1 state */ , 1, B1CH, 1, /* Battery 1 charging, */ - B1DI, 1, /* Battery 1 discharging,*/ + B1DI, 1, /* Battery 1 discharging,*/ B1PR, 1 /* Battery 1 present */ }
@@ -157,7 +157,7 @@ Method(BINF, 2, NotSerialized) Divide (Local2, 20, Local0, Index(Arg0, 5)) // Warning capacity
Store (BASN, Local0) - Name (SERN, Buffer (0x06) { " " }) + Name (SERN, Buffer (0x06) { " " }) Store (4, Local1) While (Local0) { diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index f2a8061..e6de33c 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -39,21 +39,21 @@ Device(EC) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset (0x02), - DKR1, 1, /* Dock register 1 */ + DKR1, 1, /* Dock register 1 */ Offset (0x05), HSPA, 1, Offset (0x0C), LEDS, 8, /* LED state */ Offset (0x1a), - DKR2, 1, /* Dock register 2 */ + DKR2, 1, /* Dock register 2 */ Offset (0x2a), EVNT, 8, /* write will trigger EC event */ Offset (0x3a), AMUT, 1, /* Audio Mute */ Offset (0x3B), - , 1, + , 1, KBLT, 1, /* Keyboard Light */ - , 2, + , 2, USPW, 1, /* USB Power enable */ Offset (0x4e), WAKE, 16, @@ -63,8 +63,8 @@ Device(EC) Offset (0x81), PAGE, 8, /* Information Page Selector */ Offset (0xfe), - , 4, - DKR3, 1 /* Dock register 3 */ + , 4, + DKR3, 1 /* Dock register 3 */ }
Method (_CRS, 0) @@ -149,12 +149,12 @@ Device(EC)
Method(_Q2A, 0, NotSerialized) { - Notify(^LID, 0x80) + Notify(^LID, 0x80) }
Method(_Q2B, 0, NotSerialized) { - Notify(^LID, 0x80) + Notify(^LID, 0x80) }
@@ -259,39 +259,39 @@ Device(EC)
Device (HKEY) { - Name (_HID, EisaId ("IBM0068")) - Name (BTN, 0) - /* MASK */ - Name (DHKN, 0x080C) - /* Effective Mask */ - Name (EMSK, 0) - /* Device enabled. */ - Name (EN, 0) - Method (_STA, 0, NotSerialized) - { + Name (_HID, EisaId ("IBM0068")) + Name (BTN, 0) + /* MASK */ + Name (DHKN, 0x080C) + /* Effective Mask */ + Name (EMSK, 0) + /* Device enabled. */ + Name (EN, 0) + Method (_STA, 0, NotSerialized) + { Return (0x0F) - } - /* Retrieve event. */ - Method (MHKP, 0, NotSerialized) - { + } + /* Retrieve event. */ + Method (MHKP, 0, NotSerialized) + { Store (BTN, Local0) If (LEqual (Local0, Zero)) { - Return (Zero) + Return (Zero) } Store (Zero, BTN) Add (Local0, 0x1000, Local0) Return (Local0) - } - /* Report event */ - Method (RHK, 1, NotSerialized) { - ShiftLeft (One, Subtract (Arg0, 1), Local0) - If (And (EMSK, Local0)) { + } + /* Report event */ + Method (RHK, 1, NotSerialized) { + ShiftLeft (One, Subtract (Arg0, 1), Local0) + If (And (EMSK, Local0)) { Store (Arg0, BTN) Notify (HKEY, 0x80) - } - } - /* Enable/disable all events. */ - Method (MHKC, 1, NotSerialized) { + } + } + /* Enable/disable all events. */ + Method (MHKC, 1, NotSerialized) { If (Arg0) { Store (DHKN, EMSK) } @@ -300,35 +300,35 @@ Device(EC) Store (Zero, EMSK) } Store (Arg0, EN) - } - /* Enable/disable event. */ - Method (MHKM, 2, NotSerialized) { + } + /* Enable/disable event. */ + Method (MHKM, 2, NotSerialized) { If (LLessEqual (Arg0, 0x20)) { ShiftLeft (One, Subtract (Arg0, 1), Local0) If (Arg1) { - Or (DHKN, Local0, DHKN) + Or (DHKN, Local0, DHKN) } Else { - And (DHKN, Not (Local0), DHKN) + And (DHKN, Not (Local0), DHKN) } If (EN) { - Store (DHKN, EMSK) + Store (DHKN, EMSK) } } - } - /* Mask hotkey all. */ - Method (MHKA, 0, NotSerialized) - { + } + /* Mask hotkey all. */ + Method (MHKA, 0, NotSerialized) + { Return (0x07FFFFFF) - } - /* Version */ - Method (MHKV, 0, NotSerialized) - { + } + /* Version */ + Method (MHKV, 0, NotSerialized) + { Return (0x0100) - } + } }
#include "ac.asl" diff --git a/src/ec/lenovo/h8/acpi/lid.asl b/src/ec/lenovo/h8/acpi/lid.asl index 2dfa8d1..c4531ac 100644 --- a/src/ec/lenovo/h8/acpi/lid.asl +++ b/src/ec/lenovo/h8/acpi/lid.asl @@ -21,7 +21,7 @@
Field(ERAM, ByteAcc, NoLock, Preserve) { - Offset (0x32), + Offset (0x32), , 2, WKLD, 1, Offset (0x46), diff --git a/src/ec/lenovo/h8/acpi/sleepbutton.asl b/src/ec/lenovo/h8/acpi/sleepbutton.asl index 09e88aa..ffbe538 100644 --- a/src/ec/lenovo/h8/acpi/sleepbutton.asl +++ b/src/ec/lenovo/h8/acpi/sleepbutton.asl @@ -30,7 +30,7 @@ Field(ERAM, ByteAcc, NoLock, Preserve)
Device(SLPB) { - Name (_HID, EisaId ("PNP0C0E")) + Name (_HID, EisaId ("PNP0C0E")) Method(_PRW, 0, NotSerialized) { Return (Package() { 0x18, 0x03 }) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..dab128d 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -9,11 +9,11 @@ Scope(_TZ) Multiply(Arg0, 10, Local0) Add (Local0, 2732, Local0) if (LLessEqual(Local0, 2732)) { - Return (3000) + Return (3000) }
if (LGreater(Local0, 4012)) { - Return (3000) + Return (3000) } Return (Local0) } @@ -25,10 +25,10 @@ Scope(_TZ) } Method(_TMP) { #if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 - /* Avoid tripping alarm if ME isn't booted at all yet */ - If (LAnd (LNot (MEBT), LEqual (_SB.PCI0.LPCB.EC.TMP0, 128))) { - Return (C2K(40)) - } + /* Avoid tripping alarm if ME isn't booted at all yet */ + If (LAnd (LNot (MEBT), LEqual (_SB.PCI0.LPCB.EC.TMP0, 128))) { + Return (C2K(40)) + } Store (1, MEBT) #endif Return (C2K(_SB.PCI0.LPCB.EC.TMP0)) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index af2aab3..592c96a 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -73,7 +73,7 @@ static void h8_log_ec_version(void) fwvl = ec_read(0xe8);
printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); }
void h8_set_audio_mute(int mute) diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index 8fbd9bb..dc5916f 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -44,10 +44,10 @@ Device (BATX) 0x00000096, // 6 Design Capacity of Low 0x0000000A, // 7 Capacity Granularity 1 0x00000019, // 8 Capacity Granularity 2 - "", // 9 Model Number - "", // 10 Serial Number - "", // 11 Battery Type - "" // 12 OEM Information + "", // 9 Model Number + "", // 10 Serial Number + "", // 11 Battery Type + "" // 12 OEM Information })
Name (PBST, Package () { @@ -142,7 +142,7 @@ Device (BATX) // See if within ~3% of full ShiftRight (Local2, 5, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + LLess (Local1, Add (Local2, Local3)))) { Store (Local2, Local1) } diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 4e703fe..b844e17 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -37,87 +37,87 @@ Device (EC0) // EC Name Space Configuration
Offset(0x40), - BDC0, 16, // Batt Design Capacity ; 40h, 41h - BDV0, 16, // Batt Design Voltage ; 42h, 43h - BFC0, 16, // Batt Last Full Charge Capacity ; 44h, 45h - BPC0, 16, // Batt Current ; 46h, 47h - BRC0, 16, // Batt Remaining Capacity ; 48h, 49h - BPV0, 16, // Batt Present Voltage ; 4Ah, 4Bh - BCG0, 16, // Batt Charge current ; 4Ch, 4Dh - BACV, 16, // Batt Charging Voltage ; 4Eh, 4Fh - BTM0, 16, // Batt Battery Temp ; 50h, 51h - BSN0, 16, // Batt Serial Number ; 52h, 53h - BPCT, 16, // Batt Percentage of full charge ; 54h, 55h - BSSB, 16, // BATT Battery Status SMB ; 56h, 57h - CYC0, 16, // Batt Cycle Counter ; 58h, 59h - BMD0, 16, // Manufacture Date ; 5Ah, 5Bh - // Batt Day ; BIT[4:0] (Day) - // Batt Month ; BIT[9:5] (Month) - // Batt Year ; BIT[15:10] (Year) + BDC0, 16, // Batt Design Capacity ; 40h, 41h + BDV0, 16, // Batt Design Voltage ; 42h, 43h + BFC0, 16, // Batt Last Full Charge Capacity ; 44h, 45h + BPC0, 16, // Batt Current ; 46h, 47h + BRC0, 16, // Batt Remaining Capacity ; 48h, 49h + BPV0, 16, // Batt Present Voltage ; 4Ah, 4Bh + BCG0, 16, // Batt Charge current ; 4Ch, 4Dh + BACV, 16, // Batt Charging Voltage ; 4Eh, 4Fh + BTM0, 16, // Batt Battery Temp ; 50h, 51h + BSN0, 16, // Batt Serial Number ; 52h, 53h + BPCT, 16, // Batt Percentage of full charge ; 54h, 55h + BSSB, 16, // BATT Battery Status SMB ; 56h, 57h + CYC0, 16, // Batt Cycle Counter ; 58h, 59h + BMD0, 16, // Manufacture Date ; 5Ah, 5Bh + // Batt Day ; BIT[4:0] (Day) + // Batt Month ; BIT[9:5] (Month) + // Batt Year ; BIT[15:10] (Year)
Offset(0x60), - BCHM, 32, // Battery Chemistry ; 60h - 64h - BATD, 56, // Battery Device name ; 64h - 6Ah + BCHM, 32, // Battery Chemistry ; 60h - 64h + BATD, 56, // Battery Device name ; 64h - 6Ah
Offset(0x70), - ADPT, 1, // AC Adapter Status for OS ; 70h.0 - ADPN, 1, // AC Adapter H/W status ; 70h.1 - BTIN, 1, // Battery Present ; 70h.2 - BTBD, 1, // Battery Malfunction ; 70h.3 - ACMD, 1, // ACPI Mode ; 70h.4 - , 1, // Reserved ; 70h.5 - SSBS, 1, // 1=Standard BIOS, 0=Coreboot ; 70h.6 - PSTH, 1, // Passive Thermal Policy ; 70h.7 - BST0, 8, // Battery Status ; 71h - // Bit0 : Discharging - // Bit1 : Charging - // Bit2 : Discharging and Critical Low - // Bit3-7 : Reserved - LIDF, 1, // Lid is open ; 72h.0 - GPRC, 1, // Recovery GPI Status ; 72h.1 - , 6, // Reserved ; 72h.2-7 - TPLD, 1, // TouchPad LED Activation ; 73h.0 - TPST, 1, // Touchpad LED Status ; 73h.1 - , 6, // Reserved ; 73h.2-7 + ADPT, 1, // AC Adapter Status for OS ; 70h.0 + ADPN, 1, // AC Adapter H/W status ; 70h.1 + BTIN, 1, // Battery Present ; 70h.2 + BTBD, 1, // Battery Malfunction ; 70h.3 + ACMD, 1, // ACPI Mode ; 70h.4 + , 1, // Reserved ; 70h.5 + SSBS, 1, // 1=Standard BIOS, 0=Coreboot ; 70h.6 + PSTH, 1, // Passive Thermal Policy ; 70h.7 + BST0, 8, // Battery Status ; 71h + // Bit0 : Discharging + // Bit1 : Charging + // Bit2 : Discharging and Critical Low + // Bit3-7 : Reserved + LIDF, 1, // Lid is open ; 72h.0 + GPRC, 1, // Recovery GPI Status ; 72h.1 + , 6, // Reserved ; 72h.2-7 + TPLD, 1, // TouchPad LED Activation ; 73h.0 + TPST, 1, // Touchpad LED Status ; 73h.1 + , 6, // Reserved ; 73h.2-7
Offset(0x78), - CTMP, 8, // Current CPU Temperature ; 78h - SKTB, 8, // GPU Temperature ; 79h - LTM1, 8, // Local Temp 1 ; 7Ah - LTM2, 8, // Local Temp 2 ; 7Bh - FTCH, 16, // Fan Tachometer value ; 7Ch - 7Dh - FDBG, 16, // Fan Debug - Override Fan Tach value ; 7Eh - 7Fh - , 1, // Reserved ; 80h.0 - KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1 - , 6, // Reserved ; 80h.2-7 - NPST, 8, // Number of P-State level ; 81h - MPST, 8, // Maxumum P-State ; 82h - KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0 - TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1 - , 1, // Reserved ; 83h.2 - LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); 83h.3 - RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; 83h.4 - , 3, // Reserved ; 83h.5-7 - KBEV, 1, // Keyboard Wake Event ; 84h.0 - TPEV, 1, // TouchPad Wake Event ; 84h.1 - LDEV, 1, // Lid Wake Event ; 84h.2 - , 4, // Reserved ; 84h.3-6 - PBEV, 1, // Power Button Wake Event ; 84h.7 - - ECCD, 8, // EC Code State ; 85h - ROFW, 8, // RO FW Reason ID ; 86h + CTMP, 8, // Current CPU Temperature ; 78h + SKTB, 8, // GPU Temperature ; 79h + LTM1, 8, // Local Temp 1 ; 7Ah + LTM2, 8, // Local Temp 2 ; 7Bh + FTCH, 16, // Fan Tachometer value ; 7Ch - 7Dh + FDBG, 16, // Fan Debug - Override Fan Tach value ; 7Eh - 7Fh + , 1, // Reserved ; 80h.0 + KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1 + , 6, // Reserved ; 80h.2-7 + NPST, 8, // Number of P-State level ; 81h + MPST, 8, // Maxumum P-State ; 82h + KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0 + TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1 + , 1, // Reserved ; 83h.2 + LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); 83h.3 + RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; 83h.4 + , 3, // Reserved ; 83h.5-7 + KBEV, 1, // Keyboard Wake Event ; 84h.0 + TPEV, 1, // TouchPad Wake Event ; 84h.1 + LDEV, 1, // Lid Wake Event ; 84h.2 + , 4, // Reserved ; 84h.3-6 + PBEV, 1, // Power Button Wake Event ; 84h.7 + + ECCD, 8, // EC Code State ; 85h + ROFW, 8, // RO FW Reason ID ; 86h
Offset(0xBA), - FWVR, 48, // EC Firmware Version ; BAh-BFh + FWVR, 48, // EC Firmware Version ; BAh-BFh
Offset(0xC0), - SMPR, 8, // SMBus protocol register ; C0h - SMST, 8, // SMBus status register ; C1h - SMAD, 8, // SMBus address register ; C2h - SMCM, 8, // SMBus command register ; C3h - SMD0, 0x100, // SMBus data regs (32) ; C4h - E3h - BCNT, 8, // SMBus Block Count ; E4h + SMPR, 8, // SMBus protocol register ; C0h + SMST, 8, // SMBus status register ; C1h + SMAD, 8, // SMBus address register ; C2h + SMCM, 8, // SMBus command register ; C3h + SMD0, 0x100, // SMBus data regs (32) ; C4h - E3h + BCNT, 8, // SMBus Block Count ; E4h }
Method (_CRS, 0, NotSerialized) @@ -161,17 +161,17 @@ Device (EC0) /* * EC Query Responses * - * Lid Status Change 06h + * Lid Status Change 06h * Wifi Button Event (F12) 07h * TZ Event Update CPU Temp 08h - * CPU P-State Down 0Eh - * CPU P-State UP 0Fh - - * AC plug in 10h - * AC removed 11h - * Battery Plugged in 12h - * Battery Removed 13h - * Battery State Change 14h + * CPU P-State Down 0Eh + * CPU P-State UP 0Fh + + * AC plug in 10h + * AC removed 11h + * Battery Plugged in 12h + * Battery Removed 13h + * Battery State Change 14h */
// Wifi Button Event diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 137aa81..f7b8be8 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -165,13 +165,13 @@ static void ene_kb3940q_enable_resources(device_t dev) }
static struct device_operations ops = { - .init = ene_kb3940q_init, + .init = ene_kb3940q_init, .read_resources = ene_kb3940q_read_resources, .enable_resources = ene_kb3940q_enable_resources };
static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } };
static void enable_dev(device_t dev) diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index ab01b29..f00d1e0 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -35,8 +35,8 @@ #define KBD_DATA 0x60 #define KBD_COMMAND 0x64 #define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
// 62h/66h Command Interface #define EC_DATA 0x62 @@ -101,29 +101,29 @@ void ec_mem_write(u8 addr, u8 data); #define EC_BAT_DEVICE_NAME6 0x6A
#define EC_POWER_FLAG 0x70 -#define EC_PF_ADAPTER_IN (1 << 0) -#define EC_PF_ADAPTER_PIN (1 << 1) -#define EC_PF_BATT_IN (1 << 2) -#define EC_PF_BATT_DESTROY (1 << 3) -#define EC_PF_ACPI_MODE (1 << 4) -#define EC_PF_X86_BIOS (1 << 6) -#define EC_PF_COREBOOT 0 -#define EC_PF_PASSIVE_THERM (1 << 7) +#define EC_PF_ADAPTER_IN (1 << 0) +#define EC_PF_ADAPTER_PIN (1 << 1) +#define EC_PF_BATT_IN (1 << 2) +#define EC_PF_BATT_DESTROY (1 << 3) +#define EC_PF_ACPI_MODE (1 << 4) +#define EC_PF_X86_BIOS (1 << 6) +#define EC_PF_COREBOOT 0 +#define EC_PF_PASSIVE_THERM (1 << 7)
#define EC_CHARGER_STATUS 0x71 -#define EC_CHS_BAT_DISCHARGING (1 << 0) -#define EC_CHS_BAT_CHARGING (1 << 1) -#define EC_CHS_BAT_CRITICAL (1 << 2) +#define EC_CHS_BAT_DISCHARGING (1 << 0) +#define EC_CHS_BAT_CHARGING (1 << 1) +#define EC_CHS_BAT_CRITICAL (1 << 2)
#define EC_HW_GPI_STATUS 0x72 -#define EC_GPI_LID_STAT_BIT 0 -#define EC_GPI_RECOVERY_MODE_BIT 1 -#define EC_GPI_LID_OPEN (1 << EC_GPI_LID_STAT_BIT) -#define EC_GPI_RECOVERY_STATUS (1 << EC_GPI_RECOVERY_MODE_BIT) +#define EC_GPI_LID_STAT_BIT 0 +#define EC_GPI_RECOVERY_MODE_BIT 1 +#define EC_GPI_LID_OPEN (1 << EC_GPI_LID_STAT_BIT) +#define EC_GPI_RECOVERY_STATUS (1 << EC_GPI_RECOVERY_MODE_BIT)
#define EC_GPIO_STATUS 0x73 -#define EC_GPIO_TP_LED_ENABLE (1 << 0) -#define EC_GPIO_TP_LED_STATUS (1 << 1) +#define EC_GPIO_TP_LED_ENABLE (1 << 0) +#define EC_GPIO_TP_LED_STATUS (1 << 1)
#define EC_CPU_TMP 0x78 #define EC_GPU_TMP 0x79 @@ -135,34 +135,34 @@ void ec_mem_write(u8 addr, u8 data); #define EC_FAN_DBG_RPM_HI 0x7F
#define EC_KBID_REG 0x80 -#define EC_KBD_EN 0 -#define EC_KBD_JP (1 << 1) +#define EC_KBD_EN 0 +#define EC_KBD_JP (1 << 1) #define EC_CURR_PS 0x81 #define EC_MAX_PS 0x82
#define EC_EC_PSW 0x83 -#define EC_PSW_IKB (1 << 0) -#define EC_PSW_TP (1 << 1) -#define EC_PSW_LAN (1 << 3) -#define EC_PSW_RTC (1 << 4) -#define EC_PSW_USB (1 << 5) +#define EC_PSW_IKB (1 << 0) +#define EC_PSW_TP (1 << 1) +#define EC_PSW_LAN (1 << 3) +#define EC_PSW_RTC (1 << 4) +#define EC_PSW_USB (1 << 5)
#define EC_WAKE_EVEN_TID 0x84 -#define EC_WID_IKB (1 << 0) -#define EC_WID_TP (1 << 1) -#define EC_WID_LID (1 << 2) -#define EC_WID_PWRSW (1 << 7) +#define EC_WID_IKB (1 << 0) +#define EC_WID_TP (1 << 1) +#define EC_WID_LID (1 << 2) +#define EC_WID_PWRSW (1 << 7)
#define EC_CODE_STATE 0x85 -#define EC_COS_INITIAL_STAGE 0xBB -#define EC_COS_EC_RO 0xC0 -#define EC_COS_EC_RW 0xC1 +#define EC_COS_INITIAL_STAGE 0xBB +#define EC_COS_EC_RO 0xC0 +#define EC_COS_EC_RW 0xC1
#define EC_FW_REASON_ID 0x86 -#define EC_FWR_NOT_RO 0x00 -#define EC_FWR_GPI_ASSERTED 0x01 -#define EC_FWR_HOTKEY_PRESSED 0x02 -#define EC_FWR_FIRMWARE_CORRUPT 0x03 +#define EC_FWR_NOT_RO 0x00 +#define EC_FWR_GPI_ASSERTED 0x01 +#define EC_FWR_HOTKEY_PRESSED 0x02 +#define EC_FWR_FIRMWARE_CORRUPT 0x03
#define EC_SHUTDOWN_REASON 0xB9 #define EC_FW_VER0 0xBA diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl index 1621b36..d628c9f 100644 --- a/src/ec/quanta/it8518/acpi/battery.asl +++ b/src/ec/quanta/it8518/acpi/battery.asl @@ -38,19 +38,19 @@ Device (BATX) // Name (PBIF, Package() { - 0, // 0: Power Unit - 0xFFFFFFFF, // 1: Design Capacity - 0xFFFFFFFF, // 2: Last Full Charge Capacity - 1, // 3: Battery Technology(Rechargable) - 10800, // 4: Design Voltage 10.8V - 0, // 5: Design capacity of warning - 0, // 6: Design capacity of low - 1, // 7: Battery capacity granularity 1 - 1, // 8: Battery capacity granularity 2 - "", // 9: Model Number - "", // 10: Serial Number - "", // 11: Battery Type - "" // 12: OEM Infomration + 0, // 0: Power Unit + 0xFFFFFFFF, // 1: Design Capacity + 0xFFFFFFFF, // 2: Last Full Charge Capacity + 1, // 3: Battery Technology(Rechargable) + 10800, // 4: Design Voltage 10.8V + 0, // 5: Design capacity of warning + 0, // 6: Design capacity of low + 1, // 7: Battery capacity granularity 1 + 1, // 8: Battery capacity granularity 2 + "", // 9: Model Number + "", // 10: Serial Number + "", // 11: Battery Type + "" // 12: OEM Infomration })
Name (PBST, Package () @@ -121,7 +121,7 @@ Device (BATX) // // Power Unit // SMART battery : 1 - 10mWh : 0 - mAh - // ACPI spec : 0 - mWh : 1 - mAh + // ACPI spec : 0 - mWh : 1 - mAh // Store(SBCM, Local7) XOr (Local7, One, Index (PBIF, 0)) @@ -314,7 +314,7 @@ Device (BATX) // // Get Power unit from the battery static information // SMART battery : 1 - 10mWh : 0 - mAh - // ACPI spec : 0 - mWh : 1 - mAh + // ACPI spec : 0 - mWh : 1 - mAh If (Local6) { Multiply (ECRC, 10, Local1) @@ -336,7 +336,7 @@ Device (BATX) // See if within ~3% of full ShiftRight (Local2, 5, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + LLess (Local1, Add (Local2, Local3)))) { Store (Local2, Local1) } diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl index 7549fa2..f5c6807 100644 --- a/src/ec/quanta/it8518/acpi/ec.asl +++ b/src/ec/quanta/it8518/acpi/ec.asl @@ -33,448 +33,448 @@ Device (EC0) OperationRegion(ERAM, EmbeddedControl, 0, 0xFF) Field (ERAM, ByteAcc, NoLock, Preserve) { - Offset(0x00), // [Configuration Space 0] - , 1, // Reserved bit[0] - ENGA, 1, // Enable Global attention - ENHY, 1, // Enable Hotkey function - HFNE, 1, // Enable Sticky Fn Key - DSEM, 1, // Disable embedded NumPad Emulation - EN3R, 1, // Enable 3rd Host interface and TWR registers - , 1, // Reserved bit[6] - ENTM, 1, // Enable Thermal monitoring - - Offset(0x01), // [Configuration Space 1] - ENBK, 1, // Enable Panel backlight on/ off synchronized with LID state - , 3, // Reserved bits[1:3] - WPSW, 1, // Warning if the power switch is depressed - , 2, // Reserved bits[5:6] - NTKY, 1, // do not ignore any key while Fn key is held down - - Offset(0x02), // [Configuration Space 2] - , 5, // Reserved bits[0:4] - SNLC, 1, // Smart NumLock Enable. 1:Enable 0:Disable - , 1, // Reserved bit[6] - TNKB, 1, // ThinkVantage button function bit - // 0: Scan code (Enter key) - // 1: SMI/SCI attention - - Offset(0x03), // [Configuration Space 3] - DSHP, 1, // Disable to synchronize headphone state with the speaker mute - IGPK, 1, // Ignore phantom keys - , 2, // Reserved bits[2:3] - CBAT, 1, // Change discharge/charge preference to discharge primary battery first and charge secondary battery first if possible - ADO0, 1, // Audio button behavior mode 0 - ADO1, 1, // Audio button behavior mode 1 - , 1, // Enable to use PMH fan functions to get the fan speed - - Offset(0x04), // [Sound Mask 0] - , 1, // reserved - CLBA, 1, // critical low battery alarm - LWBA, 1, // low battery alarm (YELLOW -> RED) - SUBE, 1, // suspend beep - PUBE, 1, // vm_suspend beep - RSBE, 1, // resume beep - DCBE, 1, // DC in/out beep - PFBE, 1, // power off beep - - Offset(0x05), // [Sound Mask 1] - HSPA, 1, // power off alarm - NHDD, 1, // no HDD alarm - DEAD, 1, // dead - B440, 1, // 440 hz beep - B315, 1, // 315 hz beep - T315, 1, // two 315 hz beep - R315, 1, // three 315 hz beep - BYAM, 1, // inhibit swap - - Offset(0x06), // [Sound ID (Write only)] - HSUN, 8, // Sound ID (Write Only) - - Offset(0x07), // [Sound Repeat Interval (unit time 125ms)] - HSRP, 8, // Sound Repeat Interval (Unit time : 125ms ) - - Offset(0x08), // [Sound Mask 2] - Offset(0x09), // [KBD ID] - Offset(0x0A), // [KMC command control] - // Offset 0xOB : reserved - - Offset(0x0C), // [LED On/Off/ Blinking Control (Write only)] - HLCL, 4, // 0: power LED - // 1: battery status 0 - // 2: battery status 1 - // 3: additional Bay LED (Venice) / reserved (Toronto-4) / Slicer LED (Tokyo) - // 4-6: reserved - // 7: suspend LED - // 8: dock LED 1 - // 9: dock LED 2 - // 10-13: reserved - // 14: microphone mute - // 15: reserved - , 1, // Reserved bit[4] - , 1, // Blink gradually - BLIK, 1, // Blinking - TONF, 1, // Turn on/off - - Offset(0x0D), // [Peripheral control 3] - UONE, 1, // Bit0 - Enable to supply power through USB in S3, S4 and S5 state. - , 1, // Reserved bit[1] - , 1, // set USB_AO_SEL0 signal in S3, S4, and S5 state - , 1, // set USB_AO_SEL1 signal in S3, S4, and S5 state - , 4, // Reserved bits[4:7] - - Offset(0x0E), // [Peripheral Status 4] - HFNS, 2, // Bit[1, 0] : Fn Key Status - // [0, 0] ... Unlock - // [0, 1] ... Sticky - // [1, 0] ... Lock - // [1, 1] ... Reserved - GSER, 1, // G-Sensor Diag Error. 1:Error / 0: No error - PSCS, 1, // Inhibit charging - , 1, // External power saving mode - GSUD, 1, // G-Sensor under Diag. 1: Diag is running/0: Diag comp(not running) - GSID, 2, // Bit[7,6] G-Sensor type ID - // [0,0] ... None - // [0,1] ... STMicro - // [1,0] ... Memsic - // [1,1] ... ADI - - Offset(0x0F), // [Peripheral status 5 (read only)] - , 4, // Reserved bits[0:3] - HDSU, 1, // HDD was detached in suspend (this bit is cleared when the system enters into suspend) - BYSU, 1, // Bay HDD was detached in suspend (this bit is cleared when the system enters into suspend) - , 1, // NumLock state of the embedded keyboard - TMOD, 1, // Tablet mode switch - - Offset(0x10), // [Attention Mask (00-127)] - HAM0, 8, // 10 : Attention Mask (00-07) - HAM1, 8, // 11 : Attention Mask (08-0F) - HAM2, 8, // 12 : Attention Mask (10-17) - HAM3, 8, // 13 : Attention Mask (18-1F) - HAM4, 8, // 14 : Attention Mask (20-27) - HAM5, 8, // 15 : Attention Mask (28-2F) - HAM6, 8, // 16 : Attention Mask (30-37) - HAM7, 8, // 17 : Attention Mask (38-3F) - HAM8, 8, // 18 : Attention Mask (40-47) - HAM9, 8, // 19 : Attention Mask (48-4F) - HAMA, 8, // 1A : Attention Mask (50-57) - HAMB, 8, // 1B : Attention Mask (58-5F) - HAMC, 8, // 1C : Attention Mask (60-67) - HAMD, 8, // 1D : Attention Mask (68-6F) - HAME, 8, // 1E : Attention Mask (70-77) - HAMF, 8, // 1F : Attention Mask (78-7F) - - // Offset 0x20 : reserved - Offset(0x21), // [Inhibit Charge timer byte High (00h)] (timer is kicked when high byte is written) - - Offset(0x23), // [Misc. control] - // 01h Reset charge inhibit - // 02h Inhibit to charge - // 03h Reset external power saving mode - // 04h Set to external power saving mode - // 09h Emulate pressing an eject button of optical device in the bay - // 0Ah Reset thermal state to control the fan - // 10h Start gravity sensor diagnostic program - - // Offset 24-26 : reserved - Offset(0x27), // [Passward Scan Code] - // Offset 28-29 : reserved - - Offset(0x2A), // [Attention Request] - HATR, 8, // 2A : Attention request - - Offset(0x2B), // [Trip point of battery capacity] - HT0H, 8, // 2B : MSB of Trip Point Capacity for Battery 0 - HT0L, 8, // 2C : LSB of Trip Point Capacity for Battery 0 - HT1H, 8, // 2D : MSB of Trip Point Capacity for Battery 1 - HT1L, 8, // 2E : LSB of Trip Point Capacity for Battery 1 - - Offset(0x2F), // [Fan Speed Control] - HFSP, 8, // bit 2-0: speed (0: stop, 7:highest speed) - // bit 5-3: reserved (should be 0) - // bit 6: max. speed - // bit 7: Automatic mode (fan speed controlled by thermal level) - - Offset(0x30), // [Audio mute control] - , 7, // Reserved bits[0:6] - SMUT, 1, // Mute - - Offset(0x31), // [Peripheral Control 2] - FANS, 2, // bit 0,1 Fan selector - // 00: Fan 1, 01: Fan 2 - HUWB, 1, // UWB on - ENS4, 1, // Reserved bit[3] - DSEX, 1, // Disable Express Card - AYID, 1, // Always-on Card identified - , 1, // Select USB to Always On card - , 1, // Assert the express card slot power control standby signal - - Offset(0x32), // [EC Event Mask 0] - HWPM, 1, // PME : Not used. PME# is connected to GPE directly. - HWLB, 1, // Critical Low Bat - HWLO, 1, // Lid Open - , 1, // Eject button - HWFN, 1, // FN key - , 1, // Portfino wake up - HWRI, 1, // Ring Indicator (UART) - HWBU, 1, // Bay Unlock - - Offset(0x33), // [EC Event Mask 1] - - Offset(0x34), // [Peripheral status 2 (read only)] - , 1, // Reserved bit[0] - , 1, // Beep is being sounded now - , 1, // SMBus is busy - , 1, // Reserved bit[3] - , 1, // Fan exists - , 1, // Gravity sensors exist - , 1, // Reserved bit[6] - HPLO, 1, // Power consumption warning - - Offset(0x35), // [Peripheral status 3 (Read only)] - , 1, // Input devices (keyboard and mouse) are locked by password - , 1, // Input devices are frozen (input from devices are inhibited) - , 1, // Fan power on Reset is done - , 1, // Attention is disabled temporarily - , 1, // Fan error - , 2, // Reserved bit[5:6] - , 1, // Thermal sensor error - - Offset(0x36), // [Copy register of EC Event Status (0x32)] - Offset(0x37), // [Copy register of EC Event Status (0x33)] - - Offset(0x38), // [Battery 0 status (read only)] - HB0S, 7, // bit 3-0 level - // F: Unknown - // 2-n: battery level - // 1: low level - // 0: (critical low battery, suspend/ hibernate) - // bit 4 error - // bit 5 charge - // bit 6 discharge - MBTS, 1, // bit 7 battery attached - - Offset(0x39), // [Battery 1 status (read only)] - // bit definition is the same as offset(0x38) - - Offset(0x3A), // [Peripheral control 0] - MUTE, 1, // Mute - I2CS, 1, // I2C select ( 0:Dock EEPROM etc, 1:Thermal sensor etc )(Tokyo-2) - PWRF, 1, // Power off - WANO, 1, // H/W Override bit - // (enable to control wireless devices even if the global WAN disable switch is ON) - DCBD, 1, // Bluetooth On - DCWL, 1, // Wireless Lan On - DCWW, 1, // Wireless Wan On - , 1, // 2nd Battery Inhibit (Tokyo) - - Offset(0x3B), // [Peripheral control 1] - SPKM, 1, // Speaker Mute - KBLH, 1, // Keyboard Light - , 1, // Reserved bit[2] - BTDH, 1, // Bluetooth detach - USBN, 1, // USB On - , 1, // Inhibit communication with battery 0 - , 1, // Inhibit communication with battery 1 - S3FG, 1, // Reserved bit[7] - - Offset(0x3C), // [Resume reason (Read only)] - Offset(0x3D), // [Password Control byte] - Offset(0x3E), // [Password data (8 byte)~ offset:45h] - - Offset(0x46), // [sense status 0] - FNKY, 1, // Fn key - , 1, // Reserved bit[1] - HPLD, 1, // LID open - PROF, 1, // Power off - ACPW, 1, // External power (AC status) - , 2, // Reserved bits[5:6] - CALR, 1, // LP mode (power consumption alert) - - Offset(0x47), // [sense status 1] - HPBU, 1, // Bay Unlock - DKEV, 1, // Dock event - BYNO, 1, // Bay is not Attached - HDIB, 1, // HDD in the bay - , 4, // Reserved bits[4:7] - - Offset(0x48), // [sense status 2] - HPHI, 1, // Head Phone In - GSTS, 1, // Global Wan Enable Switch - , 2, // Reserved bits[2:3] - EXGC, 1, // External Graphic Chip - DOKI, 1, // Dock attached - HDDT, 1, // HDD detect - , 1, // Reserved bit[7] - - Offset(0x49), // [sense status 3] - // Offset 0x4A : reserved - - Offset(0x4C), // [MSB of Event Timer] - ETHB, 8, // bit[14:0]=timer counter, bit[15], 0:ms, 1:sec - - Offset(0x4D), // [LSB of Event Timer] - ETLB, 8, // - - Offset(0x4E), // [EC Event Status 0] - Offset(0x4F), // [EC Event Status 1] - - Offset(0x50), // [SMB_PRTCL (protocol register)] - SMPR, 8, // 00: Controller Not In use - // 01: reserved - // 02: Write Quick command - // 03: Read Quick command - // 04: Send Quick command - // 05: Receive Byte - // 06: Write Byte - // 07: Read Byte - // 08: Write Word - // 09: Read Word - // 0A: Write block - - Offset(0x51), // [SMB_STS (status register)] - SMST, 8, // bits[0:4] Status - // bit[5] Reserved - // bit[6] Alarm Received - // bit[7] Done - - Offset(0x52), // [SMB_ADDR (address register)] - SMAD, 8, // - - Offset(0x53), // [SMB_CMD (Command register)] - SMCM, 8, // - - Offset(0x54), // [SMB_DATA (Data Register (32 bytes))~ offset:73h] - SMD0, 100, // - - Offset(0x74), // [SMB_BCNT (Block count register)] - BCNT, 8, // - - Offset(0x75), // [SMB_ALRM_ADDR (Alarm address register)] - SMAA, 8, // - - Offset(0x76), // [SMB_ALRM_DATA (Alarm data register (2 bytes))] - BATD, 16, // - - Offset(0x78), // [Temperature of thermal sensor 0 (centigrade)] - TMP0, 8, // 78 : Temperature of thermal sensor 0 - TMP1, 8, // 79 : Temperature of thermal sensor 1 - TMP2, 8, // 7A : Temperature of thermal sensor 2 - TMP3, 8, // 7B : Temperature of thermal sensor 3 - TMP4, 8, // 7C : Temperature of thermal sensor 4 - TMP5, 8, // 7D : Temperature of thermal sensor 5 - TMP6, 8, // 7E : Temperature of thermal sensor 6 - TMP7, 8, // 7F : Temperature of thermal sensor 7 - - // Offset 79-7F : reserved - Offset(0x80), // [Attention control byte] - - Offset(0x81), // [Battery information ID for 0xA0-0xAF] - HIID, 8, // (this byte is depend on the interface, 62&66 and 1600&1604) - - Offset(0x82), // [Fn Dual function - make time out time (100ms unit)] - - Offset(0x83), // [Fn Dual function ID] - HFNI, 8, // 0: none - // 1-3: Reserved - // 4: ACPI Power - // 5: ACPI Sleep - // 6: ACPI Wake - // 7: Left Ctrl key - - Offset(0x84), // [Fan Speed] - , 16, // - // (I/F Offset 3Bh bit5 => 0:Main Fan , 1:Second Fan) - - Offset(0x86), // [password 0 - 7 status] - Offset(0x87), // [password 8 - 15 status] - Offset(0x88), // [Thermal Status of Level 0 (low)] - Offset(0x89), // [Thermal Status of Level 1 (middle)] - Offset(0x8A), // [Thermal Status of Level 2 (middle high)] - Offset(0x8B), // [Thermal Status of Level 3 (high)] - // Offset 0x8C : reserved - - Offset(0x8D), // [Interval of polling Always-on cards in half minute] - HDAA, 3, // Warning Delay Period - HDAB, 3, // Stolen Delay Period - HDAC, 2, // Sensitivity - - Offset(0x8E), // [Key-number assigned to the ThinkVantage button] - Offset(0x8F), // [EC Internal Use for Fan Duty Table Creation] - Offset(0x90), // [EC internal use] - Offset(0xA0), // [Battery Information Area]~ offset:0AFh - Offset(0xB0), // [Battery 0 charge start capacity] - Offset(0xB1), // [Battery 0 charge stop capacity] - Offset(0xB2), // [Battery 1 charge start capacity] - Offset(0xB3), // [Battery 1 charge stop capacity] - - Offset(0xB4), // [Battery 0 control] - // 01h Stop refreshing the battery - // 02h Refresh the battery - // 07h Set long life span mode - // 08h Set long run time mode - - Offset(0xB5), // [Battery 1 control] - // Offset B6-C7 : reserved - - Offset(0xC8), // [Adaptive Thermal Management (ATM)] - ATMX, 8, // bit 7-4 - Thermal Table & bit 3-0 - Fan Speed Table - - Offset(0xC9), // [Wattage of AC/DC] - AC65, 8, // - - Offset(0xCA), // Reserved - but should be 0 - - Offset(0xCB), // [ATM configuration] - BFUD, 1, // bit 0 - Battery FUD Flag - , 7, // bit 1~7 - Reserved - - Offset(0xCC), // - PWMH, 8, // CC : AC Power Consumption (MSB) - PWML, 8, // CD : AC Power Consumption (LSB) - unit: 100mW - - Offset(0xCE), // [Configuration Space 4] - , 2, // Windows key mode - , 2, // Application key mode - , 1, // Swap the Fn key and the left Ctrl key - , 3, // Reserved bits[5:7] - - Offset(0xCF), // [Configuration Space 5] - HSID, 8, // Hand shaking byte of system information ID - - Offset(0xD0), // [EC Type] - // D1-DF : reserved - - Offset(0xE0), // @@ Mapping to old EC RAM for battery information - ECRC, 16, // BAT1 Sys command [0] RC - ECAC, 16, // BAT1 Sys command [0] AV_I - ECVO, 16, // BAT1 Sys command [0] Voltage - - // E1-E7 : reserved - Offset(0xE8), // [Version 0] - Offset(0xE9), // [Version 1] - Offset(0xEA), // [Machine ID] - Offset(0xEB), // [Function Specification Minor Version] - Offset(0xEC), // [EC capability 0] - Offset(0xED), // [EC capability 1] - - Offset(0xEE), // [Highest battery level] - MBTH, 4, // bit 3-0: battery 0 highest level - SBTH, 4, // bit 7-4: battery 1 highest level - // note: if highest level is 0 or 0xF, it means not defined - // (in this case, use default hightest level, it is 6) - - Offset(0xEF), // [EC Function Specification Major Version] - Offset(0xF0), // [Build ID]~ offset:0F7h - - Offset(0xF8), // [Build Date (F8: MSB, F9:LSB)] - , 4, // bit 3-0: day(1-31) - , 4, // bit 7-4: month(1-12) - , 8, // bit 15-8: year(2000 base) - - Offset(0xFA), // [Build Time (in 2seconds)] - // ex: when index FAh=5Ah and index FBh=ADh, Build Time is 5AADh .. 12:53:46 - - Offset(0xFC), // [reserved]~ offset:0FFh + Offset(0x00), // [Configuration Space 0] + , 1, // Reserved bit[0] + ENGA, 1, // Enable Global attention + ENHY, 1, // Enable Hotkey function + HFNE, 1, // Enable Sticky Fn Key + DSEM, 1, // Disable embedded NumPad Emulation + EN3R, 1, // Enable 3rd Host interface and TWR registers + , 1, // Reserved bit[6] + ENTM, 1, // Enable Thermal monitoring + + Offset(0x01), // [Configuration Space 1] + ENBK, 1, // Enable Panel backlight on/ off synchronized with LID state + , 3, // Reserved bits[1:3] + WPSW, 1, // Warning if the power switch is depressed + , 2, // Reserved bits[5:6] + NTKY, 1, // do not ignore any key while Fn key is held down + + Offset(0x02), // [Configuration Space 2] + , 5, // Reserved bits[0:4] + SNLC, 1, // Smart NumLock Enable. 1:Enable 0:Disable + , 1, // Reserved bit[6] + TNKB, 1, // ThinkVantage button function bit + // 0: Scan code (Enter key) + // 1: SMI/SCI attention + + Offset(0x03), // [Configuration Space 3] + DSHP, 1, // Disable to synchronize headphone state with the speaker mute + IGPK, 1, // Ignore phantom keys + , 2, // Reserved bits[2:3] + CBAT, 1, // Change discharge/charge preference to discharge primary battery first and charge secondary battery first if possible + ADO0, 1, // Audio button behavior mode 0 + ADO1, 1, // Audio button behavior mode 1 + , 1, // Enable to use PMH fan functions to get the fan speed + + Offset(0x04), // [Sound Mask 0] + , 1, // reserved + CLBA, 1, // critical low battery alarm + LWBA, 1, // low battery alarm (YELLOW -> RED) + SUBE, 1, // suspend beep + PUBE, 1, // vm_suspend beep + RSBE, 1, // resume beep + DCBE, 1, // DC in/out beep + PFBE, 1, // power off beep + + Offset(0x05), // [Sound Mask 1] + HSPA, 1, // power off alarm + NHDD, 1, // no HDD alarm + DEAD, 1, // dead + B440, 1, // 440 hz beep + B315, 1, // 315 hz beep + T315, 1, // two 315 hz beep + R315, 1, // three 315 hz beep + BYAM, 1, // inhibit swap + + Offset(0x06), // [Sound ID (Write only)] + HSUN, 8, // Sound ID (Write Only) + + Offset(0x07), // [Sound Repeat Interval (unit time 125ms)] + HSRP, 8, // Sound Repeat Interval (Unit time : 125ms ) + + Offset(0x08), // [Sound Mask 2] + Offset(0x09), // [KBD ID] + Offset(0x0A), // [KMC command control] + // Offset 0xOB : reserved + + Offset(0x0C), // [LED On/Off/ Blinking Control (Write only)] + HLCL, 4, // 0: power LED + // 1: battery status 0 + // 2: battery status 1 + // 3: additional Bay LED (Venice) / reserved (Toronto-4) / Slicer LED (Tokyo) + // 4-6: reserved + // 7: suspend LED + // 8: dock LED 1 + // 9: dock LED 2 + // 10-13: reserved + // 14: microphone mute + // 15: reserved + , 1, // Reserved bit[4] + , 1, // Blink gradually + BLIK, 1, // Blinking + TONF, 1, // Turn on/off + + Offset(0x0D), // [Peripheral control 3] + UONE, 1, // Bit0 - Enable to supply power through USB in S3, S4 and S5 state. + , 1, // Reserved bit[1] + , 1, // set USB_AO_SEL0 signal in S3, S4, and S5 state + , 1, // set USB_AO_SEL1 signal in S3, S4, and S5 state + , 4, // Reserved bits[4:7] + + Offset(0x0E), // [Peripheral Status 4] + HFNS, 2, // Bit[1, 0] : Fn Key Status + // [0, 0] ... Unlock + // [0, 1] ... Sticky + // [1, 0] ... Lock + // [1, 1] ... Reserved + GSER, 1, // G-Sensor Diag Error. 1:Error / 0: No error + PSCS, 1, // Inhibit charging + , 1, // External power saving mode + GSUD, 1, // G-Sensor under Diag. 1: Diag is running/0: Diag comp(not running) + GSID, 2, // Bit[7,6] G-Sensor type ID + // [0,0] ... None + // [0,1] ... STMicro + // [1,0] ... Memsic + // [1,1] ... ADI + + Offset(0x0F), // [Peripheral status 5 (read only)] + , 4, // Reserved bits[0:3] + HDSU, 1, // HDD was detached in suspend (this bit is cleared when the system enters into suspend) + BYSU, 1, // Bay HDD was detached in suspend (this bit is cleared when the system enters into suspend) + , 1, // NumLock state of the embedded keyboard + TMOD, 1, // Tablet mode switch + + Offset(0x10), // [Attention Mask (00-127)] + HAM0, 8, // 10 : Attention Mask (00-07) + HAM1, 8, // 11 : Attention Mask (08-0F) + HAM2, 8, // 12 : Attention Mask (10-17) + HAM3, 8, // 13 : Attention Mask (18-1F) + HAM4, 8, // 14 : Attention Mask (20-27) + HAM5, 8, // 15 : Attention Mask (28-2F) + HAM6, 8, // 16 : Attention Mask (30-37) + HAM7, 8, // 17 : Attention Mask (38-3F) + HAM8, 8, // 18 : Attention Mask (40-47) + HAM9, 8, // 19 : Attention Mask (48-4F) + HAMA, 8, // 1A : Attention Mask (50-57) + HAMB, 8, // 1B : Attention Mask (58-5F) + HAMC, 8, // 1C : Attention Mask (60-67) + HAMD, 8, // 1D : Attention Mask (68-6F) + HAME, 8, // 1E : Attention Mask (70-77) + HAMF, 8, // 1F : Attention Mask (78-7F) + + // Offset 0x20 : reserved + Offset(0x21), // [Inhibit Charge timer byte High (00h)] (timer is kicked when high byte is written) + + Offset(0x23), // [Misc. control] + // 01h Reset charge inhibit + // 02h Inhibit to charge + // 03h Reset external power saving mode + // 04h Set to external power saving mode + // 09h Emulate pressing an eject button of optical device in the bay + // 0Ah Reset thermal state to control the fan + // 10h Start gravity sensor diagnostic program + + // Offset 24-26 : reserved + Offset(0x27), // [Passward Scan Code] + // Offset 28-29 : reserved + + Offset(0x2A), // [Attention Request] + HATR, 8, // 2A : Attention request + + Offset(0x2B), // [Trip point of battery capacity] + HT0H, 8, // 2B : MSB of Trip Point Capacity for Battery 0 + HT0L, 8, // 2C : LSB of Trip Point Capacity for Battery 0 + HT1H, 8, // 2D : MSB of Trip Point Capacity for Battery 1 + HT1L, 8, // 2E : LSB of Trip Point Capacity for Battery 1 + + Offset(0x2F), // [Fan Speed Control] + HFSP, 8, // bit 2-0: speed (0: stop, 7:highest speed) + // bit 5-3: reserved (should be 0) + // bit 6: max. speed + // bit 7: Automatic mode (fan speed controlled by thermal level) + + Offset(0x30), // [Audio mute control] + , 7, // Reserved bits[0:6] + SMUT, 1, // Mute + + Offset(0x31), // [Peripheral Control 2] + FANS, 2, // bit 0,1 Fan selector + // 00: Fan 1, 01: Fan 2 + HUWB, 1, // UWB on + ENS4, 1, // Reserved bit[3] + DSEX, 1, // Disable Express Card + AYID, 1, // Always-on Card identified + , 1, // Select USB to Always On card + , 1, // Assert the express card slot power control standby signal + + Offset(0x32), // [EC Event Mask 0] + HWPM, 1, // PME : Not used. PME# is connected to GPE directly. + HWLB, 1, // Critical Low Bat + HWLO, 1, // Lid Open + , 1, // Eject button + HWFN, 1, // FN key + , 1, // Portfino wake up + HWRI, 1, // Ring Indicator (UART) + HWBU, 1, // Bay Unlock + + Offset(0x33), // [EC Event Mask 1] + + Offset(0x34), // [Peripheral status 2 (read only)] + , 1, // Reserved bit[0] + , 1, // Beep is being sounded now + , 1, // SMBus is busy + , 1, // Reserved bit[3] + , 1, // Fan exists + , 1, // Gravity sensors exist + , 1, // Reserved bit[6] + HPLO, 1, // Power consumption warning + + Offset(0x35), // [Peripheral status 3 (Read only)] + , 1, // Input devices (keyboard and mouse) are locked by password + , 1, // Input devices are frozen (input from devices are inhibited) + , 1, // Fan power on Reset is done + , 1, // Attention is disabled temporarily + , 1, // Fan error + , 2, // Reserved bit[5:6] + , 1, // Thermal sensor error + + Offset(0x36), // [Copy register of EC Event Status (0x32)] + Offset(0x37), // [Copy register of EC Event Status (0x33)] + + Offset(0x38), // [Battery 0 status (read only)] + HB0S, 7, // bit 3-0 level + // F: Unknown + // 2-n: battery level + // 1: low level + // 0: (critical low battery, suspend/ hibernate) + // bit 4 error + // bit 5 charge + // bit 6 discharge + MBTS, 1, // bit 7 battery attached + + Offset(0x39), // [Battery 1 status (read only)] + // bit definition is the same as offset(0x38) + + Offset(0x3A), // [Peripheral control 0] + MUTE, 1, // Mute + I2CS, 1, // I2C select ( 0:Dock EEPROM etc, 1:Thermal sensor etc )(Tokyo-2) + PWRF, 1, // Power off + WANO, 1, // H/W Override bit + // (enable to control wireless devices even if the global WAN disable switch is ON) + DCBD, 1, // Bluetooth On + DCWL, 1, // Wireless Lan On + DCWW, 1, // Wireless Wan On + , 1, // 2nd Battery Inhibit (Tokyo) + + Offset(0x3B), // [Peripheral control 1] + SPKM, 1, // Speaker Mute + KBLH, 1, // Keyboard Light + , 1, // Reserved bit[2] + BTDH, 1, // Bluetooth detach + USBN, 1, // USB On + , 1, // Inhibit communication with battery 0 + , 1, // Inhibit communication with battery 1 + S3FG, 1, // Reserved bit[7] + + Offset(0x3C), // [Resume reason (Read only)] + Offset(0x3D), // [Password Control byte] + Offset(0x3E), // [Password data (8 byte)~ offset:45h] + + Offset(0x46), // [sense status 0] + FNKY, 1, // Fn key + , 1, // Reserved bit[1] + HPLD, 1, // LID open + PROF, 1, // Power off + ACPW, 1, // External power (AC status) + , 2, // Reserved bits[5:6] + CALR, 1, // LP mode (power consumption alert) + + Offset(0x47), // [sense status 1] + HPBU, 1, // Bay Unlock + DKEV, 1, // Dock event + BYNO, 1, // Bay is not Attached + HDIB, 1, // HDD in the bay + , 4, // Reserved bits[4:7] + + Offset(0x48), // [sense status 2] + HPHI, 1, // Head Phone In + GSTS, 1, // Global Wan Enable Switch + , 2, // Reserved bits[2:3] + EXGC, 1, // External Graphic Chip + DOKI, 1, // Dock attached + HDDT, 1, // HDD detect + , 1, // Reserved bit[7] + + Offset(0x49), // [sense status 3] + // Offset 0x4A : reserved + + Offset(0x4C), // [MSB of Event Timer] + ETHB, 8, // bit[14:0]=timer counter, bit[15], 0:ms, 1:sec + + Offset(0x4D), // [LSB of Event Timer] + ETLB, 8, // + + Offset(0x4E), // [EC Event Status 0] + Offset(0x4F), // [EC Event Status 1] + + Offset(0x50), // [SMB_PRTCL (protocol register)] + SMPR, 8, // 00: Controller Not In use + // 01: reserved + // 02: Write Quick command + // 03: Read Quick command + // 04: Send Quick command + // 05: Receive Byte + // 06: Write Byte + // 07: Read Byte + // 08: Write Word + // 09: Read Word + // 0A: Write block + + Offset(0x51), // [SMB_STS (status register)] + SMST, 8, // bits[0:4] Status + // bit[5] Reserved + // bit[6] Alarm Received + // bit[7] Done + + Offset(0x52), // [SMB_ADDR (address register)] + SMAD, 8, // + + Offset(0x53), // [SMB_CMD (Command register)] + SMCM, 8, // + + Offset(0x54), // [SMB_DATA (Data Register (32 bytes))~ offset:73h] + SMD0, 100, // + + Offset(0x74), // [SMB_BCNT (Block count register)] + BCNT, 8, // + + Offset(0x75), // [SMB_ALRM_ADDR (Alarm address register)] + SMAA, 8, // + + Offset(0x76), // [SMB_ALRM_DATA (Alarm data register (2 bytes))] + BATD, 16, // + + Offset(0x78), // [Temperature of thermal sensor 0 (centigrade)] + TMP0, 8, // 78 : Temperature of thermal sensor 0 + TMP1, 8, // 79 : Temperature of thermal sensor 1 + TMP2, 8, // 7A : Temperature of thermal sensor 2 + TMP3, 8, // 7B : Temperature of thermal sensor 3 + TMP4, 8, // 7C : Temperature of thermal sensor 4 + TMP5, 8, // 7D : Temperature of thermal sensor 5 + TMP6, 8, // 7E : Temperature of thermal sensor 6 + TMP7, 8, // 7F : Temperature of thermal sensor 7 + + // Offset 79-7F : reserved + Offset(0x80), // [Attention control byte] + + Offset(0x81), // [Battery information ID for 0xA0-0xAF] + HIID, 8, // (this byte is depend on the interface, 62&66 and 1600&1604) + + Offset(0x82), // [Fn Dual function - make time out time (100ms unit)] + + Offset(0x83), // [Fn Dual function ID] + HFNI, 8, // 0: none + // 1-3: Reserved + // 4: ACPI Power + // 5: ACPI Sleep + // 6: ACPI Wake + // 7: Left Ctrl key + + Offset(0x84), // [Fan Speed] + , 16, // + // (I/F Offset 3Bh bit5 => 0:Main Fan , 1:Second Fan) + + Offset(0x86), // [password 0 - 7 status] + Offset(0x87), // [password 8 - 15 status] + Offset(0x88), // [Thermal Status of Level 0 (low)] + Offset(0x89), // [Thermal Status of Level 1 (middle)] + Offset(0x8A), // [Thermal Status of Level 2 (middle high)] + Offset(0x8B), // [Thermal Status of Level 3 (high)] + // Offset 0x8C : reserved + + Offset(0x8D), // [Interval of polling Always-on cards in half minute] + HDAA, 3, // Warning Delay Period + HDAB, 3, // Stolen Delay Period + HDAC, 2, // Sensitivity + + Offset(0x8E), // [Key-number assigned to the ThinkVantage button] + Offset(0x8F), // [EC Internal Use for Fan Duty Table Creation] + Offset(0x90), // [EC internal use] + Offset(0xA0), // [Battery Information Area]~ offset:0AFh + Offset(0xB0), // [Battery 0 charge start capacity] + Offset(0xB1), // [Battery 0 charge stop capacity] + Offset(0xB2), // [Battery 1 charge start capacity] + Offset(0xB3), // [Battery 1 charge stop capacity] + + Offset(0xB4), // [Battery 0 control] + // 01h Stop refreshing the battery + // 02h Refresh the battery + // 07h Set long life span mode + // 08h Set long run time mode + + Offset(0xB5), // [Battery 1 control] + // Offset B6-C7 : reserved + + Offset(0xC8), // [Adaptive Thermal Management (ATM)] + ATMX, 8, // bit 7-4 - Thermal Table & bit 3-0 - Fan Speed Table + + Offset(0xC9), // [Wattage of AC/DC] + AC65, 8, // + + Offset(0xCA), // Reserved - but should be 0 + + Offset(0xCB), // [ATM configuration] + BFUD, 1, // bit 0 - Battery FUD Flag + , 7, // bit 1~7 - Reserved + + Offset(0xCC), // + PWMH, 8, // CC : AC Power Consumption (MSB) + PWML, 8, // CD : AC Power Consumption (LSB) - unit: 100mW + + Offset(0xCE), // [Configuration Space 4] + , 2, // Windows key mode + , 2, // Application key mode + , 1, // Swap the Fn key and the left Ctrl key + , 3, // Reserved bits[5:7] + + Offset(0xCF), // [Configuration Space 5] + HSID, 8, // Hand shaking byte of system information ID + + Offset(0xD0), // [EC Type] + // D1-DF : reserved + + Offset(0xE0), // @@ Mapping to old EC RAM for battery information + ECRC, 16, // BAT1 Sys command [0] RC + ECAC, 16, // BAT1 Sys command [0] AV_I + ECVO, 16, // BAT1 Sys command [0] Voltage + + // E1-E7 : reserved + Offset(0xE8), // [Version 0] + Offset(0xE9), // [Version 1] + Offset(0xEA), // [Machine ID] + Offset(0xEB), // [Function Specification Minor Version] + Offset(0xEC), // [EC capability 0] + Offset(0xED), // [EC capability 1] + + Offset(0xEE), // [Highest battery level] + MBTH, 4, // bit 3-0: battery 0 highest level + SBTH, 4, // bit 7-4: battery 1 highest level + // note: if highest level is 0 or 0xF, it means not defined + // (in this case, use default hightest level, it is 6) + + Offset(0xEF), // [EC Function Specification Major Version] + Offset(0xF0), // [Build ID]~ offset:0F7h + + Offset(0xF8), // [Build Date (F8: MSB, F9:LSB)] + , 4, // bit 3-0: day(1-31) + , 4, // bit 7-4: month(1-12) + , 8, // bit 15-8: year(2000 base) + + Offset(0xFA), // [Build Time (in 2seconds)] + // ex: when index FAh=5Ah and index FBh=ADh, Build Time is 5AADh .. 12:53:46 + + Offset(0xFC), // [reserved]~ offset:0FFh } // End of ERAM
// @@ -499,10 +499,10 @@ Device (EC0) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset(0xA0), - // Battery Mode(w) + // Battery Mode(w) , 15, SBCM, 1, // bit 15 - CAPACITY_MODE - // 0: Report in mA/mAh ; 1: Enabled + // 0: Report in mA/mAh ; 1: Enabled SBMD, 16, // Manufacture Data SBCC, 16, // Cycle Count } @@ -575,25 +575,25 @@ Device (EC0) }
/* Attention Codes - * 00h No Event + * 00h No Event * 01h-0Fh Reserved for ACPI Events * 10h-1Fh Hotkey Events - * 22h Critical Low Battery - * 23h Battery Empty - * 24h Trip Point Capacity Event for Battery 0 - * 26h AC Adapter Attached - * 27h AC Adapter Detached - * 28h Power Off Switch Pressed - * 29h Power Off Switch Released - * 2Ah LID Open - * 2Bh LID Close - * 3Eh PME Event - * 40h Thermal Event - * 41h Global Wireless Enable Switch - * 43h Mute State Change - * 4Ah Battery 0 Attach/Detach - * 4Bh Battery 0 State Change - * 66h Mute Button + * 22h Critical Low Battery + * 23h Battery Empty + * 24h Trip Point Capacity Event for Battery 0 + * 26h AC Adapter Attached + * 27h AC Adapter Detached + * 28h Power Off Switch Pressed + * 29h Power Off Switch Released + * 2Ah LID Open + * 2Bh LID Close + * 3Eh PME Event + * 40h Thermal Event + * 41h Global Wireless Enable Switch + * 43h Mute State Change + * 4Ah Battery 0 Attach/Detach + * 4Bh Battery 0 State Change + * 66h Mute Button */
// Battery at critical low state diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 4798cee..938b7ac 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -185,13 +185,13 @@ static void it8518_enable_resources(device_t dev) }
static struct device_operations ops = { - .init = it8518_init, + .init = it8518_init, .read_resources = it8518_read_resources, .enable_resources = it8518_enable_resources };
static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } };
static void enable_dev(device_t dev) diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index f3a2d38..7bd4591 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -30,60 +30,60 @@ #define EC_IO_DATA EC_IO + 3
/* Wait 400ms for keyboard controller answers */ -#define KBC_TIMEOUT_IN_MS 400 +#define KBC_TIMEOUT_IN_MS 400
// 60h/64h Command Interface -#define KBD_DATA 0x60 -#define KBD_COMMAND 0x64 -#define KBD_STATUS 0x64 -#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
-#define EC_KBD_SMI_EVENT 0xCD -#define EC_KBD_CMD_UNMUTE 0xE8 -#define EC_KBD_CMD_MUTE 0xE9 +#define EC_KBD_SMI_EVENT 0xCD +#define EC_KBD_CMD_UNMUTE 0xE8 +#define EC_KBD_CMD_MUTE 0xE9
u8 ec_kbc_read_ob(void); void ec_kbc_write_cmd(u8 cmd); void ec_kbc_write_ib(u8 data);
// 62h/66h Command Interface -#define EC_DATA 0x62 -#define EC_SC 0x66 // Status & Control Register -#define SMI_EVT (1 << 6) // 1: SMI event was triggered -#define SCI_EVT (1 << 5) // 1: SCI event was triggered +#define EC_DATA 0x62 +#define EC_SC 0x66 // Status & Control Register +#define SMI_EVT (1 << 6) // 1: SMI event was triggered +#define SCI_EVT (1 << 5) // 1: SCI event was triggered
// EC Commands (defined in ec_function_spec v3.12) -#define RD_EC 0x80 -#define WR_EC 0x81 -#define QR_EC 0x84 +#define RD_EC 0x80 +#define WR_EC 0x81 +#define QR_EC 0x84
-#define EC_CMD_EXIT_BOOT_BLOCK 0x85 +#define EC_CMD_EXIT_BOOT_BLOCK 0x85 #define EC_CMD_NOTIFY_ACPI_ENTER 0x86 -#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 -#define EC_CMD_WARM_RESET 0x8C +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 +#define EC_CMD_WARM_RESET 0x8C
// ECRAM Offsets -#define EC_PERIPH_CNTL_3 0x0D -#define EC_USB_S3_EN 0x26 -#define EC_PERIPH_STAT_3 0x35 -#define EC_THERM_0 0x78 -#define EC_WAKE_SRC_ENABLE 0xBF -#define EC_FW_VER 0xE8 // 2 Bytes -#define EC_IF_MIN_VER 0xEB -#define EC_STATUS_REG 0xEC -#define EC_IF_MAJ_VER 0xEF -#define EC_MBAT_STATUS 0x0138 +#define EC_PERIPH_CNTL_3 0x0D +#define EC_USB_S3_EN 0x26 +#define EC_PERIPH_STAT_3 0x35 +#define EC_THERM_0 0x78 +#define EC_WAKE_SRC_ENABLE 0xBF +#define EC_FW_VER 0xE8 // 2 Bytes +#define EC_IF_MIN_VER 0xEB +#define EC_STATUS_REG 0xEC +#define EC_IF_MAJ_VER 0xEF +#define EC_MBAT_STATUS 0x0138
// EC 0.83b added status bits: // BIT0=EC in RO mode // BIT1=Recovery Key Sequence Detected -#define EC_IN_RO_MODE 0x1 -#define EC_IN_RECOVERY_MODE 0x3 +#define EC_IN_RO_MODE 0x1 +#define EC_IN_RECOVERY_MODE 0x3
// EC 0.86a added enable bit: -#define EC_LID_WAKE_ENABLE 0x4 +#define EC_LID_WAKE_ENABLE 0x4
u8 ec_read_ob(void); void ec_write_cmd(u8 cmd); diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl index 9b2f93b..c304e2c 100644 --- a/src/ec/smsc/mec1308/acpi/battery.asl +++ b/src/ec/smsc/mec1308/acpi/battery.asl @@ -46,10 +46,10 @@ Device (BAT0) 0xFFFFFFFF, // Design Capacity of Low 0x00000001, // Capacity Granularity 1 0x00000001, // Capacity Granularity 2 - "", // Model Number - "", // Serial Number + "", // Model Number + "", // Serial Number "LION", // Battery Type - "" // OEM Information + "" // OEM Information })
Name (PBST, Package () { @@ -153,7 +153,7 @@ Device (BAT0)
Store (SWAB (BTPR), Local1) If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), - LGreaterEqual (Local1, 0x8000))) { + LGreaterEqual (Local1, 0x8000))) { Xor (Local1, 0xFFFF, Local1) Increment (Local1) } @@ -164,7 +164,7 @@ Device (BAT0) // Store (SWAB (BTRA), Local1) If (LAnd (LNotEqual (Local1, 0xFFFFFFFF), - LGreaterEqual (Local1, 0x8000))) { + LGreaterEqual (Local1, 0x8000))) { Xor (Local1, 0xFFFF, Local1) Increment (Local1) } @@ -179,7 +179,7 @@ Device (BAT0) // See if within ~3% of full ShiftRight (Local2, 5, Local3) If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) + LLess (Local1, Add (Local2, Local3)))) { Store (Local2, Local1) } diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c index fdae5e4..14ccb58 100644 --- a/src/ec/smsc/mec1308/ec.c +++ b/src/ec/smsc/mec1308/ec.c @@ -47,7 +47,7 @@ static int ec_ready(void)
if (!ec_cmd_reg || !ec_data_reg) { printk(BIOS_DEBUG, "Invalid ports: cmd=0x%x data=0x%x\n", - ec_cmd_reg, ec_data_reg); + ec_cmd_reg, ec_data_reg); return -1; }
diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h index 07bfc4f..286b737 100644 --- a/src/ec/smsc/mec1308/ec.h +++ b/src/ec/smsc/mec1308/ec.h @@ -22,12 +22,12 @@ #ifndef _EC_SMSC_MEC1308_EC_H #define _EC_SMSC_MEC1308_EC_H
-#define EC_TIMEOUT 0xfff +#define EC_TIMEOUT 0xfff #define EC_MAILBOX_COMMAND 0x82 // Send a command -#define EC_MAILBOX_DATA 0x84 // Send data with a command +#define EC_MAILBOX_DATA 0x84 // Send data with a command #define EC_MAILBOX_DATA_H 0x85 // Send data with a command -#define EC_RAM_READ 0x88 // Read from RAM -#define EC_RAM_WRITE 0x89 // Write to RAM +#define EC_RAM_READ 0x88 // Read from RAM +#define EC_RAM_WRITE 0x89 // Write to RAM
int send_ec_command(u8 command); int send_ec_command_data(u8 command, u8 data); diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 87819ce..16bdeca 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -10,7 +10,7 @@ * * All of the information should be Position Independent Data. * That is it should be safe to relocated any of the information - * without it's meaning/correctness changing. For table that + * without it's meaning/correctness changing. For table that * can reasonably be used on multiple architectures the data * size should be fixed. This should ease the transition between * 32 bit and 64 bit architectures etc. @@ -202,7 +202,7 @@ struct lb_gpio { uint32_t polarity; uint32_t value; #define GPIO_MAX_NAME_LENGTH 16 - uint8_t name[GPIO_MAX_NAME_LENGTH]; + uint8_t name[GPIO_MAX_NAME_LENGTH]; };
struct lb_gpios { @@ -262,55 +262,55 @@ struct lb_x86_rom_mtrr { #define LB_TAG_CMOS_OPTION_TABLE 200 /* cmos header record */ struct cmos_option_table { - uint32_t tag; /* CMOS definitions table type */ - uint32_t size; /* size of the entire table */ + uint32_t tag; /* CMOS definitions table type */ + uint32_t size; /* size of the entire table */ uint32_t header_length; /* length of header */ };
/* cmos entry record - This record is variable length. The name field may be - shorter than CMOS_MAX_NAME_LENGTH. The entry may start - anywhere in the byte, but can not span bytes unless it - starts at the beginning of the byte and the length is - fills complete bytes. + This record is variable length. The name field may be + shorter than CMOS_MAX_NAME_LENGTH. The entry may start + anywhere in the byte, but can not span bytes unless it + starts at the beginning of the byte and the length is + fills complete bytes. */ #define LB_TAG_OPTION 201 struct cmos_entries { - uint32_t tag; /* entry type */ - uint32_t size; /* length of this record */ - uint32_t bit; /* starting bit from start of image */ - uint32_t length; /* length of field in bits */ - uint32_t config; /* e=enumeration, h=hex, r=reserved */ - uint32_t config_id; /* a number linking to an enumeration record */ + uint32_t tag; /* entry type */ + uint32_t size; /* length of this record */ + uint32_t bit; /* starting bit from start of image */ + uint32_t length; /* length of field in bits */ + uint32_t config; /* e=enumeration, h=hex, r=reserved */ + uint32_t config_id; /* a number linking to an enumeration record */ #define CMOS_MAX_NAME_LENGTH 32 uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name of entry in ascii, - variable length int aligned */ + variable length int aligned */ };
/* cmos enumerations record - This record is variable length. The text field may be - shorter than CMOS_MAX_TEXT_LENGTH. + This record is variable length. The text field may be + shorter than CMOS_MAX_TEXT_LENGTH. */ #define LB_TAG_OPTION_ENUM 202 struct cmos_enums { uint32_t tag; /* enumeration type */ uint32_t size; /* length of this record */ - uint32_t config_id; /* a number identifying the config id */ - uint32_t value; /* the value associated with the text */ + uint32_t config_id; /* a number identifying the config id */ + uint32_t value; /* the value associated with the text */ #define CMOS_MAX_TEXT_LENGTH 32 uint8_t text[CMOS_MAX_TEXT_LENGTH]; /* enum description in ascii, variable length int aligned */ };
/* cmos defaults record - This record contains default settings for the cmos ram. + This record contains default settings for the cmos ram. */ #define LB_TAG_OPTION_DEFAULTS 203 struct cmos_defaults { - uint32_t tag; /* default type */ - uint32_t size; /* length of this record */ - uint32_t name_length; /* length of the following name field */ + uint32_t tag; /* default type */ + uint32_t size; /* length of this record */ + uint32_t name_length; /* length of the following name field */ uint8_t name[CMOS_MAX_NAME_LENGTH]; /* name identifying the default */ #define CMOS_IMAGE_BUFFER_SIZE 256 uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 46662d5..2b31cfd 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -30,10 +30,10 @@ * states. Upon a state's entry and exit and callbacks can be made. For * example: * - * Enter State - * + - * | - * V + * Enter State + * + + * | + * V * +-----------------+ * | Entry callbacks | * +-----------------+ @@ -41,37 +41,37 @@ * +-----------------+ * | Exit callbacks | * +-------+---------+ - * | - * V - * Next State + * | + * V + * Next State * * Below is the current flow from top to bottom: * - * start - * | + * start + * | * BS_PRE_DEVICE - * | + * | * BS_DEV_INIT_CHIPS - * | + * | * BS_DEV_ENUMERATE - * | + * | * BS_DEV_RESOURCES - * | + * | * BS_DEV_ENABLE - * | + * | * BS_DEV_INIT - * | + * | * BS_POST_DEVICE - * | + * | * BS_OS_RESUME_CHECK -------- BS_OS_RESUME - * | | - * BS_WRITE_TABLES os handoff - * | + * | | + * BS_WRITE_TABLES os handoff + * | * BS_PAYLOAD_LOAD - * | + * | * BS_PAYLOAD_BOOT - * | - * payload run + * | + * payload run * * Brief description of states: * BS_PRE_DEVICE - before any device tree actions take place @@ -152,9 +152,9 @@ struct boot_state_callback { * individual callbacks on a given state. 0 is returned on success < 0 on * error. */ int boot_state_sched_on_entry(struct boot_state_callback *bscb, - boot_state_t state); + boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, - boot_state_t state); + boot_state_t state);
/* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..f9f78ab 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -66,11 +66,11 @@ struct cbfs_simple_buffer { };
void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count); + struct cbfs_media *media, + size_t offset, size_t count);
void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address); + const void *address);
// Utility functions int run_address(void *f); @@ -99,12 +99,12 @@ struct cbmem_entry; * ramstage. */ void __attribute__((weak)) cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point); + const struct cbmem_entry *ramstage, void *entry_point); /* Return NULL on error or entry point on success. The ramstage cbmem_entry is * the region where to load the cached contents to. */ void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage); + const struct cbmem_entry *ramstage); #endif /* CONFIG_RELOCATABLE_RAMSTAGE */
#endif diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 08fe815..b071a03 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -68,13 +68,13 @@ Users are welcome to use any other value for their components */
-#define CBFS_TYPE_STAGE 0x10 +#define CBFS_TYPE_STAGE 0x10 #define CBFS_TYPE_PAYLOAD 0x20 #define CBFS_TYPE_OPTIONROM 0x30 #define CBFS_TYPE_BOOTSPLASH 0x40 -#define CBFS_TYPE_RAW 0x50 -#define CBFS_TYPE_VSA 0x51 -#define CBFS_TYPE_MBI 0x52 +#define CBFS_TYPE_RAW 0x50 +#define CBFS_TYPE_VSA 0x51 +#define CBFS_TYPE_MBI 0x52 #define CBFS_TYPE_MICROCODE 0x53 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa #define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa @@ -106,8 +106,8 @@ struct cbfs_header { * before the architecture was defined (i.e., x86 only). */ #define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF -#define CBFS_ARCHITECTURE_X86 0x00000001 -#define CBFS_ARCHITECTURE_ARMV7 0x00000010 +#define CBFS_ARCHITECTURE_X86 0x00000001 +#define CBFS_ARCHITECTURE_ARMV7 0x00000010
/** This is a component header - every entry in the CBFS will have this header. @@ -145,8 +145,8 @@ struct cbfs_file { struct cbfs_stage { uint32_t compression; /** Compression type */ uint64_t entry; /** entry point */ - uint64_t load; /** Where to load in memory */ - uint32_t len; /** length of data to load */ + uint64_t load; /** Where to load in memory */ + uint32_t len; /** length of data to load */ uint32_t memlen; /** total length of object in memory */ } __attribute__((packed));
@@ -195,7 +195,7 @@ struct cbfs_media { /* returns number of bytes read from media into dest, starting from * offset for count of bytes */ size_t (*read)(struct cbfs_media *media, void *dest, size_t offset, - size_t count); + size_t count);
/* returns a pointer to memory with count of bytes from media source * starting from offset, or CBFS_MEDIA_INVALID_MAP_ADDRESS on failure. diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b3d3fff..46cdd21 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -57,7 +57,7 @@ #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_RESUME_SCRATCH 0x52455343 -#define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_CONSOLE 0x434f4e53 diff --git a/src/include/console/console.h b/src/include/console/console.h index 5750b4a..43df868 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -105,109 +105,109 @@ static inline void printk(int LEVEL, const char *fmt, ...) {
#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */
-#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) -#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) -#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) -#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) -#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) -#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) -#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) -#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) -#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) - -#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) -#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) -#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) -#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) -#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) -#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) -#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) -#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) -#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) - -#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) -#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) -#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) -#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) #define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) -#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) -#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) -#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) -#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) - -#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) -#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) -#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) -#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) + +#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) +#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) +#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) +#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) #define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) #define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) -#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) -#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) -#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) - -#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) -#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) -#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) -#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) +#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) +#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) +#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) + +#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) +#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) +#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) +#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) #define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) #define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) -#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) -#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) -#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) +#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) +#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) +#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX))
#else
/* __ROMCC__ */
-#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) -#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) -#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) -#define print_err(STR) __console_tx_string(BIOS_ERR, STR) -#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) -#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) -#define print_info(STR) __console_tx_string(BIOS_INFO, STR) -#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) -#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) - -#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) -#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) -#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) -#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) -#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) -#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) -#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) -#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) -#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) - -#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) -#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) -#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) -#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) +#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) +#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) +#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) +#define print_err(STR) __console_tx_string(BIOS_ERR, STR) +#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) +#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) +#define print_info(STR) __console_tx_string(BIOS_INFO, STR) +#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) +#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) + +#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) +#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) +#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) +#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) +#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) +#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) +#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) +#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) +#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) + +#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) +#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) +#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) +#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) #define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) -#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) -#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) -#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) -#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) - -#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) -#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) -#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) -#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) +#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) +#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) +#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) +#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) + +#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) +#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) +#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) +#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) #define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) #define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) -#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) -#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) -#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) - -#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) -#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) -#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) -#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) +#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) +#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) +#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) + +#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) +#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) +#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) +#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) #define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) #define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) -#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) -#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) -#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) +#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) +#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) +#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX)
#include "arch/x86/lib/romcc_console.c"
diff --git a/src/include/console/loglevel.h b/src/include/console/loglevel.h index 290cd89..8cc4a8a 100644 --- a/src/include/console/loglevel.h +++ b/src/include/console/loglevel.h @@ -2,15 +2,15 @@ #define LOGLEVEL_H
/* Safe for inclusion in assembly */ -#define BIOS_EMERG 0 /* system is unusable */ -#define BIOS_ALERT 1 /* action must be taken immediately */ -#define BIOS_CRIT 2 /* critical conditions */ -#define BIOS_ERR 3 /* error conditions */ -#define BIOS_WARNING 4 /* warning conditions */ -#define BIOS_NOTICE 5 /* normal but significant condition */ -#define BIOS_INFO 6 /* informational */ -#define BIOS_DEBUG 7 /* debug-level messages */ -#define BIOS_SPEW 8 /* way too many details */ +#define BIOS_EMERG 0 /* system is unusable */ +#define BIOS_ALERT 1 /* action must be taken immediately */ +#define BIOS_CRIT 2 /* critical conditions */ +#define BIOS_ERR 3 /* error conditions */ +#define BIOS_WARNING 4 /* warning conditions */ +#define BIOS_NOTICE 5 /* normal but significant condition */ +#define BIOS_INFO 6 /* informational */ +#define BIOS_DEBUG 7 /* debug-level messages */ +#define BIOS_SPEW 8 /* way too many details */ #define BIOS_NEVER 9 /* these messages are never printed */
#endif /* LOGLEVEL_H */ diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index fd8d960..2fe2a30 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -31,7 +31,7 @@ typedef signed int INT32; typedef unsigned long long UINT64; typedef unsigned char BOOLEAN;
-#define DMSG_SB_TRACE 0x02 +#define DMSG_SB_TRACE 0x02 #define TRACE(Arguments)
#ifndef TRUE diff --git a/src/include/cpu/amd/gx1def.h b/src/include/cpu/amd/gx1def.h index ee36a68..1a284e3 100644 --- a/src/include/cpu/amd/gx1def.h +++ b/src/include/cpu/amd/gx1def.h @@ -12,7 +12,7 @@ /* Display Controller Registers, offset from GX_BASE */
#define DC_UNLOCK 0x8300 -#define DC_UNLOCK_MAGIC 0x4758 +#define DC_UNLOCK_MAGIC 0x4758
#define DC_GENERAL_CFG 0x8304
@@ -29,24 +29,24 @@ /* Memory Controller Registers, offset from GX_BASE */
#define MC_MEM_CNTRL1 0x8400 -#define SDCLKSTRT (1<<17) -#define RFSHRATE (0x1ff<<8) -#define RFSHSTAG (0x3<<6) +#define SDCLKSTRT (1<<17) +#define RFSHRATE (0x1ff<<8) +#define RFSHSTAG (0x3<<6) #define X2CLKADDR (1<<5) #define RFSHTST (1<<4) #define XBUSARB (1<<3) #define SMM_MAP (1<<2) -#define PROGRAM_SDRAM (1<<0) +#define PROGRAM_SDRAM (1<<0)
#define MC_MEM_CNTRL2 0x8404 -#define SDCLK_MASK 0x000003c0 -#define SDCLKOUT_MASK 0x00000400 +#define SDCLK_MASK 0x000003c0 +#define SDCLKOUT_MASK 0x00000400
#define MC_BANK_CFG 0x8408 -#define DIMM_PG_SZ 0x00000070 -#define DIMM_SZ 0x00000700 -#define DIMM_COMP_BNK 0x00001000 -#define DIMM_MOD_BNK 0x00004000 +#define DIMM_PG_SZ 0x00000070 +#define DIMM_SZ 0x00000700 +#define DIMM_COMP_BNK 0x00001000 +#define DIMM_MOD_BNK 0x00004000
#define MC_SYNC_TIM1 0x840c
diff --git a/src/include/cpu/amd/model_fxx_msr.h b/src/include/cpu/amd/model_fxx_msr.h index 2ac2d4e..817f74c 100644 --- a/src/include/cpu/amd/model_fxx_msr.h +++ b/src/include/cpu/amd/model_fxx_msr.h @@ -7,7 +7,7 @@
#define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 +#define LS_CFG_MSR 0xC0011020 #define IC_CFG_MSR 0xC0011021 #define DC_CFG_MSR 0xC0011022 #define BU_CFG_MSR 0xC0011023 diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index 1e85596..79c0fcf 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -9,69 +9,69 @@ static inline int is_cpu_rev_a0(void) } static inline int is_cpu_pre_c0(void) { - return (cpuid_eax(1) & 0xfffef) < 0x0f48; + return (cpuid_eax(1) & 0xfffef) < 0x0f48; }
static inline int is_cpu_c0(void) { - return (cpuid_eax(1) & 0xfffef) == 0x0f48; + return (cpuid_eax(1) & 0xfffef) == 0x0f48; }
static inline int is_cpu_pre_b3(void) { - return (cpuid_eax(1) & 0xfffef) < 0x0f41; + return (cpuid_eax(1) & 0xfffef) < 0x0f41; }
static inline int is_cpu_b3(void) { - return (cpuid_eax(1) & 0xfffef) == 0x0f41; + return (cpuid_eax(1) & 0xfffef) == 0x0f41; } //AMD_D0_SUPPORT static inline int is_cpu_pre_d0(void) { - return (cpuid_eax(1) & 0xfff0f) < 0x10f00; + return (cpuid_eax(1) & 0xfff0f) < 0x10f00; }
static inline int is_cpu_d0(void) { - return (cpuid_eax(1) & 0xfff0f) == 0x10f00; + return (cpuid_eax(1) & 0xfff0f) == 0x10f00; }
//AMD_E0_SUPPORT static inline int is_cpu_pre_e0(void) { - return (cpuid_eax(1) & 0xfff0f) < 0x20f00; + return (cpuid_eax(1) & 0xfff0f) < 0x20f00; }
static inline int is_cpu_e0(void) { - return (cpuid_eax(1) & 0xfff00) == 0x20f00; + return (cpuid_eax(1) & 0xfff00) == 0x20f00; }
#ifdef __PRE_RAM__ static int is_e0_later_in_bsp(int nodeid) { - uint32_t val; - uint32_t val_old; - int e0_later; - if(nodeid==0) { // we don't need to do that for node 0 in core0/node0 - return !is_cpu_pre_e0(); - } - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; - dev = PCI_DEV(0, 0x18+nodeid,2); - val_old = pci_read_config32(dev, 0x80); - val = val_old; - val |= (1<<3); - pci_write_config32(dev, 0x80, val); - val = pci_read_config32(dev, 0x80); - e0_later = !!(val & (1<<3)); - if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed - pci_write_config32(dev, 0x80, val_old); // restore it - } - - return e0_later; + uint32_t val; + uint32_t val_old; + int e0_later; + if(nodeid==0) { // we don't need to do that for node 0 in core0/node0 + return !is_cpu_pre_e0(); + } + // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 + device_t dev; + dev = PCI_DEV(0, 0x18+nodeid,2); + val_old = pci_read_config32(dev, 0x80); + val = val_old; + val |= (1<<3); + pci_write_config32(dev, 0x80, val); + val = pci_read_config32(dev, 0x80); + e0_later = !!(val & (1<<3)); + if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed + pci_write_config32(dev, 0x80, val_old); // restore it + } + + return e0_later; } #else int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c @@ -83,17 +83,17 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c //AMD_F0_SUPPORT static inline int is_cpu_pre_f0(void) { - return (cpuid_eax(1) & 0xfff0f) < 0x40f00; + return (cpuid_eax(1) & 0xfff0f) < 0x40f00; }
static inline int is_cpu_f0(void) { - return (cpuid_eax(1) & 0xfff00) == 0x40f00; + return (cpuid_eax(1) & 0xfff00) == 0x40f00; }
static inline int is_cpu_pre_f2(void) { - return (cpuid_eax(1) & 0xfff0f) < 0x40f02; + return (cpuid_eax(1) & 0xfff0f) < 0x40f02; }
#ifdef __PRE_RAM__ @@ -104,15 +104,15 @@ static inline int is_cpu_f0_in_bsp(int nodeid) device_t dev; dev = PCI_DEV(0, 0x18+nodeid, 3); dword = pci_read_config32(dev, 0xfc); - return (dword & 0xfff00) == 0x40f00; + return (dword & 0xfff00) == 0x40f00; } static inline int is_cpu_pre_f2_in_bsp(int nodeid) { - uint32_t dword; + uint32_t dword; device_t dev; - dev = PCI_DEV(0, 0x18+nodeid, 3); - dword = pci_read_config32(dev, 0xfc); - return (dword & 0xfff0f) < 0x40f02; + dev = PCI_DEV(0, 0x18+nodeid, 3); + dword = pci_read_config32(dev, 0xfc); + return (dword & 0xfff0f) < 0x40f02; } #else int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c diff --git a/src/include/cpu/amd/sc520.h b/src/include/cpu/amd/sc520.h index c79e99e..3e99e5d 100644 --- a/src/include/cpu/amd/sc520.h +++ b/src/include/cpu/amd/sc520.h @@ -17,9 +17,9 @@ struct parreg { #define MMCRPIC (struct mmcrpic *) 0xfffefd00 //static volatile struct mmcrpic *pic = MMCRPIC;
-#define M_GINT_MODE 1 -#define M_S1_MODE 2 -#define M_S2_MODE 4 +#define M_GINT_MODE 1 +#define M_S1_MODE 2 +#define M_S2_MODE 4
/* here is the real mmcr struct */ @@ -151,7 +151,7 @@ struct gptimers { struct watchdog { unsigned short ctl; unsigned short cntll; - unsigned short cntlh; + unsigned short cntlh; unsigned char pad[10]; };
diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index 805b977..1699b41 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -13,44 +13,44 @@ #define NO_VR -1 // No virtual registers
#define VRC_MISCELLANEOUS 0x00 // Miscellaneous Class - #define VSA_VERSION_NUM 0x00 + #define VSA_VERSION_NUM 0x00 #define HIGH_MEM_ACCESS 0x01 - #define GET_VSM_INFO 0x02 // Used by INFO - #define GET_BASICS 0x00 - #define GET_EVENT 0x01 - #define GET_STATISTICS 0x02 - #define GET_HISTORY 0x03 - #define GET_HARDWARE 0x04 - #define GET_ERROR 0x05 - #define SET_VSM_TYPE 0x06 + #define GET_VSM_INFO 0x02 // Used by INFO + #define GET_BASICS 0x00 + #define GET_EVENT 0x01 + #define GET_STATISTICS 0x02 + #define GET_HISTORY 0x03 + #define GET_HARDWARE 0x04 + #define GET_ERROR 0x05 + #define SET_VSM_TYPE 0x06 #define SIGNATURE 0x03 #define VSA2_SIGNATURE 0x56534132 // 'VSA2' returned in EAX
#define GET_HW_INFO 0x04 #define VSM_VERSION 0x05 #define CTRL_ALT_DEL 0x06 - #define MSR_ACCESS 0x07 + #define MSR_ACCESS 0x07 #define GET_DESCR_INFO 0x08 #define PCI_INT_AB 0x09 // GPIO pins for INTA# and INTB# #define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD# #define WATCHDOG 0x0B // Watchdog timer
- #define MAX_MISC WATCHDOG + #define MAX_MISC WATCHDOG
// NOTE: Do not change the order of the following registers: #define VRC_AUDIO 0x01 // XpressAudio Class - #define AUDIO_VERSION 0x00 - #define PM_STATE 0x01 - #define SB_16_IO_BASE 0x02 - #define MIDI_BASE 0x03 - #define CPU_USAGE 0x04 - #define CODEC_TYPE 0x05 - #define STATE_INDEX 0x06 - #define STATE_DATA 0x07 - #define AUDIO_IRQ 0x08 // For use by native audio drivers + #define AUDIO_VERSION 0x00 + #define PM_STATE 0x01 + #define SB_16_IO_BASE 0x02 + #define MIDI_BASE 0x03 + #define CPU_USAGE 0x04 + #define CODEC_TYPE 0x05 + #define STATE_INDEX 0x06 + #define STATE_DATA 0x07 + #define AUDIO_IRQ 0x08 // For use by native audio drivers #define STATUS_PTR 0x09 // For use by native audio drivers - #define MAX_AUDIO STATUS_PTR + #define MAX_AUDIO STATUS_PTR
#define VRC_VG 0x02 // SoftVG Class #define VRC_VGA 0x02 // SoftVGA Class @@ -189,16 +189,16 @@ // SAA7127 - Not Used // ADV7300 - HDTV resolutions only // LO -> 720x480p - // MED -> 1280x720p + // MED -> 1280x720p // HI -> 1920x1080i // FS454 - Both SD and HD resolutions // SD Resolutions - NTSC and PAL // LO -> 640x480 - // MED -> 800x600 + // MED -> 800x600 // HI -> 1024x768 // HD Resolutions // LO -> 720x480p - // MED -> 1280x720p + // MED -> 1280x720p // HI -> 1920x1080i #define VG_TV_RES 0x0780 // TV resolution select mask #define VG_TV_RES_SHIFT 0x0007 // Right shift value @@ -237,16 +237,16 @@ #define VG_FT_VESST 0x2C // Fixed timings, vertical sync start #define VG_FT_VESND 0x2D // Fixed timings, vertical sync end
- #define MAX_VGA VGA_MEM_SIZE -// #define MAX_VG VG_FP_OPTION -// #define MAX_VG VG_START_OFFS_HI - #define MAX_VG VG_FT_VESND + #define MAX_VGA VGA_MEM_SIZE +// #define MAX_VG VG_FP_OPTION +// #define MAX_VG VG_START_OFFS_HI + #define MAX_VG VG_FT_VESND
#define VRC_APM 0x03 #define REPORT_EVENT 0x00 #define CAPABILITIES 0x01 #define APM_PRESENT 0x02 - #define MAX_APM APM_PRESENT + #define MAX_APM APM_PRESENT
#define VRC_PM 0x04 // Legacy PM Class @@ -275,12 +275,12 @@ // #define PM_S3_CLOCKS 0x14 // #define PM_S4_CLOCKS 0x15 // #define PM_S5_CLOCKS 0x16 - #define PM_S0_LED 0x17 - #define PM_S1_LED 0x18 - #define PM_S2_LED 0x19 - #define PM_S3_LED 0x1A - #define PM_S4_LED 0x1B - #define PM_S5_LED 0x1C + #define PM_S0_LED 0x17 + #define PM_S1_LED 0x18 + #define PM_S2_LED 0x19 + #define PM_S3_LED 0x1A + #define PM_S4_LED 0x1B + #define PM_S5_LED 0x1C #define PM_LED_GPIO 0x1D #define PM_IMM_LED 0x1E #define PM_PWR_LEDS 0x1F @@ -293,11 +293,11 @@ #define SIO_LED2 0x40 #define SIO_LED3 0x80 #define PM_PME_MASK 0x20 - #define MAX_PM PM_PME_MASK + #define MAX_PM PM_PME_MASK
#define VRC_INFRARED 0x05 - #define MAX_INFRARED NO_VR + #define MAX_INFRARED NO_VR
#define VRC_TV 0x06 // TV Encoder Class #define TV_ENCODER_TYPE 0x00 @@ -308,16 +308,16 @@ #define TV_CONTRAST 0x05 #define TV_OUTPUT 0x06 #define TV_TIMING 0x10 // 0x10...0x1D are all timings - #define MAX_TV TV_TIMING + #define MAX_TV TV_TIMING
#define VRC_EXTERNAL_AMP 0x07 - #define EAPD_VERSION 0x00 - #define AMP_POWER 0x01 - #define AMP_OFF 0x00 - #define AMP_ON 0x01 - #define AMP_TYPE 0x02 + #define EAPD_VERSION 0x00 + #define AMP_POWER 0x01 + #define AMP_OFF 0x00 + #define AMP_ON 0x01 + #define AMP_TYPE 0x02 #define MAX_EXTERNAL_AMP AMP_TYPE
@@ -340,46 +340,46 @@ #define ACPI_GEN_PARAM2 0x0F #define ACPI_GEN_PARAM3 0x10 #define ACPI_GEN_RETVAL 0x11 - #define MAX_ACPI ACPI_GEN_RETVAL + #define MAX_ACPI ACPI_GEN_RETVAL
#define VRC_ACPI_OEM 0x09 - #define MAX_ACPI_OEM NO_VR + #define MAX_ACPI_OEM NO_VR
-#define VRC_POWER 0x0A - #define BATTERY_UNITS 0x00 // No. battery units - #define BATTERY_SELECT 0x01 - #define AC_STATUS 0x02 +#define VRC_POWER 0x0A + #define BATTERY_UNITS 0x00 // No. battery units + #define BATTERY_SELECT 0x01 + #define AC_STATUS 0x02 #define BATTERY_STATUS 0x03 #define BATTERY_FLAG 0x04 #define BATTERY_PERCENTAGE 0x05 - #define BATTERY_TIME 0x06 - #define MAX_POWER BATTERY_TIME + #define BATTERY_TIME 0x06 + #define MAX_POWER BATTERY_TIME
#define VRC_OHCI 0x0B // OHCI Class - #define SET_LED 0x00 + #define SET_LED 0x00 #define INIT_OHCI 0x01 - #define MAX_OHCI INIT_OHCI + #define MAX_OHCI INIT_OHCI
-#define VRC_KEYBOARD 0x0C // Kbd Controller Class - #define KEYBOARD_PRESENT 0x00 - #define SCANCODE 0x01 +#define VRC_KEYBOARD 0x0C // Kbd Controller Class + #define KEYBOARD_PRESENT 0x00 + #define SCANCODE 0x01 #define MOUSE_PRESENT 0x02 - #define MOUSE_BUTTONS 0x03 - #define MOUSE_XY 0x04 - #define MAX_KEYBOARD MOUSE_XY + #define MOUSE_BUTTONS 0x03 + #define MOUSE_XY 0x04 + #define MAX_KEYBOARD MOUSE_XY
-#define VRC_DDC 0x0D // Video DDC Class +#define VRC_DDC 0x0D // Video DDC Class #define VRC_DDC_ENABLE 0x00 // Enable/disable register #define DDC_DISABLE 0x00 #define DDC_ENABLE 0x01 #define VRC_DDC_IO 0x01 // A non-zero value for safety - #define MAX_DDC VRC_DDC_IO + #define MAX_DDC VRC_DDC_IO
#define VRC_DEBUGGER 0x0E - #define MAX_DEBUGGER NO_VR + #define MAX_DEBUGGER NO_VR
#define VRC_STR 0x0F // Virtual Register class @@ -395,7 +395,7 @@ #define VRC_HIB_VERSION 0x03 // Read COP8 version #define VRC_HIB_SERIAL 0x04 // Read 8 byte serial number #define VRC_HIB_USRBTN 0x05 // Read POST button pressed status - #define MAX_COP8 NO_VR + #define MAX_COP8 NO_VR
#define VRC_OWL 0x11 // Virtual Register class #define VRC_OWL_DAC 0x00 // DAC (Backlight) Control @@ -459,18 +459,18 @@ #define VRC_CS_UART2 0x02 #define MAX_CHIPSET VRC_CS_UART2
-#define VRC_THERMAL 0x15 - #define VRC_THERMAL_CURR_RTEMP 0x00 // read only - #define VRC_THERMAL_CURR_LTEMP 0x01 // read only - #define VRC_THERMAL_FAN 0x02 - #define VRC_THERMAL_LOW_THRESHOLD 0x03 +#define VRC_THERMAL 0x15 + #define VRC_THERMAL_CURR_RTEMP 0x00 // read only + #define VRC_THERMAL_CURR_LTEMP 0x01 // read only + #define VRC_THERMAL_FAN 0x02 + #define VRC_THERMAL_LOW_THRESHOLD 0x03 #define VRC_THERMAL_HIGH_THRESHOLD 0x04 - #define VRC_THERMAL_INDEX 0x05 - #define VRC_THERMAL_DATA 0x06 - #define VRC_THERMAL_SMB_ADDRESS 0x07 - #define VRC_THERMAL_SMB_INDEX 0x08 - #define VRC_THERMAL_SMB_DATA 0x09 - #define MAX_THERMAL VRC_THERMAL_SMB_DATA + #define VRC_THERMAL_INDEX 0x05 + #define VRC_THERMAL_DATA 0x06 + #define VRC_THERMAL_SMB_ADDRESS 0x07 + #define VRC_THERMAL_SMB_INDEX 0x08 + #define VRC_THERMAL_SMB_DATA 0x09 + #define MAX_THERMAL VRC_THERMAL_SMB_DATA
#define MAX_VR_CLASS VRC_THERMAL
diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index a31fd9c..642dede 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -47,30 +47,30 @@ #define BBL_CR_BUSY 0x11B #define BBL_CR_CTL3 0x11E
-#define BBLCR3_L2_CONFIGURED (1<<0) +#define BBLCR3_L2_CONFIGURED (1<<0) /* bits [4:1] */ -#define BBLCR3_L2_LATENCY 0x1e +#define BBLCR3_L2_LATENCY 0x1e #define BBLCR3_L2_ECC_CHECK_ENABLE (1<<5) #define BBLCR3_L2_ADDR_PARITY_ENABLE (1<<6) #define BBLCR3_L2_CRTN_PARITY_ENABLE (1<<7) -#define BBLCR3_L2_ENABLED (1<<8) +#define BBLCR3_L2_ENABLED (1<<8) /* bits [17:13] */ -#define BBLCR3_L2_SIZE (0x1f << 13) -#define BBLCR3_L2_SIZE_256K (0x01 << 13) -#define BBLCR3_L2_SIZE_512K (0x02 << 13) -#define BBLCR3_L2_SIZE_1M (0x04 << 13) -#define BBLCR3_L2_SIZE_2M (0x08 << 13) -#define BBLCR3_L2_SIZE_4M (0x10 << 13) +#define BBLCR3_L2_SIZE (0x1f << 13) +#define BBLCR3_L2_SIZE_256K (0x01 << 13) +#define BBLCR3_L2_SIZE_512K (0x02 << 13) +#define BBLCR3_L2_SIZE_1M (0x04 << 13) +#define BBLCR3_L2_SIZE_2M (0x08 << 13) +#define BBLCR3_L2_SIZE_4M (0x10 << 13) /* bits [22:20] */ #define BBLCR3_L2_PHYSICAL_RANGE (0x7 << 20); /* TODO: This bitmask does not agree with Intel's documentation. * Get confirmation one way or another. */ -#define BBLCR3_L2_SUPPLIED_ECC 0x40000 +#define BBLCR3_L2_SUPPLIED_ECC 0x40000
#define BBLCR3_L2_HARDWARE_DISABLE (1<<23) /* Also known as... */ -#define BBLCR3_L2_NOT_PRESENT (1<<23) +#define BBLCR3_L2_NOT_PRESENT (1<<23)
/* L2 commands */ #define L2CMD_RLU 0x0c /* 01100 Data read w/ LRU update */ diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 8bfae60..7b20920 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -41,9 +41,9 @@
/* Speedstep related MSRs */ #define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D +#define IA32_PERF_STS 0x198 +#define IA32_PERF_CTL 0x199 +#define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h index d1646bf..c142da4 100644 --- a/src/include/cpu/x86/bist.h +++ b/src/include/cpu/x86/bist.h @@ -5,7 +5,7 @@ static void report_bist_failure(u32 bist) { if (bist != 0) { #if CONFIG_CACHE_AS_RAM - printk(BIOS_EMERG, "BIST failed: %08x", bist); + printk(BIOS_EMERG, "BIST failed: %08x", bist); #else print_emerg("BIST failed: "); print_emerg_hex32(bist); diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index a448228..6517f04 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -28,7 +28,7 @@ /* * Need two versions because ROMCC chokes on certain clobbers: * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: - * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 + * 0x1559920 asm Internal compiler error: lhs 1 regcm == 0 */
#if defined(__GNUC__) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 40926df..fa6c88f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,8 +25,8 @@ typedef struct msr_struct
typedef struct msrinit_struct { - unsigned index; - msr_t msr; + unsigned index; + msr_t msr; } msrinit_t;
/* The following functions require the always_inline due to AMD diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 017a77e..fd19ebb 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -4,14 +4,14 @@ /* These are the region types */ #define MTRR_TYPE_UNCACHEABLE 0 #define MTRR_TYPE_WRCOMB 1 -/*#define MTRR_TYPE_ 2*/ -/*#define MTRR_TYPE_ 3*/ +/*#define MTRR_TYPE_ 2*/ +/*#define MTRR_TYPE_ 3*/ #define MTRR_TYPE_WRTHROUGH 4 #define MTRR_TYPE_WRPROT 5 #define MTRR_TYPE_WRBACK 6 -#define MTRR_NUM_TYPES 7 +#define MTRR_NUM_TYPES 7
-#define MTRRcap_MSR 0x0fe +#define MTRRcap_MSR 0x0fe #define MTRRdefType_MSR 0x2ff
#define MTRRdefTypeEn (1 << 11) @@ -62,8 +62,8 @@ void x86_setup_mtrrs(void); * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu * above4gb - 2 means dynamically detect number of variable MTRRs available. - * non-zero means handle memory ranges above 4GiB. - * 0 means ignore memory ranges above 4GiB + * non-zero means handle memory ranges above 4GiB. + * 0 means ignore memory ranges above 4GiB */ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void enable_fixed_mtrr(void); diff --git a/src/include/cpu/x86/multiboot.h b/src/include/cpu/x86/multiboot.h index 7bc25a9..ad41366 100644 --- a/src/include/cpu/x86/multiboot.h +++ b/src/include/cpu/x86/multiboot.h @@ -29,19 +29,19 @@ #include <stdint.h>
/* How many bytes from the start of the file we search for the header. */ -#define MB_SEARCH 8192 +#define MB_SEARCH 8192
/* The magic field should contain this. */ -#define MB_MAGIC 0x1BADB002 +#define MB_MAGIC 0x1BADB002
/* This should be in %eax. */ -#define MB_MAGIC2 0x2BADB002 +#define MB_MAGIC2 0x2BADB002
/* The bits in the required part of flags field we don't support. */ -#define MB_UNSUPPORTED 0x0000fffc +#define MB_UNSUPPORTED 0x0000fffc
/* Alignment of multiboot modules. */ -#define MB_MOD_ALIGN 0x00001000 +#define MB_MOD_ALIGN 0x00001000
/* * Flags set in the 'flags' member of the multiboot header. @@ -167,8 +167,8 @@ struct multiboot_info { uint16_t vbe_interface_len; };
-#define MULTIBOOT_MEMORY_AVAILABLE 1 -#define MULTIBOOT_MEMORY_RESERVED 2 +#define MULTIBOOT_MEMORY_AVAILABLE 1 +#define MULTIBOOT_MEMORY_RESERVED 2
struct multiboot_mmap_entry { uint32_t size; diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h index 7465f62..56d3028 100644 --- a/src/include/cpu/x86/post_code.h +++ b/src/include/cpu/x86/post_code.h @@ -3,9 +3,9 @@
#if CONFIG_IO_POST -#define post_code(value) \ - movb $value, %al; \ - outb %al, $CONFIG_IO_POST_PORT +#define post_code(value) \ + movb $value, %al; \ + outb %al, $CONFIG_IO_POST_PORT
#else #define post_code(value) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 607c0f0..326edf6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -431,7 +431,7 @@ struct smm_runtime { } __attribute__ ((packed));
typedef void asmlinkage (*smm_handler_t)(void *arg, int cpu, - const struct smm_runtime *runtime); + const struct smm_runtime *runtime);
#ifdef __SMM__ /* SMM Runtime helpers. */ @@ -448,21 +448,21 @@ void *smm_get_save_state(int cpu);
/* The smm_loader_params structure provides direction to the SMM loader: * - stack_top - optional external stack provided to loader. It must be at - * least per_cpu_stack_size * num_concurrent_stacks in size. + * least per_cpu_stack_size * num_concurrent_stacks in size. * - per_cpu_stack_size - stack size per cpu for smm modules. * - num_concurrent_stacks - number of concurrent cpus in handler needing stack - * optional for setting up relocation handler. + * optional for setting up relocation handler. * - per_cpu_save_state_size - the smm save state size per cpu * - num_concurrent_save_states - number of concurrent cpus needing save state - * space + * space * - handler - optional handler to call. Only used during SMM relocation setup. * - handler_arg - optional argument to handler for SMM relocation setup. For - * loading the SMM module, the handler_arg is filled in with - * the address of the module's parameters (if present). + * loading the SMM module, the handler_arg is filled in with + * the address of the module's parameters (if present). * - runtime - this field is a result only. The SMM runtime location is filled - * into this field so the code doing the loading can manipulate the - * runtime's assumptions. e.g. updating the apic id to cpu map to - * handle sparse apic id space. + * into this field so the code doing the loading can manipulate the + * runtime's assumptions. e.g. updating the apic id to cpu map to + * handle sparse apic id space. */ struct smm_loader_params { void *stack_top; diff --git a/src/include/device/azalia.h b/src/include/device/azalia.h index 1f672fe..34b3c68 100755 --- a/src/include/device/azalia.h +++ b/src/include/device/azalia.h @@ -29,103 +29,103 @@ */
enum AzaliaPinCfgPortConnectivity { - AZALIA_PINCFG_PORT_JACK = 0b00, - AZALIA_PINCFG_PORT_NC = 0b01, - AZALIA_PINCFG_PORT_FIXED = 0b10, - AZALIA_PINCFG_PORT_MULTIPLE = 0b11, + AZALIA_PINCFG_PORT_JACK = 0b00, + AZALIA_PINCFG_PORT_NC = 0b01, + AZALIA_PINCFG_PORT_FIXED = 0b10, + AZALIA_PINCFG_PORT_MULTIPLE = 0b11, };
enum AzaliaPinCfgLocationGross { - AZALIA_PINCFG_LOCATION_EXTERNAL = 0x00, - AZALIA_PINCFG_LOCATION_INTERNAL = 0x10, - AZALIA_PINCFG_LOCATION_EXT_CHASSIS = 0x20, - AZALIA_PINCFG_LOCATION_OTHER = 0x30, + AZALIA_PINCFG_LOCATION_EXTERNAL = 0x00, + AZALIA_PINCFG_LOCATION_INTERNAL = 0x10, + AZALIA_PINCFG_LOCATION_EXT_CHASSIS = 0x20, + AZALIA_PINCFG_LOCATION_OTHER = 0x30, };
enum AzaliaPinCfgLocationFine { AZALIA_PINCFG_LOCATION_NOT_APPLICABLE = 0x00, - AZALIA_PINCFG_LOCATION_REAR = 0x01, - AZALIA_PINCFG_LOCATION_FRONT = 0x02, - AZALIA_PINCFG_LOCATION_LEFT = 0x03, - AZALIA_PINCFG_LOCATION_RIGHT = 0x04, - AZALIA_PINCFG_LOCATION_TOP = 0x05, - AZALIA_PINCFG_LOCATION_BOTTOM = 0x06, + AZALIA_PINCFG_LOCATION_REAR = 0x01, + AZALIA_PINCFG_LOCATION_FRONT = 0x02, + AZALIA_PINCFG_LOCATION_LEFT = 0x03, + AZALIA_PINCFG_LOCATION_RIGHT = 0x04, + AZALIA_PINCFG_LOCATION_TOP = 0x05, + AZALIA_PINCFG_LOCATION_BOTTOM = 0x06, };
enum AzaliaPinCfgLocationSpecial { - AZALIA_PINCFG_LOCATION_REAR_PANEL = 0x07, - AZALIA_PINCFG_LOCATION_DRIVE_BAY = 0x08, - AZALIA_PINCFG_LOCATION_RISER_CARD = 0x17, + AZALIA_PINCFG_LOCATION_REAR_PANEL = 0x07, + AZALIA_PINCFG_LOCATION_DRIVE_BAY = 0x08, + AZALIA_PINCFG_LOCATION_RISER_CARD = 0x17, AZALIA_PINCFG_LOCATION_DIGITAL_DISPLAY = 0x18, - AZALIA_PINCFG_LOCATION_ATAPI = 0x19, - AZALIA_PINCFG_LOCATION_INSIDE_LID = 0x37, - AZALIA_PINCFG_LOCATION_OUTSIDE_LID = 0x38, + AZALIA_PINCFG_LOCATION_ATAPI = 0x19, + AZALIA_PINCFG_LOCATION_INSIDE_LID = 0x37, + AZALIA_PINCFG_LOCATION_OUTSIDE_LID = 0x38, };
enum AzaliaPinCfgDefaultDevice { - AZALIA_PINCFG_DEVICE_LINEOUT = 0x0, - AZALIA_PINCFG_DEVICE_SPEAKER = 0x1, - AZALIA_PINCFG_DEVICE_HP_OUT = 0x2, - AZALIA_PINCFG_DEVICE_CD = 0x3, - AZALIA_PINCFG_DEVICE_SPDIF_OUT = 0x4, - AZALIA_PINCFG_DEVICE_DIGITAL_OUT = 0x5, - AZALIA_PINCFG_DEVICE_MODEM_LINE = 0x6, - AZALIA_PINCFG_DEVICE_MODEM_HANDSET = 0x7, - AZALIA_PINCFG_DEVICE_LINEIN = 0x8, - AZALIA_PINCFG_DEVICE_AUX = 0x9, - AZALIA_PINCFG_DEVICE_MICROPHONE = 0xA, - AZALIA_PINCFG_DEVICE_TELEPHONY = 0xB, - AZALIA_PINCFG_DEVICE_SPDIF_IN = 0xC, - AZALIA_PINCFG_DEVICE_DIGITAL_IN = 0xD, - AZALIA_PINCFG_DEVICE_OTHER = 0xF, + AZALIA_PINCFG_DEVICE_LINEOUT = 0x0, + AZALIA_PINCFG_DEVICE_SPEAKER = 0x1, + AZALIA_PINCFG_DEVICE_HP_OUT = 0x2, + AZALIA_PINCFG_DEVICE_CD = 0x3, + AZALIA_PINCFG_DEVICE_SPDIF_OUT = 0x4, + AZALIA_PINCFG_DEVICE_DIGITAL_OUT = 0x5, + AZALIA_PINCFG_DEVICE_MODEM_LINE = 0x6, + AZALIA_PINCFG_DEVICE_MODEM_HANDSET = 0x7, + AZALIA_PINCFG_DEVICE_LINEIN = 0x8, + AZALIA_PINCFG_DEVICE_AUX = 0x9, + AZALIA_PINCFG_DEVICE_MICROPHONE = 0xA, + AZALIA_PINCFG_DEVICE_TELEPHONY = 0xB, + AZALIA_PINCFG_DEVICE_SPDIF_IN = 0xC, + AZALIA_PINCFG_DEVICE_DIGITAL_IN = 0xD, + AZALIA_PINCFG_DEVICE_OTHER = 0xF, };
enum AzaliaPinCfgConnectionType { - AZALIA_PINCFG_CONN_UNKNOWN = 0x0, + AZALIA_PINCFG_CONN_UNKNOWN = 0x0, AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK = 0x1, - AZALIA_PINCFG_CONN_STEREO_PHONE_JACK = 0x2, - AZALIA_PINCFG_CONN_INTERNAL_ATAPI = 0x3, - AZALIA_PINCFG_CONN_RCA = 0x4, - AZALIA_PINCFG_CONN_OPTICAL = 0x5, - AZALIA_PINCFG_CONN_OTHER_DIGITAL = 0x6, - AZALIA_PINCFG_CONN_OTHER_ANALOG = 0x7, - AZALIA_PINCFG_CONN_DIN_PLUG = 0x8, - AZALIA_PINCFG_CONN_XLR = 0x9, - AZALIA_PINCFG_CONN_MODEM_RJ11 = 0xA, - AZALIA_PINCFG_CONN_COMBINATION = 0xB, - AZALIA_PINCFG_CONN_OTHER = 0xF, + AZALIA_PINCFG_CONN_STEREO_PHONE_JACK = 0x2, + AZALIA_PINCFG_CONN_INTERNAL_ATAPI = 0x3, + AZALIA_PINCFG_CONN_RCA = 0x4, + AZALIA_PINCFG_CONN_OPTICAL = 0x5, + AZALIA_PINCFG_CONN_OTHER_DIGITAL = 0x6, + AZALIA_PINCFG_CONN_OTHER_ANALOG = 0x7, + AZALIA_PINCFG_CONN_DIN_PLUG = 0x8, + AZALIA_PINCFG_CONN_XLR = 0x9, + AZALIA_PINCFG_CONN_MODEM_RJ11 = 0xA, + AZALIA_PINCFG_CONN_COMBINATION = 0xB, + AZALIA_PINCFG_CONN_OTHER = 0xF, };
enum AzaliaPinCfgColor { - AZALIA_PINCFG_COLOR_UNKNOWN = 0x0, - AZALIA_PINCFG_COLOR_BLACK = 0x1, - AZALIA_PINCFG_COLOR_GREY = 0x2, - AZALIA_PINCFG_COLOR_BLUE = 0x3, - AZALIA_PINCFG_COLOR_GREEN = 0x4, - AZALIA_PINCFG_COLOR_RED = 0x5, - AZALIA_PINCFG_COLOR_ORANGE = 0x6, - AZALIA_PINCFG_COLOR_YELLOW = 0x7, - AZALIA_PINCFG_COLOR_PURPLE = 0x8, - AZALIA_PINCFG_COLOR_PINK = 0x9, - AZALIA_PINCFG_COLOR_WHITE = 0xE, - AZALIA_PINCFG_COLOR_OTHER = 0xF, + AZALIA_PINCFG_COLOR_UNKNOWN = 0x0, + AZALIA_PINCFG_COLOR_BLACK = 0x1, + AZALIA_PINCFG_COLOR_GREY = 0x2, + AZALIA_PINCFG_COLOR_BLUE = 0x3, + AZALIA_PINCFG_COLOR_GREEN = 0x4, + AZALIA_PINCFG_COLOR_RED = 0x5, + AZALIA_PINCFG_COLOR_ORANGE = 0x6, + AZALIA_PINCFG_COLOR_YELLOW = 0x7, + AZALIA_PINCFG_COLOR_PURPLE = 0x8, + AZALIA_PINCFG_COLOR_PINK = 0x9, + AZALIA_PINCFG_COLOR_WHITE = 0xE, + AZALIA_PINCFG_COLOR_OTHER = 0xF, };
enum AzaliaPinCfgMisc { - AZALIA_PINCFG_MISC_IGNORE_PRESENCE = 0x1, + AZALIA_PINCFG_MISC_IGNORE_PRESENCE = 0x1, };
union AzaliaPinConfiguration { unsigned int value; struct __attribute__((aligned(4),packed)) { enum AzaliaPinCfgPortConnectivity port:2; - unsigned char location:6; + unsigned char location:6; enum AzaliaPinCfgDefaultDevice device:4; enum AzaliaPinCfgConnectionType connection:4; - enum AzaliaPinCfgColor color:4; - unsigned char misc:4; - unsigned char association:4; - unsigned char sequence:4; + enum AzaliaPinCfgColor color:4; + unsigned char misc:4; + unsigned char association:4; + unsigned char sequence:4; }; };
diff --git a/src/include/device/device.h b/src/include/device/device.h index c1a2c3d..6faa83e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -63,7 +63,7 @@ struct bus { unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ - unsigned char cap; /* PCi capability offset */ + unsigned char cap; /* PCi capability offset */ unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; }; @@ -77,7 +77,7 @@ struct pci_irq_info { unsigned int ioapic_irq_pin; unsigned int ioapic_src_pin; unsigned int ioapic_dst_id; - unsigned int ioapic_flags; + unsigned int ioapic_flags; };
struct device { @@ -95,9 +95,9 @@ struct device { u16 subsystem_device; unsigned int class; /* 3 bytes: (base, sub, prog-if) */ unsigned int hdr_type; /* PCI header type */ - unsigned int enabled : 1; /* set if we should enable the device */ - unsigned int initialized : 1; /* set if we have initialized the device */ - unsigned int on_mainboard : 1; + unsigned int enabled : 1; /* set if we should enable the device */ + unsigned int initialized : 1; /* set if we have initialized the device */ + unsigned int on_mainboard : 1; struct pci_irq_info pci_irq_info[4]; u8 command;
@@ -190,7 +190,7 @@ void show_devs_subtree(struct device *root, int debug_level, const char *msg); void show_all_devs(int debug_level, const char *msg); void show_all_devs_tree(int debug_level, const char *msg); void show_one_resource(int debug_level, struct device *dev, - struct resource *resource, const char *comment); + struct resource *resource, const char *comment); void show_all_devs_resources(int debug_level, const char* msg);
/* Rounding for boundaries. diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 53a42ee..c14d5a4 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -36,14 +36,14 @@ * These values are in 1/256 ns units. * @{ */ -#define TCK_1066MHZ 240 -#define TCK_800MHZ 320 -#define TCK_666MHZ 384 -#define TCK_533MHZ 480 -#define TCK_400MHZ 640 -#define TCK_333MHZ 768 -#define TCK_266MHZ 960 -#define TCK_200MHZ 1280 +#define TCK_1066MHZ 240 +#define TCK_800MHZ 320 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 /** @} */
/** @@ -235,12 +235,12 @@ enum ddr3_mr0_burst_length { DDR3_MR0_BURST_LENGTH_4 = 2, }; mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, - u8 write_recovery, - enum ddr3_mr0_dll_reset dll_reset, - enum ddr3_mr0_mode mode, - u8 cas, - enum ddr3_mr0_burst_type interleaved_burst, - enum ddr3_mr0_burst_length burst_length); + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type interleaved_burst, + enum ddr3_mr0_burst_length burst_length);
enum ddr3_mr1_qoff { DDR3_MR1_QOFF_ENABLE = 0, @@ -277,12 +277,12 @@ enum ddr3_mr1_dll { };
mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, - enum ddr3_mr1_tqds tqds, - enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_write_leveling write_leveling, - enum ddr3_mr1_ods output_drive_strenght, - enum ddr3_mr1_additive_latency additive_latency, - enum ddr3_mr1_dll dll_disable); + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods output_drive_strenght, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable);
enum ddr3_mr2_rttwr { DDR3_MR2_RTTWR_OFF = 0, @@ -299,8 +299,8 @@ enum ddr3_mr2_asr { };
mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range extended_temp, - enum ddr3_mr2_asr self_refresh, u8 cas_cwl); + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, u8 cas_cwl);
mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); diff --git a/src/include/device/drm_dp_helper.h b/src/include/device/drm_dp_helper.h index f2e06c3..fa9e6fc 100644 --- a/src/include/device/drm_dp_helper.h +++ b/src/include/device/drm_dp_helper.h @@ -45,120 +45,120 @@
/* AUX CH addresses */ /* DPCD */ -#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV 0x000
-#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LINK_RATE 0x001
-#define DP_MAX_LANE_COUNT 0x002 +#define DP_MAX_LANE_COUNT 0x002 # define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) +# define DP_TPS3_SUPPORTED (1 << 6) # define DP_ENHANCED_FRAME_CAP (1 << 7)
-#define DP_MAX_DOWNSPREAD 0x003 +#define DP_MAX_DOWNSPREAD 0x003 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
-#define DP_NORP 0x004 +#define DP_NORP 0x004
-#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 /* 00b = DisplayPort */ /* 01b = Analog */ /* 10b = TMDS or HDMI */ /* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 +# define DP_FORMAT_CONVERSION (1 << 3) + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_EDP_CONFIGURATION_CAP 0x00d +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e + +#define DP_PSR_SUPPORT 0x070 +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1
/* link configuration */ -#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14
-#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
-#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_2 2 # define DP_TRAINING_PATTERN_3 3 # define DP_TRAINING_PATTERN_MASK 0x3
-# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
-# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
-#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4)
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) +# define DP_SET_ANSI_8B10B (1 << 0)
#define DP_PSR_EN_CFG 0x170 # define DP_PSR_ENABLE (1 << 0) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) # define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) +# define DP_PSR_FRAME_CAPTURE (1 << 3)
-#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) # define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) +# define DP_CP_IRQ (1 << 2) +# define DP_SINK_SPECIFIC_IRQ (1 << 6)
-#define DP_EDP_CONFIGURATION_SET 0x10a +#define DP_EDP_CONFIGURATION_SET 0x10a
#define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 @@ -170,7 +170,7 @@ DP_LANE_CHANNEL_EQ_DONE | \ DP_LANE_SYMBOL_LOCKED)
-#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0) #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) @@ -194,42 +194,42 @@
#define DP_TEST_REQUEST 0x218 # define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) +# define DP_TEST_LINK_PATTERN (1 << 1) # define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
#define DP_TEST_LINK_RATE 0x219 # define DP_LINK_RATE_162 (0x6) # define DP_LINK_RATE_27 (0xa)
-#define DP_TEST_LANE_COUNT 0x220 +#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 + +#define DP_PSR_ERROR_STATUS 0x2006 +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07
#define MODE_I2C_START 1 #define MODE_I2C_WRITE 2 diff --git a/src/include/device/hypertransport_def.h b/src/include/device/hypertransport_def.h index d6276ba..4e837e5 100644 --- a/src/include/device/hypertransport_def.h +++ b/src/include/device/hypertransport_def.h @@ -1,12 +1,12 @@ #ifndef DEVICE_HYPERTRANSPORT_DEF_H #define DEVICE_HYPERTRANSPORT_DEF_H
-#define HT_FREQ_200Mhz 0 -#define HT_FREQ_300Mhz 1 -#define HT_FREQ_400Mhz 2 -#define HT_FREQ_500Mhz 3 -#define HT_FREQ_600Mhz 4 -#define HT_FREQ_800Mhz 5 +#define HT_FREQ_200Mhz 0 +#define HT_FREQ_300Mhz 1 +#define HT_FREQ_400Mhz 2 +#define HT_FREQ_500Mhz 3 +#define HT_FREQ_600Mhz 4 +#define HT_FREQ_800Mhz 5 #define HT_FREQ_1000Mhz 6 #define HT_FREQ_1200Mhz 7 #define HT_FREQ_1400Mhz 8 diff --git a/src/include/device/i915_reg.h b/src/include/device/i915_reg.h index 8bdf2cb..212820d 100644 --- a/src/include/device/i915_reg.h +++ b/src/include/device/i915_reg.h @@ -39,36 +39,36 @@ /* PCI config space */
#define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (0xf << 0) -#define GC_CLOCK_133_200 (0 << 0) -#define GC_CLOCK_100_200 (1 << 0) -#define GC_CLOCK_100_133 (2 << 0) -#define GC_CLOCK_166_250 (3 << 0) +#define GC_CLOCK_CONTROL_MASK (0xf << 0) +#define GC_CLOCK_133_200 (0 << 0) +#define GC_CLOCK_100_200 (1 << 0) +#define GC_CLOCK_100_133 (2 << 0) +#define GC_CLOCK_166_250 (3 << 0) #define GCFGC2 0xda #define GCFGC 0xf0 /* 915+ only */ -#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -#define GC_DISPLAY_CLOCK_MASK (7 << 4) -#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) -#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) -#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) -#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) -#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) -#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) -#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) -#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) -#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) -#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) -#define I945_GC_RENDER_CLOCK_MASK (7 << 0) -#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) -#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) -#define I915_GC_RENDER_CLOCK_MASK (7 << 0) -#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) +#define GC_LOW_FREQUENCY_ENABLE (1 << 7) +#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_MASK (7 << 4) +#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) +#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) +#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) +#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) +#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) +#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) +#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) +#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) +#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) +#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) +#define I945_GC_RENDER_CLOCK_MASK (7 << 0) +#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) +#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) +#define I915_GC_RENDER_CLOCK_MASK (7 << 0) +#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define LBB 0xf4
/* Graphics reset regs */ @@ -79,19 +79,19 @@ #define GRDOM_MEDIA (3<<2)
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ -#define GEN6_MBC_SNPCR_SHIFT 21 -#define GEN6_MBC_SNPCR_MASK (3<<21) -#define GEN6_MBC_SNPCR_MAX (0<<21) -#define GEN6_MBC_SNPCR_MED (1<<21) -#define GEN6_MBC_SNPCR_LOW (2<<21) -#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ +#define GEN6_MBC_SNPCR_SHIFT 21 +#define GEN6_MBC_SNPCR_MASK (3<<21) +#define GEN6_MBC_SNPCR_MAX (0<<21) +#define GEN6_MBC_SNPCR_MED (1<<21) +#define GEN6_MBC_SNPCR_LOW (2<<21) +#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
#define GEN6_MBCTL 0x0907c -#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) -#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) -#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) -#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) -#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) +#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) +#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) +#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) +#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) +#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
#define GEN6_GDRST 0x941c #define GEN6_GRDOM_FULL (1 << 0) @@ -118,12 +118,12 @@ #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) -#define PP_DIR_DCLV_2G 0xffffffff +#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090 -#define ECOCHK_SNB_BIT (1<<10) -#define ECOCHK_PPGTT_CACHE64B (0x3<<3) -#define ECOCHK_PPGTT_CACHE4B (0x0<<3) +#define ECOCHK_SNB_BIT (1<<10) +#define ECOCHK_PPGTT_CACHE64B (0x3<<3) +#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
/* VGA stuff */
@@ -132,29 +132,29 @@
#define VGA_MSR_WRITE 0x3c2 #define VGA_MSR_READ 0x3cc -#define VGA_MSR_MEM_EN (1<<1) -#define VGA_MSR_CGA_MODE (1<<0) +#define VGA_MSR_MEM_EN (1<<1) +#define VGA_MSR_CGA_MODE (1<<0)
#define VGA_SR_INDEX 0x3c4 #define VGA_SR_DATA 0x3c5
#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) +#define VGA_AR_VID_EN (1<<5) #define VGA_AR_DATA_WRITE 0x3c0 #define VGA_AR_DATA_READ 0x3c1
#define VGA_GR_INDEX 0x3ce #define VGA_GR_DATA 0x3cf /* GR05 */ -#define VGA_GR_MEM_READ_MODE_SHIFT 3 -#define VGA_GR_MEM_READ_MODE_PLANE 1 +#define VGA_GR_MEM_READ_MODE_SHIFT 3 +#define VGA_GR_MEM_READ_MODE_PLANE 1 /* GR06 */ -#define VGA_GR_MEM_MODE_MASK 0xc -#define VGA_GR_MEM_MODE_SHIFT 2 -#define VGA_GR_MEM_A0000_AFFFF 0 -#define VGA_GR_MEM_A0000_BFFFF 1 -#define VGA_GR_MEM_B0000_B7FFF 2 -#define VGA_GR_MEM_B0000_BFFFF 3 +#define VGA_GR_MEM_MODE_MASK 0xc +#define VGA_GR_MEM_MODE_SHIFT 2 +#define VGA_GR_MEM_A0000_AFFFF 0 +#define VGA_GR_MEM_A0000_BFFFF 1 +#define VGA_GR_MEM_B0000_B7FFF 2 +#define VGA_GR_MEM_B0000_BFFFF 3
#define VGA_DACMASK 0x3c6 #define VGA_DACRX 0x3c7 @@ -173,41 +173,41 @@
#define MI_NOOP MI_INSTR(0, 0) #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ +#define MI_READ_FLUSH (1 << 0) +#define MI_EXE_FLUSH (1 << 1) +#define MI_NO_WRITE_FLUSH (1 << 2) +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ +#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) +#define MI_SUSPEND_FLUSH_EN (1<<0) #define MI_REPORT_HEAD MI_INSTR(0x07, 0) #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON (0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) +#define MI_OVERLAY_CONTINUE (0x0<<21) +#define MI_OVERLAY_ON (0x1<<21) +#define MI_OVERLAY_OFF (0x2<<21) #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) +#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) #define MI_SET_CONTEXT MI_INSTR(0x18, 0) -#define MI_MM_SPACE_GTT (1<<8) -#define MI_MM_SPACE_PHYSICAL (0<<8) -#define MI_SAVE_EXT_STATE_EN (1<<3) -#define MI_RESTORE_EXT_STATE_EN (1<<2) -#define MI_FORCE_RESTORE (1<<1) -#define MI_RESTORE_INHIBIT (1<<0) +#define MI_MM_SPACE_GTT (1<<8) +#define MI_MM_SPACE_PHYSICAL (0<<8) +#define MI_SAVE_EXT_STATE_EN (1<<3) +#define MI_RESTORE_EXT_STATE_EN (1<<2) +#define MI_FORCE_RESTORE (1<<1) +#define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 +#define MI_STORE_DWORD_INDEX_SHIFT 2 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. @@ -216,23 +216,23 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) +#define MI_INVALIDATE_TLB (1<<18) +#define MI_INVALIDATE_BSD (1<<7) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER (1<<18) -#define MI_SEMAPHORE_SYNC_RV (2<<16) -#define MI_SEMAPHORE_SYNC_RB (0<<16) -#define MI_SEMAPHORE_SYNC_VR (0<<16) -#define MI_SEMAPHORE_SYNC_VB (2<<16) -#define MI_SEMAPHORE_SYNC_BR (2<<16) -#define MI_SEMAPHORE_SYNC_BV (0<<16) +#define MI_SEMAPHORE_UPDATE (1<<21) +#define MI_SEMAPHORE_COMPARE (1<<20) +#define MI_SEMAPHORE_REGISTER (1<<18) +#define MI_SEMAPHORE_SYNC_RV (2<<16) +#define MI_SEMAPHORE_SYNC_RB (0<<16) +#define MI_SEMAPHORE_SYNC_VR (0<<16) +#define MI_SEMAPHORE_SYNC_VB (2<<16) +#define MI_SEMAPHORE_SYNC_BR (2<<16) +#define MI_SEMAPHORE_SYNC_BV (0<<16) #define MI_SEMAPHORE_SYNC_INVALID (1<<0) /* * 3D instructions used by the kernel @@ -240,57 +240,57 @@ #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) +#define BLT_DEPTH_8 (0<<24) +#define BLT_DEPTH_16_565 (1<<24) +#define BLT_DEPTH_16_1555 (2<<24) +#define BLT_DEPTH_32 (3<<24) +#define BLT_ROP_GXCOPY (0xcc<<16) #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) +#define ASYNC_FLIP (1<<22) +#define DISPLAY_PLANE_A (0<<20) +#define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) -#define PIPE_CONTROL_CS_STALL (1<<20) -#define PIPE_CONTROL_QW_WRITE (1<<14) -#define PIPE_CONTROL_DEPTH_STALL (1<<13) -#define PIPE_CONTROL_WRITE_FLUSH (1<<12) -#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ -#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ -#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ -#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_NOTIFY (1<<8) -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_CS_STALL (1<<20) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WRITE_FLUSH (1<<12) +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ +#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) +#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) +#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
/* @@ -307,32 +307,32 @@ */ #define FENCE_REG_830_0 0x2000 #define FENCE_REG_945_8 0x3000 -#define I830_FENCE_START_MASK 0x07f80000 -#define I830_FENCE_TILING_Y_SHIFT 12 -#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) -#define I830_FENCE_PITCH_SHIFT 4 -#define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 4 -#define I830_FENCE_MAX_PITCH_VAL 6 -#define I830_FENCE_MAX_SIZE_VAL (1<<8) - -#define I915_FENCE_START_MASK 0x0ff00000 -#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) +#define I915_FENCE_MAX_PITCH_VAL 4 +#define I830_FENCE_MAX_PITCH_VAL 6 +#define I830_FENCE_MAX_SIZE_VAL (1<<8) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
#define FENCE_REG_965_0 0x03000 -#define I965_FENCE_PITCH_SHIFT 2 -#define I965_FENCE_TILING_Y_SHIFT 1 -#define I965_FENCE_REG_VALID (1<<0) -#define I965_FENCE_MAX_PITCH_VAL 0x0400 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) +#define I965_FENCE_MAX_PITCH_VAL 0x0400
#define FENCE_REG_SANDYBRIDGE_0 0x100000 -#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
/* control register for cpu gtt access */ #define TILECTL 0x101000 -#define TILECTL_SWZCTL (1 << 0) -#define TILECTL_TLB_PREFETCH_DIS (1 << 2) -#define TILECTL_BACKSNOOP_DIS (1 << 3) +#define TILECTL_SWZCTL (1 << 0) +#define TILECTL_TLB_PREFETCH_DIS (1 << 2) +#define TILECTL_BACKSNOOP_DIS (1 << 3)
/* * Instruction and interrupt control regs @@ -358,10 +358,10 @@ #define RING_HWS_PGA(base) ((base)+0x80) #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) #define ARB_MODE 0x04030 -#define ARB_MODE_SWIZZLE_SNB (1<<4) -#define ARB_MODE_SWIZZLE_IVB (1<<5) -#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) -#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) +#define ARB_MODE_SWIZZLE_SNB (1<<4) +#define ARB_MODE_SWIZZLE_IVB (1<<5) +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) #define RENDER_HWS_PGA_GEN7 (0x04080) #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) #define DONE_REG 0x40b0 @@ -370,21 +370,21 @@ #define RING_ACTHD(base) ((base)+0x74) #define RING_NOPID(base) ((base)+0x94) #define RING_IMR(base) ((base)+0xa8) -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ -#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ -#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ +#define TAIL_ADDR 0x001FFFF8 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ +#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ #if 0 #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 @@ -411,7 +411,7 @@ #define HWS_ADDRESS_MASK 0xfffff000 #define HWS_START_ADDRESS_SHIFT 4 #define PWRCTXA 0x2088 /* 965GM+ only */ -#define PWRCTX_EN (1<<0) +#define PWRCTX_EN (1<<0) #define IPEIR 0x02088 #define IPEHR 0x0208c #define INSTDONE 0x02090 @@ -440,12 +440,12 @@ #define GFX_MODE 0x02520 #define GFX_MODE_GEN7 0x0229c #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) -#define GFX_RUN_LIST_ENABLE (1<<15) -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) -#define GFX_SURFACE_FAULT_ENABLE (1<<12) -#define GFX_REPLAY_MODE (1<<11) -#define GFX_PSMI_GRANULARITY (1<<10) -#define GFX_PPGTT_ENABLE (1<<9) +#define GFX_RUN_LIST_ENABLE (1<<15) +#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) +#define GFX_SURFACE_FAULT_ENABLE (1<<12) +#define GFX_REPLAY_MODE (1<<11) +#define GFX_PSMI_GRANULARITY (1<<10) +#define GFX_PPGTT_ENABLE (1<<9)
#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) @@ -455,163 +455,163 @@ #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) +#define I915_DISPLAY_PORT_INTERRUPT (1<<17) +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ +#define I915_HWB_OOM_INTERRUPT (1<<13) +#define I915_SYNC_STATUS_INTERRUPT (1<<12) +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) +#define I915_DEBUG_INTERRUPT (1<<2) +#define I915_USER_INTERRUPT (1<<1) +#define I915_ASLE_INTERRUPT (1<<0) +#define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 #define ESR 0x020b8 -#define GM45_ERROR_PAGE_TABLE (1<<5) -#define GM45_ERROR_MEM_PRIV (1<<4) -#define I915_ERROR_PAGE_TABLE (1<<4) -#define GM45_ERROR_CP_PRIV (1<<3) -#define I915_ERROR_MEMORY_REFRESH (1<<1) -#define I915_ERROR_INSTRUCTION (1<<0) -#define INSTPM 0x020c0 -#define INSTPM_SELF_EN (1<<12) /* 915GM only */ -#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts +#define GM45_ERROR_PAGE_TABLE (1<<5) +#define GM45_ERROR_MEM_PRIV (1<<4) +#define I915_ERROR_PAGE_TABLE (1<<4) +#define GM45_ERROR_CP_PRIV (1<<3) +#define I915_ERROR_MEMORY_REFRESH (1<<1) +#define I915_ERROR_INSTRUCTION (1<<0) +#define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ +#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts will not assert AGPBUSY# and will only be delivered when out of C3. */ -#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ -#define ACTHD 0x020c8 +#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ +#define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1<<31) -#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ -#define MM_BURST_LENGTH 0x00700000 +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ +#define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 -#define LM_BURST_LENGTH 0x00000700 +#define LM_BURST_LENGTH 0x00000700 #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ +#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) +#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
/* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) */ -#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) +#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
/* Block grant count for isoch requests when block count is * set to a finite value. */ -#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) -#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ -#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ -#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ -#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ +#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) +#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ +#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ +#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ +#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
/* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. */ -#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) +#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
/* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. */ -#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) +#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
/* Enables non-sequential data reads through arbiter */ -#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) +#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
/* Disable FSB snooping of cacheable write cycles from binner/render * command stream */ -#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) +#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
/* Arbiter time slice for non-isoch streams */ -#define MI_ARB_TIME_SLICE_MASK (7 << 5) -#define MI_ARB_TIME_SLICE_1 (0 << 5) -#define MI_ARB_TIME_SLICE_2 (1 << 5) -#define MI_ARB_TIME_SLICE_4 (2 << 5) -#define MI_ARB_TIME_SLICE_6 (3 << 5) -#define MI_ARB_TIME_SLICE_8 (4 << 5) -#define MI_ARB_TIME_SLICE_10 (5 << 5) -#define MI_ARB_TIME_SLICE_14 (6 << 5) -#define MI_ARB_TIME_SLICE_16 (7 << 5) +#define MI_ARB_TIME_SLICE_MASK (7 << 5) +#define MI_ARB_TIME_SLICE_1 (0 << 5) +#define MI_ARB_TIME_SLICE_2 (1 << 5) +#define MI_ARB_TIME_SLICE_4 (2 << 5) +#define MI_ARB_TIME_SLICE_6 (3 << 5) +#define MI_ARB_TIME_SLICE_8 (4 << 5) +#define MI_ARB_TIME_SLICE_10 (5 << 5) +#define MI_ARB_TIME_SLICE_14 (6 << 5) +#define MI_ARB_TIME_SLICE_16 (7 << 5)
/* Low priority grace period page size */ -#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ -#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) +#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ +#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
/* Disable display A/B trickle feed */ -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
/* Set display plane priority */ -#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ -#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ +#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ +#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_MASK_SHIFT 16 +#define CM0_IZ_OPT_DISABLE (1<<6) +#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) +#define CM0_DEPTH_EVICT_DISABLE (1<<4) +#define CM0_COLOR_EVICT_DISABLE (1<<3) +#define CM0_DEPTH_WRITE_DISABLE (1<<1) +#define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ #define ECOSKPD 0x021d0 -#define ECO_GATING_CX_ONLY (1<<3) -#define ECO_FLIP_DONE (1<<0) +#define ECO_GATING_CX_ONLY (1<<3) +#define ECO_FLIP_DONE (1<<0)
/* GEN6 interrupt control */ #define GEN6_RENDER_HWSTAM 0x2098 #define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
#define GEN6_BLITTER_HWSTAM 0x22098 #define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
#define GEN6_BLITTER_ECOSKPD 0x221d0 -#define GEN6_BLITTER_LOCK_SHIFT 16 -#define GEN6_BLITTER_FBC_NOTIFY (1<<3) +#define GEN6_BLITTER_LOCK_SHIFT 16 +#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 +#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
#define GEN6_BSD_HWSTAM 0x12098 #define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) +#define GEN6_BSD_USER_INTERRUPT (1 << 12)
#define GEN6_BSD_RNCID 0x12198
@@ -622,29 +622,29 @@ #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ #define FBC_LL_BASE 0x03204 /* 4k page aligned */ #define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_C3_IDLE (1<<13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_C3_IDLE (1<<13) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) +#define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) #define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) #define FBC_FENCE_OFF 0x0321b #define FBC_TAG 0x03300
@@ -653,45 +653,45 @@ /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE 0x3200 #define DPFC_CONTROL 0x3208 -#define DPFC_CTL_EN (1<<31) -#define DPFC_CTL_PLANEA (0<<30) -#define DPFC_CTL_PLANEB (1<<30) -#define DPFC_CTL_FENCE_EN (1<<29) -#define DPFC_CTL_PERSISTENT_MODE (1<<25) -#define DPFC_SR_EN (1<<10) -#define DPFC_CTL_LIMIT_1X (0<<6) -#define DPFC_CTL_LIMIT_2X (1<<6) -#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_PERSISTENT_MODE (1<<25) +#define DPFC_SR_EN (1<<10) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) #define DPFC_RECOMP_CTL 0x320c -#define DPFC_RECOMP_STALL_EN (1<<27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) #define DPFC_STATUS 0x3210 -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) #define DPFC_STATUS2 0x3214 #define DPFC_FENCE_YOFF 0x3218 #define DPFC_CHICKEN 0x3224 -#define DPFC_HT_MODIFY (1<<31) +#define DPFC_HT_MODIFY (1<<31)
/* Framebuffer compression for Ironlake */ #define ILK_DPFC_CB_BASE 0x43200 #define ILK_DPFC_CONTROL 0x43208 /* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) +#define DPFC_RESERVED (0x1FFFFF00) #define ILK_DPFC_RECOMP_CTL 0x4320c #define ILK_DPFC_STATUS 0x43210 #define ILK_DPFC_FENCE_YOFF 0x43218 #define ILK_DPFC_CHICKEN 0x43224 #define ILK_FBC_RT_BASE 0x2128 -#define ILK_FBC_RT_VALID (1<<0) +#define ILK_FBC_RT_VALID (1<<0)
#define ILK_DISPLAY_CHICKEN1 0x42000 -#define ILK_FBCQ_DIS (1<<22) +#define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21)
@@ -701,7 +701,7 @@ * The following two registers are of type GTTMMADR */ #define SNB_DPFC_CTL_SA 0x100100 -#define SNB_CPU_FENCE_ENABLE (1<<29) +#define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104
@@ -732,52 +732,52 @@ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
#define GMBUS0 0x5100 /* clock/port select */ -#define GMBUS_RATE_100KHZ (0<<8) -#define GMBUS_RATE_50KHZ (1<<8) -#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ -#define GMBUS_RATE_MASK (3<<8) -#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) -#define GMBUS_PORT_MASK 7 +#define GMBUS_RATE_100KHZ (0<<8) +#define GMBUS_RATE_50KHZ (1<<8) +#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ +#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ +#define GMBUS_RATE_MASK (3<<8) +#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ +#define GMBUS_PORT_DISABLED 0 +#define GMBUS_PORT_SSC 1 +#define GMBUS_PORT_VGADDC 2 +#define GMBUS_PORT_PANEL 3 +#define GMBUS_PORT_DPC 4 /* HDMIC */ +#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PORT_DPD 6 /* HDMID */ +#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ +#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PORT_MASK 7 #define GMBUS1 0x5104 /* command/status */ -#define GMBUS_SW_CLR_INT (1<<31) -#define GMBUS_SW_RDY (1<<30) -#define GMBUS_ENT (1<<29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0<<25) -#define GMBUS_CYCLE_WAIT (1<<25) -#define GMBUS_CYCLE_INDEX (2<<25) -#define GMBUS_CYCLE_STOP (4<<25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1<<0) -#define GMBUS_SLAVE_WRITE (0<<0) +#define GMBUS_SW_CLR_INT (1<<31) +#define GMBUS_SW_RDY (1<<30) +#define GMBUS_ENT (1<<29) /* enable timeout */ +#define GMBUS_CYCLE_NONE (0<<25) +#define GMBUS_CYCLE_WAIT (1<<25) +#define GMBUS_CYCLE_INDEX (2<<25) +#define GMBUS_CYCLE_STOP (4<<25) +#define GMBUS_BYTE_COUNT_SHIFT 16 +#define GMBUS_SLAVE_INDEX_SHIFT 8 +#define GMBUS_SLAVE_ADDR_SHIFT 1 +#define GMBUS_SLAVE_READ (1<<0) +#define GMBUS_SLAVE_WRITE (0<<0) #define GMBUS2 0x5108 /* status */ -#define GMBUS_INUSE (1<<15) -#define GMBUS_HW_WAIT_PHASE (1<<14) -#define GMBUS_STALL_TIMEOUT (1<<13) -#define GMBUS_INT (1<<12) -#define GMBUS_HW_RDY (1<<11) -#define GMBUS_SATOER (1<<10) -#define GMBUS_ACTIVE (1<<9) +#define GMBUS_INUSE (1<<15) +#define GMBUS_HW_WAIT_PHASE (1<<14) +#define GMBUS_STALL_TIMEOUT (1<<13) +#define GMBUS_INT (1<<12) +#define GMBUS_HW_RDY (1<<11) +#define GMBUS_SATOER (1<<10) +#define GMBUS_ACTIVE (1<<9) #define GMBUS3 0x510c /* data buffer bytes 3-0 */ #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ -#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) -#define GMBUS_NAK_EN (1<<3) -#define GMBUS_IDLE_EN (1<<2) -#define GMBUS_HW_WAIT_EN (1<<1) -#define GMBUS_HW_RDY_EN (1<<0) +#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) +#define GMBUS_NAK_EN (1<<3) +#define GMBUS_IDLE_EN (1<<2) +#define GMBUS_HW_WAIT_EN (1<<1) +#define GMBUS_HW_RDY_EN (1<<0) #define GMBUS5 0x5120 /* byte index */ -#define GMBUS_2BYTE_INDEX_EN (1<<31) +#define GMBUS_2BYTE_INDEX_EN (1<<31)
/* * Clock control & power management @@ -786,31 +786,31 @@ #define VGA0 0x6000 #define VGA1 0x6004 #define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) +#define VGA0_PD_P2_DIV_4 (1 << 7) +#define VGA0_PD_P1_DIV_2 (1 << 5) +#define VGA0_PD_P1_SHIFT 0 +#define VGA0_PD_P1_MASK (0x1f << 0) +#define VGA1_PD_P2_DIV_4 (1 << 15) +#define VGA1_PD_P1_DIV_2 (1 << 13) +#define VGA1_PD_P1_SHIFT 8 +#define VGA1_PD_P1_MASK (0x1f << 8) #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_DVO_HIGH_SPEED (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
#define SRX_INDEX 0x3c4 #define SRX_DATA 0x3c5 @@ -829,29 +829,29 @@
/* Scratch pad debug 0 reg: */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 /* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 /* Ironlake */ -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
/* * Parallel to Serial Load Pulse phase selection. @@ -859,25 +859,25 @@ * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) /* * SDVO multiplier for 945G/GM. Not used on 965. */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 +#define SDVO_MULTIPLIER_MASK 0x000000ff +#define SDVO_MULTIPLIER_SHIFT_HIRES 4 +#define SDVO_MULTIPLIER_SHIFT_VGA 0 #define _DPLL_A_MD 0x0601c /* 965+ only */ /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 /* * SDVO/UDI pixel multiplier. * @@ -895,15 +895,15 @@ * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 #define _DPLL_B_MD 0x06020 /* 965+ only */ #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) #define _FPA0 0x06040 @@ -912,25 +912,25 @@ #define _FPB1 0x0604c #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 #define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +#define DPLLB_TEST_N_BYPASS (1 << 19) +#define DPLLB_TEST_M_BYPASS (1 << 18) +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +#define DPLLA_TEST_N_BYPASS (1 << 3) +#define DPLLA_TEST_M_BYPASS (1 << 2) +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 #define DSTATE_GFX_RESET_I830 (1<<6) #define DSTATE_PLL_D3_OFF (1<<3) @@ -1044,7 +1044,7 @@ #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) #define RAMCLK_GATE_D 0x6210 /* CRL only */ -#define DEUC 0x6214 /* CRL only */ +#define DEUC 0x6214 /* CRL only */
/* * Palette regs @@ -1078,7 +1078,7 @@ #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** Pineview MCH register contains DDR3 setting */ -#define CSHRDDR3CTL 0x101a8 +#define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL_DDR3 (1 << 2)
/** 965 MCH register controlling DRAM channel configuration */ @@ -1089,23 +1089,23 @@ #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) -#define MAD_DIMM_ECC_MASK (0x3 << 24) -#define MAD_DIMM_ECC_OFF (0x0 << 24) -#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) -#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) -#define MAD_DIMM_ECC_ON (0x3 << 24) -#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) -#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) -#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ -#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ -#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) -#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) -#define MAD_DIMM_A_SELECT (0x1 << 16) +#define MAD_DIMM_ECC_MASK (0x3 << 24) +#define MAD_DIMM_ECC_OFF (0x0 << 24) +#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) +#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) +#define MAD_DIMM_ECC_ON (0x3 << 24) +#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) +#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) +#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ +#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ +#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) +#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) +#define MAD_DIMM_A_SELECT (0x1 << 16) /* DIMM sizes are in multiples of 256mb. */ -#define MAD_DIMM_B_SIZE_SHIFT 8 -#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) -#define MAD_DIMM_A_SIZE_SHIFT 0 -#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) +#define MAD_DIMM_B_SIZE_SHIFT 8 +#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) +#define MAD_DIMM_A_SIZE_SHIFT 0 +#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
/* Clocking configuration register */ @@ -1126,194 +1126,194 @@ #define CLKCFG_MEM_MASK (7 << 4)
#define TSC1 0x11001 -#define TSE (1<<0) +#define TSE (1<<0) #define TR1 0x11006 #define TSFS 0x11020 -#define TSFS_SLOPE_MASK 0x0000ff00 -#define TSFS_SLOPE_SHIFT 8 -#define TSFS_INTR_MASK 0x000000ff +#define TSFS_SLOPE_MASK 0x0000ff00 +#define TSFS_SLOPE_SHIFT 8 +#define TSFS_INTR_MASK 0x000000ff
#define CRSTANDVID 0x11100 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ -#define PXVFREQ_PX_MASK 0x7f000000 -#define PXVFREQ_PX_SHIFT 24 +#define PXVFREQ_PX_MASK 0x7f000000 +#define PXVFREQ_PX_SHIFT 24 #define VIDFREQ_BASE 0x11110 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ #define VIDFREQ2 0x11114 #define VIDFREQ3 0x11118 #define VIDFREQ4 0x1111c -#define VIDFREQ_P0_MASK 0x1f000000 -#define VIDFREQ_P0_SHIFT 24 -#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 -#define VIDFREQ_P0_CSCLK_SHIFT 20 -#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 -#define VIDFREQ_P0_CRCLK_SHIFT 16 -#define VIDFREQ_P1_MASK 0x00001f00 -#define VIDFREQ_P1_SHIFT 8 -#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 -#define VIDFREQ_P1_CSCLK_SHIFT 4 -#define VIDFREQ_P1_CRCLK_MASK 0x0000000f +#define VIDFREQ_P0_MASK 0x1f000000 +#define VIDFREQ_P0_SHIFT 24 +#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 +#define VIDFREQ_P0_CSCLK_SHIFT 20 +#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 +#define VIDFREQ_P0_CRCLK_SHIFT 16 +#define VIDFREQ_P1_MASK 0x00001f00 +#define VIDFREQ_P1_SHIFT 8 +#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 +#define VIDFREQ_P1_CSCLK_SHIFT 4 +#define VIDFREQ_P1_CRCLK_MASK 0x0000000f #define INTTOEXT_BASE_ILK 0x11300 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ -#define INTTOEXT_MAP3_SHIFT 24 -#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) -#define INTTOEXT_MAP2_SHIFT 16 -#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) -#define INTTOEXT_MAP1_SHIFT 8 -#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) -#define INTTOEXT_MAP0_SHIFT 0 -#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) +#define INTTOEXT_MAP3_SHIFT 24 +#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) +#define INTTOEXT_MAP2_SHIFT 16 +#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) +#define INTTOEXT_MAP1_SHIFT 8 +#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) +#define INTTOEXT_MAP0_SHIFT 0 +#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) #define MEMSWCTL 0x11170 /* Ironlake only */ -#define MEMCTL_CMD_MASK 0xe000 -#define MEMCTL_CMD_SHIFT 13 -#define MEMCTL_CMD_RCLK_OFF 0 -#define MEMCTL_CMD_RCLK_ON 1 -#define MEMCTL_CMD_CHFREQ 2 -#define MEMCTL_CMD_CHVID 3 -#define MEMCTL_CMD_VMMOFF 4 -#define MEMCTL_CMD_VMMON 5 -#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears - when command complete */ -#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ -#define MEMCTL_FREQ_SHIFT 8 -#define MEMCTL_SFCAVM (1<<7) -#define MEMCTL_TGT_VID_MASK 0x007f +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears + when command complete */ +#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ +#define MEMCTL_FREQ_SHIFT 8 +#define MEMCTL_SFCAVM (1<<7) +#define MEMCTL_TGT_VID_MASK 0x007f #define MEMIHYST 0x1117c #define MEMINTREN 0x11180 /* 16 bits */ -#define MEMINT_RSEXIT_EN (1<<8) -#define MEMINT_CX_SUPR_EN (1<<7) -#define MEMINT_CONT_BUSY_EN (1<<6) -#define MEMINT_AVG_BUSY_EN (1<<5) -#define MEMINT_EVAL_CHG_EN (1<<4) -#define MEMINT_MON_IDLE_EN (1<<3) -#define MEMINT_UP_EVAL_EN (1<<2) -#define MEMINT_DOWN_EVAL_EN (1<<1) -#define MEMINT_SW_CMD_EN (1<<0) +#define MEMINT_RSEXIT_EN (1<<8) +#define MEMINT_CX_SUPR_EN (1<<7) +#define MEMINT_CONT_BUSY_EN (1<<6) +#define MEMINT_AVG_BUSY_EN (1<<5) +#define MEMINT_EVAL_CHG_EN (1<<4) +#define MEMINT_MON_IDLE_EN (1<<3) +#define MEMINT_UP_EVAL_EN (1<<2) +#define MEMINT_DOWN_EVAL_EN (1<<1) +#define MEMINT_SW_CMD_EN (1<<0) #define MEMINTRSTR 0x11182 /* 16 bits */ -#define MEM_RSEXIT_MASK 0xc000 -#define MEM_RSEXIT_SHIFT 14 -#define MEM_CONT_BUSY_MASK 0x3000 -#define MEM_CONT_BUSY_SHIFT 12 -#define MEM_AVG_BUSY_MASK 0x0c00 -#define MEM_AVG_BUSY_SHIFT 10 -#define MEM_EVAL_CHG_MASK 0x0300 -#define MEM_EVAL_BUSY_SHIFT 8 -#define MEM_MON_IDLE_MASK 0x00c0 -#define MEM_MON_IDLE_SHIFT 6 -#define MEM_UP_EVAL_MASK 0x0030 -#define MEM_UP_EVAL_SHIFT 4 -#define MEM_DOWN_EVAL_MASK 0x000c -#define MEM_DOWN_EVAL_SHIFT 2 -#define MEM_SW_CMD_MASK 0x0003 -#define MEM_INT_STEER_GFX 0 -#define MEM_INT_STEER_CMR 1 -#define MEM_INT_STEER_SMI 2 -#define MEM_INT_STEER_SCI 3 +#define MEM_RSEXIT_MASK 0xc000 +#define MEM_RSEXIT_SHIFT 14 +#define MEM_CONT_BUSY_MASK 0x3000 +#define MEM_CONT_BUSY_SHIFT 12 +#define MEM_AVG_BUSY_MASK 0x0c00 +#define MEM_AVG_BUSY_SHIFT 10 +#define MEM_EVAL_CHG_MASK 0x0300 +#define MEM_EVAL_BUSY_SHIFT 8 +#define MEM_MON_IDLE_MASK 0x00c0 +#define MEM_MON_IDLE_SHIFT 6 +#define MEM_UP_EVAL_MASK 0x0030 +#define MEM_UP_EVAL_SHIFT 4 +#define MEM_DOWN_EVAL_MASK 0x000c +#define MEM_DOWN_EVAL_SHIFT 2 +#define MEM_SW_CMD_MASK 0x0003 +#define MEM_INT_STEER_GFX 0 +#define MEM_INT_STEER_CMR 1 +#define MEM_INT_STEER_SMI 2 +#define MEM_INT_STEER_SCI 3 #define MEMINTRSTS 0x11184 -#define MEMINT_RSEXIT (1<<7) -#define MEMINT_CONT_BUSY (1<<6) -#define MEMINT_AVG_BUSY (1<<5) -#define MEMINT_EVAL_CHG (1<<4) -#define MEMINT_MON_IDLE (1<<3) -#define MEMINT_UP_EVAL (1<<2) -#define MEMINT_DOWN_EVAL (1<<1) -#define MEMINT_SW_CMD (1<<0) +#define MEMINT_RSEXIT (1<<7) +#define MEMINT_CONT_BUSY (1<<6) +#define MEMINT_AVG_BUSY (1<<5) +#define MEMINT_EVAL_CHG (1<<4) +#define MEMINT_MON_IDLE (1<<3) +#define MEMINT_UP_EVAL (1<<2) +#define MEMINT_DOWN_EVAL (1<<1) +#define MEMINT_SW_CMD (1<<0) #define MEMMODECTL 0x11190 -#define MEMMODE_BOOST_EN (1<<31) -#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ -#define MEMMODE_BOOST_FREQ_SHIFT 24 -#define MEMMODE_IDLE_MODE_MASK 0x00030000 -#define MEMMODE_IDLE_MODE_SHIFT 16 -#define MEMMODE_IDLE_MODE_EVAL 0 -#define MEMMODE_IDLE_MODE_CONT 1 -#define MEMMODE_HWIDLE_EN (1<<15) -#define MEMMODE_SWMODE_EN (1<<14) -#define MEMMODE_RCLK_GATE (1<<13) -#define MEMMODE_HW_UPDATE (1<<12) -#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ -#define MEMMODE_FSTART_SHIFT 8 -#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ -#define MEMMODE_FMAX_SHIFT 4 -#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ +#define MEMMODE_BOOST_EN (1<<31) +#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ +#define MEMMODE_BOOST_FREQ_SHIFT 24 +#define MEMMODE_IDLE_MODE_MASK 0x00030000 +#define MEMMODE_IDLE_MODE_SHIFT 16 +#define MEMMODE_IDLE_MODE_EVAL 0 +#define MEMMODE_IDLE_MODE_CONT 1 +#define MEMMODE_HWIDLE_EN (1<<15) +#define MEMMODE_SWMODE_EN (1<<14) +#define MEMMODE_RCLK_GATE (1<<13) +#define MEMMODE_HW_UPDATE (1<<12) +#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ +#define MEMMODE_FSTART_SHIFT 8 +#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ +#define MEMMODE_FMAX_SHIFT 4 +#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ #define RCBMAXAVG 0x1119c #define MEMSWCTL2 0x1119e /* Cantiga only */ -#define SWMEMCMD_RENDER_OFF (0 << 13) -#define SWMEMCMD_RENDER_ON (1 << 13) -#define SWMEMCMD_SWFREQ (2 << 13) -#define SWMEMCMD_TARVID (3 << 13) -#define SWMEMCMD_VRM_OFF (4 << 13) -#define SWMEMCMD_VRM_ON (5 << 13) -#define CMDSTS (1<<12) -#define SFCAVM (1<<11) -#define SWFREQ_MASK 0x0380 /* P0-7 */ -#define SWFREQ_SHIFT 7 -#define TARVID_MASK 0x001f +#define SWMEMCMD_RENDER_OFF (0 << 13) +#define SWMEMCMD_RENDER_ON (1 << 13) +#define SWMEMCMD_SWFREQ (2 << 13) +#define SWMEMCMD_TARVID (3 << 13) +#define SWMEMCMD_VRM_OFF (4 << 13) +#define SWMEMCMD_VRM_ON (5 << 13) +#define CMDSTS (1<<12) +#define SFCAVM (1<<11) +#define SWFREQ_MASK 0x0380 /* P0-7 */ +#define SWFREQ_SHIFT 7 +#define TARVID_MASK 0x001f #define MEMSTAT_CTG 0x111a0 #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 #define RSTDBYCTL 0x111b8 -#define RS1EN (1<<31) -#define RS2EN (1<<30) -#define RS3EN (1<<29) -#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ -#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ -#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ -#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ -#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ -#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ -#define RSX_STATUS_MASK (7<<20) -#define RSX_STATUS_ON (0<<20) -#define RSX_STATUS_RC1 (1<<20) -#define RSX_STATUS_RC1E (2<<20) -#define RSX_STATUS_RS1 (3<<20) -#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ -#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ -#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ -#define RSX_STATUS_RSVD2 (7<<20) -#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ -#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ -#define JRSC (1<<17) /* rsx coupled to cpu c-state */ -#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ -#define RS1CONTSAV_MASK (3<<14) -#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ -#define RS1CONTSAV_RSVD (1<<14) -#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ -#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ -#define NORMSLEXLAT_MASK (3<<12) -#define SLOW_RS123 (0<<12) -#define SLOW_RS23 (1<<12) -#define SLOW_RS3 (2<<12) -#define NORMAL_RS123 (3<<12) -#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ -#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ -#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ -#define RS_CSTATE_MASK (3<<4) -#define RS_CSTATE_C367_RS1 (0<<4) -#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) -#define RS_CSTATE_RSVD (2<<4) -#define RS_CSTATE_C367_RS2 (3<<4) -#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ -#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ +#define RS1EN (1<<31) +#define RS2EN (1<<30) +#define RS3EN (1<<29) +#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ +#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ +#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ +#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ +#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ +#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ +#define RSX_STATUS_MASK (7<<20) +#define RSX_STATUS_ON (0<<20) +#define RSX_STATUS_RC1 (1<<20) +#define RSX_STATUS_RC1E (2<<20) +#define RSX_STATUS_RS1 (3<<20) +#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ +#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ +#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ +#define RSX_STATUS_RSVD2 (7<<20) +#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ +#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ +#define JRSC (1<<17) /* rsx coupled to cpu c-state */ +#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ +#define RS1CONTSAV_MASK (3<<14) +#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ +#define RS1CONTSAV_RSVD (1<<14) +#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ +#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ +#define NORMSLEXLAT_MASK (3<<12) +#define SLOW_RS123 (0<<12) +#define SLOW_RS23 (1<<12) +#define SLOW_RS3 (2<<12) +#define NORMAL_RS123 (3<<12) +#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ +#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ +#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ +#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ +#define RS_CSTATE_MASK (3<<4) +#define RS_CSTATE_C367_RS1 (0<<4) +#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) +#define RS_CSTATE_RSVD (2<<4) +#define RS_CSTATE_C367_RS2 (3<<4) +#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ +#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ #define VIDCTL 0x111c0 #define VIDSTS 0x111c8 #define VIDSTART 0x111cc /* 8 bits */ #define MEMSTAT_ILK 0x111f8 -#define MEMSTAT_VID_MASK 0x7f00 -#define MEMSTAT_VID_SHIFT 8 -#define MEMSTAT_PSTATE_MASK 0x00f8 -#define MEMSTAT_PSTATE_SHIFT 3 -#define MEMSTAT_MON_ACTV (1<<2) -#define MEMSTAT_SRC_CTL_MASK 0x0003 -#define MEMSTAT_SRC_CTL_CORE 0 -#define MEMSTAT_SRC_CTL_TRB 1 -#define MEMSTAT_SRC_CTL_THM 2 -#define MEMSTAT_SRC_CTL_STDBY 3 +#define MEMSTAT_VID_MASK 0x7f00 +#define MEMSTAT_VID_SHIFT 8 +#define MEMSTAT_PSTATE_MASK 0x00f8 +#define MEMSTAT_PSTATE_SHIFT 3 +#define MEMSTAT_MON_ACTV (1<<2) +#define MEMSTAT_SRC_CTL_MASK 0x0003 +#define MEMSTAT_SRC_CTL_CORE 0 +#define MEMSTAT_SRC_CTL_TRB 1 +#define MEMSTAT_SRC_CTL_THM 2 +#define MEMSTAT_SRC_CTL_STDBY 3 #define RCPREVBSYTUPAVG 0x113b8 #define RCPREVBSYTDNAVG 0x113bc #define PMMISC 0x11214 -#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ +#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ #define SDEW 0x1124c #define CSIEW0 0x11250 #define CSIEW1 0x11254 @@ -1330,9 +1330,9 @@ #define RPPREVBSYTUPAVG 0x113b8 #define RPPREVBSYTDNAVG 0x113bc #define ECR 0x11600 -#define ECR_GPFE (1<<31) -#define ECR_IMONE (1<<30) -#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ +#define ECR_GPFE (1<<31) +#define ECR_IMONE (1<<30) +#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ #define OGW0 0x11608 #define OGW1 0x1160c #define EG0 0x11610 @@ -1346,7 +1346,7 @@ #define PXW 0x11664 #define PXWL 0x11680 #define LCFUSE02 0x116c0 -#define LCFUSE_HIV_MASK 0x000000ff +#define LCFUSE_HIV_MASK 0x000000ff #define CSIPLL0 0x12c10 #define DDRMPLL1 0X12c20 #define PEG_BAND_GAP_DATA 0x14d68 @@ -1362,7 +1362,7 @@ * Logical Context regs */ #define CCID 0x2180 -#define CCID_EN (1<<0) +#define CCID_EN (1<<0) /* * Overlay regs */ @@ -1415,42 +1415,42 @@
/* VGA port control */ #define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 +#define ADPA_DPMS_MASK (~(3<<10)) +#define ADPA_DPMS_ON (0<<10) +#define ADPA_DPMS_SUSPEND (1<<10) +#define ADPA_DPMS_STANDBY (2<<10) +#define ADPA_DPMS_OFF (3<<10)
/* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 -#define HDMIB_HOTPLUG_INT_EN (1 << 29) -#define DPB_HOTPLUG_INT_EN (1 << 29) -#define HDMIC_HOTPLUG_INT_EN (1 << 28) -#define DPC_HOTPLUG_INT_EN (1 << 28) -#define HDMID_HOTPLUG_INT_EN (1 << 27) -#define DPD_HOTPLUG_INT_EN (1 << 27) -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +#define HDMIB_HOTPLUG_INT_EN (1 << 29) +#define DPB_HOTPLUG_INT_EN (1 << 29) +#define HDMIC_HOTPLUG_INT_EN (1 << 28) +#define DPC_HOTPLUG_INT_EN (1 << 28) +#define HDMID_HOTPLUG_INT_EN (1 << 27) +#define DPD_HOTPLUG_INT_EN (1 << 27) +#define SDVOB_HOTPLUG_INT_EN (1 << 26) +#define SDVOC_HOTPLUG_INT_EN (1 << 25) +#define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_HOTPLUG_INT_EN (1 << 9) +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) /* must use period 64 on GM45 according to docs */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) @@ -1467,28 +1467,28 @@ #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
#define PORT_HOTPLUG_STAT 0x61114 -#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) -#define DPB_HOTPLUG_INT_STATUS (1 << 29) -#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) -#define DPC_HOTPLUG_INT_STATUS (1 << 28) -#define HDMID_HOTPLUG_INT_STATUS (1 << 27) -#define DPD_HOTPLUG_INT_STATUS (1 << 27) -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) +#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +#define DPB_HOTPLUG_INT_STATUS (1 << 29) +#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +#define DPC_HOTPLUG_INT_STATUS (1 << 28) +#define HDMID_HOTPLUG_INT_STATUS (1 << 27) +#define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_HOTPLUG_INT_STATUS (1 << 11) +#define TV_HOTPLUG_INT_STATUS (1 << 10) +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
/* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) /** * 915G/GM SDVO pixel multiplier. * @@ -1496,62 +1496,62 @@ * * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_ENCODING_SDVO (0x0 << 10) -#define SDVO_ENCODING_HDMI (0x2 << 10) +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) /** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) -#define SDVO_COLOR_RANGE_16_235 (1 << 8) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVO_AUDIO_ENABLE (1 << 6) +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) +#define SDVO_COLOR_RANGE_16_235 (1 << 8) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) /** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) /** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
/* DVO port control */ #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) +#define DVO_ENABLE (1 << 31) +#define DVO_PIPE_B_SELECT (1 << 30) +#define DVO_PIPE_STALL_UNUSED (0 << 28) +#define DVO_PIPE_STALL (1 << 28) +#define DVO_PIPE_STALL_TV (2 << 28) +#define DVO_PIPE_STALL_MASK (3 << 28) +#define DVO_USE_VGA_SYNC (1 << 15) +#define DVO_DATA_ORDER_I740 (0 << 14) +#define DVO_DATA_ORDER_FP (1 << 14) +#define DVO_VSYNC_DISABLE (1 << 11) +#define DVO_HSYNC_DISABLE (1 << 10) +#define DVO_VSYNC_TRISTATE (1 << 9) +#define DVO_HSYNC_TRISTATE (1 << 8) +#define DVO_BORDER_ENABLE (1 << 7) +#define DVO_DATA_ORDER_GBRG (1 << 6) +#define DVO_DATA_ORDER_RGGB (0 << 6) +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define DVO_BLANK_ACTIVE_HIGH (1 << 2) +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ +#define DVO_PRESERVE_MASK (0x7<<24) #define DVOA_SRCDIM 0x61124 #define DVOB_SRCDIM 0x61144 #define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */ #define LVDS 0x61180 @@ -1559,70 +1559,70 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1 << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -#define LVDS_PIPE_MASK (1 << 30) -#define LVDS_PIPE(pipe) ((pipe) << 30) +#define LVDS_PIPEB_SELECT (1 << 30) +#define LVDS_PIPE_MASK (1 << 30) +#define LVDS_PIPE(pipe) ((pipe) << 30) /* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) +#define LVDS_ENABLE_DITHER (1 << 25) /* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) +#define LVDS_VSYNC_POLARITY (1 << 21) +#define LVDS_HSYNC_POLARITY (1 << 20)
/* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_BORDER_ENABLE (1 << 15) /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) +#define LVDS_A3_POWER_MASK (3 << 6) +#define LVDS_A3_POWER_DOWN (0 << 6) +#define LVDS_A3_POWER_UP (3 << 6) /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) +#define LVDS_CLKB_POWER_MASK (3 << 4) +#define LVDS_CLKB_POWER_DOWN (0 << 4) +#define LVDS_CLKB_POWER_UP (3 << 4) /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) +#define LVDS_B0B3_POWER_MASK (3 << 2) +#define LVDS_B0B3_POWER_DOWN (0 << 2) +#define LVDS_B0B3_POWER_UP (3 << 2)
/* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT_B (1 << 29) -#define VIDEO_DIP_PORT_C (2 << 29) -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT_B (1 << 29) +#define VIDEO_DIP_PORT_C (2 << 29) +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
/* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1 << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1630,51 +1630,51 @@ * - pipe enabled * - LVDS/DVOB/DVOC on */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_POWER_UP (1 << 28) -#define PP_SEQUENCE_POWER_DOWN (2 << 28) -#define PP_SEQUENCE_MASK (3 << 28) -#define PP_SEQUENCE_SHIFT 28 -#define PP_CYCLE_DELAY_ACTIVE (1 << 27) -#define PP_SEQUENCE_STATE_MASK 0x0000000f -#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) -#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) -#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) -#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) -#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) -#define PP_SEQUENCE_STATE_RESET (0xf << 0) +#define PP_READY (1 << 30) +#define PP_SEQUENCE_NONE (0 << 28) +#define PP_SEQUENCE_POWER_UP (1 << 28) +#define PP_SEQUENCE_POWER_DOWN (2 << 28) +#define PP_SEQUENCE_MASK (3 << 28) +#define PP_SEQUENCE_SHIFT 28 +#define PP_CYCLE_DELAY_ACTIVE (1 << 27) +#define PP_SEQUENCE_STATE_MASK 0x0000000f +#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) +#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) +#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) +#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) +#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) +#define PP_SEQUENCE_STATE_RESET (0xf << 0) #define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) +#define POWER_TARGET_ON (1 << 0) #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210
/* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_FILTER_FUZZY (0 << 24) -#define PFIT_SCALING_AUTO (0 << 26) -#define PFIT_SCALING_PROGRAMMED (1 << 26) -#define PFIT_SCALING_PILLAR (2 << 26) -#define PFIT_SCALING_LETTER (3 << 26) +#define PFIT_ENABLE (1 << 31) +#define PFIT_PIPE_MASK (3 << 29) +#define PFIT_PIPE_SHIFT 29 +#define VERT_INTERP_DISABLE (0 << 10) +#define VERT_INTERP_BILINEAR (1 << 10) +#define VERT_INTERP_MASK (3 << 10) +#define VERT_AUTO_SCALE (1 << 9) +#define HORIZ_INTERP_DISABLE (0 << 6) +#define HORIZ_INTERP_BILINEAR (1 << 6) +#define HORIZ_INTERP_MASK (3 << 6) +#define HORIZ_AUTO_SCALE (1 << 5) +#define PANEL_8TO6_DITHER_ENABLE (1 << 3) +#define PFIT_FILTER_FUZZY (0 << 24) +#define PFIT_SCALING_AUTO (0 << 26) +#define PFIT_SCALING_PROGRAMMED (1 << 26) +#define PFIT_SCALING_PILLAR (2 << 26) +#define PFIT_SCALING_LETTER (3 << 26) #define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 +#define PFIT_VERT_SCALE_MASK 0xfff00000 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 /* Pre-965 */ #define PFIT_VERT_SCALE_SHIFT 20 #define PFIT_VERT_SCALE_MASK 0xfff00000 @@ -1690,17 +1690,17 @@
/* Backlight control */ #define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) +#define BLM_COMBINATION_MODE (1 << 30) /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. @@ -1708,8 +1708,8 @@ * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
#define BLC_HIST_CTL 0x61260
@@ -2199,82 +2199,82 @@ #define DP_C 0x64200 #define DP_D 0x64300
-#define DP_PORT_EN (1 << 31) -#define DP_PIPEB_SELECT (1 << 30) -#define DP_PIPE_MASK (1 << 30) +#define DP_PORT_EN (1 << 31) +#define DP_PIPEB_SELECT (1 << 30) +#define DP_PIPE_MASK (1 << 30)
/* Link training mode - select a suitable mode for each stage */ -#define DP_LINK_TRAIN_PAT_1 (0 << 28) -#define DP_LINK_TRAIN_PAT_2 (1 << 28) -#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) -#define DP_LINK_TRAIN_OFF (3 << 28) -#define DP_LINK_TRAIN_MASK (3 << 28) -#define DP_LINK_TRAIN_SHIFT 28 +#define DP_LINK_TRAIN_PAT_1 (0 << 28) +#define DP_LINK_TRAIN_PAT_2 (1 << 28) +#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) +#define DP_LINK_TRAIN_OFF (3 << 28) +#define DP_LINK_TRAIN_MASK (3 << 28) +#define DP_LINK_TRAIN_SHIFT 28
/* CPT Link training mode */ -#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) -#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) -#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) -#define DP_LINK_TRAIN_OFF_CPT (3 << 8) -#define DP_LINK_TRAIN_MASK_CPT (7 << 8) -#define DP_LINK_TRAIN_SHIFT_CPT 8 +#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) +#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) +#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) +#define DP_LINK_TRAIN_OFF_CPT (3 << 8) +#define DP_LINK_TRAIN_MASK_CPT (7 << 8) +#define DP_LINK_TRAIN_SHIFT_CPT 8
/* Signal voltages. These are mostly controlled by the other end */ -#define DP_VOLTAGE_0_4 (0 << 25) -#define DP_VOLTAGE_0_6 (1 << 25) -#define DP_VOLTAGE_0_8 (2 << 25) -#define DP_VOLTAGE_1_2 (3 << 25) -#define DP_VOLTAGE_MASK (7 << 25) -#define DP_VOLTAGE_SHIFT 25 +#define DP_VOLTAGE_0_4 (0 << 25) +#define DP_VOLTAGE_0_6 (1 << 25) +#define DP_VOLTAGE_0_8 (2 << 25) +#define DP_VOLTAGE_1_2 (3 << 25) +#define DP_VOLTAGE_MASK (7 << 25) +#define DP_VOLTAGE_SHIFT 25
/* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ -#define DP_PRE_EMPHASIS_0 (0 << 22) -#define DP_PRE_EMPHASIS_3_5 (1 << 22) -#define DP_PRE_EMPHASIS_6 (2 << 22) -#define DP_PRE_EMPHASIS_9_5 (3 << 22) -#define DP_PRE_EMPHASIS_MASK (7 << 22) -#define DP_PRE_EMPHASIS_SHIFT 22 +#define DP_PRE_EMPHASIS_0 (0 << 22) +#define DP_PRE_EMPHASIS_3_5 (1 << 22) +#define DP_PRE_EMPHASIS_6 (2 << 22) +#define DP_PRE_EMPHASIS_9_5 (3 << 22) +#define DP_PRE_EMPHASIS_MASK (7 << 22) +#define DP_PRE_EMPHASIS_SHIFT 22
/* How many wires to use. I guess 3 was too hard */ -#define DP_PORT_WIDTH_1 (0 << 19) -#define DP_PORT_WIDTH_2 (1 << 19) -#define DP_PORT_WIDTH_4 (3 << 19) -#define DP_PORT_WIDTH_MASK (7 << 19) +#define DP_PORT_WIDTH_1 (0 << 19) +#define DP_PORT_WIDTH_2 (1 << 19) +#define DP_PORT_WIDTH_4 (3 << 19) +#define DP_PORT_WIDTH_MASK (7 << 19)
/* Mystic DPCD version 1.1 special mode */ -#define DP_ENHANCED_FRAMING (1 << 18) +#define DP_ENHANCED_FRAMING (1 << 18)
/* eDP */ -#define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) -#define DP_PLL_FREQ_MASK (3 << 16) +#define DP_PLL_FREQ_270MHZ (0 << 16) +#define DP_PLL_FREQ_160MHZ (1 << 16) +#define DP_PLL_FREQ_MASK (3 << 16)
/** locked once port is enabled */ -#define DP_PORT_REVERSAL (1 << 15) +#define DP_PORT_REVERSAL (1 << 15)
/* eDP */ -#define DP_PLL_ENABLE (1 << 14) +#define DP_PLL_ENABLE (1 << 14)
/** sends the clock on lane 15 of the PEG for debug */ -#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) +#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
-#define DP_SCRAMBLING_DISABLE (1 << 12) -#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) +#define DP_SCRAMBLING_DISABLE (1 << 12) +#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
/** limit RGB values to avoid confusing TVs */ -#define DP_COLOR_RANGE_16_235 (1 << 8) +#define DP_COLOR_RANGE_16_235 (1 << 8)
/** Turn on the audio link */ -#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) +#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
/** vs and hs sync polarity */ -#define DP_SYNC_VS_HIGH (1 << 4) -#define DP_SYNC_HS_HIGH (1 << 3) +#define DP_SYNC_VS_HIGH (1 << 4) +#define DP_SYNC_HS_HIGH (1 << 3)
/** A fantasy */ -#define DP_DETECTED (1 << 2) +#define DP_DETECTED (1 << 2)
/** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported @@ -2309,27 +2309,27 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_DONE (1 << 30) +#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) +#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) +#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) +#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) +#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) +#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) +#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) +#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) +#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
/* * Computing GMCH M and N values for the Display Port link @@ -2348,14 +2348,14 @@ #define _PIPEB_GMCH_DATA_M 0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
-#define PIPE_GMCH_DATA_M_MASK (0xffffff) +#define PIPE_GMCH_DATA_M_MASK (0xffffff)
#define _PIPEA_GMCH_DATA_N 0x70054 #define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) +#define PIPE_GMCH_DATA_N_MASK (0xffffff)
/* * Computing Link M and N values for the Display Port link @@ -2370,11 +2370,11 @@
#define _PIPEA_DP_LINK_M 0x70060 #define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) +#define PIPEA_DP_LINK_M_MASK (0xffffff)
#define _PIPEA_DP_LINK_N 0x70064 #define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) +#define PIPEA_DP_LINK_N_MASK (0xffffff)
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) @@ -2385,81 +2385,81 @@
/* Pipe A */ #define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff +#define DSL_LINEMASK 0x00000fff #define _PIPEACONF 0x70008 -#define PIPECONF_ENABLE (1<<31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1<<25) -#define PIPECONF_PALETTE 0 -#define PIPECONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_ENABLE (1<<31) +#define PIPECONF_DISABLE 0 +#define PIPECONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) +#define PIPECONF_SINGLE_WIDE 0 +#define PIPECONF_PIPE_UNLOCKED 0 +#define PIPECONF_PIPE_LOCKED (1<<25) +#define PIPECONF_PALETTE 0 +#define PIPECONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_INTERLACE_MASK (7 << 21) /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ /* Ironlake and later have a complete new set of values for interlaced. PFIT * means panel fitter required, PF means progressive fetch, DBL means power * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_CXSR_DOWNCLOCK (1<<16) -#define PIPECONF_BPP_MASK (0x000000e0) -#define PIPECONF_BPP_8 (0<<5) -#define PIPECONF_BPP_10 (1<<5) -#define PIPECONF_BPP_6 (2<<5) -#define PIPECONF_BPP_12 (3<<5) -#define PIPECONF_DITHER_EN (1<<4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0<<2) -#define PIPECONF_DITHER_TYPE_ST1 (1<<2) -#define PIPECONF_DITHER_TYPE_ST2 (2<<2) -#define PIPECONF_DITHER_TYPE_TEMP (3<<2) +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) +#define PIPECONF_INTERLACED_ILK (3 << 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_BPP_MASK (0x000000e0) +#define PIPECONF_BPP_8 (0<<5) +#define PIPECONF_BPP_10 (1<<5) +#define PIPECONF_BPP_6 (2<<5) +#define PIPECONF_BPP_12 (3<<5) +#define PIPECONF_DITHER_EN (1<<4) +#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) +#define PIPECONF_DITHER_TYPE_SP (0<<2) +#define PIPECONF_DITHER_TYPE_ST1 (1<<2) +#define PIPECONF_DITHER_TYPE_ST2 (2<<2) +#define PIPECONF_DITHER_TYPE_TEMP (3<<2) #define _PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ -#define PIPE_8BPC (0 << 5) -#define PIPE_10BPC (1 << 5) -#define PIPE_6BPC (2 << 5) -#define PIPE_12BPC (3 << 5) +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) +#define PIPE_CRC_ERROR_ENABLE (1UL<<29) +#define PIPE_CRC_DONE_ENABLE (1UL<<28) +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) +#define PIPE_DPST_EVENT_ENABLE (1UL<<23) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) +#define PIPE_DPST_EVENT_STATUS (1UL<<7) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) @@ -2469,33 +2469,33 @@ #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -#define DSPARB_BEND_SHIFT 9 /* on 855 */ -#define DSPARB_AEND_SHIFT 0 +#define DSPARB_CSTART_MASK (0x7f << 7) +#define DSPARB_CSTART_SHIFT 7 +#define DSPARB_BSTART_MASK (0x7f) +#define DSPARB_BSTART_SHIFT 0 +#define DSPARB_BEND_SHIFT 9 /* on 855 */ +#define DSPARB_AEND_SHIFT 0
#define DSPFW1 0x70034 -#define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) -#define DSPFW_CURSORB_SHIFT 16 -#define DSPFW_CURSORB_MASK (0x3f<<16) -#define DSPFW_PLANEB_SHIFT 8 -#define DSPFW_PLANEB_MASK (0x7f<<8) -#define DSPFW_PLANEA_MASK (0x7f) +#define DSPFW_SR_SHIFT 23 +#define DSPFW_SR_MASK (0x1ff<<23) +#define DSPFW_CURSORB_SHIFT 16 +#define DSPFW_CURSORB_MASK (0x3f<<16) +#define DSPFW_PLANEB_SHIFT 8 +#define DSPFW_PLANEB_MASK (0x7f<<8) +#define DSPFW_PLANEA_MASK (0x7f) #define DSPFW2 0x70038 -#define DSPFW_CURSORA_MASK 0x00003f00 -#define DSPFW_CURSORA_SHIFT 8 -#define DSPFW_PLANEC_MASK (0x7f) +#define DSPFW_CURSORA_MASK 0x00003f00 +#define DSPFW_CURSORA_SHIFT 8 +#define DSPFW_PLANEC_MASK (0x7f) #define DSPFW3 0x7003c -#define DSPFW_HPLL_SR_EN (1<<31) -#define DSPFW_CURSOR_SR_SHIFT 24 -#define PINEVIEW_SELF_REFRESH_EN (1<<30) -#define DSPFW_CURSOR_SR_MASK (0x3f<<24) -#define DSPFW_HPLL_CURSOR_SHIFT 16 -#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) -#define DSPFW_HPLL_SR_MASK (0x1ff) +#define DSPFW_HPLL_SR_EN (1<<31) +#define DSPFW_CURSOR_SR_SHIFT 24 +#define PINEVIEW_SELF_REFRESH_EN (1<<30) +#define DSPFW_CURSOR_SR_MASK (0x3f<<24) +#define DSPFW_HPLL_CURSOR_SHIFT 16 +#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) +#define DSPFW_HPLL_SR_MASK (0x1ff)
/* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 @@ -2623,22 +2623,22 @@ * * do { * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; + * PIPE_FRAME_HIGH_SHIFT; * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); + * PIPE_FRAME_LOW_SHIFT); * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); + * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; */ -#define _PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define _PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 +#define _PIPEAFRAMEHIGH 0x70040 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 +#define _PIPEAFRAMEPIXEL 0x70044 +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_GM45 0x70040 #define _PIPEA_FLIPCOUNT_GM45 0x70044 @@ -2647,31 +2647,31 @@ /* Cursor A & B regs */ #define _CURACNTR 0x70080 /* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE 0x80000000 -#define CURSOR_GAMMA_ENABLE 0x40000000 -#define CURSOR_STRIDE_MASK 0x30000000 -#define CURSOR_FORMAT_SHIFT 24 -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) +#define CURSOR_ENABLE 0x80000000 +#define CURSOR_GAMMA_ENABLE 0x40000000 +#define CURSOR_STRIDE_MASK 0x30000000 +#define CURSOR_FORMAT_SHIFT 24 +#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) /* New style CUR*CNTR flags */ -#define CURSOR_MODE 0x27 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_PIPE_SELECT (1 << 28) -#define MCURSOR_PIPE_A 0x00 -#define MCURSOR_PIPE_B (1 << 28) -#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define CURSOR_MODE 0x27 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) +#define MCURSOR_PIPE_SELECT (1 << 28) +#define MCURSOR_PIPE_A 0x00 +#define MCURSOR_PIPE_B (1 << 28) +#define MCURSOR_GAMMA_ENABLE (1 << 26) #define _CURABASE 0x70084 #define _CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 #define CURSIZE 0x700a0 #define _CURBCNTR 0x700c0 #define _CURBBASE 0x700c4 @@ -2690,32 +2690,32 @@ #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */ -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_SHIFT 24 -#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ -#define DISPPLANE_TILED (1<<10) +#define _DSPACNTR 0x70180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_SHIFT 24 +#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ +#define DISPPLANE_TILED (1<<10) #define _DSPAADDR 0x70184 #define _DSPASTRIDE 0x70188 #define _DSPAPOS 0x7018C /* reserved */ @@ -2758,10 +2758,10 @@
/* Display B control */ #define _DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define _DSPBADDR 0x71184 #define _DSPBSTRIDE 0x71188 #define _DSPBPOS 0x7118C @@ -2771,23 +2771,23 @@
/* Sprite A control */ #define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) -#define DVS_GAMMA_ENABLE (1<<30) -#define DVS_PIXFORMAT_MASK (3<<25) -#define DVS_FORMAT_YUV422 (0<<25) -#define DVS_FORMAT_RGBX101010 (1<<25) -#define DVS_FORMAT_RGBX888 (2<<25) -#define DVS_FORMAT_RGBX161616 (3<<25) -#define DVS_SOURCE_KEY (1<<22) -#define DVS_RGB_ORDER_XBGR (1<<20) -#define DVS_YUV_BYTE_ORDER_MASK (3<<16) -#define DVS_YUV_ORDER_YUYV (0<<16) -#define DVS_YUV_ORDER_UYVY (1<<16) -#define DVS_YUV_ORDER_YVYU (2<<16) -#define DVS_YUV_ORDER_VYUY (3<<16) -#define DVS_DEST_KEY (1<<2) -#define DVS_TRICKLE_FEED_DISABLE (1<<14) -#define DVS_TILED (1<<10) +#define DVS_ENABLE (1<<31) +#define DVS_GAMMA_ENABLE (1<<30) +#define DVS_PIXFORMAT_MASK (3<<25) +#define DVS_FORMAT_YUV422 (0<<25) +#define DVS_FORMAT_RGBX101010 (1<<25) +#define DVS_FORMAT_RGBX888 (2<<25) +#define DVS_FORMAT_RGBX161616 (3<<25) +#define DVS_SOURCE_KEY (1<<22) +#define DVS_RGB_ORDER_XBGR (1<<20) +#define DVS_YUV_BYTE_ORDER_MASK (3<<16) +#define DVS_YUV_ORDER_YUYV (0<<16) +#define DVS_YUV_ORDER_UYVY (1<<16) +#define DVS_YUV_ORDER_YVYU (2<<16) +#define DVS_YUV_ORDER_VYUY (3<<16) +#define DVS_DEST_KEY (1<<2) +#define DVS_TRICKLE_FEED_DISABLE (1<<14) +#define DVS_TILED (1<<10) #define _DVSALINOFF 0x72184 #define _DVSASTRIDE 0x72188 #define _DVSAPOS 0x7218c @@ -2799,13 +2799,13 @@ #define _DVSATILEOFF 0x721a4 #define _DVSASURFLIVE 0x721ac #define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE (1<<31) -#define DVS_FILTER_MASK (3<<29) -#define DVS_FILTER_MEDIUM (0<<29) -#define DVS_FILTER_ENHANCING (1<<29) -#define DVS_FILTER_SOFTENING (2<<29) -#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) +#define DVS_SCALE_ENABLE (1<<31) +#define DVS_FILTER_MASK (3<<29) +#define DVS_FILTER_MEDIUM (0<<29) +#define DVS_FILTER_ENHANCING (1<<29) +#define DVS_FILTER_SOFTENING (2<<29) +#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) #define _DVSAGAMC 0x72300
#define _DVSBCNTR 0x73180 @@ -2835,29 +2835,29 @@ #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE (1<<31) -#define SPRITE_GAMMA_ENABLE (1<<30) -#define SPRITE_PIXFORMAT_MASK (7<<25) -#define SPRITE_FORMAT_YUV422 (0<<25) -#define SPRITE_FORMAT_RGBX101010 (1<<25) -#define SPRITE_FORMAT_RGBX888 (2<<25) -#define SPRITE_FORMAT_RGBX161616 (3<<25) -#define SPRITE_FORMAT_YUV444 (4<<25) -#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ -#define SPRITE_CSC_ENABLE (1<<24) -#define SPRITE_SOURCE_KEY (1<<22) -#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) -#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ -#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) -#define SPRITE_YUV_ORDER_YUYV (0<<16) -#define SPRITE_YUV_ORDER_UYVY (1<<16) -#define SPRITE_YUV_ORDER_YVYU (2<<16) -#define SPRITE_YUV_ORDER_VYUY (3<<16) -#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) -#define SPRITE_INT_GAMMA_ENABLE (1<<13) -#define SPRITE_TILED (1<<10) -#define SPRITE_DEST_KEY (1<<2) +#define SPRITE_ENABLE (1<<31) +#define SPRITE_GAMMA_ENABLE (1<<30) +#define SPRITE_PIXFORMAT_MASK (7<<25) +#define SPRITE_FORMAT_YUV422 (0<<25) +#define SPRITE_FORMAT_RGBX101010 (1<<25) +#define SPRITE_FORMAT_RGBX888 (2<<25) +#define SPRITE_FORMAT_RGBX161616 (3<<25) +#define SPRITE_FORMAT_YUV444 (4<<25) +#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ +#define SPRITE_CSC_ENABLE (1<<24) +#define SPRITE_SOURCE_KEY (1<<22) +#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) +#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ +#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) +#define SPRITE_YUV_ORDER_YUYV (0<<16) +#define SPRITE_YUV_ORDER_UYVY (1<<16) +#define SPRITE_YUV_ORDER_YVYU (2<<16) +#define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) +#define SPRITE_INT_GAMMA_ENABLE (1<<13) +#define SPRITE_TILED (1<<10) +#define SPRITE_DEST_KEY (1<<2) #define _SPRA_LINOFF 0x70284 #define _SPRA_STRIDE 0x70288 #define _SPRA_POS 0x7028c @@ -2868,13 +2868,13 @@ #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 #define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE (1<<31) -#define SPRITE_FILTER_MASK (3<<29) -#define SPRITE_FILTER_MEDIUM (0<<29) -#define SPRITE_FILTER_ENHANCING (1<<29) -#define SPRITE_FILTER_SOFTENING (2<<29) -#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) +#define SPRITE_SCALE_ENABLE (1<<31) +#define SPRITE_FILTER_MASK (3<<29) +#define SPRITE_FILTER_MEDIUM (0<<29) +#define SPRITE_FILTER_ENHANCING (1<<29) +#define SPRITE_FILTER_SOFTENING (2<<29) +#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) #define _SPRA_GAMC 0x70400
#define _SPRB_CTL 0x71280 @@ -2913,28 +2913,28 @@
#define CPU_VGACNTRL 0x41000
-#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) -#define DIGITAL_PORTA_NO_DETECT (0 << 0) -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) +#define DIGITAL_PORTA_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
/* refresh rate hardware control */ -#define RR_HW_CTL 0x45300 -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 +#define RR_HW_CTL 0x45300 +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
#define FDI_PLL_BIOS_0 0x46000 #define FDI_PLL_FB_CLOCK_MASK 0xff #define FDI_PLL_BIOS_1 0x46004 #define FDI_PLL_BIOS_2 0x46008 -#define DISPLAY_PORT_PLL_BIOS_0 0x4600c -#define DISPLAY_PORT_PLL_BIOS_1 0x46010 -#define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define DISPLAY_PORT_PLL_BIOS_0 0x4600c +#define DISPLAY_PORT_PLL_BIOS_1 0x46010 +#define DISPLAY_PORT_PLL_BIOS_2 0x46014
#define PCH_DSPCLK_GATE_D 0x42020 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) @@ -2949,47 +2949,47 @@ #define PCH_3DCGDIS1 0x46024 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define FDI_PLL_FREQ_CTL 0x46030 -#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) -#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 +#define FDI_PLL_FREQ_CTL 0x46030 +#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) +#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 -#define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 0x60034 -#define PIPE_DATA_N1_OFFSET 0 +#define _PIPEA_DATA_M1 0x60030 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK 0x7e000000 +#define PIPE_DATA_M1_OFFSET 0 +#define _PIPEA_DATA_N1 0x60034 +#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 0x60038 -#define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 0x6003c -#define PIPE_DATA_N2_OFFSET 0 +#define _PIPEA_DATA_M2 0x60038 +#define PIPE_DATA_M2_OFFSET 0 +#define _PIPEA_DATA_N2 0x6003c +#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 0x60040 -#define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 0x60044 -#define PIPE_LINK_N1_OFFSET 0 +#define _PIPEA_LINK_M1 0x60040 +#define PIPE_LINK_M1_OFFSET 0 +#define _PIPEA_LINK_N1 0x60044 +#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 0x60048 -#define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 0x6004c -#define PIPE_LINK_N2_OFFSET 0 +#define _PIPEA_LINK_M2 0x60048 +#define PIPE_LINK_M2_OFFSET 0 +#define _PIPEA_LINK_N2 0x6004c +#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 0x61030 -#define _PIPEB_DATA_N1 0x61034 +#define _PIPEB_DATA_M1 0x61030 +#define _PIPEB_DATA_N1 0x61034
-#define _PIPEB_DATA_M2 0x61038 -#define _PIPEB_DATA_N2 0x6103c +#define _PIPEB_DATA_M2 0x61038 +#define _PIPEB_DATA_N2 0x6103c
-#define _PIPEB_LINK_M1 0x61040 -#define _PIPEB_LINK_N1 0x61044 +#define _PIPEB_LINK_M1 0x61040 +#define _PIPEB_LINK_N1 0x61044
-#define _PIPEB_LINK_M2 0x61048 -#define _PIPEB_LINK_N2 0x6104c +#define _PIPEB_LINK_M2 0x61048 +#define _PIPEB_LINK_N2 0x6104c
#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) @@ -3002,9 +3002,9 @@
/* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_ENABLE (1<<31) +#define _PFA_CTL_1 0x68080 +#define _PFB_CTL_1 0x68880 +#define PF_ENABLE (1<<31) #define PF_FILTER_MASK (3<<23) #define PF_FILTER_PROGRAMMED (0<<23) #define PF_FILTER_MED_3x3 (1<<23) @@ -3026,35 +3026,35 @@ #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
/* legacy palette */ -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) -#define DE_SPRITEB_FLIP_DONE (1 << 29) -#define DE_SPRITEA_FLIP_DONE (1 << 28) -#define DE_PLANEB_FLIP_DONE (1 << 27) -#define DE_PLANEA_FLIP_DONE (1 << 26) -#define DE_PCU_EVENT (1 << 25) -#define DE_GTT_FAULT (1 << 24) -#define DE_POISON (1 << 23) -#define DE_PERFORM_COUNTER (1 << 22) -#define DE_PCH_EVENT (1 << 21) -#define DE_AUX_CHANNEL_A (1 << 20) -#define DE_DP_A_HOTPLUG (1 << 19) -#define DE_GSE (1 << 18) -#define DE_PIPEB_VBLANK (1 << 15) -#define DE_PIPEB_EVEN_FIELD (1 << 14) -#define DE_PIPEB_ODD_FIELD (1 << 13) -#define DE_PIPEB_LINE_COMPARE (1 << 12) -#define DE_PIPEB_VSYNC (1 << 11) +#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_SPRITEB_FLIP_DONE (1 << 29) +#define DE_SPRITEA_FLIP_DONE (1 << 28) +#define DE_PLANEB_FLIP_DONE (1 << 27) +#define DE_PLANEA_FLIP_DONE (1 << 26) +#define DE_PCU_EVENT (1 << 25) +#define DE_GTT_FAULT (1 << 24) +#define DE_POISON (1 << 23) +#define DE_PERFORM_COUNTER (1 << 22) +#define DE_PCH_EVENT (1 << 21) +#define DE_AUX_CHANNEL_A (1 << 20) +#define DE_DP_A_HOTPLUG (1 << 19) +#define DE_GSE (1 << 18) +#define DE_PIPEB_VBLANK (1 << 15) +#define DE_PIPEB_EVEN_FIELD (1 << 14) +#define DE_PIPEB_ODD_FIELD (1 << 13) +#define DE_PIPEB_LINE_COMPARE (1 << 12) +#define DE_PIPEB_VSYNC (1 << 11) #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) -#define DE_PIPEA_VBLANK (1 << 7) -#define DE_PIPEA_EVEN_FIELD (1 << 6) -#define DE_PIPEA_ODD_FIELD (1 << 5) -#define DE_PIPEA_LINE_COMPARE (1 << 4) -#define DE_PIPEA_VSYNC (1 << 3) +#define DE_PIPEA_VBLANK (1 << 7) +#define DE_PIPEA_EVEN_FIELD (1 << 6) +#define DE_PIPEA_ODD_FIELD (1 << 5) +#define DE_PIPEA_LINE_COMPARE (1 << 4) +#define DE_PIPEA_VSYNC (1 << 3) #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
/* More Ivybridge lolz */ @@ -3070,23 +3070,23 @@ #define DE_PIPEB_VBLANK_IVB (1<<5) #define DE_PIPEA_VBLANK_IVB (1<<0)
-#define DEISR 0x44000 -#define DEIMR 0x44004 -#define DEIIR 0x44008 -#define DEIER 0x4400c +#define DEISR 0x44000 +#define DEIMR 0x44004 +#define DEIIR 0x44008 +#define DEIER 0x4400c
/* GT interrupt */ #define GT_PIPE_NOTIFY (1 << 4) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) -#define GT_BSD_USER_INTERRUPT (1 << 5) +#define GT_SYNC_STATUS (1 << 2) +#define GT_USER_INTERRUPT (1 << 0) +#define GT_BSD_USER_INTERRUPT (1 << 5) #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) #define GT_BLT_USER_INTERRUPT (1 << 22)
-#define GTISR 0x44010 -#define GTIMR 0x44014 -#define GTIIR 0x44018 -#define GTIER 0x4401c +#define GTISR 0x44010 +#define GTIMR 0x44014 +#define GTIIR 0x44018 +#define GTIER 0x4401c
#define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ @@ -3106,9 +3106,9 @@ #define ILK_DPFD_CLK_GATE (1<<7)
/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ -#define ILK_CLK_FBC (1<<7) -#define ILK_DPFC_DIS1 (1<<8) -#define ILK_DPFC_DIS2 (1<<9) +#define ILK_CLK_FBC (1<<7) +#define ILK_DPFC_DIS1 (1<<8) +#define ILK_DPFC_DIS2 (1<<9)
#define IVB_CHICKEN3 0x4200c # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) @@ -3157,11 +3157,11 @@ #define SDE_AUXB (1 << 13) #define SDE_AUX_MASK (7 << 13) /* 12 reserved */ -#define SDE_CRT_HOTPLUG (1 << 11) -#define SDE_PORTD_HOTPLUG (1 << 10) -#define SDE_PORTC_HOTPLUG (1 << 9) -#define SDE_PORTB_HOTPLUG (1 << 8) -#define SDE_SDVOB_HOTPLUG (1 << 6) +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) #define SDE_HOTPLUG_MASK (0xf << 8) #define SDE_TRANSB_CRC_DONE (1 << 5) #define SDE_TRANSB_CRC_ERR (1 << 4) @@ -3186,41 +3186,41 @@ #define SDEIER 0xc400c
/* digital port hotplug */ -#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ -#define PORTD_HOTPLUG_ENABLE (1 << 20) -#define PORTD_PULSE_DURATION_2ms (0) -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) -#define PORTD_PULSE_DURATION_6ms (2 << 18) -#define PORTD_PULSE_DURATION_100ms (3 << 18) +#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0) +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) +#define PORTD_PULSE_DURATION_6ms (2 << 18) +#define PORTD_PULSE_DURATION_100ms (3 << 18) #define PORTD_PULSE_DURATION_MASK (3 << 18) -#define PORTD_HOTPLUG_NO_DETECT (0) -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) -#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) -#define PORTC_HOTPLUG_ENABLE (1 << 12) -#define PORTC_PULSE_DURATION_2ms (0) -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) -#define PORTC_PULSE_DURATION_6ms (2 << 10) -#define PORTC_PULSE_DURATION_100ms (3 << 10) +#define PORTD_HOTPLUG_NO_DETECT (0) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define PORTC_PULSE_DURATION_2ms (0) +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) +#define PORTC_PULSE_DURATION_6ms (2 << 10) +#define PORTC_PULSE_DURATION_100ms (3 << 10) #define PORTC_PULSE_DURATION_MASK (3 << 10) -#define PORTC_HOTPLUG_NO_DETECT (0) -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) -#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) -#define PORTB_HOTPLUG_ENABLE (1 << 4) -#define PORTB_PULSE_DURATION_2ms (0) -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) -#define PORTB_PULSE_DURATION_6ms (2 << 2) -#define PORTB_PULSE_DURATION_100ms (3 << 2) +#define PORTC_HOTPLUG_NO_DETECT (0) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define PORTB_PULSE_DURATION_2ms (0) +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) +#define PORTB_PULSE_DURATION_6ms (2 << 2) +#define PORTB_PULSE_DURATION_100ms (3 << 2) #define PORTB_PULSE_DURATION_MASK (3 << 2) -#define PORTB_HOTPLUG_NO_DETECT (0) -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) -#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) +#define PORTB_HOTPLUG_NO_DETECT (0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
-#define PCH_GPIOA 0xc5010 -#define PCH_GPIOB 0xc5014 -#define PCH_GPIOC 0xc5018 -#define PCH_GPIOD 0xc501c -#define PCH_GPIOE 0xc5020 -#define PCH_GPIOF 0xc5024 +#define PCH_GPIOA 0xc5010 +#define PCH_GPIOB 0xc5014 +#define PCH_GPIOC 0xc5018 +#define PCH_GPIOD 0xc501c +#define PCH_GPIOE 0xc5020 +#define PCH_GPIOF 0xc5024
#define PCH_GMBUS0 0xc5100 #define PCH_GMBUS1 0xc5104 @@ -3229,54 +3229,54 @@ #define PCH_GMBUS4 0xc5110 #define PCH_GMBUS5 0xc5120
-#define _PCH_DPLL_A 0xc6014 -#define _PCH_DPLL_B 0xc6018 +#define _PCH_DPLL_A 0xc6014 +#define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-#define _PCH_FPA0 0xc6040 +#define _PCH_FPA0 0xc6040 #define FP_CB_TUNE (0x3<<22) -#define _PCH_FPA1 0xc6044 -#define _PCH_FPB0 0xc6048 -#define _PCH_FPB1 0xc604c +#define _PCH_FPA1 0xc6044 +#define _PCH_FPB0 0xc6048 +#define _PCH_FPB1 0xc604c #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
-#define PCH_DPLL_TEST 0xc606c +#define PCH_DPLL_TEST 0xc606c
-#define PCH_DREF_CONTROL 0xC6200 -#define DREF_CONTROL_MASK 0x7fc3 -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) +#define PCH_DREF_CONTROL 0xC6200 +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) -#define DREF_SSC_SOURCE_DISABLE (0<<11) -#define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_DISABLE (0<<11) +#define DREF_SSC_SOURCE_ENABLE (2<<11) #define DREF_SSC_SOURCE_MASK (3<<11) -#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) #define DREF_NONSPREAD_CK505_ENABLE (1<<9) -#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) #define DREF_NONSPREAD_SOURCE_MASK (3<<9) -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) -#define DREF_SSC4_DOWNSPREAD (0<<6) -#define DREF_SSC4_CENTERSPREAD (1<<6) -#define DREF_SSC1_DISABLE (0<<1) -#define DREF_SSC1_ENABLE (1<<1) -#define DREF_SSC4_DISABLE (0) -#define DREF_SSC4_ENABLE (1) +#define DREF_SSC4_DOWNSPREAD (0<<6) +#define DREF_SSC4_CENTERSPREAD (1<<6) +#define DREF_SSC1_DISABLE (0<<1) +#define DREF_SSC1_ENABLE (1<<1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1)
-#define PCH_RAWCLK_FREQ 0xc6204 -#define FDL_TP1_TIMER_SHIFT 12 -#define FDL_TP1_TIMER_MASK (3<<12) -#define FDL_TP2_TIMER_SHIFT 10 -#define FDL_TP2_TIMER_MASK (3<<10) -#define RAWCLK_FREQ_MASK 0x3ff +#define PCH_RAWCLK_FREQ 0xc6204 +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3<<12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3<<10) +#define RAWCLK_FREQ_MASK 0x3ff
-#define PCH_DPLL_TMR_CFG 0xc6208 +#define PCH_DPLL_TMR_CFG 0xc6208
-#define PCH_SSC4_PARMS 0xc6210 -#define PCH_SSC4_AUX_PARMS 0xc6214 +#define PCH_SSC4_PARMS 0xc6210 +#define PCH_SSC4_AUX_PARMS 0xc6214
#define PCH_DPLL_SEL 0xc7000 #define TRANSA_DPLL_ENABLE (1<<3) @@ -3291,55 +3291,55 @@
/* transcoder */
-#define _TRANS_HTOTAL_A 0xe0000 -#define TRANS_HTOTAL_SHIFT 16 -#define TRANS_HACTIVE_SHIFT 0 -#define _TRANS_HBLANK_A 0xe0004 +#define _TRANS_HTOTAL_A 0xe0000 +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 +#define _TRANS_HBLANK_A 0xe0004 #define TRANS_HBLANK_END_SHIFT 16 #define TRANS_HBLANK_START_SHIFT 0 -#define _TRANS_HSYNC_A 0xe0008 +#define _TRANS_HSYNC_A 0xe0008 #define TRANS_HSYNC_END_SHIFT 16 #define TRANS_HSYNC_START_SHIFT 0 -#define _TRANS_VTOTAL_A 0xe000c -#define TRANS_VTOTAL_SHIFT 16 -#define TRANS_VACTIVE_SHIFT 0 -#define _TRANS_VBLANK_A 0xe0010 +#define _TRANS_VTOTAL_A 0xe000c +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 +#define _TRANS_VBLANK_A 0xe0010 #define TRANS_VBLANK_END_SHIFT 16 #define TRANS_VBLANK_START_SHIFT 0 -#define _TRANS_VSYNC_A 0xe0014 +#define _TRANS_VSYNC_A 0xe0014 #define TRANS_VSYNC_END_SHIFT 16 #define TRANS_VSYNC_START_SHIFT 0 #define _TRANS_VSYNCSHIFT_A 0xe0028
-#define _TRANSA_DATA_M1 0xe0030 -#define _TRANSA_DATA_N1 0xe0034 -#define _TRANSA_DATA_M2 0xe0038 -#define _TRANSA_DATA_N2 0xe003c -#define _TRANSA_DP_LINK_M1 0xe0040 -#define _TRANSA_DP_LINK_N1 0xe0044 -#define _TRANSA_DP_LINK_M2 0xe0048 -#define _TRANSA_DP_LINK_N2 0xe004c +#define _TRANSA_DATA_M1 0xe0030 +#define _TRANSA_DATA_N1 0xe0034 +#define _TRANSA_DATA_M2 0xe0038 +#define _TRANSA_DATA_N2 0xe003c +#define _TRANSA_DP_LINK_M1 0xe0040 +#define _TRANSA_DP_LINK_N1 0xe0044 +#define _TRANSA_DP_LINK_M2 0xe0048 +#define _TRANSA_DP_LINK_N2 0xe004c
/* Per-transcoder DIP controls */
-#define _VIDEO_DIP_CTL_A 0xe0200 -#define _VIDEO_DIP_DATA_A 0xe0208 -#define _VIDEO_DIP_GCP_A 0xe0210 +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_GCP_A 0xe0210
-#define _VIDEO_DIP_CTL_B 0xe1200 -#define _VIDEO_DIP_DATA_B 0xe1208 -#define _VIDEO_DIP_GCP_B 0xe1210 +#define _VIDEO_DIP_CTL_B 0xe1200 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define _VIDEO_DIP_GCP_B 0xe1210
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define _TRANS_HTOTAL_B 0xe1000 -#define _TRANS_HBLANK_B 0xe1004 -#define _TRANS_HSYNC_B 0xe1008 -#define _TRANS_VTOTAL_B 0xe100c -#define _TRANS_VBLANK_B 0xe1010 -#define _TRANS_VSYNC_B 0xe1014 +#define _TRANS_HTOTAL_B 0xe1000 +#define _TRANS_HBLANK_B 0xe1004 +#define _TRANS_HSYNC_B 0xe1008 +#define _TRANS_VTOTAL_B 0xe100c +#define _TRANS_VBLANK_B 0xe1010 +#define _TRANS_VSYNC_B 0xe1014 #define _TRANS_VSYNCSHIFT_B 0xe1028
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) @@ -3349,16 +3349,16 @@ #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ - _TRANS_VSYNCSHIFT_B) + _TRANS_VSYNCSHIFT_B)
-#define _TRANSB_DATA_M1 0xe1030 -#define _TRANSB_DATA_N1 0xe1034 -#define _TRANSB_DATA_M2 0xe1038 -#define _TRANSB_DATA_N2 0xe103c -#define _TRANSB_DP_LINK_M1 0xe1040 -#define _TRANSB_DP_LINK_N1 0xe1044 -#define _TRANSB_DP_LINK_M2 0xe1048 -#define _TRANSB_DP_LINK_N2 0xe104c +#define _TRANSB_DATA_M1 0xe1030 +#define _TRANSB_DATA_N1 0xe1034 +#define _TRANSB_DATA_M2 0xe1038 +#define _TRANSB_DATA_N2 0xe103c +#define _TRANSB_DP_LINK_M1 0xe1040 +#define _TRANSB_DP_LINK_N1 0xe1044 +#define _TRANSB_DP_LINK_M2 0xe1048 +#define _TRANSB_DP_LINK_N2 0xe104c
#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) @@ -3369,33 +3369,33 @@ #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
-#define _TRANSACONF 0xf0008 -#define _TRANSBCONF 0xf1008 +#define _TRANSACONF 0xf0008 +#define _TRANSBCONF 0xf1008 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) -#define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) -#define TRANS_STATE_MASK (1<<30) -#define TRANS_STATE_DISABLE (0<<30) -#define TRANS_STATE_ENABLE (1<<30) +#define TRANS_DISABLE (0<<31) +#define TRANS_ENABLE (1<<31) +#define TRANS_STATE_MASK (1<<30) +#define TRANS_STATE_DISABLE (0<<30) +#define TRANS_STATE_ENABLE (1<<30) #define TRANS_FSYNC_DELAY_HB1 (0<<27) #define TRANS_FSYNC_DELAY_HB2 (1<<27) #define TRANS_FSYNC_DELAY_HB3 (2<<27) #define TRANS_FSYNC_DELAY_HB4 (3<<27) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_VIDEO_AUDIO (0<<26) -#define TRANS_INTERLACE_MASK (7<<21) -#define TRANS_PROGRESSIVE (0<<21) -#define TRANS_INTERLACED (3<<21) +#define TRANS_DP_AUDIO_ONLY (1<<26) +#define TRANS_DP_VIDEO_AUDIO (0<<26) +#define TRANS_INTERLACE_MASK (7<<21) +#define TRANS_PROGRESSIVE (0<<21) +#define TRANS_INTERLACED (3<<21) #define TRANS_LEGACY_INTERLACED_ILK (2<<21) -#define TRANS_8BPC (0<<5) -#define TRANS_10BPC (1<<5) -#define TRANS_6BPC (2<<5) -#define TRANS_12BPC (3<<5) +#define TRANS_8BPC (0<<5) +#define TRANS_10BPC (1<<5) +#define TRANS_6BPC (2<<5) +#define TRANS_12BPC (3<<5)
#define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
#define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 @@ -3405,8 +3405,8 @@ #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
-#define _FDI_RXA_CHICKEN 0xc200c -#define _FDI_RXB_CHICKEN 0xc2010 +#define _FDI_RXA_CHICKEN 0xc200c +#define _FDI_RXB_CHICKEN 0xc2010 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) @@ -3415,23 +3415,23 @@ #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
/* CPU: FDI_TX */ -#define _FDI_TXA_CTL 0x60100 -#define _FDI_TXB_CTL 0x61100 +#define _FDI_TXA_CTL 0x60100 +#define _FDI_TXB_CTL 0x61100 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) -#define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) -#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) -#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) -#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) -#define FDI_LINK_TRAIN_NONE (3<<28) -#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) -#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) +#define FDI_TX_DISABLE (0<<31) +#define FDI_TX_ENABLE (1<<31) +#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) +#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) +#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) +#define FDI_LINK_TRAIN_NONE (3<<28) +#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) +#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* SNB A-stepping */ @@ -3445,48 +3445,48 @@ #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) -#define FDI_DP_PORT_WIDTH_X1 (0<<19) -#define FDI_DP_PORT_WIDTH_X2 (1<<19) -#define FDI_DP_PORT_WIDTH_X3 (2<<19) -#define FDI_DP_PORT_WIDTH_X4 (3<<19) -#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) +#define FDI_DP_PORT_WIDTH_X1 (0<<19) +#define FDI_DP_PORT_WIDTH_X2 (1<<19) +#define FDI_DP_PORT_WIDTH_X3 (2<<19) +#define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) /* Ironlake: hardwired to 1 */ -#define FDI_TX_PLL_ENABLE (1<<14) +#define FDI_TX_PLL_ENABLE (1<<14)
/* Ivybridge has different bits for lolz */ -#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) +#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) +#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) -#define FDI_LINK_TRAIN_NONE_IVB (3<<8) +#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
/* both Tx and Rx */ #define FDI_COMPOSITE_SYNC (1<<11) #define FDI_LINK_TRAIN_AUTO (1<<10) -#define FDI_SCRAMBLING_ENABLE (0<<7) -#define FDI_SCRAMBLING_DISABLE (1<<7) +#define FDI_SCRAMBLING_ENABLE (0<<7) +#define FDI_SCRAMBLING_DISABLE (1<<7)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ -#define _FDI_RXA_CTL 0xf000c -#define _FDI_RXB_CTL 0xf100c +#define _FDI_RXA_CTL 0xf000c +#define _FDI_RXB_CTL 0xf100c #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_ENABLE (1<<31) /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE (1<<27) #define FDI_FE_ERRC_ENABLE (1<<26) -#define FDI_DP_PORT_WIDTH_X8 (7<<19) -#define FDI_8BPC (0<<16) -#define FDI_10BPC (1<<16) -#define FDI_6BPC (2<<16) -#define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) -#define FDI_DMI_LINK_REVERSE_MASK (1<<14) -#define FDI_RX_PLL_ENABLE (1<<13) -#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) -#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) -#define FDI_FS_ERR_REPORT_ENABLE (1<<9) -#define FDI_FE_ERR_REPORT_ENABLE (1<<8) -#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) -#define FDI_PCDCLK (1<<4) +#define FDI_DP_PORT_WIDTH_X8 (7<<19) +#define FDI_8BPC (0<<16) +#define FDI_10BPC (1<<16) +#define FDI_6BPC (2<<16) +#define FDI_12BPC (3<<16) +#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_DMI_LINK_REVERSE_MASK (1<<14) +#define FDI_RX_PLL_ENABLE (1<<13) +#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) +#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) +#define FDI_FS_ERR_REPORT_ENABLE (1<<9) +#define FDI_FE_ERR_REPORT_ENABLE (1<<8) +#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) +#define FDI_PCDCLK (1<<4) /* CPT */ #define FDI_AUTO_TRAINING (1<<10) #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) @@ -3495,91 +3495,91 @@ #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
-#define _FDI_RXA_MISC 0xf0010 -#define _FDI_RXB_MISC 0xf1010 -#define _FDI_RXA_TUSIZE1 0xf0030 -#define _FDI_RXA_TUSIZE2 0xf0038 -#define _FDI_RXB_TUSIZE1 0xf1030 -#define _FDI_RXB_TUSIZE2 0xf1038 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define _FDI_RXA_TUSIZE1 0xf0030 +#define _FDI_RXA_TUSIZE2 0xf0038 +#define _FDI_RXB_TUSIZE1 0xf1030 +#define _FDI_RXB_TUSIZE2 0xf1038 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
/* FDI_RX interrupt register format */ -#define FDI_RX_INTER_LANE_ALIGN (1<<10) -#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ -#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ -#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) -#define FDI_RX_FS_CODE_ERR (1<<6) -#define FDI_RX_FE_CODE_ERR (1<<5) -#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) -#define FDI_RX_HDCP_LINK_FAIL (1<<3) -#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) -#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) -#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) - -#define _FDI_RXA_IIR 0xf0014 -#define _FDI_RXA_IMR 0xf0018 -#define _FDI_RXB_IIR 0xf1014 -#define _FDI_RXB_IMR 0xf1018 +#define FDI_RX_INTER_LANE_ALIGN (1<<10) +#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ +#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ +#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) +#define FDI_RX_FS_CODE_ERR (1<<6) +#define FDI_RX_FE_CODE_ERR (1<<5) +#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) +#define FDI_RX_HDCP_LINK_FAIL (1<<3) +#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) +#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) +#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) + +#define _FDI_RXA_IIR 0xf0014 +#define _FDI_RXA_IMR 0xf0018 +#define _FDI_RXB_IIR 0xf1014 +#define _FDI_RXB_IMR 0xf1018 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
-#define FDI_PLL_CTL_1 0xfe000 -#define FDI_PLL_CTL_2 0xfe004 +#define FDI_PLL_CTL_1 0xfe000 +#define FDI_PLL_CTL_2 0xfe004
/* CRT */ -#define PCH_ADPA 0xe1100 +#define PCH_ADPA 0xe1100 #define ADPA_TRANS_SELECT_MASK (1<<30) -#define ADPA_TRANS_A_SELECT 0 -#define ADPA_TRANS_B_SELECT (1<<30) +#define ADPA_TRANS_A_SELECT 0 +#define ADPA_TRANS_B_SELECT (1<<30) #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) -#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) -#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) -#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) -#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) -#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) -#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) -#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) -#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) +#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) +#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) +#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) +#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) +#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) +#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) +#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) +#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
/* or SDVOB */ -#define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) -#define TRANSCODER(pipe) ((pipe) << 30) -#define TRANSCODER_CPT(pipe) ((pipe) << 29) -#define TRANSCODER_MASK (1 << 30) -#define TRANSCODER_MASK_CPT (3 << 29) -#define COLOR_FORMAT_8bpc (0) -#define COLOR_FORMAT_12bpc (3 << 26) -#define SDVOB_HOTPLUG_ENABLE (1 << 23) -#define SDVO_ENCODING (0) -#define TMDS_ENCODING (2 << 10) -#define NULL_PACKET_VSYNC_ENABLE (1 << 9) +#define HDMIB 0xe1140 +#define PORT_ENABLE (1 << 31) +#define TRANSCODER(pipe) ((pipe) << 30) +#define TRANSCODER_CPT(pipe) ((pipe) << 29) +#define TRANSCODER_MASK (1 << 30) +#define TRANSCODER_MASK_CPT (3 << 29) +#define COLOR_FORMAT_8bpc (0) +#define COLOR_FORMAT_12bpc (3 << 26) +#define SDVOB_HOTPLUG_ENABLE (1 << 23) +#define SDVO_ENCODING (0) +#define TMDS_ENCODING (2 << 10) +#define NULL_PACKET_VSYNC_ENABLE (1 << 9) /* CPT */ #define HDMI_MODE_SELECT (1 << 9) #define DVI_MODE_SELECT (0) -#define SDVOB_BORDER_ENABLE (1 << 7) -#define AUDIO_ENABLE (1 << 6) -#define VSYNC_ACTIVE_HIGH (1 << 4) -#define HSYNC_ACTIVE_HIGH (1 << 3) -#define PORT_DETECTED (1 << 2) +#define SDVOB_BORDER_ENABLE (1 << 7) +#define AUDIO_ENABLE (1 << 6) +#define VSYNC_ACTIVE_HIGH (1 << 4) +#define HSYNC_ACTIVE_HIGH (1 << 3) +#define PORT_DETECTED (1 << 2)
/* PCH SDVOB multiplex with HDMIB */ #define PCH_SDVOB HDMIB
-#define HDMIC 0xe1150 -#define HDMID 0xe1160 +#define HDMIC 0xe1150 +#define HDMID 0xe1160
#define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) @@ -3723,16 +3723,16 @@ #define FORCEWAKE_MT 0xa188 /* multi-threaded */ #define FORCEWAKE_MT_ACK 0x130040 #define ECOBUS 0xa180 -#define FORCEWAKE_MT_ENABLE (1<<5) +#define FORCEWAKE_MT_ENABLE (1<<5)
#define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 -#define GT_FIFO_OVFERR (1<<2) -#define GT_FIFO_IAWRERR (1<<1) -#define GT_FIFO_IARDERR (1<<0) +#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_OVFERR (1<<2) +#define GT_FIFO_IAWRERR (1<<1) +#define GT_FIFO_IARDERR (1<<0)
#define GT_FIFO_FREE_ENTRIES 0x120008 -#define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL1 0x9400 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) @@ -3743,46 +3743,46 @@ # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
#define GEN6_RPNSWREQ 0xA008 -#define GEN6_TURBO_DISABLE (1<<31) -#define GEN6_FREQUENCY(x) ((x)<<25) -#define GEN6_OFFSET(x) ((x)<<19) -#define GEN6_AGGRESSIVE_TURBO (0<<15) +#define GEN6_TURBO_DISABLE (1<<31) +#define GEN6_FREQUENCY(x) ((x)<<25) +#define GEN6_OFFSET(x) ((x)<<19) +#define GEN6_AGGRESSIVE_TURBO (0<<15) #define GEN6_RC_VIDEO_FREQ 0xA00C #define GEN6_RC_CONTROL 0xA090 -#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) -#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) -#define GEN6_RC_CTL_RC6_ENABLE (1<<18) -#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) -#define GEN6_RC_CTL_RC7_ENABLE (1<<22) -#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) -#define GEN6_RC_CTL_HW_ENABLE (1<<31) +#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) +#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) +#define GEN6_RC_CTL_RC6_ENABLE (1<<18) +#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) +#define GEN6_RC_CTL_RC7_ENABLE (1<<22) +#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) +#define GEN6_RC_CTL_HW_ENABLE (1<<31) #define GEN6_RP_DOWN_TIMEOUT 0xA010 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 #define GEN6_RPSTAT1 0xA01C -#define GEN6_CAGF_SHIFT 8 -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) +#define GEN6_CAGF_SHIFT 8 +#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) #define GEN6_RP_CONTROL 0xA024 -#define GEN6_RP_MEDIA_TURBO (1<<11) -#define GEN6_RP_MEDIA_MODE_MASK (3<<9) -#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) -#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) -#define GEN6_RP_MEDIA_HW_MODE (1<<9) -#define GEN6_RP_MEDIA_SW_MODE (0<<9) -#define GEN6_RP_MEDIA_IS_GFX (1<<8) -#define GEN6_RP_ENABLE (1<<7) -#define GEN6_RP_UP_IDLE_MIN (0x1<<3) -#define GEN6_RP_UP_BUSY_AVG (0x2<<3) -#define GEN6_RP_UP_BUSY_CONT (0x4<<3) -#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) +#define GEN6_RP_MEDIA_TURBO (1<<11) +#define GEN6_RP_MEDIA_MODE_MASK (3<<9) +#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) +#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) +#define GEN6_RP_MEDIA_HW_MODE (1<<9) +#define GEN6_RP_MEDIA_SW_MODE (0<<9) +#define GEN6_RP_MEDIA_IS_GFX (1<<8) +#define GEN6_RP_ENABLE (1<<7) +#define GEN6_RP_UP_IDLE_MIN (0x1<<3) +#define GEN6_RP_UP_BUSY_AVG (0x2<<3) +#define GEN6_RP_UP_BUSY_CONT (0x4<<3) +#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) #define GEN6_RP_UP_THRESHOLD 0xA02C #define GEN6_RP_DOWN_THRESHOLD 0xA030 #define GEN6_RP_CUR_UP_EI 0xA050 -#define GEN6_CURICONT_MASK 0xffffff +#define GEN6_CURICONT_MASK 0xffffff #define GEN6_RP_CUR_UP 0xA054 -#define GEN6_CURBSYTAVG_MASK 0xffffff +#define GEN6_CURBSYTAVG_MASK 0xffffff #define GEN6_RP_PREV_UP 0xA058 #define GEN6_RP_CUR_DOWN_EI 0xA05C -#define GEN6_CURIAVG_MASK 0xffffff +#define GEN6_CURIAVG_MASK 0xffffff #define GEN6_RP_CUR_DOWN 0xA060 #define GEN6_RP_PREV_DOWN 0xA064 #define GEN6_RP_UP_EI 0xA068 @@ -3817,20 +3817,20 @@ GEN6_PM_RP_DOWN_TIMEOUT)
#define GEN6_PCODE_MAILBOX 0x138124 -#define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 +#define GEN6_PCODE_READY (1<<31) +#define GEN6_READ_OC_PARAMS 0xc +#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 +#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_DATA 0x138128 -#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_GT_CORE_STATUS 0x138060 -#define GEN6_CORE_CPD_STATE_MASK (7<<4) -#define GEN6_RCn_MASK 7 -#define GEN6_RC0 0 -#define GEN6_RC3 2 -#define GEN6_RC6 3 -#define GEN6_RC7 4 +#define GEN6_CORE_CPD_STATE_MASK (7<<4) +#define GEN6_RCn_MASK 7 +#define GEN6_RC0 0 +#define GEN6_RC3 2 +#define GEN6_RC6 3 +#define GEN6_RC7 4
#define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB @@ -3865,14 +3865,14 @@
#define IBX_AUD_CONFIG_A 0xe2000 #define CPT_AUD_CONFIG_A 0xe5000 -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) -#define AUD_CONFIG_UPPER_N_SHIFT 20 -#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) -#define AUD_CONFIG_LOWER_N_SHIFT 4 -#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) +#define AUD_CONFIG_UPPER_N_SHIFT 20 +#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) +#define AUD_CONFIG_LOWER_N_SHIFT 4 +#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 +#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) +#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
#endif /* _I915_REG_H_ */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index dae4e68..34f6064 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -36,10 +36,10 @@ #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 - revision */ -#define PCI_REVISION_ID 0x08 /* Revision ID */ -#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ -#define PCI_CLASS_DEVICE 0x0a /* Device class */ + revision */ +#define PCI_REVISION_ID 0x08 /* Revision ID */ +#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ +#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ @@ -180,7 +180,7 @@ #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrupts */ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ -#define PCI_CAP_ID_HT 0x08 /* Hypertransport */ +#define PCI_CAP_ID_HT 0x08 /* Hypertransport */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ @@ -189,23 +189,23 @@
/* Hypertransport Registers */ #define PCI_HT_CAP_SIZEOF 4 -#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ -#define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ -#define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ +#define PCI_HT_CAP_HOST_CTRL 4 /* Host link control */ +#define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */ +#define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */ #define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */ -#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ -#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ +#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ +#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ #define PCI_HT_CAP_SLAVE_WIDTH0 6 /* width value & capability */ #define PCI_HT_CAP_SLAVE_WIDTH1 0x0a /* width value & capability to */ -#define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */ -#define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ +#define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */ +#define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */ #define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */ #define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */ #define PCI_HT_CAP_SLAVE_LINK_ENUM 0x14 /* Link Enumeration Scratchpad */
/* Power Management Registers */
-#define PCI_PM_PMC 2 /* PM Capabilities Register */ +#define PCI_PM_PMC 2 /* PM Capabilities Register */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxiliary power support */ @@ -312,16 +312,16 @@ #define PCI_X_SSTATUS_SPL_OVR 0x0010 /* Split Completion Overrun */ #define PCI_X_SSTATUS_SPL_DLY 0x0020 /* Split Completion Delayed */ #define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6) /* PCI-X mode and frequency */ -#define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0 -#define PCI_X_SSTATUS_MODE1_66MHZ 0x1 -#define PCI_X_SSTATUS_MODE1_100MHZ 0x2 -#define PCI_X_SSTATUS_MODE1_133MHZ 0x3 -#define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ 0x9 -#define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ 0xa -#define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ 0xb -#define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ 0xd -#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe -#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf +#define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0 +#define PCI_X_SSTATUS_MODE1_66MHZ 0x1 +#define PCI_X_SSTATUS_MODE1_100MHZ 0x2 +#define PCI_X_SSTATUS_MODE1_133MHZ 0x3 +#define PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ 0x9 +#define PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ 0xa +#define PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ 0xb +#define PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ 0xd +#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe +#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf #define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3) /* Version */ #define PCI_X_SSTATUS_266MHZ 0x4000 /* The bus behind the bridge is 266Mhz Capable */ #define PCI_X_SSTAUTS_533MHZ 0x8000 /* The bus behind the bridge is 533Mhz Capable */ @@ -452,11 +452,11 @@ #define PCI_PWR_DSR 4 /* Data Select Register */ #define PCI_PWR_DATA 8 /* Data Register */ #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ -#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ +#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ -#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ -#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ +#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ +#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 50ab96c..43f8056 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -220,8 +220,8 @@ #define PCI_DEVICE_ID_ATI_215_LR 0x4c52 #define PCI_DEVICE_ID_ATI_215_LS 0x4c53 #define PCI_DEVICE_ID_ATI_264_LT 0x4c54 -#define PCI_DEVICE_ID_ATI_215LG 0x4c47 -#define PCI_DEVICE_ID_ATI_264LT 0x4c54 +#define PCI_DEVICE_ID_ATI_215LG 0x4c47 +#define PCI_DEVICE_ID_ATI_264LT 0x4c54 /* Mach64 VT */ #define PCI_DEVICE_ID_ATI_264VT 0x5654 #define PCI_DEVICE_ID_ATI_264VU 0x5655 @@ -319,52 +319,52 @@ #define PCI_DEVICE_ID_ATI_SB700_USB_19_2 0x4396 #define PCI_DEVICE_ID_ATI_SB700_USB_20_5 0x4399
-#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D -#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390 -#define PCI_DEVICE_ID_ATI_SB800_SATA_AHCI 0x4391 -#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID 0x4392 -#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID5 0x4393 -#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C -#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383 -#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384 -#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0 -#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1 -#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2 -#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3 -#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385 -#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399 -#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397 -#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 -#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 - -#define PCI_DEVICE_ID_ATI_SB900_LPC 0x780E -#define PCI_DEVICE_ID_ATI_SB900_SATA 0x7800 -#define PCI_DEVICE_ID_ATI_SB900_SATA_AHCI 0x7801 -#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID 0x7802 -#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID5 0x7803 -#define PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI 0x7804 -#define PCI_DEVICE_ID_ATI_SB900_IDE 0x780C -#define PCI_DEVICE_ID_ATI_SB900_HDA 0x780D -#define PCI_DEVICE_ID_ATI_SB900_PCI 0x780F -#define PCI_DEVICE_ID_ATI_SB900_PCIEA 0x43A0 -#define PCI_DEVICE_ID_ATI_SB900_PCIEB 0x43A1 -#define PCI_DEVICE_ID_ATI_SB900_PCIEC 0x43A2 -#define PCI_DEVICE_ID_ATI_SB900_PCIED 0x43A3 -#define PCI_DEVICE_ID_ATI_SB900_SM 0x780B -#define PCI_DEVICE_ID_ATI_SB900_USB_16_0 0x7812 -#define PCI_DEVICE_ID_ATI_SB900_USB_16_1 0x7812 -#define PCI_DEVICE_ID_ATI_SB900_USB_18_0 0x7807 -#define PCI_DEVICE_ID_ATI_SB900_USB_18_2 0x7808 -#define PCI_DEVICE_ID_ATI_SB900_USB_19_0 0x7807 -#define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808 -#define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809 -#define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806 -#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 -#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 +#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D +#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390 +#define PCI_DEVICE_ID_ATI_SB800_SATA_AHCI 0x4391 +#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID 0x4392 +#define PCI_DEVICE_ID_ATI_SB800_SATA_RAID5 0x4393 +#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C +#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383 +#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384 +#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0 +#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1 +#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2 +#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3 +#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397 +#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396 +#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 + +#define PCI_DEVICE_ID_ATI_SB900_LPC 0x780E +#define PCI_DEVICE_ID_ATI_SB900_SATA 0x7800 +#define PCI_DEVICE_ID_ATI_SB900_SATA_AHCI 0x7801 +#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID 0x7802 +#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID5 0x7803 +#define PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI 0x7804 +#define PCI_DEVICE_ID_ATI_SB900_IDE 0x780C +#define PCI_DEVICE_ID_ATI_SB900_HDA 0x780D +#define PCI_DEVICE_ID_ATI_SB900_PCI 0x780F +#define PCI_DEVICE_ID_ATI_SB900_PCIEA 0x43A0 +#define PCI_DEVICE_ID_ATI_SB900_PCIEB 0x43A1 +#define PCI_DEVICE_ID_ATI_SB900_PCIEC 0x43A2 +#define PCI_DEVICE_ID_ATI_SB900_PCIED 0x43A3 +#define PCI_DEVICE_ID_ATI_SB900_SM 0x780B +#define PCI_DEVICE_ID_ATI_SB900_USB_16_0 0x7812 +#define PCI_DEVICE_ID_ATI_SB900_USB_16_1 0x7812 +#define PCI_DEVICE_ID_ATI_SB900_USB_18_0 0x7807 +#define PCI_DEVICE_ID_ATI_SB900_USB_18_2 0x7808 +#define PCI_DEVICE_ID_ATI_SB900_USB_19_0 0x7807 +#define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808 +#define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809 +#define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806 +#define PCI_DEVICE_ID_AMD_HUDSON_SD 0x7806 +#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 @@ -410,7 +410,7 @@ #define PCI_DEVICE_ID_AMD_SR5670_HT 0x5A12 #define PCI_DEVICE_ID_AMD_SR5650_HT 0x5A13 #define PCI_DEVICE_ID_AMD_990FX_HT 0x5A14 -#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 +#define PCI_DEVICE_ID_AMD_SR5650_PCIE 0x5A12 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2 0x5A16 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3 0x5A17 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV4 0x5A18 @@ -454,11 +454,11 @@ #define PCI_DEVICE_ID_NS_CS5535_USB 0x002f #define PCI_DEVICE_ID_NS_CS5535_GX2VGA 0x0030 #define PCI_DEVICE_ID_NS_SCx200_BRIDGE 0x0500 -#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 -#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 -#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 -#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 -#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 +#define PCI_DEVICE_ID_NS_SCx200_SMI 0x0501 +#define PCI_DEVICE_ID_NS_SCx200_IDE 0x0502 +#define PCI_DEVICE_ID_NS_SCx200_AUDIO 0x0503 +#define PCI_DEVICE_ID_NS_SCx200_VIDEO 0x0504 +#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505 #define PCI_DEVICE_ID_NS_87410 0xd001
@@ -575,21 +575,21 @@ #define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449
#define PCI_DEVICE_ID_AMD_8151_SYSCTRL 0x7454 -#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455 -#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 -#define PCI_DEVICE_ID_AMD_8111_USB 0x7464 -#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468 -#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 -#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a -#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b +#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455 +#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 +#define PCI_DEVICE_ID_AMD_8111_USB 0x7464 +#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a +#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b #define PCI_DEVICE_ID_AMD_8111_NIC 0x7462
-#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 +#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 #define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 -#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 +#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451
-#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458 -#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459 +#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458 +#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459 #define PCI_DEVICE_ID_AMD_AES 0x2082 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 @@ -623,7 +623,7 @@ #define PCI_VENDOR_ID_AI 0x1025 #define PCI_DEVICE_ID_AI_M1435 0x1435
-#define PCI_VENDOR_ID_DELL 0x1028 +#define PCI_VENDOR_ID_DELL 0x1028
#define PCI_VENDOR_ID_MATROX 0x102B #define PCI_DEVICE_ID_MATROX_MGA_2 0x0518 @@ -653,7 +653,7 @@ #define PCI_VENDOR_ID_NEC 0x1033 #define PCI_DEVICE_ID_NEC_PCX2 0x0046 #define PCI_DEVICE_ID_NEC_NILE4 0x005a -#define PCI_DEVICE_ID_NEC_VRC5476 0x009b +#define PCI_DEVICE_ID_NEC_VRC5476 0x009b #define PCI_DEVICE_ID_NEC_VRC5477_AC97 0x00a6
#define PCI_VENDOR_ID_FD 0x1036 @@ -847,10 +847,10 @@ #define PCI_DEVICE_ID_X_AGX016 0x0001
#define PCI_VENDOR_ID_MYLEX 0x1069 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 -#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V2 0x0001 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V3 0x0002 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V4 0x0010 +#define PCI_DEVICE_ID_MYLEX_DAC960P_V5 0x0020 #define PCI_DEVICE_ID_MYLEX_DAC960_P 0x0001 #define PCI_DEVICE_ID_MYLEX_DAC960_PD 0x0002 #define PCI_DEVICE_ID_MYLEX_DAC960_PG 0x0010 @@ -980,7 +980,7 @@ #define PCI_DEVICE_ID_DATABOOK_87144 0xb106
#define PCI_VENDOR_ID_PLX 0x10b5 -#define PCI_VENDOR_ID_PLX_ROMULUS 0x106a +#define PCI_VENDOR_ID_PLX_ROMULUS 0x106a #define PCI_DEVICE_ID_PLX_R685 0x1030 #define PCI_DEVICE_ID_PLX_ROMULUS 0x106a #define PCI_DEVICE_ID_PLX_SPCOM800 0x1076 @@ -1028,12 +1028,12 @@ #define PCI_DEVICE_ID_AL_M1531 0x1531 #define PCI_DEVICE_ID_AL_M1533 0x1533 #define PCI_DEVICE_ID_AL_M1541 0x1541 -#define PCI_DEVICE_ID_AL_M1621 0x1621 -#define PCI_DEVICE_ID_AL_M1631 0x1631 -#define PCI_DEVICE_ID_AL_M1641 0x1641 -#define PCI_DEVICE_ID_AL_M1644 0x1644 -#define PCI_DEVICE_ID_AL_M1647 0x1647 -#define PCI_DEVICE_ID_AL_M1651 0x1651 +#define PCI_DEVICE_ID_AL_M1621 0x1621 +#define PCI_DEVICE_ID_AL_M1631 0x1631 +#define PCI_DEVICE_ID_AL_M1641 0x1641 +#define PCI_DEVICE_ID_AL_M1644 0x1644 +#define PCI_DEVICE_ID_AL_M1647 0x1647 +#define PCI_DEVICE_ID_AL_M1651 0x1651 #define PCI_DEVICE_ID_AL_M1543 0x1543 #define PCI_DEVICE_ID_AL_M3307 0x3307 #define PCI_DEVICE_ID_AL_M4803 0x5215 @@ -1054,7 +1054,7 @@ #define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002 #define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003 #define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004 -#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 +#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV 0x0005 #define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS 0x0083
#define PCI_VENDOR_ID_ASP 0x10cd @@ -1075,46 +1075,46 @@ #define PCI_DEVICE_ID_CERN_HIPPI_DST 0x0021 #define PCI_DEVICE_ID_CERN_HIPPI_SRC 0x0022
-#define PCI_DEVICE_ID_NVIDIA_CK8S_HT 0x00e1 -#define PCI_DEVICE_ID_NVIDIA_CK8S_LPC 0x00e0 -#define PCI_DEVICE_ID_NVIDIA_CK8S_SM 0x00e4 -#define PCI_DEVICE_ID_NVIDIA_CK8S_USB 0x00e7 -#define PCI_DEVICE_ID_NVIDIA_CK8S_USB2 0x00e8 -#define PCI_DEVICE_ID_NVIDIA_CK8S_NIC 0x00e6 -#define PCI_DEVICE_ID_NVIDIA_CK8S_ACI 0x00ea -#define PCI_DEVICE_ID_NVIDIA_CK8S_MCI 0x00e9 -#define PCI_DEVICE_ID_NVIDIA_CK8S_IDE 0x00e5 -#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA0 0x00ee -#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA1 0x00e3 -#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI 0x00ed +#define PCI_DEVICE_ID_NVIDIA_CK8S_HT 0x00e1 +#define PCI_DEVICE_ID_NVIDIA_CK8S_LPC 0x00e0 +#define PCI_DEVICE_ID_NVIDIA_CK8S_SM 0x00e4 +#define PCI_DEVICE_ID_NVIDIA_CK8S_USB 0x00e7 +#define PCI_DEVICE_ID_NVIDIA_CK8S_USB2 0x00e8 +#define PCI_DEVICE_ID_NVIDIA_CK8S_NIC 0x00e6 +#define PCI_DEVICE_ID_NVIDIA_CK8S_ACI 0x00ea +#define PCI_DEVICE_ID_NVIDIA_CK8S_MCI 0x00e9 +#define PCI_DEVICE_ID_NVIDIA_CK8S_IDE 0x00e5 +#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA0 0x00ee +#define PCI_DEVICE_ID_NVIDIA_CK8S_SATA1 0x00e3 +#define PCI_DEVICE_ID_NVIDIA_CK8S_PCI 0x00ed #define PCI_DEVICE_ID_NVIDIA_CK8S_PCI_AGP 0x00e2
-#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360 -#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365 -#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367 -#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368 -#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E -#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E -#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F -#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372 -#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373 -#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371 -#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C -#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377 -#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378 -#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369 -#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A -#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC 0x0360 +#define PCI_DEVICE_ID_NVIDIA_MCP55_SLAVE 0x0361 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2 0x0362 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3 0x0363 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4 0x0364 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5 0x0365 +#define PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6 0x0366 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PRO 0x0367 +#define PCI_DEVICE_ID_NVIDIA_MCP55_SM2 0x0368 +#define PCI_DEVICE_ID_NVIDIA_MCP55_IDE 0x036E +#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA0 0x037E +#define PCI_DEVICE_ID_NVIDIA_MCP55_SATA1 0x037F +#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC 0x0372 +#define PCI_DEVICE_ID_NVIDIA_MCP55_NIC_BRIDGE 0x0373 +#define PCI_DEVICE_ID_NVIDIA_MCP55_AZA 0x0371 +#define PCI_DEVICE_ID_NVIDIA_MCP55_USB 0x036C +#define PCI_DEVICE_ID_NVIDIA_MCP55_USB2 0x036D +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCI 0x0370 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C 0x0374 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E 0x0375 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A 0x0376 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F 0x0377 +#define PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D 0x0378 +#define PCI_DEVICE_ID_NVIDIA_MCP55_HT 0x0369 +#define PCI_DEVICE_ID_NVIDIA_MCP55_TRIM 0x036A +#define PCI_DEVICE_ID_NVIDIA_MCP55_PMU 0x036B
#define PCI_VENDOR_ID_NVIDIA 0x10de #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 @@ -1122,32 +1122,32 @@ #define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D -#define PCI_DEVICE_ID_NVIDIA_CK804_LPC 0x0050 -#define PCI_DEVICE_ID_NVIDIA_CK804_PRO 0x0051 -#define PCI_DEVICE_ID_NVIDIA_CK804_ISA 0x0051 -#define PCI_DEVICE_ID_NVIDIA_CK804_SMB 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_SM 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI 0x0052 -#define PCI_DEVICE_ID_NVIDIA_CK804_IDE 0x0053 -#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0 0x0054 -#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055 -#define PCI_DEVICE_ID_NVIDIA_CK804_ENET 0x0056 -#define PCI_DEVICE_ID_NVIDIA_CK804_NIC 0x0056 -#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2 0x0057 -#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE 0x0057 -#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM 0x0058 -#define PCI_DEVICE_ID_NVIDIA_CK804_MCI 0x0058 -#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 -#define PCI_DEVICE_ID_NVIDIA_CK804_ACI 0x0059 -#define PCI_DEVICE_ID_NVIDIA_CK804_USB 0x005A -#define PCI_DEVICE_ID_NVIDIA_CK804_USB2 0x005B -#define PCI_DEVICE_ID_NVIDIA_CK804_PCI 0x005C -#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005D -#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E 0x005D -#define PCI_DEVICE_ID_NVIDIA_CK804_MEM 0x005E -#define PCI_DEVICE_ID_NVIDIA_CK804_HT 0x005E -#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM 0x005f -#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE 0x00d3 +#define PCI_DEVICE_ID_NVIDIA_CK804_LPC 0x0050 +#define PCI_DEVICE_ID_NVIDIA_CK804_PRO 0x0051 +#define PCI_DEVICE_ID_NVIDIA_CK804_ISA 0x0051 +#define PCI_DEVICE_ID_NVIDIA_CK804_SMB 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_SM 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_ACPI 0x0052 +#define PCI_DEVICE_ID_NVIDIA_CK804_IDE 0x0053 +#define PCI_DEVICE_ID_NVIDIA_CK804_SATA0 0x0054 +#define PCI_DEVICE_ID_NVIDIA_CK804_SATA1 0x0055 +#define PCI_DEVICE_ID_NVIDIA_CK804_ENET 0x0056 +#define PCI_DEVICE_ID_NVIDIA_CK804_NIC 0x0056 +#define PCI_DEVICE_ID_NVIDIA_CK804_ENET2 0x0057 +#define PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE 0x0057 +#define PCI_DEVICE_ID_NVIDIA_CK804_MODEM 0x0058 +#define PCI_DEVICE_ID_NVIDIA_CK804_MCI 0x0058 +#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 +#define PCI_DEVICE_ID_NVIDIA_CK804_ACI 0x0059 +#define PCI_DEVICE_ID_NVIDIA_CK804_USB 0x005A +#define PCI_DEVICE_ID_NVIDIA_CK804_USB2 0x005B +#define PCI_DEVICE_ID_NVIDIA_CK804_PCI 0x005C +#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE 0x005D +#define PCI_DEVICE_ID_NVIDIA_CK804_PCI_E 0x005D +#define PCI_DEVICE_ID_NVIDIA_CK804_MEM 0x005E +#define PCI_DEVICE_ID_NVIDIA_CK804_HT 0x005E +#define PCI_DEVICE_ID_NVIDIA_CK804_TRIM 0x005f +#define PCI_DEVICE_ID_NVIDIA_CK804_SLAVE 0x00d3 #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 #define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 @@ -1197,7 +1197,7 @@ #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139
-#define PCI_VENDOR_ID_TYAN 0x10f1 +#define PCI_VENDOR_ID_TYAN 0x10f1 #define PCI_VENDOR_ID_XILINX 0x10ee #define PCI_DEVICE_ID_TURBOPAM 0x4020
@@ -1246,7 +1246,7 @@ #define PCI_DEVICE_ID_VIA_82C693_1 0x0698 #define PCI_DEVICE_ID_VIA_82C926 0x0926 #define PCI_DEVICE_ID_VIA_82C576_1 0x1571 -#define PCI_DEVICE_ID_VIA_82C416 0x1571 +#define PCI_DEVICE_ID_VIA_82C416 0x1571 #define PCI_DEVICE_ID_VIA_82C595_97 0x1595 #define PCI_DEVICE_ID_VIA_82C586_2 0x3038 #define PCI_DEVICE_ID_VIA_82C586_3 0x3040 @@ -1381,8 +1381,8 @@ #define PCI_DEVICE_ID_VIA_CN400_BRIDGE 0xB198 #define PCI_DEVICE_ID_VIA_CN400_VGA 0x3118
-#define PCI_VENDOR_ID_SIEMENS 0x110A -#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 +#define PCI_VENDOR_ID_SIEMENS 0x110A +#define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102
#define PCI_VENDOR_ID_SMC2 0x1113 #define PCI_DEVICE_ID_SMC2_1211TX 0x1211 @@ -1501,15 +1501,15 @@ #define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017 #define PCI_DEVICE_ID_SERVERWORKS_OSB4 0x0200 #define PCI_DEVICE_ID_SERVERWORKS_CSB5 0x0201 -#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 +#define PCI_DEVICE_ID_SERVERWORKS_CSB6 0x0203 #define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211 #define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212 #define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213 #define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220 #define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB #define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221 -#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 -#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE 0x0225 +#define PCI_DEVICE_ID_SERVERWORKS_GCLE2 0x0227 #define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
#define PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB 0x0130 @@ -1522,8 +1522,8 @@ #define PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2 0x144
#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_HT_PXB 0x0036 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_PXBX 0x0104 -#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA 0x024a +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_PXBX 0x0104 +#define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA 0x024a #define PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN 0x0205 #define PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE 0x0214 #define PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC 0x0234 @@ -1595,8 +1595,8 @@ #define PCI_VENDOR_ID_V3 0x11b0 #define PCI_DEVICE_ID_V3_V960 0x0001 #define PCI_DEVICE_ID_V3_V350 0x0001 -#define PCI_DEVICE_ID_V3_V960V2 0x0002 -#define PCI_DEVICE_ID_V3_V350V2 0x0002 +#define PCI_DEVICE_ID_V3_V960V2 0x0002 +#define PCI_DEVICE_ID_V3_V350V2 0x0002 #define PCI_DEVICE_ID_V3_V961 0x0002 #define PCI_DEVICE_ID_V3_V351 0x0002
@@ -1885,7 +1885,7 @@ #define PCI_DEVICE_ID_3WARE_1000 0x1000
#define PCI_VENDOR_ID_ABOCOM 0x13D1 -#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1 +#define PCI_DEVICE_ID_ABOCOM_2BD1 0x2BD1
#define PCI_VENDOR_ID_CMEDIA 0x13f6 #define PCI_DEVICE_ID_CMEDIA_CM8338A 0x0100 @@ -2573,15 +2573,15 @@ #define PCI_DEVICE_ID_INTEL_6300ESB_WDT 0x25ab
/* Intel 3100 */ -#define PCI_DEVICE_ID_INTEL_3100_LPC 0x2670 -#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c -#define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e -#define PCI_DEVICE_ID_INTEL_3100_IDE 0x2680 -#define PCI_DEVICE_ID_INTEL_3100_AHCI 0x2681 -#define PCI_DEVICE_ID_INTEL_3100_UHCI 0x2688 +#define PCI_DEVICE_ID_INTEL_3100_LPC 0x2670 +#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c +#define PCI_DEVICE_ID_INTEL_3100_PCI 0x244e +#define PCI_DEVICE_ID_INTEL_3100_IDE 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_AHCI 0x2681 +#define PCI_DEVICE_ID_INTEL_3100_UHCI 0x2688 #define PCI_DEVICE_ID_INTEL_3100_UHCI2 0x2689 -#define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b -#define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0 +#define PCI_DEVICE_ID_INTEL_3100_SMB 0x269b +#define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7 #define PCI_DEVICE_ID_INTEL_3100_PCIE_PB0 0x2690 @@ -2590,13 +2590,13 @@ #define PCI_DEVICE_ID_INTEL_3100_PCIE_PB3 0x2696
/* Intel EP80579 */ -#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031 +#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031 #define PCI_DEVICE_ID_INTEL_EP80579_EHCI 0x5035 -#define PCI_DEVICE_ID_INTEL_EP80579_IDE 0x5028 +#define PCI_DEVICE_ID_INTEL_EP80579_IDE 0x5028 #define PCI_DEVICE_ID_INTEL_EP80579_AHCI 0x5029 #define PCI_DEVICE_ID_INTEL_EP80579_UHCI 0x5033 -#define PCI_DEVICE_ID_INTEL_EP80579_SMB 0x5032 -#define PCI_DEVICE_ID_INTEL_EP80579_MC 0x5020 +#define PCI_DEVICE_ID_INTEL_EP80579_SMB 0x5032 +#define PCI_DEVICE_ID_INTEL_EP80579_MC 0x5020 #define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0 0x5024 #define PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1 0x5025
@@ -2621,7 +2621,7 @@ #define PCI_DEVICE_ID_INTEL_82454GX 0x84c4 #define PCI_DEVICE_ID_INTEL_82450GX 0x84c5 #define PCI_DEVICE_ID_INTEL_82451NX 0x84ca -#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb +#define PCI_DEVICE_ID_INTEL_82454NX 0x84cb #define PCI_DEVICE_ID_INTEL_PCIE_PA 0x3595 #define PCI_DEVICE_ID_INTEL_PCIE_PA1 0x3596 #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 @@ -2774,11 +2774,11 @@ #define PCI_DEVICE_ID_SIS_SIS968_HD_AUDIO 0x7502 /* DfF0 */
/* OLD USAGE FOR COREBOOT */ -#define PCI_VENDOR_ID_ACER 0x10b9 -#define PCI_DEVICE_ID_ACER_M1535D 0x1533 +#define PCI_VENDOR_ID_ACER 0x10b9 +#define PCI_DEVICE_ID_ACER_M1535D 0x1533
-#define PCI_DEVICE_ID_AMD_761_0 0x700E -#define PCI_DEVICE_ID_AMD_761_1 0x700F -#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412 +#define PCI_DEVICE_ID_AMD_761_0 0x700E +#define PCI_DEVICE_ID_AMD_761_1 0x700F +#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412
/* END OLDER USAGE */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 87a5002..a243a75 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -5,12 +5,12 @@ enum aspm_type { PCIE_ASPM_NONE = 0, PCIE_ASPM_L0S = 1, - PCIE_ASPM_L1 = 2, + PCIE_ASPM_L1 = 2, PCIE_ASPM_BOTH = 3, };
unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); + unsigned int max_devfn, unsigned int max); unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index a229edb..2750b91 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -45,7 +45,7 @@ struct pnp_info { #define PNP_IRQ1 0x020 #define PNP_DRQ0 0x040 #define PNP_DRQ1 0x080 -#define PNP_EN 0x100 +#define PNP_EN 0x100 #define PNP_MSC0 0x200 #define PNP_MSC1 0x400 struct io_info io0, io1, io2, io3; diff --git a/src/include/ehci.h b/src/include/ehci.h index f920352..a6a1880 100644 --- a/src/include/ehci.h +++ b/src/include/ehci.h @@ -50,11 +50,11 @@ struct ehci_caps { #define HCC_HW_PREFETCH(p) ((p)&(1 << 16))
#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ -#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ -#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ +#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ +#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ -#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ +#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ u8 portroute[8]; /* nibbles for routing - offset 0xC */ } __attribute__ ((packed));
@@ -151,7 +151,7 @@ struct ehci_regs { #define PORT_PE (1<<2) /* port enable */ #define PORT_CSC (1<<1) /* connect status change */ #define PORT_CONNECT (1<<0) /* device connected */ -#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) +#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) } __attribute__ ((packed));
#define USBMODE 0x68 /* USB Device mode */ diff --git a/src/include/elog.h b/src/include/elog.h index f9b5d53..b9fad83 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -23,111 +23,111 @@ #if CONFIG_ELOG
/* SMI command code for GSMI event logging */ -#define ELOG_GSMI_APM_CNT 0xEF +#define ELOG_GSMI_APM_CNT 0xEF
-#define MAX_EVENT_SIZE 0x7F +#define MAX_EVENT_SIZE 0x7F
/* End of log */ -#define ELOG_TYPE_EOL 0xFF +#define ELOG_TYPE_EOL 0xFF
/* * Standard SMBIOS event log types below 0x80 */ -#define ELOG_TYPE_UNDEFINED_EVENT 0x00 +#define ELOG_TYPE_UNDEFINED_EVENT 0x00 #define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01 -#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 -#define ELOG_TYPE_MEM_PARITY_ERR 0x03 -#define ELOG_TYPE_BUS_TIMEOUT 0x04 -#define ELOG_TYPE_IO_CHECK 0x05 -#define ELOG_TYPE_SW_NMI 0x06 -#define ELOG_TYPE_POST_MEM_RESIZE 0x07 -#define ELOG_TYPE_POST_ERR 0x08 -#define ELOG_TYPE_PCI_PERR 0x09 -#define ELOG_TYPE_PCI_SERR 0x0A -#define ELOG_TYPE_CPU_FAIL 0x0B -#define ELOG_TYPE_EISA_TIMEOUT 0x0C +#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02 +#define ELOG_TYPE_MEM_PARITY_ERR 0x03 +#define ELOG_TYPE_BUS_TIMEOUT 0x04 +#define ELOG_TYPE_IO_CHECK 0x05 +#define ELOG_TYPE_SW_NMI 0x06 +#define ELOG_TYPE_POST_MEM_RESIZE 0x07 +#define ELOG_TYPE_POST_ERR 0x08 +#define ELOG_TYPE_PCI_PERR 0x09 +#define ELOG_TYPE_PCI_SERR 0x0A +#define ELOG_TYPE_CPU_FAIL 0x0B +#define ELOG_TYPE_EISA_TIMEOUT 0x0C #define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D -#define ELOG_TYPE_LOG_DISABLED 0x0E -#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F -#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 +#define ELOG_TYPE_LOG_DISABLED 0x0E +#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F +#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10 #define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11 -#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 -#define ELOG_TYPE_HDD_INFO 0x13 -#define ELOG_TYPE_SYS_RECONFIG 0x14 -#define ELOG_TYPE_CPU_ERROR 0x15 -#define ELOG_TYPE_LOG_CLEAR 0x16 -#define ELOG_TYPE_BOOT 0x17 +#define ELOG_TYPE_SYS_CONFIG_INFO 0x12 +#define ELOG_TYPE_HDD_INFO 0x13 +#define ELOG_TYPE_SYS_RECONFIG 0x14 +#define ELOG_TYPE_CPU_ERROR 0x15 +#define ELOG_TYPE_LOG_CLEAR 0x16 +#define ELOG_TYPE_BOOT 0x17
/* * Extended defined OEM event types start at 0x80 */
/* OS/kernel events */ -#define ELOG_TYPE_OS_EVENT 0x81 +#define ELOG_TYPE_OS_EVENT 0x81
/* Last event from coreboot */ -#define ELOG_TYPE_OS_BOOT 0x90 +#define ELOG_TYPE_OS_BOOT 0x90
/* Embedded controller event */ -#define ELOG_TYPE_EC_EVENT 0x91 -#define EC_EVENT_LID_CLOSED 0x01 -#define EC_EVENT_LID_OPEN 0x02 -#define EC_EVENT_POWER_BUTTON 0x03 -#define EC_EVENT_AC_CONNECTED 0x04 -#define EC_EVENT_AC_DISCONNECTED 0x05 -#define EC_EVENT_BATTERY_LOW 0x06 -#define EC_EVENT_BATTERY_CRITICAL 0x07 -#define EC_EVENT_BATTERY 0x08 -#define EC_EVENT_THERMAL_THRESHOLD 0x09 -#define EC_EVENT_THERMAL_OVERLOAD 0x0a -#define EC_EVENT_THERMAL 0x0b -#define EC_EVENT_USB_CHARGER 0x0c -#define EC_EVENT_KEY_PRESSED 0x0d -#define EC_EVENT_INTERFACE_READY 0x0e -#define EC_EVENT_KEYBOARD_RECOVERY 0x0f -#define EC_EVENT_THERMAL_SHUTDOWN 0x10 -#define EC_EVENT_BATTERY_SHUTDOWN 0x11 -#define EC_EVENT_FAN_ERROR 0x12 +#define ELOG_TYPE_EC_EVENT 0x91 +#define EC_EVENT_LID_CLOSED 0x01 +#define EC_EVENT_LID_OPEN 0x02 +#define EC_EVENT_POWER_BUTTON 0x03 +#define EC_EVENT_AC_CONNECTED 0x04 +#define EC_EVENT_AC_DISCONNECTED 0x05 +#define EC_EVENT_BATTERY_LOW 0x06 +#define EC_EVENT_BATTERY_CRITICAL 0x07 +#define EC_EVENT_BATTERY 0x08 +#define EC_EVENT_THERMAL_THRESHOLD 0x09 +#define EC_EVENT_THERMAL_OVERLOAD 0x0a +#define EC_EVENT_THERMAL 0x0b +#define EC_EVENT_USB_CHARGER 0x0c +#define EC_EVENT_KEY_PRESSED 0x0d +#define EC_EVENT_INTERFACE_READY 0x0e +#define EC_EVENT_KEYBOARD_RECOVERY 0x0f +#define EC_EVENT_THERMAL_SHUTDOWN 0x10 +#define EC_EVENT_BATTERY_SHUTDOWN 0x11 +#define EC_EVENT_FAN_ERROR 0x12
/* Power */ -#define ELOG_TYPE_POWER_FAIL 0x92 -#define ELOG_TYPE_SUS_POWER_FAIL 0x93 -#define ELOG_TYPE_PWROK_FAIL 0x94 -#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 -#define ELOG_TYPE_POWER_ON 0x96 -#define ELOG_TYPE_POWER_BUTTON 0x97 -#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98 +#define ELOG_TYPE_POWER_FAIL 0x92 +#define ELOG_TYPE_SUS_POWER_FAIL 0x93 +#define ELOG_TYPE_PWROK_FAIL 0x94 +#define ELOG_TYPE_SYS_PWROK_FAIL 0x95 +#define ELOG_TYPE_POWER_ON 0x96 +#define ELOG_TYPE_POWER_BUTTON 0x97 +#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98
/* Reset */ -#define ELOG_TYPE_RESET_BUTTON 0x99 -#define ELOG_TYPE_SYSTEM_RESET 0x9a -#define ELOG_TYPE_RTC_RESET 0x9b -#define ELOG_TYPE_TCO_RESET 0x9c +#define ELOG_TYPE_RESET_BUTTON 0x99 +#define ELOG_TYPE_SYSTEM_RESET 0x9a +#define ELOG_TYPE_RTC_RESET 0x9b +#define ELOG_TYPE_TCO_RESET 0x9c
/* Sleep/Wake */ -#define ELOG_TYPE_ACPI_ENTER 0x9d -#define ELOG_TYPE_ACPI_WAKE 0x9e -#define ELOG_TYPE_WAKE_SOURCE 0x9f -#define ELOG_WAKE_SOURCE_PCIE 0x00 -#define ELOG_WAKE_SOURCE_PME 0x01 -#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 -#define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 -#define ELOG_WAKE_SOURCE_SMBUS 0x05 -#define ELOG_WAKE_SOURCE_PWRBTN 0x06 +#define ELOG_TYPE_ACPI_ENTER 0x9d +#define ELOG_TYPE_ACPI_WAKE 0x9e +#define ELOG_TYPE_WAKE_SOURCE 0x9f +#define ELOG_WAKE_SOURCE_PCIE 0x00 +#define ELOG_WAKE_SOURCE_PME 0x01 +#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 +#define ELOG_WAKE_SOURCE_RTC 0x03 +#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_SMBUS 0x05 +#define ELOG_WAKE_SOURCE_PWRBTN 0x06 struct elog_event_data_wake { u8 source; u32 instance; } __attribute__ ((packed));
/* Chrome OS related events */ -#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 -#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 -#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02 +#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 +#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
/* Management Engine Events */ -#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 -#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 +#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4 struct elog_event_data_me_extended { u8 current_working_state; u8 operation_state; @@ -139,11 +139,11 @@ struct elog_event_data_me_extended { } __attribute__ ((packed));
/* Last post code from previous boot */ -#define ELOG_TYPE_LAST_POST_CODE 0xa3 -#define ELOG_TYPE_POST_EXTRA 0xa6 +#define ELOG_TYPE_LAST_POST_CODE 0xa3 +#define ELOG_TYPE_POST_EXTRA 0xa6
/* EC Shutdown Reason */ -#define ELOG_TYPE_EC_SHUTDOWN 0xa5 +#define ELOG_TYPE_EC_SHUTDOWN 0xa5
extern int elog_init(void); extern int elog_clear(void); diff --git a/src/include/memrange.h b/src/include/memrange.h index 0e69b2f..ec43054 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -62,7 +62,7 @@ static inline unsigned long range_entry_tag(const struct range_entry *r) }
static inline void range_entry_update_tag(struct range_entry *r, - unsigned long new_tag) + unsigned long new_tag) { r->tag = new_tag; } @@ -79,8 +79,8 @@ static inline void range_entry_update_tag(struct range_entry *r, * mask and match type for all memory resources. Tag each entry with the * specified type. */ void memranges_init(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag); + unsigned long mask, unsigned long match, + unsigned long tag);
/* Remove and free all entries within the memranges structure. */ void memranges_teardown(struct memranges *ranges); @@ -89,28 +89,28 @@ void memranges_teardown(struct memranges *ranges); * Each entry will be tagged with the provided tag. e.g. To populate * all cacheable memory resources in the range: * memranges_add_resources(range, IORESOURCE_CACHEABLE, - * IORESROUCE_CACHEABLE, my_cacheable_tag); */ + * IORESROUCE_CACHEABLE, my_cacheable_tag); */ void memranges_add_resources(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag); + unsigned long mask, unsigned long match, + unsigned long tag);
/* Fill all address ranges up to limit (exclusive) not covered by an entry by * inserting new entries with the provided tag. */ void memranges_fill_holes_up_to(struct memranges *ranges, - resource_t limit, unsigned long tag); + resource_t limit, unsigned long tag);
/* Create a hole in the range by deleting/modifying entries that overlap with * the region specified by base and size. */ void memranges_create_hole(struct memranges *ranges, - resource_t base, resource_t size); + resource_t base, resource_t size);
/* Insert a resource to the given memranges. All existing ranges * covered by range specified by base and size will be removed before a * new one is added. */ void memranges_insert(struct memranges *ranges, - resource_t base, resource_t size, unsigned long tag); + resource_t base, resource_t size, unsigned long tag);
/* Returns next entry after the provided entry. NULL if r is last. */ struct range_entry *memranges_next_entry(struct memranges *ranges, - const struct range_entry *r); + const struct range_entry *r); #endif /* MEMRANGE_H_ */ diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h index f4f0dca..bacf8b3 100644 --- a/src/include/pc80/i8254.h +++ b/src/include/pc80/i8254.h @@ -23,40 +23,40 @@ /* Ports for the 8254 timer chip */ #define TIMER0_PORT 0x40 #define TIMER1_PORT 0x41 -#define TIMER2_PORT 0x42 +#define TIMER2_PORT 0x42 #define TIMER_MODE_PORT 0x43
/* Meaning of the mode bits */ -#define TIMER0_SEL 0x00 -#define TIMER1_SEL 0x40 -#define TIMER2_SEL 0x80 -#define READBACK_SEL 0xC0 - -#define LATCH_COUNT 0x00 -#define LOBYTE_ACCESS 0x10 -#define HIBYTE_ACCESS 0x20 -#define WORD_ACCESS 0x30 - -#define MODE0 0x00 -#define MODE1 0x02 -#define MODE2 0x04 -#define MODE3 0x06 -#define MODE4 0x08 -#define MODE5 0x0A - -#define BINARY_COUNT 0x00 -#define BCD_COUNT 0x01 +#define TIMER0_SEL 0x00 +#define TIMER1_SEL 0x40 +#define TIMER2_SEL 0x80 +#define READBACK_SEL 0xC0 + +#define LATCH_COUNT 0x00 +#define LOBYTE_ACCESS 0x10 +#define HIBYTE_ACCESS 0x20 +#define WORD_ACCESS 0x30 + +#define MODE0 0x00 +#define MODE1 0x02 +#define MODE2 0x04 +#define MODE3 0x06 +#define MODE4 0x08 +#define MODE5 0x0A + +#define BINARY_COUNT 0x00 +#define BCD_COUNT 0x01
/* Timers tick over at this rate */ -#define TICKS_PER_MS 1193 +#define TICKS_PER_MS 1193
/* Parallel Peripheral Controller Port B */ -#define PPC_PORTB 0x61 +#define PPC_PORTB 0x61
/* Meaning of the port bits */ -#define PPCB_T2OUT 0x20 /* Bit 5 */ -#define PPCB_SPKR 0x02 /* Bit 1 */ -#define PPCB_T2GATE 0x01 /* Bit 0 */ +#define PPCB_T2OUT 0x20 /* Bit 5 */ +#define PPCB_SPKR 0x02 /* Bit 1 */ +#define PPCB_T2GATE 0x01 /* Bit 0 */
void setup_i8254(void); #endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index fd40308..02e4c16 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -178,10 +178,10 @@ enum cb_err get_option(void *dest, const char *name); unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); #else static inline enum cb_err set_option(const char *name __attribute__((unused)), - void *val __attribute__((unused))) + void *val __attribute__((unused))) { return CB_CMOS_OTABLE_DISABLED; }; static inline enum cb_err get_option(void *dest __attribute__((unused)), - const char *name __attribute__((unused))) + const char *name __attribute__((unused))) { return CB_CMOS_OTABLE_DISABLED; } #define read_option_lowlevel(start, size, def) def #endif @@ -209,13 +209,13 @@ static inline enum cb_err get_option(void *dest __attribute__((unused)), * 3-6 = BANK 0 Extra log * 7-10 = BANK 1 Extra log */ -#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) -#define CMOS_POST_BANK_0_MAGIC 0x80 -#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) -#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) -#define CMOS_POST_BANK_1_MAGIC 0x81 -#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) -#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7) +#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET) +#define CMOS_POST_BANK_0_MAGIC 0x80 +#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1) +#define CMOS_POST_BANK_0_EXTRA (CMOS_POST_OFFSET + 3) +#define CMOS_POST_BANK_1_MAGIC 0x81 +#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2) +#define CMOS_POST_BANK_1_EXTRA (CMOS_POST_OFFSET + 7)
#define CMOS_POST_EXTRA_DEV_PATH 0x01
diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 247711a..b4416ef 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -50,7 +50,7 @@ int rmodule_load_alignment(const struct rmodule *m); * load_offset is the address to load and relocate the rmodule. * region_alignment must be a power of 2. */ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, - size_t *region_size, int *load_offset); + size_t *region_size, int *load_offset);
#define FIELD_ENTRY(x_) ((u32)&x_) #define RMODULE_HEADER(entry_, type_) \ diff --git a/src/include/sdram_mode.h b/src/include/sdram_mode.h index 4146240..c77d4e0 100644 --- a/src/include/sdram_mode.h +++ b/src/include/sdram_mode.h @@ -29,22 +29,22 @@ // These are transmitted via A0-A13
// Burst length -#define SDRAM_BURST_2 (1<<0) -#define SDRAM_BURST_4 (2<<0) -#define SDRAM_BURST_8 (3<<0) +#define SDRAM_BURST_2 (1<<0) +#define SDRAM_BURST_4 (2<<0) +#define SDRAM_BURST_8 (3<<0)
#define SDRAM_BURST_SEQUENTIAL (0<<3) #define SDRAM_BURST_INTERLEAVED (1<<3)
#define SDRAM_CAS_2_0 (2<<4) -#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */ -#define SDRAM_CAS_1_5 (5<<4) /* Optional */ -#define SDRAM_CAS_2_5 (6<<4) -#define SDRAM_CAS_MASK (7<<4) +#define SDRAM_CAS_3_0 (3<<4) /* Optional for DDR 200-333 */ +#define SDRAM_CAS_1_5 (5<<4) /* Optional */ +#define SDRAM_CAS_2_5 (6<<4) +#define SDRAM_CAS_MASK (7<<4)
#define SDRAM_MODE_NORMAL (0 << 7) -#define SDRAM_MODE_TEST (1 << 7) -#define SDRAM_MODE_DLL_RESET (2 << 7) +#define SDRAM_MODE_TEST (1 << 7) +#define SDRAM_MODE_DLL_RESET (2 << 7)
// Extended Mode Register
diff --git a/src/include/smbios.h b/src/include/smbios.h index 42c5d2d..06f38b5 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -25,12 +25,12 @@ void smbios_mainboard_set_uuid(u8 *uuid); #define BIOS_CHARACTERISTICS_PNP (1 << 9) #define BIOS_CHARACTERISTICS_APM (1 << 10) #define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11) -#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) +#define BIOS_CHARACTERISTICS_SHADOW (1 << 12) #define BIOS_CHARACTERISTICS_BOOT_FROM_CD (1 << 15) #define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16) #define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17)
-#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2)
#define SMBIOS_STATE_SAFE 3 diff --git a/src/include/spd.h b/src/include/spd.h index 2b07fb1..6e16249 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -24,12 +24,12 @@ * * Datasheet: * - Name: PC SDRAM Serial Presence Detect (SPD) Specification - * Revision 1.2A, December, 1997 + * Revision 1.2A, December, 1997 * - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf * * Datasheet (alternative): * - Name: SERIAL PRESENCE DETECT STANDARD, General Standard - * JEDEC Standard No. 21-C + * JEDEC Standard No. 21-C * - PDF: http://www.jedec.org/download/search/4_01_02_00R9.PDF */
@@ -37,72 +37,72 @@ #define _SPD_H_
/* Byte numbers. */ -#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ -#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ -#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ -#define SPD_NUM_ROWS 3 /* Number of row address bits */ -#define SPD_NUM_COLUMNS 4 /* Number of column address bits */ -#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ -#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ -#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ -#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ -#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ -#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ -#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ -#define SPD_REFRESH 12 /* Refresh rate/type */ -#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ -#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ +#define SPD_NUM_MANUFACTURER_BYTES 0 /* Number of bytes used by module manufacturer */ +#define SPD_TOTAL_SPD_MEMORY_SIZE 1 /* Total SPD memory size */ +#define SPD_MEMORY_TYPE 2 /* (Fundamental) memory type */ +#define SPD_NUM_ROWS 3 /* Number of row address bits */ +#define SPD_NUM_COLUMNS 4 /* Number of column address bits */ +#define SPD_NUM_DIMM_BANKS 5 /* Number of module rows (banks) */ +#define SPD_MODULE_DATA_WIDTH_LSB 6 /* Module data width (LSB) */ +#define SPD_MODULE_DATA_WIDTH_MSB 7 /* Module data width (MSB) */ +#define SPD_MODULE_VOLTAGE 8 /* Module interface signal levels */ +#define SPD_MIN_CYCLE_TIME_AT_CAS_MAX 9 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ +#define SPD_ACCESS_TIME_FROM_CLOCK 10 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ +#define SPD_DIMM_CONFIG_TYPE 11 /* Module configuration type */ +#define SPD_REFRESH 12 /* Refresh rate/type */ +#define SPD_PRIMARY_SDRAM_WIDTH 13 /* SDRAM width (primary SDRAM) */ +#define SPD_ERROR_CHECKING_SDRAM_WIDTH 14 /* Error checking SDRAM (data) width */ #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15 /* SDRAM device attributes, minimum clock delay for back to back random column */ -#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ -#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ -#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ -#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ -#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ -#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ -#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ -#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ -#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ -#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ -#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ -#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ -#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ -#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ +#define SPD_SUPPORTED_BURST_LENGTHS 16 /* SDRAM device attributes, burst lengths supported */ +#define SPD_NUM_BANKS_PER_SDRAM 17 /* SDRAM device attributes, number of banks on SDRAM device */ +#define SPD_ACCEPTABLE_CAS_LATENCIES 18 /* SDRAM device attributes, CAS latency */ +#define SPD_CS_LATENCY 19 /* SDRAM device attributes, CS latency */ +#define SPD_WE_LATENCY 20 /* SDRAM device attributes, WE latency */ +#define SPD_MODULE_ATTRIBUTES 21 /* SDRAM module attributes */ +#define SPD_DEVICE_ATTRIBUTES_GENERAL 22 /* SDRAM device attributes, general */ +#define SPD_SDRAM_CYCLE_TIME_2ND 23 /* SDRAM cycle time (2nd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_2ND 24 /* SDRAM access from clock (2nd highest CAS latency) */ +#define SPD_SDRAM_CYCLE_TIME_3RD 25 /* SDRAM cycle time (3rd highest CAS latency) */ +#define SPD_ACCESS_TIME_FROM_CLOCK_3RD 26 /* SDRAM access from clock (3rd highest CAS latency) */ +#define SPD_MIN_ROW_PRECHARGE_TIME 27 /* Minimum row precharge time (Trp) */ +#define SPD_MIN_ROWACTIVE_TO_ROWACTIVE 28 /* Minimum row active to row active (Trrd) */ +#define SPD_MIN_RAS_TO_CAS_DELAY 29 /* Minimum RAS to CAS delay (Trcd) */ #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY 30 /* Minimum RAS pulse width (Tras) */ #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE 31 /* Density of each row on module */ -#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ -#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ +#define SPD_CMD_SIGNAL_INPUT_SETUP_TIME 32 /* Command and address signal input setup time */ +#define SPD_CMD_SIGNAL_INPUT_HOLD_TIME 33 /* Command and address signal input hold time */ #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME 34 /* Data signal input setup time */ -#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ -#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ -#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ -#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ -#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ -#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ -#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ -#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ -#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ -#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ -#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ -#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ -#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ -#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ -#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ -#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ -#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ -#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ -#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ -#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ -#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ -#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ -#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ +#define SPD_DATA_SIGNAL_INPUT_HOLD_TIME 35 /* Data signal input hold time */ +#define SPD_WRITE_RECOVERY_TIME 36 /* Write recovery time (tWR) */ +#define SPD_INT_WRITE_TO_READ_DELAY 37 /* Internal write to read command delay (tWTR) */ +#define SPD_INT_READ_TO_PRECHARGE_DELAY 38 /* Internal read to precharge command delay (tRTP) */ +#define SPD_MEM_ANALYSIS_PROBE_PARAMS 39 /* Memory analysis probe characteristics */ +#define SPD_BYTE_41_42_EXTENSION 40 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */ +#define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH 41 /* Minimum active to active auto refresh (tRCmin) */ +#define SPD_MIN_AUTO_REFRESH_TO_ACT 42 /* Minimum auto refresh to active/auto refresh (tRFC) */ +#define SPD_MAX_DEVICE_CYCLE_TIME 43 /* Maximum device cycle time (tCKmax) */ +#define SPD_MAX_DQS_DQ_SKEW 44 /* Maximum skew between DQS and DQ (tDQSQ) */ +#define SPD_MAX_READ_DATAHOLD_SKEW 45 /* Maximum read data-hold skew factor (tQHS) */ +#define SPD_PLL_RELOCK_TIME 46 /* PLL relock time */ +#define SPD_SPD_DATA_REVISION_CODE 62 /* SPD data revision code */ +#define SPD_CHECKSUM_FOR_BYTES_0_TO_62 63 /* Checksum for bytes 0-62 */ +#define SPD_MANUFACTURER_JEDEC_ID_CODE 64 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */ +#define SPD_MANUFACTURING_LOCATION 72 /* Manufacturing location */ +#define SPD_MANUFACTURER_PART_NUMBER 73 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */ +#define SPD_REVISION_CODE 91 /* Revision code (bytes 91-92) */ +#define SPD_MANUFACTURING_DATE 93 /* Manufacturing date (byte 93: year, byte 94: week) */ +#define SPD_ASSEMBLY_SERIAL_NUMBER 95 /* Assembly serial number (bytes 95-98) */ +#define SPD_MANUFACTURER_SPECIFIC_DATA 99 /* Manufacturer specific data (bytes 99-125) */ +#define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ +#define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */
/* DRAM specifications use the following naming conventions for SPD locations */ -#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME -#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE -#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY -#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY -#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE -#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME +#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME +#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE +#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY +#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY +#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE +#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME #define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ #define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
@@ -124,26 +124,26 @@ enum spd_memory_type { };
/* SPD_MODULE_VOLTAGE values. */ -#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ -#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ -#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */ -#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */ -#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */ +#define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */ +#define SPD_VOLTAGE_LVTTL 1 /* LVTTL */ +#define SPD_VOLTAGE_HSTL 2 /* HSTL 1.5 */ +#define SPD_VOLTAGE_SSTL3 3 /* SSTL 3.3 */ +#define SPD_VOLTAGE_SSTL2 4 /* SSTL 2.5 */
/* SPD_DIMM_CONFIG_TYPE values. */ -#define ERROR_SCHEME_NONE 0 -#define ERROR_SCHEME_PARITY 1 -#define ERROR_SCHEME_ECC 2 +#define ERROR_SCHEME_NONE 0 +#define ERROR_SCHEME_PARITY 1 +#define ERROR_SCHEME_ECC 2
/* SPD_ACCEPTABLE_CAS_LATENCIES values. */ // TODO: Check values. -#define SPD_CAS_LATENCY_1_0 0x01 -#define SPD_CAS_LATENCY_1_5 0x02 -#define SPD_CAS_LATENCY_2_0 0x04 -#define SPD_CAS_LATENCY_2_5 0x08 -#define SPD_CAS_LATENCY_3_0 0x10 -#define SPD_CAS_LATENCY_3_5 0x20 -#define SPD_CAS_LATENCY_4_0 0x40 +#define SPD_CAS_LATENCY_1_0 0x01 +#define SPD_CAS_LATENCY_1_5 0x02 +#define SPD_CAS_LATENCY_2_0 0x04 +#define SPD_CAS_LATENCY_2_5 0x08 +#define SPD_CAS_LATENCY_3_0 0x10 +#define SPD_CAS_LATENCY_3_5 0x20 +#define SPD_CAS_LATENCY_4_0 0x40
#define SPD_CAS_LATENCY_DDR2_3 (1 << 3) #define SPD_CAS_LATENCY_DDR2_4 (1 << 4) @@ -151,25 +151,25 @@ enum spd_memory_type { #define SPD_CAS_LATENCY_DDR2_6 (1 << 6)
/* SPD_SUPPORTED_BURST_LENGTHS values. */ -#define SPD_BURST_LENGTH_1 1 -#define SPD_BURST_LENGTH_2 2 -#define SPD_BURST_LENGTH_4 4 -#define SPD_BURST_LENGTH_8 8 -#define SPD_BURST_LENGTH_PAGE (1 << 7) +#define SPD_BURST_LENGTH_1 1 +#define SPD_BURST_LENGTH_2 2 +#define SPD_BURST_LENGTH_4 4 +#define SPD_BURST_LENGTH_8 8 +#define SPD_BURST_LENGTH_PAGE (1 << 7)
/* SPD_MODULE_ATTRIBUTES values. */ -#define MODULE_BUFFERED 1 -#define MODULE_REGISTERED 2 +#define MODULE_BUFFERED 1 +#define MODULE_REGISTERED 2
/* DIMM SPD addresses */ -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57
#define RC00 0 #define RC01 1 diff --git a/src/include/stdlib.h b/src/include/stdlib.h index cb5a6ca7..aaf5070 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -5,10 +5,10 @@
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) -#define ALIGN_UP(x,a) ALIGN((x),(a)) -#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define ALIGN_UP(x,a) ALIGN((x),(a)) +#define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL))
#define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) diff --git a/src/include/string.h b/src/include/string.h index 77985e1..7f0f49c 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -144,15 +144,15 @@ static inline int islower(int c)
static inline int toupper(int c) { - if (islower(c)) - c -= 'a'-'A'; - return c; + if (islower(c)) + c -= 'a'-'A'; + return c; }
static inline int tolower(int c) { - if (isupper(c)) - c -= 'A'-'a'; - return c; + if (isupper(c)) + c -= 'A'-'a'; + return c; } #endif /* STRING_H */ diff --git a/src/include/thread.h b/src/include/thread.h index 0522337..4e231de 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -46,7 +46,7 @@ int thread_run(void (*func)(void *), void *arg); * transitions from occurring in the (state, seq) pair of the boot state * machine. */ int thread_run_until(void (*func)(void *), void *arg, - boot_state_t state, boot_state_sequence_t seq); + boot_state_t state, boot_state_sequence_t seq); /* Return 0 on successful yield for the given amount of time, < 0 when thread * did not yield. */ int thread_yield_microseconds(unsigned microsecs); @@ -69,7 +69,7 @@ void asmlinkage switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack); * will enter the thread_entry() function with arg as a parameter. The * saved_stack field in the struct thread needs to be updated accordingly. */ void arch_prepare_thread(struct thread *t, - void asmlinkage (*thread_entry)(void *), void *arg); + void asmlinkage (*thread_entry)(void *), void *arg); #else static inline void threads_initialize(void) {} static inline int thread_run(void (*func)(void *), void *arg) { return -1; } diff --git a/src/include/timer.h b/src/include/timer.h index 06128ce..36fa17f 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -80,7 +80,7 @@ static inline void mono_time_add_msecs(struct mono_time *mt, long ms) }
static inline void mono_time_add_rela_time(struct mono_time *mt, - const struct rela_time *t) + const struct rela_time *t) { mono_time_add_usecs(mt, t->microseconds); } @@ -88,7 +88,7 @@ static inline void mono_time_add_rela_time(struct mono_time *mt, /* Compare two absolute times: Return -1, 0, or 1 if t1 is <, =, or > t2, * respectively. */ static inline int mono_time_cmp(const struct mono_time *t1, - const struct mono_time *t2) + const struct mono_time *t2) { if (t1->microseconds == t2->microseconds) return 0; @@ -100,7 +100,7 @@ static inline int mono_time_cmp(const struct mono_time *t1, }
static inline int rela_time_cmp(const struct rela_time *t1, - const struct rela_time *t2) + const struct rela_time *t2) { if (t1->microseconds == t2->microseconds) return 0; @@ -121,21 +121,21 @@ static inline struct rela_time rela_time_init_usecs(long us)
/* Return time difference between t1 and t2. i.e. t2 - t1. */ static struct rela_time mono_time_diff(const struct mono_time *t1, - const struct mono_time *t2) + const struct mono_time *t2) { return rela_time_init_usecs(t2->microseconds - t1->microseconds); }
/* Return true if t1 after t2 */ static inline int mono_time_after(const struct mono_time *t1, - const struct mono_time *t2) + const struct mono_time *t2) { return mono_time_cmp(t1, t2) > 0; }
/* Return true if t1 before t2. */ static inline int mono_time_before(const struct mono_time *t1, - const struct mono_time *t2) + const struct mono_time *t2) { return mono_time_cmp(t1, t2) < 0; } @@ -156,7 +156,7 @@ static inline long rela_time_in_microseconds(const struct rela_time *rt) }
static inline long mono_time_diff_microseconds(const struct mono_time *t1, - const struct mono_time *t2) + const struct mono_time *t2) { struct rela_time rt; rt = mono_time_diff(t1, t2); diff --git a/src/include/trace.h b/src/include/trace.h index 79d35c9..c4a05bd 100644 --- a/src/include/trace.h +++ b/src/include/trace.h @@ -40,7 +40,7 @@ void __cyg_profile_func_exit( void *, void * ) extern volatile int trace_dis;
#define DISABLE_TRACE do { trace_dis = 1; } while (0); -#define ENABLE_TRACE do { trace_dis = 0; } while (0); +#define ENABLE_TRACE do { trace_dis = 0; } while (0); #define DISABLE_TRACE_ON_FUNCTION __attribute__ ((no_instrument_function));
#else /* !CONFIG_TRACE */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index e6a318a..e7337af 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -28,54 +28,54 @@
/* Control */ #define UART_IER 0x01 -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
#define UART_IIR 0x02 -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
#define UART_FCR 0x02 -#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ - -#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
#define UART_LCR 0x03 -#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ -#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ -#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ -#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity enable */ -#define UART_LCR_EPS 0x10 /* Even Parity Select */ -#define UART_LCR_STKP 0x20 /* Stick Parity */ -#define UART_LCR_SBRK 0x40 /* Set Break */ -#define UART_LCR_BKSE 0x80 /* Bank select enable */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity enable */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
#define UART_MCR 0x04 -#define UART_MCR_DTR 0x01 /* DTR */ -#define UART_MCR_RTS 0x02 /* RTS */ -#define UART_MCR_OUT1 0x04 /* Out 1 */ -#define UART_MCR_OUT2 0x08 /* Out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_DMA_EN 0x04 #define UART_MCR_TX_DFR 0x08 @@ -85,24 +85,24 @@
/* Status */ #define UART_LSR 0x05 -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_OE 0x02 /* Overrun */ -#define UART_LSR_PE 0x04 /* Parity error */ -#define UART_LSR_FE 0x08 /* Framing error */ -#define UART_LSR_BI 0x10 /* Break */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART_LSR_ERR 0x80 /* Error */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */
#define UART_MSR 0x06 -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */
#define UART_SCR 0x07 #define UART_SPR 0x07 diff --git a/src/include/usb_ch9.h b/src/include/usb_ch9.h index b0aa773..6254f6f8 100644 --- a/src/include/usb_ch9.h +++ b/src/include/usb_ch9.h @@ -21,28 +21,28 @@ #ifndef USB_CH9_H #define USB_CH9_H
-#define USB_DIR_OUT 0 /* to device */ -#define USB_DIR_IN 0x80 /* to host */ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */
/* * USB types, the second of three bRequestType fields */ -#define USB_TYPE_MASK (0x03 << 5) -#define USB_TYPE_STANDARD (0x00 << 5) -#define USB_TYPE_CLASS (0x01 << 5) -#define USB_TYPE_VENDOR (0x02 << 5) -#define USB_TYPE_RESERVED (0x03 << 5) +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) /* * USB recipients, the third of three bRequestType fields */ -#define USB_RECIP_MASK 0x1f -#define USB_RECIP_DEVICE 0x00 -#define USB_RECIP_INTERFACE 0x01 -#define USB_RECIP_ENDPOINT 0x02 -#define USB_RECIP_OTHER 0x03 +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 /* From Wireless USB 1.0 */ -#define USB_RECIP_PORT 0x04 -#define USB_RECIP_RPIPE 0x05 +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05
/* * Standard requests, for the bRequest field of a SETUP packet. @@ -51,51 +51,51 @@ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved * by a GET_STATUS request. */ -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C
-#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ -#define USB_REQ_GET_ENCRYPTION 0x0E -#define USB_REQ_RPIPE_ABORT 0x0E -#define USB_REQ_SET_HANDSHAKE 0x0F -#define USB_REQ_RPIPE_RESET 0x0F -#define USB_REQ_GET_HANDSHAKE 0x10 -#define USB_REQ_SET_CONNECTION 0x11 -#define USB_REQ_SET_SECURITY_DATA 0x12 -#define USB_REQ_GET_SECURITY_DATA 0x13 -#define USB_REQ_SET_WUSB_DATA 0x14 -#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 -#define USB_REQ_LOOPBACK_DATA_READ 0x16 -#define USB_REQ_SET_INTERFACE_DS 0x17 +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17
-#define USB_DT_DEBUG 0x0a +#define USB_DT_DEBUG 0x0a
-#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
struct usb_ctrlrequest { - u8 bRequestType; - u8 bRequest; - u16 wValue; - u16 wIndex; - u16 wLength; + u8 bRequestType; + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; } __attribute__ ((packed));
struct usb_debug_descriptor { - u8 bLength; - u8 bDescriptorType; + u8 bLength; + u8 bDescriptorType;
- /* bulk endpoints with 8 byte maxpacket */ - u8 bDebugInEndpoint; - u8 bDebugOutEndpoint; + /* bulk endpoints with 8 byte maxpacket */ + u8 bDebugInEndpoint; + u8 bDebugOutEndpoint; };
#endif diff --git a/src/include/vbe.h b/src/include/vbe.h index 8ad9d2e..2bc78c0 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -49,20 +49,20 @@ typedef struct { u8 win_a_attributes; // 02 u8 win_b_attributes; // 03 u16 win_granularity; // 04 - u16 win_size; // 06 + u16 win_size; // 06 u16 win_a_segment; // 08 u16 win_b_segment; // 0a u32 win_func_ptr; // 0c u16 bytes_per_scanline; // 10 u16 x_resolution; // 12 u16 y_resolution; // 14 - u8 x_charsize; // 16 - u8 y_charsize; // 17 + u8 x_charsize; // 16 + u8 y_charsize; // 17 u8 number_of_planes; // 18 u8 bits_per_pixel; // 19 u8 number_of_banks; // 20 u8 memory_model; // 21 - u8 bank_size; // 22 + u8 bank_size; // 22 u8 number_of_image_pages; // 23 u8 reserved_page; u8 red_mask_size; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 23e1600..5f0ca67 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -115,9 +115,9 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return src;
if (!cbfs_decompress(ntohl(orom->compression), - src, - dest, - ntohl(orom->len))) + src, + dest, + ntohl(orom->len))) return NULL;
return dest; @@ -131,7 +131,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, * for the romstage, the rmodule loader is used. */ void __attribute__((weak)) cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point) + const struct cbmem_entry *ramstage, void *entry_point) { uint32_t ramstage_size; const struct cbmem_entry *entry; @@ -150,12 +150,12 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, handoff->ramstage_entry_point = (uint32_t)entry_point;
memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage), - ramstage_size); + ramstage_size); }
void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) + const struct cbmem_entry *ramstage) { const struct cbmem_entry *entry_cache;
@@ -169,13 +169,13 @@ load_cached_ramstage(struct romstage_handoff *handoff,
/* Load the cached ramstage copy into the to-be-run region. */ memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache), - cbmem_entry_size(ramstage)); + cbmem_entry_size(ramstage));
return (void *)handoff->ramstage_entry_point; }
static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) + struct romstage_handoff *handoff) { struct cbfs_stage *stage; struct rmodule ramstage; @@ -194,7 +194,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name,
rmodule_offset = rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, - stage->memlen, ®ion_size, &load_offset); + stage->memlen, ®ion_size, &load_offset);
ramstage_entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE, region_size);
@@ -207,7 +207,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, name, &ramstage_region[rmodule_offset], stage->memlen);
if (!cbfs_decompress(stage->compression, &stage[1], - &ramstage_region[rmodule_offset], stage->len)) + &ramstage_region[rmodule_offset], stage->len)) return (void *) -1;
if (rmodule_parse(&ramstage_region[rmodule_offset], &ramstage)) @@ -272,16 +272,16 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) stage->entry);
final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); + ((unsigned char *) stage) + + sizeof(struct cbfs_stage), + (void *) (uint32_t) stage->load, + stage->len); if (!final_size) return (void *) -1;
/* Stages rely the below clearing so that the bss is initialized. */ memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); + stage->memlen - final_size);
DEBUG("stage loaded.\n");
@@ -310,8 +310,8 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) /* Simple buffer */
void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { + struct cbfs_media *media, + size_t offset, size_t count) { void *address = buffer->buffer + buffer->allocated;; DEBUG("simple_buffer_map(offset=%zd, count=%zd): " "allocated=%zd, size=%zd, last_allocate=%zd\n", @@ -321,7 +321,7 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, return CBFS_MEDIA_INVALID_MAP_ADDRESS; if (media->read(media, address, offset, count) != count) { ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", - count, offset); + count, offset); return CBFS_MEDIA_INVALID_MAP_ADDRESS; } buffer->allocated += count; @@ -330,7 +330,7 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, }
void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { + const void *address) { // TODO Add simple buffer management so we can free more than last // allocated one. DEBUG("simple_buffer_unmap(address=0x%p): " diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 612fef2..ce8df3d 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -32,20 +32,20 @@ * target environment: * * CBFS_CORE_WITH_LZMA (must be #define) - * if defined, ulzma() must exist for decompression of data streams + * if defined, ulzma() must exist for decompression of data streams * * CBFS_HEADER_ROM_ADDRESS * ROM address (offset) of CBFS header. Underlying CBFS media may interpret * it in other way so we call this "address". * * ERROR(x...) - * print an error message x (in printf format) + * print an error message x (in printf format) * * LOG(x...) - * print a message x (in printf format) + * print a message x (in printf format) * * DEBUG(x...) - * print a debug message x (in printf format) + * print a debug message x (in printf format) * */
@@ -75,14 +75,14 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media)
if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { ERROR("Failed to load CBFS header from 0x%x\n", - CBFS_HEADER_ROM_ADDRESS); + CBFS_HEADER_ROM_ADDRESS); return CBFS_HEADER_INVALID_ADDRESS; }
if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { ERROR("Could not find valid CBFS master header at %x: " - "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, - ntohl(header->magic)); + "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, + ntohl(header->magic)); if (header->magic == 0xffffffff) { ERROR("Maybe ROM is not mapped properly?\n"); } @@ -126,21 +126,21 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { + media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { if (memcmp(CBFS_FILE_MAGIC, file.magic, sizeof(file.magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); + "try next aligned address: 0x%x.\n", offset, + offset + new_align); offset += new_align; continue; } name_len = ntohl(file.offset) - sizeof(file); DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); + name_len);
// load file name (arbitrary length). file_name = (const char *)media->map( @@ -154,12 +154,12 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) offset + file_offset, file_len); media->unmap(media, file_name); file_ptr = media->map(media, offset, - file_offset + file_len); + file_offset + file_len); media->close(media); return file_ptr; } else { DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); + file_name); media->unmap(media, file_name); }
@@ -184,7 +184,7 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type
if (ntohl(file->type) != type) { ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); + ntohl(file->type), type); return NULL; }
@@ -203,8 +203,8 @@ int cbfs_decompress(int algo, void *src, void *dst, int len) #endif default: ERROR("tried to decompress %d bytes with algorithm #%x," - "but that algorithm id is unsupported.\n", len, - algo); + "but that algorithm id is unsupported.\n", len, + algo); return 0; } } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6449b55..bed6bc5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -150,8 +150,8 @@ void *cbmem_add(u32 id, u64 size) p = cbmem_find(id); if (p) { printk(BIOS_NOTICE, - "CBMEM section %x: using existing location at %p.\n", - id, p); + "CBMEM section %x: using existing location at %p.\n", + id, p); return p; }
@@ -257,7 +257,7 @@ static void init_cbmem_post_device(void *unused)
BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), + init_cbmem_post_device, NULL), };
int cbmem_base_check(void) @@ -290,7 +290,7 @@ void cbmem_list(void) if (cbmem_toc[i].magic != CBMEM_MAGIC) continue; cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, - cbmem_toc[i].size); + cbmem_toc[i].size); } } #endif diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index dd88300..9438ec5 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -126,7 +126,7 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) old_cons_p->buffer_size : old_cons_p->buffer_cursor;
memcpy(new_cons_p->buffer_body + cursor, old_cons_p->buffer_body, - copy_size); + copy_size);
cursor += copy_size;
diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index a60761f..db5b4a1 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -25,19 +25,19 @@ static struct cbmem_id_to_name { const char *name; } cbmem_ids[] = { { CBMEM_ID_FREESPACE, "FREE SPACE " }, - { CBMEM_ID_GDT, "GDT " }, + { CBMEM_ID_GDT, "GDT " }, { CBMEM_ID_ACPI, "ACPI " }, - { CBMEM_ID_CBTABLE, "COREBOOT " }, + { CBMEM_ID_CBTABLE, "COREBOOT " }, { CBMEM_ID_PIRQ, "IRQ TABLE " }, { CBMEM_ID_MPTABLE, "SMP TABLE " }, { CBMEM_ID_RESUME, "ACPI RESUME" }, { CBMEM_ID_RESUME_SCRATCH, "ACPISCRATCH" }, { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, { CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, - { CBMEM_ID_SMBIOS, "SMBIOS " }, + { CBMEM_ID_SMBIOS, "SMBIOS " }, { CBMEM_ID_TIMESTAMP, "TIME STAMP " }, - { CBMEM_ID_MRCDATA, "MRC DATA " }, - { CBMEM_ID_CONSOLE, "CONSOLE " }, + { CBMEM_ID_MRCDATA, "MRC DATA " }, + { CBMEM_ID_CONSOLE, "CONSOLE " }, { CBMEM_ID_ELOG, "ELOG " }, { CBMEM_ID_COVERAGE, "COVERAGE " }, { CBMEM_ID_ROMSTAGE_INFO, "ROMSTAGE " }, diff --git a/src/lib/clog2.c b/src/lib/clog2.c index c6fe6f6..15db307 100644 --- a/src/lib/clog2.c +++ b/src/lib/clog2.c @@ -11,19 +11,19 @@
unsigned long log2(unsigned long x) { - // assume 8 bits per byte. - unsigned long i = 1ULL << (sizeof(x)* CHAR_BIT - 1ULL); - unsigned long pow = sizeof(x) * CHAR_BIT - 1ULL; + // assume 8 bits per byte. + unsigned long i = 1ULL << (sizeof(x)* CHAR_BIT - 1ULL); + unsigned long pow = sizeof(x) * CHAR_BIT - 1ULL;
- if (! x) { + if (! x) { #ifdef DEBUG_LOG2 - printk(BIOS_WARNING, "%s called with invalid parameter of 0\n", + printk(BIOS_WARNING, "%s called with invalid parameter of 0\n", __func__); #endif - return -1; - } - for(; i > x; i >>= 1, pow--) - ; + return -1; + } + for(; i > x; i >>= 1, pow--) + ;
- return pow; + return pow; } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index a0a806d..d2e2942 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -309,7 +309,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
memcpy(mainboard->strings + mainboard->vendor_idx, - mainboard_vendor, strlen(mainboard_vendor) + 1); + mainboard_vendor, strlen(mainboard_vendor) + 1); memcpy(mainboard->strings + mainboard->part_number_idx, mainboard_part_number, strlen(mainboard_part_number) + 1);
@@ -342,16 +342,16 @@ static void lb_strings(struct lb_header *header) uint32_t tag; const char *string; } strings[] = { - { LB_TAG_VERSION, coreboot_version, }, + { LB_TAG_VERSION, coreboot_version, }, { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, - { LB_TAG_BUILD, coreboot_build, }, + { LB_TAG_BUILD, coreboot_build, }, { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, - { LB_TAG_COMPILE_BY, coreboot_compile_by, }, + { LB_TAG_COMPILE_BY, coreboot_compile_by, }, { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, - { LB_TAG_COMPILER, coreboot_compiler, }, - { LB_TAG_LINKER, coreboot_linker, }, - { LB_TAG_ASSEMBLER, coreboot_assembler, }, + { LB_TAG_COMPILER, coreboot_compiler, }, + { LB_TAG_LINKER, coreboot_linker, }, + { LB_TAG_ASSEMBLER, coreboot_assembler, }, }; unsigned int i; for(i = 0; i < ARRAY_SIZE(strings); i++) { @@ -391,8 +391,8 @@ static unsigned long lb_table_fini(struct lb_header *head) head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); printk(BIOS_DEBUG, - "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", - head, head->table_bytes, head->table_checksum); + "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n", + head, head->table_bytes, head->table_checksum); return (unsigned long)rec + rec->size; }
@@ -423,9 +423,9 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) * that each overlapping range will take over the next. Therefore, * add cacheable resources as RAM then add the reserved resources. */ memranges_init(&lb_ranges, IORESOURCE_CACHEABLE, - IORESOURCE_CACHEABLE, LB_MEM_RAM); + IORESOURCE_CACHEABLE, LB_MEM_RAM); memranges_add_resources(&lb_ranges, IORESOURCE_RESERVE, - IORESOURCE_RESERVE, LB_MEM_RESERVED); + IORESOURCE_RESERVE, LB_MEM_RESERVED);
return mem; } diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index e21f96e..05beaf4 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -123,7 +123,7 @@ static inline void *get_root(void) }
static inline void cbmem_entry_assign(struct cbmem_entry *entry, - u32 id, u32 start, u32 size) + u32 id, u32 start, u32 size) { entry->magic = CBMEM_ENTRY_MAGIC; entry->start = start; @@ -163,7 +163,7 @@ void cbmem_initialize_empty(void) pointer_addr -= sizeof(struct cbmem_root_pointer);
max_entries = (pointer_addr - (root_addr + sizeof(*root))) / - sizeof(struct cbmem_entry); + sizeof(struct cbmem_entry);
pointer = (void *)pointer_addr; pointer->magic = CBMEM_POINTER_MAGIC; @@ -174,13 +174,13 @@ void cbmem_initialize_empty(void) root->num_entries = 0; root->locked = 0; root->size = pointer_addr - root_addr + - sizeof(struct cbmem_root_pointer); + sizeof(struct cbmem_root_pointer);
/* Add an entry covering the root region. */ cbmem_entry_append(root, CBMEM_ID_ROOT, root_addr, root->size);
printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", - root, root->max_entries); + root, root->max_entries);
cbmem_arch_init();
@@ -205,7 +205,7 @@ static int validate_entries(struct cbmem_root *root) current_end = (u32)get_top_aligned();
printk(BIOS_DEBUG, "CBMEM: recovering %d/%d entries from root @ %p\n", - root->num_entries, root->max_entries, root); + root->num_entries, root->max_entries, root);
/* Check that all regions are properly aligned and are just below * the previous entry */ @@ -431,7 +431,7 @@ static void init_cbmem_pre_device(void *unused)
BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, - init_cbmem_pre_device, NULL), + init_cbmem_pre_device, NULL), };
void cbmem_add_lb_mem(struct lb_memory *mem) diff --git a/src/lib/edid.c b/src/lib/edid.c index d0e8b98..2f25274 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -130,17 +130,17 @@ detailed_cvt_descriptor(struct edid *out, unsigned char *x, int first) reduced = (x[2] & 0x01);
if (!valid) { - printk(BIOS_SPEW, " (broken)\n"); + printk(BIOS_SPEW, " (broken)\n"); } else { - printk(BIOS_SPEW, " %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n", - width, height, - fifty ? "50 " : "", - sixty ? "60 " : "", - seventyfive ? "75 " : "", - eightyfive ? "85 " : "", - reduced ? "60RB " : "", - names[(x[2] & 0x60) >> 5], - (((x[2] & 0x60) == 0x20) && reduced) ? "RB" : ""); + printk(BIOS_SPEW, " %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n", + width, height, + fifty ? "50 " : "", + sixty ? "60 " : "", + seventyfive ? "75 " : "", + eightyfive ? "85 " : "", + reduced ? "60RB " : "", + names[(x[2] & 0x60) >> 5], + (((x[2] & 0x60) == 0x20) && reduced) ? "RB" : ""); }
return valid; @@ -205,13 +205,13 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) if (x[2] != 0) { /* 1.3, 3.10.3 */ printk(BIOS_SPEW, "Monitor descriptor block has byte 2 nonzero (0x%02x)\n", - x[2]); + x[2]); has_valid_descriptor_pad = 0; } if (x[3] != 0xfd && x[4] != 0x00) { /* 1.3, 3.10.3 */ printk(BIOS_SPEW, "Monitor descriptor block has byte 4 nonzero (0x%02x)\n", - x[4]); + x[4]); has_valid_descriptor_pad = 0; }
@@ -273,8 +273,8 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) name_descriptor_terminated = 1; /* later. printk(BIOS_SPEW, "Monitor name: %s\n", - extract_string(name, &has_valid_string_termination, - strlen((char *)name))); + extract_string(name, &has_valid_string_termination, + strlen((char *)name))); */ } return 0; @@ -338,9 +338,9 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) if (x[7] + h_min_offset > x[8] + h_max_offset) has_valid_range_descriptor = 0; printk(BIOS_SPEW, "Monitor ranges (%s): %d-%dHz V, %d-%dkHz H", - out->range_class, - x[5] + v_min_offset, x[6] + v_max_offset, - x[7] + h_min_offset, x[8] + h_max_offset); + out->range_class, + x[5] + v_min_offset, x[6] + v_max_offset, + x[7] + h_min_offset, x[8] + h_max_offset); if (x[9]) printk(BIOS_SPEW, ", max dotclock %dMHz\n", x[9] * 10); else { @@ -357,7 +357,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) if (x[12] & 0xfc) { int raw_offset = (x[12] & 0xfc) >> 2; printk(BIOS_SPEW, "Real max dotclock: %.2fMHz\n", - (x[9] * 10) - (raw_offset * 0.25)); + (x[9] * 10) - (raw_offset * 0.25)); if (raw_offset >= 40) warning_excessive_dotclock_correction = 1; } @@ -370,11 +370,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) printk(BIOS_SPEW, "Max active pixels per line: %d\n", max_h_pixels);
printk(BIOS_SPEW, "Supported aspect ratios: %s %s %s %s %s\n", - x[14] & 0x80 ? "4:3" : "", - x[14] & 0x40 ? "16:9" : "", - x[14] & 0x20 ? "16:10" : "", - x[14] & 0x10 ? "5:4" : "", - x[14] & 0x08 ? "15:9" : ""); + x[14] & 0x80 ? "4:3" : "", + x[14] & 0x40 ? "16:9" : "", + x[14] & 0x20 ? "16:10" : "", + x[14] & 0x10 ? "5:4" : "", + x[14] & 0x08 ? "15:9" : ""); if (x[14] & 0x07) has_valid_range_descriptor = 0;
@@ -430,11 +430,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) * seems to be specified by SPWG: http://www.spwg.org/ */ printk(BIOS_SPEW, "ASCII string: %s\n", - extract_string(x + 5, &has_valid_string_termination, 13)); + extract_string(x + 5, &has_valid_string_termination, 13)); return 0; case 0xFF: printk(BIOS_SPEW, "Serial number: %s\n", - extract_string(x + 5, &has_valid_string_termination, 13)); + extract_string(x + 5, &has_valid_string_termination, 13)); return 0; default: printk(BIOS_SPEW, "Unknown monitor description type %d\n", x[3]); @@ -501,19 +501,19 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension) }
printk(BIOS_SPEW, "Detailed mode (IN HEX): Clock %d0 KHz, %x mm x %x mm\n" - " %04x %04x %04x %04x hborder %x\n" - " %04x %04x %04x %04x vborder %x\n" - " %chsync %cvsync%s%s %s\n", - (x[0] + (x[1] << 8)), - (x[12] + ((x[14] & 0xF0) << 4)), - (x[13] + ((x[14] & 0x0F) << 8)), - out->ha, out->ha + out->hso, out->ha + out->hso + out->hspw, - out->ha + out->hbl, out->hborder, - out->va, out->va + out->vso, out->va + out->vso + out->vspw, - out->va + out->vbl, out->vborder, - out->phsync, out->pvsync, - out->syncmethod, x[17] & 0x80 ?" interlaced" : "", - out->stereo + " %04x %04x %04x %04x hborder %x\n" + " %04x %04x %04x %04x vborder %x\n" + " %chsync %cvsync%s%s %s\n", + (x[0] + (x[1] << 8)), + (x[12] + ((x[14] & 0xF0) << 4)), + (x[13] + ((x[14] & 0x0F) << 8)), + out->ha, out->ha + out->hso, out->ha + out->hso + out->hspw, + out->ha + out->hbl, out->hborder, + out->va, out->va + out->vso, out->va + out->vso + out->vspw, + out->va + out->vbl, out->vborder, + out->phsync, out->pvsync, + out->syncmethod, x[17] & 0x80 ?" interlaced" : "", + out->stereo ); return 1; } @@ -579,23 +579,23 @@ cea_audio_block(unsigned char *x)
for (i = 1; i < length; i += 3) { format = (x[i] & 0x78) >> 3; - printk(BIOS_SPEW, " %s, max channels %d\n", audio_format(format), - x[i] & 0x07); - printk(BIOS_SPEW, " Supported sample rates (kHz):%s%s%s%s%s%s%s\n", - (x[i+1] & 0x40) ? " 192" : "", - (x[i+1] & 0x20) ? " 176.4" : "", - (x[i+1] & 0x10) ? " 96" : "", - (x[i+1] & 0x08) ? " 88.2" : "", - (x[i+1] & 0x04) ? " 48" : "", - (x[i+1] & 0x02) ? " 44.1" : "", - (x[i+1] & 0x01) ? " 32" : ""); + printk(BIOS_SPEW, " %s, max channels %d\n", audio_format(format), + x[i] & 0x07); + printk(BIOS_SPEW, " Supported sample rates (kHz):%s%s%s%s%s%s%s\n", + (x[i+1] & 0x40) ? " 192" : "", + (x[i+1] & 0x20) ? " 176.4" : "", + (x[i+1] & 0x10) ? " 96" : "", + (x[i+1] & 0x08) ? " 88.2" : "", + (x[i+1] & 0x04) ? " 48" : "", + (x[i+1] & 0x02) ? " 44.1" : "", + (x[i+1] & 0x01) ? " 32" : ""); if (format == 1) { - printk(BIOS_SPEW, " Supported sample sizes (bits):%s%s%s\n", - (x[2] & 0x04) ? " 24" : "", - (x[2] & 0x02) ? " 20" : "", - (x[2] & 0x01) ? " 16" : ""); + printk(BIOS_SPEW, " Supported sample sizes (bits):%s%s%s\n", + (x[2] & 0x04) ? " 24" : "", + (x[2] & 0x02) ? " 20" : "", + (x[2] & 0x01) ? " 16" : ""); } else if (format <= 8) { - printk(BIOS_SPEW, " Maximum bit rate: %d kHz\n", x[2] * 8); + printk(BIOS_SPEW, " Maximum bit rate: %d kHz\n", x[2] * 8); } } } @@ -607,8 +607,8 @@ cea_video_block(unsigned char *x) int length = x[0] & 0x1f;
for (i = 1; i < length; i++) - printk(BIOS_SPEW," VIC %02d %s\n", x[i] & 0x7f, - x[i] & 0x80 ? "(native)" : ""); + printk(BIOS_SPEW," VIC %02d %s\n", x[i] & 0x7f, + x[i] & 0x80 ? "(native)" : ""); }
static void @@ -618,69 +618,69 @@ cea_hdmi_block(struct edid *out, unsigned char *x)
printk(BIOS_SPEW, " (HDMI)\n"); printk(BIOS_SPEW, - " Source physical address %d.%d.%d.%d\n", - x[4] >> 4, x[4] & 0x0f, x[5] >> 4, x[5] & 0x0f); + " Source physical address %d.%d.%d.%d\n", + x[4] >> 4, x[4] & 0x0f, x[5] >> 4, x[5] & 0x0f);
if (length > 5) { if (x[6] & 0x80) - printk(BIOS_SPEW, " Supports_AI\n"); + printk(BIOS_SPEW, " Supports_AI\n"); if (x[6] & 0x40) - printk(BIOS_SPEW, " DC_48bit\n"); + printk(BIOS_SPEW, " DC_48bit\n"); if (x[6] & 0x20) - printk(BIOS_SPEW, " DC_36bit\n"); + printk(BIOS_SPEW, " DC_36bit\n"); if (x[6] & 0x10) - printk(BIOS_SPEW, " DC_30bit\n"); + printk(BIOS_SPEW, " DC_30bit\n"); if (x[6] & 0x08) - printk(BIOS_SPEW, " DC_Y444\n"); + printk(BIOS_SPEW, " DC_Y444\n"); /* two reserved */ if (x[6] & 0x01) - printk(BIOS_SPEW, " DVI_Dual\n"); + printk(BIOS_SPEW, " DVI_Dual\n"); }
if (length > 6) - printk(BIOS_SPEW, " Maximum TMDS clock: %dMHz\n", x[7] * 5); + printk(BIOS_SPEW, " Maximum TMDS clock: %dMHz\n", x[7] * 5);
/* XXX the walk here is really ugly, and needs to be length-checked */ if (length > 7) { int b = 0;
if (x[8] & 0x80) { - printk(BIOS_SPEW, " Video latency: %d\n", x[9 + b]); - printk(BIOS_SPEW, " Audio latency: %d\n", x[10 + b]); + printk(BIOS_SPEW, " Video latency: %d\n", x[9 + b]); + printk(BIOS_SPEW, " Audio latency: %d\n", x[10 + b]); b += 2; }
if (x[8] & 0x40) { - printk(BIOS_SPEW, " Interlaced video latency: %d\n", x[9 + b]); - printk(BIOS_SPEW, " Interlaced audio latency: %d\n", x[10 + b]); + printk(BIOS_SPEW, " Interlaced video latency: %d\n", x[9 + b]); + printk(BIOS_SPEW, " Interlaced audio latency: %d\n", x[10 + b]); b += 2; }
if (x[8] & 0x20) { int mask = 0, formats = 0; int len_xx, len_3d; - printk(BIOS_SPEW, " Extended HDMI video details:\n"); + printk(BIOS_SPEW, " Extended HDMI video details:\n"); if (x[9 + b] & 0x80) - printk(BIOS_SPEW, " 3D present\n"); + printk(BIOS_SPEW, " 3D present\n"); if ((x[9 + b] & 0x60) == 0x20) { - printk(BIOS_SPEW, " All advertised VICs are 3D-capable\n"); + printk(BIOS_SPEW, " All advertised VICs are 3D-capable\n"); formats = 1; } if ((x[9 + b] & 0x60) == 0x40) { - printk(BIOS_SPEW, " 3D-capable-VIC mask present\n"); + printk(BIOS_SPEW, " 3D-capable-VIC mask present\n"); formats = 1; mask = 1; } switch (x[9 + b] & 0x18) { case 0x00: break; case 0x08: - printk(BIOS_SPEW, " Base EDID image size is aspect ratio\n"); + printk(BIOS_SPEW, " Base EDID image size is aspect ratio\n"); break; case 0x10: - printk(BIOS_SPEW, " Base EDID image size is in units of 1cm\n"); + printk(BIOS_SPEW, " Base EDID image size is in units of 1cm\n"); break; case 0x18: - printk(BIOS_SPEW, " Base EDID image size is in units of 5cm\n"); + printk(BIOS_SPEW, " Base EDID image size is in units of 5cm\n"); break; } len_xx = (x[10 + b] & 0xe0) >> 5; @@ -688,8 +688,8 @@ cea_hdmi_block(struct edid *out, unsigned char *x) b += 2;
if (len_xx) { - printk(BIOS_SPEW, " Skipping %d bytes that HDMI refuses to publicly" - " document\n", len_xx); + printk(BIOS_SPEW, " Skipping %d bytes that HDMI refuses to publicly" + " document\n", len_xx); b += len_xx; }
@@ -803,7 +803,7 @@ cea_block(struct edid *out, unsigned char *x) int tag = (*x & 0xe0) >> 5; int length = *x & 0x1f; printk(BIOS_SPEW, - " Unknown tag %d, length %d (raw %02x)\n", tag, length, *x); + " Unknown tag %d, length %d (raw %02x)\n", tag, length, *x); break; } } @@ -920,7 +920,7 @@ static const struct { };
static void print_subsection(const char *name, unsigned char *edid, int start, - int end) + int end) { int i;
@@ -973,13 +973,13 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) manufacturer_name(out, edid + 0x08); out->model = (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)); out->serial = (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) - + (edid[0x0E] << 16) + (edid[0x0F] << 24)); + + (edid[0x0E] << 16) + (edid[0x0F] << 24));
printk(BIOS_SPEW, "Manufacturer: %s Model %x Serial Number %u\n", - out->manuf_name, - (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)), - (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) - + (edid[0x0E] << 16) + (edid[0x0F] << 24))); + out->manuf_name, + (unsigned short)(edid[0x0A] + (edid[0x0B] << 8)), + (unsigned int)(edid[0x0C] + (edid[0x0D] << 8) + + (edid[0x0E] << 16) + (edid[0x0F] << 24))); /* XXX need manufacturer ID table */
if (edid[0x10] < 55 || edid[0x10] == 0xff) { @@ -988,7 +988,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (edid[0x10] == 0xff) { has_valid_year = 1; printk(BIOS_SPEW, "Made week %hd of model year %hd\n", edid[0x10], - edid[0x11]); + edid[0x11]); out->week = edid[0x10]; out->year = edid[0x11]; } else { @@ -996,7 +996,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (edid[0x11] + 90 <= 2013) { has_valid_year = 1; printk(BIOS_SPEW, "Made week %hd of %hd\n", - edid[0x10], edid[0x11] + 1990); + edid[0x10], edid[0x11] + 1990); out->week = edid[0x10]; out->year = edid[0x11] + 1990; } @@ -1041,7 +1041,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) nonconformant_digital_display = 1; else printk(BIOS_SPEW, "%d bits per primary color channel\n", - ((edid[0x14] & 0x70) >> 3) + 4); + ((edid[0x14] & 0x70) >> 3) + 4); out->bpp = ((edid[0x14] & 0x70) >> 3) + 4;
switch (edid[0x14] & 0x0f) { @@ -1074,10 +1074,10 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) out->sync = sync;
printk(BIOS_SPEW, "Analog display, Input voltage level: %s V\n", - voltage == 3 ? "0.7/0.7" : - voltage == 2 ? "1.0/0.4" : - voltage == 1 ? "0.714/0.286" : - "0.7/0.3"); + voltage == 3 ? "0.7/0.7" : + voltage == 2 ? "1.0/0.4" : + voltage == 1 ? "0.714/0.286" : + "0.7/0.3");
if (claims_one_point_four) { if (edid[0x14] & 0x10) @@ -1094,26 +1094,26 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) }
printk(BIOS_SPEW, "Sync: %s%s%s%s\n", sync & 0x08 ? "Separate " : "", - sync & 0x04 ? "Composite " : "", - sync & 0x02 ? "SyncOnGreen " : "", - sync & 0x01 ? "Serration " : ""); + sync & 0x04 ? "Composite " : "", + sync & 0x02 ? "SyncOnGreen " : "", + sync & 0x01 ? "Serration " : ""); }
if (edid[0x15] && edid[0x16]) { printk(BIOS_SPEW, "Maximum image size: %d cm x %d cm\n", - edid[0x15], edid[0x16]); + edid[0x15], edid[0x16]); out->xsize_cm = edid[0x15]; out->ysize_cm = edid[0x16]; } else if (claims_one_point_four && (edid[0x15] || edid[0x16])) { if (edid[0x15]) { printk(BIOS_SPEW, "Aspect ratio is %f (landscape)\n", - 100.0/(edid[0x16] + 99)); + 100.0/(edid[0x16] + 99)); /* truncated to integer %. We try to avoid floating point */ out->aspect_landscape = 10000 /(edid[0x16] + 99); } else { printk(BIOS_SPEW, "Aspect ratio is %f (portrait)\n", - 100.0/(edid[0x15] + 99)); + 100.0/(edid[0x15] + 99)); out->aspect_portrait = 10000 /(edid[0x16] + 99); } } else { @@ -1172,7 +1172,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) for (i = 0; i < 17; i++) { if (edid[0x23 + i / 8] & (1 << (7 - i % 8))) { printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x, - established_timings[i].y, established_timings[i].refresh); + established_timings[i].y, established_timings[i].refresh); } }
@@ -1255,7 +1255,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n"); if (nonconformant_digital_display) printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n", - nonconformant_digital_display); + nonconformant_digital_display); if (!has_name_descriptor) printk(BIOS_ERR, "\tMissing name descriptor\n"); else if (!name_descriptor_terminated) @@ -1276,7 +1276,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.2!\n"); if (nonconformant_digital_display) printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n", - nonconformant_digital_display); + nonconformant_digital_display); if (has_name_descriptor && !name_descriptor_terminated) printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n"); } else if (claims_one_point_oh) { @@ -1303,7 +1303,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_ERR, "EDID block does not conform at all!\n"); if (nonconformant_extension) printk(BIOS_ERR, "\tHas %d nonconformant extension block(s)\n", - nonconformant_extension); + nonconformant_extension); if (!has_valid_checksum) printk(BIOS_ERR, "\tBlock has broken checksum\n"); if (!has_valid_cvt) @@ -1330,10 +1330,10 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
if (warning_excessive_dotclock_correction) printk(BIOS_ERR, - "Warning: CVT block corrects dotclock by more than 9.75MHz\n"); + "Warning: CVT block corrects dotclock by more than 9.75MHz\n"); if (warning_zero_preferred_refresh) printk(BIOS_ERR, - "Warning: CVT block does not set preferred refresh rate\n"); + "Warning: CVT block does not set preferred refresh rate\n"); return !conformant; }
@@ -1344,30 +1344,30 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) * at offset 0x6c (fourth detailed block): (all other bits reserved) * 0x6c: 00 00 00 0e 00 * 0x71: bit 6-5: data color mapping (00 conventional/fpdi/vesa, 01 openldi) - * bit 4-3: pixels per clock (00 1, 01 2, 10 4, 11 reserved) - * bit 2-0: bits per pixel (000 18, 001 24, 010 30, else reserved) + * bit 4-3: pixels per clock (00 1, 01 2, 10 4, 11 reserved) + * bit 2-0: bits per pixel (000 18, 001 24, 010 30, else reserved) * 0x72: bit 5: FPSCLK polarity (0 normal 1 inverted) - * bit 4: DE polarity (0 high active 1 low active) - * bit 3-0: interface (0000 LVDS TFT - * 0001 mono STN 4/8bit - * 0010 color STN 8/16 bit - * 0011 18 bit tft - * 0100 24 bit tft - * 0101 tmds - * else reserved) + * bit 4: DE polarity (0 high active 1 low active) + * bit 3-0: interface (0000 LVDS TFT + * 0001 mono STN 4/8bit + * 0010 color STN 8/16 bit + * 0011 18 bit tft + * 0100 24 bit tft + * 0101 tmds + * else reserved) * 0x73: bit 1: horizontal display mode (0 normal 1 right/left reverse) - * bit 0: vertical display mode (0 normal 1 up/down reverse) + * bit 0: vertical display mode (0 normal 1 up/down reverse) * 0x74: bit 7-4: total poweroff seq delay (0000 vga controller default - * else time in 10ms (10ms to 150ms)) - * bit 3-0: total poweron seq delay (as above) + * else time in 10ms (10ms to 150ms)) + * bit 3-0: total poweron seq delay (as above) * 0x75: contrast power on/off seq delay, same as 0x74 * 0x76: bit 7: backlight control enable (1 means this field is valid) - * bit 6: backlight enabled at boot (0 on 1 off) - * bit 5-0: backlight brightness control steps (0..63) + * bit 6: backlight enabled at boot (0 on 1 off) + * bit 5-0: backlight brightness control steps (0..63) * 0x77: bit 7: contrast control, same bit pattern as 0x76 except bit 6 resvd * 0x78 - 0x7c: reserved * 0x7d: bit 7-4: EPI descriptor major version (1) - * bit 3-0: EPI descriptor minor version (0) + * bit 3-0: EPI descriptor minor version (0) * * ---- * @@ -1436,7 +1436,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr) break; default: printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - edid->bpp); + edid->bpp); return; }
diff --git a/src/lib/gcov-io.c b/src/lib/gcov-io.c index 37c1c3e..6d0ea8d 100644 --- a/src/lib/gcov-io.c +++ b/src/lib/gcov-io.c @@ -419,7 +419,7 @@ gcov_read_words (unsigned words) excess = gcov_var.alloc - gcov_var.length; #endif excess = fread (gcov_var.buffer + gcov_var.length, - 1, excess << 2, gcov_var.file) >> 2; + 1, excess << 2, gcov_var.file) >> 2; gcov_var.length += excess; if (gcov_var.length < words) { diff --git a/src/lib/gcov-io.h b/src/lib/gcov-io.h index c5332ec..a8bd166 100644 --- a/src/lib/gcov-io.h +++ b/src/lib/gcov-io.h @@ -109,8 +109,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see basic_block: header int32:flags* arcs: header int32:block_no arc* arc: int32:dest_block int32:flags - lines: header int32:block_no line* - int32:0 string:NULL + lines: header int32:block_no line* + int32:0 string:NULL line: int32:line_no | int32:0 string:filename
The BASIC_BLOCK record holds per-bb flags. The number of blocks @@ -130,9 +130,9 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see blocks they are for.
The data file contains the following records. - data: {unit summary:object summary:program* function-data*}* + data: {unit summary:object summary:program* function-data*}* unit: header int32:checksum - function-data: announce_function present counts + function-data: announce_function present counts announce_function: header int32:ident int32:lineno_checksum int32:cfg_checksum present: header int32:present @@ -335,26 +335,26 @@ typedef HOST_WIDEST_INT gcov_type; /* Counters that are collected. */ #define GCOV_COUNTER_ARCS 0 /* Arc transitions. */ #define GCOV_COUNTERS_SUMMABLE 1 /* Counters which can be - summed. */ + summed. */ #define GCOV_FIRST_VALUE_COUNTER 1 /* The first of counters used for value - profiling. They must form a consecutive - interval and their order must match - the order of HIST_TYPEs in - value-prof.h. */ + profiling. They must form a consecutive + interval and their order must match + the order of HIST_TYPEs in + value-prof.h. */ #define GCOV_COUNTER_V_INTERVAL 1 /* Histogram of value inside an interval. */ #define GCOV_COUNTER_V_POW2 2 /* Histogram of exact power2 logarithm - of a value. */ + of a value. */ #define GCOV_COUNTER_V_SINGLE 3 /* The most common value of expression. */ #define GCOV_COUNTER_V_DELTA 4 /* The most common difference between - consecutive values of expression. */ + consecutive values of expression. */
#define GCOV_COUNTER_V_INDIR 5 /* The most common indirect address */ #define GCOV_COUNTER_AVERAGE 6 /* Compute average value passed to the - counter. */ + counter. */ #define GCOV_COUNTER_IOR 7 /* IOR of the all values passed to - counter. */ + counter. */ #define GCOV_LAST_VALUE_COUNTER 7 /* The last of counters used for value - profiling. */ + profiling. */ #define GCOV_COUNTERS 8
/* Number of counters used for value profiling. */ @@ -416,7 +416,7 @@ struct gcov_ctr_summary gcov_unsigned_t runs; /* number of program runs */ gcov_type sum_all; /* sum of all counters accumulated. */ gcov_type run_max; /* maximum value on a single run. */ - gcov_type sum_max; /* sum of individual run max values. */ + gcov_type sum_max; /* sum of individual run max values. */ };
/* Object & program summary record. */ @@ -469,7 +469,7 @@ struct gcov_info
unsigned n_functions; /* number of functions */ const struct gcov_fn_info *const *functions; /* pointer to pointers - to function information */ + to function information */ };
/* Register a new object file module. */ @@ -528,7 +528,7 @@ GCOV_LINKAGE struct gcov_var unsigned length; /* Read limit in the block. */ unsigned overread; /* Number of words overread. */ int error; /* < 0 overflow, > 0 disk error. */ - int mode; /* < 0 writing, > 0 reading */ + int mode; /* < 0 writing, > 0 reading */ #if IN_LIBGCOV /* Holds one block plus 4 bytes, thus all coverage reads & writes fit within this buffer and we always can transfer GCOV_BLOCK_SIZE @@ -575,7 +575,7 @@ GCOV_LINKAGE void gcov_write_counter (gcov_type) ATTRIBUTE_HIDDEN; GCOV_LINKAGE void gcov_write_tag_length (gcov_unsigned_t, gcov_unsigned_t) ATTRIBUTE_HIDDEN; GCOV_LINKAGE void gcov_write_summary (gcov_unsigned_t /*tag*/, - const struct gcov_summary *) + const struct gcov_summary *) ATTRIBUTE_HIDDEN; static void gcov_rewrite (void); GCOV_LINKAGE void gcov_seek (gcov_position_t /*position*/) ATTRIBUTE_HIDDEN; @@ -583,7 +583,7 @@ GCOV_LINKAGE void gcov_seek (gcov_position_t /*position*/) ATTRIBUTE_HIDDEN; /* Available outside libgcov */ GCOV_LINKAGE const char *gcov_read_string (void); GCOV_LINKAGE void gcov_sync (gcov_position_t /*base*/, - gcov_unsigned_t /*length */); + gcov_unsigned_t /*length */); #endif
#if !IN_GCOV diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index efb61db..ea1c4c7 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -3,9 +3,9 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val) { #if CONFIG_CACHE_AS_RAM - printk(BIOS_DEBUG, "%s%02x\n", strval, val); + printk(BIOS_DEBUG, "%s%02x\n", strval, val); #else - print_debug(strval); print_debug_hex8(val); print_debug("\n"); + print_debug(strval); print_debug_hex8(val); print_debug("\n"); #endif }
@@ -30,12 +30,12 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl)
/* Now setup those things we can auto detect */ for(i = 0; i < controllers; i++) { - print_debug_sdram_8("Ram2.", i); + print_debug_sdram_8("Ram2.", i);
#if CONFIG_RAMINIT_SYSINFO sdram_set_spd_registers(ctrl + i, sysinfo); #else - sdram_set_spd_registers(ctrl + i); + sdram_set_spd_registers(ctrl + i); #endif
} diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index fed153b..d892425 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -232,7 +232,7 @@ static boot_state_t bs_payload_load(void *arg) timestamp_add_now(TS_LOAD_PAYLOAD);
payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/payload"); + CONFIG_CBFS_PREFIX "/payload"); if (! payload) die("Could not find a payload\n");
@@ -280,10 +280,10 @@ static void bs_report_time(struct boot_state *state) exit_time = mono_time_diff(×->samples[2], ×->samples[3]);
printk(BIOS_DEBUG, "BS: %s times (us): entry %ld run %ld exit %ld\n", - state->name, - rela_time_in_microseconds(&entry_time), - rela_time_in_microseconds(&run_time), - rela_time_in_microseconds(&exit_time)); + state->name, + rela_time_in_microseconds(&entry_time), + rela_time_in_microseconds(&run_time), + rela_time_in_microseconds(&exit_time)); } #else static inline void bs_sample_time(struct boot_state *state) {} @@ -305,7 +305,7 @@ static void bs_run_timers(int drain) {} #endif
static void bs_call_callbacks(struct boot_state *state, - boot_state_sequence_t seq) + boot_state_sequence_t seq) { struct boot_phase *phase = &state->phases[seq];
@@ -320,7 +320,7 @@ static void bs_call_callbacks(struct boot_state *state,
#if BOOT_STATE_DEBUG printk(BS_DEBUG_LVL, "BS: callback (%p) @ %s.\n", - bscb, bscb->location); + bscb, bscb->location); #endif bscb->callback(bscb->arg);
@@ -359,7 +359,7 @@ static void bs_walk_state_machine(void)
if (state->complete) { printk(BIOS_EMERG, "BS: %s state already executed.\n", - state->name); + state->name); break; }
@@ -400,13 +400,13 @@ static void bs_walk_state_machine(void) }
static int boot_state_sched_callback(struct boot_state *state, - struct boot_state_callback *bscb, - boot_state_sequence_t seq) + struct boot_state_callback *bscb, + boot_state_sequence_t seq) { if (state->complete) { printk(BIOS_WARNING, - "Tried to schedule callback on completed state %s.\n", - state->name); + "Tried to schedule callback on completed state %s.\n", + state->name);
return -1; } @@ -418,7 +418,7 @@ static int boot_state_sched_callback(struct boot_state *state, }
int boot_state_sched_on_entry(struct boot_state_callback *bscb, - boot_state_t state_id) + boot_state_t state_id) { struct boot_state *state = &boot_states[state_id];
@@ -426,7 +426,7 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, }
int boot_state_sched_on_exit(struct boot_state_callback *bscb, - boot_state_t state_id) + boot_state_t state_id) { struct boot_state *state = &boot_states[state_id];
@@ -464,7 +464,7 @@ void main(void) post_code(POST_CONSOLE_READY);
printk(BIOS_NOTICE, "coreboot-%s%s %s booting...\n", - coreboot_version, coreboot_extra_version, coreboot_build); + coreboot_version, coreboot_extra_version, coreboot_build);
post_code(POST_CONSOLE_BOOT_MSG);
@@ -490,8 +490,8 @@ int boot_state_block(boot_state_t state, boot_state_sequence_t seq) if (current_phase.state_id > state || (current_phase.state_id == state && current_phase.seq > seq) ) { printk(BIOS_WARNING, - "BS: Completed state (%d, %d) block attempted.\n", - state, seq); + "BS: Completed state (%d, %d) block attempted.\n", + state, seq); return -1; }
@@ -509,8 +509,8 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq) if (current_phase.state_id > state || (current_phase.state_id == state && current_phase.seq > seq) ) { printk(BIOS_WARNING, - "BS: Completed state (%d, %d) unblock attempted.\n", - state, seq); + "BS: Completed state (%d, %d) unblock attempted.\n", + state, seq); return -1; }
@@ -518,8 +518,8 @@ int boot_state_unblock(boot_state_t state, boot_state_sequence_t seq)
if (bp->blockers == 0) { printk(BIOS_WARNING, - "BS: Unblock attempted on non-blocked state (%d, %d).\n", - state, seq); + "BS: Unblock attempted on non-blocked state (%d, %d).\n", + state, seq); return -1; }
diff --git a/src/lib/jpeg.c b/src/lib/jpeg.c index 4297299..6db91cd 100644 --- a/src/lib/jpeg.c +++ b/src/lib/jpeg.c @@ -111,7 +111,7 @@ static void col221111_32 __P((int *, unsigned char *, int)); #define M_APP0 0xe0 #define M_DQT 0xdb #define M_SOF0 0xc0 -#define M_DHT 0xc4 +#define M_DHT 0xc4 #define M_DRI 0xdd #define M_SOS 0xda #define M_RST0 0xd0 @@ -215,7 +215,7 @@ static int readtables(int till) l -= hufflen[i]; } dec_makehuff(dhuff + tt, hufflen, - huffvals); + huffvals); } break;
@@ -265,9 +265,9 @@ int jpeg_check_size(unsigned char *buf, int width, int height) readtables(M_SOF0); getword(); getbyte(); - if (height != getword() || width != getword()) + if (height != getword() || width != getword()) return 0; - return 1; + return 1; }
int jpeg_decode(unsigned char *buf, unsigned char *pic, @@ -409,7 +409,7 @@ int jpeg_decode(unsigned char *buf, unsigned char *pic, }
/****************************************************************/ -/************** huffman decoder ***************/ +/************** huffman decoder ***************/ /****************************************************************/
static int fillbits __P((struct in *, int, unsigned int)); @@ -595,7 +595,7 @@ static void dec_makehuff(struct dec_hufftbl *hu, int *hufflen, unsigned char *hu (DECBITS - (i + 1 + v)) | 128; } else x = v << 16 | (hu-> vals[k] & 0xf0) << 4 | - (DECBITS - (i + 1)); + (DECBITS - (i + 1)); hu->llvals[c | d] = x; } } @@ -608,7 +608,7 @@ static void dec_makehuff(struct dec_hufftbl *hu, int *hufflen, unsigned char *hu }
/****************************************************************/ -/************** idct ***************/ +/************** idct ***************/ /****************************************************************/
#define ONE ((PREC)IFIX(1.)) @@ -768,7 +768,7 @@ static void scaleidctqtab(PREC *q, PREC sc) }
/****************************************************************/ -/************** color decoder ***************/ +/************** color decoder ***************/ /****************************************************************/
#define ROUND @@ -778,20 +778,20 @@ static void scaleidctqtab(PREC *q, PREC sc) * * y:0..255 Cb:-128..127 Cr:-128..127 * - * R = Y + 1.40200 * Cr - * G = Y - 0.34414 * Cb - 0.71414 * Cr - * B = Y + 1.77200 * Cb + * R = Y + 1.40200 * Cr + * G = Y - 0.34414 * Cb - 0.71414 * Cr + * B = Y + 1.77200 * Cb * * => - * Cr *= 1.40200; - * Cb *= 1.77200; - * Cg = 0.19421 * Cb + .50937 * Cr; - * R = Y + Cr; - * G = Y - Cg; - * B = Y + Cb; + * Cr *= 1.40200; + * Cb *= 1.77200; + * Cg = 0.19421 * Cb + .50937 * Cr; + * R = Y + Cr; + * G = Y - Cg; + * B = Y + Cb; * * => - * Cg = (50 * Cb + 130 * Cr + 128) >> 8; + * Cg = (50 * Cb + 130 * Cr + 128) >> 8; */
static void initcol(PREC q[][64]) @@ -842,34 +842,34 @@ static void initcol(PREC q[][64])
#ifdef __LITTLE_ENDIAN #define PIC_16(yin, xin, p, xout, add) \ -( \ - y = outy[(yin) * 8 + xin], \ +( \ + y = outy[(yin) * 8 + xin], \ y = ((CLAMP(y + cr + add*2+1) & 0xf8) << 8) | \ ((CLAMP(y - cg + add ) & 0xfc) << 3) | \ - ((CLAMP(y + cb + add*2+1) ) >> 3), \ - p[(xout) * 2 + 0] = y & 0xff, \ - p[(xout) * 2 + 1] = y >> 8 \ + ((CLAMP(y + cb + add*2+1) ) >> 3), \ + p[(xout) * 2 + 0] = y & 0xff, \ + p[(xout) * 2 + 1] = y >> 8 \ ) #else #ifdef CONFIG_PPC #define PIC_16(yin, xin, p, xout, add) \ -( \ - y = outy[(yin) * 8 + xin], \ +( \ + y = outy[(yin) * 8 + xin], \ y = ((CLAMP(y + cr + add*2+1) & 0xf8) << 7) | \ ((CLAMP(y - cg + add*2+1) & 0xf8) << 2) | \ - ((CLAMP(y + cb + add*2+1) ) >> 3), \ - p[(xout) * 2 + 0] = y >> 8, \ - p[(xout) * 2 + 1] = y & 0xff \ + ((CLAMP(y + cb + add*2+1) ) >> 3), \ + p[(xout) * 2 + 0] = y >> 8, \ + p[(xout) * 2 + 1] = y & 0xff \ ) #else #define PIC_16(yin, xin, p, xout, add) \ -( \ - y = outy[(yin) * 8 + xin], \ +( \ + y = outy[(yin) * 8 + xin], \ y = ((CLAMP(y + cr + add*2+1) & 0xf8) << 8) | \ ((CLAMP(y - cg + add ) & 0xfc) << 3) | \ - ((CLAMP(y + cb + add*2+1) ) >> 3), \ - p[(xout) * 2 + 0] = y >> 8, \ - p[(xout) * 2 + 1] = y & 0xff \ + ((CLAMP(y + cb + add*2+1) ) >> 3), \ + p[(xout) * 2 + 0] = y >> 8, \ + p[(xout) * 2 + 1] = y & 0xff \ ) #endif #endif @@ -892,13 +892,13 @@ static void initcol(PREC q[][64]) PIC(xin / 4 * 8 + 1, (xin & 3) * 2 + 1, pic1, xin * 2 + 1) \ )
-#define PIC221111_16(xin) \ -( \ - CBCRCG(0, xin), \ - PIC_16(xin / 4 * 8 + 0, (xin & 3) * 2 + 0, pic0, xin * 2 + 0, 3), \ - PIC_16(xin / 4 * 8 + 0, (xin & 3) * 2 + 1, pic0, xin * 2 + 1, 0), \ - PIC_16(xin / 4 * 8 + 1, (xin & 3) * 2 + 0, pic1, xin * 2 + 0, 1), \ - PIC_16(xin / 4 * 8 + 1, (xin & 3) * 2 + 1, pic1, xin * 2 + 1, 2) \ +#define PIC221111_16(xin) \ +( \ + CBCRCG(0, xin), \ + PIC_16(xin / 4 * 8 + 0, (xin & 3) * 2 + 0, pic0, xin * 2 + 0, 3), \ + PIC_16(xin / 4 * 8 + 0, (xin & 3) * 2 + 1, pic0, xin * 2 + 1, 0), \ + PIC_16(xin / 4 * 8 + 1, (xin & 3) * 2 + 0, pic1, xin * 2 + 0, 1), \ + PIC_16(xin / 4 * 8 + 1, (xin & 3) * 2 + 1, pic1, xin * 2 + 1, 2) \ )
#define PIC221111_32(xin) \ diff --git a/src/lib/libgcov.c b/src/lib/libgcov.c index dbbd709..7c7615b 100644 --- a/src/lib/libgcov.c +++ b/src/lib/libgcov.c @@ -83,7 +83,7 @@ void __gcov_flush (void) {}
#ifdef L_gcov_merge_add void __gcov_merge_add (gcov_type *counters __attribute__ ((unused)), - unsigned n_counters __attribute__ ((unused))) {} + unsigned n_counters __attribute__ ((unused))) {} #endif
#ifdef L_gcov_merge_single @@ -153,22 +153,22 @@ create_file_directory (char *filename) for (; *s != '\0'; s++) if (IS_DIR_SEPARATOR(*s)) { - char sep = *s; + char sep = *s; *s = '\0';
- /* Try to make directory if it doesn't already exist. */ - if (access (filename, F_OK) == -1 + /* Try to make directory if it doesn't already exist. */ + if (access (filename, F_OK) == -1 #ifdef TARGET_POSIX_IO - && mkdir (filename, 0755) == -1 + && mkdir (filename, 0755) == -1 #else - && mkdir (filename) == -1 + && mkdir (filename) == -1 #endif - /* The directory might have been made by another process. */ + /* The directory might have been made by another process. */ && errno != EEXIST) { - fprintf (stderr, "profiling:%s:Cannot create directory\n", + fprintf (stderr, "profiling:%s:Cannot create directory\n", filename); - *s = sep; + *s = sep; return -1; };
@@ -295,8 +295,8 @@ gcov_version (struct gcov_info *ptr, gcov_unsigned_t version, GCOV_UNSIGNED2STRING (e, GCOV_VERSION);
fprintf (stderr, - "profiling:%s:Version mismatch - expected %.4s got %.4s\n", - filename? filename : ptr->filename, e, v); + "profiling:%s:Version mismatch - expected %.4s got %.4s\n", + filename? filename : ptr->filename, e, v); return 0; } return 1; @@ -428,48 +428,48 @@ gcov_exit (void)
/* Avoid to add multiple drive letters into combined path. */ if (prefix_length != 0 && HAS_DRIVE_SPEC(fname)) - fname += 2; + fname += 2;
/* Build relocated filename, stripping off leading - directories from the initial filename if requested. */ + directories from the initial filename if requested. */ if (gcov_prefix_strip > 0) - { - int level = 0; - s = fname; - if (IS_DIR_SEPARATOR(*s)) - ++s; + { + int level = 0; + s = fname; + if (IS_DIR_SEPARATOR(*s)) + ++s;
- /* Skip selected directory levels. */ + /* Skip selected directory levels. */ for (; (*s != '\0') && (level < gcov_prefix_strip); s++) if (IS_DIR_SEPARATOR(*s)) { fname = s; level++; } - } + }
/* Update complete filename with stripped original. */ if (prefix_length != 0 && !IS_DIR_SEPARATOR (*fname)) - { - /* If prefix is given, add directory separator. */ + { + /* If prefix is given, add directory separator. */ strcpy (gi_filename_up, "/"); strcpy (gi_filename_up + 1, fname); } else - strcpy (gi_filename_up, fname); + strcpy (gi_filename_up, fname);
if (!gcov_open (gi_filename)) { /* Open failed likely due to missed directory. Create directory and retry to open file. */ - if (create_file_directory (gi_filename)) + if (create_file_directory (gi_filename)) { fprintf (stderr, "profiling:%s:Skip\n", gi_filename); continue; } if (!gcov_open (gi_filename)) { - fprintf (stderr, "profiling:%s:Cannot open\n", gi_filename); + fprintf (stderr, "profiling:%s:Cannot open\n", gi_filename); continue; } } @@ -481,7 +481,7 @@ gcov_exit (void) if (tag != GCOV_DATA_MAGIC) { fprintf (stderr, "profiling:%s:Not a gcov data file\n", - gi_filename); + gi_filename); goto read_fatal; } length = gcov_read_unsigned (); @@ -524,7 +524,7 @@ gcov_exit (void)
/* Merge execution counts for each function. */ for (f_ix = 0; (unsigned)f_ix != gi_ptr->n_functions; - f_ix++, tag = gcov_read_unsigned ()) + f_ix++, tag = gcov_read_unsigned ()) { gfi_ptr = gi_ptr->functions[f_ix];
@@ -548,7 +548,7 @@ gcov_exit (void) this point, so cannot simply keep the data in the file. */ fn_tail = buffer_fn_data (gi_filename, - gi_ptr, fn_tail, f_ix); + gi_ptr, fn_tail, f_ix); if (!fn_tail) goto read_mismatch; continue; @@ -577,7 +577,7 @@ gcov_exit (void) tag = gcov_read_unsigned (); length = gcov_read_unsigned (); if (tag != GCOV_TAG_FOR_COUNTER (t_ix) - || length != GCOV_TAG_COUNTER_LENGTH (ci_ptr->num)) + || length != GCOV_TAG_COUNTER_LENGTH (ci_ptr->num)) goto read_mismatch; (*merge) (ci_ptr->values, ci_ptr->num); ci_ptr++; @@ -590,8 +590,8 @@ gcov_exit (void) { read_mismatch:; fprintf (stderr, "profiling:%s:Merge mismatch for %s %u\n", - gi_filename, f_ix >= 0 ? "function" : "summary", - f_ix < 0 ? -1 - f_ix : f_ix); + gi_filename, f_ix >= 0 ? "function" : "summary", + f_ix < 0 ? -1 - f_ix : f_ix); goto read_fatal; } } @@ -599,7 +599,7 @@ gcov_exit (void)
read_error:; fprintf (stderr, "profiling:%s:%s merging\n", gi_filename, - error < 0 ? "Overflow": "Error"); + error < 0 ? "Overflow": "Error");
goto read_fatal;
@@ -637,8 +637,8 @@ gcov_exit (void) && memcmp (cs_all, cs_prg, sizeof (*cs_all))) { fprintf (stderr, "profiling:%s:Invocation mismatch - some data files may have been removed%s\n", - gi_filename, GCOV_LOCKED - ? "" : " or concurrently updated without locking support"); + gi_filename, GCOV_LOCKED + ? "" : " or concurrently updated without locking support"); all_prg.checksum = ~0u; } } @@ -698,7 +698,7 @@ gcov_exit (void)
n_counts = ci_ptr->num; gcov_write_tag_length (GCOV_TAG_FOR_COUNTER (t_ix), - GCOV_TAG_COUNTER_LENGTH (n_counts)); + GCOV_TAG_COUNTER_LENGTH (n_counts)); gcov_type *c_ptr = ci_ptr->values; while (n_counts--) gcov_write_counter (*c_ptr++); @@ -736,7 +736,7 @@ __gcov_init (struct gcov_info *info)
/* Refresh the longest file name information */ if (filename_length > gcov_max_filename) - gcov_max_filename = filename_length; + gcov_max_filename = filename_length;
#ifndef __COREBOOT__ if (!gcov_list) @@ -978,7 +978,7 @@ __gcov_one_value_profiler (gcov_type *counters, gcov_type value) /* Tries to determine the most common value among its inputs. */ void __gcov_indirect_call_profiler (gcov_type* counter, gcov_type value, - void* cur_func, void* callee_func) + void* cur_func, void* callee_func) { /* If the C++ virtual tables contain function descriptors then one function may have multiple descriptors and we need to dereference diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index 1cf647d..f822d15 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -170,9 +170,9 @@ int LzmaDecode(CLzmaDecoderState *vs, CProb *prob; UInt32 bound; int posState = (int)( - (nowPos - ) - & posStateMask); + (nowPos + ) + & posStateMask);
prob = p + IsMatch + (state << kNumPosBitsMax) + posState; IfBit0(prob) @@ -180,30 +180,30 @@ int LzmaDecode(CLzmaDecoderState *vs, int symbol = 1; UpdateBit0(prob) prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); + ((( + (nowPos + ) + & literalPosMask) << lc) + (previousByte >> (8 - lc))));
if (state >= kNumLitStates) { - int matchByte; - matchByte = outStream[nowPos - rep0]; - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); + int matchByte; + matchByte = outStream[nowPos - rep0]; + do + { + int bit; + CProb *probLit; + matchByte <<= 1; + bit = (matchByte & 0x100); + probLit = prob + 0x100 + bit + symbol; + RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) + } + while (symbol < 0x100); } while (symbol < 0x100) { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) + CProb *probLit = prob + symbol; + RC_GET_BIT(probLit, symbol) } previousByte = (Byte)symbol;
@@ -218,173 +218,173 @@ int LzmaDecode(CLzmaDecoderState *vs, prob = p + IsRep + state; IfBit0(prob) { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; + UpdateBit0(prob); + rep3 = rep2; + rep2 = rep1; + rep1 = rep0; + state = state < kNumLitStates ? 0 : 3; + prob = p + LenCoder; } else { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - UpdateBit0(prob); - - if (nowPos == 0) - return LZMA_RESULT_DATA_ERROR; - - state = state < kNumLitStates ? 9 : 11; - previousByte = outStream[nowPos - rep0]; - outStream[nowPos++] = previousByte; - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; + UpdateBit1(prob); + prob = p + IsRepG0 + state; + IfBit0(prob) + { + UpdateBit0(prob); + prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; + IfBit0(prob) + { + UpdateBit0(prob); + + if (nowPos == 0) + return LZMA_RESULT_DATA_ERROR; + + state = state < kNumLitStates ? 9 : 11; + previousByte = outStream[nowPos - rep0]; + outStream[nowPos++] = previousByte; + + continue; + } + else + { + UpdateBit1(prob); + } + } + else + { + UInt32 distance; + UpdateBit1(prob); + prob = p + IsRepG1 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep1; + } + else + { + UpdateBit1(prob); + prob = p + IsRepG2 + state; + IfBit0(prob) + { + UpdateBit0(prob); + distance = rep2; + } + else + { + UpdateBit1(prob); + distance = rep3; + rep3 = rep2; + } + rep2 = rep1; + } + rep1 = rep0; + rep0 = distance; + } + state = state < kNumLitStates ? 8 : 11; + prob = p + RepLenCoder; } { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; + int numBits, offset; + CProb *probLen = prob + LenChoice; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenLow + (posState << kLenNumLowBits); + offset = 0; + numBits = kLenNumLowBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenChoice2; + IfBit0(probLen) + { + UpdateBit0(probLen); + probLen = prob + LenMid + (posState << kLenNumMidBits); + offset = kLenNumLowSymbols; + numBits = kLenNumMidBits; + } + else + { + UpdateBit1(probLen); + probLen = prob + LenHigh; + offset = kLenNumLowSymbols + kLenNumMidSymbols; + numBits = kLenNumHighBits; + } + } + RangeDecoderBitTreeDecode(probLen, numBits, len); + len += offset; }
if (state < 4) { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } + int posSlot; + state += kNumLitStates; + prob = p + PosSlot + + ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << + kNumPosSlotBits); + RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); + if (posSlot >= kStartPosModelIndex) + { + int numDirectBits = ((posSlot >> 1) - 1); + rep0 = (2 | ((UInt32)posSlot & 1)); + if (posSlot < kEndPosModelIndex) + { + rep0 <<= numDirectBits; + prob = p + SpecPos + rep0 - posSlot - 1; + } + else + { + numDirectBits -= kNumAlignBits; + do + { + RC_NORMALIZE + Range >>= 1; + rep0 <<= 1; + if (Code >= Range) + { + Code -= Range; + rep0 |= 1; + } + } + while (--numDirectBits != 0); + prob = p + Align; + rep0 <<= kNumAlignBits; + numDirectBits = kNumAlignBits; + } + { + int i = 1; + int mi = 1; + do + { + CProb *prob3 = prob + mi; + RC_GET_BIT2(prob3, mi, ; , rep0 |= i); + i <<= 1; + } + while(--numDirectBits != 0); + } + } + else + rep0 = posSlot; + if (++rep0 == (UInt32)(0)) + { + /* it's for stream version */ + len = kLzmaStreamWasFinishedId; + break; + } }
len += kMatchMinLen; if (rep0 > nowPos) - return LZMA_RESULT_DATA_ERROR; + return LZMA_RESULT_DATA_ERROR;
do { - previousByte = outStream[nowPos - rep0]; - len--; - outStream[nowPos++] = previousByte; + previousByte = outStream[nowPos - rep0]; + len--; + outStream[nowPos++] = previousByte; } while(len != 0 && nowPos < outSize); } diff --git a/src/lib/memrange.c b/src/lib/memrange.c index af56e72..d99fece 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -25,21 +25,21 @@ static struct range_entry *free_list;
static inline void range_entry_link(struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry *r) { r->next = *prev_ptr; *prev_ptr = r; }
static inline void range_entry_unlink(struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry *r) { *prev_ptr = r->next; r->next = NULL; }
static inline void range_entry_unlink_and_free(struct range_entry **prev_ptr, - struct range_entry *r) + struct range_entry *r) { range_entry_unlink(prev_ptr, r); range_entry_link(&free_list, r); @@ -59,7 +59,7 @@ static struct range_entry *alloc_range(void)
static inline struct range_entry * range_list_add(struct range_entry **prev_ptr, resource_t begin, resource_t end, - unsigned long tag) + unsigned long tag) { struct range_entry *new_entry;
@@ -107,8 +107,8 @@ static void merge_neighbor_entries(struct memranges *ranges) }
static void remove_memranges(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long unused) + resource_t begin, resource_t end, + unsigned long unused) { struct range_entry *cur; struct range_entry *next; @@ -171,8 +171,8 @@ static void remove_memranges(struct memranges *ranges, }
static void merge_add_memranges(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long tag) + resource_t begin, resource_t end, + unsigned long tag) { struct range_entry *cur; struct range_entry **prev_ptr; @@ -205,12 +205,12 @@ static void merge_add_memranges(struct memranges *ranges, }
typedef void (*range_action_t)(struct memranges *ranges, - resource_t begin, resource_t end, - unsigned long tag); + resource_t begin, resource_t end, + unsigned long tag);
static void do_action(struct memranges *ranges, - resource_t base, resource_t size, unsigned long tag, - range_action_t action) + resource_t base, resource_t size, unsigned long tag, + range_action_t action) { resource_t end; resource_t begin; @@ -225,13 +225,13 @@ static void do_action(struct memranges *ranges, }
void memranges_create_hole(struct memranges *ranges, - resource_t base, resource_t size) + resource_t base, resource_t size) { do_action(ranges, base, size, -1, remove_memranges); }
void memranges_insert(struct memranges *ranges, - resource_t base, resource_t size, unsigned long tag) + resource_t base, resource_t size, unsigned long tag) { do_action(ranges, base, size, tag, merge_add_memranges); } @@ -249,8 +249,8 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res) }
void memranges_add_resources(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) + unsigned long mask, unsigned long match, + unsigned long tag) { struct collect_context context;
@@ -264,8 +264,8 @@ void memranges_add_resources(struct memranges *ranges, }
void memranges_init(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) + unsigned long mask, unsigned long match, + unsigned long tag) { ranges->entries = NULL; memranges_add_resources(ranges, mask, match, tag); @@ -279,7 +279,7 @@ void memranges_teardown(struct memranges *ranges) }
void memranges_fill_holes_up_to(struct memranges *ranges, - resource_t limit, unsigned long tag) + resource_t limit, unsigned long tag) { struct range_entry *cur; struct range_entry *prev; @@ -301,7 +301,7 @@ void memranges_fill_holes_up_to(struct memranges *ranges, if (end >= limit) end = limit - 1; range_list_add(&prev->next, range_entry_end(prev), - end, tag); + end, tag); }
prev = cur; @@ -316,14 +316,14 @@ void memranges_fill_holes_up_to(struct memranges *ranges, * to be added to cover the range up to the limit. */ if (prev != NULL && range_entry_end(prev) < limit) range_list_add(&prev->next, range_entry_end(prev), - limit - 1, tag); + limit - 1, tag);
/* Merge all entries that were newly added. */ merge_neighbor_entries(ranges); }
struct range_entry *memranges_next_entry(struct memranges *ranges, - const struct range_entry *r) + const struct range_entry *r) { return r->next; } diff --git a/src/lib/ne2k.c b/src/lib/ne2k.c index b678d79..ca89078 100644 --- a/src/lib/ne2k.c +++ b/src/lib/ne2k.c @@ -155,7 +155,7 @@ unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned shor sum = (sum + (sum >> 16)) & 0xFFFF; } } - return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff; + return (~((sum & 0xff) | (((sum >> 8) & 0xff) << 8) )) & 0xffff; }
@@ -389,7 +389,7 @@ int ne2k_init(unsigned int eth_nic_base) {
/* Power management controller */ dev = pci_locate_device(PCI_ID(0x10ec, - 0x8029), 0); + 0x8029), 0);
if (dev == PCI_DEV_INVALID) return 0; @@ -443,16 +443,16 @@ static void read_resources(struct device *dev)
static struct device_operations ne2k_ops = { .read_resources = read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, + .init = 0, + .scan_bus = 0, };
static const struct pci_driver ne2k_driver __pci_driver = { - .ops = &ne2k_ops, - .vendor = 0x10ec, - .device = 0x8029, + .ops = &ne2k_ops, + .vendor = 0x10ec, + .device = 0x8029, };
#endif diff --git a/src/lib/ns8390.h b/src/lib/ns8390.h index eeffe45..82335a3 100644 --- a/src/lib/ns8390.h +++ b/src/lib/ns8390.h @@ -95,7 +95,7 @@ NE1000/2000 definitions
#define D8390_TXBUF_SIZE 6 #define D8390_RXBUF_END 32 -#define D8390_PAGE_SIZE 256 +#define D8390_PAGE_SIZE 256
struct ringbuffer { unsigned char status; diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index e9173fa..6ca89f7 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -179,7 +179,7 @@ void ram_check(unsigned long start, unsigned long stop) /* * This is much more of a "Is my DRAM properly configured?" * test than a "Is my DRAM faulty?" test. Not all bits - * are tested. -Tyson + * are tested. -Tyson */ #if !defined(__ROMCC__) printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start); @@ -204,7 +204,7 @@ int ram_check_nodie(unsigned long start, unsigned long stop) /* * This is much more of a "Is my DRAM properly configured?" * test than a "Is my DRAM faulty?" test. Not all bits - * are tested. -Tyson + * are tested. -Tyson */ #if !defined(__ROMCC__) printk(BIOS_DEBUG, "Testing DRAM at : %08lx\n", start); diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 462c7d7..8baa3f1 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -71,7 +71,7 @@ static inline int rmodule_is_loaded(const struct rmodule *module)
/* Calculate a loaded program address based on the blob address. */ static inline void *rmodule_load_addr(const struct rmodule *module, - u32 blob_addr) + u32 blob_addr) { char *loc = module->location; return &loc[blob_addr - module->header->module_link_start_address]; @@ -104,7 +104,7 @@ int rmodule_parse(void *ptr, struct rmodule *module) /* The payload lives after the header. */ module->payload = &base[rhdr->payload_begin_offset]; module->payload_size = rhdr->payload_end_offset - - rhdr->payload_begin_offset; + rhdr->payload_begin_offset; module->relocations = &base[rhdr->relocations_begin_offset];
return 0; @@ -130,7 +130,7 @@ void *rmodule_parameters(const struct rmodule *module) int rmodule_entry_offset(const struct rmodule *module) { return module->header->module_entry_point - - module->header->module_link_start_address; + module->header->module_link_start_address; }
void *rmodule_entry(const struct rmodule *module) @@ -164,9 +164,9 @@ static inline int rmodule_number_relocations(const struct rmodule *module) static void rmodule_copy_payload(const struct rmodule *module) { printk(BIOS_DEBUG, "Loading module at %p with entry %p. " - "filesize: 0x%x memsize: 0x%x\n", - module->location, rmodule_entry(module), - module->payload_size, rmodule_memory_size(module)); + "filesize: 0x%x memsize: 0x%x\n", + module->location, rmodule_entry(module), + module->payload_size, rmodule_memory_size(module));
/* No need to copy the payload if the load location and the * payload location are the same. */ @@ -177,7 +177,7 @@ static void rmodule_copy_payload(const struct rmodule *module) }
static inline u32 *rmodule_adjustment_location(const struct rmodule *module, - const void *reloc) + const void *reloc) { int reloc_offset;
@@ -203,7 +203,7 @@ static int rmodule_relocate(const struct rmodule *module) num_relocations = rmodule_number_relocations(module);
printk(BIOS_DEBUG, "Processing %d relocs with adjust value of 0x%08x\n", - num_relocations, adjustment); + num_relocations, adjustment);
while (num_relocations > 0) { u32 *adjust_loc; @@ -215,8 +215,8 @@ static int rmodule_relocate(const struct rmodule *module) adjust_loc = rmodule_adjustment_location(module, reloc); if (adjust_loc != NULL) { printk(PK_ADJ_LEVEL, "Adjusting %p: 0x%08x -> 0x%08x\n", - adjust_loc, *adjust_loc, - *adjust_loc + adjustment); + adjust_loc, *adjust_loc, + *adjust_loc + adjustment); *adjust_loc += adjustment; }
@@ -244,8 +244,8 @@ int rmodule_load(void *base, struct rmodule *module) * 1. Copy payload to base address. * 2. Adjust relocations within the module to new base address. * 3. Clear the bss segment last since the relocations live where - * the bss is. If an rmodule is being loaded from its load - * address the relocations need to be processed before the bss. + * the bss is. If an rmodule is being loaded from its load + * address the relocations need to be processed before the bss. */ module->location = base; rmodule_copy_payload(module); @@ -256,7 +256,7 @@ int rmodule_load(void *base, struct rmodule *module) }
int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, - size_t *region_size, int *load_offset) + size_t *region_size, int *load_offset) { /* region_alignment must be a power of 2. */ if (region_alignment & (region_alignment - 1)) @@ -289,7 +289,7 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, * +--------------------------------+ region_alignment + region_size * | >= 0 bytes from alignment | * +--------------------------------+ program end (4KiB aligned) - * | program size | + * | program size | * +--------------------------------+ program_begin (4KiB aligned) * | sizeof(struct rmodule_header) | * +--------------------------------+ rmodule header start diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 0cdbb2f..74f07fd 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -126,7 +126,7 @@ SECTIONS } _relocations_begin_offset = LOADADDR(.relocations); _relocations_end_offset = _relocations_begin_offset + - SIZEOF(.relocations); + SIZEOF(.relocations);
/DISCARD/ : { /* Drop unnecessary sections. Since these modules are linked diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 222eae2..97ed84f 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -200,7 +200,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) * to load onto the bounce buffer instead. */ /* ret: 1 : A new segment is inserted before the seg. - * 0 : A new segment is inserted after the seg, or no new one. + * 0 : A new segment is inserted after the seg, or no new one. */ unsigned long start, middle, end, ret = 0;
@@ -247,7 +247,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) /* compute the new value of start */ start = seg->s_dstaddr;
- printk(BIOS_SPEW, " early: [0x%016lx, 0x%016lx, 0x%016lx)\n", + printk(BIOS_SPEW, " early: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); @@ -279,7 +279,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->next->prev = new; seg->next = new;
- printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", + printk(BIOS_SPEW, " late: [0x%016lx, 0x%016lx, 0x%016lx)\n", new->s_dstaddr, new->s_dstaddr + new->s_filesz, new->s_dstaddr + new->s_memsz); @@ -358,7 +358,7 @@ static int build_self_segment_list(
case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); + (void *)(intptr_t)ntohll(segment->load_addr)); *entry = ntohll(segment->load_addr); /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the diff --git a/src/lib/stack.c b/src/lib/stack.c index 1f9e009..d3c5514 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -1,6 +1,6 @@ /* This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described +called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has been authored by an employee or employees of the University of diff --git a/src/lib/thread.c b/src/lib/thread.c index 6508bfa..02c797c 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -192,8 +192,8 @@ static void asmlinkage call_wrapper_block_state(void *arg) /* Prepare a thread so that it starts by executing thread_entry(thread_arg). * Within thread_entry() it will call func(arg). */ static void prepare_thread(struct thread *t, void *func, void *arg, - void asmlinkage (*thread_entry)(void *), - void *thread_arg) + void asmlinkage (*thread_entry)(void *), + void *thread_arg) { /* Stash the function and argument to run. */ t->entry = func; @@ -291,7 +291,7 @@ int thread_run(void (*func)(void *), void *arg)
if (!thread_can_yield(current)) { printk(BIOS_ERR, - "thread_run() called from non-yielding context!\n"); + "thread_run() called from non-yielding context!\n"); return -1; }
@@ -309,7 +309,7 @@ int thread_run(void (*func)(void *), void *arg) }
int thread_run_until(void (*func)(void *), void *arg, - boot_state_t state, boot_state_sequence_t seq) + boot_state_t state, boot_state_sequence_t seq) { struct thread *current; struct thread *t; @@ -319,7 +319,7 @@ int thread_run_until(void (*func)(void *), void *arg,
if (!thread_can_yield(current)) { printk(BIOS_ERR, - "thread_run() called from non-yielding context!\n"); + "thread_run() called from non-yielding context!\n"); return -1; }
diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index 8d11f10..edb83b1 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -53,7 +53,7 @@ static inline struct timeout_callback *timer_queue_head(struct timer_queue *tq) }
static int timer_queue_insert(struct timer_queue *tq, - struct timeout_callback *tocb) + struct timeout_callback *tocb) { int index;
@@ -103,7 +103,7 @@ static int timer_queue_min_child_index(struct timer_queue *tq, int index) return left_child_index;
if (mono_time_cmp(&tq->queue[left_child_index]->expiration, - &tq->queue[right_child_index]->expiration) < 0) { + &tq->queue[right_child_index]->expiration) < 0) { return left_child_index; } return right_child_index; diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 261b90f..08b8e8b 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -97,8 +97,8 @@ void uart8250_init(unsigned base_port, unsigned divisor) outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
/* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - outb(divisor & 0xFF, base_port + UART_DLL); - outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
/* Set to 3 for 8N1 */ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 885599b..eacbcfd 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -630,12 +630,12 @@ try_next_port:
dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar); dprintk(BIOS_INFO, "debug_port: %d\n", debug_port); - dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); + dprintk(BIOS_INFO, "n_ports: %d\n", n_ports);
- for (i = 1; i <= n_ports; i++) { - portsc = read32((unsigned long)&ehci_regs->port_status[i-1]); - dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc); - } + for (i = 1; i <= n_ports; i++) { + portsc = read32((unsigned long)&ehci_regs->port_status[i-1]); + dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc); + }
if(port_map_tried && (new_debug_port != debug_port)) { if(--playtimes) { diff --git a/src/lib/version.c b/src/lib/version.c index 4ec1eb6..cb6857a 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -50,7 +50,7 @@ const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; const char coreboot_compile_by[] = COREBOOT_COMPILE_BY; const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST; const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN; -const char coreboot_compiler[] = COREBOOT_COMPILER; -const char coreboot_linker[] = COREBOOT_LINKER; -const char coreboot_assembler[] = COREBOOT_ASSEMBLER; +const char coreboot_compiler[] = COREBOOT_COMPILER; +const char coreboot_linker[] = COREBOOT_LINKER; +const char coreboot_assembler[] = COREBOOT_ASSEMBLER;
diff --git a/src/lib/xmodem.c b/src/lib/xmodem.c index c3bb1d8..4d2170a 100644 --- a/src/lib/xmodem.c +++ b/src/lib/xmodem.c @@ -1,6 +1,6 @@ /* - Copyright 2006 Arastra, Inc. - Copyright 2001, 2002 Georges Menie (www.menie.org) + Copyright 2006 Arastra, Inc. + Copyright 2001, 2002 Georges Menie (www.menie.org)
This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fdb0eac..60c3101 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -338,7 +338,7 @@ config MAINBOARD_SERIAL_NUMBER string "SMBIOS Serial Number" depends on GENERATE_SMBIOS_TABLES default "123456789" - help + help The Serial Number to store in SMBIOS structures.
config MAINBOARD_VERSION diff --git a/src/mainboard/a-trend/atc-6220/devicetree.cb b/src/mainboard/a-trend/atc-6220/devicetree.cb index 0dea9ae..1488b86 100644 --- a/src/mainboard/a-trend/atc-6220/devicetree.cb +++ b/src/mainboard/a-trend/atc-6220/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/a-trend/atc-6220/irq_tables.c b/src/mainboard/a-trend/atc-6220/irq_tables.c index c1b42e4..58bb855 100644 --- a/src/mainboard/a-trend/atc-6220/irq_tables.c +++ b/src/mainboard/a-trend/atc-6220/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x4e, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/a-trend/atc-6240/devicetree.cb b/src/mainboard/a-trend/atc-6240/devicetree.cb index e0bfdac..9641b21 100644 --- a/src/mainboard/a-trend/atc-6240/devicetree.cb +++ b/src/mainboard/a-trend/atc-6240/devicetree.cb @@ -9,48 +9,48 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - io 0x60 = 0x00 - end - device pnp 3f0.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 3f0.8 off # GPIO 2 / WDT - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a off # ACPI - end - device pnp 3f0.b off # HWM (TODO) - end - end + chip superio/winbond/w83627hf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + io 0x60 = 0x00 + end + device pnp 3f0.7 on # Game port / MIDI / GPIO 1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 3f0.8 off # GPIO 2 / WDT + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a off # ACPI + end + device pnp 3f0.b off # HWM (TODO) + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/a-trend/atc-6240/irq_tables.c b/src/mainboard/a-trend/atc-6240/irq_tables.c index 3383056..20e865b 100644 --- a/src/mainboard/a-trend/atc-6240/irq_tables.c +++ b/src/mainboard/a-trend/atc-6240/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x44, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0e<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c b/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c index 79bbb3e..998bf4e 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c +++ b/src/mainboard/aaeon/pfm-540i_revb/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -58,7 +58,7 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* CPU */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* Ethernet */ diff --git a/src/mainboard/abit/be6-ii_v2_0/devicetree.cb b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb index 3a6648a..2323043 100644 --- a/src/mainboard/abit/be6-ii_v2_0/devicetree.cb +++ b/src/mainboard/abit/be6-ii_v2_0/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB) device pci 7.2 on end # USB diff --git a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c index dfc639b..7f1659a 100644 --- a/src/mainboard/abit/be6-ii_v2_0/irq_tables.c +++ b/src/mainboard/abit/be6-ii_v2_0/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x4b, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x13<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x11<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x61, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index fdf08aa..bb0061c 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -93,7 +93,7 @@ config RAMBASE default 0x200000
config VGA_BIOS_ID - string - default "1002,9712" + string + default "1002,9712"
endif #BOARD_ADVANSUS_A785E_I diff --git a/src/mainboard/advansus/a785e-i/acpi/ide.asl b/src/mainboard/advansus/a785e-i/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/advansus/a785e-i/acpi/ide.asl +++ b/src/mainboard/advansus/a785e-i/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c index 2591d84..a941938 100644 --- a/src/mainboard/advansus/a785e-i/acpi_tables.c +++ b/src/mainboard/advansus/a785e-i/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/advansus/a785e-i/cmos.layout b/src/mainboard/advansus/a785e-i/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/advansus/a785e-i/cmos.layout +++ b/src/mainboard/advansus/a785e-i/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index f7db1cc..ac3b1f5 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -57,46 +57,46 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 94757b5..0150658 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ADVANSUS", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "ADVANSUS", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -129,13 +129,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -154,7 +154,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -279,8 +279,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -416,16 +416,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -796,7 +796,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1175,7 +1175,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1197,8 +1197,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1208,8 +1208,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1217,8 +1217,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1226,8 +1226,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1236,8 +1236,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1246,8 +1246,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1255,8 +1255,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1264,32 +1264,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1543,8 +1543,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1587,43 +1587,43 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1632,7 +1632,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 0feeed5..991839f 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -137,7 +137,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d..75595a5 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -42,7 +42,7 @@ void enable_int_gfx(void) RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ #endif /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c index 73ada4d..9f5bc3f 100644 --- a/src/mainboard/advansus/a785e-i/mptable.c +++ b/src/mainboard/advansus/a785e-i/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11, dword); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -81,7 +81,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index f1eb9f5..c608916 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -141,13 +141,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -219,7 +219,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/advansus/a785e-i/resourcemap.c b/src/mainboard/advansus/a785e-i/resourcemap.c index 183883a..a1fe5a0 100644 --- a/src/mainboard/advansus/a785e-i/resourcemap.c +++ b/src/mainboard/advansus/a785e-i/resourcemap.c @@ -31,21 +31,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -65,25 +65,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -104,27 +104,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -145,21 +145,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -176,23 +176,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -206,23 +206,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -236,35 +236,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 8e7aa40..dcdd356 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -238,8 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/advantech/pcm-5820/devicetree.cb b/src/mainboard/advantech/pcm-5820/devicetree.cb index 8027ee2..b7f62d7 100644 --- a/src/mainboard/advantech/pcm-5820/devicetree.cb +++ b/src/mainboard/advantech/pcm-5820/devicetree.cb @@ -3,44 +3,44 @@ chip northbridge/amd/gx1 # Northbridge device pci 0.0 on end # Host bridge chip southbridge/amd/cs5530 # Southbridge device pci 12.0 on # ISA bridge - chip superio/winbond/w83977f # SUper I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.4 on # RTC / On-Now control - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # IR - # TODO? - end - device pnp 3f0.7 on # GPIO 1 - # TODO? - end - device pnp 3f0.8 on # GPIO 2 - # TODO? - end - end + chip superio/winbond/w83977f # SUper I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.4 on # RTC / On-Now control + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # IR + # TODO? + end + device pnp 3f0.7 on # GPIO 1 + # TODO? + end + device pnp 3f0.8 on # GPIO 2 + # TODO? + end + end end device pci 12.1 on end # SMI device pci 12.2 on end # IDE diff --git a/src/mainboard/advantech/pcm-5820/irq_tables.c b/src/mainboard/advantech/pcm-5820/irq_tables.c index ac25227..e9dc6dd 100644 --- a/src/mainboard/advantech/pcm-5820/irq_tables.c +++ b/src/mainboard/advantech/pcm-5820/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xde, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0b << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, } diff --git a/src/mainboard/amd/bimini_fam10/acpi/ide.asl b/src/mainboard/amd/bimini_fam10/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/amd/bimini_fam10/acpi/ide.asl +++ b/src/mainboard/amd/bimini_fam10/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/bimini_fam10/acpi_tables.c b/src/mainboard/amd/bimini_fam10/acpi_tables.c index f86ea02..c693d47 100644 --- a/src/mainboard/amd/bimini_fam10/acpi_tables.c +++ b/src/mainboard/amd/bimini_fam10/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/bimini_fam10/cmos.layout b/src/mainboard/amd/bimini_fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/amd/bimini_fam10/cmos.layout +++ b/src/mainboard/amd/bimini_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index 25676f0..9274797 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 off end # register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "2" # Configuration C + register "gpp_configuration" = "2" # Configuration C register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 03a00e0..e345537 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -129,13 +129,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -154,7 +154,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -279,8 +279,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -416,16 +416,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -796,7 +796,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1175,7 +1175,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1197,8 +1197,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1208,8 +1208,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1217,8 +1217,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1226,8 +1226,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1236,8 +1236,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1246,8 +1246,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1255,8 +1255,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1264,32 +1264,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1543,8 +1543,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1587,43 +1587,43 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1632,7 +1632,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index c4924d4..1aabc9a 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 32c8862..d48e814 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -90,7 +90,7 @@ u8 is_dev3_present(void) return 0; }
-#if 0 /* not tested yet. */ +#if 0 /* not tested yet. */ /******************************************************** * bimini uses SB800 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c index 792fa41..3c7d56f 100644 --- a/src/mainboard/amd/bimini_fam10/mptable.c +++ b/src/mainboard/amd/bimini_fam10/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -74,7 +74,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -85,7 +85,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -138,7 +138,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/bimini_fam10/resourcemap.c b/src/mainboard/amd/bimini_fam10/resourcemap.c index 1d8d523..8fc8b02 100644 --- a/src/mainboard/amd/bimini_fam10/resourcemap.c +++ b/src/mainboard/amd/bimini_fam10/resourcemap.c @@ -31,21 +31,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -65,25 +65,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -104,27 +104,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -145,21 +145,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -176,23 +176,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -206,23 +206,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -236,35 +236,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7afec9a..aaf0d38 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -243,8 +243,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/amd/db800/cmos.layout b/src/mainboard/amd/db800/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/amd/db800/cmos.layout +++ b/src/mainboard/amd/db800/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/amd/db800/irq_tables.c b/src/mainboard/amd/db800/irq_tables.c index b5495ac..167b1f6 100644 --- a/src/mainboard/amd/db800/irq_tables.c +++ b/src/mainboard/amd/db800/irq_tables.c @@ -43,7 +43,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -52,10 +52,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x002B, /* Device */ 0, /* Miniport data */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ diff --git a/src/mainboard/amd/dbm690t/acpi/ide.asl b/src/mainboard/amd/dbm690t/acpi/ide.asl index 7cee00d..5e6d207 100644 --- a/src/mainboard/amd/dbm690t/acpi/ide.asl +++ b/src/mainboard/amd/dbm690t/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/dbm690t/acpi_tables.c b/src/mainboard/amd/dbm690t/acpi_tables.c index 3b659b1..b7a28ad 100644 --- a/src/mainboard/amd/dbm690t/acpi_tables.c +++ b/src/mainboard/amd/dbm690t/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/dbm690t/cmos.layout b/src/mainboard/amd/dbm690t/cmos.layout index 86aadf5..981f476 100644 --- a/src/mainboard/amd/dbm690t/cmos.layout +++ b/src/mainboard/amd/dbm690t/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index 8dd971e..17e6a9e 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/amd/amdk8/root_complex device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 32df673..fe30c4c 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -380,16 +380,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -762,7 +762,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1142,7 +1142,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1164,8 +1164,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1175,8 +1175,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1184,8 +1184,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1193,8 +1193,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1396,7 +1396,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1411,7 +1411,7 @@ DefinitionBlock ( Offset (0xF0), APC0, 8, /* APC/PME Event Enable Register */ APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ + APC2, 8, /* APC/PME Control Register 1 */ APC3, 8, /* Environment Controller Special Configuration Register */ APC4, 8 /* APC/PME Control Register 2 */ } @@ -1435,7 +1435,7 @@ DefinitionBlock ( * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1577,23 +1577,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1602,7 +1602,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 43a8d91..02d5c0e 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -27,12 +27,12 @@ #include <southbridge/amd/sb600/sb600.h>
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); + u8 val); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 8ef9138..5866da7 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index c9888b9..7a1c439 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -28,15 +28,15 @@ #include "OEM.h" /* SMBUS0_BASE_ADDRESS */
#ifndef SB_GPIO_REG01 -#define SB_GPIO_REG01 1 +#define SB_GPIO_REG01 1 #endif
#ifndef SB_GPIO_REG24 -#define SB_GPIO_REG24 24 +#define SB_GPIO_REG24 24 #endif
#ifndef SB_GPIO_REG27 -#define SB_GPIO_REG27 27 +#define SB_GPIO_REG27 27 #endif
#ifdef __PRE_RAM__ @@ -48,9 +48,9 @@ static void select_socket(UINT8 socket_id) { AMD_CONFIG_PARAMS StdHeader; - UINT32 PciData32; - UINT8 PciData8; - PCI_ADDR PciAddress; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress;
/* Set SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); @@ -200,12 +200,12 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -222,14 +222,14 @@ AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -352,12 +352,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -470,8 +470,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -504,7 +504,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); return Status; @@ -512,9 +512,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -577,13 +577,13 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16;
FcnData = Data; MemData = ConfigPtr; @@ -591,10 +591,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h index 4159076..b09a4a9 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.h +++ b/src/mainboard/amd/dinar/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; @@ -68,12 +68,12 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h index a756942..277ed9c 100644 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -50,15 +50,15 @@ * **/
-//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl index 1ff2e79..545d6e5 100644 --- a/src/mainboard/amd/dinar/acpi/ide.asl +++ b/src/mainboard/amd/dinar/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 179822b..18a0d27 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -41,38 +41,38 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); @@ -83,12 +83,12 @@ extern VOID OemCustomizeInitPost(IN AMD_POST_PARAMS *InitPost); BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the MMIO configuration space range. The size of the MMIO configuration space range varies with this field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: -Bits Buses Bits Buses -0h 1 5h 32 -1h 2 6h 64 -2h 4 7h 128 -3h 8 8h 256 -4h 16 Fh-9h Reserved +Bits Buses Bits Buses +0h 1 5h 32 +1h 2 6h 64 +2h 4 7h 128 +3h 8 8h 256 +4h 16 Fh-9h Reserved */ STATIC UINT8 @@ -97,7 +97,7 @@ GetEndBusNum ( ) { UINT64 BusNum; - UINT8 Index; + UINT8 Index; for (Index = 1; Index <= 8; Index ++ ) { BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; if (BusNum == 1 ) { @@ -109,16 +109,16 @@ GetEndBusNum (
static UINT32 amdinitcpuio(VOID) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 TopMem; - UINT32 NodeCnt; - UINT32 Node; - UINT32 SbLink; - UINT32 Index; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 NodeCnt; + UINT32 Node; + UINT32 SbLink; + UINT32 Index;
/* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); @@ -232,11 +232,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -366,7 +366,7 @@ agesawrapper_amdinitearly ( * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -377,7 +377,7 @@ VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
VOID OemCustomizeInitPost ( - IN AMD_POST_PARAMS *InitPost + IN AMD_POST_PARAMS *InitPost ) { InitPost->MemConfig.UmaMode = UMA_AUTO; @@ -391,8 +391,8 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr;
@@ -528,9 +528,9 @@ agesawrapper_amdinitlate(VOID) AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -560,8 +560,8 @@ agesawrapper_amdinitlate(VOID) AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 62fd277..528ca70 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,48 +31,48 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MMIO_NP_BIT BIT7 +#define MMIO_NP_BIT BIT7
/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 +#define SB_ACPI_BASE_ADDRESS 0x0400 #define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 #define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn #define MmioAddress( BaseAddr, Register ) \ ( (UINTN)BaseAddr + \ (UINTN)(Register) \ @@ -83,19 +83,19 @@ *Mmio32Ptr( BaseAddr, Register )
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -105,17 +105,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 41f5415..ec1be45 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 6049 $ @e $Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ */ @@ -89,75 +89,75 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_PLAT_NUM_IO_APICS 2 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE -#define BLDCFG_ONLINE_SPARE TRUE -#define BLDCFG_MEMORY_PARITY_ENABLE TRUE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION TRUE -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 0 -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased -#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 -//#define BLDCFG_USE_ATM_MODE TRUE - -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_PLAT_NUM_IO_APICS 2 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE +#define BLDCFG_ONLINE_SPARE TRUE +#define BLDCFG_MEMORY_PARITY_ENABLE TRUE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION TRUE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 0 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 +//#define BLDCFG_USE_ATM_MODE TRUE + +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 #define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife -//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 +//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000
-//#define IDSOPT_IDS_ENABLED TRUE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define IDSOPT_IDS_ENABLED TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE #define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE -#define BLDCFG_PSTATE_HPC_MODE FALSE +#define BLDCFG_PSTATE_HPC_MODE FALSE
#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap /* @@ -166,18 +166,18 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
/***************************************************************************** @@ -202,8 +202,8 @@ #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. -#define INSTALL_G34_SOCKET_SUPPORT TRUE -#define INSTALL_FAMILY_10_SUPPORT TRUE +#define INSTALL_G34_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_10_SUPPORT TRUE #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT @@ -223,13 +223,13 @@ // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0xFF) -#define DFLT_SCRUB_L2_RATE (0x10) -#define DFLT_SCRUB_L3_RATE (0x10) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0x12) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define DFLT_VRM_SLEW_RATE (2500) +#define DFLT_SCRUB_DRAM_RATE (0xFF) +#define DFLT_SCRUB_L2_RATE (0x10) +#define DFLT_SCRUB_L3_RATE (0x10) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0x12) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define DFLT_VRM_SLEW_RATE (2500)
/* Process the options... * This file include MUST occur @@ -409,7 +409,7 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -424,51 +424,51 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. //
- // Dinar has the following routing: - // CS0 M[B,A]_CLK_H/L[0] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[1] - // CS3 M[B,A]_CLK_H/L[3] + // Dinar has the following routing: + // CS0 M[B,A]_CLK_H/L[0] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[1] + // CS3 M[B,A]_CLK_H/L[3] MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), PSO_END @@ -494,8 +494,8 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -521,7 +521,7 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); /* *************************************************************************** @@ -530,7 +530,7 @@ UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0 */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ @@ -544,7 +544,7 @@ UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0 */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout index 89ef0ca..9a34814 100644 --- a/src/mainboard/amd/dinar/cmos.layout +++ b/src/mainboard/amd/dinar/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd4..4200cfe 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -26,7 +26,7 @@ chip northbridge/amd/agesa/family15/root_complex device domain 0 on subsystemid 0x1022 0x1705 inherit chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex device pci 0.1 off end # CLKCONFIG diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl index 3f6c273..73994f4 100644 --- a/src/mainboard/amd/dinar/dsdt.asl +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -19,65 +19,65 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ - - /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ - /* Memory related values */ - Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - - /* Some global data */ - Name(OSV, Ones) /* Assume nothing */ - Name(GPIC, 0x1) /* Assume PIC */ - - /* - * Processor Object - * - */ - Scope (_PR) { /* define processor scope */ - Processor( - C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ - 0, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C001, /* name space name */ - 1, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C002, /* name space name */ - 2, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } - Processor( - C003, /* name space name */ - 3, /* Unique number for this processor */ - 0x810, /* PBLK system I/O address !hardcoded! */ - 0x06 /* PBLKLEN for boot processor */ - ) { - } + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (_PR) { /* define processor scope */ + Processor( + C000, /* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C001, /* name space name */ + 1, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C002, /* name space name */ + 2, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + C003, /* name space name */ + 3, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } Processor( C004, /* name space name */ 4, /* Unique number for this processor */ @@ -106,1067 +106,1067 @@ DefinitionBlock ( 0x06 /* PBLKLEN for boot processor */ ) { } - } /* End _PR scope */ - - /* PIC IRQ mapping registers, C00h-C01h. */ - OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) - Field(PIRQ, ByteAcc, NoLock, Preserve) { - PIDX, 0x00000008, - PDAT, 0x00000008, /* Offset: 1h */ - } - IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - Offset(0x10), - PIRS, 0x00000008, - Offset(0x13), - HDAD, 0x00000008, - , 0x00000008, - GEC, 0x00000008, - Offset(0x30), - USB1, 0x00000008, - USB2, 0x00000008, - USB3, 0x00000008, - USB4, 0x00000008, - USB5, 0x00000008, - USB6, 0x00000008, - USB7, 0x00000008, - Offset(0x40), - IDE, 0x00000008, - SATA, 0x00000008, - Offset(0x50), - GPP0, 0x00000008, - GPP1, 0x00000008, - GPP2, 0x00000008, - GPP3, 0x00000008 - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ - OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) - Field(PMRG, ByteAcc, NoLock, Preserve) { - PMRI, 0x00000008, - PMRD, 0x00000008, - } - IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { - Offset(0x24), - MMSO,32, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x50), - HPAD,32, - Offset(0x60), - P1EB,16, - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xC8), - ,2, - SPRE,1, - TPDE,1, - Offset(0xF0), - ,3, - RSTU,1 - } - - /* PM1 Event Block - * First word is PM1_Status, Second word is PM1_Enable - */ - OperationRegion(P1E0, SystemIO, P1EB, 0x04) - Field(P1E0, ByteAcc, NoLock, Preserve) { - ,14, - PEWS,1, - WSTA,1, - ,14, - PEWD,1 - } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + }
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), - FLG0, 8 + Offset (0x10), + FLG0, 8 }
- Scope(_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - } - - - #include "acpi/routing.asl" - - Scope(_SB) { - - /* Debug Port registers, 80h. */ - OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) - Field(DBBG, ByteAcc, NoLock, Preserve) { - DBG8, 0x00000008, - } - - Method(_PIC, 1) { - Store(Arg0, GPIC) - If (GPIC) { - Store(0xAA, _SB.DBG8) - _SB.DSPI() - } else { - Store(0xAC, _SB.DBG8) - } - } - - Method(DSPI, 0) { - _SB.GRUA(0x1F) - _SB.GRUB(0x1F) - _SB.GRUC(0x1F) - _SB.GRUD(0x1F) - Store(0x1F, PIRE) - Store(0x1F, PIRF) - Store(0x1F, PIRG) - Store(0x1F, PIRH) - } - - Method(GRUA, 1) { - Store(Arg0, PIRA) - Store(Arg0, HDAD) - Store(Arg0, GEC) - Store(Arg0, GPP0) - Store(Arg0, GPP0) - } - - Method(GRUB, 1) { - Store(Arg0, PIRB) - Store(Arg0, USB2) - Store(Arg0, USB4) - Store(Arg0, USB6) - Store(Arg0, GPP1) - Store(Arg0, IDE) - } - - Method(GRUC, 1) { - Store(Arg0, PIRC) - Store(Arg0, USB1) - Store(Arg0, USB3) - Store(Arg0, USB5) - Store(Arg0, USB7) - Store(Arg0, GPP2) - } - - Method(GRUD, 1) { - Store(Arg0, PIRD) - Store(Arg0, SATA) - Store(Arg0, GPP3) - } - - Name(IRQB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 15 - }}) - - Name(IRQP, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) { - 3, 4, 5, 7, 10, 11, 12, 14, 15 - }}) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - Method(_STA, 0) { - if (PIRA) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - _SB.GRUA(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRA, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - _SB.GRUA(Local0) - } - } - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - Method(_STA, 0) { - if (PIRB) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - _SB.GRUB(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRB, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - _SB.GRUB(Local0) - } - } - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - Method(_STA, 0) { - if (PIRC) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - _SB.GRUC(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRC, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - _SB.GRUC(Local0) - } - } - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Method(_STA, 0) { - if (PIRD) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - _SB.GRUD(0x1F) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRD, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - _SB.GRUD(Local0) - } - } - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - Method(_STA, 0) { - if (PIRE) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRE) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRE, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRE) - } - } - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - Method(_STA, 0) { - if (PIRF) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRF) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRF, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRF) - } - } - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - Method(_STA, 0) { - if (PIRG) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRG) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRG, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRG) - } - } - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - Method(_STA, 0) { - if (PIRH) { - Return(0x0B) - } else { - Return(0x09) - } - } - Method(_DIS ,0) { - Store(0x1F, PIRH) - } - Method(_PRS ,0) { - Return(IRQP) - } - Method(_CRS ,0) { - CreateWordField(IRQB, 1, IRQN) - ShiftLeft(1, PIRH, IRQN) - Return(IRQB) - } - Method(_SRS, 1) { - CreateWordField(Arg0, 1, IRQM) - FindSetRightBit(IRQM, Local0) - Decrement(Local0) - Store(Local0, PIRH) - } - } - } /* End Scope(_SB) */ - - - /* Supported sleep states: */ - Name(_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * _PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(_PTS, 1) { - /* DBGO("\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(_SB.SBRI, 0x13)) { - * Store(0,_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - } /* End Method(_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * _GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(_GTS, 1) { - * DBGO("\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * _BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(_BFS, 1) { - /* DBGO("\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * _WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(_WAK, 1) { - /* DBGO("\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PEWS, PEWS) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - Return(WKST) - } /* End Method(_WAK) */ - - Scope(_GPE) { /* Start Scope GPE */ - } /* End Scope GPE */ - - /* South Bridge */ - Scope(_SB) { /* Start _SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the _SB scope */ - - /* _SB.PCI0 */ - /* Note: Only need HID on Primary Bus */ - Device(PCI0) { - External (TOM1) - External (TOM2) - External (TOM3) - External (TOM4) - Name(_HID, EISAID("PNP0A03")) - Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ - Method(_BBN, 0) { /* Bus number = 0 */ - Return(0) - } - Method(_STA, 0) { - /* DBGO("\_SB\PCI0\_STA\n") */ - Return(0x0B) /* Status is visible */ - } - Method(_PRT,0) { - If(GPIC){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ - } /* end _PRT */ - - /* Describe the Northbridge devices */ - Device(AMRT) { - Name(_ADR, 0x00000000) - } /* end AMRT */ - - /* The internal GFX bridge */ - Device(AGPB) { - Name(_ADR, 0x00010000) - Method(_STA,0) { - Return(0x0F) - } - } /* end AGPB */ - - /* The external GFX bridge */ - Device(PBR2) { - Name(_ADR, 0x00020000) - Method(_PRT,0) { - If(GPIC){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR2 */ - - /* The external GFX bridge */ - Device(PBR3) { - Name(_ADR, 0x00030000) - Method(_PRT,0) { - If(GPIC){ Return(APS3) } /* APIC mode */ - Return (PS3) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR3 */ - - Device(PBR4) { - Name(_ADR, 0x00040000) - Method(_PRT,0) { - If(GPIC){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR4 */ - - Device(PBR5) { - Name(_ADR, 0x00050000) - Method(_PRT,0) { - If(GPIC){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR5 */ - - Device(PBR6) { - Name(_ADR, 0x00060000) - Method(_PRT,0) { - If(GPIC){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR6 */ - - /* The onboard EtherNet chip */ - Device(PBR7) { - Name(_ADR, 0x00070000) - Method(_PRT,0) { - If(GPIC){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ - } /* end PBR7 */ - - Device(PE20) { - Name(_ADR, 0x00150000) - Method(_PRT,0) { - If(GPIC){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ - } /* end _PRT */ - } /* end PE20 */ - Device(PE21) { - Name(_ADR, 0x00150001) - Method(_PRT,0) { - If(GPIC){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ - } /* end _PRT */ - } /* end PE21 */ - Device(PE22) { - Name(_ADR, 0x00150002) - Method(_PRT,0) { - If(GPIC){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ - } /* end _PRT */ - } /* end PE22 */ - Device(PE23) { - Name(_ADR, 0x00150003) - Method(_PRT,0) { - If(GPIC){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ - } /* end _PRT */ - } /* end PE23 */ - - /* Describe the Southbridge devices */ - Device(AZHD) { - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - } - } /* end AZHD */ - - Device(GEC) { - Name(_ADR, 0x00140006) - } /* end GEC */ - - Device(UOH1) { - Name(_ADR, 0x00120000) - } /* end UOH1 */ - - Device(UOH3) { - Name(_ADR, 0x00130000) - } /* end UOH3 */ - - Device(UOH5) { - Name(_ADR, 0x00160000) - } /* end UOH5 */ - - Device(UEH1) { - Name(_ADR, 0x00140005) - } /* end UEH1 */ - - Device(UOH2) { - Name(_ADR, 0x00120002) - } /* end UOH2 */ - - Device(UOH4) { - Name(_ADR, 0x00130002) - } /* end UOH4 */ - - Device(UOH6) { - Name(_ADR, 0x00160002) - } /* end UOH5 */ - - Device(XHC0) { - Name(_ADR, 0x00100000) - } /* end XHC0 */ - - Device(XHC1) { - Name(_ADR, 0x00100001) - } /* end XHC1 */ - - Device(SBUS) { - Name(_ADR, 0x00140000) - } /* end SBUS */ - - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() {8} - IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) - }) - Method(_CRS, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(BUF0) - } - Return(BUF1) - } - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(BUF0, ResourceTemplate() { - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Name(BUF1, ResourceTemplate() { - IRQNoFlags() {0} - IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) - }) - Method(_CRS, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(BUF0) - } - Return(BUF1) - } - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ - /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - - Device (PS2M) { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () { - IRQNoFlags () {12} - }) - Method (_STA, 0) { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { - Return (0x0F) - } Else { - Return (0x00) - } - } - } - - Device (PS2K) { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } - } /* end LIBR */ - - Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" - } /* end STCR */ - - /* Primary (and only) IDE channel */ - Device(IDEC) { - Name(_ADR, 0x00140001) - #include "acpi/ide.asl" - } /* end IDEC */ - - Device(HPET) { - Name(_HID,EISAID("PNP0103")) - Name(CRS, ResourceTemplate() { - IRQNoFlags() {0} - IRQNoFlags() {8} - Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) - }) - Method(_STA, 0) { - If(LAnd(HPAD, 0xFFFFFF00)) { - Return(0x0F) - } - Return(0x0) - } - Method(_CRS, 0) { - CreateDWordField(CRS, 0x0A, HPEB) - Store(HPAD, Local0) - And(Local0, 0xFFFFFFC0, HPEB) - Return(CRS) - } - } /* End Device(_SB.PCI0.HPET) */ - - Name(CRES, ResourceTemplate() { - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) - }) /* End Name(_SB.PCI0.CRES) */ - - Method(_CRS, 0) { - /* DBGO("\_SB\PCI0\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - Store(_SB.PCI0.TOM1, MM1B) - Subtract(PCBA, MM1B, MM1L) - - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_STA, 0x0B) /* sata is invisible */ - } - } /* End _SB scope */ + Scope(_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, _SB.DBG8) + _SB.DSPI() + } else { + Store(0xAC, _SB.DBG8) + } + } + + Method(DSPI, 0) { + _SB.GRUA(0x1F) + _SB.GRUB(0x1F) + _SB.GRUC(0x1F) + _SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + }}) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + _SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + _SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + _SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + _SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + _SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + _SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + _SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + _SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * _PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(_PTS, 1) { + /* DBGO("\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(_SB.SBRI, 0x13)) { + * Store(0,_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * _GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(_GTS, 1) { + * DBGO("\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * _BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(_BFS, 1) { + /* DBGO("\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * _WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(_WAK, 1) { + /* DBGO("\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(_WAK) */ + + Scope(_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(_SB) { /* Start _SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the _SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\_SB\PCI0\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\_SB\PCI0\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End _SB scope */ } /* End of ASL file */ diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c index 713ead9..34923c4 100644 --- a/src/mainboard/amd/dinar/fadt.c +++ b/src/mainboard/amd/dinar/fadt.c @@ -61,7 +61,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pstate_cnt = 0xe2;
/* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index a59bc43..558af68 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -145,7 +145,7 @@ void get_bus_conf(void) }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10;
#if CONFIG_AMD_SB_CIMX diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index 4e60f18..2ec4f31 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,47 +30,47 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #ifndef SB_GPIO_REG01 -#define SB_GPIO_REG01 1 +#define SB_GPIO_REG01 1 #endif
#ifndef SB_GPIO_REG07 -#define SB_GPIO_REG07 7 +#define SB_GPIO_REG07 7 #endif
#ifndef SB_GPIO_REG25 -#define SB_GPIO_REG25 25 +#define SB_GPIO_REG25 25 #endif
#ifndef SB_GPIO_REG26 -#define SB_GPIO_REG26 26 +#define SB_GPIO_REG26 26 #endif
#ifndef SB_GPIO_REG27 -#define SB_GPIO_REG27 27 +#define SB_GPIO_REG27 27 #endif
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ void gpioEarlyInit (void);
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ void @@ -182,32 +182,32 @@ gpioEarlyInit( // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO // // set INTE#/GPIO32 as GPO for PCIE_SW - RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN - RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
// set AD9/GPIO9 as GPI for MXM_PRESENT2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI
// set AD10/GPIO10 as GPI for MXM_PRESENT1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI
// set GNT1#/GPIO44 as GPO for MXM Reset - RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable - RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
// set AD28/GPIO28 as GPI for MXM_PWRGD - RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI
// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) @@ -283,21 +283,21 @@ gpioEarlyInit( // Clock: GPP_CLK3 // // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
// // APU GPP1: WUSB @@ -307,21 +307,21 @@ gpioEarlyInit( // // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW + // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD01/GPIO01 as GPO for MPCIE_RST2# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH - // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// // APU GPP2: WWAN @@ -331,19 +331,19 @@ gpioEarlyInit( // // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW + // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD00/GPIO00 as GPO for MPCIE_RST1# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO - // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN - // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
@@ -355,27 +355,27 @@ gpioEarlyInit( // Clock: GPP_CLK8 // // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO - // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE // To fix glitch issue - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW // // Enable/Disable OnBoard LAN // @@ -399,11 +399,11 @@ gpioEarlyInit( // if (!CONFIG_ONBOARD_1394) { // 1 - DISABLED - // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE - RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH } // else @@ -419,11 +419,11 @@ gpioEarlyInit( // // external USB 3.0 control: // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO26: PCIE_RST#_USB3.0 - // GPIO46: PCIE_USB30_CLKREQ# - // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON - // Clock: GPP_CLK7 - // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + // GPIO26: PCIE_RST#_USB3.0 + // GPIO46: PCIE_USB30_CLKREQ# + // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + // Clock: GPP_CLK7 + // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // disable Onboard NEC USB3.0 controller if (!CONFIG_ONBOARD_USB30) { @@ -438,7 +438,7 @@ gpioEarlyInit( // // BlueTooth control: BT_ON // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO07: BT_ON, 0 - OFF, 1 - ON + // GPIO07: BT_ON, 0 - OFF, 1 - ON // if (!CONFIG_ONBOARD_BLUETOOTH) { //- if (SystemConfiguration.amdBlueTooth == 1) { @@ -449,7 +449,7 @@ gpioEarlyInit( // // WebCam control: // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE - // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // if (!CONFIG_ONBOARD_WEBCAM) { //- if (SystemConfiguration.amdWebCam == 1) { @@ -460,7 +460,7 @@ gpioEarlyInit( // // Travis enable: // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE - // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // if (!CONFIG_ONBOARD_TRAVIS) { //- if (SystemConfiguration.amdTravisCtrl == 0) { @@ -472,9 +472,9 @@ gpioEarlyInit( // Disable Light Sensor if needed // if (CONFIG_ONBOARD_LIGHTSENSOR) { - //- if (SystemConfiguration.amdLightSensor == 1) { + //- if (SystemConfiguration.amdLightSensor == 1) { RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); - //- } + //- } }
} diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h index 1e60157..e062229 100644 --- a/src/mainboard/amd/dinar/gpio.h +++ b/src/mainboard/amd/dinar/gpio.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,7 +30,7 @@ #include <cbtypes.h>
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define Mmio_Address( BaseAddr, Register ) \ @@ -69,1234 +69,1234 @@ )
#define SMIREG_EVENT_ENABLE 0x04 -#define SMIREG_SCITRIG 0x08 -#define SMIREG_SCILEVEL 0x0C -#define SMIREG_SMISCIEN 0x14 -#define SMIREG_SCIS0EN 0x20 -#define SMIREG_SCIMAP0 0x40 -#define SMIREG_SCIMAP1 0x44 -#define SMIREG_SCIMAP2 0x48 -#define SMIREG_SCIMAP3 0x4C -#define SMIREG_SCIMAP4 0x50 -#define SMIREG_SCIMAP5 0x54 -#define SMIREG_SCIMAP6 0x58 -#define SMIREG_SCIMAP7 0x5C -#define SMIREG_SCIMAP8 0x60 -#define SMIREG_SCIMAP9 0x64 -#define SMIREG_SCIMAP10 0x68 -#define SMIREG_SCIMAP11 0x6C -#define SMIREG_SCIMAP12 0x70 -#define SMIREG_SCIMAP13 0x74 -#define SMIREG_SCIMAP14 0x78 -#define SMIREG_SCIMAP15 0x7C -#define SMIREG_SMITRIG 0x98 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 #define SMIREG_SMICONTROL0 0xA0 #define SMIREG_SMICONTROL1 0xA4
-#define FUNCTION0 0 -#define FUNCTION1 1 -#define FUNCTION2 2 -#define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7
// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE -// 1:BATTERY IS FINE(DEFAULT) -// 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 -// 00 - REVA -// 01 - REVB -// 10 - REVC -// 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. -// 0:USB3.0 I/F in Express CARD -// 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) -// 1:ENABLE; 0:DISABLE +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +// 1:BATTERY IS FINE(DEFAULT) +// 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 +// 00 - REVA +// 01 - REVB +// 10 - REVC +// 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. +// 0:USB3.0 I/F in Express CARD +// 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) +// 1:ENABLE; 0:DISABLE // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# -#define GPIO_68_SELECT FUNCTION0+NonGpio -#define GPIO_69_SELECT FUNCTION0+NonGpio -#define GPIO_70_SELECT FUNCTION0+NonGpio -#define GPIO_71_SELECT FUNCTION0+NonGpio -#define GPIO_72_SELECT FUNCTION0+NonGpio -#define GPIO_73_SELECT FUNCTION0+NonGpio -#define GPIO_74_SELECT FUNCTION0+NonGpio -#define GPIO_75_SELECT FUNCTION0+NonGpio -#define GPIO_76_SELECT FUNCTION0+NonGpio -#define GPIO_77_SELECT FUNCTION0+NonGpio -#define GPIO_78_SELECT FUNCTION0+NonGpio -#define GPIO_79_SELECT FUNCTION0+NonGpio -#define GPIO_80_SELECT FUNCTION0+NonGpio -#define GPIO_81_SELECT FUNCTION0+NonGpio -#define GPIO_82_SELECT FUNCTION0+NonGpio -#define GPIO_83_SELECT FUNCTION0+NonGpio -#define GPIO_84_SELECT FUNCTION0+NonGpio -#define GPIO_85_SELECT FUNCTION0+NonGpio -#define GPIO_86_SELECT FUNCTION0+NonGpio -#define GPIO_87_SELECT FUNCTION0+NonGpio -#define GPIO_88_SELECT FUNCTION0+NonGpio -#define GPIO_89_SELECT FUNCTION0+NonGpio -#define GPIO_90_SELECT FUNCTION0+NonGpio -#define GPIO_91_SELECT FUNCTION0+NonGpio -#define GPIO_92_SELECT FUNCTION0+NonGpio -#define GPIO_93_SELECT FUNCTION0+NonGpio -#define GPIO_94_SELECT FUNCTION0+NonGpio -#define GPIO_95_SELECT FUNCTION0+NonGpio +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio // GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, // special pin difination for SB700 VGA OUTPUT, high active, // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, // plus judge GPIO40 and GPIO19 level,low is assert. -// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) -// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, +// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) +// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI -#define GPIO_120_SELECT FUNCTION0+NonGpio -#define GPIO_121_SELECT FUNCTION0+NonGpio -#define GPIO_122_SELECT FUNCTION0+NonGpio -#define GPIO_123_SELECT FUNCTION0+NonGpio -#define GPIO_124_SELECT FUNCTION0+NonGpio -#define GPIO_125_SELECT FUNCTION0+NonGpio -#define GPIO_126_SELECT FUNCTION0+NonGpio -#define GPIO_127_SELECT FUNCTION0+NonGpio -#define GPIO_128_SELECT FUNCTION0+NonGpio -#define GPIO_129_SELECT FUNCTION0+NonGpio -#define GPIO_130_SELECT FUNCTION0+NonGpio -#define GPIO_131_SELECT FUNCTION0+NonGpio -#define GPIO_132_SELECT FUNCTION0+NonGpio -#define GPIO_133_SELECT FUNCTION0+NonGpio -#define GPIO_134_SELECT FUNCTION0+NonGpio -#define GPIO_135_SELECT FUNCTION0+NonGpio -#define GPIO_136_SELECT FUNCTION0+NonGpio -#define GPIO_137_SELECT FUNCTION0+NonGpio -#define GPIO_138_SELECT FUNCTION0+NonGpio -#define GPIO_139_SELECT FUNCTION0+NonGpio -#define GPIO_140_SELECT FUNCTION0+NonGpio -#define GPIO_141_SELECT FUNCTION0+NonGpio -#define GPIO_142_SELECT FUNCTION0+NonGpio -#define GPIO_143_SELECT FUNCTION0+NonGpio -#define GPIO_144_SELECT FUNCTION0+NonGpio -#define GPIO_145_SELECT FUNCTION0+NonGpio -#define GPIO_146_SELECT FUNCTION0+NonGpio -#define GPIO_147_SELECT FUNCTION0+NonGpio -#define GPIO_148_SELECT FUNCTION0+NonGpio -#define GPIO_149_SELECT FUNCTION0+NonGpio -#define GPIO_150_SELECT FUNCTION0+NonGpio -#define GPIO_151_SELECT FUNCTION0+NonGpio -#define GPIO_152_SELECT FUNCTION0+NonGpio -#define GPIO_153_SELECT FUNCTION0+NonGpio -#define GPIO_154_SELECT FUNCTION0+NonGpio -#define GPIO_155_SELECT FUNCTION0+NonGpio -#define GPIO_156_SELECT FUNCTION0+NonGpio -#define GPIO_157_SELECT FUNCTION0+NonGpio -#define GPIO_158_SELECT FUNCTION0+NonGpio -#define GPIO_159_SELECT FUNCTION0+NonGpio -#define GPIO_160_SELECT FUNCTION0+NonGpio +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio
// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
#define TYPE_GPI (1<<5) #define TYPE_GPO (0<<5)
-#define GPIO_00_TYPE TYPE_GPO -#define GPIO_01_TYPE TYPE_GPO -#define GPIO_02_TYPE TYPE_GPO -#define GPIO_03_TYPE TYPE_GPO -#define GPIO_04_TYPE TYPE_GPO -#define GPIO_05_TYPE TYPE_GPO -#define GPIO_06_TYPE TYPE_GPO -#define GPIO_07_TYPE TYPE_GPO -#define GPIO_08_TYPE TYPE_GPO -#define GPIO_09_TYPE TYPE_GPI -#define GPIO_10_TYPE TYPE_GPI -#define GPIO_11_TYPE TYPE_GPO -#define GPIO_12_TYPE TYPE_GPO -#define GPIO_13_TYPE TYPE_GPO -#define GPIO_14_TYPE TYPE_GPO -#define GPIO_15_TYPE TYPE_GPO -#define GPIO_16_TYPE TYPE_GPO -#define GPIO_17_TYPE TYPE_GPO -#define GPIO_18_TYPE TYPE_GPO -#define GPIO_19_TYPE TYPE_GPO -#define GPIO_20_TYPE TYPE_GPO -#define GPIO_21_TYPE TYPE_GPO -#define GPIO_22_TYPE TYPE_GPO -#define GPIO_23_TYPE TYPE_GPO -#define GPIO_24_TYPE TYPE_GPO -#define GPIO_25_TYPE TYPE_GPO -#define GPIO_26_TYPE TYPE_GPO -#define GPIO_27_TYPE TYPE_GPO -#define GPIO_28_TYPE TYPE_GPI -#define GPIO_29_TYPE TYPE_GPO -#define GPIO_30_TYPE TYPE_GPI -#define GPIO_31_TYPE TYPE_GPI -#define GPIO_32_TYPE TYPE_GPO -#define GPIO_33_TYPE TYPE_GPI -#define GPIO_34_TYPE TYPE_GPO -#define GPIO_35_TYPE TYPE_GPO -#define GPIO_36_TYPE TYPE_GPO -#define GPIO_37_TYPE TYPE_GPO -#define GPIO_38_TYPE TYPE_GPO -#define GPIO_39_TYPE TYPE_GPO -#define GPIO_40_TYPE TYPE_GPO -#define GPIO_41_TYPE TYPE_GPI -#define GPIO_42_TYPE TYPE_GPI -#define GPIO_43_TYPE TYPE_GPO -#define GPIO_44_TYPE TYPE_GPO -#define GPIO_45_TYPE TYPE_GPO -#define GPIO_46_TYPE TYPE_GPI -#define GPIO_47_TYPE TYPE_GPO -#define GPIO_48_TYPE TYPE_GPO -#define GPIO_49_TYPE TYPE_GPO -#define GPIO_50_TYPE TYPE_GPO -#define GPIO_51_TYPE TYPE_GPO -#define GPIO_52_TYPE TYPE_GPO -#define GPIO_53_TYPE TYPE_GPO -#define GPIO_54_TYPE TYPE_GPO -#define GPIO_55_TYPE TYPE_GPO -#define GPIO_56_TYPE TYPE_GPI -#define GPIO_57_TYPE TYPE_GPO -#define GPIO_58_TYPE TYPE_GPO -#define GPIO_59_TYPE TYPE_GPO -#define GPIO_60_TYPE TYPE_GPI -#define GPIO_61_TYPE TYPE_GPI -#define GPIO_62_TYPE TYPE_GPI -#define GPIO_63_TYPE TYPE_GPI -#define GPIO_64_TYPE TYPE_GPI -#define GPIO_65_TYPE TYPE_GPI -#define GPIO_66_TYPE TYPE_GPO -#define GPIO_67_TYPE TYPE_GPO -#define GPIO_68_TYPE TYPE_GPO -#define GPIO_69_TYPE TYPE_GPO -#define GPIO_70_TYPE TYPE_GPO -#define GPIO_71_TYPE TYPE_GPO -#define GPIO_72_TYPE TYPE_GPO -#define GPIO_73_TYPE TYPE_GPO -#define GPIO_74_TYPE TYPE_GPO -#define GPIO_75_TYPE TYPE_GPO -#define GPIO_76_TYPE TYPE_GPO -#define GPIO_77_TYPE TYPE_GPO -#define GPIO_78_TYPE TYPE_GPO -#define GPIO_79_TYPE TYPE_GPO -#define GPIO_80_TYPE TYPE_GPO -#define GPIO_81_TYPE TYPE_GPO -#define GPIO_82_TYPE TYPE_GPO -#define GPIO_83_TYPE TYPE_GPO -#define GPIO_84_TYPE TYPE_GPO -#define GPIO_85_TYPE TYPE_GPO -#define GPIO_86_TYPE TYPE_GPO -#define GPIO_87_TYPE TYPE_GPO -#define GPIO_88_TYPE TYPE_GPO -#define GPIO_89_TYPE TYPE_GPO -#define GPIO_90_TYPE TYPE_GPO -#define GPIO_91_TYPE TYPE_GPO -#define GPIO_92_TYPE TYPE_GPO -#define GPIO_93_TYPE TYPE_GPO -#define GPIO_94_TYPE TYPE_GPO -#define GPIO_95_TYPE TYPE_GPO +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO
// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 -#define GPIO_96_TYPE TYPE_GPI -#define GPIO_97_TYPE TYPE_GPI -#define GPIO_98_TYPE TYPE_GPI -#define GPIO_99_TYPE TYPE_GPI -#define GPIO_100_TYPE TYPE_GPI -#define GPIO_101_TYPE TYPE_GPI -#define GPIO_102_TYPE TYPE_GPO -#define GPIO_103_TYPE TYPE_GPO -#define GPIO_104_TYPE TYPE_GPI -#define GPIO_105_TYPE TYPE_GPI -#define GPIO_106_TYPE TYPE_GPO -#define GPIO_107_TYPE TYPE_GPI -#define GPIO_108_TYPE TYPE_GPI -#define GPIO_109_TYPE TYPE_GPI -#define GPIO_110_TYPE TYPE_GPI -#define GPIO_111_TYPE TYPE_GPI -#define GPIO_112_TYPE TYPE_GPI -#define GPIO_113_TYPE TYPE_GPI -#define GPIO_114_TYPE TYPE_GPO -#define GPIO_115_TYPE TYPE_GPI -#define GPIO_116_TYPE TYPE_GPI -#define GPIO_117_TYPE TYPE_GPI -#define GPIO_118_TYPE TYPE_GPI -#define GPIO_119_TYPE TYPE_GPI +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI
-#define GPIO_120_TYPE TYPE_GPO -#define GPIO_121_TYPE TYPE_GPO -#define GPIO_122_TYPE TYPE_GPO -#define GPIO_123_TYPE TYPE_GPO -#define GPIO_124_TYPE TYPE_GPO -#define GPIO_125_TYPE TYPE_GPO -#define GPIO_126_TYPE TYPE_GPO -#define GPIO_127_TYPE TYPE_GPO -#define GPIO_128_TYPE TYPE_GPO -#define GPIO_129_TYPE TYPE_GPO -#define GPIO_130_TYPE TYPE_GPO -#define GPIO_131_TYPE TYPE_GPO -#define GPIO_132_TYPE TYPE_GPO -#define GPIO_133_TYPE TYPE_GPO -#define GPIO_134_TYPE TYPE_GPO -#define GPIO_135_TYPE TYPE_GPO -#define GPIO_136_TYPE TYPE_GPO -#define GPIO_137_TYPE TYPE_GPO -#define GPIO_138_TYPE TYPE_GPO -#define GPIO_139_TYPE TYPE_GPO -#define GPIO_140_TYPE TYPE_GPO -#define GPIO_141_TYPE TYPE_GPO -#define GPIO_142_TYPE TYPE_GPO -#define GPIO_143_TYPE TYPE_GPO -#define GPIO_144_TYPE TYPE_GPO -#define GPIO_145_TYPE TYPE_GPO -#define GPIO_146_TYPE TYPE_GPO -#define GPIO_147_TYPE TYPE_GPO -#define GPIO_148_TYPE TYPE_GPO -#define GPIO_149_TYPE TYPE_GPO -#define GPIO_150_TYPE TYPE_GPO -#define GPIO_151_TYPE TYPE_GPO -#define GPIO_152_TYPE TYPE_GPO -#define GPIO_153_TYPE TYPE_GPO -#define GPIO_154_TYPE TYPE_GPO -#define GPIO_155_TYPE TYPE_GPO -#define GPIO_156_TYPE TYPE_GPO -#define GPIO_157_TYPE TYPE_GPO -#define GPIO_158_TYPE TYPE_GPO -#define GPIO_159_TYPE TYPE_GPO -#define GPIO_160_TYPE TYPE_GPO -#define GPIO_161_TYPE TYPE_GPO -#define GPIO_162_TYPE TYPE_GPO -#define GPIO_163_TYPE TYPE_GPO -#define GPIO_164_TYPE TYPE_GPI -#define GPIO_165_TYPE TYPE_GPO -#define GPIO_166_TYPE TYPE_GPI -#define GPIO_167_TYPE TYPE_GPI -#define GPIO_168_TYPE TYPE_GPI -#define GPIO_169_TYPE TYPE_GPI -#define GPIO_170_TYPE TYPE_GPO -#define GPIO_171_TYPE TYPE_GPI -#define GPIO_172_TYPE TYPE_GPO -#define GPIO_173_TYPE TYPE_GPI -#define GPIO_174_TYPE TYPE_GPI -#define GPIO_175_TYPE TYPE_GPO -#define GPIO_176_TYPE TYPE_GPO -#define GPIO_177_TYPE TYPE_GPO -#define GPIO_178_TYPE TYPE_GPO -#define GPIO_179_TYPE TYPE_GPO -#define GPIO_180_TYPE TYPE_GPO -#define GPIO_181_TYPE TYPE_GPO -#define GPIO_182_TYPE TYPE_GPO -#define GPIO_183_TYPE TYPE_GPO -#define GPIO_184_TYPE TYPE_GPI -#define GPIO_185_TYPE TYPE_GPO -#define GPIO_186_TYPE TYPE_GPO -#define GPIO_187_TYPE TYPE_GPO -#define GPIO_188_TYPE TYPE_GPO -#define GPIO_189_TYPE TYPE_GPI -#define GPIO_190_TYPE TYPE_GPI -#define GPIO_191_TYPE TYPE_GPO -#define GPIO_192_TYPE TYPE_GPO -#define GPIO_193_TYPE TYPE_GPO -#define GPIO_194_TYPE TYPE_GPO -#define GPIO_195_TYPE TYPE_GPO -#define GPIO_196_TYPE TYPE_GPO -#define GPIO_197_TYPE TYPE_GPO -#define GPIO_198_TYPE TYPE_GPO -#define GPIO_199_TYPE TYPE_GPI -#define GPIO_200_TYPE TYPE_GPO -#define GPIO_201_TYPE TYPE_GPI -#define GPIO_202_TYPE TYPE_GPI -#define GPIO_203_TYPE TYPE_GPI -#define GPIO_204_TYPE TYPE_GPI -#define GPIO_205_TYPE TYPE_GPI -#define GPIO_206_TYPE TYPE_GPI -#define GPIO_207_TYPE TYPE_GPI -#define GPIO_208_TYPE TYPE_GPI -#define GPIO_209_TYPE TYPE_GPO -#define GPIO_210_TYPE TYPE_GPO -#define GPIO_211_TYPE TYPE_GPO -#define GPIO_212_TYPE TYPE_GPO -#define GPIO_213_TYPE TYPE_GPO -#define GPIO_214_TYPE TYPE_GPO -#define GPIO_215_TYPE TYPE_GPO -#define GPIO_216_TYPE TYPE_GPO -#define GPIO_217_TYPE TYPE_GPO -#define GPIO_218_TYPE TYPE_GPO -#define GPIO_219_TYPE TYPE_GPO -#define GPIO_220_TYPE TYPE_GPO -#define GPIO_221_TYPE TYPE_GPO -#define GPIO_222_TYPE TYPE_GPO -#define GPIO_223_TYPE TYPE_GPO -#define GPIO_224_TYPE TYPE_GPO -#define GPIO_225_TYPE TYPE_GPO -#define GPIO_226_TYPE TYPE_GPO -#define GPIO_227_TYPE TYPE_GPO -#define GPIO_228_TYPE TYPE_GPO -#define GPIO_229_TYPE TYPE_GPO +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO
-#define GPO_LOW (0<<6) -#define GPO_HI (1<<6) +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6)
-#define GPO_00_LEVEL GPO_HI -#define GPO_01_LEVEL GPO_HI -#define GPO_02_LEVEL GPO_HI -#define GPO_03_LEVEL GPO_HI -#define GPO_04_LEVEL GPO_HI -#define GPO_05_LEVEL GPO_HI -#define GPO_06_LEVEL GPO_HI -#define GPO_07_LEVEL GPO_HI -#define GPO_08_LEVEL GPO_HI -#define GPO_09_LEVEL GPO_LOW -#define GPO_10_LEVEL GPO_LOW -#define GPO_11_LEVEL GPO_HI -#define GPO_12_LEVEL GPO_HI -#define GPO_13_LEVEL GPO_HI -#define GPO_14_LEVEL GPO_HI -#define GPO_15_LEVEL GPO_HI -#define GPO_16_LEVEL GPO_HI -#define GPO_17_LEVEL GPO_HI -#define GPO_18_LEVEL GPO_HI -#define GPO_19_LEVEL GPO_LOW -#define GPO_20_LEVEL GPO_LOW -#define GPO_21_LEVEL GPO_LOW -#define GPO_22_LEVEL GPO_HI -#define GPO_23_LEVEL GPO_HI -#define GPO_24_LEVEL GPO_HI -#define GPO_25_LEVEL GPO_HI -#define GPO_26_LEVEL GPO_HI -#define GPO_27_LEVEL GPO_HI -#define GPO_28_LEVEL GPO_LOW -#define GPO_29_LEVEL GPO_HI -#define GPO_30_LEVEL GPO_LOW -#define GPO_31_LEVEL GPO_LOW -#define GPO_32_LEVEL GPO_HI -#define GPO_33_LEVEL GPO_LOW -#define GPO_34_LEVEL GPO_LOW -#define GPO_35_LEVEL GPO_LOW -#define GPO_36_LEVEL GPO_LOW -#define GPO_37_LEVEL GPO_HI -#define GPO_38_LEVEL GPO_HI -#define GPO_39_LEVEL GPO_HI -#define GPO_40_LEVEL GPO_LOW -#define GPO_41_LEVEL GPO_LOW -#define GPO_42_LEVEL GPO_LOW -#define GPO_43_LEVEL GPO_LOW -#define GPO_44_LEVEL GPO_HI -#define GPO_45_LEVEL GPO_HI -#define GPO_46_LEVEL GPO_LOW -#define GPO_47_LEVEL GPO_LOW -#define GPO_48_LEVEL GPO_LOW -#define GPO_49_LEVEL GPO_HI -#define GPO_50_LEVEL GPO_HI -#define GPO_51_LEVEL GPO_LOW -#define GPO_52_LEVEL GPO_HI -#define GPO_53_LEVEL GPO_HI -#define GPO_54_LEVEL GPO_LOW -#define GPO_55_LEVEL GPO_LOW -#define GPO_56_LEVEL GPO_LOW -#define GPO_57_LEVEL GPO_HI -#define GPO_58_LEVEL GPO_HI -#define GPO_59_LEVEL GPO_HI -#define GPO_60_LEVEL GPO_LOW -#define GPO_61_LEVEL GPO_LOW -#define GPO_62_LEVEL GPO_LOW -#define GPO_63_LEVEL GPO_LOW -#define GPO_64_LEVEL GPO_LOW -#define GPO_65_LEVEL GPO_LOW -#define GPO_66_LEVEL GPO_LOW -#define GPO_67_LEVEL GPO_LOW -#define GPO_68_LEVEL GPO_LOW -#define GPO_69_LEVEL GPO_LOW -#define GPO_70_LEVEL GPO_LOW -#define GPO_71_LEVEL GPO_LOW -#define GPO_72_LEVEL GPO_LOW -#define GPO_73_LEVEL GPO_LOW -#define GPO_74_LEVEL GPO_LOW -#define GPO_75_LEVEL GPO_LOW -#define GPO_76_LEVEL GPO_LOW -#define GPO_77_LEVEL GPO_LOW -#define GPO_78_LEVEL GPO_LOW -#define GPO_79_LEVEL GPO_LOW -#define GPO_80_LEVEL GPO_LOW -#define GPO_81_LEVEL GPO_LOW -#define GPO_82_LEVEL GPO_LOW -#define GPO_83_LEVEL GPO_LOW -#define GPO_84_LEVEL GPO_LOW -#define GPO_85_LEVEL GPO_LOW -#define GPO_86_LEVEL GPO_LOW -#define GPO_87_LEVEL GPO_LOW -#define GPO_88_LEVEL GPO_LOW -#define GPO_89_LEVEL GPO_LOW -#define GPO_90_LEVEL GPO_LOW -#define GPO_91_LEVEL GPO_LOW -#define GPO_92_LEVEL GPO_LOW -#define GPO_93_LEVEL GPO_LOW -#define GPO_94_LEVEL GPO_LOW -#define GPO_95_LEVEL GPO_LOW -#define GPO_96_LEVEL GPO_LOW -#define GPO_97_LEVEL GPO_LOW -#define GPO_98_LEVEL GPO_LOW -#define GPO_99_LEVEL GPO_LOW -#define GPO_100_LEVEL GPO_LOW -#define GPO_101_LEVEL GPO_LOW -#define GPO_102_LEVEL GPO_LOW -#define GPO_103_LEVEL GPO_LOW -#define GPO_104_LEVEL GPO_LOW -#define GPO_105_LEVEL GPO_LOW -#define GPO_106_LEVEL GPO_LOW -#define GPO_107_LEVEL GPO_LOW -#define GPO_108_LEVEL GPO_HI -#define GPO_109_LEVEL GPO_LOW -#define GPO_110_LEVEL GPO_HI -#define GPO_111_LEVEL GPO_HI -#define GPO_112_LEVEL GPO_HI -#define GPO_113_LEVEL GPO_LOW -#define GPO_114_LEVEL GPO_LOW -#define GPO_115_LEVEL GPO_LOW -#define GPO_116_LEVEL GPO_LOW -#define GPO_117_LEVEL GPO_LOW -#define GPO_118_LEVEL GPO_LOW -#define GPO_119_LEVEL GPO_LOW -#define GPO_120_LEVEL GPO_LOW -#define GPO_121_LEVEL GPO_LOW -#define GPO_122_LEVEL GPO_LOW -#define GPO_123_LEVEL GPO_LOW -#define GPO_124_LEVEL GPO_LOW -#define GPO_125_LEVEL GPO_LOW -#define GPO_126_LEVEL GPO_LOW -#define GPO_127_LEVEL GPO_LOW -#define GPO_128_LEVEL GPO_LOW -#define GPO_129_LEVEL GPO_LOW -#define GPO_130_LEVEL GPO_LOW -#define GPO_131_LEVEL GPO_LOW -#define GPO_132_LEVEL GPO_LOW -#define GPO_133_LEVEL GPO_LOW -#define GPO_134_LEVEL GPO_LOW -#define GPO_135_LEVEL GPO_LOW -#define GPO_136_LEVEL GPO_LOW -#define GPO_137_LEVEL GPO_LOW -#define GPO_138_LEVEL GPO_LOW -#define GPO_139_LEVEL GPO_LOW -#define GPO_140_LEVEL GPO_LOW -#define GPO_141_LEVEL GPO_LOW -#define GPO_142_LEVEL GPO_LOW -#define GPO_143_LEVEL GPO_LOW -#define GPO_144_LEVEL GPO_LOW -#define GPO_145_LEVEL GPO_LOW -#define GPO_146_LEVEL GPO_LOW -#define GPO_147_LEVEL GPO_LOW -#define GPO_148_LEVEL GPO_LOW -#define GPO_149_LEVEL GPO_LOW -#define GPO_150_LEVEL GPO_LOW -#define GPO_151_LEVEL GPO_LOW -#define GPO_152_LEVEL GPO_LOW -#define GPO_153_LEVEL GPO_LOW -#define GPO_154_LEVEL GPO_LOW -#define GPO_155_LEVEL GPO_LOW -#define GPO_156_LEVEL GPO_LOW -#define GPO_157_LEVEL GPO_LOW -#define GPO_158_LEVEL GPO_LOW -#define GPO_159_LEVEL GPO_LOW -#define GPO_160_LEVEL GPO_LOW -#define GPO_161_LEVEL GPO_LOW -#define GPO_162_LEVEL GPO_LOW -#define GPO_163_LEVEL GPO_LOW -#define GPO_164_LEVEL GPO_LOW -#define GPO_165_LEVEL GPO_LOW -#define GPO_166_LEVEL GPO_LOW -#define GPO_167_LEVEL GPO_LOW -#define GPO_168_LEVEL GPO_LOW -#define GPO_169_LEVEL GPO_LOW -#define GPO_170_LEVEL GPO_HI -#define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -#define GPO_173_LEVEL GPO_LOW -#define GPO_174_LEVEL GPO_LOW -#define GPO_175_LEVEL GPO_LOW -#define GPO_176_LEVEL GPO_LOW -#define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU -#define GPO_179_LEVEL GPO_HI -#define GPO_180_LEVEL GPO_HI -#define GPO_181_LEVEL GPO_LOW -#define GPO_182_LEVEL GPO_HI -#define GPO_183_LEVEL GPO_LOW -#define GPO_184_LEVEL GPO_LOW -#define GPO_185_LEVEL GPO_LOW -#define GPO_186_LEVEL GPO_LOW -#define GPO_187_LEVEL GPO_LOW -#define GPO_188_LEVEL GPO_LOW -#define GPO_189_LEVEL GPO_LOW -#define GPO_190_LEVEL GPO_LOW -#define GPO_191_LEVEL GPO_LOW -#define GPO_192_LEVEL GPO_LOW -#define GPO_193_LEVEL GPO_LOW -#define GPO_194_LEVEL GPO_LOW -#define GPO_195_LEVEL GPO_LOW -#define GPO_196_LEVEL GPO_LOW -#define GPO_197_LEVEL GPO_LOW -#define GPO_198_LEVEL GPO_LOW -#define GPO_199_LEVEL GPO_LOW -#define GPO_200_LEVEL GPO_HI -#define GPO_201_LEVEL GPO_LOW -#define GPO_202_LEVEL GPO_LOW -#define GPO_203_LEVEL GPO_LOW -#define GPO_204_LEVEL GPO_LOW -#define GPO_205_LEVEL GPO_LOW -#define GPO_206_LEVEL GPO_LOW -#define GPO_207_LEVEL GPO_LOW -#define GPO_208_LEVEL GPO_LOW -#define GPO_209_LEVEL GPO_LOW -#define GPO_210_LEVEL GPO_LOW -#define GPO_211_LEVEL GPO_LOW -#define GPO_212_LEVEL GPO_LOW -#define GPO_213_LEVEL GPO_LOW -#define GPO_214_LEVEL GPO_LOW -#define GPO_215_LEVEL GPO_LOW -#define GPO_216_LEVEL GPO_LOW -#define GPO_217_LEVEL GPO_LOW -#define GPO_218_LEVEL GPO_LOW -#define GPO_219_LEVEL GPO_LOW -#define GPO_220_LEVEL GPO_LOW -#define GPO_221_LEVEL GPO_LOW -#define GPO_222_LEVEL GPO_LOW -#define GPO_223_LEVEL GPO_LOW -#define GPO_224_LEVEL GPO_LOW -#define GPO_225_LEVEL GPO_LOW -#define GPO_226_LEVEL GPO_LOW -#define GPO_227_LEVEL GPO_LOW -#define GPO_228_LEVEL GPO_LOW -#define GPO_229_LEVEL GPO_LOW +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW
-#define GPIO_NONSTICKY (0<<2) -#define GPIO_STICKY (1<<2) +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2)
-#define GPIO_00_STICKY GPIO_NONSTICKY -#define GPIO_01_STICKY GPIO_NONSTICKY -#define GPIO_02_STICKY GPIO_NONSTICKY -#define GPIO_03_STICKY GPIO_NONSTICKY -#define GPIO_04_STICKY GPIO_NONSTICKY -#define GPIO_05_STICKY GPIO_NONSTICKY -#define GPIO_06_STICKY GPIO_NONSTICKY -#define GPIO_07_STICKY GPIO_NONSTICKY -#define GPIO_08_STICKY GPIO_NONSTICKY -#define GPIO_09_STICKY GPIO_NONSTICKY -#define GPIO_10_STICKY GPIO_NONSTICKY -#define GPIO_11_STICKY GPIO_NONSTICKY -#define GPIO_12_STICKY GPIO_NONSTICKY -#define GPIO_13_STICKY GPIO_NONSTICKY -#define GPIO_14_STICKY GPIO_NONSTICKY -#define GPIO_15_STICKY GPIO_NONSTICKY -#define GPIO_16_STICKY GPIO_NONSTICKY -#define GPIO_17_STICKY GPIO_STICKY -#define GPIO_18_STICKY GPIO_NONSTICKY -#define GPIO_19_STICKY GPIO_NONSTICKY -#define GPIO_20_STICKY GPIO_NONSTICKY -#define GPIO_21_STICKY GPIO_NONSTICKY -#define GPIO_22_STICKY GPIO_NONSTICKY -#define GPIO_23_STICKY GPIO_NONSTICKY -#define GPIO_24_STICKY GPIO_NONSTICKY -#define GPIO_25_STICKY GPIO_NONSTICKY -#define GPIO_26_STICKY GPIO_NONSTICKY -#define GPIO_27_STICKY GPIO_NONSTICKY -#define GPIO_28_STICKY GPIO_NONSTICKY -#define GPIO_29_STICKY GPIO_NONSTICKY -#define GPIO_30_STICKY GPIO_NONSTICKY -#define GPIO_31_STICKY GPIO_NONSTICKY -#define GPIO_32_STICKY GPIO_NONSTICKY -#define GPIO_33_STICKY GPIO_NONSTICKY -#define GPIO_34_STICKY GPIO_NONSTICKY -#define GPIO_35_STICKY GPIO_NONSTICKY -#define GPIO_36_STICKY GPIO_NONSTICKY -#define GPIO_37_STICKY GPIO_NONSTICKY -#define GPIO_38_STICKY GPIO_NONSTICKY -#define GPIO_39_STICKY GPIO_NONSTICKY -#define GPIO_40_STICKY GPIO_NONSTICKY -#define GPIO_41_STICKY GPIO_NONSTICKY -#define GPIO_42_STICKY GPIO_NONSTICKY -#define GPIO_43_STICKY GPIO_NONSTICKY -#define GPIO_44_STICKY GPIO_NONSTICKY -#define GPIO_45_STICKY GPIO_NONSTICKY -#define GPIO_46_STICKY GPIO_NONSTICKY -#define GPIO_47_STICKY GPIO_NONSTICKY -#define GPIO_48_STICKY GPIO_NONSTICKY -#define GPIO_49_STICKY GPIO_NONSTICKY -#define GPIO_50_STICKY GPIO_NONSTICKY -#define GPIO_51_STICKY GPIO_NONSTICKY -#define GPIO_52_STICKY GPIO_NONSTICKY -#define GPIO_53_STICKY GPIO_NONSTICKY -#define GPIO_54_STICKY GPIO_NONSTICKY -#define GPIO_55_STICKY GPIO_NONSTICKY -#define GPIO_56_STICKY GPIO_NONSTICKY -#define GPIO_57_STICKY GPIO_NONSTICKY -#define GPIO_58_STICKY GPIO_NONSTICKY -#define GPIO_59_STICKY GPIO_NONSTICKY -#define GPIO_60_STICKY GPIO_NONSTICKY -#define GPIO_61_STICKY GPIO_NONSTICKY -#define GPIO_62_STICKY GPIO_NONSTICKY -#define GPIO_63_STICKY GPIO_NONSTICKY -#define GPIO_64_STICKY GPIO_NONSTICKY -#define GPIO_65_STICKY GPIO_NONSTICKY -#define GPIO_66_STICKY GPIO_NONSTICKY -#define GPIO_67_STICKY GPIO_NONSTICKY -#define GPIO_68_STICKY GPIO_NONSTICKY -#define GPIO_69_STICKY GPIO_NONSTICKY -#define GPIO_70_STICKY GPIO_NONSTICKY -#define GPIO_71_STICKY GPIO_NONSTICKY -#define GPIO_72_STICKY GPIO_NONSTICKY -#define GPIO_73_STICKY GPIO_NONSTICKY -#define GPIO_74_STICKY GPIO_NONSTICKY -#define GPIO_75_STICKY GPIO_NONSTICKY -#define GPIO_76_STICKY GPIO_NONSTICKY -#define GPIO_77_STICKY GPIO_NONSTICKY -#define GPIO_78_STICKY GPIO_NONSTICKY -#define GPIO_79_STICKY GPIO_NONSTICKY -#define GPIO_80_STICKY GPIO_NONSTICKY -#define GPIO_81_STICKY GPIO_NONSTICKY -#define GPIO_82_STICKY GPIO_NONSTICKY -#define GPIO_83_STICKY GPIO_NONSTICKY -#define GPIO_84_STICKY GPIO_NONSTICKY -#define GPIO_85_STICKY GPIO_NONSTICKY -#define GPIO_86_STICKY GPIO_NONSTICKY -#define GPIO_87_STICKY GPIO_NONSTICKY -#define GPIO_88_STICKY GPIO_NONSTICKY -#define GPIO_89_STICKY GPIO_NONSTICKY -#define GPIO_90_STICKY GPIO_NONSTICKY -#define GPIO_91_STICKY GPIO_NONSTICKY -#define GPIO_92_STICKY GPIO_NONSTICKY -#define GPIO_93_STICKY GPIO_NONSTICKY -#define GPIO_94_STICKY GPIO_NONSTICKY -#define GPIO_95_STICKY GPIO_NONSTICKY -#define GPIO_96_STICKY GPIO_NONSTICKY -#define GPIO_97_STICKY GPIO_NONSTICKY -#define GPIO_98_STICKY GPIO_NONSTICKY -#define GPIO_99_STICKY GPIO_NONSTICKY -#define GPIO_100_STICKY GPIO_NONSTICKY -#define GPIO_101_STICKY GPIO_NONSTICKY -#define GPIO_102_STICKY GPIO_STICKY -#define GPIO_103_STICKY GPIO_STICKY -#define GPIO_104_STICKY GPIO_NONSTICKY -#define GPIO_105_STICKY GPIO_NONSTICKY -#define GPIO_106_STICKY GPIO_NONSTICKY -#define GPIO_107_STICKY GPIO_NONSTICKY -#define GPIO_108_STICKY GPIO_STICKY -#define GPIO_109_STICKY GPIO_NONSTICKY -#define GPIO_110_STICKY GPIO_NONSTICKY -#define GPIO_111_STICKY GPIO_NONSTICKY -#define GPIO_112_STICKY GPIO_NONSTICKY -#define GPIO_113_STICKY GPIO_NONSTICKY -#define GPIO_114_STICKY GPIO_NONSTICKY -#define GPIO_115_STICKY GPIO_NONSTICKY -#define GPIO_116_STICKY GPIO_NONSTICKY -#define GPIO_117_STICKY GPIO_NONSTICKY -#define GPIO_118_STICKY GPIO_NONSTICKY -#define GPIO_119_STICKY GPIO_NONSTICKY -#define GPIO_120_STICKY GPIO_NONSTICKY -#define GPIO_121_STICKY GPIO_NONSTICKY -#define GPIO_122_STICKY GPIO_NONSTICKY -#define GPIO_123_STICKY GPIO_NONSTICKY -#define GPIO_124_STICKY GPIO_NONSTICKY -#define GPIO_125_STICKY GPIO_NONSTICKY -#define GPIO_126_STICKY GPIO_NONSTICKY -#define GPIO_127_STICKY GPIO_NONSTICKY -#define GPIO_128_STICKY GPIO_NONSTICKY -#define GPIO_129_STICKY GPIO_NONSTICKY -#define GPIO_130_STICKY GPIO_NONSTICKY -#define GPIO_131_STICKY GPIO_NONSTICKY -#define GPIO_132_STICKY GPIO_NONSTICKY -#define GPIO_133_STICKY GPIO_NONSTICKY -#define GPIO_134_STICKY GPIO_NONSTICKY -#define GPIO_135_STICKY GPIO_NONSTICKY -#define GPIO_136_STICKY GPIO_NONSTICKY -#define GPIO_137_STICKY GPIO_NONSTICKY -#define GPIO_138_STICKY GPIO_NONSTICKY -#define GPIO_139_STICKY GPIO_NONSTICKY -#define GPIO_140_STICKY GPIO_NONSTICKY -#define GPIO_141_STICKY GPIO_NONSTICKY -#define GPIO_142_STICKY GPIO_NONSTICKY -#define GPIO_143_STICKY GPIO_NONSTICKY -#define GPIO_144_STICKY GPIO_NONSTICKY -#define GPIO_145_STICKY GPIO_NONSTICKY -#define GPIO_146_STICKY GPIO_NONSTICKY -#define GPIO_147_STICKY GPIO_NONSTICKY -#define GPIO_148_STICKY GPIO_NONSTICKY -#define GPIO_149_STICKY GPIO_NONSTICKY -#define GPIO_150_STICKY GPIO_NONSTICKY -#define GPIO_151_STICKY GPIO_NONSTICKY -#define GPIO_152_STICKY GPIO_NONSTICKY -#define GPIO_153_STICKY GPIO_NONSTICKY -#define GPIO_154_STICKY GPIO_NONSTICKY -#define GPIO_155_STICKY GPIO_NONSTICKY -#define GPIO_156_STICKY GPIO_NONSTICKY -#define GPIO_157_STICKY GPIO_NONSTICKY -#define GPIO_158_STICKY GPIO_NONSTICKY -#define GPIO_159_STICKY GPIO_NONSTICKY -#define GPIO_160_STICKY GPIO_NONSTICKY -#define GPIO_161_STICKY GPIO_NONSTICKY -#define GPIO_162_STICKY GPIO_NONSTICKY -#define GPIO_163_STICKY GPIO_NONSTICKY -#define GPIO_164_STICKY GPIO_NONSTICKY -#define GPIO_165_STICKY GPIO_NONSTICKY -#define GPIO_166_STICKY GPIO_NONSTICKY -#define GPIO_167_STICKY GPIO_NONSTICKY -#define GPIO_168_STICKY GPIO_NONSTICKY -#define GPIO_169_STICKY GPIO_NONSTICKY -#define GPIO_170_STICKY GPIO_STICKY -#define GPIO_171_STICKY GPIO_NONSTICKY -#define GPIO_172_STICKY GPIO_STICKY -#define GPIO_173_STICKY GPIO_NONSTICKY -#define GPIO_174_STICKY GPIO_NONSTICKY -#define GPIO_175_STICKY GPIO_NONSTICKY -#define GPIO_176_STICKY GPIO_NONSTICKY -#define GPIO_177_STICKY GPIO_NONSTICKY -#define GPIO_178_STICKY GPIO_NONSTICKY -#define GPIO_179_STICKY GPIO_NONSTICKY -#define GPIO_180_STICKY GPIO_NONSTICKY -#define GPIO_181_STICKY GPIO_NONSTICKY -#define GPIO_182_STICKY GPIO_NONSTICKY -#define GPIO_183_STICKY GPIO_NONSTICKY -#define GPIO_184_STICKY GPIO_NONSTICKY -#define GPIO_185_STICKY GPIO_NONSTICKY -#define GPIO_186_STICKY GPIO_NONSTICKY -#define GPIO_187_STICKY GPIO_NONSTICKY -#define GPIO_188_STICKY GPIO_NONSTICKY -#define GPIO_189_STICKY GPIO_NONSTICKY -#define GPIO_190_STICKY GPIO_NONSTICKY -#define GPIO_191_STICKY GPIO_NONSTICKY -#define GPIO_192_STICKY GPIO_NONSTICKY -#define GPIO_193_STICKY GPIO_NONSTICKY -#define GPIO_194_STICKY GPIO_NONSTICKY -#define GPIO_195_STICKY GPIO_NONSTICKY -#define GPIO_196_STICKY GPIO_NONSTICKY -#define GPIO_197_STICKY GPIO_NONSTICKY -#define GPIO_198_STICKY GPIO_NONSTICKY -#define GPIO_199_STICKY GPIO_NONSTICKY -#define GPIO_200_STICKY GPIO_NONSTICKY -#define GPIO_201_STICKY GPIO_NONSTICKY -#define GPIO_202_STICKY GPIO_NONSTICKY -#define GPIO_203_STICKY GPIO_NONSTICKY -#define GPIO_204_STICKY GPIO_NONSTICKY -#define GPIO_205_STICKY GPIO_NONSTICKY -#define GPIO_206_STICKY GPIO_NONSTICKY -#define GPIO_207_STICKY GPIO_NONSTICKY -#define GPIO_208_STICKY GPIO_NONSTICKY -#define GPIO_209_STICKY GPIO_NONSTICKY -#define GPIO_210_STICKY GPIO_NONSTICKY -#define GPIO_211_STICKY GPIO_NONSTICKY -#define GPIO_212_STICKY GPIO_NONSTICKY -#define GPIO_213_STICKY GPIO_NONSTICKY -#define GPIO_214_STICKY GPIO_NONSTICKY -#define GPIO_215_STICKY GPIO_NONSTICKY -#define GPIO_216_STICKY GPIO_NONSTICKY -#define GPIO_217_STICKY GPIO_NONSTICKY -#define GPIO_218_STICKY GPIO_NONSTICKY -#define GPIO_219_STICKY GPIO_NONSTICKY -#define GPIO_220_STICKY GPIO_NONSTICKY -#define GPIO_221_STICKY GPIO_NONSTICKY -#define GPIO_222_STICKY GPIO_NONSTICKY -#define GPIO_223_STICKY GPIO_NONSTICKY -#define GPIO_224_STICKY GPIO_NONSTICKY -#define GPIO_225_STICKY GPIO_NONSTICKY -#define GPIO_226_STICKY GPIO_NONSTICKY -#define GPIO_227_STICKY GPIO_NONSTICKY -#define GPIO_228_STICKY GPIO_NONSTICKY -#define GPIO_229_STICKY GPIO_NONSTICKY +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY
-#define PULLUP_ENABLE (0<<3) -#define PULLUP_DISABLE (1<<3) +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3)
-#define GPIO_00_PULLUP PULLUP_DISABLE -#define GPIO_01_PULLUP PULLUP_DISABLE -#define GPIO_02_PULLUP PULLUP_DISABLE -#define GPIO_03_PULLUP PULLUP_DISABLE -#define GPIO_04_PULLUP PULLUP_DISABLE -#define GPIO_05_PULLUP PULLUP_DISABLE -#define GPIO_06_PULLUP PULLUP_DISABLE -#define GPIO_07_PULLUP PULLUP_DISABLE -#define GPIO_08_PULLUP PULLUP_DISABLE -#define GPIO_09_PULLUP PULLUP_DISABLE -#define GPIO_10_PULLUP PULLUP_DISABLE -#define GPIO_11_PULLUP PULLUP_DISABLE -#define GPIO_12_PULLUP PULLUP_DISABLE -#define GPIO_13_PULLUP PULLUP_DISABLE -#define GPIO_14_PULLUP PULLUP_DISABLE -#define GPIO_15_PULLUP PULLUP_DISABLE -#define GPIO_16_PULLUP PULLUP_DISABLE -#define GPIO_17_PULLUP PULLUP_DISABLE -#define GPIO_18_PULLUP PULLUP_DISABLE -#define GPIO_19_PULLUP PULLUP_DISABLE -#define GPIO_20_PULLUP PULLUP_DISABLE -#define GPIO_21_PULLUP PULLUP_DISABLE -#define GPIO_22_PULLUP PULLUP_DISABLE -#define GPIO_23_PULLUP PULLUP_DISABLE -#define GPIO_24_PULLUP PULLUP_DISABLE -#define GPIO_25_PULLUP PULLUP_DISABLE -#define GPIO_26_PULLUP PULLUP_DISABLE -#define GPIO_27_PULLUP PULLUP_DISABLE -#define GPIO_28_PULLUP PULLUP_DISABLE -#define GPIO_29_PULLUP PULLUP_DISABLE -#define GPIO_30_PULLUP PULLUP_DISABLE -#define GPIO_31_PULLUP PULLUP_DISABLE -#define GPIO_32_PULLUP PULLUP_DISABLE -#define GPIO_33_PULLUP PULLUP_DISABLE -#define GPIO_34_PULLUP PULLUP_DISABLE -#define GPIO_35_PULLUP PULLUP_DISABLE -#define GPIO_36_PULLUP PULLUP_DISABLE -#define GPIO_37_PULLUP PULLUP_DISABLE -#define GPIO_38_PULLUP PULLUP_DISABLE -#define GPIO_39_PULLUP PULLUP_DISABLE -#define GPIO_40_PULLUP PULLUP_DISABLE -#define GPIO_41_PULLUP PULLUP_DISABLE -#define GPIO_42_PULLUP PULLUP_DISABLE -#define GPIO_43_PULLUP PULLUP_DISABLE -#define GPIO_44_PULLUP PULLUP_DISABLE -#define GPIO_45_PULLUP PULLUP_DISABLE -#define GPIO_46_PULLUP PULLUP_DISABLE -#define GPIO_47_PULLUP PULLUP_DISABLE -#define GPIO_48_PULLUP PULLUP_DISABLE -#define GPIO_49_PULLUP PULLUP_DISABLE -#define GPIO_50_PULLUP PULLUP_DISABLE -#define GPIO_51_PULLUP PULLUP_DISABLE -#define GPIO_52_PULLUP PULLUP_DISABLE -#define GPIO_53_PULLUP PULLUP_DISABLE -#define GPIO_54_PULLUP PULLUP_DISABLE -#define GPIO_55_PULLUP PULLUP_DISABLE -#define GPIO_56_PULLUP PULLUP_DISABLE -#define GPIO_57_PULLUP PULLUP_DISABLE -#define GPIO_58_PULLUP PULLUP_DISABLE -#define GPIO_59_PULLUP PULLUP_DISABLE -#define GPIO_60_PULLUP PULLUP_DISABLE -#define GPIO_61_PULLUP PULLUP_DISABLE -#define GPIO_62_PULLUP PULLUP_DISABLE -#define GPIO_63_PULLUP PULLUP_DISABLE -#define GPIO_64_PULLUP PULLUP_DISABLE -#define GPIO_65_PULLUP PULLUP_DISABLE -#define GPIO_66_PULLUP PULLUP_DISABLE -#define GPIO_67_PULLUP PULLUP_DISABLE -#define GPIO_68_PULLUP PULLUP_DISABLE -#define GPIO_69_PULLUP PULLUP_DISABLE -#define GPIO_70_PULLUP PULLUP_DISABLE -#define GPIO_71_PULLUP PULLUP_DISABLE -#define GPIO_72_PULLUP PULLUP_DISABLE -#define GPIO_73_PULLUP PULLUP_DISABLE -#define GPIO_74_PULLUP PULLUP_DISABLE -#define GPIO_75_PULLUP PULLUP_DISABLE -#define GPIO_76_PULLUP PULLUP_DISABLE -#define GPIO_77_PULLUP PULLUP_DISABLE -#define GPIO_78_PULLUP PULLUP_DISABLE -#define GPIO_79_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_81_PULLUP PULLUP_DISABLE -#define GPIO_82_PULLUP PULLUP_DISABLE -#define GPIO_83_PULLUP PULLUP_DISABLE -#define GPIO_84_PULLUP PULLUP_DISABLE -#define GPIO_85_PULLUP PULLUP_DISABLE -#define GPIO_86_PULLUP PULLUP_DISABLE -#define GPIO_87_PULLUP PULLUP_DISABLE -#define GPIO_88_PULLUP PULLUP_DISABLE -#define GPIO_89_PULLUP PULLUP_DISABLE -#define GPIO_90_PULLUP PULLUP_DISABLE -#define GPIO_91_PULLUP PULLUP_DISABLE -#define GPIO_92_PULLUP PULLUP_DISABLE -#define GPIO_93_PULLUP PULLUP_DISABLE -#define GPIO_94_PULLUP PULLUP_DISABLE -#define GPIO_95_PULLUP PULLUP_DISABLE -#define GPIO_96_PULLUP PULLUP_DISABLE -#define GPIO_97_PULLUP PULLUP_DISABLE -#define GPIO_98_PULLUP PULLUP_DISABLE -#define GPIO_99_PULLUP PULLUP_DISABLE -#define GPIO_100_PULLUP PULLUP_DISABLE -#define GPIO_101_PULLUP PULLUP_DISABLE -#define GPIO_102_PULLUP PULLUP_DISABLE -#define GPIO_103_PULLUP PULLUP_DISABLE -#define GPIO_104_PULLUP PULLUP_DISABLE -#define GPIO_105_PULLUP PULLUP_DISABLE -#define GPIO_106_PULLUP PULLUP_DISABLE -#define GPIO_107_PULLUP PULLUP_DISABLE -#define GPIO_108_PULLUP PULLUP_DISABLE -#define GPIO_109_PULLUP PULLUP_DISABLE -#define GPIO_110_PULLUP PULLUP_DISABLE -#define GPIO_111_PULLUP PULLUP_DISABLE -#define GPIO_112_PULLUP PULLUP_DISABLE -#define GPIO_113_PULLUP PULLUP_DISABLE -#define GPIO_114_PULLUP PULLUP_DISABLE -#define GPIO_115_PULLUP PULLUP_DISABLE -#define GPIO_116_PULLUP PULLUP_DISABLE -#define GPIO_117_PULLUP PULLUP_DISABLE -#define GPIO_118_PULLUP PULLUP_ENABLE -#define GPIO_119_PULLUP PULLUP_DISABLE -#define GPIO_120_PULLUP PULLUP_DISABLE -#define GPIO_121_PULLUP PULLUP_DISABLE -#define GPIO_122_PULLUP PULLUP_DISABLE -#define GPIO_123_PULLUP PULLUP_DISABLE -#define GPIO_124_PULLUP PULLUP_DISABLE -#define GPIO_125_PULLUP PULLUP_DISABLE -#define GPIO_126_PULLUP PULLUP_DISABLE -#define GPIO_127_PULLUP PULLUP_DISABLE -#define GPIO_128_PULLUP PULLUP_DISABLE -#define GPIO_129_PULLUP PULLUP_DISABLE -#define GPIO_130_PULLUP PULLUP_DISABLE -#define GPIO_131_PULLUP PULLUP_DISABLE -#define GPIO_132_PULLUP PULLUP_DISABLE -#define GPIO_133_PULLUP PULLUP_DISABLE -#define GPIO_134_PULLUP PULLUP_DISABLE -#define GPIO_135_PULLUP PULLUP_DISABLE -#define GPIO_136_PULLUP PULLUP_DISABLE -#define GPIO_137_PULLUP PULLUP_DISABLE -#define GPIO_138_PULLUP PULLUP_DISABLE -#define GPIO_139_PULLUP PULLUP_DISABLE -#define GPIO_140_PULLUP PULLUP_DISABLE -#define GPIO_141_PULLUP PULLUP_DISABLE -#define GPIO_142_PULLUP PULLUP_DISABLE -#define GPIO_143_PULLUP PULLUP_DISABLE -#define GPIO_144_PULLUP PULLUP_DISABLE -#define GPIO_145_PULLUP PULLUP_DISABLE -#define GPIO_146_PULLUP PULLUP_DISABLE -#define GPIO_147_PULLUP PULLUP_DISABLE -#define GPIO_148_PULLUP PULLUP_DISABLE -#define GPIO_149_PULLUP PULLUP_DISABLE -#define GPIO_150_PULLUP PULLUP_DISABLE -#define GPIO_151_PULLUP PULLUP_DISABLE -#define GPIO_152_PULLUP PULLUP_DISABLE -#define GPIO_153_PULLUP PULLUP_DISABLE -#define GPIO_154_PULLUP PULLUP_DISABLE -#define GPIO_155_PULLUP PULLUP_DISABLE -#define GPIO_156_PULLUP PULLUP_DISABLE -#define GPIO_157_PULLUP PULLUP_DISABLE -#define GPIO_158_PULLUP PULLUP_DISABLE -#define GPIO_159_PULLUP PULLUP_DISABLE -#define GPIO_160_PULLUP PULLUP_DISABLE -#define GPIO_161_PULLUP PULLUP_DISABLE -#define GPIO_162_PULLUP PULLUP_DISABLE -#define GPIO_163_PULLUP PULLUP_DISABLE -#define GPIO_164_PULLUP PULLUP_DISABLE -#define GPIO_165_PULLUP PULLUP_DISABLE -#define GPIO_166_PULLUP PULLUP_DISABLE -#define GPIO_167_PULLUP PULLUP_DISABLE -#define GPIO_168_PULLUP PULLUP_DISABLE -#define GPIO_169_PULLUP PULLUP_DISABLE -#define GPIO_170_PULLUP PULLUP_DISABLE -#define GPIO_171_PULLUP PULLUP_DISABLE -#define GPIO_172_PULLUP PULLUP_DISABLE -#define GPIO_173_PULLUP PULLUP_DISABLE -#define GPIO_174_PULLUP PULLUP_DISABLE -#define GPIO_175_PULLUP PULLUP_DISABLE -#define GPIO_176_PULLUP PULLUP_DISABLE -#define GPIO_177_PULLUP PULLUP_DISABLE -#define GPIO_178_PULLUP PULLUP_DISABLE -#define GPIO_179_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_181_PULLUP PULLUP_DISABLE -#define GPIO_182_PULLUP PULLUP_DISABLE -#define GPIO_183_PULLUP PULLUP_DISABLE -#define GPIO_184_PULLUP PULLUP_DISABLE -#define GPIO_185_PULLUP PULLUP_DISABLE -#define GPIO_186_PULLUP PULLUP_DISABLE -#define GPIO_187_PULLUP PULLUP_DISABLE -#define GPIO_188_PULLUP PULLUP_DISABLE -#define GPIO_189_PULLUP PULLUP_DISABLE -#define GPIO_190_PULLUP PULLUP_DISABLE -#define GPIO_191_PULLUP PULLUP_DISABLE -#define GPIO_192_PULLUP PULLUP_DISABLE -#define GPIO_193_PULLUP PULLUP_DISABLE -#define GPIO_194_PULLUP PULLUP_DISABLE -#define GPIO_195_PULLUP PULLUP_DISABLE -#define GPIO_196_PULLUP PULLUP_DISABLE -#define GPIO_197_PULLUP PULLUP_DISABLE -#define GPIO_198_PULLUP PULLUP_DISABLE -#define GPIO_199_PULLUP PULLUP_DISABLE -#define GPIO_200_PULLUP PULLUP_DISABLE -#define GPIO_201_PULLUP PULLUP_DISABLE -#define GPIO_202_PULLUP PULLUP_DISABLE -#define GPIO_203_PULLUP PULLUP_DISABLE -#define GPIO_204_PULLUP PULLUP_DISABLE -#define GPIO_205_PULLUP PULLUP_DISABLE -#define GPIO_206_PULLUP PULLUP_DISABLE -#define GPIO_207_PULLUP PULLUP_DISABLE -#define GPIO_208_PULLUP PULLUP_DISABLE -#define GPIO_209_PULLUP PULLUP_DISABLE -#define GPIO_210_PULLUP PULLUP_DISABLE -#define GPIO_211_PULLUP PULLUP_DISABLE -#define GPIO_212_PULLUP PULLUP_DISABLE -#define GPIO_213_PULLUP PULLUP_DISABLE -#define GPIO_214_PULLUP PULLUP_DISABLE -#define GPIO_215_PULLUP PULLUP_DISABLE -#define GPIO_216_PULLUP PULLUP_DISABLE -#define GPIO_217_PULLUP PULLUP_DISABLE -#define GPIO_218_PULLUP PULLUP_DISABLE -#define GPIO_219_PULLUP PULLUP_DISABLE -#define GPIO_220_PULLUP PULLUP_DISABLE -#define GPIO_221_PULLUP PULLUP_DISABLE -#define GPIO_222_PULLUP PULLUP_DISABLE -#define GPIO_223_PULLUP PULLUP_DISABLE -#define GPIO_224_PULLUP PULLUP_DISABLE -#define GPIO_225_PULLUP PULLUP_DISABLE -#define GPIO_226_PULLUP PULLUP_DISABLE -#define GPIO_227_PULLUP PULLUP_DISABLE -#define GPIO_228_PULLUP PULLUP_DISABLE -#define GPIO_229_PULLUP PULLUP_DISABLE +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE
-#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_ENABLE (1<<4) #define PULLDOWN_DISABLE (0<<4)
#define GPIO_00_PULLDOWN PULLDOWN_DISABLE @@ -1532,230 +1532,230 @@ #define GPIO_228_PULLDOWN PULLDOWN_DISABLE #define GPIO_229_PULLDOWN PULLDOWN_DISABLE
-#define EVENT_DISABLE 0 -#define EVENT_ENABLE 1 +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1
-#define GEVENT_00_EVENTENABLE EVENT_DISABLE -#define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# -#define GEVENT_06_EVENTENABLE EVENT_DISABLE -#define GEVENT_07_EVENTENABLE EVENT_DISABLE -#define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO -#define GEVENT_10_EVENTENABLE EVENT_DISABLE -#define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# -#define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN -#define GEVENT_18_EVENTENABLE EVENT_DISABLE -#define GEVENT_19_EVENTENABLE EVENT_DISABLE -#define GEVENT_20_EVENTENABLE EVENT_DISABLE -#define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI#
-#define SCITRIG_LOW 0 -#define SCITRIG_HI 1 +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1
-#define GEVENT_00_SCITRIG SCITRIG_LOW -#define GEVENT_01_SCITRIG SCITRIG_LOW -#define GEVENT_02_SCITRIG SCITRIG_LOW -#define GEVENT_03_SCITRIG SCITRIG_LOW -#define GEVENT_04_SCITRIG SCITRIG_LOW -#define GEVENT_05_SCITRIG SCITRIG_LOW -#define GEVENT_06_SCITRIG SCITRIG_LOW -#define GEVENT_07_SCITRIG SCITRIG_LOW -#define GEVENT_08_SCITRIG SCITRIG_LOW -#define GEVENT_09_SCITRIG SCITRIG_LOW -#define GEVENT_10_SCITRIG SCITRIG_LOW -#define GEVENT_11_SCITRIG SCITRIG_LOW -#define GEVENT_12_SCITRIG SCITRIG_LOW -#define GEVENT_13_SCITRIG SCITRIG_LOW -#define GEVENT_14_SCITRIG SCITRIG_LOW -#define GEVENT_15_SCITRIG SCITRIG_LOW -#define GEVENT_16_SCITRIG SCITRIG_LOW -#define GEVENT_17_SCITRIG SCITRIG_HI -#define GEVENT_18_SCITRIG SCITRIG_LOW -#define GEVENT_19_SCITRIG SCITRIG_LOW -#define GEVENT_20_SCITRIG SCITRIG_LOW -#define GEVENT_21_SCITRIG SCITRIG_LOW -#define GEVENT_22_SCITRIG SCITRIG_LOW -#define GEVENT_23_SCITRIG SCITRIG_LOW +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW
-#define SCILEVEL_EDGE 0 -#define SCILEVEL_LEVEL 1 +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1
-#define GEVENT_00_SCILEVEL SCILEVEL_EDGE -#define GEVENT_01_SCILEVEL SCILEVEL_EDGE -#define GEVENT_02_SCILEVEL SCILEVEL_EDGE -#define GEVENT_03_SCILEVEL SCILEVEL_EDGE -#define GEVENT_04_SCILEVEL SCILEVEL_EDGE -#define GEVENT_05_SCILEVEL SCILEVEL_EDGE -#define GEVENT_06_SCILEVEL SCILEVEL_EDGE -#define GEVENT_07_SCILEVEL SCILEVEL_EDGE -#define GEVENT_08_SCILEVEL SCILEVEL_EDGE -#define GEVENT_09_SCILEVEL SCILEVEL_EDGE -#define GEVENT_10_SCILEVEL SCILEVEL_EDGE -#define GEVENT_11_SCILEVEL SCILEVEL_EDGE -#define GEVENT_12_SCILEVEL SCILEVEL_EDGE -#define GEVENT_13_SCILEVEL SCILEVEL_EDGE -#define GEVENT_14_SCILEVEL SCILEVEL_EDGE -#define GEVENT_15_SCILEVEL SCILEVEL_EDGE -#define GEVENT_16_SCILEVEL SCILEVEL_EDGE -#define GEVENT_17_SCILEVEL SCILEVEL_EDGE -#define GEVENT_18_SCILEVEL SCILEVEL_EDGE -#define GEVENT_19_SCILEVEL SCILEVEL_EDGE -#define GEVENT_20_SCILEVEL SCILEVEL_EDGE -#define GEVENT_21_SCILEVEL SCILEVEL_EDGE -#define GEVENT_22_SCILEVEL SCILEVEL_EDGE -#define GEVENT_23_SCILEVEL SCILEVEL_EDGE +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE
-#define SMISCI_DISABLE 0 -#define SMISCI_ENABLE 1 +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1
-#define GEVENT_00_SMISCIEN SMISCI_DISABLE -#define GEVENT_01_SMISCIEN SMISCI_DISABLE -#define GEVENT_02_SMISCIEN SMISCI_DISABLE -#define GEVENT_03_SMISCIEN SMISCI_DISABLE -#define GEVENT_04_SMISCIEN SMISCI_DISABLE -#define GEVENT_05_SMISCIEN SMISCI_DISABLE -#define GEVENT_06_SMISCIEN SMISCI_DISABLE -#define GEVENT_07_SMISCIEN SMISCI_DISABLE -#define GEVENT_08_SMISCIEN SMISCI_DISABLE -#define GEVENT_09_SMISCIEN SMISCI_DISABLE -#define GEVENT_10_SMISCIEN SMISCI_DISABLE -#define GEVENT_11_SMISCIEN SMISCI_DISABLE -#define GEVENT_12_SMISCIEN SMISCI_DISABLE -#define GEVENT_13_SMISCIEN SMISCI_DISABLE -#define GEVENT_14_SMISCIEN SMISCI_DISABLE -#define GEVENT_15_SMISCIEN SMISCI_DISABLE -#define GEVENT_16_SMISCIEN SMISCI_DISABLE -#define GEVENT_17_SMISCIEN SMISCI_DISABLE -#define GEVENT_18_SMISCIEN SMISCI_DISABLE -#define GEVENT_19_SMISCIEN SMISCI_DISABLE -#define GEVENT_20_SMISCIEN SMISCI_DISABLE -#define GEVENT_21_SMISCIEN SMISCI_DISABLE -#define GEVENT_22_SMISCIEN SMISCI_DISABLE -#define GEVENT_23_SMISCIEN SMISCI_DISABLE +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE
-#define SCIS0_DISABLE 0 -#define SCIS0_ENABLE 1 +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1
-#define GEVENT_00_SCIS0EN SCIS0_DISABLE -#define GEVENT_01_SCIS0EN SCIS0_DISABLE -#define GEVENT_02_SCIS0EN SCIS0_DISABLE -#define GEVENT_03_SCIS0EN SCIS0_DISABLE -#define GEVENT_04_SCIS0EN SCIS0_DISABLE -#define GEVENT_05_SCIS0EN SCIS0_DISABLE -#define GEVENT_06_SCIS0EN SCIS0_DISABLE -#define GEVENT_07_SCIS0EN SCIS0_DISABLE -#define GEVENT_08_SCIS0EN SCIS0_DISABLE -#define GEVENT_09_SCIS0EN SCIS0_DISABLE -#define GEVENT_10_SCIS0EN SCIS0_DISABLE -#define GEVENT_11_SCIS0EN SCIS0_DISABLE -#define GEVENT_12_SCIS0EN SCIS0_DISABLE -#define GEVENT_13_SCIS0EN SCIS0_DISABLE -#define GEVENT_14_SCIS0EN SCIS0_DISABLE -#define GEVENT_15_SCIS0EN SCIS0_DISABLE -#define GEVENT_16_SCIS0EN SCIS0_DISABLE -#define GEVENT_17_SCIS0EN SCIS0_DISABLE -#define GEVENT_18_SCIS0EN SCIS0_DISABLE -#define GEVENT_19_SCIS0EN SCIS0_DISABLE -#define GEVENT_20_SCIS0EN SCIS0_DISABLE -#define GEVENT_21_SCIS0EN SCIS0_DISABLE -#define GEVENT_22_SCIS0EN SCIS0_DISABLE -#define GEVENT_23_SCIS0EN SCIS0_DISABLE +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE
-#define GEVENT_SCIMASK 0x1F -#define GEVENT_00_SCIMAP 0 -#define GEVENT_01_SCIMAP 1 -#define GEVENT_02_SCIMAP 2 -#define GEVENT_03_SCIMAP 3 -#define GEVENT_04_SCIMAP 4 -#define GEVENT_05_SCIMAP 5 -#define GEVENT_06_SCIMAP 6 -#define GEVENT_07_SCIMAP 7 -#define GEVENT_08_SCIMAP 8 -#define GEVENT_09_SCIMAP 9 -#define GEVENT_10_SCIMAP 10 -#define GEVENT_11_SCIMAP 11 -#define GEVENT_12_SCIMAP 12 -#define GEVENT_13_SCIMAP 13 -#define GEVENT_14_SCIMAP 14 -#define GEVENT_15_SCIMAP 15 -#define GEVENT_16_SCIMAP 16 -#define GEVENT_17_SCIMAP 17 -#define GEVENT_18_SCIMAP 18 -#define GEVENT_19_SCIMAP 19 -#define GEVENT_20_SCIMAP 20 -#define GEVENT_21_SCIMAP 21 -#define GEVENT_22_SCIMAP 22 -#define GEVENT_23_SCIMAP 23 +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23
-#define SMITRIG_LOW 0 -#define SMITRIG_HI 1 +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1
-#define GEVENT_00_SMITRIG SMITRIG_HI -#define GEVENT_01_SMITRIG SMITRIG_HI -#define GEVENT_02_SMITRIG SMITRIG_HI -#define GEVENT_03_SMITRIG SMITRIG_HI -#define GEVENT_04_SMITRIG SMITRIG_HI -#define GEVENT_05_SMITRIG SMITRIG_HI -#define GEVENT_06_SMITRIG SMITRIG_HI -#define GEVENT_07_SMITRIG SMITRIG_HI -#define GEVENT_08_SMITRIG SMITRIG_HI -#define GEVENT_09_SMITRIG SMITRIG_HI -#define GEVENT_10_SMITRIG SMITRIG_HI -#define GEVENT_11_SMITRIG SMITRIG_HI -#define GEVENT_12_SMITRIG SMITRIG_HI -#define GEVENT_13_SMITRIG SMITRIG_HI -#define GEVENT_14_SMITRIG SMITRIG_HI -#define GEVENT_15_SMITRIG SMITRIG_HI -#define GEVENT_16_SMITRIG SMITRIG_HI -#define GEVENT_17_SMITRIG SMITRIG_HI -#define GEVENT_18_SMITRIG SMITRIG_HI -#define GEVENT_19_SMITRIG SMITRIG_HI -#define GEVENT_20_SMITRIG SMITRIG_HI -#define GEVENT_21_SMITRIG SMITRIG_HI -#define GEVENT_22_SMITRIG SMITRIG_HI -#define GEVENT_23_SMITRIG SMITRIG_HI +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI
-#define SMICONTROL_MASK 3 -#define SMICONTROL_DISABLE 0 -#define SMICONTROL_SMI 1 -#define SMICONTROL_NMI 2 -#define SMICONTROL_IRQ13 3 +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3
-#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE
#define GPIO_RSVD_ZONE0_S GPIO_81 #define GPIO_RSVD_ZONE0_E GPIO_95 @@ -1763,7 +1763,7 @@ #define GPIO_RSVD_ZONE1_E GPIO_127
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ typedef enum _GPIO_COUNT @@ -2274,13 +2274,13 @@ typedef enum _GEVENT_COUNT typedef struct _GEVENT_SETTINGS { u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 } GEVENT_SETTINGS;
GEVENT_SETTINGS gevent_table[] = @@ -2312,17 +2312,17 @@ GEVENT_SETTINGS gevent_table[] = };
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 60779f8..b4a7246 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
}
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index ebcc40f..46c9e2e 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -104,8 +104,8 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); * - * @param[in] u32 func Northbridge CIMx CallBackId - * @param[in] u32 data Northbridge Input Data. + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. * */ diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 71cac2e..e0101c4 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -67,7 +67,7 @@ /** * Bitmap of ports that have slot or onboard device connected. * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) - * #define DEFAULT_PORT_FORCE_GEN1 0x604 + * #define DEFAULT_PORT_FORCE_GEN1 0x604 */ #ifndef DEFAULT_PORT_FORCE_GEN1 #define DEFAULT_PORT_FORCE_GEN1 0x0 @@ -108,12 +108,12 @@
/** * Default GPP3a core configuraton on NB #0/1/2/3. - * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 - * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 - * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 - * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 - * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 - * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 */ #ifndef DEFAULT_GPP3A_CONFIG #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 @@ -154,17 +154,17 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. } NB_PLATFORM_CONFIG;
/** diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index c9a0949..87ef265 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -19,7 +19,7 @@
#include <string.h> -#include <console/console.h> /* printk */ +#include <console/console.h> /* printk */ #include "Platform.h" #include "sb700_cfg.h"
@@ -96,7 +96,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER;
/* USB */ - sb_config->UsbIntClock = 0; // Use external clock + sb_config->UsbIntClock = 0; // Use external clock sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 216c264..bc35397 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -30,10 +30,10 @@ * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7
/* In SB700, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -57,7 +57,7 @@ * 0 - Disable Spread Spectrum function * 1 - Enable Spread Spectrum function */ -#define SPREAD_SPECTRUM 0 +#define SPREAD_SPECTRUM 0
/** * @def SB_HPET_TIMER @@ -65,7 +65,7 @@ * 0 - Disable hpet * 1 - Enable hpet */ -#define HPET_TIMER 1 +#define HPET_TIMER 1
/** * @def USB_CONFIG @@ -80,7 +80,7 @@ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 */ -#define USB_CINFIG 0x7F +#define USB_CINFIG 0x7F
/** * @def PCI_CLOCK_CTRL @@ -93,14 +93,14 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x1F
/** * @def SATA_CONTROLLER * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER -#define SATA_CONTROLLER 1 +#define SATA_CONTROLLER 1 #endif
/** @@ -109,14 +109,14 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE NATIVE_IDE_MODE #endif
/** * @brief INCHIP Sata IDE Controller Mode */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1
/** * @def SATA_IDE_MODE @@ -124,7 +124,7 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE -#define SATA_IDE_MODE IDE_LEGACY_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE #endif
/** @@ -136,37 +136,37 @@ * @brief 01/11: Reference clock from internal clock through * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01
-#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK
/** * @def SATA_PORT_MULT_CAP_RESERVED * @brief 1 ON, 0 0FF */ -#define SATA_PORT_MULT_CAP_RESERVED 1 +#define SATA_PORT_MULT_CAP_RESERVED 1
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2
/** * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER -#define AZALIA_CONTROLLER AZALIA_AUTO +#define AZALIA_CONTROLLER AZALIA_AUTO #endif
/** @@ -176,7 +176,7 @@ * 1 - enable */ #ifndef AZALIA_PIN_CONFIG -#define AZALIA_PIN_CONFIG 1 +#define AZALIA_PIN_CONFIG 1 #endif
/** @@ -191,19 +191,19 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA +//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN -#define AZALIA_SDIN_PIN_0 0x2 -#define AZALIA_SDIN_PIN_1 0x2 -#define AZALIA_SDIN_PIN_2 0x2 -#define AZALIA_SDIN_PIN_3 0x0 +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif
/** * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER -#define GPP_CONTROLLER 1 +#define GPP_CONTROLLER 1 #endif
/** @@ -216,7 +216,7 @@ * GPP_CFGMODE_X1111 */ #ifndef GPP_CFGMODE -#define GPP_CFGMODE GPP_CFGMODE_X1111 +#define GPP_CFGMODE GPP_CFGMODE_X1111 #endif
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 452a592..46af039 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -95,14 +95,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -224,12 +224,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -340,8 +340,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -374,7 +374,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; @@ -382,9 +382,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -440,14 +440,14 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; @@ -455,10 +455,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; @@ -535,12 +535,12 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; + UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; - UINT8 Data8; + UINT8 Data8; UINT16 Data16;
FcnData = Data; @@ -568,7 +568,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; } @@ -584,7 +584,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; } @@ -600,7 +600,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; } diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h index 35056fa..9b6d728 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.h +++ b/src/mainboard/amd/inagua/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; @@ -68,12 +68,12 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index cf868fe..cb0cc5f 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -103,9 +103,9 @@ config VGA_BIOS default n
#config VGA_BIOS_FILE -# string "VGA BIOS path and filename" -# depends on VGA_BIOS -# default "rom/video/OntarioGenericVBios.bin" +# string "VGA BIOS path and filename" +# depends on VGA_BIOS +# default "rom/video/OntarioGenericVBios.bin"
config VGA_BIOS_ID string "VGA device PCI IDs" diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ b/src/mainboard/amd/inagua/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index c64e523..7d07c7a 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -84,7 +84,7 @@ OemCustomizeInitEarly ( PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS { - 0, //Descriptor flags + 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1) }, @@ -122,10 +122,10 @@ OemCustomizeInitEarly ( BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (BrazosPcieComplexListPtr, 0, diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 111ad6f..5bc6326 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -25,44 +25,44 @@ #include "amdlib.h"
//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
diff --git a/src/mainboard/amd/inagua/acpi/ide.asl b/src/mainboard/amd/inagua/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/amd/inagua/acpi/ide.asl +++ b/src/mainboard/amd/inagua/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index e7a47c0..d052d79 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -484,8 +484,8 @@ agesawrapper_amdinitlate ( AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h index 31f22c1..9fef3cc 100644 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ b/src/mainboard/amd/inagua/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,26 +30,26 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 86de3b4..3f54795 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -168,9 +168,9 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .init.unknown = 0x00, .init.num_hunks = sizeof(selfboot_patch.init.hunk4_code) ? 0x80 : 0x60, .init.size = sizeof(selfboot_patch.init.hunk1_code) - + sizeof(selfboot_patch.init.hunk2_code) - + sizeof(selfboot_patch.init.hunk3_code) - + sizeof(selfboot_patch.init.hunk4_code), + + sizeof(selfboot_patch.init.hunk2_code) + + sizeof(selfboot_patch.init.hunk3_code) + + sizeof(selfboot_patch.init.hunk4_code), .init.hunk1_size = sizeof(selfboot_patch.init.hunk1_code), .init.hunk2_size = sizeof(selfboot_patch.init.hunk2_code), .init.hunk3_size = sizeof(selfboot_patch.init.hunk3_code), @@ -204,13 +204,13 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 14-11: any bit 1=firmware execution seemed delayed * 10: 0=firmware execution seemed delayed * 9,2,0: select PHY type, affects these registers, probably more - * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes + * 9 2 0 | reg 0x05A4 PHY reg 31 PHY 23,24,28 Notes * -------+---------------------------------------------------------- - * 0 0 0 | 0x331C71C1 - changed Inband Status enabled - * 0 1 0 | 0x3210C500 - changed - - * 0 X 1 | 0x33FF66C0 changed - 10/100 Mbit only - * 1 X 0 | 0x330C5180 - - - - * 1 X 1 | 0x391C6140 - - - + * 0 0 0 | 0x331C71C1 - changed Inband Status enabled + * 0 1 0 | 0x3210C500 - changed - + * 0 X 1 | 0x33FF66C0 changed - 10/100 Mbit only + * 1 X 0 | 0x330C5180 - - - + * 1 X 1 | 0x391C6140 - - - */ #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF .header.basic_config = be16(0x0404), //original for B50610 @@ -256,7 +256,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! #endif be(0xC1F005A0), be(0xFEFFEFFF), be(0x01001000), //v1.05 : 5A0.24,12=1: auto-clock-switch be(0x06100D34), be(0x00000000), //v1.03 : MemD34: clear config vars - be(0x06100D38), be(0x00000000), //v1.03 : - | + be(0x06100D38), be(0x00000000), //v1.03 : - | be(0x06100D3C), be(0x00000000), //v1.03 : MemD3F| }, //-->INIT1_LENGTH!
@@ -307,7 +307,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! #if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY #endif - be(0xF7F30116), // IDDQ PHY + be(0xF7F30116), // IDDQ PHY be(0xC40005A0), //v1.09 : 5A0.0=0: Port Mode = MII be(0xC4180400), //v1.09 : 400.3=0| be(0xC3100400), //v1.09 : 400.2=1| diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index dbf9787..379e994 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -318,7 +318,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -333,57 +333,57 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), @@ -410,8 +410,8 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -437,7 +437,7 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
@@ -447,7 +447,7 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index f7c7bb2..a254adf 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index be281055..7c37c2f 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -122,7 +122,7 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc23007..b6bf694 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -46,7 +46,7 @@ void set_pcie_dereset(void) { /** * GPIO32 Pcie Device DeAssert for APU - * GPIO25 Pcie LAN, APU GPP2 + * GPIO25 Pcie LAN, APU GPP2 * GPIO02 MINIPCIE SLOT1, APU GPP3 * GPIO50 Pcie Device DeAssert for Hudson Southbridge * GPIO05 Express Card, SB GPP0 diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7352205..2f7f7ac 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -64,7 +64,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 byte; @@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -147,7 +147,7 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 1f602e2..83ee45d 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/amd/mahogany/acpi/ide.asl b/src/mainboard/amd/mahogany/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/amd/mahogany/acpi/ide.asl +++ b/src/mainboard/amd/mahogany/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c index a493ccf..cc86b24 100644 --- a/src/mainboard/amd/mahogany/acpi_tables.c +++ b/src/mainboard/amd/mahogany/acpi_tables.c @@ -79,7 +79,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/mahogany/cmos.layout b/src/mainboard/amd/mahogany/cmos.layout index 37530b7..94ba135 100644 --- a/src/mainboard/amd/mahogany/cmos.layout +++ b/src/mainboard/amd/mahogany/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb index 56efd84..d4fe42f 100644 --- a/src/mainboard/amd/mahogany/devicetree.cb +++ b/src/mainboard/amd/mahogany/devicetree.cb @@ -31,7 +31,7 @@ chip northbridge/amd/amdk8/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 01cb8dd..ef1bd0c 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -379,16 +379,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -759,7 +759,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1139,7 +1139,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1161,8 +1161,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1172,8 +1172,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1181,8 +1181,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1190,8 +1190,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1200,8 +1200,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1210,8 +1210,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1219,8 +1219,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1412,7 +1412,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1592,23 +1592,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1617,7 +1617,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index f05ce7f..6c2c6bd 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0e542ff..cc2c7f3 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -60,7 +60,7 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); }
-#if 0 /* not tested yet */ +#if 0 /* not tested yet */ /******************************************************** * mahogany uses SB700 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index e83837d..90b1df7 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -155,7 +155,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/mahogany_fam10/acpi/ide.asl b/src/mainboard/amd/mahogany_fam10/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/ide.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/mahogany_fam10/cmos.layout b/src/mainboard/amd/mahogany_fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/amd/mahogany_fam10/cmos.layout +++ b/src/mainboard/amd/mahogany_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 4fd77b7..5c2595f 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index f55480d..af89cf6 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1455,7 +1455,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1652,23 +1652,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1677,7 +1677,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 7d4514a..a74c8fb 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -60,7 +60,7 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); }
-#if 0 /* not tested yet. */ +#if 0 /* not tested yet. */ /******************************************************** * mahogany uses SB700 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 9f5eb12..3894d0b 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/mahogany_fam10/resourcemap.c b/src/mainboard/amd/mahogany_fam10/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/amd/mahogany_fam10/resourcemap.c +++ b/src/mainboard/amd/mahogany_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index a9f8b46..08fcb9f 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -236,8 +236,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/amd/norwich/cmos.layout b/src/mainboard/amd/norwich/cmos.layout index 864d89a..83122ad 100644 --- a/src/mainboard/amd/norwich/cmos.layout +++ b/src/mainboard/amd/norwich/cmos.layout @@ -1,70 +1,70 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 1 e 0 dcon_present +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/amd/norwich/irq_tables.c b/src/mainboard/amd/norwich/irq_tables.c index 9183df8..0c2872e 100644 --- a/src/mainboard/amd/norwich/irq_tables.c +++ b/src/mainboard/amd/norwich/irq_tables.c @@ -43,7 +43,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -52,10 +52,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x002B, /* Device */ 0, /* Miniport data */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x1, 0x0}, /* slot1 */ diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 3fd3684..b2bf4fe 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -28,17 +28,17 @@
STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer }, - {AGESA_DO_RESET, fam16kb_Reset }, - {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer }, - {AGESA_READ_SPD, fam16kb_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData }, + {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer }, + {AGESA_DO_RESET, fam16kb_Reset }, + {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer }, + {AGESA_READ_SPD, fam16kb_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam16kb_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam16kb_HookBeforeExitSelfRefresh }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam16kb_HookGfxGetVbiosImage } };
@@ -66,9 +66,9 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 + {0x11, 0x411111F0}, // - SPDIF_OUT2 + {0x12, 0x411111F0}, // - DMIC_1/2 + {0x13, 0x411111F0}, // - DMIC_3/4 {0x14, 0x411111F0}, // Port D - LOUT1 {0x15, 0x411111F0}, // Port A - LOUT2 {0x16, 0x411111F0}, // @@ -77,8 +77,8 @@ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { {0x19, 0x411111F0}, // Port F - MIC2 {0x1a, 0x01813030}, // Port C - LINE1 {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 + {0x1d, 0x40130605}, // - PCBEEP + {0x1e, 0x01441120}, // - SPDIF_OUT1 {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} }; diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h index e006441..97bcd3f 100644 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ b/src/mainboard/amd/olivehill/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -54,14 +54,14 @@ //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 0775ad3..f6ccf4d 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -100,7 +100,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { };
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, + .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, .PciePortList = PortList, .DdiLinkList = DdiList @@ -118,7 +118,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -127,7 +127,7 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; + AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams; diff --git a/src/mainboard/amd/olivehill/acpi/ide.asl b/src/mainboard/amd/olivehill/acpi/ide.asl index 853dc13..820e4cd 100644 --- a/src/mainboard/amd/olivehill/acpi/ide.asl +++ b/src/mainboard/amd/olivehill/acpi/ide.asl @@ -32,21 +32,21 @@ Scope (_SB) { */
/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ })
-Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ })
-Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ })
/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ })
Name(PORT, Package(){ @@ -56,21 +56,21 @@ Name(PORT, Package(){ OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ Field(ICRG, AnyAcc, NoLock, Preserve) { - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ }
-Method(GTTM, 1) /* get total time*/ +Method(GTTM, 1) /* get total time*/ { - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ Increment(Local0) Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ Increment(Local1) @@ -82,7 +82,7 @@ Device(PRID) Name (_ADR, Zero) Method(_GTM, 0) { - NAME(OTBF, Buffer(20) { /* out buffer */ + NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -96,7 +96,7 @@ Device(PRID) CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
/* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ + If(And(PPCR, 0x01)) { /* primary PIO control */ Return(OTBF) }
@@ -108,7 +108,7 @@ Device(PRID) /* save total time of primary PIO slave Timing to PIO spd1 */ Store(GTTM(PPTS), PSD1)
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ Or(BFFG, 0x01, BFFG) Store(DerefOf(Index(UDTT, PDMM)), DSD0) } @@ -116,7 +116,7 @@ Device(PRID) Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ }
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ Or(BFFG, 0x04, BFFG) Store(DerefOf(Index(UDTT, PDSM)), DSD1) } @@ -124,12 +124,12 @@ Device(PRID) Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ }
- Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */
Method(_STM, 3, NotSerialized) { - NAME(INBF, Buffer(20) { /* in buffer */ + NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -143,14 +143,14 @@ Device(PRID) CreateDwordField(INBF, 16, BFFG) /*buffer flag */
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) Divide(Local0, 7, PDMM,) Or(PDCR, 0x01, PDCR) @@ -162,7 +162,7 @@ Device(PRID) } }
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) Divide(Local0, 7, PDSM,) Or(PDCR, 0x02, PDCR) @@ -201,15 +201,15 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } } Return(CMBF) } - } /* End Device(MST) */ + } /* End Device(MST) */
Device(SLAV) { @@ -237,14 +237,14 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } } Return(CMBF) } - } /* End Device(SLAV) */ + } /* End Device(SLAV) */ } #endif diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index dd59225..94eb784 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -64,11 +64,11 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); + 0xFEC20000, 24);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index ecd85ee..325fd83 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -52,38 +52,38 @@ VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 @@ -91,11 +91,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -140,11 +140,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -225,9 +225,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,16 +270,16 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -315,12 +315,12 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -380,9 +380,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -411,9 +411,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -443,11 +443,11 @@ agesawrapper_amdinitlate ( AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */ return (UINT32)Status; @@ -464,9 +464,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -491,12 +491,12 @@ UINT32 agesawrapper_amdinitresume(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -528,7 +528,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -550,16 +550,16 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) UINT32 agesawrapper_amds3laterestore (VOID) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -594,7 +594,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; UINT8 byte;
@@ -631,12 +631,12 @@ UINT32 agesawrapper_amdS3Save(VOID) AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -658,8 +658,8 @@ UINT32 agesawrapper_amdS3Save(VOID)
S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info ( S3DataType, @@ -667,8 +667,8 @@ UINT32 agesawrapper_amdS3Save(VOID) AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; @@ -697,9 +697,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; diff --git a/src/mainboard/amd/olivehill/agesawrapper.h b/src/mainboard/amd/olivehill/agesawrapper.h index 5007510..6db7f33 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.h +++ b/src/mainboard/amd/olivehill/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,27 +30,27 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index ae7f5e9..d107860 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -38,7 +38,7 @@ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -57,34 +57,34 @@ #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #define INSTALL_FT3_SOCKET_SUPPORT FALSE #endif #endif
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent, // as reported by the ACPI _PSD object. For single-link processors, @@ -96,74 +96,74 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
@@ -172,64 +172,64 @@ #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif
-#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
/* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -265,12 +265,12 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ @@ -306,66 +306,66 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL olivehill_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0]) +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&olivehill_gpio[0])
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -380,61 +380,61 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket // #define SEED_A 0x12 HW_RXEN_SEED( @@ -474,8 +474,8 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -501,6 +501,6 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index 5520564..784cd13 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -21,93 +21,93 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index 3bcaaee..a671969 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -46,7 +46,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/olivehill/dsdt.asl b/src/mainboard/amd/olivehill/dsdt.asl index e0c21cf..539ee9a 100644 --- a/src/mainboard/amd/olivehill/dsdt.asl +++ b/src/mainboard/amd/olivehill/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 81caf7d..bf97b88 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -141,7 +141,7 @@ void get_bus_conf(void) for (j = bus_yangtze[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_yangtze = apicid_base; diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index a20bbc6..aa45dba 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_yangtze[6];
@@ -60,7 +60,7 @@ static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) }
static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) + unsigned char id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -88,12 +88,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v)
*(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; #endif - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0); @@ -166,7 +166,7 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
/* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -228,7 +228,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 5eaf460..e8e4191 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -28,17 +28,17 @@
STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, - {AGESA_DO_RESET, fam15tn_Reset }, - {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, - {AGESA_READ_SPD, fam15tn_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } };
diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h index e006441..97bcd3f 100644 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ b/src/mainboard/amd/parmer/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -54,14 +54,14 @@ //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 784f6d9..26c234e 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -155,7 +155,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -164,7 +164,7 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; + AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams; @@ -188,12 +188,12 @@ OemCustomizeInitEarly ( PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (PcieComplexListPtr, - 0, - sizeof(PCIe_COMPLEX_DESCRIPTOR), - &InitEarly->StdHeader); + 0, + sizeof(PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader);
- PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST; - PcieComplexListPtr->SocketId = 0; + PcieComplexListPtr->Flags = DESCRIPTOR_TERMINATE_LIST; + PcieComplexListPtr->SocketId = 0; PcieComplexListPtr->PciePortList = PortList; PcieComplexListPtr->DdiLinkList = DdiList;
diff --git a/src/mainboard/amd/parmer/acpi/mainboard.asl b/src/mainboard/amd/parmer/acpi/mainboard.asl index 040f069..e50d1f7 100644 --- a/src/mainboard/amd/parmer/acpi/mainboard.asl +++ b/src/mainboard/amd/parmer/acpi/mainboard.asl @@ -31,7 +31,7 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl index 108e204..b21ce23 100644 --- a/src/mainboard/amd/parmer/acpi/routing.asl +++ b/src/mainboard/amd/parmer/acpi/routing.asl @@ -72,7 +72,7 @@
/* SB devices */ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, INTC, 0 }, Package(){0x0012FFFF, 1, INTB, 0 },
@@ -150,7 +150,7 @@
/* SB devices in APIC mode */ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 },
diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index d93fecc..96c508b 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -64,7 +64,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write Hudson IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index fcbdded..0e549ac 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -52,38 +52,38 @@ VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 @@ -91,11 +91,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -140,11 +140,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -225,9 +225,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,16 +270,16 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -315,12 +315,12 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -380,9 +380,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -411,9 +411,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -443,11 +443,11 @@ agesawrapper_amdinitlate ( AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */ return (UINT32)Status; @@ -464,9 +464,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -491,12 +491,12 @@ UINT32 agesawrapper_amdinitresume(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -528,7 +528,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -551,16 +551,16 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) UINT32 agesawrapper_amds3laterestore (VOID) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -595,7 +595,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; UINT8 byte;
@@ -633,12 +633,12 @@ UINT32 agesawrapper_amdS3Save(VOID) AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -660,8 +660,8 @@ UINT32 agesawrapper_amdS3Save(VOID)
S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info ( S3DataType, @@ -669,8 +669,8 @@ UINT32 agesawrapper_amdS3Save(VOID) AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; @@ -699,9 +699,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; diff --git a/src/mainboard/amd/parmer/agesawrapper.h b/src/mainboard/amd/parmer/agesawrapper.h index 5007510..6db7f33 100644 --- a/src/mainboard/amd/parmer/agesawrapper.h +++ b/src/mainboard/amd/parmer/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,27 +30,27 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 1a23190..411b9d7 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -58,29 +58,29 @@
#define INSTALL_FM2_SOCKET_SUPPORT FALSE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent, // as reported by the ACPI _PSD object. For single-link processors, @@ -92,145 +92,145 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
// Specify the default values for the VRM controlling the VDDNB plane. // If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
-#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif
-#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -266,23 +266,23 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define DDR2100_FREQUENCY 1050 ///< DDR 2100 #define DDR2133_FREQUENCY 1066 ///< DDR 2133 #define DDR2400_FREQUENCY 1200 ///< DDR 2400 @@ -307,66 +307,66 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0])
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -381,61 +381,61 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -467,8 +467,8 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -494,6 +494,6 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index 5520564..784cd13 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -21,93 +21,93 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 62b37e1..11c7745 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -49,7 +49,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS + device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address end diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index ef2ae6f..8f0f8ac 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index c92fea9..854d0bb 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -130,7 +130,7 @@ void get_bus_conf(void) for (j = bus_hudson[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index d106697..4bdf75d 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6];
@@ -60,7 +60,7 @@ static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) }
static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) + unsigned char id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -88,12 +88,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -189,7 +189,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 700da08..c53a22f 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -99,14 +99,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -231,12 +231,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ b/src/mainboard/amd/persimmon/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/persimmon/acpi/ide.asl b/src/mainboard/amd/persimmon/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/amd/persimmon/acpi/ide.asl +++ b/src/mainboard/amd/persimmon/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 0572335..401c88a 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -474,9 +474,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -505,8 +505,8 @@ agesawrapper_amdinitlate ( AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
@@ -526,12 +526,12 @@ agesawrapper_amdinitresume ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -565,15 +565,15 @@ agesawrapper_amds3laterestore ( ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -609,12 +609,12 @@ agesawrapper_amdS3Save ( AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index f7c7bb2..a254adf 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 258d895..d729d55 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 0578e27..a999aef 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ @@ -258,15 +258,15 @@ static const CODECTBLLIST codec_tablelist[] =
/* set up an ACPI prefered power management profile */ /* from acpi.h - * PM_UNSPECIFIED = 0, - * PM_DESKTOP = 1, - * PM_MOBILE = 2, - * PM_WORKSTATION = 3, - * PM_ENTERPRISE_SERVER = 4, - * PM_SOHO_SERVER = 5, - * PM_APPLIANCE_PC = 6, + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, * PM_PERFORMANCE_SERVER = 7, - * PM_TABLET = 8 + * PM_TABLET = 8 */ #define FADT_PM_PROFILE 1
diff --git a/src/mainboard/amd/pistachio/acpi/ide.asl b/src/mainboard/amd/pistachio/acpi/ide.asl index 7cee00d..5e6d207 100644 --- a/src/mainboard/amd/pistachio/acpi/ide.asl +++ b/src/mainboard/amd/pistachio/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 30274c3..f87c3ab 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/pistachio/cmos.layout b/src/mainboard/amd/pistachio/cmos.layout index 86aadf5..981f476 100644 --- a/src/mainboard/amd/pistachio/cmos.layout +++ b/src/mainboard/amd/pistachio/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index 760e5ab..51a4348 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -49,7 +49,7 @@ chip northbridge/amd/amdk8/root_complex device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index 3e5ba54..8f5b42a 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -380,16 +380,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -762,7 +762,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1141,7 +1141,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1163,8 +1163,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1174,8 +1174,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1183,8 +1183,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1192,8 +1192,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1202,8 +1202,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1500,23 +1500,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1525,7 +1525,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 75f92bd..d7f5d3b 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -31,7 +31,7 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); + u8 val); #define ADT7475_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address) #define ADT7475_write_byte(address, val) \ @@ -96,35 +96,35 @@ static void set_thermal_config(void)
/* remote 1 low temp limit */ ADT7475_write_byte(0x4e, 0x00); - /* remote 1 High temp limit (90C) */ + /* remote 1 High temp limit (90C) */ ADT7475_write_byte(0x4f, 0x9a);
/* remote2 Low Temp Limit */ ADT7475_write_byte(0x52, 0x00); - /* remote2 High Limit (90C) */ + /* remote2 High Limit (90C) */ ADT7475_write_byte(0x53, 0x9a);
- /* remote 1 therm temp limit (95C) */ + /* remote 1 therm temp limit (95C) */ ADT7475_write_byte(0x6a, 0x9f); - /* remote 2 therm temp limit (95C) */ + /* remote 2 therm temp limit (95C) */ ADT7475_write_byte(0x6c, 0x9f);
- /* PWM 1 minimum duty cycle (37%) */ + /* PWM 1 minimum duty cycle (37%) */ ADT7475_write_byte(0x64, 0x60); - /* PWM 1 Maximum duty cycle (100%) */ + /* PWM 1 Maximum duty cycle (100%) */ ADT7475_write_byte(0x38, 0xff); - /* PWM 3 minimum duty cycle (37%) */ + /* PWM 3 minimum duty cycle (37%) */ ADT7475_write_byte(0x66, 0x60); - /* PWM 3 Maximum Duty Cycle (100%) */ + /* PWM 3 Maximum Duty Cycle (100%) */ ADT7475_write_byte(0x3a, 0xff);
- /* Remote 1 temperature Tmin (32C) */ + /* Remote 1 temperature Tmin (32C) */ ADT7475_write_byte(0x67, 0x60); - /* Remote 2 temperature Tmin (32C) */ + /* Remote 2 temperature Tmin (32C) */ ADT7475_write_byte(0x69, 0x60); - /* remote 1 Trange (53C ramp range) */ + /* remote 1 Trange (53C ramp range) */ ADT7475_write_byte(0x5f, 0xe8); - /* remote 2 Trange (53C ramp range) */ + /* remote 2 Trange (53C ramp range) */ ADT7475_write_byte(0x61, 0xe8);
/* PWM2 Duty cycle */ diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 8ef9138..5866da7 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/pistachio/resourcemap.c b/src/mainboard/amd/pistachio/resourcemap.c index 1507994..efaecd3 100644 --- a/src/mainboard/amd/pistachio/resourcemap.c +++ b/src/mainboard/amd/pistachio/resourcemap.c @@ -31,21 +31,21 @@ static void setup_pistachio_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -65,25 +65,25 @@ static void setup_pistachio_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -104,27 +104,27 @@ static void setup_pistachio_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -145,21 +145,21 @@ static void setup_pistachio_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -176,23 +176,23 @@ static void setup_pistachio_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -206,23 +206,23 @@ static void setup_pistachio_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -236,35 +236,35 @@ static void setup_pistachio_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/rumba/cmos.layout b/src/mainboard/amd/rumba/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/amd/rumba/cmos.layout +++ b/src/mainboard/amd/rumba/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index a7a352f..441e005 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -9,11 +9,11 @@ chip northbridge/amd/gx2 device pci 1.1 on end chip southbridge/amd/cs5536 register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci d.0 on end # Realtek 8139 LAN + device pci f.0 on end # ISA Bridge + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI end end diff --git a/src/mainboard/amd/rumba/irq_tables.c b/src/mainboard/amd/rumba/irq_tables.c index 5c045cc..57444f4 100644 --- a/src/mainboard/amd/rumba/irq_tables.c +++ b/src/mainboard/amd/rumba/irq_tables.c @@ -27,23 +27,23 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x2, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 8c97109..f1c5e69 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -29,10 +29,10 @@ static void init(struct device *dev)
static void mainboard_enable(struct device *dev) { - dev->ops->init = init; + dev->ops->init = init; }
struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, };
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl index 77958b2..bd4d96a 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111.asl @@ -2,171 +2,171 @@ * Copyright 2005 AMD */ //AMD8111 - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} - }) - - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00} - }) + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} + }) + + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00} + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { + Method (_PRT, 0, NotSerialized) + { If (LEqual (^DNCG, Ones)) { Store (DADD(_SB.PCI0.SBDN, 0x0001ffff), Local0) // Update the Device Number according to SBDN - Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
Store (0x00, ^DNCG)
}
- If (LNot (PICF)) { + If (LNot (PICF)) { Return (PICM) } - Else { + Else { Return (APIC) } - } + }
- Device (SBC3) - { - /* acpi smbus it should be 0x00040003 if 8131 present */ + Device (SBC3) + { + /* acpi smbus it should be 0x00040003 if 8131 present */ Method (_ADR, 0, NotSerialized) { Return (DADD(_SB.PCI0.SBDN, 0x00010003)) } - OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) - Field (PIRQ, ByteAcc, Lock, Preserve) - { - PIBA, 8, - PIDC, 8 - } + OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) + Field (PIRQ, ByteAcc, Lock, Preserve) + { + PIBA, 8, + PIDC, 8 + } /* - OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) - Field (TS3_, DWordAcc, NoLock, Preserve) - { - PTS3, 16 - } + OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + Field (TS3_, DWordAcc, NoLock, Preserve) + { + PTS3, 16 + } */ - } - - Device (HPET) - { - Name (HPT, 0x00) - Name (_HID, EisaId ("PNP0103")) - Name (_UID, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) - }) - Return (BUF0) - } - } + } + + Device (HPET) + { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } + }
#include "amd8111_pic.asl"
#include "amd8111_isa.asl"
- Device (TP2P) - { - /* 8111 P2P and it should 0x00030000 when 8131 present*/ - Method (_ADR, 0, NotSerialized) - { + Device (TP2P) + { + /* 8111 P2P and it should 0x00030000 when 8131 present*/ + Method (_ADR, 0, NotSerialized) + { Return (DADD(_SB.PCI0.SBDN, 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } - Else { Return (Package (0x02) { 0x08, 0x01 }) } - } - - Device (USB0) - { - Name (_ADR, 0x00000000) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Device (USB1) - { - Name (_ADR, 0x00000001) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Name (APIC, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4 - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3 - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } - }) - - Name (PICM, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //Slot 4 - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, //Slot 3 - Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } - }) - - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } + Else { Return (Package (0x02) { 0x08, 0x01 }) } + } + + Device (USB0) + { + Name (_ADR, 0x00000000) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Device (USB1) + { + Name (_ADR, 0x00000001) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Name (APIC, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + + Name (PICM, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //Slot 4 + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, //Slot 3 + Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } + }) + + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl index 56c0a16..883bfd8 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl @@ -6,174 +6,174 @@ */ //AMD8111 isa
- Device (ISA) - { - /* lpc 0x00040000 */ - Method (_ADR, 0, NotSerialized) - { + Device (ISA) + { + /* lpc 0x00040000 */ + Method (_ADR, 0, NotSerialized) + { Return (DADD(_SB.PCI0.SBDN, 0x00010000)) - } - - OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers - Field (PIRY, ByteAcc, NoLock, Preserve) - { - Z000, 2, // Parallel Port Range - , 1, - ECP, 1, // ECP Enable - FDC1, 1, // Floppy Drive Controller 1 - FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), - Z001, 3, // Serial Port A Range - SAEN, 1, // Serial Post A Enabled - Z002, 3, // Serial Port B Range - SBEN, 1 // Serial Post B Enabled - } - - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) - IRQ (Edge, ActiveHigh, Exclusive) {2} - }) - } - - Device (DMA1) - { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) - IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) - IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer16) {4} - }) - } - - Device (TMR) - { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) - IRQ (Edge, ActiveHigh, Exclusive) {0} - }) - } - - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) - IRQ (Edge, ActiveHigh, Exclusive) {8} - }) - } - - Device (SPKR) - { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) - }) - } - - Device (COPR) - { - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) - IRQ (Edge, ActiveHigh, Exclusive) {13} - }) - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x00) - Name (SYR1, ResourceTemplate () - { - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) - IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) - IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) - IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - }) - Method (_CRS, 0, NotSerialized) - { - Return (SYR1) - } - } - - Device (MEM) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF - Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - }) + } + + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) + { + Z000, 2, // Parallel Port Range + , 1, + ECP, 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) + }) + } + + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (SYR1, ResourceTemplate () + { + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + }) + Method (_CRS, 0, NotSerialized) + { + Return (SYR1) + } + } + + Device (MEM) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + }) // Read the Video Memory length - CreateDWordField (BUF0, 0x14, CLEN) - CreateDWordField (BUF0, 0x10, CBAS) - - ShiftLeft (VGA1, 0x09, Local0) - Store (Local0, CLEN) - - Return (BUF0) - } - } - - Device (PS2M) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQNoFlags () {12} - }) - Method (_STA, 0, NotSerialized) - { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { Return (0x0F) } - Else { Return (0x00) } - } - } - - Device (PS2K) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) + { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { Return (0x0F) } + Else { Return (0x00) } + } + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } #include "superio.asl"
- } + }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl index 228f3f8..5ad094a 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_pic.asl @@ -3,358 +3,358 @@ */ //AMD8111 pic LNKA B C D
- Device (LNKA) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { // Routing enable - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) - Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKB) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) - ShiftLeft (Local1, 0x04, Local1) - Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKC) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) - Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) - } - } - - Device (LNKD) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) - ShiftLeft (Local1, 0x04, Local1) - Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) - } - } + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { // Routing enable + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) + Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) + ShiftLeft (Local1, 0x04, Local1) + Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) + Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) + ShiftLeft (Local1, 0x04, Local1) + Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) + } + }
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl index 172f0bf..03f0a0d 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131.asl @@ -2,118 +2,118 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + }
- Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + }
- Name (APIC, Package (0x14) - { + Name (APIC, Package (0x14) + { // Slot A - PIRQ BCDA - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot A - PIRQ BCDA - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
//Cypress Slot B - PIRQ CDAB - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
//Cypress Slot C - PIRQ DABC - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
//Cypress Slot D - PIRQ ABCD - Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } - }) - Name (PICM, Package (0x14) - { - Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKB, 0x00 },//Slot 2 - Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //? + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B } + }) + Name (PICM, Package (0x14) + { + Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKB, 0x00 },//Slot 2 + Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, _SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0006FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0006FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
- Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + }
- Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + }
- Name (APIC, Package (0x04) - { + Name (APIC, Package (0x04) + { // Slot A - PIRQ ABCD - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl index 8b8bc9f..dbcc381 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8131_2.asl @@ -2,113 +2,113 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - }) + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl index e5cfe3c..1a7cd2f 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8132_2.asl @@ -2,113 +2,113 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - }) + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl index ce85502..577d35a 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl +++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8151.asl @@ -1,29 +1,29 @@ // AMD8151 - Device (AGPB) - { - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } + Device (AGPB) + { + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + }
- Name (APIC, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
diff --git a/src/mainboard/amd/serengeti_cheetah/cmos.layout b/src/mainboard/amd/serengeti_cheetah/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/amd/serengeti_cheetah/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index 1fea190..7c0065d 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end + end + end device domain 0 on subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdk8 @@ -28,132 +28,132 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off # CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 - end + end end end device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-2-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-2-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-3-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-3-1 - device i2c 57 on end - end - end + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end end end # acpi device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
- device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end # device pci 19.0 + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0
- device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end
end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end
end
diff --git a/src/mainboard/amd/serengeti_cheetah/dsdt.asl b/src/mainboard/amd/serengeti_cheetah/dsdt.asl index da14fe8..160e1bb 100644 --- a/src/mainboard/amd/serengeti_cheetah/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah/dsdt.asl @@ -5,10 +5,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) { Scope (_PR) { - Processor (CPU0, 0x00, 0x0000C010, 0x06) {} - Processor (CPU1, 0x01, 0x00000000, 0x00) {} - Processor (CPU2, 0x02, 0x00000000, 0x00) {} - Processor (CPU3, 0x03, 0x00000000, 0x00) {} + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {}
}
@@ -21,8 +21,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Scope (_SB) { - Device (PCI0) - { + Device (PCI0) + { /* BUS0 root bus */
External (BUSN) @@ -36,174 +36,174 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (CBST)
- Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - _SB.OSTP () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (_SB.GMEM (0x00, _SB.PCI0.SBLK), BUF0, Local1) - Concatenate (_SB.GIOR (0x00, _SB.PCI0.SBLK), Local1, Local2) - Concatenate (_SB.GWBN (0x00, _SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + _SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (_SB.GMEM (0x00, _SB.PCI0.SBLK), BUF0, Local1) + Concatenate (_SB.GIOR (0x00, _SB.PCI0.SBLK), Local1, Local2) + Concatenate (_SB.GWBN (0x00, _SB.PCI0.SBLK), Local2, Local3) + Return (Local3) }
#include "acpi/pci0_hc.asl"
- } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (_SB.PCI0.CBST) - } + } + Device (PCI1) + { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Return (_SB.PCI0.CBST) + } Name (_BBN, 0x00) - } + }
}
Scope (_GPE) { - Method (_L08, 0, NotSerialized) - { - Notify (_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (_SB.PCI0.PG0A, 0x02) - } + Method (_L08, 0, NotSerialized) + { + Notify (_SB.PCI0, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (_SB.PCI0.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (_SB.PCI0.PG0A, 0x02) + } }
Method (_PTS, 1, NotSerialized) { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) } /* Method (_WAK, 1, NotSerialized) { - Or (Arg0, 0xE0, Local0) - Store (Local0, DBG1) + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) } */ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method { - Store (Arg0, PICF) + Store (Arg0, PICF) }
OperationRegion (DEBG, SystemIO, 0x80, 0x01) Field (DEBG, ByteAcc, Lock, Preserve) { - DBG1, 8 + DBG1, 8 }
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) Field (EXTM, WordAcc, Lock, Preserve) { - AMEM, 32 + AMEM, 32 }
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) Field (VGAM, ByteAcc, Lock, Preserve) { - VGA1, 8 + VGA1, 8 }
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), - FLG0, 8 + Offset (0x10), + FLG0, 8 }
OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, - IRQR, 1 + , 4, + IRQR, 1 }
OperationRegion (Z007, SystemIO, 0x21, 0x01) Field (Z007, ByteAcc, NoLock, Preserve) { - Z008, 8 + Z008, 8 }
OperationRegion (Z009, SystemIO, 0xA1, 0x01) Field (Z009, ByteAcc, NoLock, Preserve) { - Z00A, 8 + Z00A, 8 }
#include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/amd/serengeti_cheetah/fadt.c b/src/mainboard/amd/serengeti_cheetah/fadt.c index f677b4e..d6ff1f3 100644 --- a/src/mainboard/amd/serengeti_cheetah/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah/fadt.c @@ -43,8 +43,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->pm1b_cnt_blk = 0x0000; fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0;
fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; @@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16;
- fadt->cst_cnt = 0xe3; + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; fadt->flush_size = 0; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f5cd846..cc72167 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -19,23 +19,23 @@ static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -109,8 +109,8 @@ void get_bus_conf(void) m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8111_0, sysconf.sbdn); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8111_0, sysconf.sbdn); }
/* 8132-1 */ @@ -119,8 +119,8 @@ void get_bus_conf(void) m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3); }
/* 8132-2 */ @@ -129,8 +129,8 @@ void get_bus_conf(void) m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3 + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3 + 1); }
/* HT chain 1 */ @@ -157,11 +157,11 @@ void get_bus_conf(void) PCI_DEVFN(m->sbdn3a[j], 0)); if (dev) { m->bus_8132a[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j]); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j]); }
/* 8132-2 */ @@ -170,11 +170,11 @@ void get_bus_conf(void) PCI_DEVFN(m->sbdn3a[j] + 1, 0)); if (dev) { m->bus_8132a[j][2] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j] + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j] + 1); }
break; @@ -190,12 +190,12 @@ void get_bus_conf(void)
if (dev) { m->bus_8151[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); - // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); + pci_read_config8(dev, PCI_SECONDARY_BUS); + // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8151[j][0], m->sbdn5[j] + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8151[j][0], m->sbdn5[j] + 1); }
break; diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 637f980..d2e46dd 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -17,8 +17,8 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; + pirq_info->bus = bus; + pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -30,7 +30,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->rfu = rfu; }
@@ -44,8 +44,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
struct mb_sysconf_t *m;
@@ -53,12 +53,12 @@ unsigned long write_pirq_routing_table(unsigned long addr)
m = sysconf.mb;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -81,62 +81,62 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0;
- { - device_t dev; - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ3 - PINTB = IRQ5 - PINTC = IRQ10 - PINTD = IRQ11 - */ - pci_write_config16(dev, 0x56, 0xba53); - } - } + { + device_t dev; + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ3 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ11 + */ + pci_write_config16(dev, 0x56, 0xba53); + } + }
//pci bridge - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; - pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; + pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; - pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; + printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; + pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); + write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++;
//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++;
int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff;
- write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - j++; + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + j++;
- } + }
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h index 3042dd0..402ac68 100644 --- a/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h @@ -9,18 +9,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1;
- unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3];
- unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2];
- unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2];
- unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7];
};
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 866875d..9e612c8 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -12,15 +12,15 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, j, bus_isa; struct mb_sysconf_t *m;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
@@ -30,50 +30,50 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 - { - device_t dev; + { + device_t dev; struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); - if (dev) { + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); - if (dev) { + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); } - } + }
- j = 0; + j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue;
- switch(sysconf.hcid[i]) { - case 1: // 8132 + switch(sysconf.hcid[i]) { + case 1: // 8132 case 3: // 8131 - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); - } - } - break; - } - j++; - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); + } + } + break; + } + j++; + }
}
@@ -81,76 +81,76 @@ static void *smp_write_config_table(void *v)
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
//Slot 3 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + }
//Slot 4 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + }
//Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); // + }
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 - } - - j = 0; - - for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - int ii; - device_t dev; - struct resource *res; - switch(sysconf.hcid[i]) { - case 1: + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + } + + j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + int ii; + device_t dev; + struct resource *res; + switch(sysconf.hcid[i]) { + case 1: case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // - } - } - } - - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 - } - } - } - - break; - case 2: - - // Slot AGP - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); - break; - } - - j++; - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 1 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + } + } + } + + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 2 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + } + } + } + + break; + case 2: + + // Slot AGP + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); + break; + } + + j++; + }
diff --git a/src/mainboard/amd/serengeti_cheetah/resourcemap.c b/src/mainboard/amd/serengeti_cheetah/resourcemap.c index be11b68..4503b5c 100644 --- a/src/mainboard/amd/serengeti_cheetah/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah/resourcemap.c @@ -16,21 +16,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -50,25 +50,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -89,27 +89,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -130,21 +130,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -161,23 +161,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -191,23 +191,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -221,35 +221,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070013, // AMD 8151 on link0 of CPU 1 diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 8d985b7..c11a3f1 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -29,8 +29,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -38,36 +38,36 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); }
#if 0 static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 - int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - } while ((ret!=0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/amdk8.h" @@ -91,36 +91,36 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + // four node + RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, + RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif
};
struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
@@ -129,37 +129,37 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_mb_resource_map(); + setup_mb_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif
#if CONFIG_SET_FIDVID @@ -168,23 +168,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) {
- { + { /* Read FIDVID_STATUS */ - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + }
enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid);
- // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + }
} else { print_debug("Changing FIDVID not supported\n"); @@ -195,15 +195,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -217,29 +217,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif
#if 0 - for(i=1;i<256;i<<=1) { - change_i2c_mux(i); - dump_smbus_registers(); - } + for(i=1;i<256;i<<=1) { + change_i2c_mux(i); + dump_smbus_registers(); + } #endif
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - print_pci_devices(); + print_pci_devices(); #endif
#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl index 791454c..da53836 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt2.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt2.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci2_hc.asl" - } + } }
} diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl index 28fe5f4..5d297f0 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt3.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt3.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci3_hc.asl" - } + } }
} diff --git a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl index 93abb7f..917a205 100644 --- a/src/mainboard/amd/serengeti_cheetah/ssdt4.asl +++ b/src/mainboard/amd/serengeti_cheetah/ssdt4.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci4_hc.asl" - } + } }
} diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl index e39c119..48269c7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl @@ -34,8 +34,8 @@ Field (PIRY, ByteAcc, NoLock, Preserve) { Z000, 2, // Parallel Port Range - , 1, - ECP, 1, // ECP Enable + , 1, + ECP, 1, // ECP Enable FDC1, 1, // Floppy Drive Controller 1 FDC2, 1, // Floppy Drive Controller 2 Offset (0x01), diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl index 553a695..f481235 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl @@ -85,7 +85,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) 0x000CFFFF, // Address Range Maximum 0x00000000, // Address Translation Offset 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c index 29de236..b7298ae 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/fadt.c @@ -65,8 +65,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->pm1b_cnt_blk = 0x0000; fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0;
fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; @@ -76,7 +76,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16;
- fadt->cst_cnt = 0x00;// SMM is not used for p-state control + fadt->cst_cnt = 0x00;// SMM is not used for p-state control // fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c index 7cac10e..f47c5ba 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index c5adab3..5deb993 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -347,8 +347,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 2aca184..c387cc9 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -97,14 +97,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -147,7 +147,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (CurrNodeOffset != 0) { CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; + return AGESA_BOUNDS_CHK; } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points @@ -163,18 +163,18 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (FreedNodeOffset != 0) { FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } } PrevNodeOffset = FreedNodeOffset; FreedNodeOffset = FreedNodePtr->NextNodeOffset; @@ -191,23 +191,23 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* If BestFitNode is larger than the requested buffer, fragment the node further */ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
- NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; }
/* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; }
/* Add BestFitNode to the list of Allocated nodes */ @@ -227,12 +227,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -289,8 +289,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -305,7 +305,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -345,8 +345,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -379,7 +379,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; @@ -387,9 +387,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -445,14 +445,14 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; @@ -460,10 +460,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; @@ -540,12 +540,12 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; + UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; - UINT8 Data8; + UINT8 Data8; UINT16 Data16;
FcnData = Data; @@ -566,51 +566,51 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; } break; case 6: switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; } break; case 7: switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; } break; } diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h index be14425..260731a 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.h +++ b/src/mainboard/amd/south_station/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; @@ -68,12 +68,12 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ b/src/mainboard/amd/south_station/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index a8511ea..2f51b4c 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -47,68 +47,68 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) - }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) - }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } };
PCIe_DDI_DESCRIPTOR DdiList [] = { - /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) - }, - /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1) - } + /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) + }, + /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1) + } };
PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
// GNB PCIe topology Porting @@ -130,25 +130,25 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + 0, + sizeof(Brazos), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 5efcd7d..e81bc3e 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -25,44 +25,44 @@ #include "amdlib.h"
//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/amd/south_station/acpi/ide.asl b/src/mainboard/amd/south_station/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/amd/south_station/acpi/ide.asl +++ b/src/mainboard/amd/south_station/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index 635b632..ba4ae93 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -453,9 +453,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h index b02fd5e..442f46f 100644 --- a/src/mainboard/amd/south_station/agesawrapper.h +++ b/src/mainboard/amd/south_station/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,26 +30,26 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 87f9b88..c74238a 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -61,10 +61,10 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE @@ -77,146 +77,146 @@ #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
/* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
/* @@ -271,54 +271,54 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data. #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -333,57 +333,57 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), @@ -410,8 +410,8 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -437,7 +437,7 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
@@ -447,7 +447,7 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 60335d7..9fcdf50 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -17,46 +17,46 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge
- chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f device pnp 4e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -79,7 +79,7 @@ chip northbridge/amd/agesa/family14/root_complex io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + end # f81865f end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 @@ -92,21 +92,21 @@ chip northbridge/amd/agesa/family14/root_complex register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 +# end # device pci 18.0 # These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end
- register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }"
- end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index f7c7bb2..a254adf 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index df8ce6e..0a375c1 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -125,7 +125,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index e9175d8..3a2ccf5 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 byte; @@ -74,7 +74,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -85,7 +85,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index a8888d2..46a38e3 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 60a33ed..00f2e4d 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -28,17 +28,17 @@
STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, - {AGESA_DO_RESET, fam15tn_Reset }, - {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, - {AGESA_READ_SPD, fam15tn_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } };
diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h index e006441..97bcd3f 100644 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ b/src/mainboard/amd/thatcher/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -54,14 +54,14 @@ //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index ec5d68d..bf6f4d4 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -143,10 +143,10 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { };
PCIe_COMPLEX_DESCRIPTOR Trinity = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
/*---------------------------------------------------------------------------------------*/ @@ -161,7 +161,7 @@ PCIe_COMPLEX_DESCRIPTOR Trinity = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -170,10 +170,10 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *TrinityPcieComplexListPtr; - VOID *TrinityPciePortPtr; - VOID *TrinityPcieDdiPtr; + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
@@ -196,25 +196,25 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity); - TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr, - 0, - sizeof(Trinity), - &InitEarly->StdHeader); + 0, + sizeof(Trinity), + &InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/amd/thatcher/acpi/mainboard.asl b/src/mainboard/amd/thatcher/acpi/mainboard.asl index 040f069..e50d1f7 100644 --- a/src/mainboard/amd/thatcher/acpi/mainboard.asl +++ b/src/mainboard/amd/thatcher/acpi/mainboard.asl @@ -31,7 +31,7 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/amd/thatcher/acpi/routing.asl b/src/mainboard/amd/thatcher/acpi/routing.asl index 108e204..b21ce23 100644 --- a/src/mainboard/amd/thatcher/acpi/routing.asl +++ b/src/mainboard/amd/thatcher/acpi/routing.asl @@ -72,7 +72,7 @@
/* SB devices */ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, INTC, 0 }, Package(){0x0012FFFF, 1, INTB, 0 },
@@ -150,7 +150,7 @@
/* SB devices in APIC mode */ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 },
diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index d93fecc..96c508b 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -64,7 +64,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write Hudson IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 6331197..9f51262 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -52,38 +52,38 @@ VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 @@ -91,11 +91,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -140,11 +140,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -223,9 +223,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -268,16 +268,16 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -313,12 +313,12 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -378,9 +378,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -409,9 +409,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -441,11 +441,11 @@ agesawrapper_amdinitlate ( AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */ return (UINT32)Status; @@ -462,9 +462,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -489,12 +489,12 @@ UINT32 agesawrapper_amdinitresume(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -528,7 +528,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -550,16 +550,16 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) UINT32 agesawrapper_amds3laterestore (VOID) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -596,7 +596,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; UINT8 byte;
@@ -633,12 +633,12 @@ UINT32 agesawrapper_amdS3Save(VOID) AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -660,8 +660,8 @@ UINT32 agesawrapper_amdS3Save(VOID)
S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); #if 1 /* TODO: Save the params to NvStorage */ Status = OemAgesaSaveS3Info ( S3DataType, @@ -669,8 +669,8 @@ UINT32 agesawrapper_amdS3Save(VOID) AmdS3SaveParamsPtr->S3DataBlock.NvStorage); #endif printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; @@ -702,9 +702,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h index 5007510..6db7f33 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.h +++ b/src/mainboard/amd/thatcher/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,27 +30,27 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 87f0460..c840604 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -58,29 +58,29 @@
#define INSTALL_FM2_SOCKET_SUPPORT FALSE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent, // as reported by the ACPI _PSD object. For single-link processors, @@ -92,145 +92,145 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
// Specify the default values for the VRM controlling the VDDNB plane. // If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
-#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif
-#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -266,23 +266,23 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define DDR2100_FREQUENCY 1050 ///< DDR 2100 #define DDR2133_FREQUENCY 1066 ///< DDR 2133 #define DDR2400_FREQUENCY 1200 ///< DDR 2400 @@ -307,66 +307,66 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33 #define FCH_NO_XHCI_SUPPORT TRUE GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&thatcher_gpio[0])
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -381,61 +381,61 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -467,8 +467,8 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -494,7 +494,7 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
@@ -504,7 +504,7 @@ UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0 */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index 5520564..784cd13 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -21,93 +21,93 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 330ee6b..1c945b8 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -49,7 +49,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS + device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address end @@ -59,7 +59,7 @@ chip northbridge/amd/agesa/family15tn/root_complex end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + device pci 14.3 on # LPC 0x439d chip superio/smsc/lpc47n217 device pnp 2e.3 off # Parallel io 0x60 = 0x378 diff --git a/src/mainboard/amd/thatcher/dsdt.asl b/src/mainboard/amd/thatcher/dsdt.asl index ef2ae6f..8f0f8ac 100644 --- a/src/mainboard/amd/thatcher/dsdt.asl +++ b/src/mainboard/amd/thatcher/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index c92fea9..854d0bb 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -130,7 +130,7 @@ void get_bus_conf(void) for (j = bus_hudson[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 10d2fea..c0886ad 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6];
@@ -60,7 +60,7 @@ static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) }
static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) + unsigned char id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -88,12 +88,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -189,7 +189,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 3c2fc52..12818c7 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -81,12 +81,12 @@ config RAMBASE default 0x200000
config VGA_BIOS - bool - default n + bool + default n
config VGA_BIOS_ID - string - depends on VGA_BIOS - default "1002,9615" + string + depends on VGA_BIOS + default "1002,9615"
endif # BOARD_AMD_TILAPIA_FAM10 diff --git a/src/mainboard/amd/tilapia_fam10/acpi/ide.asl b/src/mainboard/amd/tilapia_fam10/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi/ide.asl +++ b/src/mainboard/amd/tilapia_fam10/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/tilapia_fam10/acpi_tables.c b/src/mainboard/amd/tilapia_fam10/acpi_tables.c index b305b40..67dfda3 100644 --- a/src/mainboard/amd/tilapia_fam10/acpi_tables.c +++ b/src/mainboard/amd/tilapia_fam10/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/amd/tilapia_fam10/cmos.layout b/src/mainboard/amd/tilapia_fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/amd/tilapia_fam10/cmos.layout +++ b/src/mainboard/amd/tilapia_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 9315440..02c2ce5 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index e6816b0..f37ae6d 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1655,23 +1655,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1680,7 +1680,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 48e4c17..eff18ea 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -28,7 +28,7 @@ #include "southbridge/amd/sb700/smbus.h"
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -92,7 +92,7 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0x7e, word); }
-#if 0 /* TODO: */ +#if 0 /* TODO: */ /******************************************************** * tilapia uses SB700 GPIO8 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to @@ -186,7 +186,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -198,7 +198,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/tilapia_fam10/resourcemap.c b/src/mainboard/amd/tilapia_fam10/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/amd/tilapia_fam10/resourcemap.c +++ b/src/mainboard/amd/tilapia_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 0c6126b..7296d4f 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -236,8 +236,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 7d49c07..5df1d9a 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -27,15 +27,15 @@ #include "Hudson-2.h"
#ifndef SB_GPIO_REG01 -#define SB_GPIO_REG01 1 +#define SB_GPIO_REG01 1 #endif
#ifndef SB_GPIO_REG24 -#define SB_GPIO_REG24 24 +#define SB_GPIO_REG24 24 #endif
#ifndef SB_GPIO_REG27 -#define SB_GPIO_REG27 27 +#define SB_GPIO_REG27 27 #endif
STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -152,12 +152,12 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -174,14 +174,14 @@ AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -224,7 +224,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (CurrNodeOffset != 0) { CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; + return AGESA_BOUNDS_CHK; } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points @@ -240,18 +240,18 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (FreedNodeOffset != 0) { FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } } PrevNodeOffset = FreedNodeOffset; FreedNodeOffset = FreedNodePtr->NextNodeOffset; @@ -268,23 +268,23 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* If BestFitNode is larger than the requested buffer, fragment the node further */ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
- NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; }
/* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; }
/* Add BestFitNode to the list of Allocated nodes */ @@ -304,12 +304,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -366,8 +366,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -382,7 +382,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -422,8 +422,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -456,7 +456,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); return Status; @@ -464,9 +464,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -518,13 +518,13 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16;
FcnData = Data; MemData = ConfigPtr; @@ -532,10 +532,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; @@ -580,12 +580,12 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; + UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; - UINT8 Data8; + UINT8 Data8; UINT16 Data16;
FcnData = Data; @@ -606,15 +606,15 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - while (!(Data8 & BIT7)) { - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); - } - // GPIO44: PE_GPIO0 MXM Reset - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); + while (!(Data8 & BIT7)) { + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28); + } + // GPIO44: PE_GPIO0 MXM Reset + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); + Status = AGESA_SUCCESS; } } else { Status = AGESA_UNSUPPORTED; @@ -625,8 +625,8 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); //DE-Assert ALL PCIE RESET // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // APU GPP1 (Dev 5) Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01); @@ -646,15 +646,15 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8); - Status = AGESA_SUCCESS; + Status = AGESA_SUCCESS; } // Travis Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24); - Data8 &= ~(UINT8)BIT6 ; + Data8 &= ~(UINT8)BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8); //Assert ALL PCIE RESET // APU GPP0 (Dev 4) - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // APU GPP1 (Dev 5) diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.h b/src/mainboard/amd/torpedo/BiosCallOuts.h index a68f0f1..9646090 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.h +++ b/src/mainboard/amd/torpedo/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; @@ -70,7 +70,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
// These registers are not defined in cimx/SB900/Hudson-2.h -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG25 25 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG25 25 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index cfcf3cb..5f7f0af 100644 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -20,89 +20,89 @@ if BOARD_AMD_TORPEDO
config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select ARCH_X86 - select DIMM_DDR3 - select DIMM_UNREGISTERED + select DIMM_DDR3 + select DIMM_UNREGISTERED select CPU_AMD_AGESA_FAMILY12 select NORTHBRIDGE_AMD_AGESA_FAMILY12 select SOUTHBRIDGE_AMD_CIMX_SB900 select SUPERIO_SMSC_KBC1100 - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT - select HAVE_ACPI_TABLES + select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select GFXUMA + select GFXUMA
config MAINBOARD_DIR - string - default amd/torpedo + string + default amd/torpedo
config APIC_ID_OFFSET - hex - default 0x0 + hex + default 0x0
config MAINBOARD_PART_NUMBER - string - default "Torpedo" + string + default "Torpedo"
config HW_MEM_HOLE_SIZEK - hex - default 0x200000 + hex + default 0x200000
config MAX_CPUS - int - default 4 + int + default 4
config MAX_PHYSICAL_CPUS - int - default 1 + int + default 1
config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n + bool + default n
config MEM_TRAIN_SEQ - int - default 2 + int + default 2
config SB_HT_CHAIN_ON_BUS0 - int - default 1 + int + default 1
config HT_CHAIN_END_UNITID_BASE - hex - default 0x1 + hex + default 0x1
config HT_CHAIN_UNITID_BASE - hex - default 0x0 + hex + default 0x0
config IRQ_SLOT_COUNT - int - default 11 + int + default 11
config RAMTOP - hex - default 0x1000000 + hex + default 0x1000000
config HEAP_SIZE - hex - default 0xc0000 + hex + default 0xc0000
config RAMBASE - hex - default 0x200000 + hex + default 0x200000
config SIO_PORT - hex - default 0x2e + hex + default 0x2e
config ONBOARD_VGA_IS_PRIMARY bool diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 1812921..677757e 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -17,15 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB + #define BIOS_SIZE 0x04 //04 - 1MB #endif -#define LEGACY_FREE 0x00 +#define LEGACY_FREE 0x00 #if !CONFIG_ONBOARD_USB30 - #define XHCI_SUPPORT 0x01 + #define XHCI_SUPPORT 0x01 #endif
-//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 +//#define ACPI_SLEEP_TRAP 0x01 // No sleep trap smi support in coreboot. +//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
/** * Module Specific Defines for platform BIOS @@ -38,9 +38,9 @@ * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 */ #ifdef MOVE_PCIEBAR_TO_F0000000 - #define PCIEX_BASE_ADDRESS 0xF7000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS 0xE0000000 + #define PCIEX_BASE_ADDRESS 0xE0000000 #endif
/** @@ -48,7 +48,7 @@ * */ #ifndef SMBUS0_BASE_ADDRESS - #define SMBUS0_BASE_ADDRESS 0xB00 + #define SMBUS0_BASE_ADDRESS 0xB00 #endif
/** @@ -56,7 +56,7 @@ * */ #ifndef SMBUS1_BASE_ADDRESS - #define SMBUS1_BASE_ADDRESS 0xB20 + #define SMBUS1_BASE_ADDRESS 0xB20 #endif
/** @@ -64,7 +64,7 @@ * */ #ifndef SIO_PME_BASE_ADDRESS - #define SIO_PME_BASE_ADDRESS 0xE00 + #define SIO_PME_BASE_ADDRESS 0xE00 #endif
/** @@ -72,7 +72,7 @@ * */ #ifndef SPI_BASE_ADDRESS - #define SPI_BASE_ADDRESS 0xFEC10000 + #define SPI_BASE_ADDRESS 0xFEC10000 #endif
/** @@ -80,7 +80,7 @@ * */ #ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address + #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address #endif
/** @@ -88,7 +88,7 @@ * */ #ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address #endif
/** @@ -96,129 +96,129 @@ * */ #ifdef ALT_ADDR_400 - #define ACPI_BLK_BASE 0x400 + #define ACPI_BLK_BASE 0x400 #else - #define ACPI_BLK_BASE 0x800 + #define ACPI_BLK_BASE 0x800 #endif
-#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM1_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 +#define PM1_STATUS_OFFSET 0x00 +#define PM1_ENABLE_OFFSET 0x02 +#define PM1_CONTROL_OFFSET 0x04 +#define PM_TIMER_OFFSET 0x08 +#define CPU_CONTROL_OFFSET 0x10 +#define EVENT_STATUS_OFFSET 0x20 +#define EVENT_ENABLE_OFFSET 0x24
/** * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address * */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr +#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
/** * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address * */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr +#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
/** * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address * */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr +#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
/** * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address * */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr +#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
/** * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address * */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr +#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
/** * SMI_CMD_PORT - ACPI SMI Command block base address * */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
/** * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address * */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
/** * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. * Define value for SSID while SATA controller set to IDE mode. */ -#define SATA_IDE_MODE_SSID 0x78001022 +#define SATA_IDE_MODE_SSID 0x78001022 /** * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. * Define value for SSID while SATA controller set to RAID mode. */ -#define SATA_RAID_MODE_SSID 0x78021022 +#define SATA_RAID_MODE_SSID 0x78021022
/** * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. * Define value for SSID while SATA controller set to RAID5 mode. */ -#define SATA_RAID5_MODE_SSID 0x78031022 +#define SATA_RAID5_MODE_SSID 0x78031022
/** * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. * Define value for SSID while SATA controller set to AHCI mode. */ -#define SATA_AHCI_SSID 0x78011022 +#define SATA_AHCI_SSID 0x78011022
/** * OHCI_SSID - All SB OHCI controllers SSID value. * */ -#define OHCI_SSID 0x78071022 +#define OHCI_SSID 0x78071022
/** * EHCI_SSID - All SB EHCI controllers SSID value. * */ -#define EHCI_SSID 0x78081022 +#define EHCI_SSID 0x78081022
/** * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. * */ -#define OHCI4_SSID 0x78091022 +#define OHCI4_SSID 0x78091022
/** * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. * */ -#define SMBUS_SSID 0x780B1022 +#define SMBUS_SSID 0x780B1022
/** * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. * */ -#define IDE_SSID 0x780C1022 +#define IDE_SSID 0x780C1022
/** * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. * */ -#define AZALIA_SSID 0x780D1022 +#define AZALIA_SSID 0x780D1022
/** * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. * */ -#define LPC_SSID 0x780E1022 +#define LPC_SSID 0x780E1022
/** * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. * */ -#define PCIB_SSID 0x780F1022 +#define PCIB_SSID 0x780F1022
diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h index 4e86877..93f0394 100644 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ b/src/mainboard/amd/torpedo/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -50,15 +50,15 @@ * **/
-//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_ASSERT_ENABLED TRUE
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 1639393..7cfffc7 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -29,13 +29,13 @@ PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) { - 0, //Descriptor flags + 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) }, // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) { - 0, //Descriptor flags + 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) }, @@ -74,7 +74,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) { - 0, //Descriptor flags + 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, @@ -87,10 +87,10 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { };
PCIe_COMPLEX_DESCRIPTOR Llano = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
/*---------------------------------------------------------------------------------------*/ @@ -105,7 +105,7 @@ PCIe_COMPLEX_DESCRIPTOR Llano = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -114,10 +114,10 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *LlanoPcieComplexListPtr; - VOID *LlanoPciePortPtr; - VOID *LlanoPcieDdiPtr; + AGESA_STATUS Status; + VOID *LlanoPcieComplexListPtr; + VOID *LlanoPciePortPtr; + VOID *LlanoPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
@@ -140,25 +140,25 @@ OemCustomizeInitEarly ( LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Llano); - LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (LlanoPcieComplexListPtr, - 0, - sizeof(Llano), - &InitEarly->StdHeader); + 0, + sizeof(Llano), + &InitEarly->StdHeader);
LibAmdMemFill (LlanoPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (LlanoPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader); LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 5efcd7d..e81bc3e 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -25,44 +25,44 @@ #include "amdlib.h"
//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/amd/torpedo/acpi/ide.asl b/src/mainboard/amd/torpedo/acpi/ide.asl index b3aed9c..cb284ed 100755 --- a/src/mainboard/amd/torpedo/acpi/ide.asl +++ b/src/mainboard/amd/torpedo/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index effe12e..46aff47 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -71,12 +71,12 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB900 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb900, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); + current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); + current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 8d06811..6ed8923 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -41,55 +41,55 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 ReadAmdSbPmr ( - IN UINT8 IndexValue, - OUT UINT8 *DataValue + IN UINT8 IndexValue, + OUT UINT8 *DataValue );
UINT32 WriteAmdSbPmr ( - IN UINT8 IndexValue, - IN UINT8 DataValue + IN UINT8 IndexValue, + IN UINT8 DataValue );
VOID ClearSBSmiAndWake ( - IN UINT16 PmBase + IN UINT16 PmBase );
VOID @@ -102,8 +102,8 @@ ClearAllSmiEnableInPmio ( /* Read SB Power Management Area */ UINT32 ReadAmdSbPmr ( - IN UINT8 IndexValue, - OUT UINT8 *DataValue + IN UINT8 IndexValue, + OUT UINT8 *DataValue ) { WriteIo8 (SB_PM_INDEX_PORT, IndexValue); @@ -114,8 +114,8 @@ ReadAmdSbPmr ( /* Write ATI SB Power Management Area */ UINT32 WriteAmdSbPmr ( - IN UINT8 IndexValue, - IN UINT8 DataValue + IN UINT8 IndexValue, + IN UINT8 DataValue ) { WriteIo8 (SB_PM_INDEX_PORT, IndexValue); @@ -126,7 +126,7 @@ WriteAmdSbPmr ( /* Clear any SMI status or wake status left over from boot. */ VOID ClearSBSmiAndWake ( - IN UINT16 PmBase + IN UINT16 PmBase ) { UINT16 Pm1Sts; @@ -156,7 +156,7 @@ ClearAllSmiEnableInPmio ( { UINT32 AcpiMmioAddr; UINT32 SmiMmioAddr; - UINT8 Data8 = 0 ; + UINT8 Data8 = 0 ; UINT16 Data16 = 0;
/* Get SB900 MMIO Base (AcpiMmioAddr) */ @@ -184,11 +184,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable MMIO on AMD CPU Address Map Controller */
@@ -233,11 +233,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -302,15 +302,15 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -339,9 +339,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -367,15 +367,15 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -413,9 +413,9 @@ agesawrapper_amdinitenv ( AMD_INTERFACE_PARAMS AmdParamStruct;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -471,9 +471,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -500,9 +500,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -515,14 +515,14 @@ agesawrapper_amdinitlate ( ASSERT(Status == AGESA_SUCCESS); }
- DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; + DmiTable = AmdLateParams.DmiTable; + AcpiPstate = AmdLateParams.AcpiPState; + AcpiSrat = AmdLateParams.AcpiSrat; + AcpiSlit = AmdLateParams.AcpiSlit;
- AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + AcpiWheaMce = AmdLateParams.AcpiWheaMce; + AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; + AcpiAlib = AmdLateParams.AcpiAlib;
return (UINT32)Status; } @@ -537,9 +537,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -564,9 +564,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL; diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index 473d1c3..db4eced 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,47 +31,47 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
/* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 +#define SB_ACPI_BASE_ADDRESS 0x0400 #define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 #define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn #define MmioAddress( BaseAddr, Register ) \ ( (UINTN)BaseAddr + \ (UINTN)(Register) \ @@ -82,19 +82,19 @@ *Mmio32Ptr( BaseAddr, Register )
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -104,17 +104,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 91718ed..17f5784 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 6049 $ @e $Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ */ @@ -62,29 +62,29 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_DCT_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE -#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE +#define BLDOPT_REMOVE_DDR2_SUPPORT TRUE +#define BLDOPT_REMOVE_DDR3_SUPPORT FALSE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI FALSE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI FALSE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
//For revision C single-link processors #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE @@ -92,17 +92,17 @@ /* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/***************************************************************************** * Define the RELEASE VERSION string @@ -117,89 +117,89 @@ * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "LlanoPI " - // This string MUST be exactly 8 characters long + // This is the delivery package title, "LlanoPI " + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
/* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_VRM_CURRENT_LIMIT 65000 //240000 //120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 15000 // 0 +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY //DDR1066_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
//enable HW C1E #define BLDCFG_PLATFORM_C1E_MODE 0 //C1eModeHardware -//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 +//#define BLDCFG_PLATFORM_C1E_OPDATA 0x415 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 //0 //CStateModeC6 +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L. Default is Zero. +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime per BKDG. Defaults to 5000, same as core VRM. Cannot be zero. +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Llano/Ontario +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Llano/Ontario +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Llano/Ontario
-#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE -#define BLDCFG_STEREO_3D_PINOUT TRUE +#define BLDCFG_UMA_ABOVE4G_SUPPORT TRUE +#define BLDCFG_STEREO_3D_PINOUT TRUE
/* Process the options... * This file include MUST occur AFTER the user option selection settings @@ -222,11 +222,11 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList //#define OPTION_NB_LCLK_DPM_INIT FALSE -//#define OPTION_POWER_GATE FALSE +//#define OPTION_POWER_GATE FALSE //#define OPTION_PCIE_POWER_GATE FALSE -//#define OPTION_ALIB FALSE +//#define OPTION_ALIB FALSE //#define OPTION_PCIe_MID_INIT FALSE -//#define OPTION_NB_MID_INIT FALSE +//#define OPTION_NB_MID_INIT FALSE
#include "cpuRegisters.h" #include "cpuFamRegisters.h" @@ -243,7 +243,7 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -258,57 +258,57 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), @@ -335,8 +335,8 @@ UINT8 AGESA_MEM_TABLE_LN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x15, 0x14, 0x21, 0x11, 0x40, 0x2A, 0x34, 0x2D, 0x15),// DCT0, DIMM0 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -366,7 +366,7 @@ UINT8 AGESA_MEM_TABLE_LN[][sizeof (MEM_TABLE_ALIAS)] = // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct0, BFMaxLatency, MTOverride, 0x0C), // NBACCESS (MTAfterMaxRdLatTrn, MTNode0, MTDct1, BFMaxLatency, MTOverride, 0x0C), // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableLN = sizeof (AGESA_MEM_TABLE_LN) / sizeof (AGESA_MEM_TABLE_LN[0]);
@@ -376,7 +376,7 @@ UINT8 SizeOfTableLN = sizeof (AGESA_MEM_TABLE_LN) / sizeof (AGESA_MEM_TABLE_LN[0 */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/torpedo/cmos.layout b/src/mainboard/amd/torpedo/cmos.layout index 95ce3b5..1676c25 100755 --- a/src/mainboard/amd/torpedo/cmos.layout +++ b/src/mainboard/amd/torpedo/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index bc53f13..583dffd 100755 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -17,53 +17,53 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family12/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family12 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family12 # CPU side of HT root complex - chip northbridge/amd/agesa/family12 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics Bridge - device pci 1.1 on end # Audio Controller - device pci 2.0 on end # Root Port - device pci 3.0 on end # Root Port - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC + device cpu_cluster 0 on + chip cpu/amd/agesa/family12 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family12 # CPU side of HT root complex + chip northbridge/amd/agesa/family12 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics Bridge + device pci 1.1 on end # Audio Controller + device pci 2.0 on end # Root Port + device pci 3.0 on end # Root Port + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 end #LPC device pci 14.4 on end # PCI bridge device pci 14.5 on end # USB 2 @@ -76,15 +76,15 @@ chip northbridge/amd/agesa/family12/root_complex register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb900 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex - end #domain + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family12/root_complex
diff --git a/src/mainboard/amd/torpedo/dimmSpd.c b/src/mainboard/amd/torpedo/dimmSpd.c index 55fb2c3..5596042 100644 --- a/src/mainboard/amd/torpedo/dimmSpd.c +++ b/src/mainboard/amd/torpedo/dimmSpd.c @@ -6,13 +6,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED @@ -28,7 +28,7 @@ ***************************************************************************/
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -38,22 +38,22 @@ #include "dimmSpd.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define SMBUS_BASE_ADDR 0xB00 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
typedef struct _DIMM_INFO_SMBUS{ - UINT8 SocketId; - UINT8 MemChannelId; - UINT8 DimmId; - UINT8 SmbusAddress; + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; } DIMM_INFO_SMBUS; /* * SPD address table - porting required @@ -66,17 +66,17 @@ STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = };
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
@@ -125,31 +125,31 @@ ReadSmbusByteData (
Address |= 1; // set read bit
- __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 1, 0x1F); // clear error status - __outbyte (Iobase + 3, Offset); // offset in eeprom - __outbyte (Iobase + 4, Address); // slave address and read bit - __outbyte (Iobase + 2, 0x48); // read byte command + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and read bit + __outbyte (Iobase + 2, 0x48); // read byte command
/* time limit to avoid hanging for unexpected error status (should never happen) */ Limit = __rdtsc () + 2000000000 / 10; for (;;) { Status = __inbyte (Iobase); if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting break; }
Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors + if (Status == 2) Status = 0; // check for done with no errors return Status; }
/* * * ReadSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData + * this function is faster function readSmbusByteData * */
@@ -161,34 +161,34 @@ ReadSmbusByte ( OUT UINT8 *Buffer ) { - UINTN Status; + UINTN Status; UINT64 Limit;
- __outbyte (Iobase + 0, 0xFF); // clear error status - __outbyte (Iobase + 2, 0x44); // read command + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status Limit = __rdtsc () + 2000000000 / 10; for (;;) { Status = __inbyte (Iobase); if (__rdtsc () > Limit) break; - if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting break; }
Buffer [0] = __inbyte (Iobase + 5); - if (Status == 2) Status = 0; // check for done with no errors + if (Status == 2) Status = 0; // check for done with no errors return Status; }
/* * * ReadSpd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. * */
@@ -226,11 +226,11 @@ AmdMemoryReadSPD ( UINTN Index; UINTN MaxSocket = DIMENSION (SpdAddrLookup); for (Index = 0; Index < MaxSocket; Index ++){ - if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && - (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && - (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { - SmBusAddress = SpdAddrLookup[Index].SmbusAddress; - break; + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; } }
diff --git a/src/mainboard/amd/torpedo/dimmSpd.h b/src/mainboard/amd/torpedo/dimmSpd.h index 81ab02e..668a159 100644 --- a/src/mainboard/amd/torpedo/dimmSpd.h +++ b/src/mainboard/amd/torpedo/dimmSpd.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -29,22 +29,22 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -56,7 +56,7 @@ AmdMemoryReadSPD ( );
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index 2ecd80b..9e7faf1 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -131,13 +131,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -156,7 +156,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -227,8 +227,8 @@ DefinitionBlock ( OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), - FLG0, 8 + Offset (0x10), + FLG0, 8 }
Scope(_SB) { @@ -812,7 +812,7 @@ DefinitionBlock ( } Method(_PRT,0) { If(GPIC){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -832,8 +832,8 @@ DefinitionBlock ( Device(PBR2) { Name(_ADR, 0x00020000) Method(_PRT,0) { - If(GPIC){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -841,32 +841,32 @@ DefinitionBlock ( Device(PBR3) { Name(_ADR, 0x00030000) Method(_PRT,0) { - If(GPIC){ Return(APS3) } /* APIC mode */ - Return (PS3) /* PIC Mode */ + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ } /* end _PRT */ } /* end PBR3 */
Device(PBR4) { Name(_ADR, 0x00040000) Method(_PRT,0) { - If(GPIC){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
Device(PBR5) { Name(_ADR, 0x00050000) Method(_PRT,0) { - If(GPIC){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
Device(PBR6) { Name(_ADR, 0x00060000) Method(_PRT,0) { - If(GPIC){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -874,37 +874,37 @@ DefinitionBlock ( Device(PBR7) { Name(_ADR, 0x00070000) Method(_PRT,0) { - If(GPIC){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
Device(PE20) { Name(_ADR, 0x00150000) Method(_PRT,0) { - If(GPIC){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Method(_PRT,0) { - If(GPIC){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Method(_PRT,0) { - If(GPIC){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Method(_PRT,0) { - If(GPIC){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1110,7 +1110,7 @@ DefinitionBlock ( Method(_CRS, 0) { /* DBGO("\_SB\PCI0\_CRS\n") */ CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* * Declare memory between TOM1 and 4GB as available * for PCI MMIO. diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 2b4e9fa..a69a058 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -128,7 +128,7 @@ void get_bus_conf(void) for (j = bus_sb900[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10;
sb_Late_Post(); diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index d2d2bea..262d0f1 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,46 +30,46 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #ifndef SB_GPIO_REG01 -#define SB_GPIO_REG01 1 +#define SB_GPIO_REG01 1 #endif
#ifndef SB_GPIO_REG07 -#define SB_GPIO_REG07 7 +#define SB_GPIO_REG07 7 #endif
#ifndef SB_GPIO_REG25 -#define SB_GPIO_REG25 25 +#define SB_GPIO_REG25 25 #endif
#ifndef SB_GPIO_REG26 -#define SB_GPIO_REG26 26 +#define SB_GPIO_REG26 26 #endif
#ifndef SB_GPIO_REG27 -#define SB_GPIO_REG27 27 +#define SB_GPIO_REG27 27 #endif
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ void @@ -124,9 +124,9 @@ gpioEarlyInit( Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } // Configure GPIO - if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { - Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); - Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { if ( BoardType == 0 ) { @@ -182,12 +182,12 @@ gpioEarlyInit( // // set INTE#/GPIO32 as GPO for PCIE_SW RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO
// set AD9/GPIO9 as GPI for MXM_PRESENT2# RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO @@ -199,11 +199,11 @@ gpioEarlyInit(
// set GNT1#/GPIO44 as GPO for MXM Reset RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO
// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO
// set AD28/GPIO28 as GPI for MXM_PWRGD RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO @@ -282,21 +282,21 @@ gpioEarlyInit( // Clock: GPP_CLK3 // // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER - RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# - RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3
// // APU GPP1: WUSB @@ -306,21 +306,21 @@ gpioEarlyInit( // // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD01/GPIO01 as GPO for MPCIE_RST2# RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH -// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE +// RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH +// RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// // APU GPP2: WWAN @@ -330,19 +330,19 @@ gpioEarlyInit( // // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD00/GPIO00 as GPO for MPCIE_RST1# RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO -// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW +// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN -// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO +// RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
@@ -354,25 +354,25 @@ gpioEarlyInit( // Clock: GPP_CLK8 // // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: - RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 - RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO -// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO +// RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE
// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# - RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2#
// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C - RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH - RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE // To fix glitch issue RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW // @@ -398,12 +398,12 @@ gpioEarlyInit( // if (!CONFIG_ONBOARD_1394) { // 1 - DISABLED -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW +// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 -// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH +// RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH } // else // { // 0 - AUTO @@ -418,11 +418,11 @@ gpioEarlyInit( // // external USB 3.0 control: // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO26: PCIE_RST#_USB3.0 -// GPIO46: PCIE_USB30_CLKREQ# -// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON -// Clock: GPP_CLK7 -// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +// GPIO26: PCIE_RST#_USB3.0 +// GPIO46: PCIE_USB30_CLKREQ# +// GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON +// Clock: GPP_CLK7 +// GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { // disable Onboard NEC USB3.0 controller if (!CONFIG_ONBOARD_USB30) { @@ -437,7 +437,7 @@ gpioEarlyInit( // // BlueTooth control: BT_ON // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO07: BT_ON, 0 - OFF, 1 - ON +// GPIO07: BT_ON, 0 - OFF, 1 - ON // if (!CONFIG_ONBOARD_BLUETOOTH) { //- if (SystemConfiguration.amdBlueTooth == 1) { @@ -448,7 +448,7 @@ if (!CONFIG_ONBOARD_BLUETOOTH) { // // WebCam control: // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE -// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF +// GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF // if (!CONFIG_ONBOARD_WEBCAM) { //- if (SystemConfiguration.amdWebCam == 1) { @@ -459,7 +459,7 @@ if (!CONFIG_ONBOARD_WEBCAM) { // // Travis enable: // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE -// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE +// GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE // if (!CONFIG_ONBOARD_TRAVIS) { //- if (SystemConfiguration.amdTravisCtrl == 0) { @@ -472,7 +472,7 @@ if (!CONFIG_ONBOARD_TRAVIS) { // if (CONFIG_ONBOARD_LIGHTSENSOR) { //- if (SystemConfiguration.amdLightSensor == 1) { - RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); //- } }
diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 86c1329..15d97ab 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,7 +30,7 @@ #include <cpu/amd/common/cbtypes.h>
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define Mmio_Address( BaseAddr, Register ) \ @@ -48,7 +48,7 @@ Mmio32_G( BaseAddr, Register ) = \ (u32) ( \ ( Mmio32_G( BaseAddr, Register ) & \ - (u32)(AndData) \ + (u32)(AndData) \ ) | \ (u32)(OrData) \ ) @@ -63,1240 +63,1240 @@ Mmio8_G( BaseAddr, Register ) = \ (u8) ( \ ( Mmio8_G( BaseAddr, Register ) & \ - (u8)(AndData) \ - ) | \ + (u8)(AndData) \ + ) | \ (u8)(OrData) \ )
#define SMIREG_EVENT_ENABLE 0x04 -#define SMIREG_SCITRIG 0x08 -#define SMIREG_SCILEVEL 0x0C -#define SMIREG_SMISCIEN 0x14 -#define SMIREG_SCIS0EN 0x20 -#define SMIREG_SCIMAP0 0x40 -#define SMIREG_SCIMAP1 0x44 -#define SMIREG_SCIMAP2 0x48 -#define SMIREG_SCIMAP3 0x4C -#define SMIREG_SCIMAP4 0x50 -#define SMIREG_SCIMAP5 0x54 -#define SMIREG_SCIMAP6 0x58 -#define SMIREG_SCIMAP7 0x5C -#define SMIREG_SCIMAP8 0x60 -#define SMIREG_SCIMAP9 0x64 -#define SMIREG_SCIMAP10 0x68 -#define SMIREG_SCIMAP11 0x6C -#define SMIREG_SCIMAP12 0x70 -#define SMIREG_SCIMAP13 0x74 -#define SMIREG_SCIMAP14 0x78 -#define SMIREG_SCIMAP15 0x7C -#define SMIREG_SMITRIG 0x98 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 #define SMIREG_SMICONTROL0 0xA0 #define SMIREG_SMICONTROL1 0xA4
-#define FUNCTION0 0 -#define FUNCTION1 1 -#define FUNCTION2 2 -#define FUNCTION3 3 -#define NonGpio 0x80 // BIT7 +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7
// S0-domain General Purpose I/O: GPIO 00~67 -#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT -#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT -#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT -#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED -#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT -#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT -#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED -#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF -#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level -#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED -#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 -#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 -#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 -#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default -#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. -#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) -#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) -#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE - // 1:BATTERY IS FINE(DEFAULT) - // 0:BATTERY IS LOW -#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF -#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default -#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high -#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high -#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high -#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT -#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT -#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 -#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 - // 00 - REVA - // 01 - REVB - // 10 - REVC - // 11 - REVD -#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO -#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. - // 0:USB3.0 I/F in Express CARD - // 1:PCIE I/F in Express CARD detection -#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF -#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# -#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC -#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED -#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. -#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# -#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# -#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK -#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE -#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF -#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# -#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA -#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ -#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 -#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V -#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 -#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT -#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE -#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE -#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) - // 1:ENABLE; 0:DISABLE - // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 -#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN -#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER -#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER -#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE -#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# -#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 -#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 -#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# -#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 -#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM -#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default -#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# -#define GPIO_68_SELECT FUNCTION0+NonGpio -#define GPIO_69_SELECT FUNCTION0+NonGpio -#define GPIO_70_SELECT FUNCTION0+NonGpio -#define GPIO_71_SELECT FUNCTION0+NonGpio -#define GPIO_72_SELECT FUNCTION0+NonGpio -#define GPIO_73_SELECT FUNCTION0+NonGpio -#define GPIO_74_SELECT FUNCTION0+NonGpio -#define GPIO_75_SELECT FUNCTION0+NonGpio -#define GPIO_76_SELECT FUNCTION0+NonGpio -#define GPIO_77_SELECT FUNCTION0+NonGpio -#define GPIO_78_SELECT FUNCTION0+NonGpio -#define GPIO_79_SELECT FUNCTION0+NonGpio -#define GPIO_80_SELECT FUNCTION0+NonGpio -#define GPIO_81_SELECT FUNCTION0+NonGpio -#define GPIO_82_SELECT FUNCTION0+NonGpio -#define GPIO_83_SELECT FUNCTION0+NonGpio -#define GPIO_84_SELECT FUNCTION0+NonGpio -#define GPIO_85_SELECT FUNCTION0+NonGpio -#define GPIO_86_SELECT FUNCTION0+NonGpio -#define GPIO_87_SELECT FUNCTION0+NonGpio -#define GPIO_88_SELECT FUNCTION0+NonGpio -#define GPIO_89_SELECT FUNCTION0+NonGpio -#define GPIO_90_SELECT FUNCTION0+NonGpio -#define GPIO_91_SELECT FUNCTION0+NonGpio -#define GPIO_92_SELECT FUNCTION0+NonGpio -#define GPIO_93_SELECT FUNCTION0+NonGpio -#define GPIO_94_SELECT FUNCTION0+NonGpio -#define GPIO_95_SELECT FUNCTION0+NonGpio +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE + // 1:BATTERY IS FINE(DEFAULT) + // 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 + // 00 - REVA + // 01 - REVB + // 10 - REVC + // 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. + // 0:USB3.0 I/F in Express CARD + // 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) + // 1:ENABLE; 0:DISABLE + // DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio // GEVENT 00~23 are mapped to GPIO 96~119 -#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# -#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# -#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP -#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# -#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# -#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active -#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, - // there is a confliction to IR function when this pin is as a GEVENT. -#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, - // special pin difination for SB900 VGA OUTPUT, high active, - // VGA power for Hudson-M2 will be down when it was asserted. -#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active -#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) -#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 -#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 -#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active - // [option for SPI_TPM_CS# in Hudson-M2 A12)] -#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & - // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time -#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, - // plus judge GPIO40 and GPIO19 level,low is assert. - // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) - // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) -#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active -#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, - // low active, when it's low, BIOS will enbale ODD_PWR -#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# -#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK -#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# -#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT -#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 -#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# -#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI -#define GPIO_120_SELECT FUNCTION0+NonGpio -#define GPIO_121_SELECT FUNCTION0+NonGpio -#define GPIO_122_SELECT FUNCTION0+NonGpio -#define GPIO_123_SELECT FUNCTION0+NonGpio -#define GPIO_124_SELECT FUNCTION0+NonGpio -#define GPIO_125_SELECT FUNCTION0+NonGpio -#define GPIO_126_SELECT FUNCTION0+NonGpio -#define GPIO_127_SELECT FUNCTION0+NonGpio -#define GPIO_128_SELECT FUNCTION0+NonGpio -#define GPIO_129_SELECT FUNCTION0+NonGpio -#define GPIO_130_SELECT FUNCTION0+NonGpio -#define GPIO_131_SELECT FUNCTION0+NonGpio -#define GPIO_132_SELECT FUNCTION0+NonGpio -#define GPIO_133_SELECT FUNCTION0+NonGpio -#define GPIO_134_SELECT FUNCTION0+NonGpio -#define GPIO_135_SELECT FUNCTION0+NonGpio -#define GPIO_136_SELECT FUNCTION0+NonGpio -#define GPIO_137_SELECT FUNCTION0+NonGpio -#define GPIO_138_SELECT FUNCTION0+NonGpio -#define GPIO_139_SELECT FUNCTION0+NonGpio -#define GPIO_140_SELECT FUNCTION0+NonGpio -#define GPIO_141_SELECT FUNCTION0+NonGpio -#define GPIO_142_SELECT FUNCTION0+NonGpio -#define GPIO_143_SELECT FUNCTION0+NonGpio -#define GPIO_144_SELECT FUNCTION0+NonGpio -#define GPIO_145_SELECT FUNCTION0+NonGpio -#define GPIO_146_SELECT FUNCTION0+NonGpio -#define GPIO_147_SELECT FUNCTION0+NonGpio -#define GPIO_148_SELECT FUNCTION0+NonGpio -#define GPIO_149_SELECT FUNCTION0+NonGpio -#define GPIO_150_SELECT FUNCTION0+NonGpio -#define GPIO_151_SELECT FUNCTION0+NonGpio -#define GPIO_152_SELECT FUNCTION0+NonGpio -#define GPIO_153_SELECT FUNCTION0+NonGpio -#define GPIO_154_SELECT FUNCTION0+NonGpio -#define GPIO_155_SELECT FUNCTION0+NonGpio -#define GPIO_156_SELECT FUNCTION0+NonGpio -#define GPIO_157_SELECT FUNCTION0+NonGpio -#define GPIO_158_SELECT FUNCTION0+NonGpio -#define GPIO_159_SELECT FUNCTION0+NonGpio -#define GPIO_160_SELECT FUNCTION0+NonGpio +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, + // there is a confliction to IR function when this pin is as a GEVENT. +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, + // special pin difination for SB900 VGA OUTPUT, high active, + // VGA power for Hudson-M2 will be down when it was asserted. +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active + // [option for SPI_TPM_CS# in Hudson-M2 A12)] +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & + // USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, + // plus judge GPIO40 and GPIO19 level,low is assert. + // LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) + // DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, + // low active, when it's low, BIOS will enbale ODD_PWR +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio
// S5-domain General Purpose I/O -#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# -#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM -#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 -#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 -#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 -#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 -#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. -#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, -#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE -#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 -#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# -#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE -#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 -#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 -#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO -#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR -#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 -#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 -#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# -#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB -#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE -#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE - // option for HDMI CEC signal OW ACTIVE -#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active -#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT -#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA -#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK -#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active - // RESERVED FOR LCD BACKLIGHT PWM -#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL -#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM -#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF -#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI -#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO -#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO -#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, -#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA -#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE + // option for HDMI CEC signal OW ACTIVE +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active + // RESERVED FOR LCD BACKLIGHT PWM +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD
#define TYPE_GPI (1<<5) #define TYPE_GPO (0<<5)
-#define GPIO_00_TYPE TYPE_GPO -#define GPIO_01_TYPE TYPE_GPO -#define GPIO_02_TYPE TYPE_GPO -#define GPIO_03_TYPE TYPE_GPO -#define GPIO_04_TYPE TYPE_GPO -#define GPIO_05_TYPE TYPE_GPO -#define GPIO_06_TYPE TYPE_GPO -#define GPIO_07_TYPE TYPE_GPO -#define GPIO_08_TYPE TYPE_GPO -#define GPIO_09_TYPE TYPE_GPI -#define GPIO_10_TYPE TYPE_GPI -#define GPIO_11_TYPE TYPE_GPO -#define GPIO_12_TYPE TYPE_GPO -#define GPIO_13_TYPE TYPE_GPO -#define GPIO_14_TYPE TYPE_GPO -#define GPIO_15_TYPE TYPE_GPO -#define GPIO_16_TYPE TYPE_GPO -#define GPIO_17_TYPE TYPE_GPO -#define GPIO_18_TYPE TYPE_GPO -#define GPIO_19_TYPE TYPE_GPO -#define GPIO_20_TYPE TYPE_GPO -#define GPIO_21_TYPE TYPE_GPO -#define GPIO_22_TYPE TYPE_GPO -#define GPIO_23_TYPE TYPE_GPO -#define GPIO_24_TYPE TYPE_GPO -#define GPIO_25_TYPE TYPE_GPO -#define GPIO_26_TYPE TYPE_GPO -#define GPIO_27_TYPE TYPE_GPO -#define GPIO_28_TYPE TYPE_GPI -#define GPIO_29_TYPE TYPE_GPO -#define GPIO_30_TYPE TYPE_GPI -#define GPIO_31_TYPE TYPE_GPI -#define GPIO_32_TYPE TYPE_GPO -#define GPIO_33_TYPE TYPE_GPI -#define GPIO_34_TYPE TYPE_GPO -#define GPIO_35_TYPE TYPE_GPO -#define GPIO_36_TYPE TYPE_GPO -#define GPIO_37_TYPE TYPE_GPO -#define GPIO_38_TYPE TYPE_GPO -#define GPIO_39_TYPE TYPE_GPO -#define GPIO_40_TYPE TYPE_GPO -#define GPIO_41_TYPE TYPE_GPI -#define GPIO_42_TYPE TYPE_GPI -#define GPIO_43_TYPE TYPE_GPO -#define GPIO_44_TYPE TYPE_GPO -#define GPIO_45_TYPE TYPE_GPO -#define GPIO_46_TYPE TYPE_GPI -#define GPIO_47_TYPE TYPE_GPO -#define GPIO_48_TYPE TYPE_GPO -#define GPIO_49_TYPE TYPE_GPO -#define GPIO_50_TYPE TYPE_GPO -#define GPIO_51_TYPE TYPE_GPO -#define GPIO_52_TYPE TYPE_GPO -#define GPIO_53_TYPE TYPE_GPO -#define GPIO_54_TYPE TYPE_GPO -#define GPIO_55_TYPE TYPE_GPO -#define GPIO_56_TYPE TYPE_GPI -#define GPIO_57_TYPE TYPE_GPO -#define GPIO_58_TYPE TYPE_GPO -#define GPIO_59_TYPE TYPE_GPO -#define GPIO_60_TYPE TYPE_GPI -#define GPIO_61_TYPE TYPE_GPI -#define GPIO_62_TYPE TYPE_GPI -#define GPIO_63_TYPE TYPE_GPI -#define GPIO_64_TYPE TYPE_GPI -#define GPIO_65_TYPE TYPE_GPI -#define GPIO_66_TYPE TYPE_GPO -#define GPIO_67_TYPE TYPE_GPO -#define GPIO_68_TYPE TYPE_GPO -#define GPIO_69_TYPE TYPE_GPO -#define GPIO_70_TYPE TYPE_GPO -#define GPIO_71_TYPE TYPE_GPO -#define GPIO_72_TYPE TYPE_GPO -#define GPIO_73_TYPE TYPE_GPO -#define GPIO_74_TYPE TYPE_GPO -#define GPIO_75_TYPE TYPE_GPO -#define GPIO_76_TYPE TYPE_GPO -#define GPIO_77_TYPE TYPE_GPO -#define GPIO_78_TYPE TYPE_GPO -#define GPIO_79_TYPE TYPE_GPO -#define GPIO_80_TYPE TYPE_GPO -#define GPIO_81_TYPE TYPE_GPO -#define GPIO_82_TYPE TYPE_GPO -#define GPIO_83_TYPE TYPE_GPO -#define GPIO_84_TYPE TYPE_GPO -#define GPIO_85_TYPE TYPE_GPO -#define GPIO_86_TYPE TYPE_GPO -#define GPIO_87_TYPE TYPE_GPO -#define GPIO_88_TYPE TYPE_GPO -#define GPIO_89_TYPE TYPE_GPO -#define GPIO_90_TYPE TYPE_GPO -#define GPIO_91_TYPE TYPE_GPO -#define GPIO_92_TYPE TYPE_GPO -#define GPIO_93_TYPE TYPE_GPO -#define GPIO_94_TYPE TYPE_GPO -#define GPIO_95_TYPE TYPE_GPO +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO
// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 -#define GPIO_96_TYPE TYPE_GPI -#define GPIO_97_TYPE TYPE_GPI -#define GPIO_98_TYPE TYPE_GPI -#define GPIO_99_TYPE TYPE_GPI -#define GPIO_100_TYPE TYPE_GPI -#define GPIO_101_TYPE TYPE_GPI -#define GPIO_102_TYPE TYPE_GPO -#define GPIO_103_TYPE TYPE_GPO -#define GPIO_104_TYPE TYPE_GPI -#define GPIO_105_TYPE TYPE_GPI -#define GPIO_106_TYPE TYPE_GPO -#define GPIO_107_TYPE TYPE_GPI -#define GPIO_108_TYPE TYPE_GPI -#define GPIO_109_TYPE TYPE_GPI -#define GPIO_110_TYPE TYPE_GPI -#define GPIO_111_TYPE TYPE_GPI -#define GPIO_112_TYPE TYPE_GPI -#define GPIO_113_TYPE TYPE_GPI -#define GPIO_114_TYPE TYPE_GPO -#define GPIO_115_TYPE TYPE_GPI -#define GPIO_116_TYPE TYPE_GPI -#define GPIO_117_TYPE TYPE_GPI -#define GPIO_118_TYPE TYPE_GPI -#define GPIO_119_TYPE TYPE_GPI +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI
-#define GPIO_120_TYPE TYPE_GPO -#define GPIO_121_TYPE TYPE_GPO -#define GPIO_122_TYPE TYPE_GPO -#define GPIO_123_TYPE TYPE_GPO -#define GPIO_124_TYPE TYPE_GPO -#define GPIO_125_TYPE TYPE_GPO -#define GPIO_126_TYPE TYPE_GPO -#define GPIO_127_TYPE TYPE_GPO -#define GPIO_128_TYPE TYPE_GPO -#define GPIO_129_TYPE TYPE_GPO -#define GPIO_130_TYPE TYPE_GPO -#define GPIO_131_TYPE TYPE_GPO -#define GPIO_132_TYPE TYPE_GPO -#define GPIO_133_TYPE TYPE_GPO -#define GPIO_134_TYPE TYPE_GPO -#define GPIO_135_TYPE TYPE_GPO -#define GPIO_136_TYPE TYPE_GPO -#define GPIO_137_TYPE TYPE_GPO -#define GPIO_138_TYPE TYPE_GPO -#define GPIO_139_TYPE TYPE_GPO -#define GPIO_140_TYPE TYPE_GPO -#define GPIO_141_TYPE TYPE_GPO -#define GPIO_142_TYPE TYPE_GPO -#define GPIO_143_TYPE TYPE_GPO -#define GPIO_144_TYPE TYPE_GPO -#define GPIO_145_TYPE TYPE_GPO -#define GPIO_146_TYPE TYPE_GPO -#define GPIO_147_TYPE TYPE_GPO -#define GPIO_148_TYPE TYPE_GPO -#define GPIO_149_TYPE TYPE_GPO -#define GPIO_150_TYPE TYPE_GPO -#define GPIO_151_TYPE TYPE_GPO -#define GPIO_152_TYPE TYPE_GPO -#define GPIO_153_TYPE TYPE_GPO -#define GPIO_154_TYPE TYPE_GPO -#define GPIO_155_TYPE TYPE_GPO -#define GPIO_156_TYPE TYPE_GPO -#define GPIO_157_TYPE TYPE_GPO -#define GPIO_158_TYPE TYPE_GPO -#define GPIO_159_TYPE TYPE_GPO -#define GPIO_160_TYPE TYPE_GPO -#define GPIO_161_TYPE TYPE_GPO -#define GPIO_162_TYPE TYPE_GPO -#define GPIO_163_TYPE TYPE_GPO -#define GPIO_164_TYPE TYPE_GPI -#define GPIO_165_TYPE TYPE_GPO -#define GPIO_166_TYPE TYPE_GPI -#define GPIO_167_TYPE TYPE_GPI -#define GPIO_168_TYPE TYPE_GPI -#define GPIO_169_TYPE TYPE_GPI -#define GPIO_170_TYPE TYPE_GPO -#define GPIO_171_TYPE TYPE_GPI -#define GPIO_172_TYPE TYPE_GPO -#define GPIO_173_TYPE TYPE_GPI -#define GPIO_174_TYPE TYPE_GPI -#define GPIO_175_TYPE TYPE_GPO -#define GPIO_176_TYPE TYPE_GPO -#define GPIO_177_TYPE TYPE_GPO -#define GPIO_178_TYPE TYPE_GPO -#define GPIO_179_TYPE TYPE_GPO -#define GPIO_180_TYPE TYPE_GPO -#define GPIO_181_TYPE TYPE_GPO -#define GPIO_182_TYPE TYPE_GPO -#define GPIO_183_TYPE TYPE_GPO -#define GPIO_184_TYPE TYPE_GPI -#define GPIO_185_TYPE TYPE_GPO -#define GPIO_186_TYPE TYPE_GPO -#define GPIO_187_TYPE TYPE_GPO -#define GPIO_188_TYPE TYPE_GPO -#define GPIO_189_TYPE TYPE_GPI -#define GPIO_190_TYPE TYPE_GPI -#define GPIO_191_TYPE TYPE_GPO -#define GPIO_192_TYPE TYPE_GPO -#define GPIO_193_TYPE TYPE_GPO -#define GPIO_194_TYPE TYPE_GPO -#define GPIO_195_TYPE TYPE_GPO -#define GPIO_196_TYPE TYPE_GPO -#define GPIO_197_TYPE TYPE_GPO -#define GPIO_198_TYPE TYPE_GPO -#define GPIO_199_TYPE TYPE_GPI -#define GPIO_200_TYPE TYPE_GPO -#define GPIO_201_TYPE TYPE_GPI -#define GPIO_202_TYPE TYPE_GPI -#define GPIO_203_TYPE TYPE_GPI -#define GPIO_204_TYPE TYPE_GPI -#define GPIO_205_TYPE TYPE_GPI -#define GPIO_206_TYPE TYPE_GPI -#define GPIO_207_TYPE TYPE_GPI -#define GPIO_208_TYPE TYPE_GPI -#define GPIO_209_TYPE TYPE_GPO -#define GPIO_210_TYPE TYPE_GPO -#define GPIO_211_TYPE TYPE_GPO -#define GPIO_212_TYPE TYPE_GPO -#define GPIO_213_TYPE TYPE_GPO -#define GPIO_214_TYPE TYPE_GPO -#define GPIO_215_TYPE TYPE_GPO -#define GPIO_216_TYPE TYPE_GPO -#define GPIO_217_TYPE TYPE_GPO -#define GPIO_218_TYPE TYPE_GPO -#define GPIO_219_TYPE TYPE_GPO -#define GPIO_220_TYPE TYPE_GPO -#define GPIO_221_TYPE TYPE_GPO -#define GPIO_222_TYPE TYPE_GPO -#define GPIO_223_TYPE TYPE_GPO -#define GPIO_224_TYPE TYPE_GPO -#define GPIO_225_TYPE TYPE_GPO -#define GPIO_226_TYPE TYPE_GPO -#define GPIO_227_TYPE TYPE_GPO -#define GPIO_228_TYPE TYPE_GPO -#define GPIO_229_TYPE TYPE_GPO +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO
-#define GPO_LOW (0<<6) -#define GPO_HI (1<<6) +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6)
-#define GPO_00_LEVEL GPO_HI -#define GPO_01_LEVEL GPO_HI -#define GPO_02_LEVEL GPO_HI -#define GPO_03_LEVEL GPO_HI -#define GPO_04_LEVEL GPO_HI -#define GPO_05_LEVEL GPO_HI -#define GPO_06_LEVEL GPO_HI -#define GPO_07_LEVEL GPO_HI -#define GPO_08_LEVEL GPO_HI -#define GPO_09_LEVEL GPO_LOW -#define GPO_10_LEVEL GPO_LOW -#define GPO_11_LEVEL GPO_HI -#define GPO_12_LEVEL GPO_HI -#define GPO_13_LEVEL GPO_HI -#define GPO_14_LEVEL GPO_HI -#define GPO_15_LEVEL GPO_HI -#define GPO_16_LEVEL GPO_HI -#define GPO_17_LEVEL GPO_HI -#define GPO_18_LEVEL GPO_HI -#define GPO_19_LEVEL GPO_LOW -#define GPO_20_LEVEL GPO_LOW -#define GPO_21_LEVEL GPO_LOW -#define GPO_22_LEVEL GPO_HI -#define GPO_23_LEVEL GPO_HI -#define GPO_24_LEVEL GPO_HI -#define GPO_25_LEVEL GPO_HI -#define GPO_26_LEVEL GPO_HI -#define GPO_27_LEVEL GPO_HI -#define GPO_28_LEVEL GPO_LOW -#define GPO_29_LEVEL GPO_HI -#define GPO_30_LEVEL GPO_LOW -#define GPO_31_LEVEL GPO_LOW -#define GPO_32_LEVEL GPO_HI -#define GPO_33_LEVEL GPO_LOW -#define GPO_34_LEVEL GPO_LOW -#define GPO_35_LEVEL GPO_LOW -#define GPO_36_LEVEL GPO_LOW -#define GPO_37_LEVEL GPO_HI -#define GPO_38_LEVEL GPO_HI -#define GPO_39_LEVEL GPO_HI -#define GPO_40_LEVEL GPO_LOW -#define GPO_41_LEVEL GPO_LOW -#define GPO_42_LEVEL GPO_LOW -#define GPO_43_LEVEL GPO_LOW -#define GPO_44_LEVEL GPO_HI -#define GPO_45_LEVEL GPO_HI -#define GPO_46_LEVEL GPO_LOW -#define GPO_47_LEVEL GPO_LOW -#define GPO_48_LEVEL GPO_LOW -#define GPO_49_LEVEL GPO_HI -#define GPO_50_LEVEL GPO_HI -#define GPO_51_LEVEL GPO_LOW -#define GPO_52_LEVEL GPO_HI -#define GPO_53_LEVEL GPO_HI -#define GPO_54_LEVEL GPO_LOW -#define GPO_55_LEVEL GPO_LOW -#define GPO_56_LEVEL GPO_LOW -#define GPO_57_LEVEL GPO_HI -#define GPO_58_LEVEL GPO_HI -#define GPO_59_LEVEL GPO_HI -#define GPO_60_LEVEL GPO_LOW -#define GPO_61_LEVEL GPO_LOW -#define GPO_62_LEVEL GPO_LOW -#define GPO_63_LEVEL GPO_LOW -#define GPO_64_LEVEL GPO_LOW -#define GPO_65_LEVEL GPO_LOW -#define GPO_66_LEVEL GPO_LOW -#define GPO_67_LEVEL GPO_LOW -#define GPO_68_LEVEL GPO_LOW -#define GPO_69_LEVEL GPO_LOW -#define GPO_70_LEVEL GPO_LOW -#define GPO_71_LEVEL GPO_LOW -#define GPO_72_LEVEL GPO_LOW -#define GPO_73_LEVEL GPO_LOW -#define GPO_74_LEVEL GPO_LOW -#define GPO_75_LEVEL GPO_LOW -#define GPO_76_LEVEL GPO_LOW -#define GPO_77_LEVEL GPO_LOW -#define GPO_78_LEVEL GPO_LOW -#define GPO_79_LEVEL GPO_LOW -#define GPO_80_LEVEL GPO_LOW -#define GPO_81_LEVEL GPO_LOW -#define GPO_82_LEVEL GPO_LOW -#define GPO_83_LEVEL GPO_LOW -#define GPO_84_LEVEL GPO_LOW -#define GPO_85_LEVEL GPO_LOW -#define GPO_86_LEVEL GPO_LOW -#define GPO_87_LEVEL GPO_LOW -#define GPO_88_LEVEL GPO_LOW -#define GPO_89_LEVEL GPO_LOW -#define GPO_90_LEVEL GPO_LOW -#define GPO_91_LEVEL GPO_LOW -#define GPO_92_LEVEL GPO_LOW -#define GPO_93_LEVEL GPO_LOW -#define GPO_94_LEVEL GPO_LOW -#define GPO_95_LEVEL GPO_LOW -#define GPO_96_LEVEL GPO_LOW -#define GPO_97_LEVEL GPO_LOW -#define GPO_98_LEVEL GPO_LOW -#define GPO_99_LEVEL GPO_LOW -#define GPO_100_LEVEL GPO_LOW -#define GPO_101_LEVEL GPO_LOW -#define GPO_102_LEVEL GPO_LOW -#define GPO_103_LEVEL GPO_LOW -#define GPO_104_LEVEL GPO_LOW -#define GPO_105_LEVEL GPO_LOW -#define GPO_106_LEVEL GPO_LOW -#define GPO_107_LEVEL GPO_LOW -#define GPO_108_LEVEL GPO_HI -#define GPO_109_LEVEL GPO_LOW -#define GPO_110_LEVEL GPO_HI -#define GPO_111_LEVEL GPO_HI -#define GPO_112_LEVEL GPO_HI -#define GPO_113_LEVEL GPO_LOW -#define GPO_114_LEVEL GPO_LOW -#define GPO_115_LEVEL GPO_LOW -#define GPO_116_LEVEL GPO_LOW -#define GPO_117_LEVEL GPO_LOW -#define GPO_118_LEVEL GPO_LOW -#define GPO_119_LEVEL GPO_LOW -#define GPO_120_LEVEL GPO_LOW -#define GPO_121_LEVEL GPO_LOW -#define GPO_122_LEVEL GPO_LOW -#define GPO_123_LEVEL GPO_LOW -#define GPO_124_LEVEL GPO_LOW -#define GPO_125_LEVEL GPO_LOW -#define GPO_126_LEVEL GPO_LOW -#define GPO_127_LEVEL GPO_LOW -#define GPO_128_LEVEL GPO_LOW -#define GPO_129_LEVEL GPO_LOW -#define GPO_130_LEVEL GPO_LOW -#define GPO_131_LEVEL GPO_LOW -#define GPO_132_LEVEL GPO_LOW -#define GPO_133_LEVEL GPO_LOW -#define GPO_134_LEVEL GPO_LOW -#define GPO_135_LEVEL GPO_LOW -#define GPO_136_LEVEL GPO_LOW -#define GPO_137_LEVEL GPO_LOW -#define GPO_138_LEVEL GPO_LOW -#define GPO_139_LEVEL GPO_LOW -#define GPO_140_LEVEL GPO_LOW -#define GPO_141_LEVEL GPO_LOW -#define GPO_142_LEVEL GPO_LOW -#define GPO_143_LEVEL GPO_LOW -#define GPO_144_LEVEL GPO_LOW -#define GPO_145_LEVEL GPO_LOW -#define GPO_146_LEVEL GPO_LOW -#define GPO_147_LEVEL GPO_LOW -#define GPO_148_LEVEL GPO_LOW -#define GPO_149_LEVEL GPO_LOW -#define GPO_150_LEVEL GPO_LOW -#define GPO_151_LEVEL GPO_LOW -#define GPO_152_LEVEL GPO_LOW -#define GPO_153_LEVEL GPO_LOW -#define GPO_154_LEVEL GPO_LOW -#define GPO_155_LEVEL GPO_LOW -#define GPO_156_LEVEL GPO_LOW -#define GPO_157_LEVEL GPO_LOW -#define GPO_158_LEVEL GPO_LOW -#define GPO_159_LEVEL GPO_LOW -#define GPO_160_LEVEL GPO_LOW -#define GPO_161_LEVEL GPO_LOW -#define GPO_162_LEVEL GPO_LOW -#define GPO_163_LEVEL GPO_LOW -#define GPO_164_LEVEL GPO_LOW -#define GPO_165_LEVEL GPO_LOW -#define GPO_166_LEVEL GPO_LOW -#define GPO_167_LEVEL GPO_LOW -#define GPO_168_LEVEL GPO_LOW -#define GPO_169_LEVEL GPO_LOW -#define GPO_170_LEVEL GPO_HI -#define GPO_171_LEVEL GPO_LOW -#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE -#define GPO_173_LEVEL GPO_LOW -#define GPO_174_LEVEL GPO_LOW -#define GPO_175_LEVEL GPO_LOW -#define GPO_176_LEVEL GPO_LOW -#define GPO_177_LEVEL GPO_LOW -#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU -#define GPO_179_LEVEL GPO_HI -#define GPO_180_LEVEL GPO_HI -#define GPO_181_LEVEL GPO_LOW -#define GPO_182_LEVEL GPO_HI -#define GPO_183_LEVEL GPO_LOW -#define GPO_184_LEVEL GPO_LOW -#define GPO_185_LEVEL GPO_LOW -#define GPO_186_LEVEL GPO_LOW -#define GPO_187_LEVEL GPO_LOW -#define GPO_188_LEVEL GPO_LOW -#define GPO_189_LEVEL GPO_LOW -#define GPO_190_LEVEL GPO_LOW -#define GPO_191_LEVEL GPO_LOW -#define GPO_192_LEVEL GPO_LOW -#define GPO_193_LEVEL GPO_LOW -#define GPO_194_LEVEL GPO_LOW -#define GPO_195_LEVEL GPO_LOW -#define GPO_196_LEVEL GPO_LOW -#define GPO_197_LEVEL GPO_LOW -#define GPO_198_LEVEL GPO_LOW -#define GPO_199_LEVEL GPO_LOW -#define GPO_200_LEVEL GPO_HI -#define GPO_201_LEVEL GPO_LOW -#define GPO_202_LEVEL GPO_LOW -#define GPO_203_LEVEL GPO_LOW -#define GPO_204_LEVEL GPO_LOW -#define GPO_205_LEVEL GPO_LOW -#define GPO_206_LEVEL GPO_LOW -#define GPO_207_LEVEL GPO_LOW -#define GPO_208_LEVEL GPO_LOW -#define GPO_209_LEVEL GPO_LOW -#define GPO_210_LEVEL GPO_LOW -#define GPO_211_LEVEL GPO_LOW -#define GPO_212_LEVEL GPO_LOW -#define GPO_213_LEVEL GPO_LOW -#define GPO_214_LEVEL GPO_LOW -#define GPO_215_LEVEL GPO_LOW -#define GPO_216_LEVEL GPO_LOW -#define GPO_217_LEVEL GPO_LOW -#define GPO_218_LEVEL GPO_LOW -#define GPO_219_LEVEL GPO_LOW -#define GPO_220_LEVEL GPO_LOW -#define GPO_221_LEVEL GPO_LOW -#define GPO_222_LEVEL GPO_LOW -#define GPO_223_LEVEL GPO_LOW -#define GPO_224_LEVEL GPO_LOW -#define GPO_225_LEVEL GPO_LOW -#define GPO_226_LEVEL GPO_LOW -#define GPO_227_LEVEL GPO_LOW -#define GPO_228_LEVEL GPO_LOW -#define GPO_229_LEVEL GPO_LOW +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW
-#define GPIO_NONSTICKY (0<<2) -#define GPIO_STICKY (1<<2) +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2)
-#define GPIO_00_STICKY GPIO_NONSTICKY -#define GPIO_01_STICKY GPIO_NONSTICKY -#define GPIO_02_STICKY GPIO_NONSTICKY -#define GPIO_03_STICKY GPIO_NONSTICKY -#define GPIO_04_STICKY GPIO_NONSTICKY -#define GPIO_05_STICKY GPIO_NONSTICKY -#define GPIO_06_STICKY GPIO_NONSTICKY -#define GPIO_07_STICKY GPIO_NONSTICKY -#define GPIO_08_STICKY GPIO_NONSTICKY -#define GPIO_09_STICKY GPIO_NONSTICKY -#define GPIO_10_STICKY GPIO_NONSTICKY -#define GPIO_11_STICKY GPIO_NONSTICKY -#define GPIO_12_STICKY GPIO_NONSTICKY -#define GPIO_13_STICKY GPIO_NONSTICKY -#define GPIO_14_STICKY GPIO_NONSTICKY -#define GPIO_15_STICKY GPIO_NONSTICKY -#define GPIO_16_STICKY GPIO_NONSTICKY -#define GPIO_17_STICKY GPIO_STICKY -#define GPIO_18_STICKY GPIO_NONSTICKY -#define GPIO_19_STICKY GPIO_NONSTICKY -#define GPIO_20_STICKY GPIO_NONSTICKY -#define GPIO_21_STICKY GPIO_NONSTICKY -#define GPIO_22_STICKY GPIO_NONSTICKY -#define GPIO_23_STICKY GPIO_NONSTICKY -#define GPIO_24_STICKY GPIO_NONSTICKY -#define GPIO_25_STICKY GPIO_NONSTICKY -#define GPIO_26_STICKY GPIO_NONSTICKY -#define GPIO_27_STICKY GPIO_NONSTICKY -#define GPIO_28_STICKY GPIO_NONSTICKY -#define GPIO_29_STICKY GPIO_NONSTICKY -#define GPIO_30_STICKY GPIO_NONSTICKY -#define GPIO_31_STICKY GPIO_NONSTICKY -#define GPIO_32_STICKY GPIO_NONSTICKY -#define GPIO_33_STICKY GPIO_NONSTICKY -#define GPIO_34_STICKY GPIO_NONSTICKY -#define GPIO_35_STICKY GPIO_NONSTICKY -#define GPIO_36_STICKY GPIO_NONSTICKY -#define GPIO_37_STICKY GPIO_NONSTICKY -#define GPIO_38_STICKY GPIO_NONSTICKY -#define GPIO_39_STICKY GPIO_NONSTICKY -#define GPIO_40_STICKY GPIO_NONSTICKY -#define GPIO_41_STICKY GPIO_NONSTICKY -#define GPIO_42_STICKY GPIO_NONSTICKY -#define GPIO_43_STICKY GPIO_NONSTICKY -#define GPIO_44_STICKY GPIO_NONSTICKY -#define GPIO_45_STICKY GPIO_NONSTICKY -#define GPIO_46_STICKY GPIO_NONSTICKY -#define GPIO_47_STICKY GPIO_NONSTICKY -#define GPIO_48_STICKY GPIO_NONSTICKY -#define GPIO_49_STICKY GPIO_NONSTICKY -#define GPIO_50_STICKY GPIO_NONSTICKY -#define GPIO_51_STICKY GPIO_NONSTICKY -#define GPIO_52_STICKY GPIO_NONSTICKY -#define GPIO_53_STICKY GPIO_NONSTICKY -#define GPIO_54_STICKY GPIO_NONSTICKY -#define GPIO_55_STICKY GPIO_NONSTICKY -#define GPIO_56_STICKY GPIO_NONSTICKY -#define GPIO_57_STICKY GPIO_NONSTICKY -#define GPIO_58_STICKY GPIO_NONSTICKY -#define GPIO_59_STICKY GPIO_NONSTICKY -#define GPIO_60_STICKY GPIO_NONSTICKY -#define GPIO_61_STICKY GPIO_NONSTICKY -#define GPIO_62_STICKY GPIO_NONSTICKY -#define GPIO_63_STICKY GPIO_NONSTICKY -#define GPIO_64_STICKY GPIO_NONSTICKY -#define GPIO_65_STICKY GPIO_NONSTICKY -#define GPIO_66_STICKY GPIO_NONSTICKY -#define GPIO_67_STICKY GPIO_NONSTICKY -#define GPIO_68_STICKY GPIO_NONSTICKY -#define GPIO_69_STICKY GPIO_NONSTICKY -#define GPIO_70_STICKY GPIO_NONSTICKY -#define GPIO_71_STICKY GPIO_NONSTICKY -#define GPIO_72_STICKY GPIO_NONSTICKY -#define GPIO_73_STICKY GPIO_NONSTICKY -#define GPIO_74_STICKY GPIO_NONSTICKY -#define GPIO_75_STICKY GPIO_NONSTICKY -#define GPIO_76_STICKY GPIO_NONSTICKY -#define GPIO_77_STICKY GPIO_NONSTICKY -#define GPIO_78_STICKY GPIO_NONSTICKY -#define GPIO_79_STICKY GPIO_NONSTICKY -#define GPIO_80_STICKY GPIO_NONSTICKY -#define GPIO_81_STICKY GPIO_NONSTICKY -#define GPIO_82_STICKY GPIO_NONSTICKY -#define GPIO_83_STICKY GPIO_NONSTICKY -#define GPIO_84_STICKY GPIO_NONSTICKY -#define GPIO_85_STICKY GPIO_NONSTICKY -#define GPIO_86_STICKY GPIO_NONSTICKY -#define GPIO_87_STICKY GPIO_NONSTICKY -#define GPIO_88_STICKY GPIO_NONSTICKY -#define GPIO_89_STICKY GPIO_NONSTICKY -#define GPIO_90_STICKY GPIO_NONSTICKY -#define GPIO_91_STICKY GPIO_NONSTICKY -#define GPIO_92_STICKY GPIO_NONSTICKY -#define GPIO_93_STICKY GPIO_NONSTICKY -#define GPIO_94_STICKY GPIO_NONSTICKY -#define GPIO_95_STICKY GPIO_NONSTICKY -#define GPIO_96_STICKY GPIO_NONSTICKY -#define GPIO_97_STICKY GPIO_NONSTICKY -#define GPIO_98_STICKY GPIO_NONSTICKY -#define GPIO_99_STICKY GPIO_NONSTICKY -#define GPIO_100_STICKY GPIO_NONSTICKY -#define GPIO_101_STICKY GPIO_NONSTICKY -#define GPIO_102_STICKY GPIO_STICKY -#define GPIO_103_STICKY GPIO_STICKY -#define GPIO_104_STICKY GPIO_NONSTICKY -#define GPIO_105_STICKY GPIO_NONSTICKY -#define GPIO_106_STICKY GPIO_NONSTICKY -#define GPIO_107_STICKY GPIO_NONSTICKY -#define GPIO_108_STICKY GPIO_STICKY -#define GPIO_109_STICKY GPIO_NONSTICKY -#define GPIO_110_STICKY GPIO_NONSTICKY -#define GPIO_111_STICKY GPIO_NONSTICKY -#define GPIO_112_STICKY GPIO_NONSTICKY -#define GPIO_113_STICKY GPIO_NONSTICKY -#define GPIO_114_STICKY GPIO_NONSTICKY -#define GPIO_115_STICKY GPIO_NONSTICKY -#define GPIO_116_STICKY GPIO_NONSTICKY -#define GPIO_117_STICKY GPIO_NONSTICKY -#define GPIO_118_STICKY GPIO_NONSTICKY -#define GPIO_119_STICKY GPIO_NONSTICKY -#define GPIO_120_STICKY GPIO_NONSTICKY -#define GPIO_121_STICKY GPIO_NONSTICKY -#define GPIO_122_STICKY GPIO_NONSTICKY -#define GPIO_123_STICKY GPIO_NONSTICKY -#define GPIO_124_STICKY GPIO_NONSTICKY -#define GPIO_125_STICKY GPIO_NONSTICKY -#define GPIO_126_STICKY GPIO_NONSTICKY -#define GPIO_127_STICKY GPIO_NONSTICKY -#define GPIO_128_STICKY GPIO_NONSTICKY -#define GPIO_129_STICKY GPIO_NONSTICKY -#define GPIO_130_STICKY GPIO_NONSTICKY -#define GPIO_131_STICKY GPIO_NONSTICKY -#define GPIO_132_STICKY GPIO_NONSTICKY -#define GPIO_133_STICKY GPIO_NONSTICKY -#define GPIO_134_STICKY GPIO_NONSTICKY -#define GPIO_135_STICKY GPIO_NONSTICKY -#define GPIO_136_STICKY GPIO_NONSTICKY -#define GPIO_137_STICKY GPIO_NONSTICKY -#define GPIO_138_STICKY GPIO_NONSTICKY -#define GPIO_139_STICKY GPIO_NONSTICKY -#define GPIO_140_STICKY GPIO_NONSTICKY -#define GPIO_141_STICKY GPIO_NONSTICKY -#define GPIO_142_STICKY GPIO_NONSTICKY -#define GPIO_143_STICKY GPIO_NONSTICKY -#define GPIO_144_STICKY GPIO_NONSTICKY -#define GPIO_145_STICKY GPIO_NONSTICKY -#define GPIO_146_STICKY GPIO_NONSTICKY -#define GPIO_147_STICKY GPIO_NONSTICKY -#define GPIO_148_STICKY GPIO_NONSTICKY -#define GPIO_149_STICKY GPIO_NONSTICKY -#define GPIO_150_STICKY GPIO_NONSTICKY -#define GPIO_151_STICKY GPIO_NONSTICKY -#define GPIO_152_STICKY GPIO_NONSTICKY -#define GPIO_153_STICKY GPIO_NONSTICKY -#define GPIO_154_STICKY GPIO_NONSTICKY -#define GPIO_155_STICKY GPIO_NONSTICKY -#define GPIO_156_STICKY GPIO_NONSTICKY -#define GPIO_157_STICKY GPIO_NONSTICKY -#define GPIO_158_STICKY GPIO_NONSTICKY -#define GPIO_159_STICKY GPIO_NONSTICKY -#define GPIO_160_STICKY GPIO_NONSTICKY -#define GPIO_161_STICKY GPIO_NONSTICKY -#define GPIO_162_STICKY GPIO_NONSTICKY -#define GPIO_163_STICKY GPIO_NONSTICKY -#define GPIO_164_STICKY GPIO_NONSTICKY -#define GPIO_165_STICKY GPIO_NONSTICKY -#define GPIO_166_STICKY GPIO_NONSTICKY -#define GPIO_167_STICKY GPIO_NONSTICKY -#define GPIO_168_STICKY GPIO_NONSTICKY -#define GPIO_169_STICKY GPIO_NONSTICKY -#define GPIO_170_STICKY GPIO_STICKY -#define GPIO_171_STICKY GPIO_NONSTICKY -#define GPIO_172_STICKY GPIO_STICKY -#define GPIO_173_STICKY GPIO_NONSTICKY -#define GPIO_174_STICKY GPIO_NONSTICKY -#define GPIO_175_STICKY GPIO_NONSTICKY -#define GPIO_176_STICKY GPIO_NONSTICKY -#define GPIO_177_STICKY GPIO_NONSTICKY -#define GPIO_178_STICKY GPIO_NONSTICKY -#define GPIO_179_STICKY GPIO_NONSTICKY -#define GPIO_180_STICKY GPIO_NONSTICKY -#define GPIO_181_STICKY GPIO_NONSTICKY -#define GPIO_182_STICKY GPIO_NONSTICKY -#define GPIO_183_STICKY GPIO_NONSTICKY -#define GPIO_184_STICKY GPIO_NONSTICKY -#define GPIO_185_STICKY GPIO_NONSTICKY -#define GPIO_186_STICKY GPIO_NONSTICKY -#define GPIO_187_STICKY GPIO_NONSTICKY -#define GPIO_188_STICKY GPIO_NONSTICKY -#define GPIO_189_STICKY GPIO_NONSTICKY -#define GPIO_190_STICKY GPIO_NONSTICKY -#define GPIO_191_STICKY GPIO_NONSTICKY -#define GPIO_192_STICKY GPIO_NONSTICKY -#define GPIO_193_STICKY GPIO_NONSTICKY -#define GPIO_194_STICKY GPIO_NONSTICKY -#define GPIO_195_STICKY GPIO_NONSTICKY -#define GPIO_196_STICKY GPIO_NONSTICKY -#define GPIO_197_STICKY GPIO_NONSTICKY -#define GPIO_198_STICKY GPIO_NONSTICKY -#define GPIO_199_STICKY GPIO_NONSTICKY -#define GPIO_200_STICKY GPIO_NONSTICKY -#define GPIO_201_STICKY GPIO_NONSTICKY -#define GPIO_202_STICKY GPIO_NONSTICKY -#define GPIO_203_STICKY GPIO_NONSTICKY -#define GPIO_204_STICKY GPIO_NONSTICKY -#define GPIO_205_STICKY GPIO_NONSTICKY -#define GPIO_206_STICKY GPIO_NONSTICKY -#define GPIO_207_STICKY GPIO_NONSTICKY -#define GPIO_208_STICKY GPIO_NONSTICKY -#define GPIO_209_STICKY GPIO_NONSTICKY -#define GPIO_210_STICKY GPIO_NONSTICKY -#define GPIO_211_STICKY GPIO_NONSTICKY -#define GPIO_212_STICKY GPIO_NONSTICKY -#define GPIO_213_STICKY GPIO_NONSTICKY -#define GPIO_214_STICKY GPIO_NONSTICKY -#define GPIO_215_STICKY GPIO_NONSTICKY -#define GPIO_216_STICKY GPIO_NONSTICKY -#define GPIO_217_STICKY GPIO_NONSTICKY -#define GPIO_218_STICKY GPIO_NONSTICKY -#define GPIO_219_STICKY GPIO_NONSTICKY -#define GPIO_220_STICKY GPIO_NONSTICKY -#define GPIO_221_STICKY GPIO_NONSTICKY -#define GPIO_222_STICKY GPIO_NONSTICKY -#define GPIO_223_STICKY GPIO_NONSTICKY -#define GPIO_224_STICKY GPIO_NONSTICKY -#define GPIO_225_STICKY GPIO_NONSTICKY -#define GPIO_226_STICKY GPIO_NONSTICKY -#define GPIO_227_STICKY GPIO_NONSTICKY -#define GPIO_228_STICKY GPIO_NONSTICKY -#define GPIO_229_STICKY GPIO_NONSTICKY +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY
-#define PULLUP_ENABLE (0<<3) -#define PULLUP_DISABLE (1<<3) +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3)
-#define GPIO_00_PULLUP PULLUP_DISABLE -#define GPIO_01_PULLUP PULLUP_DISABLE -#define GPIO_02_PULLUP PULLUP_DISABLE -#define GPIO_03_PULLUP PULLUP_DISABLE -#define GPIO_04_PULLUP PULLUP_DISABLE -#define GPIO_05_PULLUP PULLUP_DISABLE -#define GPIO_06_PULLUP PULLUP_DISABLE -#define GPIO_07_PULLUP PULLUP_DISABLE -#define GPIO_08_PULLUP PULLUP_DISABLE -#define GPIO_09_PULLUP PULLUP_DISABLE -#define GPIO_10_PULLUP PULLUP_DISABLE -#define GPIO_11_PULLUP PULLUP_DISABLE -#define GPIO_12_PULLUP PULLUP_DISABLE -#define GPIO_13_PULLUP PULLUP_DISABLE -#define GPIO_14_PULLUP PULLUP_DISABLE -#define GPIO_15_PULLUP PULLUP_DISABLE -#define GPIO_16_PULLUP PULLUP_DISABLE -#define GPIO_17_PULLUP PULLUP_DISABLE -#define GPIO_18_PULLUP PULLUP_DISABLE -#define GPIO_19_PULLUP PULLUP_DISABLE -#define GPIO_20_PULLUP PULLUP_DISABLE -#define GPIO_21_PULLUP PULLUP_DISABLE -#define GPIO_22_PULLUP PULLUP_DISABLE -#define GPIO_23_PULLUP PULLUP_DISABLE -#define GPIO_24_PULLUP PULLUP_DISABLE -#define GPIO_25_PULLUP PULLUP_DISABLE -#define GPIO_26_PULLUP PULLUP_DISABLE -#define GPIO_27_PULLUP PULLUP_DISABLE -#define GPIO_28_PULLUP PULLUP_DISABLE -#define GPIO_29_PULLUP PULLUP_DISABLE -#define GPIO_30_PULLUP PULLUP_DISABLE -#define GPIO_31_PULLUP PULLUP_DISABLE -#define GPIO_32_PULLUP PULLUP_DISABLE -#define GPIO_33_PULLUP PULLUP_DISABLE -#define GPIO_34_PULLUP PULLUP_DISABLE -#define GPIO_35_PULLUP PULLUP_DISABLE -#define GPIO_36_PULLUP PULLUP_DISABLE -#define GPIO_37_PULLUP PULLUP_DISABLE -#define GPIO_38_PULLUP PULLUP_DISABLE -#define GPIO_39_PULLUP PULLUP_DISABLE -#define GPIO_40_PULLUP PULLUP_DISABLE -#define GPIO_41_PULLUP PULLUP_DISABLE -#define GPIO_42_PULLUP PULLUP_DISABLE -#define GPIO_43_PULLUP PULLUP_DISABLE -#define GPIO_44_PULLUP PULLUP_DISABLE -#define GPIO_45_PULLUP PULLUP_DISABLE -#define GPIO_46_PULLUP PULLUP_DISABLE -#define GPIO_47_PULLUP PULLUP_DISABLE -#define GPIO_48_PULLUP PULLUP_DISABLE -#define GPIO_49_PULLUP PULLUP_DISABLE -#define GPIO_50_PULLUP PULLUP_DISABLE -#define GPIO_51_PULLUP PULLUP_DISABLE -#define GPIO_52_PULLUP PULLUP_DISABLE -#define GPIO_53_PULLUP PULLUP_DISABLE -#define GPIO_54_PULLUP PULLUP_DISABLE -#define GPIO_55_PULLUP PULLUP_DISABLE -#define GPIO_56_PULLUP PULLUP_DISABLE -#define GPIO_57_PULLUP PULLUP_DISABLE -#define GPIO_58_PULLUP PULLUP_DISABLE -#define GPIO_59_PULLUP PULLUP_DISABLE -#define GPIO_60_PULLUP PULLUP_DISABLE -#define GPIO_61_PULLUP PULLUP_DISABLE -#define GPIO_62_PULLUP PULLUP_DISABLE -#define GPIO_63_PULLUP PULLUP_DISABLE -#define GPIO_64_PULLUP PULLUP_DISABLE -#define GPIO_65_PULLUP PULLUP_DISABLE -#define GPIO_66_PULLUP PULLUP_DISABLE -#define GPIO_67_PULLUP PULLUP_DISABLE -#define GPIO_68_PULLUP PULLUP_DISABLE -#define GPIO_69_PULLUP PULLUP_DISABLE -#define GPIO_70_PULLUP PULLUP_DISABLE -#define GPIO_71_PULLUP PULLUP_DISABLE -#define GPIO_72_PULLUP PULLUP_DISABLE -#define GPIO_73_PULLUP PULLUP_DISABLE -#define GPIO_74_PULLUP PULLUP_DISABLE -#define GPIO_75_PULLUP PULLUP_DISABLE -#define GPIO_76_PULLUP PULLUP_DISABLE -#define GPIO_77_PULLUP PULLUP_DISABLE -#define GPIO_78_PULLUP PULLUP_DISABLE -#define GPIO_79_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_80_PULLUP PULLUP_DISABLE -#define GPIO_81_PULLUP PULLUP_DISABLE -#define GPIO_82_PULLUP PULLUP_DISABLE -#define GPIO_83_PULLUP PULLUP_DISABLE -#define GPIO_84_PULLUP PULLUP_DISABLE -#define GPIO_85_PULLUP PULLUP_DISABLE -#define GPIO_86_PULLUP PULLUP_DISABLE -#define GPIO_87_PULLUP PULLUP_DISABLE -#define GPIO_88_PULLUP PULLUP_DISABLE -#define GPIO_89_PULLUP PULLUP_DISABLE -#define GPIO_90_PULLUP PULLUP_DISABLE -#define GPIO_91_PULLUP PULLUP_DISABLE -#define GPIO_92_PULLUP PULLUP_DISABLE -#define GPIO_93_PULLUP PULLUP_DISABLE -#define GPIO_94_PULLUP PULLUP_DISABLE -#define GPIO_95_PULLUP PULLUP_DISABLE -#define GPIO_96_PULLUP PULLUP_DISABLE -#define GPIO_97_PULLUP PULLUP_DISABLE -#define GPIO_98_PULLUP PULLUP_DISABLE -#define GPIO_99_PULLUP PULLUP_DISABLE -#define GPIO_100_PULLUP PULLUP_DISABLE -#define GPIO_101_PULLUP PULLUP_DISABLE -#define GPIO_102_PULLUP PULLUP_DISABLE -#define GPIO_103_PULLUP PULLUP_DISABLE -#define GPIO_104_PULLUP PULLUP_DISABLE -#define GPIO_105_PULLUP PULLUP_DISABLE -#define GPIO_106_PULLUP PULLUP_DISABLE -#define GPIO_107_PULLUP PULLUP_DISABLE -#define GPIO_108_PULLUP PULLUP_DISABLE -#define GPIO_109_PULLUP PULLUP_DISABLE -#define GPIO_110_PULLUP PULLUP_DISABLE -#define GPIO_111_PULLUP PULLUP_DISABLE -#define GPIO_112_PULLUP PULLUP_DISABLE -#define GPIO_113_PULLUP PULLUP_DISABLE -#define GPIO_114_PULLUP PULLUP_DISABLE -#define GPIO_115_PULLUP PULLUP_DISABLE -#define GPIO_116_PULLUP PULLUP_DISABLE -#define GPIO_117_PULLUP PULLUP_DISABLE -#define GPIO_118_PULLUP PULLUP_ENABLE -#define GPIO_119_PULLUP PULLUP_DISABLE -#define GPIO_120_PULLUP PULLUP_DISABLE -#define GPIO_121_PULLUP PULLUP_DISABLE -#define GPIO_122_PULLUP PULLUP_DISABLE -#define GPIO_123_PULLUP PULLUP_DISABLE -#define GPIO_124_PULLUP PULLUP_DISABLE -#define GPIO_125_PULLUP PULLUP_DISABLE -#define GPIO_126_PULLUP PULLUP_DISABLE -#define GPIO_127_PULLUP PULLUP_DISABLE -#define GPIO_128_PULLUP PULLUP_DISABLE -#define GPIO_129_PULLUP PULLUP_DISABLE -#define GPIO_130_PULLUP PULLUP_DISABLE -#define GPIO_131_PULLUP PULLUP_DISABLE -#define GPIO_132_PULLUP PULLUP_DISABLE -#define GPIO_133_PULLUP PULLUP_DISABLE -#define GPIO_134_PULLUP PULLUP_DISABLE -#define GPIO_135_PULLUP PULLUP_DISABLE -#define GPIO_136_PULLUP PULLUP_DISABLE -#define GPIO_137_PULLUP PULLUP_DISABLE -#define GPIO_138_PULLUP PULLUP_DISABLE -#define GPIO_139_PULLUP PULLUP_DISABLE -#define GPIO_140_PULLUP PULLUP_DISABLE -#define GPIO_141_PULLUP PULLUP_DISABLE -#define GPIO_142_PULLUP PULLUP_DISABLE -#define GPIO_143_PULLUP PULLUP_DISABLE -#define GPIO_144_PULLUP PULLUP_DISABLE -#define GPIO_145_PULLUP PULLUP_DISABLE -#define GPIO_146_PULLUP PULLUP_DISABLE -#define GPIO_147_PULLUP PULLUP_DISABLE -#define GPIO_148_PULLUP PULLUP_DISABLE -#define GPIO_149_PULLUP PULLUP_DISABLE -#define GPIO_150_PULLUP PULLUP_DISABLE -#define GPIO_151_PULLUP PULLUP_DISABLE -#define GPIO_152_PULLUP PULLUP_DISABLE -#define GPIO_153_PULLUP PULLUP_DISABLE -#define GPIO_154_PULLUP PULLUP_DISABLE -#define GPIO_155_PULLUP PULLUP_DISABLE -#define GPIO_156_PULLUP PULLUP_DISABLE -#define GPIO_157_PULLUP PULLUP_DISABLE -#define GPIO_158_PULLUP PULLUP_DISABLE -#define GPIO_159_PULLUP PULLUP_DISABLE -#define GPIO_160_PULLUP PULLUP_DISABLE -#define GPIO_161_PULLUP PULLUP_DISABLE -#define GPIO_162_PULLUP PULLUP_DISABLE -#define GPIO_163_PULLUP PULLUP_DISABLE -#define GPIO_164_PULLUP PULLUP_DISABLE -#define GPIO_165_PULLUP PULLUP_DISABLE -#define GPIO_166_PULLUP PULLUP_DISABLE -#define GPIO_167_PULLUP PULLUP_DISABLE -#define GPIO_168_PULLUP PULLUP_DISABLE -#define GPIO_169_PULLUP PULLUP_DISABLE -#define GPIO_170_PULLUP PULLUP_DISABLE -#define GPIO_171_PULLUP PULLUP_DISABLE -#define GPIO_172_PULLUP PULLUP_DISABLE -#define GPIO_173_PULLUP PULLUP_DISABLE -#define GPIO_174_PULLUP PULLUP_DISABLE -#define GPIO_175_PULLUP PULLUP_DISABLE -#define GPIO_176_PULLUP PULLUP_DISABLE -#define GPIO_177_PULLUP PULLUP_DISABLE -#define GPIO_178_PULLUP PULLUP_DISABLE -#define GPIO_179_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_180_PULLUP PULLUP_DISABLE -#define GPIO_181_PULLUP PULLUP_DISABLE -#define GPIO_182_PULLUP PULLUP_DISABLE -#define GPIO_183_PULLUP PULLUP_DISABLE -#define GPIO_184_PULLUP PULLUP_DISABLE -#define GPIO_185_PULLUP PULLUP_DISABLE -#define GPIO_186_PULLUP PULLUP_DISABLE -#define GPIO_187_PULLUP PULLUP_DISABLE -#define GPIO_188_PULLUP PULLUP_DISABLE -#define GPIO_189_PULLUP PULLUP_DISABLE -#define GPIO_190_PULLUP PULLUP_DISABLE -#define GPIO_191_PULLUP PULLUP_DISABLE -#define GPIO_192_PULLUP PULLUP_DISABLE -#define GPIO_193_PULLUP PULLUP_DISABLE -#define GPIO_194_PULLUP PULLUP_DISABLE -#define GPIO_195_PULLUP PULLUP_DISABLE -#define GPIO_196_PULLUP PULLUP_DISABLE -#define GPIO_197_PULLUP PULLUP_DISABLE -#define GPIO_198_PULLUP PULLUP_DISABLE -#define GPIO_199_PULLUP PULLUP_DISABLE -#define GPIO_200_PULLUP PULLUP_DISABLE -#define GPIO_201_PULLUP PULLUP_DISABLE -#define GPIO_202_PULLUP PULLUP_DISABLE -#define GPIO_203_PULLUP PULLUP_DISABLE -#define GPIO_204_PULLUP PULLUP_DISABLE -#define GPIO_205_PULLUP PULLUP_DISABLE -#define GPIO_206_PULLUP PULLUP_DISABLE -#define GPIO_207_PULLUP PULLUP_DISABLE -#define GPIO_208_PULLUP PULLUP_DISABLE -#define GPIO_209_PULLUP PULLUP_DISABLE -#define GPIO_210_PULLUP PULLUP_DISABLE -#define GPIO_211_PULLUP PULLUP_DISABLE -#define GPIO_212_PULLUP PULLUP_DISABLE -#define GPIO_213_PULLUP PULLUP_DISABLE -#define GPIO_214_PULLUP PULLUP_DISABLE -#define GPIO_215_PULLUP PULLUP_DISABLE -#define GPIO_216_PULLUP PULLUP_DISABLE -#define GPIO_217_PULLUP PULLUP_DISABLE -#define GPIO_218_PULLUP PULLUP_DISABLE -#define GPIO_219_PULLUP PULLUP_DISABLE -#define GPIO_220_PULLUP PULLUP_DISABLE -#define GPIO_221_PULLUP PULLUP_DISABLE -#define GPIO_222_PULLUP PULLUP_DISABLE -#define GPIO_223_PULLUP PULLUP_DISABLE -#define GPIO_224_PULLUP PULLUP_DISABLE -#define GPIO_225_PULLUP PULLUP_DISABLE -#define GPIO_226_PULLUP PULLUP_DISABLE -#define GPIO_227_PULLUP PULLUP_DISABLE -#define GPIO_228_PULLUP PULLUP_DISABLE -#define GPIO_229_PULLUP PULLUP_DISABLE +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE
-#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_ENABLE (1<<4) #define PULLDOWN_DISABLE (0<<4)
#define GPIO_00_PULLDOWN PULLDOWN_DISABLE @@ -1532,230 +1532,230 @@ #define GPIO_228_PULLDOWN PULLDOWN_DISABLE #define GPIO_229_PULLDOWN PULLDOWN_DISABLE
-#define EVENT_DISABLE 0 -#define EVENT_ENABLE 1 +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1
-#define GEVENT_00_EVENTENABLE EVENT_DISABLE -#define GEVENT_01_EVENTENABLE EVENT_DISABLE -#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# -#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# -#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# -#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# -#define GEVENT_06_EVENTENABLE EVENT_DISABLE -#define GEVENT_07_EVENTENABLE EVENT_DISABLE -#define GEVENT_08_EVENTENABLE EVENT_DISABLE -#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO -#define GEVENT_10_EVENTENABLE EVENT_DISABLE -#define GEVENT_11_EVENTENABLE EVENT_DISABLE -#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# -#define GEVENT_13_EVENTENABLE EVENT_DISABLE -#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# -#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# -#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA -#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN -#define GEVENT_18_EVENTENABLE EVENT_DISABLE -#define GEVENT_19_EVENTENABLE EVENT_DISABLE -#define GEVENT_20_EVENTENABLE EVENT_DISABLE -#define GEVENT_21_EVENTENABLE EVENT_DISABLE -#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# -#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI#
-#define SCITRIG_LOW 0 -#define SCITRIG_HI 1 +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1
-#define GEVENT_00_SCITRIG SCITRIG_LOW -#define GEVENT_01_SCITRIG SCITRIG_LOW -#define GEVENT_02_SCITRIG SCITRIG_LOW -#define GEVENT_03_SCITRIG SCITRIG_LOW -#define GEVENT_04_SCITRIG SCITRIG_LOW -#define GEVENT_05_SCITRIG SCITRIG_LOW -#define GEVENT_06_SCITRIG SCITRIG_LOW -#define GEVENT_07_SCITRIG SCITRIG_LOW -#define GEVENT_08_SCITRIG SCITRIG_LOW -#define GEVENT_09_SCITRIG SCITRIG_LOW -#define GEVENT_10_SCITRIG SCITRIG_LOW -#define GEVENT_11_SCITRIG SCITRIG_LOW -#define GEVENT_12_SCITRIG SCITRIG_LOW -#define GEVENT_13_SCITRIG SCITRIG_LOW -#define GEVENT_14_SCITRIG SCITRIG_LOW -#define GEVENT_15_SCITRIG SCITRIG_LOW -#define GEVENT_16_SCITRIG SCITRIG_LOW -#define GEVENT_17_SCITRIG SCITRIG_HI -#define GEVENT_18_SCITRIG SCITRIG_LOW -#define GEVENT_19_SCITRIG SCITRIG_LOW -#define GEVENT_20_SCITRIG SCITRIG_LOW -#define GEVENT_21_SCITRIG SCITRIG_LOW -#define GEVENT_22_SCITRIG SCITRIG_LOW -#define GEVENT_23_SCITRIG SCITRIG_LOW +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW
-#define SCILEVEL_EDGE 0 -#define SCILEVEL_LEVEL 1 +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1
-#define GEVENT_00_SCILEVEL SCILEVEL_EDGE -#define GEVENT_01_SCILEVEL SCILEVEL_EDGE -#define GEVENT_02_SCILEVEL SCILEVEL_EDGE -#define GEVENT_03_SCILEVEL SCILEVEL_EDGE -#define GEVENT_04_SCILEVEL SCILEVEL_EDGE -#define GEVENT_05_SCILEVEL SCILEVEL_EDGE -#define GEVENT_06_SCILEVEL SCILEVEL_EDGE -#define GEVENT_07_SCILEVEL SCILEVEL_EDGE -#define GEVENT_08_SCILEVEL SCILEVEL_EDGE -#define GEVENT_09_SCILEVEL SCILEVEL_EDGE -#define GEVENT_10_SCILEVEL SCILEVEL_EDGE -#define GEVENT_11_SCILEVEL SCILEVEL_EDGE -#define GEVENT_12_SCILEVEL SCILEVEL_EDGE -#define GEVENT_13_SCILEVEL SCILEVEL_EDGE -#define GEVENT_14_SCILEVEL SCILEVEL_EDGE -#define GEVENT_15_SCILEVEL SCILEVEL_EDGE -#define GEVENT_16_SCILEVEL SCILEVEL_EDGE -#define GEVENT_17_SCILEVEL SCILEVEL_EDGE -#define GEVENT_18_SCILEVEL SCILEVEL_EDGE -#define GEVENT_19_SCILEVEL SCILEVEL_EDGE -#define GEVENT_20_SCILEVEL SCILEVEL_EDGE -#define GEVENT_21_SCILEVEL SCILEVEL_EDGE -#define GEVENT_22_SCILEVEL SCILEVEL_EDGE -#define GEVENT_23_SCILEVEL SCILEVEL_EDGE +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE
-#define SMISCI_DISABLE 0 -#define SMISCI_ENABLE 1 +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1
-#define GEVENT_00_SMISCIEN SMISCI_DISABLE -#define GEVENT_01_SMISCIEN SMISCI_DISABLE -#define GEVENT_02_SMISCIEN SMISCI_DISABLE -#define GEVENT_03_SMISCIEN SMISCI_DISABLE -#define GEVENT_04_SMISCIEN SMISCI_DISABLE -#define GEVENT_05_SMISCIEN SMISCI_DISABLE -#define GEVENT_06_SMISCIEN SMISCI_DISABLE -#define GEVENT_07_SMISCIEN SMISCI_DISABLE -#define GEVENT_08_SMISCIEN SMISCI_DISABLE -#define GEVENT_09_SMISCIEN SMISCI_DISABLE -#define GEVENT_10_SMISCIEN SMISCI_DISABLE -#define GEVENT_11_SMISCIEN SMISCI_DISABLE -#define GEVENT_12_SMISCIEN SMISCI_DISABLE -#define GEVENT_13_SMISCIEN SMISCI_DISABLE -#define GEVENT_14_SMISCIEN SMISCI_DISABLE -#define GEVENT_15_SMISCIEN SMISCI_DISABLE -#define GEVENT_16_SMISCIEN SMISCI_DISABLE -#define GEVENT_17_SMISCIEN SMISCI_DISABLE -#define GEVENT_18_SMISCIEN SMISCI_DISABLE -#define GEVENT_19_SMISCIEN SMISCI_DISABLE -#define GEVENT_20_SMISCIEN SMISCI_DISABLE -#define GEVENT_21_SMISCIEN SMISCI_DISABLE -#define GEVENT_22_SMISCIEN SMISCI_DISABLE -#define GEVENT_23_SMISCIEN SMISCI_DISABLE +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE
-#define SCIS0_DISABLE 0 -#define SCIS0_ENABLE 1 +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1
-#define GEVENT_00_SCIS0EN SCIS0_DISABLE -#define GEVENT_01_SCIS0EN SCIS0_DISABLE -#define GEVENT_02_SCIS0EN SCIS0_DISABLE -#define GEVENT_03_SCIS0EN SCIS0_DISABLE -#define GEVENT_04_SCIS0EN SCIS0_DISABLE -#define GEVENT_05_SCIS0EN SCIS0_DISABLE -#define GEVENT_06_SCIS0EN SCIS0_DISABLE -#define GEVENT_07_SCIS0EN SCIS0_DISABLE -#define GEVENT_08_SCIS0EN SCIS0_DISABLE -#define GEVENT_09_SCIS0EN SCIS0_DISABLE -#define GEVENT_10_SCIS0EN SCIS0_DISABLE -#define GEVENT_11_SCIS0EN SCIS0_DISABLE -#define GEVENT_12_SCIS0EN SCIS0_DISABLE -#define GEVENT_13_SCIS0EN SCIS0_DISABLE -#define GEVENT_14_SCIS0EN SCIS0_DISABLE -#define GEVENT_15_SCIS0EN SCIS0_DISABLE -#define GEVENT_16_SCIS0EN SCIS0_DISABLE -#define GEVENT_17_SCIS0EN SCIS0_DISABLE -#define GEVENT_18_SCIS0EN SCIS0_DISABLE -#define GEVENT_19_SCIS0EN SCIS0_DISABLE -#define GEVENT_20_SCIS0EN SCIS0_DISABLE -#define GEVENT_21_SCIS0EN SCIS0_DISABLE -#define GEVENT_22_SCIS0EN SCIS0_DISABLE -#define GEVENT_23_SCIS0EN SCIS0_DISABLE +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE
-#define GEVENT_SCIMASK 0x1F -#define GEVENT_00_SCIMAP 0 -#define GEVENT_01_SCIMAP 1 -#define GEVENT_02_SCIMAP 2 -#define GEVENT_03_SCIMAP 3 -#define GEVENT_04_SCIMAP 4 -#define GEVENT_05_SCIMAP 5 -#define GEVENT_06_SCIMAP 6 -#define GEVENT_07_SCIMAP 7 -#define GEVENT_08_SCIMAP 8 -#define GEVENT_09_SCIMAP 9 -#define GEVENT_10_SCIMAP 10 -#define GEVENT_11_SCIMAP 11 -#define GEVENT_12_SCIMAP 12 -#define GEVENT_13_SCIMAP 13 -#define GEVENT_14_SCIMAP 14 -#define GEVENT_15_SCIMAP 15 -#define GEVENT_16_SCIMAP 16 -#define GEVENT_17_SCIMAP 17 -#define GEVENT_18_SCIMAP 18 -#define GEVENT_19_SCIMAP 19 -#define GEVENT_20_SCIMAP 20 -#define GEVENT_21_SCIMAP 21 -#define GEVENT_22_SCIMAP 22 -#define GEVENT_23_SCIMAP 23 +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23
-#define SMITRIG_LOW 0 -#define SMITRIG_HI 1 +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1
-#define GEVENT_00_SMITRIG SMITRIG_HI -#define GEVENT_01_SMITRIG SMITRIG_HI -#define GEVENT_02_SMITRIG SMITRIG_HI -#define GEVENT_03_SMITRIG SMITRIG_HI -#define GEVENT_04_SMITRIG SMITRIG_HI -#define GEVENT_05_SMITRIG SMITRIG_HI -#define GEVENT_06_SMITRIG SMITRIG_HI -#define GEVENT_07_SMITRIG SMITRIG_HI -#define GEVENT_08_SMITRIG SMITRIG_HI -#define GEVENT_09_SMITRIG SMITRIG_HI -#define GEVENT_10_SMITRIG SMITRIG_HI -#define GEVENT_11_SMITRIG SMITRIG_HI -#define GEVENT_12_SMITRIG SMITRIG_HI -#define GEVENT_13_SMITRIG SMITRIG_HI -#define GEVENT_14_SMITRIG SMITRIG_HI -#define GEVENT_15_SMITRIG SMITRIG_HI -#define GEVENT_16_SMITRIG SMITRIG_HI -#define GEVENT_17_SMITRIG SMITRIG_HI -#define GEVENT_18_SMITRIG SMITRIG_HI -#define GEVENT_19_SMITRIG SMITRIG_HI -#define GEVENT_20_SMITRIG SMITRIG_HI -#define GEVENT_21_SMITRIG SMITRIG_HI -#define GEVENT_22_SMITRIG SMITRIG_HI -#define GEVENT_23_SMITRIG SMITRIG_HI +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI
-#define SMICONTROL_MASK 3 -#define SMICONTROL_DISABLE 0 -#define SMICONTROL_SMI 1 -#define SMICONTROL_NMI 2 -#define SMICONTROL_IRQ13 3 +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3
-#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE -#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE
#define GPIO_RSVD_ZONE0_S GPIO_81 #define GPIO_RSVD_ZONE0_E GPIO_95 @@ -1763,7 +1763,7 @@ #define GPIO_RSVD_ZONE1_E GPIO_127
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ typedef enum _GPIO_COUNT @@ -2273,14 +2273,14 @@ typedef enum _GEVENT_COUNT
typedef struct _GEVENT_SETTINGS { - u8 EventEnable; // 0: Disable, 1: Enable - u8 SciTrig; // 0: Falling Edge, 1: Rising Edge - u8 SciLevl; // 0: Edge trigger, 1: Level Trigger - u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI - u8 SciS0En; // 0: Disable, 1: Enable - u8 SciMap; // 0000b->1111b - u8 SmiTrig; // 0: Active Low, 1: Active High - u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 + u8 EventEnable; // 0: Disable, 1: Enable + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 } GEVENT_SETTINGS;
GEVENT_SETTINGS gevent_table[] = @@ -2312,17 +2312,17 @@ GEVENT_SETTINGS gevent_table[] = };
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index da97d6a..efdad16 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -29,7 +29,7 @@ #include <cpu/amd/amdfam12.h> #include "SbPlatform.h"
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_sb900[6];
@@ -108,12 +108,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 byte; @@ -138,12 +138,12 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
//mptable_add_isa_interrupts(mc, bus_isa, apicid_sb900, 0); - /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb900, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb900, 0x1); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb900, 0x2); @@ -166,7 +166,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -232,7 +232,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 8ecb09c..7817799 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -55,7 +55,7 @@ * @li <b>0</b> - Legacy free disable */ #ifndef SBCIMx_LEGACY_FREE - #define SBCIMx_LEGACY_FREE 0 + #define SBCIMx_LEGACY_FREE 0 #endif
/** @@ -100,7 +100,7 @@ * @li <b>1</b> - Use EC PS/2 function. */ #ifndef INCHIP_EC_KBD - #define INCHIP_EC_KBD 0 + #define INCHIP_EC_KBD 0 #endif
/** @@ -109,7 +109,7 @@ * @li <b>1</b> - EC controller support Channel10. */ #ifndef INCHIP_EC_CHANNEL10 - #define INCHIP_EC_CHANNEL10 1 + #define INCHIP_EC_CHANNEL10 1 #endif
/** @@ -217,7 +217,7 @@ * @li <b>0</b> - Primary * @li <b>1</b> - Secondary<TD></TD> * Sata Controller set as primary or - * secondary while Combined Mode is enabled + * secondary while Combined Mode is enabled */ #ifndef SATA_COMBINE_MODE_CHANNEL #define SATA_COMBINE_MODE_CHANNEL 0 @@ -230,7 +230,7 @@ * SataController Set to Max Gen2 mode */ #ifndef SATA_MAX_GEN2_MODE - #define SATA_MAX_GEN2_MODE 0 + #define SATA_MAX_GEN2_MODE 0 #endif
/** @@ -240,10 +240,10 @@ * Sata IDE Controller set to Combined Mode */ #ifndef SATA_COMBINE_MODE - #define SATA_COMBINE_MODE 0 + #define SATA_COMBINE_MODE 0 #endif
-#define SATA_CLK_RESERVED 9 +#define SATA_CLK_RESERVED 9
/** * @section NbSbGen2 @@ -281,45 +281,45 @@ * @li <b>1</b> - Enable * Spread Spectrum function */ -#define INCHIP_SPREAD_SPECTRUM 1 +#define INCHIP_SPREAD_SPECTRUM 1
/** * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG * * - Usb Ohci1 Contoller is define at BIT0 * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func0) + * (Bus 0 Dev 18 Func0) * - Usb Ehci1 Contoller is define at BIT1 * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func2) + * (Bus 0 Dev 18 Func2) * - Usb Ohci2 Contoller is define at BIT2 * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func0) + * (Bus 0 Dev 19 Func0) * - Usb Ehci2 Contoller is define at BIT3 * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func2) + * (Bus 0 Dev 19 Func2) * - Usb Ohci3 Contoller is define at BIT4 * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func0) + * (Bus 0 Dev 22 Func0) * - Usb Ehci3 Contoller is define at BIT5 * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func2) + * (Bus 0 Dev 22 Func2) * - Usb Ohci4 Contoller is define at BIT6 * 0:Disable 1:Enable - * (Bus 0 Dev 20 Func5) + * (Bus 0 Dev 20 Func5) */ -#define INCHIP_USB_CINFIG 0x7F -#define INCHIP_USB_OHCI1_CINFIG 0x01 -#define INCHIP_USB_OHCI2_CINFIG 0x01 +#define INCHIP_USB_CINFIG 0x7F +#define INCHIP_USB_OHCI1_CINFIG 0x01 +#define INCHIP_USB_OHCI2_CINFIG 0x01 #if CONFIG_ONBOARD_USB30 -#define INCHIP_USB_OHCI3_CINFIG 0x00 +#define INCHIP_USB_OHCI3_CINFIG 0x00 #else -#define INCHIP_USB_OHCI3_CINFIG 0x01 +#define INCHIP_USB_OHCI3_CINFIG 0x01 #endif -#define INCHIP_USB_OHCI4_CINFIG 0x01 -#define INCHIP_USB_EHCI1_CINFIG 0x01 -#define INCHIP_USB_EHCI2_CINFIG 0x01 -#define INCHIP_USB_EHCI3_CINFIG 0x01 +#define INCHIP_USB_OHCI4_CINFIG 0x01 +#define INCHIP_USB_EHCI1_CINFIG 0x01 +#define INCHIP_USB_EHCI2_CINFIG 0x01 +#define INCHIP_USB_EHCI3_CINFIG 0x01
/** * @section INCHIP_SATA_MODE INCHIP_SATA_MODE @@ -331,7 +331,7 @@ * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver) * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver) */ -#define INCHIP_SATA_MODE 0 +#define INCHIP_SATA_MODE 0
/** * @section INCHIP_IDE_MODE INCHIP_IDE_MODE @@ -339,7 +339,7 @@ * @li <b>1</b> - Native IDE mode<TD></TD> * ** DO NOT ALLOW SATA & IDE use same mode ** */ -#define INCHIP_IDE_MODE 1 +#define INCHIP_IDE_MODE 1
#define SATA_PORT_MULT_CAP_RESERVED 1
@@ -381,35 +381,35 @@ * - 01: Reserved * - 10: As a Azalia SDIN pin */ -#define AZALIA_PIN_CONFIG 0x2A +#define AZALIA_PIN_CONFIG 0x2A
/** * @section AzaliaSnoop * @li <b>0</b> - disable * @li <b>1</b> - enable * */ -#define INCHIP_AZALIA_SNOOP 0x01 +#define INCHIP_AZALIA_SNOOP 0x01
/** * @section NCHIP_GEC_CONTROLLER * @li <b>0</b> - Enable * * @li <b>1</b> - Disable */ -#define INCHIP_GEC_CONTROLLER 0x00 +#define INCHIP_GEC_CONTROLLER 0x00
/** * @section SB_HPET_TIMER SB_HPET_TIMER * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_HPET_TIMER 1 +#define SB_HPET_TIMER 1
/** * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_GPP_CONTROLLER 1 +#define SB_GPP_CONTROLLER 1
/** * @section GPP_LINK_CONFIG GPP_LINK_CONFIG @@ -419,35 +419,35 @@ * @li <b>0011</b> - Port ABCD -> 2:1:1:0 * @li <b>0100</b> - Port ABCD -> 1:1:1:1 */ -#define GPP_LINK_CONFIG 4 +#define GPP_LINK_CONFIG 4
/** * @section SB_GPP_PORT0 SB_GPP_PORT0 * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_GPP_PORT0 1 +#define SB_GPP_PORT0 1
/** * @section SB_GPP_PORT1 SB_GPP_PORT1 * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_GPP_PORT1 1 +#define SB_GPP_PORT1 1
/** * @section SB_GPP_PORT2 SB_GPP_PORT2 * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_GPP_PORT2 1 +#define SB_GPP_PORT2 1
/** * @section SB_GPP_PORT3 SB_GPP_PORT3 * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define SB_GPP_PORT3 1 +#define SB_GPP_PORT3 1
/** * @section SB_IR_CONTROLLER @@ -456,7 +456,7 @@ * @li <b>10 </b> - Rx and Tx1 * @li <b>11 </b> - Rx and both Tx0,Tx1 */ -#define SB_IR_CONTROLLER 3 +#define SB_IR_CONTROLLER 3
/** * @section INCHIP_USB_PHY_POWER_DOWN @@ -477,14 +477,14 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define INCHIP_NB_SB_GEN2 1 +#define INCHIP_NB_SB_GEN2 1
/** * @section INCHIP_GPP_GEN2 * @li <b>0</b> - Disable * @li <b>1</b> - Enable */ -#define INCHIP_GPP_GEN2 1 +#define INCHIP_GPP_GEN2 1
/** * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE @@ -498,7 +498,7 @@ * @li <b>0</b> - Gb PHY Mode * * @li <b>1</b> - 100/10 PHY Mode */ -#define INCHIP_GEC_PHY_STATUS 0 +#define INCHIP_GEC_PHY_STATUS 0
/** * @section INCHIP_GEC_POWER_POLICY @@ -507,14 +507,14 @@ * @li <b>2</b> - S3 * @li <b>3</b> - Never power down * */ -#define INCHIP_GEC_POWER_POLICY 3 +#define INCHIP_GEC_POWER_POLICY 3
/** * @section INCHIP_GEC_DEBUGBUS * @li <b>0</b> - Disable * * @li <b>1</b> - Enable */ -#define INCHIP_GEC_DEBUGBUS 0 +#define INCHIP_GEC_DEBUGBUS 0
/** * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE @@ -522,7 +522,7 @@ * @li <b>1</b> - Enable * SataController Set to Max Gen2 mode */ -#define SATA_MAX_GEN2_MODE 0 +#define SATA_MAX_GEN2_MODE 0
/** * @section INCHIP_SATA_AGGR_LINK_PM_CAP @@ -545,14 +545,14 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable * */ -#define INCHIP_SATA_PSC_CAP 0 +#define INCHIP_SATA_PSC_CAP 0
/** * @section INCHIP_SATA_SSC_CAP * @li <b>0</b> - Disable * @li <b>1</b> - Enable * */ -#define INCHIP_SATA_SSC_CAP 0 +#define INCHIP_SATA_SSC_CAP 0
/** * @section INCHIP_SATA_CLK_AUTO_OFF @@ -566,21 +566,21 @@ * @li <b>0</b> - Disable * @li <b>1</b> - Enable * */ -#define INCHIP_SATA_FIS_BASE_SW 1 +#define INCHIP_SATA_FIS_BASE_SW 1
/** * @section INCHIP_SATA_CCC_SUPPORT * @li <b>0</b> - Disable * @li <b>1</b> - Enable * */ -#define INCHIP_SATA_CCC_SUPPORT 1 +#define INCHIP_SATA_CCC_SUPPORT 1
/** * @section INCHIP_SATA_MSI_CAP * @li <b>0</b> - Disable * @li <b>1</b> - Enable * */ -#define INCHIP_SATA_MSI_CAP 1 +#define INCHIP_SATA_MSI_CAP 1
/** * @section CIMXSB_SATA_TARGET_8DEVICE_CAP @@ -608,7 +608,7 @@ * @li <b>0</b> - Disable * * @li <b>1</b> - Enable */ -#define INCHIP_SATA_FORCE_RAID5 0 +#define INCHIP_SATA_FORCE_RAID5 0
/** * @section SATA_GPIO_0_CAP @@ -1031,10 +1031,10 @@
/** * @section GppPortAspm - * @li <b>01</b> - Disabled - * @li <b>01</b> - L0s - * @li <b>10</b> - L1 - * @li <b>11</b> - L0s + L1 + * @li <b>01</b> - Disabled + * @li <b>01</b> - L0s + * @li <b>10</b> - L1 + * @li <b>11</b> - L0s + L1 */ #define INCHIP_GPP_PORT_ASPM 3
@@ -1215,7 +1215,7 @@ #define INCHIP_STRESS_RESET_MODE 0
#ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F + #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F #endif
/** diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 2aca184..c387cc9 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -97,14 +97,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -147,7 +147,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (CurrNodeOffset != 0) { CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; + return AGESA_BOUNDS_CHK; } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points @@ -163,18 +163,18 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (FreedNodeOffset != 0) { FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } } PrevNodeOffset = FreedNodeOffset; FreedNodeOffset = FreedNodePtr->NextNodeOffset; @@ -191,23 +191,23 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* If BestFitNode is larger than the requested buffer, fragment the node further */ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
- NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; }
/* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; }
/* Add BestFitNode to the list of Allocated nodes */ @@ -227,12 +227,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -289,8 +289,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -305,7 +305,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -345,8 +345,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -379,7 +379,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; @@ -387,9 +387,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -445,14 +445,14 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; @@ -460,10 +460,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; @@ -540,12 +540,12 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; + UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr; UINT32 AcpiMmioAddr; - UINT8 Data8; + UINT8 Data8; UINT16 Data16;
FcnData = Data; @@ -566,51 +566,51 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 + Status = AGESA_SUCCESS; + break; } break; case 6: switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 + Status = AGESA_SUCCESS; + break; } break; case 7: switch (ResetInfo->ResetControl) { case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 &= ~(UINT8)BIT6 ; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); + Data8 |= BIT6 ; + Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 + Status = AGESA_SUCCESS; + break; } break; } diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h index be14425..260731a 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.h +++ b/src/mainboard/amd/union_station/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; @@ -68,12 +68,12 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ b/src/mainboard/amd/union_station/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 829b6c9..57237e3 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -47,70 +47,70 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) - }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) - }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } };
PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeHDMI, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeHDMI, Aux2, Hdp2} - } + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeHDMI, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeHDMI, Aux2, Hdp2} + } };
PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
// GNB PCIe topology Porting @@ -132,25 +132,25 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + 0, + sizeof(Brazos), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 5efcd7d..e81bc3e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -25,44 +25,44 @@ #include "amdlib.h"
//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/amd/union_station/acpi/ide.asl b/src/mainboard/amd/union_station/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/amd/union_station/acpi/ide.asl +++ b/src/mainboard/amd/union_station/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index 635b632..ba4ae93 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -453,9 +453,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h index b02fd5e..442f46f 100644 --- a/src/mainboard/amd/union_station/agesawrapper.h +++ b/src/mainboard/amd/union_station/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,26 +30,26 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 87f9b88..c74238a 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -61,10 +61,10 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE @@ -77,146 +77,146 @@ #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
/* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
/* @@ -271,54 +271,54 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
/* QUANDRANK_TYPE*/ -#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM -#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
/* USER_MEMORY_TIMING_MODE */ -#define TIMING_MODE_AUTO 0 ///< Use best rate possible -#define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
/* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data. #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -333,57 +333,57 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), @@ -410,8 +410,8 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -437,7 +437,7 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
@@ -447,7 +447,7 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 2289126..e2422f3 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -17,45 +17,45 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge
- chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 @@ -68,21 +68,21 @@ chip northbridge/amd/agesa/family14/root_complex register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 +# end # device pci 18.0 # These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end
- register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }"
- end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index f7c7bb2..a254adf 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index df8ce6e..0a375c1 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -125,7 +125,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index e9175d8..3a2ccf5 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 byte; @@ -74,7 +74,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -85,7 +85,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index a8888d2..46a38e3 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/aopen/Kconfig b/src/mainboard/aopen/Kconfig index b0fc66b..f48a9a7 100644 --- a/src/mainboard/aopen/Kconfig +++ b/src/mainboard/aopen/Kconfig @@ -1,7 +1,7 @@ if VENDOR_AOPEN
choice - prompt "Mainboard model" + prompt "Mainboard model"
config BOARD_AOPEN_DXPLPLUSU bool "DXPL Plus-U" diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl index a0a76e6..742bd08 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl @@ -25,7 +25,7 @@ Device (USB0) OperationRegion (USBS, PCI_Config, 0x00, 0x0100) Field (USBS, ByteAcc, NoLock, Preserve) { - Offset (0xC4), URES, 8 + Offset (0xC4), URES, 8 } }
@@ -36,7 +36,7 @@ Device (USB1) OperationRegion (USBS, PCI_Config, 0x00, 0x0100) Field (USBS, ByteAcc, NoLock, Preserve) { - Offset (0xC4), URES, 8 + Offset (0xC4), URES, 8 } }
@@ -47,7 +47,7 @@ Device (USB2) OperationRegion (USBS, PCI_Config, 0x00, 0x0100) Field (USBS, ByteAcc, NoLock, Preserve) { - Offset (0xC4), URES, 8 + Offset (0xC4), URES, 8 } }
@@ -58,14 +58,14 @@ Device (USB3) OperationRegion (USBS, PCI_Config, 0x00, 0x0100) Field (USBS, ByteAcc, NoLock, Preserve) { - Offset (0xC4), URES, 8 + Offset (0xC4), URES, 8 } }
Device(PCI5) { Name (_ADR, 0x001E0000) - Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ Name (_PRT, Package() { Package() { 0x0003ffff, 0, 0, 20 }, Package() { 0x0003ffff, 1, 0, 21 }, @@ -87,9 +87,9 @@ Device (ICH0) OperationRegion (ACPI, SystemIO, 0x0400, 0xC0) Field (ACPI, ByteAcc, NoLock, Preserve) { - Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, - Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, - Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, + Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8, + Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8, + Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8, Offset (0xB8), GPLV,8 }
@@ -150,9 +150,9 @@ Device (ICH0) Name (MSBG, ResourceTemplate () { Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,) Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,) - }) + })
- Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, NotSerialized) { Return (MSBG) } diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl index b20bc78..12854fb 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl @@ -42,11 +42,11 @@ Device(P64B) Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */ })
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) Field (PBPC, ByteAcc, NoLock, Preserve) { - Offset (0x3E), BCRL, 8, BCRH, 8 + Offset (0x3E), BCRL, 8, BCRH, 8 }
@@ -84,11 +84,11 @@ Device(P64A) Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */ })
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ + Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */ OperationRegion (PBPC, PCI_Config, 0x00, 0xFF) Field (PBPC, ByteAcc, NoLock, Preserve) { - Offset (0x3E), BCRL, 8, BCRH, 8 + Offset (0x3E), BCRL, 8, BCRH, 8 }
#include "acpi/scsi.asl" diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl index 3c3b609..82e97cd 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -27,9 +27,9 @@ Device (SCS0) OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) Field (SCSC, ByteAcc, NoLock, Preserve) { - Offset (0x2C), SID, 32, - Offset (0xE0), PMC, 8, - Offset (0xFF), IDW, 8 + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 } }
@@ -39,9 +39,9 @@ Device (SCS1) OperationRegion (SCSC, PCI_Config, 0x00, 0x0100) Field (SCSC, ByteAcc, NoLock, Preserve) { - Offset (0x2C), SID, 32, - Offset (0xE0), PMC, 8, - Offset (0xFF), IDW, 8 + Offset (0x2C), SID, 32, + Offset (0xE0), PMC, 8, + Offset (0xFF), IDW, 8 } }
diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl index 693b58e..adae577 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/superio.asl @@ -28,7 +28,7 @@ Name (MSBF, ResourceTemplate () OperationRegion (LPC0, SystemIO, 0x0E00, 0x60) Field (LPC0, ByteAcc, NoLock, Preserve) { - PME0, 8, + PME0, 8, Offset (0x02), PME2,8, Offset (0x04), PME4,8, Offset (0x0A), PMEA,8, @@ -51,26 +51,26 @@ Field (LPC0, ByteAcc, NoLock, Preserve) OperationRegion (SMC1, SystemIO, 0x2E, 0x02) Field (SMC1, ByteAcc, NoLock, Preserve) { - INDX, 8, DATA, 8 + INDX, 8, DATA, 8 }
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) { - Offset (0x07), LDN, 8, - Offset (0x22), PWRC, 8, - Offset (0x30), ACTR, 8, + Offset (0x07), LDN, 8, + Offset (0x22), PWRC, 8, + Offset (0x30), ACTR, 8, Offset (0x60), - IOAH, 8, IOAL, 8, - IOBH, 8, IOBL, 8, - - Offset (0x70), INTR, 8, - Offset (0x72), INT1, 8, - Offset (0x74), DMCH, 8, - Offset (0xB2), SPS1, 8, SPS2, 8, - Offset (0xB8), D2TS, 8, - Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8, - Offset (0xF4), WDTC, 8, - Offset (0xF6), GP01, 8, GP02, 8, GP04, 8 + IOAH, 8, IOAL, 8, + IOBH, 8, IOBL, 8, + + Offset (0x70), INTR, 8, + Offset (0x72), INT1, 8, + Offset (0x74), DMCH, 8, + Offset (0xB2), SPS1, 8, SPS2, 8, + Offset (0xB8), D2TS, 8, + Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8, + Offset (0xF4), WDTC, 8, + Offset (0xF6), GP01, 8, GP02, 8, GP04, 8 }
Method (ECFG, 0, NotSerialized) diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 9707b9d..7a993c4 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -26,12 +26,12 @@ * code and the mainboard fadt. */ #define APM_CNT 0x0 /* ACPI mode only */ -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x0 -#define ACPI_DISABLE 0xAA -#define ACPI_ENABLE 0x55 -#define S4_BIOS 0x77 -#define GNVS_UPDATE 0xea +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x0 +#define ACPI_DISABLE 0xAA +#define ACPI_ENABLE 0x55 +#define S4_BIOS 0x77 +#define GNVS_UPDATE 0xea
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c index a59d7e8..115bbcc 100644 --- a/src/mainboard/aopen/dxplplusu/irq_tables.c +++ b/src/mainboard/aopen/dxplplusu/irq_tables.c @@ -43,7 +43,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PCI_DEVICE_ID_INTEL_82801DB_LPC, // Device ID of compatible PCI interrupt router 0, // Additional miniport information { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero - 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) + 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) { // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space // This was determined from linux-2.6.11/arch/i386/pci/irq.c @@ -51,19 +51,19 @@ static const struct irq_routing_table intel_irq_routing_table = { // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
- // INTA# INTB# INTC# INTD# + // INTA# INTB# INTC# INTD# // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
- {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus - {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1 + {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus + {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // USB 1.1
- {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE + {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // GbE
- {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, - {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI + {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, + {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, // SCSI
{PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, // 32-bit slot
diff --git a/src/mainboard/arima/hdama/cmos.layout b/src/mainboard/arima/hdama/cmos.layout index d8e2eee..57af6d5 100644 --- a/src/mainboard/arima/hdama/cmos.layout +++ b/src/mainboard/arima/hdama/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/arima/hdama/irq_tables.c b/src/mainboard/arima/hdama/irq_tables.c index 9250d1f..0cf483b 100644 --- a/src/mainboard/arima/hdama/irq_tables.c +++ b/src/mainboard/arima/hdama/irq_tables.c @@ -17,7 +17,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ @@ -26,7 +26,7 @@ static const struct irq_routing_table intel_irq_routing_table = { IRQ_ROUTER_DEVICE, /* Device */ 0x00, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb0, /* u8 checksum , mod 256 checksum must give zero */ + 0xb0, /* u8 checksum , mod 256 checksum must give zero */ { /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */ /* PCI Slot 1-6 */ IRQ_SLOT(1, 3,1,0, 2,3,4,1 ), @@ -44,5 +44,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index f67327e..37dc843 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -152,7 +152,7 @@ static void *smp_write_config_table(void *v) /* Standard local interrupt assignments */ mptable_lintsrc(mc, bus_isa);
- /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ + /* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ /* On board nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13); diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 4df8416..0e840a6 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -104,8 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
allow_all_aps_stop(bsp_apicid); diff --git a/src/mainboard/artecgroup/dbe61/cmos.layout b/src/mainboard/artecgroup/dbe61/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/artecgroup/dbe61/cmos.layout +++ b/src/mainboard/artecgroup/dbe61/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/artecgroup/dbe61/irq_tables.c b/src/mainboard/artecgroup/dbe61/irq_tables.c index 0f21913..38ec0e2 100644 --- a/src/mainboard/artecgroup/dbe61/irq_tables.c +++ b/src/mainboard/artecgroup/dbe61/irq_tables.c @@ -43,7 +43,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -52,10 +52,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x002B, /* Device */ 0, /* Miniport data */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x0D << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c index 692d2ab..58dd9f5 100644 --- a/src/mainboard/artecgroup/dbe61/mainboard.c +++ b/src/mainboard/artecgroup/dbe61/mainboard.c @@ -48,9 +48,9 @@ static void init(struct device *dev)
static void mainboard_enable(struct device *dev) { - dev->ops->init = init; + dev->ops->init = init; }
struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/artecgroup/dbe61/spd_table.h b/src/mainboard/artecgroup/dbe61/spd_table.h index 3d45b6f..e30a7c4 100644 --- a/src/mainboard/artecgroup/dbe61/spd_table.h +++ b/src/mainboard/artecgroup/dbe61/spd_table.h @@ -29,25 +29,25 @@ struct spd_entry { /* 128MB */ const struct spd_entry spd_table [] = { -{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ -{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ -{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ -{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ -{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ -{SPD_REFRESH, 0x82}, /* Refresh rate/type */ -{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */ -{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */ -{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */ -{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */ -{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */ -{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */ -{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */ -{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */ +{SPD_MEMORY_TYPE, 0x07}, /* (Fundamental) memory type */ +{SPD_NUM_ROWS, 0x0D}, /* Number of row address bits */ +{SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ +{SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ +{SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x50}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ +{SPD_REFRESH, 0x82}, /* Refresh rate/type */ +{SPD_PRIMARY_SDRAM_WIDTH, 0x08}, /* SDRAM width (primary SDRAM) */ +{SPD_NUM_BANKS_PER_SDRAM, 0x04}, /* SDRAM device attributes, number of banks on SDRAM device */ +{SPD_ACCEPTABLE_CAS_LATENCIES, 0x1C}, /* SDRAM device attributes, CAS latency */ +{SPD_MODULE_ATTRIBUTES, 0x20}, /* SDRAM module attributes */ +{SPD_DEVICE_ATTRIBUTES_GENERAL, 0xC0}, /* SDRAM device attributes, general */ +{SPD_SDRAM_CYCLE_TIME_2ND, 0x60}, /* SDRAM cycle time (2nd highest CAS latency) */ +{SPD_SDRAM_CYCLE_TIME_3RD, 0x75}, /* SDRAM cycle time (3rd highest CAS latency) */ +{SPD_MIN_ROW_PRECHARGE_TIME, 0x3C}, /* Minimum row precharge time (Trp) */ {SPD_MIN_ROWACTIVE_TO_ROWACTIVE, 0x28}, /* Minimum row active to row active (Trrd) */ -{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */ +{SPD_MIN_RAS_TO_CAS_DELAY, 0x3C}, /* Minimum RAS to CAS delay (Trcd) */ {SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY, 0x28}, /* Minimum RAS pulse width (Tras) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ {SPD_CMD_SIGNAL_INPUT_HOLD_TIME, 0x60}, /* Command and address signal input hold time */ -{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ -{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ +{SPD_tRC, 0x37}, /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +{SPD_tRFC, 0x46} /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ }; diff --git a/src/mainboard/asi/mb_5blgp/devicetree.cb b/src/mainboard/asi/mb_5blgp/devicetree.cb index d84bf0e..c40d855 100644 --- a/src/mainboard/asi/mb_5blgp/devicetree.cb +++ b/src/mainboard/asi/mb_5blgp/devicetree.cb @@ -4,42 +4,42 @@ chip northbridge/amd/gx1 # Northbridge chip southbridge/amd/cs5530 # Southbridge device pci 0f.0 on end # Ethernet device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # System wake-up control (SWC) - irq 0x60 = 0x500 - end - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 on # GPIO - irq 0x60 = 0x800 - end - device pnp 2e.8 on # Fan speed control - irq 0x60 = 0x900 - end - end + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # System wake-up control (SWC) + irq 0x60 = 0x500 + end + device pnp 2e.5 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 on # GPIO + irq 0x60 = 0x800 + end + device pnp 2e.8 on # Fan speed control + irq 0x60 = 0x900 + end + end end device pci 12.1 off end # SMI device pci 12.2 on end # IDE diff --git a/src/mainboard/asi/mb_5blgp/irq_tables.c b/src/mainboard/asi/mb_5blgp/irq_tables.c index b37e8f9..c825a17 100644 --- a/src/mainboard/asi/mb_5blgp/irq_tables.c +++ b/src/mainboard/asi/mb_5blgp/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x96, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */ {0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */ {0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */ diff --git a/src/mainboard/asi/mb_5blmp/devicetree.cb b/src/mainboard/asi/mb_5blmp/devicetree.cb index e8e6ac3..bf38743 100644 --- a/src/mainboard/asi/mb_5blmp/devicetree.cb +++ b/src/mainboard/asi/mb_5blmp/devicetree.cb @@ -4,34 +4,34 @@ chip northbridge/amd/gx1 # Northbridge chip southbridge/amd/cs5530 # Southbridge device pci 0f.0 off end # Ethernet (Realtek RTL8139B) device pci 12.0 on # ISA bridge - chip superio/nsc/pc87351 # Super I/O - device pnp 2e.4 on # PS/2 keyboard (+ mouse?) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - # irq 0x72 = 12 - end - device pnp 2e.a on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.e on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.f off # Floppy - io 0x60 = 0x3f2 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.10 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.12 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end + chip superio/nsc/pc87351 # Super I/O + device pnp 2e.4 on # PS/2 keyboard (+ mouse?) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + # irq 0x72 = 12 + end + device pnp 2e.a on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.e on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.f off # Floppy + io 0x60 = 0x3f2 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.10 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.12 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end end device pci 12.1 off end # SMI device pci 12.2 on end # IDE diff --git a/src/mainboard/asi/mb_5blmp/irq_tables.c b/src/mainboard/asi/mb_5blmp/irq_tables.c index 01d364d..e1bbf92 100644 --- a/src/mainboard/asi/mb_5blmp/irq_tables.c +++ b/src/mainboard/asi/mb_5blmp/irq_tables.c @@ -9,18 +9,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0xe00, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x0002, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ // USB {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, // eth0 @@ -35,5 +35,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c index a0b74d0..590dfcb 100644 --- a/src/mainboard/asrock/939a785gmh/acpi_tables.c +++ b/src/mainboard/asrock/939a785gmh/acpi_tables.c @@ -79,7 +79,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asrock/939a785gmh/cmos.layout b/src/mainboard/asrock/939a785gmh/cmos.layout index 37530b7..94ba135 100644 --- a/src/mainboard/asrock/939a785gmh/cmos.layout +++ b/src/mainboard/asrock/939a785gmh/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb index f246dcf..bc8c1f5 100644 --- a/src/mainboard/asrock/939a785gmh/devicetree.cb +++ b/src/mainboard/asrock/939a785gmh/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/amd/amdk8/root_complex device pci 9.0 on end # GPP for x1 slot device pci a.0 on end # GPP for internal network adapter register "gppsb_configuration" = "4" # Configuration ? - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x60c" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl index 9bd9bb1..f3e30d3 100644 --- a/src/mainboard/asrock/939a785gmh/dsdt.asl +++ b/src/mainboard/asrock/939a785gmh/dsdt.asl @@ -428,7 +428,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -478,7 +478,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -500,8 +500,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -510,8 +510,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -520,8 +520,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -630,17 +630,17 @@ DefinitionBlock ( Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index f05ce7f..6c2c6bd 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 58ad8b2..9265893 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -57,7 +57,7 @@ void set_pcie_reset() pcie_rst_toggle(0x0); }
-#if 0 /* not tested yet */ +#if 0 /* not tested yet */ /******************************************************** * mahogany uses SB700 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 8e663ec..2d8b072 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -153,7 +153,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index a6a82f9..46d1cbd 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -95,14 +95,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -145,7 +145,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (CurrNodeOffset != 0) { CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { - return AGESA_BOUNDS_CHK; + return AGESA_BOUNDS_CHK; } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points @@ -161,18 +161,18 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (FreedNodeOffset != 0) { FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - if (BestFitNodeOffset == 0) { - /* First node that fits the requested buffer size */ - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } else { - /* Find out whether current node is a better fit than the previous nodes */ - BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); - if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { - BestFitNodeOffset = FreedNodeOffset; - BestFitPrevNodeOffset = PrevNodeOffset; - } - } + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } } PrevNodeOffset = FreedNodeOffset; FreedNodeOffset = FreedNodePtr->NextNodeOffset; @@ -189,23 +189,23 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
/* If BestFitNode is larger than the requested buffer, fragment the node further */ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { - NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
- NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); - NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); - NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; } else { - /* Otherwise, next free node is NextNodeOffset of BestFitNode */ - NextFreeOffset = BestFitNodePtr->NextNodeOffset; + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; }
/* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { - BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; } else { - BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; }
/* Add BestFitNode to the list of Allocated nodes */ @@ -225,12 +225,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -287,8 +287,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
} else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -303,7 +303,7 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -343,8 +343,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -377,7 +377,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; @@ -385,9 +385,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -443,14 +443,14 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; + AGESA_STATUS Status; + UINTN FcnData; MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; @@ -458,10 +458,10 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = AGESA_SUCCESS; /* Get SB800 MMIO Base (AcpiMmioAddr) */ WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 = Data8<<8; WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); + Data8 = ReadIo8(0xCD7); Data16 |= Data8; AcpiMmioAddr = (UINT32)Data16 << 16; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h index ac40410..07dd635 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.h +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h"
#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */
typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 026deeb..bb36348 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -20,83 +20,83 @@ if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select ARCH_X86 select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_WINBOND_W83627HF select SB_SUPERIO_HWM - select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select LIFT_BSP_APIC_ID + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT select AMDMCT - select HAVE_ACPI_TABLES + select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select GFXUMA
config MAINBOARD_DIR - string - default asrock/e350m1 + string + default asrock/e350m1
config APIC_ID_OFFSET - hex - default 0x0 + hex + default 0x0
config MAINBOARD_PART_NUMBER - string - default "E350M1" + string + default "E350M1"
config HW_MEM_HOLE_SIZEK - hex - default 0x200000 + hex + default 0x200000
config MAX_CPUS - int - default 2 + int + default 2
config MAX_PHYSICAL_CPUS - int - default 1 + int + default 1
config HW_MEM_HOLE_SIZE_AUTO_INC - bool - default n + bool + default n
config MEM_TRAIN_SEQ - int - default 2 + int + default 2
config IRQ_SLOT_COUNT - int - default 11 + int + default 11
config RAMTOP - hex - default 0x1000000 + hex + default 0x1000000
config HEAP_SIZE - hex - default 0xc0000 + hex + default 0xc0000
config RAMBASE - hex - default 0x200000 + hex + default 0x200000
config SIO_PORT - hex - default 0x2e + hex + default 0x2e
config ONBOARD_VGA_IS_PRIMARY bool default y
config VGA_BIOS_ID - string - default "1002,9802" + string + default "1002,9802"
config DRIVERS_PS2_KEYBOARD bool diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h index 600753c..806208d 100644 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ b/src/mainboard/asrock/e350m1/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -53,14 +53,14 @@ #define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index 50a8db9..222aefa 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -47,70 +47,70 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + VOID *BrazosPcieComplexListPtr; + VOID *BrazosPciePortPtr; + VOID *BrazosPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) - }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) + }, #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) - }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + }, #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + } };
PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } + // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + {ConnectorTypeDP, Aux1, Hdp1} + }, + // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + {ConnectorTypeDP, Aux2, Hdp2} + } };
PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
// GNB PCIe topology Porting @@ -132,25 +132,25 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + 0, + sizeof(Brazos), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); LibAmdMemCopy (BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..e81bc3e 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -25,44 +25,44 @@ #include "amdlib.h"
//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly ( diff --git a/src/mainboard/asrock/e350m1/acpi/ide.asl b/src/mainboard/asrock/e350m1/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/asrock/e350m1/acpi/ide.asl +++ b/src/mainboard/asrock/e350m1/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl index ebf7ddb..8dbaabb 100644 --- a/src/mainboard/asrock/e350m1/acpi/smbus.asl +++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl @@ -21,18 +21,18 @@ Mutex (SBX0, 0x00) OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) Field (SMB0, ByteAcc, NoLock, Preserve) { - HSTS, 8, /* SMBUS status */ - SSTS, 8, /* SMBUS slave status */ - HCNT, 8, /* SMBUS control */ - HCMD, 8, /* SMBUS host cmd */ - HADD, 8, /* SMBUS address */ - DAT0, 8, /* SMBUS data0 */ - DAT1, 8, /* SMBUS data1 */ - BLKD, 8, /* SMBUS block data */ - SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shadow cmd */ - SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shadow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ }
Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 151abb1..2a10934 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -453,9 +453,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h index dee4224..e0d389a 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ b/src/mainboard/asrock/e350m1/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,29 +31,29 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -63,17 +63,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 19ba4f3..ab03c95 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -63,10 +63,10 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE @@ -79,51 +79,51 @@ #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
-#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE - #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE - #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT TRUE -#define BLDOPT_REMOVE_SLIT TRUE -#define BLDOPT_REMOVE_WHEA TRUE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE + #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE + #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
/* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
/* * Agesa configuration values selection. @@ -148,100 +148,100 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = { CPU_LIST_TERMINAL } };
-#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -//#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +//#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
/* Include the files that instantiate the configuration definitions. */ @@ -271,12 +271,12 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = * version string as appropriate for the release. The trunk copy of this file * should also be updated/incremented for the next expected version, + trailing 'X' ****************************************************************************/ - // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ @@ -306,19 +306,19 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data. #include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -333,57 +333,57 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), @@ -410,8 +410,8 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -437,7 +437,7 @@ CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
@@ -447,7 +447,7 @@ CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABL */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index c908421..4c59269 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -17,43 +17,43 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge
- chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -114,17 +114,17 @@ chip northbridge/amd/agesa/family14/root_complex
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - #device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end
register "spdAddrLookup" = " { @@ -132,7 +132,7 @@ chip northbridge/amd/agesa/family14/root_complex { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }"
- end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end #domain end #northbridge/amd/agesa/family14/root_complex
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index df8ce6e..0a375c1 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -125,7 +125,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 95df2a6..9ace29d 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
u32 dword; u8 byte; @@ -74,7 +74,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -85,7 +85,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 24a66dd..065f5e4 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index dc41579..029424f 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -29,17 +29,17 @@
STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer }, - {AGESA_DO_RESET, fam16kb_Reset }, - {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer }, - {AGESA_READ_SPD, fam16kb_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData }, + {AGESA_ALLOCATE_BUFFER, fam16kb_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam16kb_DeallocateBuffer }, + {AGESA_DO_RESET, fam16kb_Reset }, + {AGESA_LOCATE_BUFFER, fam16kb_LocateBuffer }, + {AGESA_READ_SPD, fam16kb_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam16kb_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam16kb_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam16kb_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam16kb_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam16kb_HookBeforeExitSelfRefresh }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam16kb_HookGfxGetVbiosImage } };
@@ -68,7 +68,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) */ static const CODEC_ENTRY Alc662_VerbTbl[] = { - { 0x14, /*01014010*/ /* Port D - green headphone jack */ + { 0x14, /*01014010*/ /* Port D - green headphone jack */ (AZALIA_PINCFG_PORT_JACK << 30) | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) | (AZALIA_PINCFG_DEVICE_LINEOUT << 20) @@ -77,7 +77,7 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (1 << 4) | (0 << 0) }, - { 0x15, /*0x90170120*/ /* Port A - white speaker header */ + { 0x15, /*0x90170120*/ /* Port A - white speaker header */ (AZALIA_PINCFG_PORT_FIXED << 30) | (AZALIA_PINCFG_LOCATION_INTERNAL << 24) | (AZALIA_PINCFG_DEVICE_SPEAKER << 20) @@ -87,8 +87,8 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (2 << 4) | (0 << 0) }, - { 0x16, 0x411111F0 }, /* Port G - not connected */ - { 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */ + { 0x16, 0x411111F0 }, /* Port G - not connected */ + { 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */ (AZALIA_PINCFG_PORT_JACK << 30) | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) @@ -97,7 +97,7 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (4 << 4) | (0 << 0) }, - { 0x19, /*0x02A19050*/ /* Port F - front panel header mic */ + { 0x19, /*0x02A19050*/ /* Port F - front panel header mic */ (AZALIA_PINCFG_PORT_NC << 30) | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) @@ -106,7 +106,7 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (5 << 4) | (0 << 0) }, - { 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */ + { 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */ (AZALIA_PINCFG_PORT_NC << 30) | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) | (AZALIA_PINCFG_DEVICE_LINEIN << 20) @@ -115,7 +115,7 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (4 << 4) | (0xF << 0) }, - { 0x1B, /*0x02214030*/ /* Port E - front panel line-out */ + { 0x1B, /*0x02214030*/ /* Port E - front panel line-out */ (AZALIA_PINCFG_PORT_NC << 30) | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) @@ -124,9 +124,9 @@ static const CODEC_ENTRY Alc662_VerbTbl[] = | (3 << 4) | (0 << 0) }, - { 0x1C, 0x411111F0 }, /* CD-in - Not Connected */ - { 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */ - { 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */ + { 0x1C, 0x411111F0 }, /* CD-in - Not Connected */ + { 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */ + { 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */ { 0xFF, 0xFFFFFFFF }, };
diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h index 0a1d328..4435371 100644 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ b/src/mainboard/asrock/imb-a180/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -54,14 +54,14 @@ //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index 24d8381..41e00ab 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -100,7 +100,7 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { };
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { - .Flags = DESCRIPTOR_TERMINATE_LIST, + .Flags = DESCRIPTOR_TERMINATE_LIST, .SocketId = 0, .PciePortList = PortList, .DdiLinkList = DdiList @@ -118,7 +118,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -127,7 +127,7 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; + AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams; diff --git a/src/mainboard/asrock/imb-a180/acpi/ide.asl b/src/mainboard/asrock/imb-a180/acpi/ide.asl index 853dc13..820e4cd 100644 --- a/src/mainboard/asrock/imb-a180/acpi/ide.asl +++ b/src/mainboard/asrock/imb-a180/acpi/ide.asl @@ -32,21 +32,21 @@ Scope (_SB) { */
/* Some timing tables */ -Name(UDTT, Package(){ /* Udma timing table */ - 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ })
-Name(MDTT, Package(){ /* MWDma timing table */ - 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ })
-Name(POTT, Package(){ /* Pio timing table */ - 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ })
/* Some timing register value tables */ -Name(MDRT, Package(){ /* MWDma timing register table */ - 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ })
Name(PORT, Package(){ @@ -56,21 +56,21 @@ Name(PORT, Package(){ OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ Field(ICRG, AnyAcc, NoLock, Preserve) { - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ - PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ - PDSM, 4, /* Primary UltraDMA Mode */ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ }
-Method(GTTM, 1) /* get total time*/ +Method(GTTM, 1) /* get total time*/ { - Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ Increment(Local0) Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ Increment(Local1) @@ -82,7 +82,7 @@ Device(PRID) Name (_ADR, Zero) Method(_GTM, 0) { - NAME(OTBF, Buffer(20) { /* out buffer */ + NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -96,7 +96,7 @@ Device(PRID) CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
/* Just return if the channel is disabled */ - If(And(PPCR, 0x01)) { /* primary PIO control */ + If(And(PPCR, 0x01)) { /* primary PIO control */ Return(OTBF) }
@@ -108,7 +108,7 @@ Device(PRID) /* save total time of primary PIO slave Timing to PIO spd1 */ Store(GTTM(PPTS), PSD1)
- If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ Or(BFFG, 0x01, BFFG) Store(DerefOf(Index(UDTT, PDMM)), DSD0) } @@ -116,7 +116,7 @@ Device(PRID) Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ }
- If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ Or(BFFG, 0x04, BFFG) Store(DerefOf(Index(UDTT, PDSM)), DSD1) } @@ -124,12 +124,12 @@ Device(PRID) Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ }
- Return(OTBF) /* out buffer */ - } /* End Method(_GTM) */ + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */
Method(_STM, 3, NotSerialized) { - NAME(INBF, Buffer(20) { /* in buffer */ + NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, @@ -143,14 +143,14 @@ Device(PRID) CreateDwordField(INBF, 16, BFFG) /*buffer flag */
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) - Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) - Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
- If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) Divide(Local0, 7, PDMM,) Or(PDCR, 0x01, PDCR) @@ -162,7 +162,7 @@ Device(PRID) } }
- If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) Divide(Local0, 7, PDSM,) Or(PDCR, 0x02, PDCR) @@ -201,15 +201,15 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } } Return(CMBF) } - } /* End Device(MST) */ + } /* End Device(MST) */
Device(SLAV) { @@ -237,14 +237,14 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } } Return(CMBF) } - } /* End Device(SLAV) */ + } /* End Device(SLAV) */ } #endif diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index b5ae758..999f52b 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -64,11 +64,11 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
/* TODO: Remove the hardcode */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, - 0xFEC20000, 24); + 0xFEC20000, 24);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 8300e34..40f30ed 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -52,38 +52,38 @@ VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 @@ -91,11 +91,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -140,11 +140,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -225,9 +225,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,16 +270,16 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -315,12 +315,12 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -380,9 +380,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -411,9 +411,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -443,11 +443,11 @@ agesawrapper_amdinitlate ( AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */ return (UINT32)Status; @@ -464,9 +464,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -491,12 +491,12 @@ UINT32 agesawrapper_amdinitresume(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -528,7 +528,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -550,16 +550,16 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) UINT32 agesawrapper_amds3laterestore (VOID) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -594,7 +594,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; UINT8 byte;
@@ -631,12 +631,12 @@ UINT32 agesawrapper_amdS3Save(VOID) AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -658,8 +658,8 @@ UINT32 agesawrapper_amdS3Save(VOID)
S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info ( S3DataType, @@ -667,8 +667,8 @@ UINT32 agesawrapper_amdS3Save(VOID) AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; @@ -697,9 +697,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.h b/src/mainboard/asrock/imb-a180/agesawrapper.h index db893cd..20f0a05 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.h +++ b/src/mainboard/asrock/imb-a180/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,27 +30,27 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 7c57183..0ae076f 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -38,7 +38,7 @@ #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
-#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FT3_SOCKET_SUPPORT TRUE #define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT FALSE @@ -57,34 +57,34 @@ #ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE #undef INSTALL_FT3_SOCKET_SUPPORT - #define INSTALL_FT3_SOCKET_SUPPORT FALSE + #define INSTALL_FT3_SOCKET_SUPPORT FALSE #endif #endif
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_CDIT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_CDIT TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent, // as reported by the ACPI _PSD object. For single-link processors, @@ -96,74 +96,74 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 15000 -#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 -#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 -#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_SLEW_RATE 10000 -#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE - -#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_VRM_CURRENT_LIMIT 15000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000 +#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000 +#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_SLEW_RATE 10000 +#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE + +#define BLDCFG_PLAT_NUM_IO_APICS 3 #define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the - // core for C-state entry requests. A value - // of 0 in this field specifies that the core - // does not trap any IO addresses for C-state entry. - // Values greater than 0xFFF8 results in undefined behavior. -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled -#define BLDCFG_IOMMU_SUPPORT FALSE -#define OPTION_GFX_INIT_SVIEW FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife - -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL -#define BLDCFG_CFG_ABM_SUPPORT TRUE - -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the + // core for C-state entry requests. A value + // of 0 in this field specifies that the core + // does not trap any IO addresses for C-state entry. + // Values greater than 0xFFF8 results in undefined behavior. +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled +#define BLDCFG_IOMMU_SUPPORT FALSE +#define OPTION_GFX_INIT_SVIEW FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife + +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL +#define BLDCFG_CFG_ABM_SUPPORT TRUE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
@@ -172,64 +172,64 @@ #define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20) #endif
-#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
/* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = { @@ -265,12 +265,12 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ @@ -306,66 +306,66 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA4 -#define DFLT_FCH_GPP_PORT0_PRESENT FALSE -#define DFLT_FCH_GPP_PORT1_PRESENT FALSE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA4 +#define DFLT_FCH_GPP_PORT0_PRESENT FALSE +#define DFLT_FCH_GPP_PORT1_PRESENT FALSE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL imba180_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) +//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -380,61 +380,61 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket // #define SEED_A 0x12 HW_RXEN_SEED( @@ -474,8 +474,8 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -501,6 +501,6 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]); diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index f6b5806..0e43d10 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -21,93 +21,93 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 3bcaaee..a671969 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -46,7 +46,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SM + device pci 14.0 on # SM chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/asrock/imb-a180/dsdt.asl b/src/mainboard/asrock/imb-a180/dsdt.asl index 78d9bca..4d5cdf9 100644 --- a/src/mainboard/asrock/imb-a180/dsdt.asl +++ b/src/mainboard/asrock/imb-a180/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c index a380872..b043d25 100644 --- a/src/mainboard/asrock/imb-a180/get_bus_conf.c +++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c @@ -141,7 +141,7 @@ void get_bus_conf(void) for (j = bus_yangtze[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_yangtze = apicid_base; diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 83c0b41..c62806f 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_yangtze[6];
@@ -60,7 +60,7 @@ static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) }
static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) + unsigned char id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -88,12 +88,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -157,7 +157,7 @@ static void *smp_write_config_table(void *v)
*(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; #endif - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0); @@ -166,7 +166,7 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
/* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); @@ -228,7 +228,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asus/a8n_e/cmos.layout b/src/mainboard/asus/a8n_e/cmos.layout index 726de26..98aa751 100644 --- a/src/mainboard/asus/a8n_e/cmos.layout +++ b/src/mainboard/asus/a8n_e/cmos.layout @@ -1,27 +1,27 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler 0 384 r 0 reserved_memory 384 1 e 4 boot_option 385 1 e 4 last_boot diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb index c864de7..5ec7016 100644 --- a/src/mainboard/asus/a8n_e/devicetree.cb +++ b/src/mainboard/asus/a8n_e/devicetree.cb @@ -9,107 +9,107 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0x815a inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 0x00 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x71 = 2 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - irq 0x71 = 2 - end - device pnp 2e.7 on # GPIO config - io 0x60 = 0x0800 - # Set GPIO 1 & 2 - io 0x25 = 0x0000 - # Set GPIO 3 & 4 - io 0x27 = 0x2540 - # GPIO Polarity for Set 3 - io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 - io 0xba = 0x0100 - # Simple I/O register config - io 0xc0 = 0x0000 - io 0xc2 = 0x2540 - io 0xc8 = 0x0000 - io 0xca = 0x0500 - end - device pnp 2e.8 on # MIDI port - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a off # IR (N/A on this board) - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # TODO - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x0000 + irq 0x70 = 0x00 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x71 = 2 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + irq 0x71 = 2 + end + device pnp 2e.7 on # GPIO config + io 0x60 = 0x0800 + # Set GPIO 1 & 2 + io 0x25 = 0x0000 + # Set GPIO 3 & 4 + io 0x27 = 0x2540 + # GPIO Polarity for Set 3 + io 0xb2 = 0x2100 + # GPIO Pin Internal Pull up for Set 3 + io 0xba = 0x0100 + # Simple I/O register config + io 0xc0 = 0x0000 + io 0xc2 = 0x2540 + io 0xc8 = 0x0000 + io 0xca = 0x0500 + end + device pnp 2e.8 on # MIDI port + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a off # IR (N/A on this board) + io 0x60 = 0x310 + irq 0x70 = 11 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # TODO + # register "mac_eeprom_smbus" = "3" + # register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index a55401b..a37afd5 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -105,12 +105,12 @@ void get_bus_conf(void)
for (i = 2; i < 6; i++) { dev = dev_find_slot(bus_ck804[0], - PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); + PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); if (dev) { bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804[0], sbdn + 0x0b + i - 2); + bus_ck804[0], sbdn + 0x0b + i - 2); } }
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index 1c7ca45..97bc561 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -107,7 +107,7 @@ static void *smp_write_config_table(void *v) bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804, 0x17);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_ck804[0]);
/* There is no extension information... */ diff --git a/src/mainboard/asus/a8v-e_deluxe/cmos.layout b/src/mainboard/asus/a8v-e_deluxe/cmos.layout index fc13a3c..0e3e716 100644 --- a/src/mainboard/asus/a8v-e_deluxe/cmos.layout +++ b/src/mainboard/asus/a8v-e_deluxe/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb index 5e56acc..36efb14 100644 --- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb +++ b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb @@ -8,86 +8,86 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO 5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl index 3afcdc3..e59794b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl +++ b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl @@ -180,7 +180,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c index 71e0e1e..7c4ac4b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/mptable.c +++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
diff --git a/src/mainboard/asus/a8v-e_se/cmos.layout b/src/mainboard/asus/a8v-e_se/cmos.layout index fc13a3c..0e3e716 100644 --- a/src/mainboard/asus/a8v-e_se/cmos.layout +++ b/src/mainboard/asus/a8v-e_se/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb index f2d078a..f8647e1 100644 --- a/src/mainboard/asus/a8v-e_se/devicetree.cb +++ b/src/mainboard/asus/a8v-e_se/devicetree.cb @@ -8,86 +8,86 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO 5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl index 5f98168..1337625 100644 --- a/src/mainboard/asus/a8v-e_se/dsdt.asl +++ b/src/mainboard/asus/a8v-e_se/dsdt.asl @@ -59,17 +59,17 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs @@ -211,7 +211,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c index 71e0e1e..7c4ac4b 100644 --- a/src/mainboard/asus/a8v-e_se/mptable.c +++ b/src/mainboard/asus/a8v-e_se/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
diff --git a/src/mainboard/asus/dsbf/cmos.layout b/src/mainboard/asus/dsbf/cmos.layout index 29e78ad..cc81664 100644 --- a/src/mainboard/asus/dsbf/cmos.layout +++ b/src/mainboard/asus/dsbf/cmos.layout @@ -23,115 +23,115 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes 9 0 Secondary 9 1 Primary # ----------------------------------------------------------------- diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb index b4d1b63..5149ab2 100644 --- a/src/mainboard/asus/dsbf/devicetree.cb +++ b/src/mainboard/asus/dsbf/devicetree.cb @@ -41,10 +41,10 @@ chip northbridge/intel/i5000 device pci 00.0 on # PCI Express Upstream Port device pci 00.0 on # PCI Express Downstream Port E1 device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A - ioapic_irq 8 INTA 0x11 - ioapic_irq 8 INTB 0x10 - ioapic_irq 8 INTC 0x11 - ioapic_irq 8 INTD 0x10 + ioapic_irq 8 INTA 0x11 + ioapic_irq 8 INTB 0x10 + ioapic_irq 8 INTC 0x11 + ioapic_irq 8 INTD 0x10 # PCI slot device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B # PCI slot @@ -57,26 +57,26 @@ chip northbridge/intel/i5000 ioapic_irq 9 INTB 0 ioapic_irq 9 INTC 1 ioapic_irq 9 INTD 2 - # PCI-X Slot + # PCI-X Slot end
end end
device pci 03.0 on - ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTA 0x10 end device pci 04.0 on - ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTA 0x10 end device pci 05.0 on - ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTA 0x10 end device pci 06.0 on - ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTA 0x10 end device pci 07.0 on - ioapic_irq 8 INTA 0x10 + ioapic_irq 8 INTA 0x10 end
device pci 10.0 on end # FBD @@ -144,10 +144,10 @@ chip northbridge/intel/i5000
device pnp 2e.3 off end device pnp 2e.5 on # KBC - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end
device pnp 2e.6 off end # CIR diff --git a/src/mainboard/asus/dsbf/irq_tables.c b/src/mainboard/asus/dsbf/irq_tables.c index 65c1822..8d99e9a 100644 --- a/src/mainboard/asus/dsbf/irq_tables.c +++ b/src/mainboard/asus/dsbf/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index f4e65cb..d16f167 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -41,7 +41,7 @@ #define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_HPTC 0x3404 /* 32 bit */ #define RCBA_GCS 0x3410 /* 32 bit */ -#define RCBA_FD 0x3418 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */
static void early_config(void) { @@ -78,13 +78,13 @@ static void setup_gpio(void) pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4));
- outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ + outl(0x1b0ce7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xec00ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xff350000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000e742, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000006, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000300, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */
}
@@ -129,12 +129,12 @@ void main(unsigned long bist)
enable_smbus();
- smbus_write_byte(0x6f, 0x00, 0x63); - smbus_write_byte(0x6f, 0x01, 0x04); - smbus_write_byte(0x6f, 0x02, 0x53); - smbus_write_byte(0x6f, 0x03, 0x39); - smbus_write_byte(0x6f, 0x08, 0x06); - smbus_write_byte(0x6f, 0x09, 0x00); + smbus_write_byte(0x6f, 0x00, 0x63); + smbus_write_byte(0x6f, 0x01, 0x04); + smbus_write_byte(0x6f, 0x02, 0x53); + smbus_write_byte(0x6f, 0x03, 0x39); + smbus_write_byte(0x6f, 0x08, 0x06); + smbus_write_byte(0x6f, 0x09, 0x00);
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); i5000_fbdimm_init(); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 2bc0055..7815195 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -28,17 +28,17 @@
STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, - {AGESA_DO_RESET, fam15tn_Reset }, - {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, - {AGESA_READ_SPD, fam15tn_ReadSpd }, - {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_ALLOCATE_BUFFER, fam15tn_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, + {AGESA_DO_RESET, fam15tn_Reset }, + {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, fam15tn_HookGfxGetVbiosImage } };
diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h index bf7eedc..e0e2561 100644 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ b/src/mainboard/asus/f2a85-m/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -50,18 +50,18 @@ * **/
-//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED TRUE #define IDSOPT_TRACING_ENABLED TRUE #define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 8ff64c6..6c7622a 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -120,10 +120,10 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { };
PCIe_COMPLEX_DESCRIPTOR Trinity = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] };
/*---------------------------------------------------------------------------------------*/ @@ -138,7 +138,7 @@ PCIe_COMPLEX_DESCRIPTOR Trinity = { * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ @@ -147,10 +147,10 @@ OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly ) { - AGESA_STATUS Status; - VOID *TrinityPcieComplexListPtr; - VOID *TrinityPciePortPtr; - VOID *TrinityPcieDdiPtr; + AGESA_STATUS Status; + VOID *TrinityPcieComplexListPtr; + VOID *TrinityPciePortPtr; + VOID *TrinityPcieDdiPtr;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
@@ -172,25 +172,25 @@ OemCustomizeInitEarly ( TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(Trinity); - TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof(PortList); - TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
LibAmdMemFill (TrinityPcieComplexListPtr, - 0, - sizeof(Trinity), - &InitEarly->StdHeader); + 0, + sizeof(Trinity), + &InitEarly->StdHeader);
LibAmdMemFill (TrinityPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); + 0, + sizeof(PortList), + &InitEarly->StdHeader);
LibAmdMemFill (TrinityPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); + 0, + sizeof(DdiList), + &InitEarly->StdHeader);
LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); diff --git a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl index f554bbd..3012d5c 100644 --- a/src/mainboard/asus/f2a85-m/acpi/mainboard.asl +++ b/src/mainboard/asus/f2a85-m/acpi/mainboard.asl @@ -31,6 +31,6 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
/* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl index 0685f8d..c9151f1 100644 --- a/src/mainboard/asus/f2a85-m/acpi/routing.asl +++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl @@ -57,7 +57,7 @@ Package(){0x0014FFFF, 3, INTD, 0 },
/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, INTC, 0 }, Package(){0x0012FFFF, 1, INTB, 0 },
@@ -121,7 +121,7 @@
/* SB devices in APIC mode */ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 - * EHCI @ func 2 */ + * EHCI @ func 2 */ Package(){0x0012FFFF, 0, 0, 18 }, Package(){0x0012FFFF, 1, 0, 17 },
diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index d93fecc..96c508b 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -64,7 +64,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write Hudson IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 529878b..b1fb53d 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -52,38 +52,38 @@ VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ UINT32 @@ -91,11 +91,11 @@ agesawrapper_amdinitcpuio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); @@ -140,11 +140,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -185,14 +185,14 @@ agesawrapper_amdinitreset ( AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -225,9 +225,9 @@ agesawrapper_amdinitearly ( AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,16 +270,16 @@ agesawrapper_amdinitpost ( ) { AGESA_STATUS status; - UINT16 i; - UINT32 *HeadPtr; + UINT16 i; + UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -315,12 +315,12 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -380,9 +380,9 @@ agesawrapper_amdinitmid ( agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -411,9 +411,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -443,11 +443,11 @@ agesawrapper_amdinitlate ( AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */ return (UINT32)Status; @@ -464,9 +464,9 @@ agesawrapper_amdlaterunaptask ( AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -491,12 +491,12 @@ UINT32 agesawrapper_amdinitresume(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -530,7 +530,7 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -552,16 +552,16 @@ UINT32 agesawrapper_fchs3earlyrestore (VOID) UINT32 agesawrapper_amds3laterestore (VOID) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio(); LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -598,7 +598,7 @@ UINT32 agesawrapper_fchs3laterestore (VOID) { AGESA_STATUS status = AGESA_SUCCESS;
- FCH_DATA_BLOCK FchParams; + FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; UINT8 byte;
@@ -635,12 +635,12 @@ UINT32 agesawrapper_amdS3Save(VOID) AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -662,8 +662,8 @@ UINT32 agesawrapper_amdS3Save(VOID)
S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); #if 1 /* TODO: Save the params to NvStorage */ Status = OemAgesaSaveS3Info ( S3DataType, @@ -671,8 +671,8 @@ UINT32 agesawrapper_amdS3Save(VOID) AmdS3SaveParamsPtr->S3DataBlock.NvStorage); #endif printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; @@ -704,9 +704,9 @@ agesawrapper_amdreadeventlog ( EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h index 5007510..6db7f33 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ b/src/mainboard/asus/f2a85-m/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -30,27 +30,27 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 0091cd9..7ccba40 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -28,7 +28,7 @@ * For Information about this file, see @ref platforminstall. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 23714 $ @e $Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $ */ @@ -58,30 +58,30 @@
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDOPT_REMOVE_SRAT FALSE //TRUE -#define BLDOPT_REMOVE_SLIT FALSE //TRUE -#define BLDOPT_REMOVE_WHEA FALSE //TRUE +//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDOPT_REMOVE_SRAT FALSE //TRUE +#define BLDOPT_REMOVE_SLIT FALSE //TRUE +#define BLDOPT_REMOVE_WHEA FALSE //TRUE #define BLDOPT_REMOVE_CRAT TRUE -#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
//This element selects whether P-States should be forced to be independent, // as reported by the ACPI _PSD object. For single-link processors, @@ -93,145 +93,145 @@ #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER /* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 90000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE FALSE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_DRAM_RATE 0 -#define BLDCFG_SCRUB_L2_RATE 0 -#define BLDCFG_SCRUB_L3_RATE 0 -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_SCRUB_DC_RATE 0 -#define BLDCFG_ECC_SYMBOL_SIZE 4 -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_ECC_SYNC_FLOOD FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 - -#define BLDOPT_REMOVE_ALIB FALSE -#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled -#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' -#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 - -#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 -#define BLDCFG_CFG_ABM_SUPPORT 0 - -//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 +#define BLDCFG_VRM_CURRENT_LIMIT 90000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE FALSE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_DRAM_RATE 0 +#define BLDCFG_SCRUB_L2_RATE 0 +#define BLDCFG_SCRUB_L3_RATE 0 +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_SCRUB_DC_RATE 0 +#define BLDCFG_ECC_SYMBOL_SIZE 4 +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_ECC_SYNC_FLOOD FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 + +#define BLDOPT_REMOVE_ALIB FALSE +#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled +#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' +#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 + +#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 +#define BLDCFG_CFG_ABM_SUPPORT 0 + +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
// Specify the default values for the VRM controlling the VDDNB plane. // If not specified, the values used for the core VRM will be applied -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
-#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 +#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA -#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED +#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED -//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ -#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ +#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif
-#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID +//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ -// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 -// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 -// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 -// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 -// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 -// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 -// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 -// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 -// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 -// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 -// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 -// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 -// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 -// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 -// #define BLDCFG_AZALIA_SSID 0x780D1022 -// #define BLDCFG_SMBUS_SSID 0x780B1022 -// #define BLDCFG_IDE_SSID 0x780C1022 -// #define BLDCFG_SATA_AHCI_SSID 0x78011022 -// #define BLDCFG_SATA_IDE_SSID 0x78001022 -// #define BLDCFG_SATA_RAID5_SSID 0x78031022 -// #define BLDCFG_SATA_RAID_SSID 0x78021022 -// #define BLDCFG_EHCI_SSID 0x78081022 -// #define BLDCFG_OHCI_SSID 0x78071022 -// #define BLDCFG_LPC_SSID 0x780E1022 -// #define BLDCFG_SD_SSID 0x78061022 -// #define BLDCFG_XHCI_SSID 0x78121022 -// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE -// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 -// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE -// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE -// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE +// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 +// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 +// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 +// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 +// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 +// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 +// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 +// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 +// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 +// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 +// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 +// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 +// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 +// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 +// #define BLDCFG_AZALIA_SSID 0x780D1022 +// #define BLDCFG_SMBUS_SSID 0x780B1022 +// #define BLDCFG_IDE_SSID 0x780C1022 +// #define BLDCFG_SATA_AHCI_SSID 0x78011022 +// #define BLDCFG_SATA_IDE_SSID 0x78001022 +// #define BLDCFG_SATA_RAID5_SSID 0x78031022 +// #define BLDCFG_SATA_RAID_SSID 0x78021022 +// #define BLDCFG_EHCI_SSID 0x78081022 +// #define BLDCFG_OHCI_SSID 0x78071022 +// #define BLDCFG_LPC_SSID 0x780E1022 +// #define BLDCFG_SD_SSID 0x78061022 +// #define BLDCFG_XHCI_SSID 0x78121022 +// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE +// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 +// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE +// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE +// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = { @@ -267,23 +267,23 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "cpuLateInit.h" #include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI" - // This string MUST be exactly 8 characters long + // This is the delivery package title, "BrazosPI" + // This string MUST be exactly 8 characters long #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component - // This string MUST be exactly 12 characters long + // This is the release version number of the AGESA component + // This string MUST be exactly 12 characters long #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 #define DDR2100_FREQUENCY 1050 ///< DDR 2100 #define DDR2133_FREQUENCY 1066 ///< DDR 2133 #define DDR2400_FREQUENCY 1200 ///< DDR 2400 @@ -308,66 +308,66 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = * Comment out or mark TRUE those features you want to REMOVE from the build. */
-#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 -#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 -#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 -#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 -#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 -#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 -#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 -#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 -#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 +#define DFLT_SMBUS0_BASE_ADDRESS 0xB00 +#define DFLT_SMBUS1_BASE_ADDRESS 0xB20 +#define DFLT_SIO_PME_BASE_ADDRESS 0xE00 +#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 +#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 +#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 +#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 +#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 +#define DFLT_SPI_BASE_ADDRESS 0xFEC10000 #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 -#define DFLT_HPET_BASE_ADDRESS 0xFED00000 -#define DFLT_SMI_CMD_PORT 0xB0 -#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -#define DFLT_GEC_BASE_ADDRESS 0xFED61000 -#define DFLT_AZALIA_SSID 0x780D1022 -#define DFLT_SMBUS_SSID 0x780B1022 -#define DFLT_IDE_SSID 0x780C1022 -#define DFLT_SATA_AHCI_SSID 0x78011022 -#define DFLT_SATA_IDE_SSID 0x78001022 -#define DFLT_SATA_RAID5_SSID 0x78031022 -#define DFLT_SATA_RAID_SSID 0x78021022 -#define DFLT_EHCI_SSID 0x78081022 -#define DFLT_OHCI_SSID 0x78071022 -#define DFLT_LPC_SSID 0x780E1022 -#define DFLT_SD_SSID 0x78061022 -#define DFLT_XHCI_SSID 0x78121022 -#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE -#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE -#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 -#define DFLT_FCH_GPP_PORT0_PRESENT TRUE -#define DFLT_FCH_GPP_PORT1_PRESENT TRUE -#define DFLT_FCH_GPP_PORT2_PRESENT FALSE -#define DFLT_FCH_GPP_PORT3_PRESENT FALSE -#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE -#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE +#define DFLT_HPET_BASE_ADDRESS 0xFED00000 +#define DFLT_SMI_CMD_PORT 0xB0 +#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +#define DFLT_GEC_BASE_ADDRESS 0xFED61000 +#define DFLT_AZALIA_SSID 0x780D1022 +#define DFLT_SMBUS_SSID 0x780B1022 +#define DFLT_IDE_SSID 0x780C1022 +#define DFLT_SATA_AHCI_SSID 0x78011022 +#define DFLT_SATA_IDE_SSID 0x78001022 +#define DFLT_SATA_RAID5_SSID 0x78031022 +#define DFLT_SATA_RAID_SSID 0x78021022 +#define DFLT_EHCI_SSID 0x78081022 +#define DFLT_OHCI_SSID 0x78071022 +#define DFLT_LPC_SSID 0x780E1022 +#define DFLT_SD_SSID 0x78061022 +#define DFLT_XHCI_SSID 0x78121022 +#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE +#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE +#define DFLT_FCH_GPP_LINK_CONFIG PortA1B1C1D1 +#define DFLT_FCH_GPP_PORT0_PRESENT TRUE +#define DFLT_FCH_GPP_PORT1_PRESENT TRUE +#define DFLT_FCH_GPP_PORT2_PRESENT FALSE +#define DFLT_FCH_GPP_PORT3_PRESENT FALSE +#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE +#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33 //#define FCH_NO_XHCI_SUPPORT FALSE GPIO_CONTROL f2a85_m_gpio[] = { // {183, Function1, PullUpB}, {-1} }; -#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
// The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000)
#include "PlatformInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -382,61 +382,61 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Speicifes the HW RXEN training seed for a channel of a socket + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Speicifes the HW RXEN training seed for a channel of a socket //
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), @@ -471,8 +471,8 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -498,7 +498,7 @@ UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
@@ -508,7 +508,7 @@ UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0 */ //AGESA_STATUS //AgesaReadSpd ( -// IN UINTN FcnData, +// IN UINTN FcnData, // IN OUT AGESA_READ_SPD_PARAMS *ReadSpd // ) //{ diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index 5520564..784cd13 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -21,93 +21,93 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..5b9927a 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -49,7 +49,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on # SMBUS + device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 device i2c 50 on end # 7-bit SPD address end @@ -59,7 +59,7 @@ chip northbridge/amd/agesa/family15tn/root_complex end # SM device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d + device pci 14.3 on # LPC 0x439d chip superio/ite/it8712f device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index bb9c0fe..d70359a 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -64,14 +64,14 @@ DefinitionBlock (
/** * TODO: The devices listed here (SBR0 and SBR1) do not appear to - * be referenced anywhere and could possibly be removed. + * be referenced anywhere and could possibly be removed. */ Device(SBR0) { /* PCIe 1x SB */ Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(ABR0) } /* APIC mode */ - Return (PBR0) /* PIC mode */ + If(PMOD){ Return(ABR0) } /* APIC mode */ + Return (PBR0) /* PIC mode */ } }
@@ -79,8 +79,8 @@ DefinitionBlock ( Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT, 0) { - If(PMOD){ Return(ABR1) } /* APIC mode */ - Return (PBR1) /* PIC mode */ + If(PMOD){ Return(ABR1) } /* APIC mode */ + Return (PBR1) /* PIC mode */ } } } diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index c92fea9..854d0bb 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -130,7 +130,7 @@ void get_bus_conf(void) for (j = bus_hudson[2]; j < bus_isa; j++) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 97df048..1a0feca 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -29,7 +29,7 @@ #include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
-//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 +//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1 #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6];
@@ -61,7 +61,7 @@ static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) }
static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) + unsigned char id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -89,12 +89,12 @@ static void *smp_write_config_table(void *v) get_bus_conf();
//mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */
dword = 0; dword = pm_ioread(0x34) & 0xF0; @@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); mptable_add_isa_interrupts(mc, bus_isa, apicid_hudson, 0); @@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_hudson, (pin))
/* IOMMU */ PCI_INT(0x0, 0x0, 0x0, 0x10); @@ -184,7 +184,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 031bb50..52a6595 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -82,7 +82,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30);
- /* enable SB MMIO space */ + /* enable SB MMIO space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7);
diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout index fc13a3c..0e3e716 100644 --- a/src/mainboard/asus/k8v-x/cmos.layout +++ b/src/mainboard/asus/k8v-x/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 6bb9bc8..7b0b073 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -8,87 +8,87 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - register "usb2_termination_set" = "1" - register "usb2_termination_a" = "8" - register "usb2_termination_b" = "8" - register "usb2_termination_c" = "6" - register "usb2_termination_d" = "6" - register "usb2_termination_e" = "6" - register "usb2_termination_f" = "6" - register "usb2_termination_g" = "6" - register "usb2_termination_h" = "6" - register "usb2_dpll_set" = "1" - register "usb2_dpll_delay" = "3" - register "int_efgh_as_gpio" = "1" - register "enable_gpo3" = "1" - register "disable_gpo26_gpo27" = "1" - register "enable_aol_2_smb_slave" = "1" - register "enable_gpo5" = "1" - register "gpio15_12_dir_output" = "1" - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 10.4 on end # USB2 - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip superio/winbond/w83697hf # Super I/O - register "hwmon_fan1_divisor" = "128" - register "hwmon_fan2_divisor" = "4" - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - end - device pnp 2e.6 off # CIR - end - device pnp 2e.7 off # Game port/GPIO 1 - end - device pnp 2e.8 off # MIDI/GPIO 5 - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "int_efgh_as_gpio" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 10.4 on end # USB2 + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + end + device pnp 2e.6 off # CIR + end + device pnp 2e.7 off # Game port/GPIO 1 + end + device pnp 2e.8 off # MIDI/GPIO 5 + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl index 76c7abd..50f9af0 100644 --- a/src/mainboard/asus/k8v-x/dsdt.asl +++ b/src/mainboard/asus/k8v-x/dsdt.asl @@ -59,17 +59,17 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs @@ -148,7 +148,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c index 794194c..ba65403 100644 --- a/src/mainboard/asus/k8v-x/mptable.c +++ b/src/mainboard/asus/k8v-x/mptable.c @@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
diff --git a/src/mainboard/asus/m2n-e/cmos.layout b/src/mainboard/asus/m2n-e/cmos.layout index 7281d23..cd95368 100644 --- a/src/mainboard/asus/m2n-e/cmos.layout +++ b/src/mainboard/asus/m2n-e/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb index bbe2124..7391f77 100644 --- a/src/mainboard/asus/m2n-e/devicetree.cb +++ b/src/mainboard/asus/m2n-e/devicetree.cb @@ -28,88 +28,88 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0x8239 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A) - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - io 0x62 = 0x000 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x000 - irq 0x70 = 0 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 # PS/2 mouse IRQ - end - device pnp 2e.7 off # GPIO - io 0x60 = 0x0000 # SMI# Normal Run Access - io 0x62 = 0x800 # Simple I/O - io 0x64 = 0x0000 # Serial Flash I/F - end - device pnp 2e.8 off # MIDI (N/A) - end - device pnp 2e.9 off # Game port (N/A) - end - device pnp 2e.a off # Consumer IR (N/A) - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # Azalia (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A) - device pci a.0 on end # PCI E 5 (PCIEX4) - device pci b.0 off end # PCI E 4 - device pci c.0 on end # PCI E 3 (PCIEX1_2) - device pci d.0 on end # PCI E 2 (PCIEX1_1) - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 (PCIEX16_1) - register "ide0_enable" = "1" # Primary IDE - register "ide1_enable" = "0" # Secondary IDE (N/A) - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A) + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + io 0x62 = 0x000 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x000 + irq 0x70 = 0 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard IRQ + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 # PS/2 mouse IRQ + end + device pnp 2e.7 off # GPIO + io 0x60 = 0x0000 # SMI# Normal Run Access + io 0x62 = 0x800 # Simple I/O + io 0x64 = 0x0000 # Serial Flash I/F + end + device pnp 2e.8 off # MIDI (N/A) + end + device pnp 2e.9 off # Game port (N/A) + end + device pnp 2e.a off # Consumer IR (N/A) + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # Azalia (HD Audio) + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC (N/A) + device pci a.0 on end # PCI E 5 (PCIEX4) + device pci b.0 off end # PCI E 4 + device pci c.0 on end # PCI E 3 (PCIEX1_2) + device pci d.0 on end # PCI E 2 (PCIEX1_1) + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 (PCIEX16_1) + register "ide0_enable" = "1" # Primary IDE + register "ide1_enable" = "0" # Secondary IDE (N/A) + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.0 on end # Link 1 device pci 18.0 on end diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index fd7d304..1f43e60 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -41,13 +41,13 @@ unsigned pci1234x[] = { * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c. */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { @@ -55,13 +55,13 @@ unsigned hcdnx[] = { * device in chain, assume every chain only have 4 ht device at most. */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -100,14 +100,14 @@ void get_bus_conf(void) bus_mcp55[2]++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, " - "using defaults\n", sbdn + 0x06); + "using defaults\n", sbdn + 0x06); bus_mcp55[1] = 2; bus_mcp55[2] = 3; }
for (i = 2; i < 8; i++) { dev = dev_find_slot(bus_mcp55[0], - PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); if (dev) bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 333ec49..baea34d 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4); }
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa);
/* Compute the checksums. */ diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c index 304980b..5bc10b6 100644 --- a/src/mainboard/asus/m2n-e/resourcemap.c +++ b/src/mainboard/asus/m2n-e/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c index 91a5da1..d4faf63 100644 --- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c +++ b/src/mainboard/asus/m2v-mx_se/acpi_tables.c @@ -177,11 +177,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat);
/* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); + printk(BIOS_DEBUG, "ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit);
/* SSDT */ printk(BIOS_DEBUG, "ACPI: * SSDT\n"); diff --git a/src/mainboard/asus/m2v-mx_se/cmos.layout b/src/mainboard/asus/m2v-mx_se/cmos.layout index f2e90e7..b23b589 100644 --- a/src/mainboard/asus/m2v-mx_se/cmos.layout +++ b/src/mainboard/asus/m2v-mx_se/cmos.layout @@ -1,96 +1,96 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -448 3 e 10 videoram_size -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +448 3 e 10 videoram_size +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% # videoram_size: mimics the bits in the ramcontroller. 10 1 8MB 10 2 16MB diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb index 213e3ea..94f9b40 100644 --- a/src/mainboard/asus/m2v-mx_se/devicetree.cb +++ b/src/mainboard/asus/m2v-mx_se/devicetree.cb @@ -8,66 +8,66 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x1d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR end end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8M890 - end + device pci 12.0 on end # VIA LAN + device pci 13.0 on end # br + device pci 13.1 on end # br2 need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8M890 + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index c555058..952e422 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -75,17 +75,17 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs @@ -216,7 +216,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } diff --git a/src/mainboard/asus/m2v/cmos.layout b/src/mainboard/asus/m2v/cmos.layout index fc13a3c..0e3e716 100644 --- a/src/mainboard/asus/m2v/cmos.layout +++ b/src/mainboard/asus/m2v/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb index 61d94ba..4cf2787 100644 --- a/src/mainboard/asus/m2v/devicetree.cb +++ b/src/mainboard/asus/m2v/devicetree.cb @@ -8,64 +8,64 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1043 0 inherit chip northbridge/amd/amdk8 # mc0 device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x0d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # Com2 (N/A on this board) - device pnp 2e.3 on # Lpt1 - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0xd00 - io 0x62 = 0xc00 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - device pci 13.0 on end # br - device pci 13.1 on end # br2, need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x0d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # Com2 (N/A on this board) + device pnp 2e.3 on # Lpt1 + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0xd00 + io 0x62 = 0xc00 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + device pci 13.0 on end # br + device pci 13.1 on end # br2, need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl index fde6ae8..e2d665a 100644 --- a/src/mainboard/asus/m2v/dsdt.asl +++ b/src/mainboard/asus/m2v/dsdt.asl @@ -66,11 +66,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) * * Package contents: * ofs len desc - * 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system state. - * 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any - * given state, OSPM must write the PM1a_CNT.SLP_TYP register before the - * PM1b_CNT.SLP_TYP register. - * 2 2 Reserved + * 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system state. + * 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any + * given state, OSPM must write the PM1a_CNT.SLP_TYP register before the + * PM1b_CNT.SLP_TYP register. + * 2 2 Reserved */ Name (_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) Name (_S3, Package () { 0x01, 0x01, 0x00, 0x00 }) @@ -374,7 +374,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } @@ -413,11 +413,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Method(_CRS, 0) { Name(TMP, ResourceTemplate() { WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length ,, ) IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) @@ -466,18 +466,18 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Offset (0x55), /* * Offset 0x55: - * 3-0: reserved - * 7-4: PCI INTA# routing + * 3-0: reserved + * 7-4: PCI INTA# routing * Offset 0x56: - * 3-0: PCI INTB# routing - * 7-4: PCI INTC# routing + * 3-0: PCI INTB# routing + * 7-4: PCI INTC# routing * Offset 0x57: - * 3-0: reserved - * 7-4: PCI INTD# routing + * 3-0: reserved + * 7-4: PCI INTD# routing * * Valid values for routing link: - * 0: disabled - * 2,8,13: reserved + * 0: disabled + * 2,8,13: reserved * 1,3-7,9-12,14,15: corresponding irq */ , 4, @@ -545,7 +545,7 @@ PCI_INTX_DEV(INTD, PIND, 4) { Offset (0x94), /* two LSB bits are blink rate */ - LEDR, 2, + LEDR, 2, }
Method (_PTS, 1, NotSerialized) diff --git a/src/mainboard/asus/m2v/irq_tables.c b/src/mainboard/asus/m2v/irq_tables.c index de42fcf..8881af5 100644 --- a/src/mainboard/asus/m2v/irq_tables.c +++ b/src/mainboard/asus/m2v/irq_tables.c @@ -45,18 +45,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ (0x11<<3)|0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */ + 0, /* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */ PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */ - 0, /* Miniport data */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5f, /* u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5f, /* u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* peg bridge */ {0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0}, /* pcie bridge */ diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c index b74a1e3..63a2b9b 100644 --- a/src/mainboard/asus/m2v/mptable.c +++ b/src/mainboard/asus/m2v/mptable.c @@ -131,7 +131,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11); smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, 0); /* There is no extension information... */
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 509df90..9840b83 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -207,12 +207,12 @@ static void m2v_bus_init(void) PCI_DEVICE_ID_VIA_K8T890CF_5), 0); /* * bit | meaning - * 6 | 0: hide scratch register function 0:0.6 (we don't use it) - * 5 | 1: enable pcie bridge 0:2.0 - * 4 | 0: hide pcie bridge 0:3.3 (not connected) - * 3 | 1: enable pcie bridge 0:3.2 - * 2 | 1: enable pcie bridge 0:3.1 - * 1 | 1: enable pcie bridge 0:3.0 + * 6 | 0: hide scratch register function 0:0.6 (we don't use it) + * 5 | 1: enable pcie bridge 0:2.0 + * 4 | 0: hide pcie bridge 0:3.3 (not connected) + * 3 | 1: enable pcie bridge 0:3.2 + * 2 | 1: enable pcie bridge 0:3.1 + * 1 | 1: enable pcie bridge 0:3.0 */ pci_write_config8(dev, 0xf0, 0x2e); } diff --git a/src/mainboard/asus/m4a78-em/acpi/ide.asl b/src/mainboard/asus/m4a78-em/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/asus/m4a78-em/acpi/ide.asl +++ b/src/mainboard/asus/m4a78-em/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/asus/m4a78-em/acpi_tables.c b/src/mainboard/asus/m4a78-em/acpi_tables.c index 023345c..88b39cb 100644 --- a/src/mainboard/asus/m4a78-em/acpi_tables.c +++ b/src/mainboard/asus/m4a78-em/acpi_tables.c @@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asus/m4a78-em/cmos.layout b/src/mainboard/asus/m4a78-em/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/asus/m4a78-em/cmos.layout +++ b/src/mainboard/asus/m4a78-em/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb index e760c17..eceed54 100644 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ b/src/mainboard/asus/m4a78-em/devicetree.cb @@ -21,7 +21,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index a844640..a83ad64 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/asus/m4a78-em/irq_tables.c b/src/mainboard/asus/m4a78-em/irq_tables.c index 41d5880..3be0601 100644 --- a/src/mainboard/asus/m4a78-em/irq_tables.c +++ b/src/mainboard/asus/m4a78-em/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xca, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/asus/m4a78-em/resourcemap.c +++ b/src/mainboard/asus/m4a78-em/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index f19fa8d..78ac6dd 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -237,8 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/asus/m4a785-m/acpi/ide.asl b/src/mainboard/asus/m4a785-m/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/asus/m4a785-m/acpi/ide.asl +++ b/src/mainboard/asus/m4a785-m/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c index 21a8b33..8770240 100644 --- a/src/mainboard/asus/m4a785-m/acpi_tables.c +++ b/src/mainboard/asus/m4a785-m/acpi_tables.c @@ -93,7 +93,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asus/m4a785-m/cmos.layout b/src/mainboard/asus/m4a785-m/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/asus/m4a785-m/cmos.layout +++ b/src/mainboard/asus/m4a785-m/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb index 4549ead..1ea100f 100644 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ b/src/mainboard/asus/m4a785-m/devicetree.cb @@ -21,7 +21,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 off end # device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index a844640..a83ad64 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/asus/m4a785-m/irq_tables.c b/src/mainboard/asus/m4a785-m/irq_tables.c index 708f311..6bef2f2 100644 --- a/src/mainboard/asus/m4a785-m/irq_tables.c +++ b/src/mainboard/asus/m4a785-m/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x8, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, {0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0}, {0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0}, diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..3d93abf 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -28,7 +28,7 @@ #include "southbridge/amd/sb700/smbus.h"
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/asus/m4a785-m/resourcemap.c +++ b/src/mainboard/asus/m4a785-m/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f8d6680..723ddcd 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -237,8 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically @@ -258,7 +258,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) #else static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF}; /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((node == 0) && (link == 0)) { /* BSP SB link */ + if ((node == 0) && (link == 0)) { /* BSP SB link */ *List = swaplist; return 1; } diff --git a/src/mainboard/asus/m4a785t-m/acpi/ide.asl b/src/mainboard/asus/m4a785t-m/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/asus/m4a785t-m/acpi/ide.asl +++ b/src/mainboard/asus/m4a785t-m/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/asus/m4a785t-m/cmos.layout +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index 9783989..194a09b 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -23,7 +23,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 off end # device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index 5449d01..5548a42 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "ASUS", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1439,7 +1439,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1557,23 +1557,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1582,7 +1582,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 942a81d..899aba6 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -91,7 +91,7 @@ config RAMBASE default 0x200000
config VGA_BIOS_ID - string - default "1002,9715" + string + default "1002,9715"
endif #BOARD_ASUS_M5A88_V diff --git a/src/mainboard/asus/m5a88-v/acpi/ide.asl b/src/mainboard/asus/m5a88-v/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/asus/m5a88-v/acpi/ide.asl +++ b/src/mainboard/asus/m5a88-v/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c index 2591d84..a941938 100644 --- a/src/mainboard/asus/m5a88-v/acpi_tables.c +++ b/src/mainboard/asus/m5a88-v/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/asus/m5a88-v/cmos.layout b/src/mainboard/asus/m5a88-v/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/asus/m5a88-v/cmos.layout +++ b/src/mainboard/asus/m5a88-v/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb index 4b3142e..c5712d3 100644 --- a/src/mainboard/asus/m5a88-v/devicetree.cb +++ b/src/mainboard/asus/m5a88-v/devicetree.cb @@ -57,46 +57,46 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/ite/it8721f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/ite/it8721f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index 6e1ccd1..060309f 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "ASUS ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -129,13 +129,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -154,7 +154,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -279,8 +279,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -416,16 +416,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -796,7 +796,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1175,7 +1175,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1197,8 +1197,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1208,8 +1208,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1217,8 +1217,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1226,8 +1226,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1236,8 +1236,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1246,8 +1246,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1255,8 +1255,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1264,32 +1264,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1543,8 +1543,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1587,43 +1587,43 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1632,7 +1632,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 9bb26e6..b0d7183 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -138,7 +138,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c index cb7aeee..191a186 100644 --- a/src/mainboard/asus/m5a88-v/mptable.c +++ b/src/mainboard/asus/m5a88-v/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x11, dword); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -81,7 +81,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index f1eb9f5..c608916 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -141,13 +141,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -219,7 +219,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c index 183883a..a1fe5a0 100644 --- a/src/mainboard/asus/m5a88-v/resourcemap.c +++ b/src/mainboard/asus/m5a88-v/resourcemap.c @@ -31,21 +31,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -65,25 +65,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -104,27 +104,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -145,21 +145,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -176,23 +176,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -206,23 +206,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -236,35 +236,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 368b659..6e01576 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -237,8 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/asus/mew-am/devicetree.cb b/src/mainboard/asus/mew-am/devicetree.cb index 8a20cab..4cfecdd 100644 --- a/src/mainboard/asus/mew-am/devicetree.cb +++ b/src/mainboard/asus/mew-am/devicetree.cb @@ -13,42 +13,42 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 2e.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end - end + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a on # Power-management events (PME) + io 0x60 = 0x600 + end + device pnp 2e.b on # MIDI port (MPU-401) + io 0x60 = 0x330 + irq 0x70 = 5 + end + end end device pci 1f.1 on end # IDE device pci 1f.2 on end # USB diff --git a/src/mainboard/asus/mew-am/irq_tables.c b/src/mainboard/asus/mew-am/irq_tables.c index 06968d5..1ac6fdb 100644 --- a/src/mainboard/asus/mew-am/irq_tables.c +++ b/src/mainboard/asus/mew-am/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xe3, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x1e<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, {0x01,(0x08<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x01,(0x09<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, diff --git a/src/mainboard/asus/mew-vm/cmos.layout b/src/mainboard/asus/mew-vm/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/asus/mew-vm/cmos.layout +++ b/src/mainboard/asus/mew-vm/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c index 4fbf122..bea468c 100644 --- a/src/mainboard/asus/mew-vm/irq_tables.c +++ b/src/mainboard/asus/mew-vm/irq_tables.c @@ -9,10 +9,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ 0xe20, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7120, /* Device */ @@ -21,7 +21,7 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x89, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b-d/devicetree.cb index fe82a0d..7e92d71 100644 --- a/src/mainboard/asus/p2b-d/devicetree.cb +++ b/src/mainboard/asus/p2b-d/devicetree.cb @@ -12,39 +12,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b-d/irq_tables.c index af6f851..c79ebd7 100644 --- a/src/mainboard/asus/p2b-d/irq_tables.c +++ b/src/mainboard/asus/p2b-d/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x54, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c index 51d00a3..542008b 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b-d/mptable.c @@ -45,10 +45,10 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
- /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */ + /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums. */ diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b-ds/devicetree.cb index b8e9e85..a7358a8 100644 --- a/src/mainboard/asus/p2b-ds/devicetree.cb +++ b/src/mainboard/asus/p2b-ds/devicetree.cb @@ -12,39 +12,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b-ds/irq_tables.c index b678520..df79cf6 100644 --- a/src/mainboard/asus/p2b-ds/irq_tables.c +++ b/src/mainboard/asus/p2b-ds/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x36, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c index ee3c20e..5d68024 100644 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ b/src/mainboard/asus/p2b-ds/mptable.c @@ -45,11 +45,11 @@ static void *smp_write_config_table(void *v) /* Legacy Interrupts */ mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
- /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); + /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13);
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, 0x1);
/* Compute the checksums. */ diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b-f/devicetree.cb index 5bee5ae..c092560 100644 --- a/src/mainboard/asus/p2b-f/devicetree.cb +++ b/src/mainboard/asus/p2b-f/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b-f/irq_tables.c index a66761f..8e09af0 100644 --- a/src/mainboard/asus/p2b-f/irq_tables.c +++ b/src/mainboard/asus/p2b-f/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf9, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb index 9a785da..945876f 100644 --- a/src/mainboard/asus/p2b-ls/devicetree.cb +++ b/src/mainboard/asus/p2b-ls/devicetree.cb @@ -9,43 +9,43 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI - device pci 7.0 on end # Onboard LAN + device pci 6.0 on end # Onboard SCSI + device pci 7.0 on end # Onboard LAN register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b-ls/irq_tables.c index e5ff319..34028c3 100644 --- a/src/mainboard/asus/p2b-ls/irq_tables.c +++ b/src/mainboard/asus/p2b-ls/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x10, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0}, {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0}, {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p2b/devicetree.cb b/src/mainboard/asus/p2b/devicetree.cb index 84f0c29..6d589a3 100644 --- a/src/mainboard/asus/p2b/devicetree.cb +++ b/src/mainboard/asus/p2b/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 00d1d76..b318a94 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -28,11 +28,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) * 1: suspend to ram S3 * 2: powered on suspend, context lost S2 * Note: 'context lost' means the CPU restarts at the reset - * vector + * vector * 3: powered on suspend, CPU context lost S1 * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 * 4: powered on suspend, context maintained S1 * 5: working (clock control) S0 * 6: reserved diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c index ed38e47..fb2e97b 100644 --- a/src/mainboard/asus/p2b/irq_tables.c +++ b/src/mainboard/asus/p2b/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x54, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb index 5bee5ae..c092560 100644 --- a/src/mainboard/asus/p3b-f/devicetree.cb +++ b/src/mainboard/asus/p3b-f/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 4.1 on end # IDE device pci 4.2 on end # USB diff --git a/src/mainboard/asus/p3b-f/irq_tables.c b/src/mainboard/asus/p3b-f/irq_tables.c index 6a5f0c9..a44a442 100644 --- a/src/mainboard/asus/p3b-f/irq_tables.c +++ b/src/mainboard/asus/p3b-f/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x95, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 99b9c67..8f7308a 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -93,11 +93,11 @@ config RAMBASE default 0x200000
config VGA_BIOS_ID - string - default "1002,9712" + string + default "1002,9712"
config SIO_PORT - hex - default 0x2E + hex + default 0x2E
endif #BOARD_AVALUE_EAX_785E diff --git a/src/mainboard/avalue/eax-785e/acpi/ide.asl b/src/mainboard/avalue/eax-785e/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/avalue/eax-785e/acpi/ide.asl +++ b/src/mainboard/avalue/eax-785e/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c index 2591d84..a941938 100644 --- a/src/mainboard/avalue/eax-785e/acpi_tables.c +++ b/src/mainboard/avalue/eax-785e/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB800 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/avalue/eax-785e/cmos.layout +++ b/src/mainboard/avalue/eax-785e/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01..7006e79 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -44,46 +44,46 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 Keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 Keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf end # LPC 0x439d device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index dd766f7..265479a 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AVALUE ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AVALUE ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -129,13 +129,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -154,7 +154,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -279,8 +279,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -416,16 +416,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -796,7 +796,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1175,7 +1175,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1197,8 +1197,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1208,8 +1208,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1217,8 +1217,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1226,8 +1226,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1236,8 +1236,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1246,8 +1246,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1255,8 +1255,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1264,32 +1264,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1543,8 +1543,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1587,43 +1587,43 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1632,7 +1632,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index 9bb26e6..b0d7183 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -138,7 +138,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469..4ed71dc 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -42,7 +42,7 @@ void enable_int_gfx(void) RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ #endif /* make sure the Acpi MMIO(fed80000) is accessible */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); + RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c index 1889e02..db32011 100644 --- a/src/mainboard/avalue/eax-785e/mptable.c +++ b/src/mainboard/avalue/eax-785e/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword); dword &= 0xFFFFFFF0;
@@ -71,7 +71,7 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -82,7 +82,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -136,7 +136,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 68db913..5d8e09e 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -221,7 +221,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ diff --git a/src/mainboard/avalue/eax-785e/resourcemap.c b/src/mainboard/avalue/eax-785e/resourcemap.c index 183883a..a1fe5a0 100644 --- a/src/mainboard/avalue/eax-785e/resourcemap.c +++ b/src/mainboard/avalue/eax-785e/resourcemap.c @@ -31,21 +31,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -65,25 +65,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -104,27 +104,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -145,21 +145,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -176,23 +176,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -206,23 +206,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -236,35 +236,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 39c7247..a9f59dd 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -238,8 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/axus/tc320/devicetree.cb b/src/mainboard/axus/tc320/devicetree.cb index 970f71f..d3fd76d 100644 --- a/src/mainboard/axus/tc320/devicetree.cb +++ b/src/mainboard/axus/tc320/devicetree.cb @@ -3,43 +3,43 @@ chip northbridge/amd/gx1 # Northbridge device pci 0.0 on end # Host bridge chip southbridge/amd/cs5530 # Southbridge device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe800 - end - end + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe800 + end + end end device pci 12.1 off end # SMI device pci 12.2 off end # IDE diff --git a/src/mainboard/axus/tc320/irq_tables.c b/src/mainboard/axus/tc320/irq_tables.c index 71cf2e1..6c54eca 100644 --- a/src/mainboard/axus/tc320/irq_tables.c +++ b/src/mainboard/axus/tc320/irq_tables.c @@ -29,14 +29,14 @@ * * This is the physical routing on this board: * - * IRQ 5530 USB Network + * IRQ 5530 USB Network * controller northbridge device device - * 00.13.0 00.0e.00 + * 00.13.0 00.0e.00 * -------------------------------------------- - * 11 INTA# INTA# n.c. - * 15 INTB# n.c. INTA# - * INTC# n.c. n.c. - * INTD# n.c. n.c. + * 11 INTA# INTA# n.c. + * 15 INTB# n.c. INTA# + * INTC# n.c. n.c. + * INTD# n.c. n.c. */
#include <arch/pirq_routing.h> @@ -83,7 +83,7 @@ static const struct irq_routing_table intel_irq_routing_table = { .bus = 0x00, .devfn = (0x13 << 3) | 0x0, .irq = { - /* Link Bitmap */ + /* Link Bitmap */ [0] = { INT_A, IRQ_BITMAP_LINK0 }, [1] = { INT_B, IRQ_BITMAP_LINK1 }, [2] = { INT_C, IRQ_BITMAP_LINK2 }, @@ -99,7 +99,7 @@ static const struct irq_routing_table intel_irq_routing_table = { .bus = 0x00, .devfn = (0x0e << 3) | 0x0, .irq = { - /* Link Bitmap */ + /* Link Bitmap */ [0] = { INT_B, IRQ_BITMAP_LINK1 }, [1] = { INT_C, IRQ_BITMAP_LINK2 }, [2] = { INT_D, IRQ_BITMAP_LINK3 }, diff --git a/src/mainboard/azza/pt-6ibd/devicetree.cb b/src/mainboard/azza/pt-6ibd/devicetree.cb index a2f5513..05cbe20 100644 --- a/src/mainboard/azza/pt-6ibd/devicetree.cb +++ b/src/mainboard/azza/pt-6ibd/devicetree.cb @@ -9,39 +9,39 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/azza/pt-6ibd/irq_tables.c b/src/mainboard/azza/pt-6ibd/irq_tables.c index d99b230..b17e134 100644 --- a/src/mainboard/azza/pt-6ibd/irq_tables.c +++ b/src/mainboard/azza/pt-6ibd/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x3c, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x09<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/bachmann/ot200/cmos.layout b/src/mainboard/bachmann/ot200/cmos.layout index 90ade93..9719405 100644 --- a/src/mainboard/bachmann/ot200/cmos.layout +++ b/src/mainboard/bachmann/ot200/cmos.layout @@ -22,37 +22,37 @@ entries #start-bit length config config-ID name # ----------------------------------------------------------------- # RTC reserved -0 384 r 0 reserved_memory +0 384 r 0 reserved_memory
# ----------------------------------------------------------------- # coreboot config options: console -384 3 e 1 baud_rate -387 4 e 2 debug_level +384 3 e 1 baud_rate +387 4 e 2 debug_level
# ----------------------------------------------------------------- # coreboot config options: check sums -1008 16 h 0 check_sum +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 115200 -1 1 57600 -1 2 38400 -1 3 19200 -1 4 9600 -1 5 4800 -1 6 2400 -1 7 1200 -2 0 Emergency -2 1 Alert -2 2 Critical -2 3 Error -2 4 Warning -2 5 Notice -2 6 Info -2 7 Debug -2 8 Spew +1 0 115200 +1 1 57600 +1 2 38400 +1 3 19200 +1 4 9600 +1 5 4800 +1 6 2400 +1 7 1200 +2 0 Emergency +2 1 Alert +2 2 Critical +2 3 Error +2 4 Warning +2 5 Notice +2 6 Info +2 7 Debug +2 8 Spew
checksums
diff --git a/src/mainboard/bachmann/ot200/devicetree.cb b/src/mainboard/bachmann/ot200/devicetree.cb index 1e61b3d..0e2f3ab 100644 --- a/src/mainboard/bachmann/ot200/devicetree.cb +++ b/src/mainboard/bachmann/ot200/devicetree.cb @@ -2,7 +2,7 @@ chip northbridge/amd/lx device domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics - device pci 1.2 on end # AES + device pci 1.2 on end # AES chip southbridge/amd/cs5536 register "lpc_serirq_enable" = "0x00000000" register "lpc_serirq_polarity" = "0x00000000" @@ -20,7 +20,7 @@ chip northbridge/amd/lx register "unwanted_vpci[0]" = "0" # End of list has a zero device pci 4.0 on end # Ethernet 0 device pci f.0 on # ISA Bridge - chip drivers/generic/generic # eeprom + chip drivers/generic/generic # eeprom device i2c 52 on end end end diff --git a/src/mainboard/bachmann/ot200/irq_tables.c b/src/mainboard/bachmann/ot200/irq_tables.c index 428032f..0b0406f 100644 --- a/src/mainboard/bachmann/ot200/irq_tables.c +++ b/src/mainboard/bachmann/ot200/irq_tables.c @@ -55,10 +55,10 @@ static const struct irq_routing_table intel_irq_routing_table = { * for this structure (including checksum). */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */ } };
diff --git a/src/mainboard/bcom/winnet100/devicetree.cb b/src/mainboard/bcom/winnet100/devicetree.cb index 61a71e6..b4c2947 100644 --- a/src/mainboard/bcom/winnet100/devicetree.cb +++ b/src/mainboard/bcom/winnet100/devicetree.cb @@ -4,43 +4,43 @@ chip northbridge/amd/gx1 # Northbridge chip southbridge/amd/cs5530 # Southbridge device pci 0f.0 on end # Ethernet (onboard) device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 (used for smartcard reader) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, Advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 (used for smartcard reader) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe8 + end + end end device pci 12.1 off end # SMI device pci 12.2 on end # IDE diff --git a/src/mainboard/bcom/winnet100/irq_tables.c b/src/mainboard/bcom/winnet100/irq_tables.c index 8d9e157..730ba64 100644 --- a/src/mainboard/bcom/winnet100/irq_tables.c +++ b/src/mainboard/bcom/winnet100/irq_tables.c @@ -28,14 +28,14 @@ * * This is the physical routing on this board: * - * 5530 USB Network - * northbridge device device - * 00.13.0 00.0f.00 + * 5530 USB Network + * northbridge device device + * 00.13.0 00.0f.00 * ------------------------------------ - * INTA# INTA# n.c. - * INTB# n.c. n.c. - * INTC# n.c. INTA# - * INTD# n.c. n.c. + * INTA# INTA# n.c. + * INTB# n.c. n.c. + * INTC# n.c. INTA# + * INTD# n.c. n.c. */
#include <arch/pirq_routing.h> @@ -81,7 +81,7 @@ static const struct irq_routing_table intel_irq_routing_table = { .bus = 0x00, .devfn = (0x13 << 3) | 0x0, .irq = { - /* Link Bitmap */ + /* Link Bitmap */ [0] = { INT_A, IRQ_BITMAP_LINK0 }, [1] = { INT_B, IRQ_BITMAP_LINK1 }, [2] = { INT_C, IRQ_BITMAP_LINK2 }, @@ -98,7 +98,7 @@ static const struct irq_routing_table intel_irq_routing_table = { .bus = 0x00, .devfn = (0x0f << 3) | 0x0, .irq = { - /* Link Bitmap */ + /* Link Bitmap */ [0] = { INT_C, IRQ_BITMAP_LINK2 }, [1] = { INT_D, IRQ_BITMAP_LINK3 }, [2] = { INT_A, IRQ_BITMAP_LINK0 }, diff --git a/src/mainboard/bcom/winnetp680/cmos.layout b/src/mainboard/bcom/winnetp680/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/bcom/winnetp680/cmos.layout +++ b/src/mainboard/bcom/winnetp680/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/bcom/winnetp680/devicetree.cb b/src/mainboard/bcom/winnetp680/devicetree.cb index f0a086b..ff83c11 100644 --- a/src/mainboard/bcom/winnetp680/devicetree.cb +++ b/src/mainboard/bcom/winnetp680/devicetree.cb @@ -23,34 +23,34 @@ chip northbridge/via/cn700 # Northbridge device pci 10.3 on end # UHCI device pci 10.4 on end # EHCI device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, GPIO 1 - device pnp 2e.8 off end # MIDI port, GPIO 5 - device pnp 2e.9 off end # GPIO 2-4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - end + chip superio/winbond/w83697hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, GPIO 1 + device pnp 2e.8 off end # MIDI port, GPIO 5 + device pnp 2e.9 off end # GPIO 2-4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + end end device pci 11.5 on end # AC'97 audio device pci 12.0 on end # Ethernet diff --git a/src/mainboard/bcom/winnetp680/irq_tables.c b/src/mainboard/bcom/winnetp680/irq_tables.c index 888cf48..8cff836 100644 --- a/src/mainboard/bcom/winnetp680/irq_tables.c +++ b/src/mainboard/bcom/winnetp680/irq_tables.c @@ -34,7 +34,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x3e, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, diff --git a/src/mainboard/biostar/m6tba/devicetree.cb b/src/mainboard/biostar/m6tba/devicetree.cb index 0d35e9c..7d99b42 100644 --- a/src/mainboard/biostar/m6tba/devicetree.cb +++ b/src/mainboard/biostar/m6tba/devicetree.cb @@ -9,33 +9,33 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.8 on # Aux I/O - end - end + chip superio/smsc/smscsuperio # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.8 on # Aux I/O + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/biostar/m6tba/irq_tables.c b/src/mainboard/biostar/m6tba/irq_tables.c index 268cd38..ce7e5e0 100644 --- a/src/mainboard/biostar/m6tba/irq_tables.c +++ b/src/mainboard/biostar/m6tba/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xc7, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/broadcom/blast/cmos.layout b/src/mainboard/broadcom/blast/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/broadcom/blast/cmos.layout +++ b/src/mainboard/broadcom/blast/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index b1486a6..d6b7ae4 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -1,117 +1,117 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x161f 0x3050 inherit chip northbridge/amd/amdk8 device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on # Legacy pci main 0x0205 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 71 on end #0 pca9554 0 + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on # Legacy pci main 0x0205 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 71 on end #0 pca9554 0 device i2c 71 on end #0 pca9554 1 device i2c 71 on end #0 pca9554 2 device i2c 71 on end #0 pca9554 3 device i2c 71 on end #0 pca9554 4 device i2c 71 on end #0 pca9554 5 - device i2c 71 on #0 pca9554 6 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 71 on #1 pca9554 7 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end + device i2c 71 on #0 pca9554 6 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 71 on #1 pca9554 7 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end
end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC io 0x60 = 0x70 io 0x62 = 0x72 end - end - end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 4.0 on end # it is in bcm5785_0 bus - end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 4.0 on end # it is in bcm5785_0 bus + end end # device pci 18.0
- device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -119,16 +119,16 @@ chip northbridge/amd/amdk8/root_complex
end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end
end
diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 5de8952..9fe3900 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -21,24 +21,24 @@ unsigned apicid_bcm5785[3]; unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn2; @@ -83,8 +83,8 @@ void get_bus_conf(void) } } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:07.0, using defaults\n", - bus_bcm5785_0); + "ERROR - could not find PCI %02x:07.0, using defaults\n", + bus_bcm5785_0); }
/* bcm5780 */ @@ -96,8 +96,8 @@ void get_bus_conf(void) pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_bcm5780[i]); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_bcm5780[i]); } }
diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 64734a5..2d1aa38 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -13,11 +13,11 @@ #include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; + pirq_info->bus = bus; + pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -49,17 +49,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
get_bus_conf();
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -89,14 +89,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..66ef37b 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -19,31 +19,31 @@ extern unsigned sbdn2;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev = 0; + { + device_t dev = 0; struct resource *res; for(i=0; i<3; i++) { - dev = dev_find_device(0x1166, 0x0235, dev); - if (dev) { + dev = dev_find_device(0x1166, 0x0235, dev); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base); } - } + } }
} @@ -57,77 +57,77 @@ static void *smp_write_config_table(void *v)
//SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
//USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // - } + for(i=0;i<3;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); // + }
- /* enable int */ - /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ - { - device_t dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts - pci_write_config32(dev, 0x6c, dword); + /* enable int */ + /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x6c); + dword |= (1<<4); // enable interrupts + pci_write_config32(dev, 0x6c, dword);
- } + }
- } + }
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); // + }
//pci slot (on bcm5785) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); // + }
//onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); // + }
- for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); // + }
//onboard Broadcom - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // - } + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); // + }
// First PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); // + }
// Second PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); // + }
// Third PCI-E x1 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); // + }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/broadcom/blast/resourcemap.c b/src/mainboard/broadcom/blast/resourcemap.c index 71f0bba..cc7919c 100644 --- a/src/mainboard/broadcom/blast/resourcemap.c +++ b/src/mainboard/broadcom/blast/resourcemap.c @@ -17,21 +17,21 @@ static void setup_blast_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -51,25 +51,25 @@ static void setup_blast_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -90,27 +90,27 @@ static void setup_blast_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -131,21 +131,21 @@ static void setup_blast_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -162,23 +162,23 @@ static void setup_blast_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -192,23 +192,23 @@ static void setup_blast_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -222,35 +222,35 @@ static void setup_blast_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 0b4d422..a14ef40 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -29,8 +29,8 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_HUB, device); + unsigned device=(ctrl->channel0[0])>>8; + smbus_send_byte(SMBUS_HUB, device); }
#if 0 @@ -38,15 +38,15 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x71 int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - ret = smbus_send_byte(SMBUS_HUB, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + ret = smbus_send_byte(SMBUS_HUB, device); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); } #endif
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/raminit.c" @@ -65,74 +65,74 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, };
- int needs_reset; + int needs_reset; unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + struct mem_controller ctrl[8];
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ - } + }
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
- setup_blast_resource_map(); + setup_blast_resource_map();
#if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - wait_all_core0_started(); - start_other_cores(); + // It is said that we should start core1 after all core0 launched + wait_all_core0_started(); + start_other_cores(); #endif - wait_all_aps_started(bsp_apicid); + wait_all_aps_started(bsp_apicid);
- needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
bcm5785_early_setup();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
#if 0 - int i; - for(i=4;i<8;i++) { - change_i2c_mux(i); - dump_smbus_registers(); - } + int i; + for(i=4;i<8;i++) { + change_i2c_mux(i); + dump_smbus_registers(); + } #endif
memreset_setup(); @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(nodes, ctrl);
#if 0 - print_pci_devices(); + print_pci_devices(); dump_pci_devices(); #endif
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb index def9e2f..e044b50 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb +++ b/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb @@ -10,42 +10,42 @@ chip northbridge/intel/i440bx # Northbridge device pci a.0 on end # NIC (onboard) chip southbridge/intel/i82371eb # Southbridge device pci 14.0 on # ISA bridge - # chip superio/nsc/pc97307 # Super I/O - chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!) - device pnp 15c.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 15c.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 15c.2 on # RTC, APC - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 15c.3 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 15c.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 15c.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 15c.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 15c.7 on # GPIO 1 - end - device pnp 15c.8 on # Power management - end - end + # chip superio/nsc/pc97307 # Super I/O + chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!) + device pnp 15c.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 15c.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 15c.2 on # RTC, APC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 15c.3 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 15c.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 15c.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 15c.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 15c.7 on # GPIO 1 + end + device pnp 15c.8 on # Power management + end + end end device pci 14.1 on end # IDE device pci 14.2 on end # USB diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c index 5761235..0a9dd9c 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x97, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0d<<3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, {0x00,(0x0e<<3)|0x0, {{0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x00ef8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x63, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, diff --git a/src/mainboard/digitallogic/adl855pc/cmos.layout b/src/mainboard/digitallogic/adl855pc/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/digitallogic/adl855pc/cmos.layout +++ b/src/mainboard/digitallogic/adl855pc/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/digitallogic/adl855pc/devicetree.cb b/src/mainboard/digitallogic/adl855pc/devicetree.cb index 3a9603b..e9ba1eb 100644 --- a/src/mainboard/digitallogic/adl855pc/devicetree.cb +++ b/src/mainboard/digitallogic/adl855pc/devicetree.cb @@ -14,38 +14,38 @@ chip northbridge/intel/i855 register "enable_usb" = "0" register "enable_native_ide" = "0" chip superio/winbond/w83627hf # link 1 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end - end + end end end device cpu_cluster 0 on diff --git a/src/mainboard/digitallogic/adl855pc/irq_tables.c b/src/mainboard/digitallogic/adl855pc/irq_tables.c index 94adba1..e7e4bd1 100644 --- a/src/mainboard/digitallogic/adl855pc/irq_tables.c +++ b/src/mainboard/digitallogic/adl855pc/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ - 0x88, /* Where the interrupt router lies (dev) */ - 0x1c20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x8231, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x88, /* Where the interrupt router lies (dev) */ + 0x1c20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x8231, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* 8231 ethernet */ {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, @@ -32,5 +32,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 7eefedd..05e3e61 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -34,8 +34,8 @@ void main(unsigned long bist) #endif }
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -45,7 +45,7 @@ void main(unsigned long bist) #endif
if (!bios_reset_detected()) { - enable_smbus(); + enable_smbus(); #if 0 dump_spd_registers(); dump_smbus_registers(); diff --git a/src/mainboard/digitallogic/msm586seg/cmos.layout b/src/mainboard/digitallogic/msm586seg/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/digitallogic/msm586seg/cmos.layout +++ b/src/mainboard/digitallogic/msm586seg/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/digitallogic/msm586seg/irq_tables.c b/src/mainboard/digitallogic/msm586seg/irq_tables.c index 15dcddd..d4f1fb0 100644 --- a/src/mainboard/digitallogic/msm586seg/irq_tables.c +++ b/src/mainboard/digitallogic/msm586seg/irq_tables.c @@ -9,23 +9,23 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0}, {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c index 6cb5f07..8d632a9 100644 --- a/src/mainboard/digitallogic/msm586seg/mainboard.c +++ b/src/mainboard/digitallogic/msm586seg/mainboard.c @@ -12,7 +12,7 @@ static void irqdump(void) void *mmcr; int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, - 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, + 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 9f3da08..4efbef3 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -12,26 +12,26 @@ void setup_pars(void) volatile unsigned long *par; /* as per the book: */ /* PAR register setup */ - /* set up the PAR registers as they are on the MSM586SEG */ - par = (unsigned long *) 0xfffef088; - - /* NOTE: move this to mainboard.c ASAP */ - *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/ - *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/ - *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/ - *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/ - *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/ - *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/ - *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/ - *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/ - *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/ - *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/ - *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/ - *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/ - *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/ - *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/ - *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ - *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ + /* set up the PAR registers as they are on the MSM586SEG */ + par = (unsigned long *) 0xfffef088; + + /* NOTE: move this to mainboard.c ASAP */ + *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/ + *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/ + *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/ + *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/ + *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/ + *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/ + *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/ + *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/ + *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/ + *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/ + *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/ + *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/ + *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/ + *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/ + *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ + *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ }
#include "cpu/amd/sc520/raminit.c" @@ -160,9 +160,9 @@ static void main(unsigned long bist) for(i = 0; i < 100; i++) ;
- setupsc520(); + setupsc520(); irqinit(); - console_init(); + console_init(); for(i = 0; i < 100; i++) print_err("fill usart\n"); // while(1) @@ -180,7 +180,7 @@ static void main(unsigned long bist) #if 0
/* clear memory 1meg */ - __asm__ volatile( + __asm__ volatile( "1: \n\t" "movl %0, %%fs:(%1)\n\t" "addl $4,%1\n\t" @@ -220,7 +220,7 @@ static void main(unsigned long bist)
print_err("loop forever\n"); post_code(0xdd); - __asm__ volatile( + __asm__ volatile( "movl %0, %%edi\n\t" "jmp *%%edi\n\t" : diff --git a/src/mainboard/digitallogic/msm800sev/cmos.layout b/src/mainboard/digitallogic/msm800sev/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/digitallogic/msm800sev/cmos.layout +++ b/src/mainboard/digitallogic/msm800sev/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 839b767..52a37d2 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,8 +69,8 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI end end diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c index 53cbb27..7bc9452 100644 --- a/src/mainboard/digitallogic/msm800sev/irq_tables.c +++ b/src/mainboard/digitallogic/msm800sev/irq_tables.c @@ -43,10 +43,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x0f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x100b, /* Vendor */ 0x2b, /* Device */ @@ -56,7 +56,7 @@ static const struct irq_routing_table intel_irq_routing_table = { value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0}, {0x00,(0x13<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c index 6d4a4ac..2d07d3d 100644 --- a/src/mainboard/digitallogic/msm800sev/mainboard.c +++ b/src/mainboard/digitallogic/msm800sev/mainboard.c @@ -28,10 +28,10 @@ static void init(struct device *dev)
static void mainboard_enable(struct device *dev) { - dev->ops->init = init; + dev->ops->init = init; }
struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, };
diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index 723a251..1cec20c 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -184,7 +184,7 @@ config IDE_COMPATIBLE_SELECTION depends on IDE_STANDARD_COMPATIBLE hex "IDE Compatible Selection" default 0x808624db - help + help IDE controller PCI vendor/device ID value setting.
Higher 16-bit is vendor ID, lower 16-bit is device ID. diff --git a/src/mainboard/dmp/vortex86ex/hda_verb.h b/src/mainboard/dmp/vortex86ex/hda_verb.h index 0556315..c85c324 100644 --- a/src/mainboard/dmp/vortex86ex/hda_verb.h +++ b/src/mainboard/dmp/vortex86ex/hda_verb.h @@ -19,9 +19,9 @@
static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 - 0x10714700, // Subsystem ID - 0x0000000f, // Number of jacks + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000f, // Number of jacks
/* ===== HDA Codec Subsystem ID Verb-table ===== */ /* HDA Codec Subsystem ID : 0x10EC0000 */ diff --git a/src/mainboard/dmp/vortex86ex/irq_tables.c b/src/mainboard/dmp/vortex86ex/irq_tables.c index c185c4f..2aa8486 100644 --- a/src/mainboard/dmp/vortex86ex/irq_tables.c +++ b/src/mainboard/dmp/vortex86ex/irq_tables.c @@ -35,7 +35,7 @@ static const struct irq_routing_table intel_irq_routing_table = { * for this structure (including checksum). */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0}, {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0}, {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0}, diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index b08d621..a9e2c89 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -29,12 +29,12 @@ #include "northbridge/dmp/vortex86ex/raminit.c" #include "cpu/dmp/dmp_post_code.h"
-#define DMP_CPUID_SX 0x31504d44 -#define DMP_CPUID_DX 0x32504d44 -#define DMP_CPUID_MX 0x33504d44 -#define DMP_CPUID_DX2 0x34504d44 +#define DMP_CPUID_SX 0x31504d44 +#define DMP_CPUID_DX 0x32504d44 +#define DMP_CPUID_MX 0x33504d44 +#define DMP_CPUID_DX2 0x34504d44 #define DMP_CPUID_MX_PLUS 0x35504d44 -#define DMP_CPUID_EX 0x37504d44 +#define DMP_CPUID_EX 0x37504d44
static u32 get_dmp_id(void) { diff --git a/src/mainboard/eaglelion/5bcm/cmos.layout b/src/mainboard/eaglelion/5bcm/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/eaglelion/5bcm/cmos.layout +++ b/src/mainboard/eaglelion/5bcm/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/eaglelion/5bcm/devicetree.cb b/src/mainboard/eaglelion/5bcm/devicetree.cb index 33f1f90..05ca6b2 100644 --- a/src/mainboard/eaglelion/5bcm/devicetree.cb +++ b/src/mainboard/eaglelion/5bcm/devicetree.cb @@ -2,45 +2,45 @@ chip northbridge/amd/gx1 device domain 0 on device pci 0.0 on end chip southbridge/amd/cs5530 - device pci 12.0 on - chip superio/nsc/pc97317 - device pnp 2e.0 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # FDC - end - device pnp 2e.4 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power Management - io 0x60 = 0xe800 - end - end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA + device pci 12.0 on + chip superio/nsc/pc97317 + device pnp 2e.0 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # FDC + end + device pnp 2e.4 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power Management + io 0x60 = 0xe800 + end + end + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 off end # Audio + device pci 12.4 off end # VGA end end end diff --git a/src/mainboard/eaglelion/5bcm/irq_tables.c b/src/mainboard/eaglelion/5bcm/irq_tables.c index 95f67bc..d1a0315 100644 --- a/src/mainboard/eaglelion/5bcm/irq_tables.c +++ b/src/mainboard/eaglelion/5bcm/irq_tables.c @@ -9,23 +9,23 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x2, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/ecs/p6iwp-fe/devicetree.cb b/src/mainboard/ecs/p6iwp-fe/devicetree.cb index 405b547..541bb2b 100644 --- a/src/mainboard/ecs/p6iwp-fe/devicetree.cb +++ b/src/mainboard/ecs/p6iwp-fe/devicetree.cb @@ -33,50 +33,50 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA bridge - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 - io 0x64 = 0x1200 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 + io 0x64 = 0x1200 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end end device pci 1f.1 on end # IDE device pci 1f.2 on end # USB diff --git a/src/mainboard/ecs/p6iwp-fe/irq_tables.c b/src/mainboard/ecs/p6iwp-fe/irq_tables.c index f9cc97d..1b4c1c4 100644 --- a/src/mainboard/ecs/p6iwp-fe/irq_tables.c +++ b/src/mainboard/ecs/p6iwp-fe/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x7, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, {0x01, (0x04 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c index d024b5d..d5de3ad 100644 --- a/src/mainboard/emulation/qemu-armv7/media.c +++ b/src/mainboard/emulation/qemu-armv7/media.c @@ -23,7 +23,7 @@ static int emu_rom_open(struct cbfs_media *media) { }
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count) { - return (void*)(offset + CONFIG_BOOTBLOCK_BASE); + return (void*)(offset + CONFIG_BOOTBLOCK_BASE); }
static void *emu_rom_unmap(struct cbfs_media *media, const void *address) { diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c index 4a16436..4102662 100644 --- a/src/mainboard/emulation/qemu-armv7/romstage.c +++ b/src/mainboard/emulation/qemu-armv7/romstage.c @@ -19,7 +19,7 @@
void main(void) { - void *entry; + void *entry;
console_init();
diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c index dfe5d0a..b7b83d6 100644 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -34,7 +34,7 @@ static void pl011_uart_tx_flush(void) { #if !defined(__PRE_RAM__)
static const struct console_driver pl011_uart_console __console = { - .init = pl011_init_dev, + .init = pl011_init_dev, .tx_byte = pl011_uart_tx_byte, .tx_flush = pl011_uart_tx_flush, }; diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 0f3e83b..2f10c70 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -9,70 +9,70 @@ Scope(_SB) {
/* Methods called by run-time generated SSDT Processor objects */ Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer - // Arg0 = Processor ID = Local APIC ID - // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return - Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) - // Update the processor id, lapic id, and enable/disable status - Store(Arg0, Index(Local1, 2)) - Store(Arg0, Index(Local1, 3)) - Store(Local0, Index(Local1, 4)) - Return (Local1) + // _MAT method - create an madt apic buffer + // Arg0 = Processor ID = Local APIC ID + // Local0 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Arg0)), Local0) + // Local1 = Buffer (in madt apic form) to return + Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) + // Update the processor id, lapic id, and enable/disable status + Store(Arg0, Index(Local1, 2)) + Store(Arg0, Index(Local1, 3)) + Store(Local0, Index(Local1, 4)) + Return (Local1) } Method(CPST, 1, NotSerialized) { - // _STA method - return ON status of cpu - // Arg0 = Processor ID = Local APIC ID - // Local0 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Arg0)), Local0) - If (Local0) { - Return (0xF) - } Else { - Return (0x0) - } + // _STA method - return ON status of cpu + // Arg0 = Processor ID = Local APIC ID + // Local0 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Arg0)), Local0) + If (Local0) { + Return (0xF) + } Else { + Return (0x0) + } } Method(CPEJ, 2, NotSerialized) { - // _EJ0 method - eject callback - Sleep(200) + // _EJ0 method - eject callback + Sleep(200) }
/* CPU hotplug notify method */ OperationRegion(PRST, SystemIO, 0xaf00, 32) Field(PRST, ByteAcc, NoLock, Preserve) { - PRS, 256 + PRS, 256 } Method(PRSC, 0) { - // Local5 = active cpu bitmap - Store(PRS, Local5) - // Local2 = last read byte from bitmap - Store(Zero, Local2) - // Local0 = Processor ID / APIC ID iterator - Store(Zero, Local0) - While (LLess(Local0, SizeOf(CPON))) { - // Local1 = CPON flag for this cpu - Store(DerefOf(Index(CPON, Local0)), Local1) - If (And(Local0, 0x07)) { - // Shift down previously read bitmap byte - ShiftRight(Local2, 1, Local2) - } Else { - // Read next byte from cpu bitmap - Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2) - } - // Local3 = active state for this cpu - Store(And(Local2, 1), Local3) + // Local5 = active cpu bitmap + Store(PRS, Local5) + // Local2 = last read byte from bitmap + Store(Zero, Local2) + // Local0 = Processor ID / APIC ID iterator + Store(Zero, Local0) + While (LLess(Local0, SizeOf(CPON))) { + // Local1 = CPON flag for this cpu + Store(DerefOf(Index(CPON, Local0)), Local1) + If (And(Local0, 0x07)) { + // Shift down previously read bitmap byte + ShiftRight(Local2, 1, Local2) + } Else { + // Read next byte from cpu bitmap + Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2) + } + // Local3 = active state for this cpu + Store(And(Local2, 1), Local3)
- If (LNotEqual(Local1, Local3)) { - // State change - update CPON with new state - Store(Local3, Index(CPON, Local0)) - // Do CPU notify - If (LEqual(Local3, 1)) { - NTFY(Local0, 1) - } Else { - NTFY(Local0, 3) - } - } - Increment(Local0) - } + If (LNotEqual(Local1, Local3)) { + // State change - update CPON with new state + Store(Local3, Index(CPON, Local0)) + // Do CPU notify + If (LEqual(Local3, 1)) { + NTFY(Local0, 1) + } Else { + NTFY(Local0, 3) + } + } + Increment(Local0) + } } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl index 276321f..4de9cdc 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/dbug.asl @@ -6,21 +6,21 @@ Scope() { /* Debug Output */ OperationRegion(DBG, SystemIO, 0x0402, 0x01) Field(DBG, ByteAcc, NoLock, Preserve) { - DBGB, 8, + DBGB, 8, }
/* Debug method - use this method to send output to the QEMU * BIOS debug port. This method handles strings, integers, * and buffers. For example: DBUG("abc") DBUG(0x123) */ Method(DBUG, 1) { - ToHexString(Arg0, Local0) - ToBuffer(Local0, Local0) - Subtract(SizeOf(Local0), 1, Local1) - Store(Zero, Local2) - While (LLess(Local2, Local1)) { - Store(DerefOf(Index(Local0, Local2)), DBGB) - Increment(Local2) - } - Store(0x0A, DBGB) + ToHexString(Arg0, Local0) + ToBuffer(Local0, Local0) + Subtract(SizeOf(Local0), 1, Local1) + Store(Zero, Local2) + While (LLess(Local2, Local1)) { + Store(DerefOf(Index(Local0, Local2)), DBGB) + Increment(Local2) + } + Store(0x0A, DBGB) } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl index f33e527..6ca27da 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/hpet.asl @@ -4,33 +4,33 @@
Scope(_SB) { Device(HPET) { - Name(_HID, EISAID("PNP0103")) - Name(_UID, 0) - OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400) - Field(HPTM, DWordAcc, Lock, Preserve) { - VEND, 32, - PRD, 32, - } - Method(_STA, 0, NotSerialized) { - Store(VEND, Local0) - Store(PRD, Local1) - ShiftRight(Local0, 16, Local0) - If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) { - Return (0x0) - } - If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) { - Return (0x0) - } - Return (0x0F) - } - Name(_CRS, ResourceTemplate() { -#if 0 /* This makes WinXP BSOD for not yet figured reasons. */ - IRQNoFlags() {2, 8} + Name(_HID, EISAID("PNP0103")) + Name(_UID, 0) + OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400) + Field(HPTM, DWordAcc, Lock, Preserve) { + VEND, 32, + PRD, 32, + } + Method(_STA, 0, NotSerialized) { + Store(VEND, Local0) + Store(PRD, Local1) + ShiftRight(Local0, 16, Local0) + If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) { + Return (0x0) + } + If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) { + Return (0x0) + } + Return (0x0F) + } + Name(_CRS, ResourceTemplate() { +#if 0 /* This makes WinXP BSOD for not yet figured reasons. */ + IRQNoFlags() {2, 8} #endif - Memory32Fixed(ReadOnly, - 0xFED00000, // Address Base - 0x00000400, // Address Length - ) - }) + Memory32Fixed(ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl index 23761db..bdc6bcc 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/isa.asl @@ -2,101 +2,101 @@ Scope(_SB.PCI0.ISA) {
Device(RTC) { - Name(_HID, EisaId("PNP0B00")) - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0070, 0x0070, 0x10, 0x02) - IRQNoFlags() { 8 } - IO(Decode16, 0x0072, 0x0072, 0x02, 0x06) - }) + Name(_HID, EisaId("PNP0B00")) + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x10, 0x02) + IRQNoFlags() { 8 } + IO(Decode16, 0x0072, 0x0072, 0x02, 0x06) + }) }
Device(KBD) { - Name(_HID, EisaId("PNP0303")) - Method(_STA, 0, NotSerialized) { - Return (0x0f) - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO(Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags() { 1 } - }) + Name(_HID, EisaId("PNP0303")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO(Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags() { 1 } + }) }
Device(MOU) { - Name(_HID, EisaId("PNP0F13")) - Method(_STA, 0, NotSerialized) { - Return (0x0f) - } - Name(_CRS, ResourceTemplate() { - IRQNoFlags() { 12 } - }) + Name(_HID, EisaId("PNP0F13")) + Method(_STA, 0, NotSerialized) { + Return (0x0f) + } + Name(_CRS, ResourceTemplate() { + IRQNoFlags() { 12 } + }) }
Device(FDC0) { - Name(_HID, EisaId("PNP0700")) - Method(_STA, 0, NotSerialized) { - Store(FDEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags() { 6 } - DMA(Compatibility, NotBusMaster, Transfer8) { 2 } - }) + Name(_HID, EisaId("PNP0700")) + Method(_STA, 0, NotSerialized) { + Store(FDEN, Local0) + If (LEqual(Local0, 0)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags() { 6 } + DMA(Compatibility, NotBusMaster, Transfer8) { 2 } + }) }
Device(LPT) { - Name(_HID, EisaId("PNP0400")) - Method(_STA, 0, NotSerialized) { - Store(LPEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0378, 0x0378, 0x08, 0x08) - IRQNoFlags() { 7 } - }) + Name(_HID, EisaId("PNP0400")) + Method(_STA, 0, NotSerialized) { + Store(LPEN, Local0) + If (LEqual(Local0, 0)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0378, 0x0378, 0x08, 0x08) + IRQNoFlags() { 7 } + }) }
Device(COM1) { - Name(_HID, EisaId("PNP0501")) - Name(_UID, 0x01) - Method(_STA, 0, NotSerialized) { - Store(CAEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08) - IRQNoFlags() { 4 } - }) + Name(_HID, EisaId("PNP0501")) + Name(_UID, 0x01) + Method(_STA, 0, NotSerialized) { + Store(CAEN, Local0) + If (LEqual(Local0, 0)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08) + IRQNoFlags() { 4 } + }) }
Device(COM2) { - Name(_HID, EisaId("PNP0501")) - Name(_UID, 0x02) - Method(_STA, 0, NotSerialized) { - Store(CBEN, Local0) - If (LEqual(Local0, 0)) { - Return (0x00) - } Else { - Return (0x0F) - } - } - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x02F8, 0x02F8, 0x00, 0x08) - IRQNoFlags() { 3 } - }) + Name(_HID, EisaId("PNP0501")) + Name(_UID, 0x02) + Method(_STA, 0, NotSerialized) { + Store(CBEN, Local0) + If (LEqual(Local0, 0)) { + Return (0x00) + } Else { + Return (0x0F) + } + } + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x02F8, 0x02F8, 0x00, 0x08) + IRQNoFlags() { 3 } + }) } } diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl index 63d1fd5..e1448d9 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/pci-crs.asl @@ -2,93 +2,93 @@ Scope(_SB.PCI0) {
Name(CRES, ResourceTemplate() { - WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x00FF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0100, // Address Length - ,, ) - IO(Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length - ) - WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length - ,, , TypeStatic) - WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0D00, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0xF300, // Address Length - ,, , TypeStatic) - DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000A0000, // Address Range Minimum - 0x000BFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00020000, // Address Length - ,, , AddressRangeMemory, TypeStatic) - DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0xE0000000, // Address Range Minimum - 0xFEBFFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x1EC00000, // Address Length - ,, PW32, AddressRangeMemory, TypeStatic) + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x00FF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0100, // Address Length + ,, ) + IO(Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0D00, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0xF300, // Address Length + ,, , TypeStatic) + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000A0000, // Address Range Minimum + 0x000BFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00020000, // Address Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0xE0000000, // Address Range Minimum + 0xFEBFFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x1EC00000, // Address Length + ,, PW32, AddressRangeMemory, TypeStatic) })
Name(CR64, ResourceTemplate() { - QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x8000000000, // Address Range Minimum - 0xFFFFFFFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x8000000000, // Address Length - ,, PW64, AddressRangeMemory, TypeStatic) + QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x8000000000, // Address Range Minimum + 0xFFFFFFFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x8000000000, // Address Length + ,, PW64, AddressRangeMemory, TypeStatic) })
Method(_CRS, 0) { #if 0 - /* Fields provided by dynamically created ssdt */ - External(P0S, IntObj) - External(P0E, IntObj) - External(P1V, IntObj) - External(P1S, BuffObj) - External(P1E, BuffObj) - External(P1L, BuffObj) + /* Fields provided by dynamically created ssdt */ + External(P0S, IntObj) + External(P0E, IntObj) + External(P1V, IntObj) + External(P1S, BuffObj) + External(P1E, BuffObj) + External(P1L, BuffObj)
- /* fixup 32bit pci io window */ - CreateDWordField(CRES, _SB.PCI0.PW32._MIN, PS32) - CreateDWordField(CRES, _SB.PCI0.PW32._MAX, PE32) - CreateDWordField(CRES, _SB.PCI0.PW32._LEN, PL32) - Store(P0S, PS32) - Store(P0E, PE32) - Store(Add(Subtract(P0E, P0S), 1), PL32) + /* fixup 32bit pci io window */ + CreateDWordField(CRES, _SB.PCI0.PW32._MIN, PS32) + CreateDWordField(CRES, _SB.PCI0.PW32._MAX, PE32) + CreateDWordField(CRES, _SB.PCI0.PW32._LEN, PL32) + Store(P0S, PS32) + Store(P0E, PE32) + Store(Add(Subtract(P0E, P0S), 1), PL32)
- If (LEqual(P1V, Zero)) { - Return (CRES) - } + If (LEqual(P1V, Zero)) { + Return (CRES) + }
- /* fixup 64bit pci io window */ - CreateQWordField(CR64, _SB.PCI0.PW64._MIN, PS64) - CreateQWordField(CR64, _SB.PCI0.PW64._MAX, PE64) - CreateQWordField(CR64, _SB.PCI0.PW64._LEN, PL64) - Store(P1S, PS64) - Store(P1E, PE64) - Store(P1L, PL64) - /* add window and return result */ - ConcatenateResTemplate(CRES, CR64, Local0) - Return (Local0) + /* fixup 64bit pci io window */ + CreateQWordField(CR64, _SB.PCI0.PW64._MIN, PS64) + CreateQWordField(CR64, _SB.PCI0.PW64._MAX, PE64) + CreateQWordField(CR64, _SB.PCI0.PW64._LEN, PL64) + Store(P1S, PS64) + Store(P1E, PE64) + Store(P1L, PL64) + /* add window and return result */ + ConcatenateResTemplate(CRES, CR64, Local0) + Return (Local0) #else - Return (CRES) + Return (CRES) #endif } } diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/emulation/qemu-i440fx/dsdt.asl b/src/mainboard/emulation/qemu-i440fx/dsdt.asl index e63d10f..dd37a18 100644 --- a/src/mainboard/emulation/qemu-i440fx/dsdt.asl +++ b/src/mainboard/emulation/qemu-i440fx/dsdt.asl @@ -18,12 +18,12 @@ */
DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "CORE", // OEMID - "COREBOOT", // TABLE ID - 0x1 // OEM Revision + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x1 // OEM Revision ) {
@@ -35,11 +35,11 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - } + Device(PCI0) { + Name(_HID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + } }
#include "acpi/pci-crs.asl" @@ -51,26 +51,26 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - Device(VGA) { - Name(_ADR, 0x00020000) - OperationRegion(PCIC, PCI_Config, Zero, 0x4) - Field(PCIC, DWordAcc, NoLock, Preserve) { - VEND, 32 - } - Method(_S1D, 0, NotSerialized) { - Return (0x00) - } - Method(_S2D, 0, NotSerialized) { - Return (0x00) - } - Method(_S3D, 0, NotSerialized) { - If (LEqual(VEND, 0x1001b36)) { - Return (0x03) // QXL - } Else { - Return (0x00) - } - } - } + Device(VGA) { + Name(_ADR, 0x00020000) + OperationRegion(PCIC, PCI_Config, Zero, 0x4) + Field(PCIC, DWordAcc, NoLock, Preserve) { + VEND, 32 + } + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + If (LEqual(VEND, 0x1001b36)) { + Return (0x03) // QXL + } Else { + Return (0x00) + } + } + } }
@@ -79,10 +79,10 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - Device(PX13) { - Name(_ADR, 0x00010003) - OperationRegion(P13C, PCI_Config, 0x00, 0xff) - } + Device(PX13) { + Name(_ADR, 0x00010003) + OperationRegion(P13C, PCI_Config, 0x00, 0xff) + } }
@@ -91,25 +91,25 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - Device(ISA) { - Name(_ADR, 0x00010000) - - /* PIIX PCI to ISA irq remapping */ - OperationRegion(P40C, PCI_Config, 0x60, 0x04) - - /* enable bits */ - Field(_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) { - Offset(0x5f), - , 7, - LPEN, 1, // LPT - Offset(0x67), - , 3, - CAEN, 1, // COM1 - , 3, - CBEN, 1, // COM2 - } - Name(FDEN, 1) - } + Device(ISA) { + Name(_ADR, 0x00010000) + + /* PIIX PCI to ISA irq remapping */ + OperationRegion(P40C, PCI_Config, 0x60, 0x04) + + /* enable bits */ + Field(_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) { + Offset(0x5f), + , 7, + LPEN, 1, // LPT + Offset(0x67), + , 3, + CAEN, 1, // COM1 + , 3, + CBEN, 1, // COM2 + } + Name(FDEN, 1) + } }
#include "acpi/isa.asl" @@ -120,43 +120,43 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - OperationRegion(PCST, SystemIO, 0xae00, 0x08) - Field(PCST, DWordAcc, NoLock, WriteAsZeros) { - PCIU, 32, - PCID, 32, - } - - OperationRegion(SEJ, SystemIO, 0xae08, 0x04) - Field(SEJ, DWordAcc, NoLock, WriteAsZeros) { - B0EJ, 32, - } - - /* Methods called by bulk generated PCI devices below */ - - /* Methods called by hotplug devices */ - Method(PCEJ, 1, NotSerialized) { - // _EJ0 method - eject callback - Store(ShiftLeft(1, Arg0), B0EJ) - Return (0x0) - } - - /* Hotplug notification method supplied by SSDT */ - External(_SB.PCI0.PCNT, MethodObj) - - /* PCI hotplug notify method */ - Method(PCNF, 0) { - // Local0 = iterator - Store(Zero, Local0) - While (LLess(Local0, 31)) { - Increment(Local0) - If (And(PCIU, ShiftLeft(1, Local0))) { - PCNT(Local0, 1) - } - If (And(PCID, ShiftLeft(1, Local0))) { - PCNT(Local0, 3) - } - } - } + OperationRegion(PCST, SystemIO, 0xae00, 0x08) + Field(PCST, DWordAcc, NoLock, WriteAsZeros) { + PCIU, 32, + PCID, 32, + } + + OperationRegion(SEJ, SystemIO, 0xae08, 0x04) + Field(SEJ, DWordAcc, NoLock, WriteAsZeros) { + B0EJ, 32, + } + + /* Methods called by bulk generated PCI devices below */ + + /* Methods called by hotplug devices */ + Method(PCEJ, 1, NotSerialized) { + // _EJ0 method - eject callback + Store(ShiftLeft(1, Arg0), B0EJ) + Return (0x0) + } + + /* Hotplug notification method supplied by SSDT */ + External(_SB.PCI0.PCNT, MethodObj) + + /* PCI hotplug notify method */ + Method(PCNF, 0) { + // Local0 = iterator + Store(Zero, Local0) + While (LLess(Local0, 31)) { + Increment(Local0) + If (And(PCIU, ShiftLeft(1, Local0))) { + PCNT(Local0, 1) + } + If (And(PCID, ShiftLeft(1, Local0))) { + PCNT(Local0, 3) + } + } + } }
@@ -165,12 +165,12 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB) { - Scope(PCI0) { - Name(_PRT, Package() { - /* PCI IRQ routing table, example from ACPI 2.0a specification, - section 6.2.8.1 */ - /* Note: we provide the same info as the PCI routing - table of the Bochs BIOS */ + Scope(PCI0) { + Name(_PRT, Package() { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */
#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \ Package() { nr##ffff, 0, lnk0, 0 }, \ @@ -183,112 +183,112 @@ DefinitionBlock ( #define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA) #define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
- prt_slot0(0x0000), - /* Device 1 is power mgmt device, and can only use irq 9 */ - prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD), - prt_slot2(0x0002), - prt_slot3(0x0003), - prt_slot0(0x0004), - prt_slot1(0x0005), - prt_slot2(0x0006), - prt_slot3(0x0007), - prt_slot0(0x0008), - prt_slot1(0x0009), - prt_slot2(0x000a), - prt_slot3(0x000b), - prt_slot0(0x000c), - prt_slot1(0x000d), - prt_slot2(0x000e), - prt_slot3(0x000f), - prt_slot0(0x0010), - prt_slot1(0x0011), - prt_slot2(0x0012), - prt_slot3(0x0013), - prt_slot0(0x0014), - prt_slot1(0x0015), - prt_slot2(0x0016), - prt_slot3(0x0017), - prt_slot0(0x0018), - prt_slot1(0x0019), - prt_slot2(0x001a), - prt_slot3(0x001b), - prt_slot0(0x001c), - prt_slot1(0x001d), - prt_slot2(0x001e), - prt_slot3(0x001f), - }) - } - - Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { - PRQ0, 8, - PRQ1, 8, - PRQ2, 8, - PRQ3, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, NotSerialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - If (LLess(Arg0, 0x80)) { - Store(Arg0, PRRI) - } - Return (PRR0) - } - -#define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQ0) - define_link(LNKB, 1, PRQ1) - define_link(LNKC, 2, PRQ2) - define_link(LNKD, 3, PRQ3) - - Device(LNKS) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - Name(_PRS, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 9 } - }) - - // The SCI cannot be disabled and is always attached to GSI 9, - // so these are no-ops. We only need this link to override the - // polarity to active high and match the content of the MADT. - Method(_STA, 0, NotSerialized) { Return (0x0b) } - Method(_DIS, 0, NotSerialized) { } - Method(_CRS, 0, NotSerialized) { Return (_PRS) } - Method(_SRS, 1, NotSerialized) { } - } + prt_slot0(0x0000), + /* Device 1 is power mgmt device, and can only use irq 9 */ + prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD), + prt_slot2(0x0002), + prt_slot3(0x0003), + prt_slot0(0x0004), + prt_slot1(0x0005), + prt_slot2(0x0006), + prt_slot3(0x0007), + prt_slot0(0x0008), + prt_slot1(0x0009), + prt_slot2(0x000a), + prt_slot3(0x000b), + prt_slot0(0x000c), + prt_slot1(0x000d), + prt_slot2(0x000e), + prt_slot3(0x000f), + prt_slot0(0x0010), + prt_slot1(0x0011), + prt_slot2(0x0012), + prt_slot3(0x0013), + prt_slot0(0x0014), + prt_slot1(0x0015), + prt_slot2(0x0016), + prt_slot3(0x0017), + prt_slot0(0x0018), + prt_slot1(0x0019), + prt_slot2(0x001a), + prt_slot3(0x001b), + prt_slot0(0x001c), + prt_slot1(0x001d), + prt_slot2(0x001e), + prt_slot3(0x001f), + }) + } + + Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, NotSerialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + If (LLess(Arg0, 0x80)) { + Store(Arg0, PRRI) + } + Return (PRR0) + } + +#define define_link(link, uid, reg) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQ0) + define_link(LNKB, 1, PRQ1) + define_link(LNKC, 2, PRQ2) + define_link(LNKD, 3, PRQ3) + + Device(LNKS) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Name(_PRS, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 9 } + }) + + // The SCI cannot be disabled and is always attached to GSI 9, + // so these are no-ops. We only need this link to override the + // polarity to active high and match the content of the MADT. + Method(_STA, 0, NotSerialized) { Return (0x0b) } + Method(_DIS, 0, NotSerialized) { } + Method(_CRS, 0, NotSerialized) { Return (_PRS) } + Method(_SRS, 1, NotSerialized) { } + } }
#if 0 @@ -301,47 +301,47 @@ DefinitionBlock ( ****************************************************************/
Scope(_GPE) { - Name(_HID, "ACPI0006") + Name(_HID, "ACPI0006")
- Method(_L00) { - } - Method(_E01) { + Method(_L00) { + } + Method(_E01) { #if 0 - // PCI hotplug event - _SB.PCI0.PCNF() + // PCI hotplug event + _SB.PCI0.PCNF() #endif - } - Method(_E02) { + } + Method(_E02) { #if 0 - // CPU hotplug event - _SB.PRSC() + // CPU hotplug event + _SB.PRSC() #endif - } - Method(_L03) { - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } } } diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 085f2a9..ead1189 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -25,7 +25,7 @@ #include "fw_cfg.h" #include "fw_cfg_if.h"
-#define FW_CFG_PORT_CTL 0x0510 +#define FW_CFG_PORT_CTL 0x0510 #define FW_CFG_PORT_DATA 0x0511
static unsigned char fw_cfg_detected = 0xff; @@ -40,7 +40,7 @@ static int fw_cfg_present(void) fw_cfg_get(FW_CFG_SIGNATURE, sig, sizeof(sig)); fw_cfg_detected = (memcmp(sig, qsig, 4) == 0) ? 1 : 0; printk(BIOS_INFO, "QEMU: firmware config interface %s\n", - fw_cfg_detected ? "detected" : "not found"); + fw_cfg_detected ? "detected" : "not found"); } return fw_cfg_detected; } @@ -66,10 +66,10 @@ static void fw_cfg_init_file(void) fw_cfg_get(FW_CFG_FILE_DIR, fw_files, size); fw_files->count = swab32(fw_files->count); for (i = 0; i < count; i++) { - fw_files->f[i].size = swab32(fw_files->f[i].size); + fw_files->f[i].size = swab32(fw_files->f[i].size); fw_files->f[i].select = swab16(fw_files->f[i].select); - printk(BIOS_DEBUG, "QEMU: %s [size=%d]\n", - fw_files->f[i].name, fw_files->f[i].size); + printk(BIOS_DEBUG, "QEMU: %s [size=%d]\n", + fw_files->f[i].name, fw_files->f[i].size); } }
@@ -192,7 +192,7 @@ struct BiosLinkerLoaderEntry { typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
enum { - BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, + BIOS_LINKER_LOADER_COMMAND_ALLOCATE = 0x1, BIOS_LINKER_LOADER_COMMAND_ADD_POINTER = 0x2, BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3, }; @@ -227,7 +227,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) case BIOS_LINKER_LOADER_COMMAND_ALLOCATE: current = ALIGN(current, s[i].alloc.align); printk(BIOS_DEBUG, "QEMU: loading "%s" to 0x%lx\n", - s[i].alloc.file, current); + s[i].alloc.file, current);
rc = fw_cfg_check_file(s[i].alloc.file); if (rc < 0) @@ -268,7 +268,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) * would simply not fit in there ... */ printk(BIOS_DEBUG, "QEMU: acpi: unimplemented ptr size %d\n", - s[i].pointer.size); + s[i].pointer.size); goto err; } break; @@ -287,12 +287,12 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) ptr4 = (uint32_t*)(addrs[dst] + s[i].cksum.offset); *ptr4 = 0; *ptr4 = acpi_checksum((void *)(addrs[dst] + s[i].cksum.start), - s[i].cksum.length); + s[i].cksum.length); break;
default: printk(BIOS_DEBUG, "QEMU: acpi: unknown script cmd 0x%x @ %p\n", - s[i].command, s+i); + s[i].command, s+i); goto err; }; } @@ -310,7 +310,7 @@ err: }
/* ---------------------------------------------------------------------- */ -/* pick up smbios information from fw_cfg */ +/* pick up smbios information from fw_cfg */
static const char *type1_manufacturer; static const char *type1_product_name; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 2d27245..afb7433 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -3,52 +3,52 @@ * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h */
-#define FW_CFG_SIGNATURE 0x00 -#define FW_CFG_ID 0x01 -#define FW_CFG_UUID 0x02 -#define FW_CFG_RAM_SIZE 0x03 -#define FW_CFG_NOGRAPHIC 0x04 -#define FW_CFG_NB_CPUS 0x05 -#define FW_CFG_MACHINE_ID 0x06 -#define FW_CFG_KERNEL_ADDR 0x07 -#define FW_CFG_KERNEL_SIZE 0x08 -#define FW_CFG_KERNEL_CMDLINE 0x09 -#define FW_CFG_INITRD_ADDR 0x0a -#define FW_CFG_INITRD_SIZE 0x0b -#define FW_CFG_BOOT_DEVICE 0x0c -#define FW_CFG_NUMA 0x0d -#define FW_CFG_BOOT_MENU 0x0e -#define FW_CFG_MAX_CPUS 0x0f -#define FW_CFG_KERNEL_ENTRY 0x10 -#define FW_CFG_KERNEL_DATA 0x11 -#define FW_CFG_INITRD_DATA 0x12 -#define FW_CFG_CMDLINE_ADDR 0x13 -#define FW_CFG_CMDLINE_SIZE 0x14 -#define FW_CFG_CMDLINE_DATA 0x15 -#define FW_CFG_SETUP_ADDR 0x16 -#define FW_CFG_SETUP_SIZE 0x17 -#define FW_CFG_SETUP_DATA 0x18 -#define FW_CFG_FILE_DIR 0x19 +#define FW_CFG_SIGNATURE 0x00 +#define FW_CFG_ID 0x01 +#define FW_CFG_UUID 0x02 +#define FW_CFG_RAM_SIZE 0x03 +#define FW_CFG_NOGRAPHIC 0x04 +#define FW_CFG_NB_CPUS 0x05 +#define FW_CFG_MACHINE_ID 0x06 +#define FW_CFG_KERNEL_ADDR 0x07 +#define FW_CFG_KERNEL_SIZE 0x08 +#define FW_CFG_KERNEL_CMDLINE 0x09 +#define FW_CFG_INITRD_ADDR 0x0a +#define FW_CFG_INITRD_SIZE 0x0b +#define FW_CFG_BOOT_DEVICE 0x0c +#define FW_CFG_NUMA 0x0d +#define FW_CFG_BOOT_MENU 0x0e +#define FW_CFG_MAX_CPUS 0x0f +#define FW_CFG_KERNEL_ENTRY 0x10 +#define FW_CFG_KERNEL_DATA 0x11 +#define FW_CFG_INITRD_DATA 0x12 +#define FW_CFG_CMDLINE_ADDR 0x13 +#define FW_CFG_CMDLINE_SIZE 0x14 +#define FW_CFG_CMDLINE_DATA 0x15 +#define FW_CFG_SETUP_ADDR 0x16 +#define FW_CFG_SETUP_SIZE 0x17 +#define FW_CFG_SETUP_DATA 0x18 +#define FW_CFG_FILE_DIR 0x19
-#define FW_CFG_FILE_FIRST 0x20 -#define FW_CFG_FILE_SLOTS 0x10 -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS) +#define FW_CFG_FILE_FIRST 0x20 +#define FW_CFG_FILE_SLOTS 0x10 +#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
-#define FW_CFG_WRITE_CHANNEL 0x4000 -#define FW_CFG_ARCH_LOCAL 0x8000 -#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) +#define FW_CFG_WRITE_CHANNEL 0x4000 +#define FW_CFG_ARCH_LOCAL 0x8000 +#define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL)
-#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) -#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) -#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) -#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) -#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) +#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) +#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) +#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) +#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) +#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
-#define FW_CFG_INVALID 0xffff +#define FW_CFG_INVALID 0xffff
typedef struct FWCfgFile { - uint32_t size; /* file size */ - uint16_t select; /* write this to 0x510 to read it */ + uint32_t size; /* file size */ + uint16_t select; /* write this to 0x510 to read it */ uint16_t reserved; char name[56]; } FWCfgFile; diff --git a/src/mainboard/emulation/qemu-i440fx/irq_tables.c b/src/mainboard/emulation/qemu-i440fx/irq_tables.c index 21eeabf..c46b745 100644 --- a/src/mainboard/emulation/qemu-i440fx/irq_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/irq_tables.c @@ -9,18 +9,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x01<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x7000, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x7, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0x0def8}}, 0x0, 0x0}, {0x00,(0x02<<3)|0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0x0def8}}, 0x1, 0x0}, {0x00,(0x03<<3)|0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0x0def8}}, 0x2, 0x0}, @@ -31,5 +31,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index 90ad2db..e69564d 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -52,10 +52,10 @@ static void qemu_nb_init(device_t dev)
static struct device_operations nb_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = qemu_nb_init, - .ops_pci = 0, + .init = qemu_nb_init, + .ops_pci = 0, };
static const struct pci_driver nb_driver __pci_driver = { diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 0f8c0c2..8620945 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -30,14 +30,14 @@ static unsigned long qemu_get_high_memory_size(void) }
static void qemu_reserve_ports(struct device *dev, unsigned int idx, - unsigned int base, unsigned int size, - const char *name) + unsigned int base, unsigned int size, + const char *name) { unsigned int end = base + size -1; struct resource *res;
printk(BIOS_DEBUG, "QEMU: reserve ioports 0x%04x-0x%04x [%s]\n", - base, end, name); + base, end, name); res = new_resource(dev, idx); res->base = base; res->size = size; @@ -73,20 +73,20 @@ static void cpu_pci_domain_read_resources(struct device *dev) switch (list[i].type) { case 1: /* ram */ printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n", - list[i].address, list[i].length); + list[i].address, list[i].length); if (list[i].address == 0) { tomk = list[i].length / 1024; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); } else { ram_resource(dev, idx++, - list[i].address / 1024, - list[i].length / 1024); + list[i].address / 1024, + list[i].length / 1024); } break; case 2: /* reserved */ printk(BIOS_DEBUG, "QEMU: e820/res: 0x%08llx +0x%08llx\n", - list[i].address, list[i].length); + list[i].address, list[i].length); res = new_resource(dev, idx++); res->base = list[i].address; res->size = list[i].length; @@ -268,10 +268,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, };
static void northbridge_enable(struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 4e79b2c..5f2456f 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -103,7 +103,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ - /* then FIRMWARE_CTRL must be zero. */ + /* then FIRMWARE_CTRL must be zero. */ fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0;
@@ -212,7 +212,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - reg & 0xf0000000, 0x0, 0x0, 255); + reg & 0xf0000000, 0x0, 0x0, 255); return current; }
diff --git a/src/mainboard/emulation/qemu-q35/dsdt.asl b/src/mainboard/emulation/qemu-q35/dsdt.asl index 0e8da7b..008b8fc 100644 --- a/src/mainboard/emulation/qemu-q35/dsdt.asl +++ b/src/mainboard/emulation/qemu-q35/dsdt.asl @@ -18,28 +18,28 @@ */ /* * Copyright (c) 2010 Isaku Yamahata - * yamahata at valinux co jp + * yamahata at valinux co jp * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset. */
DefinitionBlock ( - "dsdt.aml", // Output Filename - "DSDT", // Signature - 0x01, // DSDT Compliance Revision - "CORE", // OEMID - "COREBOOT", // TABLE ID - 0x2 // OEM Revision + "dsdt.aml", // Output Filename + "DSDT", // Signature + 0x01, // DSDT Compliance Revision + "CORE", // OEMID + "COREBOOT", // TABLE ID + 0x2 // OEM Revision ) {
#include "../qemu-i440fx/acpi/dbug.asl"
Scope(_SB) { - OperationRegion(PCST, SystemIO, 0xae00, 0x0c) - OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) - Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { - PCIB, 8, - } + OperationRegion(PCST, SystemIO, 0xae00, 0x0c) + OperationRegion(PCSB, SystemIO, 0xae0c, 0x01) + Field(PCSB, AnyAcc, NoLock, WriteAsZeros) { + PCIB, 8, + } }
@@ -48,67 +48,67 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A08")) - Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - - // _OSC: based on sample of ACPI3.0b spec - Name(SUPP, 0) // PCI _OSC Support Field value - Name(CTRL, 0) // PCI _OSC Control Field value - Method(_OSC, 4) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 0, CDW1) - - // Check for proper UUID - If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - // Create DWORD-addressable fields from the Capabilities Buffer - CreateDWordField(Arg3, 4, CDW2) - CreateDWordField(Arg3, 8, CDW3) - - // Save Capabilities DWORD2 & 3 - Store(CDW2, SUPP) - Store(CDW3, CTRL) - - // Always allow native PME, AER (no dependencies) - // Never allow SHPC (no SHPC controller in this system) - And(CTRL, 0x1D, CTRL) + Device(PCI0) { + Name(_HID, EisaId("PNP0A08")) + Name(_CID, EisaId("PNP0A03")) + Name(_ADR, 0x00) + Name(_UID, 1) + + // _OSC: based on sample of ACPI3.0b spec + Name(SUPP, 0) // PCI _OSC Support Field value + Name(CTRL, 0) // PCI _OSC Control Field value + Method(_OSC, 4) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 0, CDW1) + + // Check for proper UUID + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + // Create DWORD-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3, 4, CDW2) + CreateDWordField(Arg3, 8, CDW3) + + // Save Capabilities DWORD2 & 3 + Store(CDW2, SUPP) + Store(CDW3, CTRL) + + // Always allow native PME, AER (no dependencies) + // Never allow SHPC (no SHPC controller in this system) + And(CTRL, 0x1D, CTRL)
#if 0 // For now, nothing to do - If (Not(And(CDW1, 1))) { // Query flag clear? - // Disable GPEs for features granted native control. - If (And(CTRL, 0x01)) { // Hot plug control granted? - Store(0, HPCE) // clear the hot plug SCI enable bit - Store(1, HPCS) // clear the hot plug SCI status bit - } - If (And(CTRL, 0x04)) { // PME control granted? - Store(0, PMCE) // clear the PME SCI enable bit - Store(1, PMCS) // clear the PME SCI status bit - } - If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? - // Set status to not restore PCI Express cap structure - // upon resume from S3 - Store(1, S3CR) - } - } + If (Not(And(CDW1, 1))) { // Query flag clear? + // Disable GPEs for features granted native control. + If (And(CTRL, 0x01)) { // Hot plug control granted? + Store(0, HPCE) // clear the hot plug SCI enable bit + Store(1, HPCS) // clear the hot plug SCI status bit + } + If (And(CTRL, 0x04)) { // PME control granted? + Store(0, PMCE) // clear the PME SCI enable bit + Store(1, PMCS) // clear the PME SCI status bit + } + If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure? + // Set status to not restore PCI Express cap structure + // upon resume from S3 + Store(1, S3CR) + } + } #endif - If (LNotEqual(Arg1, One)) { - // Unknown revision - Or(CDW1, 0x08, CDW1) - } - If (LNotEqual(CDW3, CTRL)) { - // Capabilities bits were masked - Or(CDW1, 0x10, CDW1) - } - // Update DWORD3 in the buffer - Store(CTRL, CDW3) - } Else { - Or(CDW1, 4, CDW1) // Unrecognized UUID - } - Return (Arg3) - } - } + If (LNotEqual(Arg1, One)) { + // Unknown revision + Or(CDW1, 0x08, CDW1) + } + If (LNotEqual(CDW3, CTRL)) { + // Capabilities bits were masked + Or(CDW1, 0x10, CDW1) + } + // Update DWORD3 in the buffer + Store(CTRL, CDW3) + } Else { + Or(CDW1, 4, CDW1) // Unrecognized UUID + } + Return (Arg3) + } + } }
#include "../qemu-i440fx/acpi/pci-crs.asl" @@ -120,18 +120,18 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - Device(VGA) { - Name(_ADR, 0x00010000) - Method(_S1D, 0, NotSerialized) { - Return (0x00) - } - Method(_S2D, 0, NotSerialized) { - Return (0x00) - } - Method(_S3D, 0, NotSerialized) { - Return (0x00) - } - } + Device(VGA) { + Name(_ADR, 0x00010000) + Method(_S1D, 0, NotSerialized) { + Return (0x00) + } + Method(_S2D, 0, NotSerialized) { + Return (0x00) + } + Method(_S3D, 0, NotSerialized) { + Return (0x00) + } + } }
@@ -140,33 +140,33 @@ DefinitionBlock ( ****************************************************************/
Scope(_SB.PCI0) { - /* PCI D31:f0 LPC ISA bridge */ - Device(ISA) { - /* PCI D31:f0 */ - Name(_ADR, 0x001f0000) - - /* ICH9 PCI to ISA irq remapping */ - OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) - - OperationRegion(LPCD, PCI_Config, 0x80, 0x2) - Field(LPCD, AnyAcc, NoLock, Preserve) { - COMA, 3, - , 1, - COMB, 3, - - Offset(0x01), - LPTD, 2, - , 2, - FDCD, 2 - } - OperationRegion(LPCE, PCI_Config, 0x82, 0x2) - Field(LPCE, AnyAcc, NoLock, Preserve) { - CAEN, 1, - CBEN, 1, - LPEN, 1, - FDEN, 1 - } - } + /* PCI D31:f0 LPC ISA bridge */ + Device(ISA) { + /* PCI D31:f0 */ + Name(_ADR, 0x001f0000) + + /* ICH9 PCI to ISA irq remapping */ + OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) + + OperationRegion(LPCD, PCI_Config, 0x80, 0x2) + Field(LPCD, AnyAcc, NoLock, Preserve) { + COMA, 3, + , 1, + COMB, 3, + + Offset(0x01), + LPTD, 2, + , 2, + FDCD, 2 + } + OperationRegion(LPCE, PCI_Config, 0x82, 0x2) + Field(LPCE, AnyAcc, NoLock, Preserve) { + CAEN, 1, + CBEN, 1, + LPEN, 1, + FDEN, 1 + } + } }
#include "../qemu-i440fx/acpi/isa.asl" @@ -179,15 +179,15 @@ DefinitionBlock ( /* Zero => PIC mode, One => APIC Mode */ Name(\PICF, Zero) Method(_PIC, 1, NotSerialized) { - Store(Arg0, \PICF) + Store(Arg0, \PICF) }
Scope(_SB) { - Scope(PCI0) { + Scope(PCI0) { #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \ - Package() { nr##ffff, 0, lnk0, 0 }, \ - Package() { nr##ffff, 1, lnk1, 0 }, \ - Package() { nr##ffff, 2, lnk2, 0 }, \ + Package() { nr##ffff, 0, lnk0, 0 }, \ + Package() { nr##ffff, 1, lnk1, 0 }, \ + Package() { nr##ffff, 2, lnk2, 0 }, \ Package() { nr##ffff, 3, lnk3, 0 }
#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD) @@ -200,51 +200,51 @@ DefinitionBlock ( #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF) #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
- Name(PRTP, Package() { - prt_slot_lnkE(0x0000), - prt_slot_lnkF(0x0001), - prt_slot_lnkG(0x0002), - prt_slot_lnkH(0x0003), - prt_slot_lnkE(0x0004), - prt_slot_lnkF(0x0005), - prt_slot_lnkG(0x0006), - prt_slot_lnkH(0x0007), - prt_slot_lnkE(0x0008), - prt_slot_lnkF(0x0009), - prt_slot_lnkG(0x000a), - prt_slot_lnkH(0x000b), - prt_slot_lnkE(0x000c), - prt_slot_lnkF(0x000d), - prt_slot_lnkG(0x000e), - prt_slot_lnkH(0x000f), - prt_slot_lnkE(0x0010), - prt_slot_lnkF(0x0011), - prt_slot_lnkG(0x0012), - prt_slot_lnkH(0x0013), - prt_slot_lnkE(0x0014), - prt_slot_lnkF(0x0015), - prt_slot_lnkG(0x0016), - prt_slot_lnkH(0x0017), - prt_slot_lnkE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31 - see the default value of D<N>IR */ - prt_slot_lnkA(0x0019), - prt_slot_lnkA(0x001a), - prt_slot_lnkA(0x001b), - prt_slot_lnkA(0x001c), - prt_slot_lnkA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_lnkE(0x001e), - - prt_slot_lnkA(0x001f) - }) + Name(PRTP, Package() { + prt_slot_lnkE(0x0000), + prt_slot_lnkF(0x0001), + prt_slot_lnkG(0x0002), + prt_slot_lnkH(0x0003), + prt_slot_lnkE(0x0004), + prt_slot_lnkF(0x0005), + prt_slot_lnkG(0x0006), + prt_slot_lnkH(0x0007), + prt_slot_lnkE(0x0008), + prt_slot_lnkF(0x0009), + prt_slot_lnkG(0x000a), + prt_slot_lnkH(0x000b), + prt_slot_lnkE(0x000c), + prt_slot_lnkF(0x000d), + prt_slot_lnkG(0x000e), + prt_slot_lnkH(0x000f), + prt_slot_lnkE(0x0010), + prt_slot_lnkF(0x0011), + prt_slot_lnkG(0x0012), + prt_slot_lnkH(0x0013), + prt_slot_lnkE(0x0014), + prt_slot_lnkF(0x0015), + prt_slot_lnkG(0x0016), + prt_slot_lnkH(0x0017), + prt_slot_lnkE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31 + see the default value of D<N>IR */ + prt_slot_lnkA(0x0019), + prt_slot_lnkA(0x001a), + prt_slot_lnkA(0x001b), + prt_slot_lnkA(0x001c), + prt_slot_lnkA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_lnkE(0x001e), + + prt_slot_lnkA(0x001f) + })
#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \ - Package() { nr##ffff, 0, gsi0, 0 }, \ - Package() { nr##ffff, 1, gsi1, 0 }, \ - Package() { nr##ffff, 2, gsi2, 0 }, \ + Package() { nr##ffff, 0, gsi0, 0 }, \ + Package() { nr##ffff, 1, gsi1, 0 }, \ + Package() { nr##ffff, 2, gsi2, 0 }, \ Package() { nr##ffff, 3, gsi3, 0 }
#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID) @@ -257,149 +257,149 @@ DefinitionBlock ( #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF) #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
- Name(PRTA, Package() { - prt_slot_gsiE(0x0000), - prt_slot_gsiF(0x0001), - prt_slot_gsiG(0x0002), - prt_slot_gsiH(0x0003), - prt_slot_gsiE(0x0004), - prt_slot_gsiF(0x0005), - prt_slot_gsiG(0x0006), - prt_slot_gsiH(0x0007), - prt_slot_gsiE(0x0008), - prt_slot_gsiF(0x0009), - prt_slot_gsiG(0x000a), - prt_slot_gsiH(0x000b), - prt_slot_gsiE(0x000c), - prt_slot_gsiF(0x000d), - prt_slot_gsiG(0x000e), - prt_slot_gsiH(0x000f), - prt_slot_gsiE(0x0010), - prt_slot_gsiF(0x0011), - prt_slot_gsiG(0x0012), - prt_slot_gsiH(0x0013), - prt_slot_gsiE(0x0014), - prt_slot_gsiF(0x0015), - prt_slot_gsiG(0x0016), - prt_slot_gsiH(0x0017), - prt_slot_gsiE(0x0018), - - /* INTA -> PIRQA for slot 25 - 31, but 30 - see the default value of D<N>IR */ - prt_slot_gsiA(0x0019), - prt_slot_gsiA(0x001a), - prt_slot_gsiA(0x001b), - prt_slot_gsiA(0x001c), - prt_slot_gsiA(0x001d), - - /* PCIe->PCI bridge. use PIRQ[E-H] */ - prt_slot_gsiE(0x001e), - - prt_slot_gsiA(0x001f) - }) - - Method(_PRT, 0, NotSerialized) { - /* PCI IRQ routing table, example from ACPI 2.0a specification, - section 6.2.8.1 */ - /* Note: we provide the same info as the PCI routing - table of the Bochs BIOS */ - If (LEqual(\PICF, Zero)) { - Return (PRTP) - } Else { - Return (PRTA) - } - } - } - - Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { - PRQA, 8, - PRQB, 8, - PRQC, 8, - PRQD, 8, - - Offset(0x08), - PRQE, 8, - PRQF, 8, - PRQG, 8, - PRQH, 8 - } - - Method(IQST, 1, NotSerialized) { - // _STA method - get status - If (And(0x80, Arg0)) { - Return (0x09) - } - Return (0x0B) - } - Method(IQCR, 1, NotSerialized) { - // _CRS method - get current settings - Name(PRR0, ResourceTemplate() { - Interrupt(, Level, ActiveHigh, Shared) { 0 } - }) - CreateDWordField(PRR0, 0x05, PRRI) - Store(And(Arg0, 0x0F), PRRI) - Return (PRR0) - } - -#define define_link(link, uid, reg) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - 5, 10, 11 \ - } \ - }) \ - Method(_STA, 0, NotSerialized) { \ - Return (IQST(reg)) \ - } \ - Method(_DIS, 0, NotSerialized) { \ - Or(reg, 0x80, reg) \ - } \ - Method(_CRS, 0, NotSerialized) { \ - Return (IQCR(reg)) \ - } \ - Method(_SRS, 1, NotSerialized) { \ - CreateDWordField(Arg0, 0x05, PRRI) \ - Store(PRRI, reg) \ - } \ - } - - define_link(LNKA, 0, PRQA) - define_link(LNKB, 1, PRQB) - define_link(LNKC, 2, PRQC) - define_link(LNKD, 3, PRQD) - define_link(LNKE, 4, PRQE) - define_link(LNKF, 5, PRQF) - define_link(LNKG, 6, PRQG) - define_link(LNKH, 7, PRQH) - -#define define_gsi_link(link, uid, gsi) \ - Device(link) { \ - Name(_HID, EISAID("PNP0C0F")) \ - Name(_UID, uid) \ - Name(_PRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Name(_CRS, ResourceTemplate() { \ - Interrupt(, Level, ActiveHigh, Shared) { \ - gsi \ - } \ - }) \ - Method(_SRS, 1, NotSerialized) { \ - } \ - } - - define_gsi_link(GSIA, 0, 0x10) - define_gsi_link(GSIB, 0, 0x11) - define_gsi_link(GSIC, 0, 0x12) - define_gsi_link(GSID, 0, 0x13) - define_gsi_link(GSIE, 0, 0x14) - define_gsi_link(GSIF, 0, 0x15) - define_gsi_link(GSIG, 0, 0x16) - define_gsi_link(GSIH, 0, 0x17) + Name(PRTA, Package() { + prt_slot_gsiE(0x0000), + prt_slot_gsiF(0x0001), + prt_slot_gsiG(0x0002), + prt_slot_gsiH(0x0003), + prt_slot_gsiE(0x0004), + prt_slot_gsiF(0x0005), + prt_slot_gsiG(0x0006), + prt_slot_gsiH(0x0007), + prt_slot_gsiE(0x0008), + prt_slot_gsiF(0x0009), + prt_slot_gsiG(0x000a), + prt_slot_gsiH(0x000b), + prt_slot_gsiE(0x000c), + prt_slot_gsiF(0x000d), + prt_slot_gsiG(0x000e), + prt_slot_gsiH(0x000f), + prt_slot_gsiE(0x0010), + prt_slot_gsiF(0x0011), + prt_slot_gsiG(0x0012), + prt_slot_gsiH(0x0013), + prt_slot_gsiE(0x0014), + prt_slot_gsiF(0x0015), + prt_slot_gsiG(0x0016), + prt_slot_gsiH(0x0017), + prt_slot_gsiE(0x0018), + + /* INTA -> PIRQA for slot 25 - 31, but 30 + see the default value of D<N>IR */ + prt_slot_gsiA(0x0019), + prt_slot_gsiA(0x001a), + prt_slot_gsiA(0x001b), + prt_slot_gsiA(0x001c), + prt_slot_gsiA(0x001d), + + /* PCIe->PCI bridge. use PIRQ[E-H] */ + prt_slot_gsiE(0x001e), + + prt_slot_gsiA(0x001f) + }) + + Method(_PRT, 0, NotSerialized) { + /* PCI IRQ routing table, example from ACPI 2.0a specification, + section 6.2.8.1 */ + /* Note: we provide the same info as the PCI routing + table of the Bochs BIOS */ + If (LEqual(\PICF, Zero)) { + Return (PRTP) + } Else { + Return (PRTA) + } + } + } + + Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + + Offset(0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method(IQST, 1, NotSerialized) { + // _STA method - get status + If (And(0x80, Arg0)) { + Return (0x09) + } + Return (0x0B) + } + Method(IQCR, 1, NotSerialized) { + // _CRS method - get current settings + Name(PRR0, ResourceTemplate() { + Interrupt(, Level, ActiveHigh, Shared) { 0 } + }) + CreateDWordField(PRR0, 0x05, PRRI) + Store(And(Arg0, 0x0F), PRRI) + Return (PRR0) + } + +#define define_link(link, uid, reg) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + 5, 10, 11 \ + } \ + }) \ + Method(_STA, 0, NotSerialized) { \ + Return (IQST(reg)) \ + } \ + Method(_DIS, 0, NotSerialized) { \ + Or(reg, 0x80, reg) \ + } \ + Method(_CRS, 0, NotSerialized) { \ + Return (IQCR(reg)) \ + } \ + Method(_SRS, 1, NotSerialized) { \ + CreateDWordField(Arg0, 0x05, PRRI) \ + Store(PRRI, reg) \ + } \ + } + + define_link(LNKA, 0, PRQA) + define_link(LNKB, 1, PRQB) + define_link(LNKC, 2, PRQC) + define_link(LNKD, 3, PRQD) + define_link(LNKE, 4, PRQE) + define_link(LNKF, 5, PRQF) + define_link(LNKG, 6, PRQG) + define_link(LNKH, 7, PRQH) + +#define define_gsi_link(link, uid, gsi) \ + Device(link) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + Name(_PRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Name(_CRS, ResourceTemplate() { \ + Interrupt(, Level, ActiveHigh, Shared) { \ + gsi \ + } \ + }) \ + Method(_SRS, 1, NotSerialized) { \ + } \ + } + + define_gsi_link(GSIA, 0, 0x10) + define_gsi_link(GSIB, 0, 0x11) + define_gsi_link(GSIC, 0, 0x12) + define_gsi_link(GSID, 0, 0x13) + define_gsi_link(GSIE, 0, 0x14) + define_gsi_link(GSIF, 0, 0x15) + define_gsi_link(GSIG, 0, 0x16) + define_gsi_link(GSIH, 0, 0x17) }
#if 0 @@ -412,43 +412,43 @@ DefinitionBlock ( ****************************************************************/
Scope(_GPE) { - Name(_HID, "ACPI0006") + Name(_HID, "ACPI0006")
- Method(_L00) { - } - Method(_L01) { + Method(_L00) { + } + Method(_L01) { #if 0 - // CPU hotplug event - _SB.PRSC() + // CPU hotplug event + _SB.PRSC() #endif - } - Method(_L02) { - } - Method(_L03) { - } - Method(_L04) { - } - Method(_L05) { - } - Method(_L06) { - } - Method(_L07) { - } - Method(_L08) { - } - Method(_L09) { - } - Method(_L0A) { - } - Method(_L0B) { - } - Method(_L0C) { - } - Method(_L0D) { - } - Method(_L0E) { - } - Method(_L0F) { - } + } + Method(_L02) { + } + Method(_L03) { + } + Method(_L04) { + } + Method(_L05) { + } + Method(_L06) { + } + Method(_L07) { + } + Method(_L08) { + } + Method(_L09) { + } + Method(_L0A) { + } + Method(_L0B) { + } + Method(_L0C) { + } + Method(_L0D) { + } + Method(_L0E) { + } + Method(_L0F) { + } } } diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 78c92a9..4e6daf0 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include <console/console.h>
-#define Q35_PAM0 0x90 +#define Q35_PAM0 0x90
static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, @@ -72,10 +72,10 @@ static void qemu_nb_read_resources(struct device *dev)
static struct device_operations nb_operations = { .read_resources = qemu_nb_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = qemu_nb_init, - .ops_pci = 0, + .init = qemu_nb_init, + .ops_pci = 0, };
static const struct pci_driver nb_driver __pci_driver = { diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl index 01de2e4..6f66a62 100644 --- a/src/mainboard/getac/p470/acpi/platform.asl +++ b/src/mainboard/getac/p470/acpi/platform.asl @@ -229,13 +229,13 @@ Scope(_SB) * We have to do this in order to be able to work around * certain windows bugs. * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 */
/* Let's assume we're running at least Windows 2000 */ diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index c879078..4b2deb6 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -23,123 +23,123 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 6256ca1..66057e9 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -21,20 +21,20 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end
- device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge # autodetect: #device pci 01.0 off end # i945 PCIe root port #device pci 02.0 on end # vga controller #device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0a" register "pirqb_routing" = "0x0a" register "pirqc_routing" = "0x0a" @@ -55,32 +55,32 @@ chip northbridge/intel/i945 register "gpe0_en" = "0x00800106" register "alt_gp_smi_en" = "0x0100"
- register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe port 1 - device pci 1c.1 on end # PCIe port 2 - device pci 1c.2 on end # PCIe port 3 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe port 1 + device pci 1c.1 on end # PCIe port 2 + device pci 1c.2 on end # PCIe port 3 device pci 1c.3 on end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on chip southbridge/ti/pcixx12
end end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/fdc37n972 + device pci 1f.0 on # LPC bridge + chip superio/smsc/fdc37n972 device pnp 2e.0 off # Floppy end device pnp 2e.1 off # ACPI PM @@ -91,11 +91,11 @@ chip northbridge/intel/i945 irq 0x70 = 5 end device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off end - device pnp 2e.5 off - end #device pnp 2e.6 on # RTC # io 0x60 = 0x70 # io 0x62 = 0x74 @@ -107,19 +107,19 @@ chip northbridge/intel/i945 end #device pnp 2e.9 on # Mailbox #end - end - chip superio/smsc/sio10n268 - device pnp 4e.0 off # Floppy + end + chip superio/smsc/sio10n268 + device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end #device pnp 4e.2 on # COM3 - # io 0x60 = 0x3e8 - # irq 0x70 = 11 + # io 0x60 = 0x3e8 + # irq 0x70 = 11 #end #device pnp 4e.3 on # COM4 - # io 0x60 = 0x2e8 - # irq 0x70 = 10 + # io 0x60 = 0x2e8 + # irq 0x70 = 10 #end device pnp 4e.5 on # Keyboard io 0x60 = 0x60 @@ -137,12 +137,12 @@ chip northbridge/intel/i945 end chip ec/acpi end - end + end
- end + end device pci 1f.1 on end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end end diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 14f7484..17edc74 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -26,19 +26,19 @@ #define EC_OEM_SC 0x6c
/* EC_SC input */ -#define EC_SMI_EVT (1 << 6) // 1: SMI event pending -#define EC_SCI_EVT (1 << 5) // 1: SCI event pending -#define EC_BURST (1 << 4) // controller is in burst mode -#define EC_CMD (1 << 3) // 1: byte in data register is command +#define EC_SMI_EVT (1 << 6) // 1: SMI event pending +#define EC_SCI_EVT (1 << 5) // 1: SCI event pending +#define EC_BURST (1 << 4) // controller is in burst mode +#define EC_CMD (1 << 3) // 1: byte in data register is command // 0: byte in data register is data -#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) /* EC_SC output */ -#define RD_EC 0x80 // Read Embedded Controller -#define WR_EC 0x81 // Write Embedded Controller -#define BE_EC 0x82 // Burst Enable Embedded Controller -#define BD_EC 0x83 // Burst Disable Embedded Controller -#define QR_EC 0x84 // Query Embedded Controller +#define RD_EC 0x80 // Read Embedded Controller +#define WR_EC 0x81 // Write Embedded Controller +#define BE_EC 0x82 // Burst Enable Embedded Controller +#define BD_EC 0x83 // Burst Disable Embedded Controller +#define QR_EC 0x84 // Query Embedded Controller
int send_ec_oem_command(u8 command); int send_ec_oem_data(u8 data); diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index a1b9625..2f46c46 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -23,10 +23,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -34,7 +34,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf, /* u8 checksum. */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index 9b59bb4..69f8f60 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -29,14 +29,14 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index f4e43e5..8c7326a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -82,7 +82,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT + lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index c66abad..ae6482c 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -160,12 +160,12 @@ static void mainboard_smi_hotkey(u8 hotkey) case 0x3d: break; // Fn+F3 case 0x3e: break; // Fn+F4 case 0x3f: break; // Fn+F5 - case 0x40: // Fn+F6 (Decrease Display Brightness) + case 0x40: // Fn+F6 (Decrease Display Brightness) reg8 = ec_read(0x17); reg8 = (reg8 > 8) ? (reg8 - 8) : 0; ec_write(0x17, reg8); return; - case 0x41: // Fn+F7 (Increase Display Brightness) + case 0x41: // Fn+F7 (Increase Display Brightness) reg8 = ec_read(0x17); reg8 += 8; reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; diff --git a/src/mainboard/gigabyte/ga-6bxc/devicetree.cb b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb index 5b5c1ae..e4aacd0 100644 --- a/src/mainboard/gigabyte/ga-6bxc/devicetree.cb +++ b/src/mainboard/gigabyte/ga-6bxc/devicetree.cb @@ -9,37 +9,37 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.2 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.4 on # APC - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 3f0.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 3f0.7 on # GPIO - end - end + chip superio/ite/it8671f # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # APC + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 3f0.7 on # GPIO + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c index 0314a34..db7d90d 100644 --- a/src/mainboard/gigabyte/ga-6bxc/irq_tables.c +++ b/src/mainboard/gigabyte/ga-6bxc/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x8, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/gigabyte/ga-6bxe/devicetree.cb b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb index 85f4785..b6be586 100644 --- a/src/mainboard/gigabyte/ga-6bxe/devicetree.cb +++ b/src/mainboard/gigabyte/ga-6bxe/devicetree.cb @@ -9,37 +9,37 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.2 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.4 on # APC - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 3f0.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 3f0.7 on # GPIO - end - end + chip superio/ite/it8671f # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # APC + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 3f0.7 on # GPIO + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/gigabyte/ga-6bxe/irq_tables.c b/src/mainboard/gigabyte/ga-6bxe/irq_tables.c index 1bf573e..2596478 100644 --- a/src/mainboard/gigabyte/ga-6bxe/irq_tables.c +++ b/src/mainboard/gigabyte/ga-6bxe/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xb4, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x08 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, {0x00, (0x09 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, {0x00, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout +++ b/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index c2aecad..ed47051 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -1,83 +1,83 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_AM2 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x1039 0x1234 inherit chip northbridge/amd/amdk8 #mc0 device pci 18.0 on # devices on link 0, link 0 == LDT 0 - chip southbridge/sis/sis966 + chip southbridge/sis/sis966 device pci 0.0 on end # Northbridge device pci 1.0 on # AGP bridge device pci 0.0 on end end - device pci 2.0 on # LPC + device pci 2.0 on # LPC chip superio/ite/it8716f device pnp 2e.0 off # Floppy (N/A) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.2 off # Com2 (N/A) - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 off # Com2 (N/A) + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.3 off # Parallel port (N/A) - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.3 off # Parallel port (N/A) + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 end device pnp 2e.5 off # PS/2 keyboard (N/A) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end device pnp 2e.6 off # Mouse (N/A) - irq 0x70 = 12 + irq 0x70 = 12 end - device pnp 2e.8 off # MIDI (N/A) + device pnp 2e.8 off # MIDI (N/A) io 0x60 = 0x300 irq 0x70 = 10 end - device pnp 2e.9 off # GAME (N/A) + device pnp 2e.9 off # GAME (N/A) io 0x60 = 0x220 end - device pnp 2e.a off end # CIR (N/A) + device pnp 2e.a off end # CIR (N/A) end end
- device pci 2.5 off end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183,Native Mode) - device pci 6.0 on end # PCI-e x1 - device pci 7.0 on end # PCI-e x1 - device pci a.0 off end - device pci b.0 off end - device pci c.0 off end - device pci d.0 off end - device pci e.0 off end - device pci f.0 off end # HD Audio (SiS7502) + device pci 2.5 off end # IDE (SiS5513) + device pci 2.6 off end # Modem (SiS7013) + device pci 2.7 off end # Audio (SiS7012) + device pci 3.0 on end # USB (SiS7001,USB1.1) + device pci 3.1 on end # USB (SiS7001,USB1.1) + device pci 3.3 on end # USB (SiS7002,USB2.0) + device pci 4.0 on end # NIC (SiS191) + device pci 5.0 on end # SATA (SiS1183,Native Mode) + device pci 6.0 on end # PCI-e x1 + device pci 7.0 on end # PCI-e x1 + device pci a.0 off end + device pci b.0 off end + device pci c.0 off end + device pci d.0 off end + device pci e.0 off end + device pci f.0 off end # HD Audio (SiS7502)
- register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end end # device pci 18.0 device pci 18.0 on end # Link 1 @@ -89,16 +89,16 @@ chip northbridge/amd/amdk8/root_complex
end # PCI domain
-# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# device pnp 0.8 off end # io +# device pnp 0.9 off end # io +# end end #root_complex diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 9315cbd..26220dd 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -41,24 +41,24 @@ unsigned apicid_sis966; unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -102,8 +102,8 @@ void get_bus_conf(void) bus_sis966[2]++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x06); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06);
bus_sis966[1] = 2; bus_sis966[2] = 3; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c index 5d108cb..8fc6dfb 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c @@ -39,18 +39,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; } extern unsigned char bus_sis966[8]; //1
@@ -63,17 +63,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v; unsigned sbdn;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ + /* This table must be betweeen 0xf0000 & 0x100000 */ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); @@ -113,51 +113,51 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "done.\n");
- { - device_t dev; - dev = dev_find_slot(0, PCI_DEVFN(2,0)); + { + device_t dev; + dev = dev_find_slot(0, PCI_DEVFN(2,0)); if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D
- PINTA = IRQ10 - PINTB = IRQ11 + PINTA = IRQ10 + PINTB = IRQ11 PINTC = NA PINTD = IRQ10 - PINTE = IRQ11 - PINTF = IRQ5 + PINTE = IRQ11 + PINTF = IRQ5 PINTG = NA PINTH = IRQ7
- */ - uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; + */ + uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
- for(i=0;i<8;i++) - pci_write_config8(dev, reg[i], irq[i]); + for(i=0;i<8;i++) + pci_write_config8(dev, reg[i], irq[i]); } // endif
- printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n"); + printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
- dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) - pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 - pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 - pci_write_config8(dev, 0x3C, 0x05); - dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0 + dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE) + pci_write_config8(dev, 0x3C, 0x0A); + dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1 + pci_write_config8(dev, 0x3C, 0x0B); + dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1 + pci_write_config8(dev, 0x3C, 0x05); + dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0 pci_write_config8(dev, 0x3C, 0x07); - dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN) + dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN) + pci_write_config8(dev, 0x3C, 0x0A); + dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA) + pci_write_config8(dev, 0x3C, 0x0B); + dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA) - pci_write_config8(dev, 0x3C, 0x0B); - dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E - pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E - pci_write_config8(dev, 0x3C, 0x0A); - dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia - pci_write_config8(dev, 0x3C, 0x05); - } + dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E + pci_write_config8(dev, 0x3C, 0x0A); + dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia + pci_write_config8(dev, 0x3C, 0x05); + }
printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size); for (i = 0; i < pirq->size; i+=4) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..80ec6d8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -34,15 +34,15 @@ extern unsigned apicid_sis966;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; unsigned sbdn; int i, j, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); sbdn = sysconf.sbdn; @@ -50,28 +50,28 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; + { + device_t dev; struct resource *res; uint32_t dword;
- dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_sis966, 0x11, res->base); }
dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword);
- dword = 0xd0001202; - pci_write_config32(dev, 0x84, dword); + dword = 0xd0001202; + pci_write_config32(dev, 0x84, dword);
- } + } }
mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0); @@ -80,28 +80,28 @@ static void *smp_write_config_table(void *v) * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
- PCI_INT(0, sbdn+1, 1, 0xa); - PCI_INT(0, sbdn+2, 0, 0x16); // 22 - PCI_INT(0, sbdn+2, 1, 0x17); // 23 - PCI_INT(0, sbdn+6, 1, 0x17); // 23 - PCI_INT(0, sbdn+5, 0, 0x14); // 20 - PCI_INT(0, sbdn+5, 1, 0x17); // 23 - PCI_INT(0, sbdn+5, 2, 0x15); // 21 - PCI_INT(0, sbdn+8, 0, 0x16); // 22 + PCI_INT(0, sbdn+1, 1, 0xa); + PCI_INT(0, sbdn+2, 0, 0x16); // 22 + PCI_INT(0, sbdn+2, 1, 0x17); // 23 + PCI_INT(0, sbdn+6, 1, 0x17); // 23 + PCI_INT(0, sbdn+5, 0, 0x14); // 20 + PCI_INT(0, sbdn+5, 1, 0x17); // 23 + PCI_INT(0, sbdn+5, 2, 0x15); // 21 + PCI_INT(0, sbdn+8, 0, 0x16); // 22
for(j=7; j>=2; j--) { if(!bus_sis966[j]) continue; - for(i=0;i<4;i++) { - PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); - } + for(i=0;i<4;i++) { + PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4); + } }
for(j=0; j<2; j++) - for(i=0;i<4;i++) { - PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); - } + for(i=0;i<4;i++) { + PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4); + }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c index ee8119e..0f8542b 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index e06cb5b..e60a822 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -75,12 +75,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define SIS966_PCI_E_X_0 0
#define SIS966_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/sis/sis966/early_setup_ss.h" #include "cpu/amd/car/post_cache_as_ram.c" @@ -90,20 +90,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -117,94 +117,94 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, };
- struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + }
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); + pnp_write_config(SERIAL_DEV, 0x23, 0); it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV);
- setup_mb_resource_map(); + setup_mb_resource_map();
- console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif - setup_coherent_ht_domain(); // routing table and start other core0 + setup_coherent_ht_domain(); // routing table and start other core0
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
- needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- sis_init_stage1(); - enable_smbus(); + sis_init_stage1(); + enable_smbus();
- //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- sis_init_stage2(); - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + sis_init_stage2(); + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/gigabyte/m57sli/cmos.layout b/src/mainboard/gigabyte/m57sli/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/gigabyte/m57sli/cmos.layout +++ b/src/mainboard/gigabyte/m57sli/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb index 5902932..342b8bd 100644 --- a/src/mainboard/gigabyte/m57sli/devicetree.cb +++ b/src/mainboard/gigabyte/m57sli/devicetree.cb @@ -9,140 +9,140 @@ device domain 0 on # PCI domain chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy and any LDN - # Watchdog from CLKIN (24 MHz) - irq 0x23 = 0x11 - # Serial Flash (SPI only) - # 0x24 = 0x1a - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Embedded controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO, SPI flash - # Pin 84 is not GP10 - irq 0x25 = 0x0 - # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 - irq 0x26 = 0x43 - # Pin 13 is GP35 - irq 0x27 = 0x20 - # Pin 70 is not GP46 - # irq 0x28 = 0x0 - # Pin 6,3,128,127,126 is GP63,64,65,66,67 - irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), - # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), - # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal - # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal - # voltage divider for VCC5V - # irq 0x2c = 0x1f - # Simple I/O base - io 0x62 = 0x800 - # Serial Flash I/O (SPI only) - io 0x64 = 0x820 - # Watchdog force timeout (parallel flash only) - # irq 0x71 = 0x1 - # No WDT interrupt - irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup - irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup - irq 0xbc = 0x01 - # SIO pin set 1 alternate function - # irq 0xc0 = 0x0 - # SIO pin set 2 mixed function - irq 0xc1 = 0x43 - # SIO pin set 3 mixed function - irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - # irq 0xc3 = 0x0 - # SIO pin set 1 input mode - # irq 0xc8 = 0x0 - # SIO pin set 2 input mode - irq 0xc9 = 0x0 - # SIO pin set 4 input mode - # irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - # irq 0xf0 = 0x10 - # SMI# level trigger - # irq 0xf1 = 0x40 - # HWMON alert beep pin location - irq 0xf6 = 0x28 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # Consumer IR - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AUDIO - device pci 8.0 on end # NIC - device pci 9.0 off end # N/A - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy and any LDN + # Watchdog from CLKIN (24 MHz) + irq 0x23 = 0x11 + # Serial Flash (SPI only) + # 0x24 = 0x1a + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Embedded controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO, SPI flash + # Pin 84 is not GP10 + irq 0x25 = 0x0 + # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # Pin 13 is GP35 + irq 0x27 = 0x20 + # Pin 70 is not GP46 + # irq 0x28 = 0x0 + # Pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), + # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), + # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal + # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal + # voltage divider for VCC5V + # irq 0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + io 0x64 = 0x820 + # Watchdog force timeout (parallel flash only) + # irq 0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + # irq 0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + # irq 0xc3 = 0x0 + # SIO pin set 1 input mode + # irq 0xc8 = 0x0 + # SIO pin set 2 input mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + # irq 0xcb = 0x0 + # Generate SMI# on EC IRQ + # irq 0xf0 = 0x10 + # SMI# level trigger + # irq 0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # Consumer IR + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AUDIO + device pci 8.0 on end # NIC + device pci 9.0 off end # N/A + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # Link 1 device pci 18.0 on end diff --git a/src/mainboard/gigabyte/m57sli/dsdt.asl b/src/mainboard/gigabyte/m57sli/dsdt.asl index 3df689d..ddb9931 100644 --- a/src/mainboard/gigabyte/m57sli/dsdt.asl +++ b/src/mainboard/gigabyte/m57sli/dsdt.asl @@ -55,21 +55,21 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) External (HCDN)
Method (_CRS, 0, NotSerialized) - { + { Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index c798415..b054faa 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -39,24 +39,24 @@ unsigned apicid_mcp55; unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -100,8 +100,8 @@ void get_bus_conf(void) bus_mcp55[2]++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x06); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06);
bus_mcp55[1] = 2; bus_mcp55[2] = 3; diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index f56c040..33ae52f 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -37,18 +37,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; } extern unsigned char bus_mcp55[8]; //1
@@ -63,18 +63,18 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v; unsigned sbdn;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -102,14 +102,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 1536823..5e5a223 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -33,15 +33,15 @@ extern unsigned apicid_mcp55;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; unsigned sbdn; int i, j, k, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); sbdn = sysconf.sbdn; @@ -49,21 +49,21 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; + { + device_t dev; struct resource *res;
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); } /* set up the interrupt registers of mcp55 */ - pci_write_config32(dev, 0x7c, 0xc643c643); - pci_write_config32(dev, 0x80, 0x8da01009); - pci_write_config32(dev, 0x84, 0x200018d2); - } + pci_write_config32(dev, 0x7c, 0xc643c643); + pci_write_config32(dev, 0x80, 0x8da01009); + pci_write_config32(dev, 0x84, 0x200018d2); + } }
mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0); @@ -86,28 +86,28 @@ static void *smp_write_config_table(void *v) PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
/* The PCIe slots, each on its own bus */ - k = 1; - for(i=0; i<4; i++){ - for(j=7; j>1; j--){ - if(k>3) k=0; - PCI_INT(j,0,i, 16+k); - k++; - } - k--; - } + k = 1; + for(i=0; i<4; i++){ + for(j=7; j>1; j--){ + if(k>3) k=0; + PCI_INT(j,0,i, 16+k); + k++; + } + k--; + }
/* On bus 1: the PCI bus slots... physical PCI slots are j = 7,8 FireWire is j = 10 */ - k=2; - for(i=0; i<4; i++){ - for(j=6; j<11; j++){ - if(k>3) k=0; - PCI_INT(1,j,i, 16+k); - k++; - } - } + k=2; + for(i=0; i<4; i++){ + for(j=6; j<11; j++){ + if(k>3) k=0; + PCI_INT(1,j,i, 16+k); + k++; + } + }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c index ee8119e..0f8542b 100644 --- a/src/mainboard/gigabyte/m57sli/resourcemap.c +++ b/src/mainboard/gigabyte/m57sli/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 469e195..c54e579 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -59,12 +59,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) }
#define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" @@ -82,20 +82,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte;
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -109,19 +109,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, };
- struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0; uint8_t tmp = 0;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + }
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV); @@ -139,74 +139,74 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV);
- setup_mb_resource_map(); + setup_mb_resource_map();
- console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif - setup_coherent_ht_domain(); // routing table and start other core0 + setup_coherent_ht_domain(); // routing table and start other core0
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
init_timer(); // Need to use TMICT to synconize FID/VID
- needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x();
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } - allow_all_aps_stop(bsp_apicid); + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } + allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus(); + enable_smbus();
- /* all ap stopped? */ + /* all ap stopped? */
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl +++ b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 8318856..7f8e586 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -70,7 +70,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/gigabyte/ma785gm/cmos.layout +++ b/src/mainboard/gigabyte/ma785gm/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb index c7d9932..0a7e8f7 100644 --- a/src/mainboard/gigabyte/ma785gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 off end # device pci a.0 on end # PCIE P2P bridge 0x9609 register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index faf2171..599a0f2 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "GIGA ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "GIGA ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index cd06069..3e67c63 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -124,7 +124,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/gigabyte/ma785gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 056e0df..ef852af 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -232,8 +232,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl b/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl +++ b/src/mainboard/gigabyte/ma785gmt/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c index a2182f9..de24432 100644 --- a/src/mainboard/gigabyte/ma785gmt/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gmt/acpi_tables.c @@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/gigabyte/ma785gmt/cmos.layout b/src/mainboard/gigabyte/ma785gmt/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/gigabyte/ma785gmt/cmos.layout +++ b/src/mainboard/gigabyte/ma785gmt/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb index bd98313..5c1376e 100644 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "2" diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index faf2171..599a0f2 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "GIGA ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "GIGA ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 89b50bb..80cf633 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -28,7 +28,7 @@ #include "southbridge/amd/sb700/smbus.h"
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */
#define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) @@ -157,7 +157,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword |= (1 << 26); pci_write_config32(sm_dev, 0xfc, dword); @@ -169,7 +169,7 @@ static void set_gpio40_gfx(void) dword = pci_read_config32(sm_dev, 0xfc); dword &= ~(1 << 10);
- /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* When the gpio40 is configured as GPIO, this will represent the output value*/ /* 1 :enable two x8 , 0 : master slot enable only */ dword &= ~(1 << 26); pci_write_config32(sm_dev, 0xfc, dword); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c +++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 056e0df..ef852af 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -232,8 +232,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/gigabyte/ma78gm/acpi/ide.asl b/src/mainboard/gigabyte/ma78gm/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi/ide.asl +++ b/src/mainboard/gigabyte/ma78gm/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/gigabyte/ma78gm/acpi_tables.c b/src/mainboard/gigabyte/ma78gm/acpi_tables.c index a2182f9..de24432 100644 --- a/src/mainboard/gigabyte/ma78gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma78gm/acpi_tables.c @@ -68,7 +68,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/gigabyte/ma78gm/cmos.layout b/src/mainboard/gigabyte/ma78gm/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/gigabyte/ma78gm/cmos.layout +++ b/src/mainboard/gigabyte/ma78gm/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 8d81fbe..12494a4 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index faf2171..599a0f2 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "GIGA ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "GIGA ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index c4ec478..c106e8f 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/gigabyte/ma78gm/resourcemap.c +++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 431e554..326b9a0 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -235,8 +235,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/google/butterfly/acpi/chromeos.asl b/src/mainboard/google/butterfly/acpi/chromeos.asl index 27373e1..d660797 100644 --- a/src/mainboard/google/butterfly/acpi/chromeos.asl +++ b/src/mainboard/google/butterfly/acpi/chromeos.asl @@ -20,6 +20,6 @@ Name(OIPG, Package() { Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect + Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect })
diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl index ba725ac..00d4949 100644 --- a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl +++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl @@ -25,7 +25,7 @@ Method(_PRT) If (PICM) { Return (Package() { // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) // PCIe Root Ports 0:1c.x diff --git a/src/mainboard/google/butterfly/acpi/superio.asl b/src/mainboard/google/butterfly/acpi/superio.asl index 2089604..ec60667 100644 --- a/src/mainboard/google/butterfly/acpi/superio.asl +++ b/src/mainboard/google/butterfly/acpi/superio.asl @@ -20,7 +20,7 @@ /* mainboard configuration */ #include "../ec.h"
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
/* ACPI code for EC SuperIO functions */ #include <ec/quanta/ene_kb3940q/acpi/superio.asl> diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 95b45db..0754f14 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -227,7 +227,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..7faf58d 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -21,117 +21,117 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 608827a..fc3ae81 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock( "DSDT", 0x02, // DSDT revision: ACPI v2.0 "COREv4", // OEM id - "COREBOOT", // OEM table id + "COREBOOT", // OEM table id 0x20110725 // OEM revision ) { diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c index dd2298d..c3a827d 100644 --- a/src/mainboard/google/butterfly/ec.c +++ b/src/mainboard/google/butterfly/ec.c @@ -28,9 +28,9 @@ void butterfly_ec_init(void) /* Report EC info */ /* EC version: 6 bytes */ printk(BIOS_DEBUG," EC version: %c%c%c%c%c%c\n", - ec_mem_read(EC_FW_VER0), ec_mem_read(EC_FW_VER1), - ec_mem_read(EC_FW_VER2), ec_mem_read(EC_FW_VER3), - ec_mem_read(EC_FW_VER4), ec_mem_read(EC_FW_VER5)); + ec_mem_read(EC_FW_VER0), ec_mem_read(EC_FW_VER1), + ec_mem_read(EC_FW_VER2), ec_mem_read(EC_FW_VER3), + ec_mem_read(EC_FW_VER4), ec_mem_read(EC_FW_VER5));
/* Disable wake on USB, LAN & RTC */ /* Enable Wake from Keyboard */ diff --git a/src/mainboard/google/butterfly/ec.h b/src/mainboard/google/butterfly/ec.h index 5bbbd5a..3729815 100644 --- a/src/mainboard/google/butterfly/ec.h +++ b/src/mainboard/google/butterfly/ec.h @@ -20,7 +20,7 @@ #ifndef BUTTERFLY_EC_H #define BUTTERFLY_EC_H
-#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */ +#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
/* EC SMI sources TODO: MLR- make defines */
diff --git a/src/mainboard/google/butterfly/hda_verb.h b/src/mainboard/google/butterfly/hda_verb.h index 1901a68..5355c91 100644 --- a/src/mainboard/google/butterfly/hda_verb.h +++ b/src/mainboard/google/butterfly/hda_verb.h @@ -17,10 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-/* Vendor Name : IDT - * Vendor ID : 0x111d76e5 - * Subsystem ID : 0x103c18f9 - * Revision ID : 0x100303 +/* Vendor Name : IDT + * Vendor ID : 0x111d76e5 + * Subsystem ID : 0x103c18f9 + * Revision ID : 0x100303 */
@@ -213,18 +213,18 @@ static const u32 mainboard_cim_verb_data[] = { 0x00D70740, /* Enable PortD as Output */ 0x0017A200, /* Disable ClkEn of PortSenseTst */ 0x0017C621, /* Slave Port - Port A used as microphone input for - combo Jack - Master Port - Port B used for Jack Presence Detect - Enable Combo Jack Detection */ + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ 0x0017A208, /* Enable ClkEn of PortSenseTst */ 0x00170500, /* Set power state to D0 */
/* --- Next Codec --- */
-/* Vendor Name : Intel - * Vendor ID : 0x80862806 - * Subsystem ID : 0x80860101 - * Revision ID : 0x100000 +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 */ /* coreboot specific header */ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index b11c226..68ee477 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -85,7 +85,7 @@ static int get_mac_address(u32 *high_dword, u32 *low_dword, sizeof(key) - 1, search_length); if (offset == search_length) { printk(BIOS_DEBUG, - "Error: Could not locate '%s' in VPD\n", key); + "Error: Could not locate '%s' in VPD\n", key); return 0; } printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); @@ -113,9 +113,9 @@ static int get_mac_address(u32 *high_dword, u32 *low_dword, *low_dword = 0; for (i = 0; i < 2; i++) { *low_dword |= (get_hex_digit((char *)(search_address + offset)) - << (4 + (i * 8))); + << (4 + (i * 8))); *low_dword |= (get_hex_digit((char *)(search_address + offset + 1)) - << (i * 8)); + << (i * 8)); offset += 3; }
@@ -197,7 +197,7 @@ static int int15_handler(void) int res = 0;
printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", - __func__, X86_AX); + __func__, X86_AX);
switch (X86_AX) { case 0x5f34: @@ -206,7 +206,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ @@ -263,7 +263,7 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", - X86_CH); + X86_CH); break; } break; @@ -308,7 +308,7 @@ static void mainboard_init(device_t dev)
/* Get NIC's IO base address */ ethernet_dev = dev_find_device(BUTTERFLY_NIC_VENDOR_ID, - BUTTERFLY_NIC_DEVICE_ID, dev); + BUTTERFLY_NIC_DEVICE_ID, dev); if (ethernet_dev != NULL) { io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
@@ -331,11 +331,11 @@ static void mainboard_init(device_t dev) * Section 5.6 LED Mode Configuration * * Step1: Write C0h to I/O register 0x50 via byte access to - * disable 'register protection' + * disable 'register protection' * Step2: Write xx001111b to I/O register 0x52 via byte access - * (bit7 is LEDS1 and bit6 is LEDS0) + * (bit7 is LEDS1 and bit6 is LEDS0) * Step3: Write 0x00 to I/O register 0x50 via byte access to - * enable 'register protection' + * enable 'register protection' */ outb(0xc0, io_base + 0x50); /* Disable protection */ outb((BUTTERFLY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h index e32e023..6e08499 100644 --- a/src/mainboard/google/butterfly/onboard.h +++ b/src/mainboard/google/butterfly/onboard.h @@ -23,9 +23,9 @@ #include <arch/smp/mpspec.h> /* uses 7-bit I2C address */ /* must be set to edge triggered */ -#define BUTTERFLY_TRACKPAD_NAME "trackpad" -#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67 -#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */ +#define BUTTERFLY_TRACKPAD_NAME "trackpad" +#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67 +#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */
/* defines for programming the MAC address */ #define BUTTERFLY_NIC_VENDOR_ID 0x10EC diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index f56884d..b339914 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -62,19 +62,19 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P2IP ETH0 INTB -> PIRQF * D28IP_P3IP SDCARD INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * Trackpad interrupt is edge triggered and cannot be shared. - * TRACKPAD -> PIRQG + * TRACKPAD -> PIRQG
*/
@@ -146,7 +146,7 @@ void main(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb_port_config: { - /* enabled usb oc pin length */ + /* enabled usb oc pin length */ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ diff --git a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl b/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl index 82a2eba..881675b 100644 --- a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl @@ -42,12 +42,12 @@ Method(_PRT) Package() { 0x001fffff, 1, 0, 18 }, Package() { 0x001fffff, 2, 0, 17 }, Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, 0, 20 }, Package() { 0x0015ffff, 1, 0, 21 }, Package() { 0x0015ffff, 2, 0, 21 }, Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, 0, 23 }, }) } Else { @@ -70,12 +70,12 @@ Method(_PRT) Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, Package() { 0x0015ffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 2, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 3, _SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, }) } diff --git a/src/mainboard/google/falco/acpi/superio.asl b/src/mainboard/google/falco/acpi/superio.asl index 18da3d0..b2caae5 100644 --- a/src/mainboard/google/falco/acpi/superio.asl +++ b/src/mainboard/google/falco/acpi/superio.asl @@ -20,10 +20,10 @@ /* mainboard configuration */ #include <mainboard/google/falco/ec.h>
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
/* ACPI code for EC SuperIO functions */ #include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/falco/acpi_tables.c b/src/mainboard/google/falco/acpi_tables.c index 7a3ccea..313a939 100644 --- a/src/mainboard/google/falco/acpi_tables.c +++ b/src/mainboard/google/falco/acpi_tables.c @@ -241,7 +241,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; acpi_save_gnvs((unsigned long)gnvs); break; diff --git a/src/mainboard/google/falco/cmos.layout b/src/mainboard/google/falco/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/falco/cmos.layout +++ b/src/mainboard/google/falco/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/falco/ec.c b/src/mainboard/google/falco/ec.c index 0919f0f..74bb385 100644 --- a/src/mainboard/google/falco/ec.c +++ b/src/mainboard/google/falco/ec.c @@ -32,7 +32,7 @@ void mainboard_ec_init(void) /* Restore SCI event mask on resume. */ if (acpi_slp_type == 3) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); + MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */ google_chromeec_set_smi_mask(0); @@ -42,7 +42,7 @@ void mainboard_ec_init(void) google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); + MAINBOARD_EC_S5_WAKE_EVENTS); }
/* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/falco/ec.h b/src/mainboard/google/falco/ec.h index 11d2453..86be0df 100644 --- a/src/mainboard/google/falco/ec.h +++ b/src/mainboard/google/falco/ec.h @@ -22,17 +22,17 @@
#include <ec/google/chromeec/ec_commands.h>
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ +#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ +#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) @@ -42,7 +42,7 @@
/* EC can wake from S5 with lid or power button */ #define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */ diff --git a/src/mainboard/google/falco/gpio.h b/src/mainboard/google/falco/gpio.h index 3af0d59..45f117d 100644 --- a/src/mainboard/google/falco/gpio.h +++ b/src/mainboard/google/falco/gpio.h @@ -23,101 +23,101 @@ struct pch_lp_gpio_map;
const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - LP_GPIO_INPUT, /* 9: RAM_ID1 */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ - LP_GPIO_INPUT, /* 13: RAM_ID0 */ - LP_GPIO_INPUT, /* 14: EC_IN_RW */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 16: UNUSED */ - LP_GPIO_UNUSED, /* 17: UNUSED */ - LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_UNUSED, /* 20: UNUSED */ - LP_GPIO_UNUSED, /* 21: UNUSED */ - LP_GPIO_UNUSED, /* 22: UNUSED */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 16: UNUSED */ + LP_GPIO_UNUSED, /* 17: UNUSED */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ - LP_GPIO_UNUSED, /* 26: UNUSED */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_UNUSED, /* 41: UNUSED */ - LP_GPIO_UNUSED, /* 42: UNUSED */ - LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ - LP_GPIO_UNUSED, /* 44: UNUSED */ - LP_GPIO_UNUSED, /* 45: UNUSED */ - LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - LP_GPIO_INPUT, /* 47: RAM_ID2 */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_UNUSED, /* 49: UNUSED */ - LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_INPUT, /* 51: ALS_INT_L */ - LP_GPIO_INPUT, /* 52: SIM_DET */ - LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ - LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_UNUSED, /* 56: UNUSED */ - LP_GPIO_UNUSED, /* 57: UNUSED */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_UNUSED, /* 61: UNUSED */ - LP_GPIO_UNUSED, /* 62: UNUSED */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_UNUSED, /* 72: UNUSED */ - LP_GPIO_UNUSED, /* 73: UNUSED */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_UNUSED, /* 42: UNUSED */ + LP_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + LP_GPIO_UNUSED, /* 44: UNUSED */ + LP_GPIO_UNUSED, /* 45: UNUSED */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_UNUSED, /* 49: UNUSED */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_INPUT, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_UNUSED, /* 57: UNUSED */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_UNUSED, /* 61: UNUSED */ + LP_GPIO_UNUSED, /* 62: UNUSED */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_UNUSED, /* 72: UNUSED */ + LP_GPIO_UNUSED, /* 73: UNUSED */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END };
diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index 3bf26e3..dc4338a 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -51,7 +51,7 @@ static int int15_handler(void) int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f34: @@ -60,7 +60,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CX = 0x0001; @@ -117,13 +117,13 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index ef6a849..04b9cb4 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -33,14 +33,14 @@ const struct rcba_config_instruction rcba_config[] = {
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD + * D29IP_E1P EHCI INTA -> PIRQD * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ @@ -98,9 +98,9 @@ static void copy_spd(struct pei_data *peid) peid->dimm_channel1_disabled = 3;
memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); }
void mainboard_romstage_entry(unsigned long bist) @@ -132,19 +132,19 @@ void mainboard_romstage_entry(unsigned long bist) max_ddr3_freq: 1600, usb2_ports: { /* Length, Enable, OCn# */ - { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ - { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ + { 0x0040, 1, 0 }, /* P0: Port A, CN8 */ + { 0x0040, 1, 0 }, /* P1: Port B, CN9 */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ - { 0x0040, 1, 3 }, /* P7: USB2 Port */ + { 0x0040, 1, 3 }, /* P7: USB2 Port */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN8 */ - { 1, 0 }, /* P2; Port B, CN9 */ + { 1, 0 }, /* P1; Port A, CN8 */ + { 1, 0 }, /* P2; Port B, CN9 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, diff --git a/src/mainboard/google/link/acpi/superio.asl b/src/mainboard/google/link/acpi/superio.asl index b1ef4ae..544e347 100644 --- a/src/mainboard/google/link/acpi/superio.asl +++ b/src/mainboard/google/link/acpi/superio.asl @@ -20,10 +20,10 @@ /* mainboard configuration */ #include "../ec.h"
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
/* ACPI code for EC SuperIO functions */ #include "../../../../ec/google/chromeec/acpi/superio.asl" diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index dbbde68..e9478a3 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -244,7 +244,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/link/drm_dp_helper.h b/src/mainboard/google/link/drm_dp_helper.h index f2e06c3..fa9e6fc 100644 --- a/src/mainboard/google/link/drm_dp_helper.h +++ b/src/mainboard/google/link/drm_dp_helper.h @@ -45,120 +45,120 @@
/* AUX CH addresses */ /* DPCD */ -#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV 0x000
-#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LINK_RATE 0x001
-#define DP_MAX_LANE_COUNT 0x002 +#define DP_MAX_LANE_COUNT 0x002 # define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) +# define DP_TPS3_SUPPORTED (1 << 6) # define DP_ENHANCED_FRAME_CAP (1 << 7)
-#define DP_MAX_DOWNSPREAD 0x003 +#define DP_MAX_DOWNSPREAD 0x003 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
-#define DP_NORP 0x004 +#define DP_NORP 0x004
-#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 /* 00b = DisplayPort */ /* 01b = Analog */ /* 10b = TMDS or HDMI */ /* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 +# define DP_FORMAT_CONVERSION (1 << 3) + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_EDP_CONFIGURATION_CAP 0x00d +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e + +#define DP_PSR_SUPPORT 0x070 +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1
/* link configuration */ -#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14
-#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
-#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_2 2 # define DP_TRAINING_PATTERN_3 3 # define DP_TRAINING_PATTERN_MASK 0x3
-# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
-# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
-#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4)
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) +# define DP_SET_ANSI_8B10B (1 << 0)
#define DP_PSR_EN_CFG 0x170 # define DP_PSR_ENABLE (1 << 0) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) # define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) +# define DP_PSR_FRAME_CAPTURE (1 << 3)
-#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) # define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) +# define DP_CP_IRQ (1 << 2) +# define DP_SINK_SPECIFIC_IRQ (1 << 6)
-#define DP_EDP_CONFIGURATION_SET 0x10a +#define DP_EDP_CONFIGURATION_SET 0x10a
#define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 @@ -170,7 +170,7 @@ DP_LANE_CHANNEL_EQ_DONE | \ DP_LANE_SYMBOL_LOCKED)
-#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0) #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) @@ -194,42 +194,42 @@
#define DP_TEST_REQUEST 0x218 # define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) +# define DP_TEST_LINK_PATTERN (1 << 1) # define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
#define DP_TEST_LINK_RATE 0x219 # define DP_LINK_RATE_162 (0x6) # define DP_LINK_RATE_27 (0xa)
-#define DP_TEST_LANE_COUNT 0x220 +#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 + +#define DP_PSR_ERROR_STATUS 0x2006 +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07
#define MODE_I2C_START 1 #define MODE_I2C_WRITE 2 diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index 07da080..2231878 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -32,7 +32,7 @@ void link_ec_init(void) /* Restore SCI event mask on resume. */ if (acpi_slp_type == 3) { google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S3_WAKE_EVENTS); + LINK_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */ google_chromeec_set_smi_mask(0); @@ -42,7 +42,7 @@ void link_ec_init(void) google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); } else { google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S5_WAKE_EVENTS); + LINK_EC_S5_WAKE_EVENTS); }
/* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h index 0044347..9dfaf16 100644 --- a/src/mainboard/google/link/ec.h +++ b/src/mainboard/google/link/ec.h @@ -23,16 +23,16 @@ #include <ec/google/chromeec/ec_commands.h>
#define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */ -#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ +#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */
#define LINK_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) @@ -42,7 +42,7 @@
/* EC can wake from S5 with lid or power button */ #define LINK_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */ diff --git a/src/mainboard/google/link/fadt.c b/src/mainboard/google/link/fadt.c index 5ce9ab1..1a09ccc 100644 --- a/src/mainboard/google/link/fadt.c +++ b/src/mainboard/google/link/fadt.c @@ -26,11 +26,11 @@ * code and the mainboard fadt. */ #define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h index 6caa48b..52ff718 100644 --- a/src/mainboard/google/link/gpio.h +++ b/src/mainboard/google/link/gpio.h @@ -104,18 +104,18 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map link_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/google/link/i915_reg.h b/src/mainboard/google/link/i915_reg.h index 8bdf2cb..212820d 100644 --- a/src/mainboard/google/link/i915_reg.h +++ b/src/mainboard/google/link/i915_reg.h @@ -39,36 +39,36 @@ /* PCI config space */
#define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (0xf << 0) -#define GC_CLOCK_133_200 (0 << 0) -#define GC_CLOCK_100_200 (1 << 0) -#define GC_CLOCK_100_133 (2 << 0) -#define GC_CLOCK_166_250 (3 << 0) +#define GC_CLOCK_CONTROL_MASK (0xf << 0) +#define GC_CLOCK_133_200 (0 << 0) +#define GC_CLOCK_100_200 (1 << 0) +#define GC_CLOCK_100_133 (2 << 0) +#define GC_CLOCK_166_250 (3 << 0) #define GCFGC2 0xda #define GCFGC 0xf0 /* 915+ only */ -#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -#define GC_DISPLAY_CLOCK_MASK (7 << 4) -#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) -#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) -#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) -#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) -#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) -#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) -#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) -#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) -#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) -#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) -#define I945_GC_RENDER_CLOCK_MASK (7 << 0) -#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) -#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) -#define I915_GC_RENDER_CLOCK_MASK (7 << 0) -#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) +#define GC_LOW_FREQUENCY_ENABLE (1 << 7) +#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_MASK (7 << 4) +#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) +#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) +#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) +#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) +#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) +#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) +#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) +#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) +#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) +#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) +#define I945_GC_RENDER_CLOCK_MASK (7 << 0) +#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) +#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) +#define I915_GC_RENDER_CLOCK_MASK (7 << 0) +#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define LBB 0xf4
/* Graphics reset regs */ @@ -79,19 +79,19 @@ #define GRDOM_MEDIA (3<<2)
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ -#define GEN6_MBC_SNPCR_SHIFT 21 -#define GEN6_MBC_SNPCR_MASK (3<<21) -#define GEN6_MBC_SNPCR_MAX (0<<21) -#define GEN6_MBC_SNPCR_MED (1<<21) -#define GEN6_MBC_SNPCR_LOW (2<<21) -#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ +#define GEN6_MBC_SNPCR_SHIFT 21 +#define GEN6_MBC_SNPCR_MASK (3<<21) +#define GEN6_MBC_SNPCR_MAX (0<<21) +#define GEN6_MBC_SNPCR_MED (1<<21) +#define GEN6_MBC_SNPCR_LOW (2<<21) +#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
#define GEN6_MBCTL 0x0907c -#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) -#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) -#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) -#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) -#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) +#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) +#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) +#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) +#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) +#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
#define GEN6_GDRST 0x941c #define GEN6_GRDOM_FULL (1 << 0) @@ -118,12 +118,12 @@ #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) -#define PP_DIR_DCLV_2G 0xffffffff +#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090 -#define ECOCHK_SNB_BIT (1<<10) -#define ECOCHK_PPGTT_CACHE64B (0x3<<3) -#define ECOCHK_PPGTT_CACHE4B (0x0<<3) +#define ECOCHK_SNB_BIT (1<<10) +#define ECOCHK_PPGTT_CACHE64B (0x3<<3) +#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
/* VGA stuff */
@@ -132,29 +132,29 @@
#define VGA_MSR_WRITE 0x3c2 #define VGA_MSR_READ 0x3cc -#define VGA_MSR_MEM_EN (1<<1) -#define VGA_MSR_CGA_MODE (1<<0) +#define VGA_MSR_MEM_EN (1<<1) +#define VGA_MSR_CGA_MODE (1<<0)
#define VGA_SR_INDEX 0x3c4 #define VGA_SR_DATA 0x3c5
#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) +#define VGA_AR_VID_EN (1<<5) #define VGA_AR_DATA_WRITE 0x3c0 #define VGA_AR_DATA_READ 0x3c1
#define VGA_GR_INDEX 0x3ce #define VGA_GR_DATA 0x3cf /* GR05 */ -#define VGA_GR_MEM_READ_MODE_SHIFT 3 -#define VGA_GR_MEM_READ_MODE_PLANE 1 +#define VGA_GR_MEM_READ_MODE_SHIFT 3 +#define VGA_GR_MEM_READ_MODE_PLANE 1 /* GR06 */ -#define VGA_GR_MEM_MODE_MASK 0xc -#define VGA_GR_MEM_MODE_SHIFT 2 -#define VGA_GR_MEM_A0000_AFFFF 0 -#define VGA_GR_MEM_A0000_BFFFF 1 -#define VGA_GR_MEM_B0000_B7FFF 2 -#define VGA_GR_MEM_B0000_BFFFF 3 +#define VGA_GR_MEM_MODE_MASK 0xc +#define VGA_GR_MEM_MODE_SHIFT 2 +#define VGA_GR_MEM_A0000_AFFFF 0 +#define VGA_GR_MEM_A0000_BFFFF 1 +#define VGA_GR_MEM_B0000_B7FFF 2 +#define VGA_GR_MEM_B0000_BFFFF 3
#define VGA_DACMASK 0x3c6 #define VGA_DACRX 0x3c7 @@ -173,41 +173,41 @@
#define MI_NOOP MI_INSTR(0, 0) #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ +#define MI_READ_FLUSH (1 << 0) +#define MI_EXE_FLUSH (1 << 1) +#define MI_NO_WRITE_FLUSH (1 << 2) +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ +#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) +#define MI_SUSPEND_FLUSH_EN (1<<0) #define MI_REPORT_HEAD MI_INSTR(0x07, 0) #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON (0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) +#define MI_OVERLAY_CONTINUE (0x0<<21) +#define MI_OVERLAY_ON (0x1<<21) +#define MI_OVERLAY_OFF (0x2<<21) #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) +#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) #define MI_SET_CONTEXT MI_INSTR(0x18, 0) -#define MI_MM_SPACE_GTT (1<<8) -#define MI_MM_SPACE_PHYSICAL (0<<8) -#define MI_SAVE_EXT_STATE_EN (1<<3) -#define MI_RESTORE_EXT_STATE_EN (1<<2) -#define MI_FORCE_RESTORE (1<<1) -#define MI_RESTORE_INHIBIT (1<<0) +#define MI_MM_SPACE_GTT (1<<8) +#define MI_MM_SPACE_PHYSICAL (0<<8) +#define MI_SAVE_EXT_STATE_EN (1<<3) +#define MI_RESTORE_EXT_STATE_EN (1<<2) +#define MI_FORCE_RESTORE (1<<1) +#define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 +#define MI_STORE_DWORD_INDEX_SHIFT 2 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. @@ -216,23 +216,23 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) +#define MI_INVALIDATE_TLB (1<<18) +#define MI_INVALIDATE_BSD (1<<7) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER (1<<18) -#define MI_SEMAPHORE_SYNC_RV (2<<16) -#define MI_SEMAPHORE_SYNC_RB (0<<16) -#define MI_SEMAPHORE_SYNC_VR (0<<16) -#define MI_SEMAPHORE_SYNC_VB (2<<16) -#define MI_SEMAPHORE_SYNC_BR (2<<16) -#define MI_SEMAPHORE_SYNC_BV (0<<16) +#define MI_SEMAPHORE_UPDATE (1<<21) +#define MI_SEMAPHORE_COMPARE (1<<20) +#define MI_SEMAPHORE_REGISTER (1<<18) +#define MI_SEMAPHORE_SYNC_RV (2<<16) +#define MI_SEMAPHORE_SYNC_RB (0<<16) +#define MI_SEMAPHORE_SYNC_VR (0<<16) +#define MI_SEMAPHORE_SYNC_VB (2<<16) +#define MI_SEMAPHORE_SYNC_BR (2<<16) +#define MI_SEMAPHORE_SYNC_BV (0<<16) #define MI_SEMAPHORE_SYNC_INVALID (1<<0) /* * 3D instructions used by the kernel @@ -240,57 +240,57 @@ #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) +#define BLT_DEPTH_8 (0<<24) +#define BLT_DEPTH_16_565 (1<<24) +#define BLT_DEPTH_16_1555 (2<<24) +#define BLT_DEPTH_32 (3<<24) +#define BLT_ROP_GXCOPY (0xcc<<16) #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) +#define ASYNC_FLIP (1<<22) +#define DISPLAY_PLANE_A (0<<20) +#define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) -#define PIPE_CONTROL_CS_STALL (1<<20) -#define PIPE_CONTROL_QW_WRITE (1<<14) -#define PIPE_CONTROL_DEPTH_STALL (1<<13) -#define PIPE_CONTROL_WRITE_FLUSH (1<<12) -#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ -#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ -#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ -#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_NOTIFY (1<<8) -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_CS_STALL (1<<20) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WRITE_FLUSH (1<<12) +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ +#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) +#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) +#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
/* @@ -307,32 +307,32 @@ */ #define FENCE_REG_830_0 0x2000 #define FENCE_REG_945_8 0x3000 -#define I830_FENCE_START_MASK 0x07f80000 -#define I830_FENCE_TILING_Y_SHIFT 12 -#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) -#define I830_FENCE_PITCH_SHIFT 4 -#define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 4 -#define I830_FENCE_MAX_PITCH_VAL 6 -#define I830_FENCE_MAX_SIZE_VAL (1<<8) - -#define I915_FENCE_START_MASK 0x0ff00000 -#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) +#define I915_FENCE_MAX_PITCH_VAL 4 +#define I830_FENCE_MAX_PITCH_VAL 6 +#define I830_FENCE_MAX_SIZE_VAL (1<<8) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
#define FENCE_REG_965_0 0x03000 -#define I965_FENCE_PITCH_SHIFT 2 -#define I965_FENCE_TILING_Y_SHIFT 1 -#define I965_FENCE_REG_VALID (1<<0) -#define I965_FENCE_MAX_PITCH_VAL 0x0400 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) +#define I965_FENCE_MAX_PITCH_VAL 0x0400
#define FENCE_REG_SANDYBRIDGE_0 0x100000 -#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
/* control register for cpu gtt access */ #define TILECTL 0x101000 -#define TILECTL_SWZCTL (1 << 0) -#define TILECTL_TLB_PREFETCH_DIS (1 << 2) -#define TILECTL_BACKSNOOP_DIS (1 << 3) +#define TILECTL_SWZCTL (1 << 0) +#define TILECTL_TLB_PREFETCH_DIS (1 << 2) +#define TILECTL_BACKSNOOP_DIS (1 << 3)
/* * Instruction and interrupt control regs @@ -358,10 +358,10 @@ #define RING_HWS_PGA(base) ((base)+0x80) #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) #define ARB_MODE 0x04030 -#define ARB_MODE_SWIZZLE_SNB (1<<4) -#define ARB_MODE_SWIZZLE_IVB (1<<5) -#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) -#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) +#define ARB_MODE_SWIZZLE_SNB (1<<4) +#define ARB_MODE_SWIZZLE_IVB (1<<5) +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) #define RENDER_HWS_PGA_GEN7 (0x04080) #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) #define DONE_REG 0x40b0 @@ -370,21 +370,21 @@ #define RING_ACTHD(base) ((base)+0x74) #define RING_NOPID(base) ((base)+0x94) #define RING_IMR(base) ((base)+0xa8) -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ -#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ -#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ +#define TAIL_ADDR 0x001FFFF8 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ +#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ #if 0 #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 @@ -411,7 +411,7 @@ #define HWS_ADDRESS_MASK 0xfffff000 #define HWS_START_ADDRESS_SHIFT 4 #define PWRCTXA 0x2088 /* 965GM+ only */ -#define PWRCTX_EN (1<<0) +#define PWRCTX_EN (1<<0) #define IPEIR 0x02088 #define IPEHR 0x0208c #define INSTDONE 0x02090 @@ -440,12 +440,12 @@ #define GFX_MODE 0x02520 #define GFX_MODE_GEN7 0x0229c #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) -#define GFX_RUN_LIST_ENABLE (1<<15) -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) -#define GFX_SURFACE_FAULT_ENABLE (1<<12) -#define GFX_REPLAY_MODE (1<<11) -#define GFX_PSMI_GRANULARITY (1<<10) -#define GFX_PPGTT_ENABLE (1<<9) +#define GFX_RUN_LIST_ENABLE (1<<15) +#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) +#define GFX_SURFACE_FAULT_ENABLE (1<<12) +#define GFX_REPLAY_MODE (1<<11) +#define GFX_PSMI_GRANULARITY (1<<10) +#define GFX_PPGTT_ENABLE (1<<9)
#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) @@ -455,163 +455,163 @@ #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) +#define I915_DISPLAY_PORT_INTERRUPT (1<<17) +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ +#define I915_HWB_OOM_INTERRUPT (1<<13) +#define I915_SYNC_STATUS_INTERRUPT (1<<12) +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) +#define I915_DEBUG_INTERRUPT (1<<2) +#define I915_USER_INTERRUPT (1<<1) +#define I915_ASLE_INTERRUPT (1<<0) +#define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 #define ESR 0x020b8 -#define GM45_ERROR_PAGE_TABLE (1<<5) -#define GM45_ERROR_MEM_PRIV (1<<4) -#define I915_ERROR_PAGE_TABLE (1<<4) -#define GM45_ERROR_CP_PRIV (1<<3) -#define I915_ERROR_MEMORY_REFRESH (1<<1) -#define I915_ERROR_INSTRUCTION (1<<0) -#define INSTPM 0x020c0 -#define INSTPM_SELF_EN (1<<12) /* 915GM only */ -#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts +#define GM45_ERROR_PAGE_TABLE (1<<5) +#define GM45_ERROR_MEM_PRIV (1<<4) +#define I915_ERROR_PAGE_TABLE (1<<4) +#define GM45_ERROR_CP_PRIV (1<<3) +#define I915_ERROR_MEMORY_REFRESH (1<<1) +#define I915_ERROR_INSTRUCTION (1<<0) +#define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ +#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts will not assert AGPBUSY# and will only be delivered when out of C3. */ -#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ -#define ACTHD 0x020c8 +#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ +#define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1<<31) -#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ -#define MM_BURST_LENGTH 0x00700000 +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ +#define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 -#define LM_BURST_LENGTH 0x00000700 +#define LM_BURST_LENGTH 0x00000700 #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ +#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) +#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
/* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) */ -#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) +#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
/* Block grant count for isoch requests when block count is * set to a finite value. */ -#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) -#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ -#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ -#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ -#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ +#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) +#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ +#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ +#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ +#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
/* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. */ -#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) +#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
/* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. */ -#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) +#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
/* Enables non-sequential data reads through arbiter */ -#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) +#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
/* Disable FSB snooping of cacheable write cycles from binner/render * command stream */ -#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) +#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
/* Arbiter time slice for non-isoch streams */ -#define MI_ARB_TIME_SLICE_MASK (7 << 5) -#define MI_ARB_TIME_SLICE_1 (0 << 5) -#define MI_ARB_TIME_SLICE_2 (1 << 5) -#define MI_ARB_TIME_SLICE_4 (2 << 5) -#define MI_ARB_TIME_SLICE_6 (3 << 5) -#define MI_ARB_TIME_SLICE_8 (4 << 5) -#define MI_ARB_TIME_SLICE_10 (5 << 5) -#define MI_ARB_TIME_SLICE_14 (6 << 5) -#define MI_ARB_TIME_SLICE_16 (7 << 5) +#define MI_ARB_TIME_SLICE_MASK (7 << 5) +#define MI_ARB_TIME_SLICE_1 (0 << 5) +#define MI_ARB_TIME_SLICE_2 (1 << 5) +#define MI_ARB_TIME_SLICE_4 (2 << 5) +#define MI_ARB_TIME_SLICE_6 (3 << 5) +#define MI_ARB_TIME_SLICE_8 (4 << 5) +#define MI_ARB_TIME_SLICE_10 (5 << 5) +#define MI_ARB_TIME_SLICE_14 (6 << 5) +#define MI_ARB_TIME_SLICE_16 (7 << 5)
/* Low priority grace period page size */ -#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ -#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) +#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ +#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
/* Disable display A/B trickle feed */ -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
/* Set display plane priority */ -#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ -#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ +#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ +#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_MASK_SHIFT 16 +#define CM0_IZ_OPT_DISABLE (1<<6) +#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) +#define CM0_DEPTH_EVICT_DISABLE (1<<4) +#define CM0_COLOR_EVICT_DISABLE (1<<3) +#define CM0_DEPTH_WRITE_DISABLE (1<<1) +#define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ #define ECOSKPD 0x021d0 -#define ECO_GATING_CX_ONLY (1<<3) -#define ECO_FLIP_DONE (1<<0) +#define ECO_GATING_CX_ONLY (1<<3) +#define ECO_FLIP_DONE (1<<0)
/* GEN6 interrupt control */ #define GEN6_RENDER_HWSTAM 0x2098 #define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
#define GEN6_BLITTER_HWSTAM 0x22098 #define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
#define GEN6_BLITTER_ECOSKPD 0x221d0 -#define GEN6_BLITTER_LOCK_SHIFT 16 -#define GEN6_BLITTER_FBC_NOTIFY (1<<3) +#define GEN6_BLITTER_LOCK_SHIFT 16 +#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 +#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
#define GEN6_BSD_HWSTAM 0x12098 #define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) +#define GEN6_BSD_USER_INTERRUPT (1 << 12)
#define GEN6_BSD_RNCID 0x12198
@@ -622,29 +622,29 @@ #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ #define FBC_LL_BASE 0x03204 /* 4k page aligned */ #define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_C3_IDLE (1<<13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_C3_IDLE (1<<13) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) +#define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) #define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) #define FBC_FENCE_OFF 0x0321b #define FBC_TAG 0x03300
@@ -653,45 +653,45 @@ /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE 0x3200 #define DPFC_CONTROL 0x3208 -#define DPFC_CTL_EN (1<<31) -#define DPFC_CTL_PLANEA (0<<30) -#define DPFC_CTL_PLANEB (1<<30) -#define DPFC_CTL_FENCE_EN (1<<29) -#define DPFC_CTL_PERSISTENT_MODE (1<<25) -#define DPFC_SR_EN (1<<10) -#define DPFC_CTL_LIMIT_1X (0<<6) -#define DPFC_CTL_LIMIT_2X (1<<6) -#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_PERSISTENT_MODE (1<<25) +#define DPFC_SR_EN (1<<10) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) #define DPFC_RECOMP_CTL 0x320c -#define DPFC_RECOMP_STALL_EN (1<<27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) #define DPFC_STATUS 0x3210 -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) #define DPFC_STATUS2 0x3214 #define DPFC_FENCE_YOFF 0x3218 #define DPFC_CHICKEN 0x3224 -#define DPFC_HT_MODIFY (1<<31) +#define DPFC_HT_MODIFY (1<<31)
/* Framebuffer compression for Ironlake */ #define ILK_DPFC_CB_BASE 0x43200 #define ILK_DPFC_CONTROL 0x43208 /* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) +#define DPFC_RESERVED (0x1FFFFF00) #define ILK_DPFC_RECOMP_CTL 0x4320c #define ILK_DPFC_STATUS 0x43210 #define ILK_DPFC_FENCE_YOFF 0x43218 #define ILK_DPFC_CHICKEN 0x43224 #define ILK_FBC_RT_BASE 0x2128 -#define ILK_FBC_RT_VALID (1<<0) +#define ILK_FBC_RT_VALID (1<<0)
#define ILK_DISPLAY_CHICKEN1 0x42000 -#define ILK_FBCQ_DIS (1<<22) +#define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21)
@@ -701,7 +701,7 @@ * The following two registers are of type GTTMMADR */ #define SNB_DPFC_CTL_SA 0x100100 -#define SNB_CPU_FENCE_ENABLE (1<<29) +#define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104
@@ -732,52 +732,52 @@ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
#define GMBUS0 0x5100 /* clock/port select */ -#define GMBUS_RATE_100KHZ (0<<8) -#define GMBUS_RATE_50KHZ (1<<8) -#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ -#define GMBUS_RATE_MASK (3<<8) -#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) -#define GMBUS_PORT_MASK 7 +#define GMBUS_RATE_100KHZ (0<<8) +#define GMBUS_RATE_50KHZ (1<<8) +#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ +#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ +#define GMBUS_RATE_MASK (3<<8) +#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ +#define GMBUS_PORT_DISABLED 0 +#define GMBUS_PORT_SSC 1 +#define GMBUS_PORT_VGADDC 2 +#define GMBUS_PORT_PANEL 3 +#define GMBUS_PORT_DPC 4 /* HDMIC */ +#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PORT_DPD 6 /* HDMID */ +#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ +#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PORT_MASK 7 #define GMBUS1 0x5104 /* command/status */ -#define GMBUS_SW_CLR_INT (1<<31) -#define GMBUS_SW_RDY (1<<30) -#define GMBUS_ENT (1<<29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0<<25) -#define GMBUS_CYCLE_WAIT (1<<25) -#define GMBUS_CYCLE_INDEX (2<<25) -#define GMBUS_CYCLE_STOP (4<<25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1<<0) -#define GMBUS_SLAVE_WRITE (0<<0) +#define GMBUS_SW_CLR_INT (1<<31) +#define GMBUS_SW_RDY (1<<30) +#define GMBUS_ENT (1<<29) /* enable timeout */ +#define GMBUS_CYCLE_NONE (0<<25) +#define GMBUS_CYCLE_WAIT (1<<25) +#define GMBUS_CYCLE_INDEX (2<<25) +#define GMBUS_CYCLE_STOP (4<<25) +#define GMBUS_BYTE_COUNT_SHIFT 16 +#define GMBUS_SLAVE_INDEX_SHIFT 8 +#define GMBUS_SLAVE_ADDR_SHIFT 1 +#define GMBUS_SLAVE_READ (1<<0) +#define GMBUS_SLAVE_WRITE (0<<0) #define GMBUS2 0x5108 /* status */ -#define GMBUS_INUSE (1<<15) -#define GMBUS_HW_WAIT_PHASE (1<<14) -#define GMBUS_STALL_TIMEOUT (1<<13) -#define GMBUS_INT (1<<12) -#define GMBUS_HW_RDY (1<<11) -#define GMBUS_SATOER (1<<10) -#define GMBUS_ACTIVE (1<<9) +#define GMBUS_INUSE (1<<15) +#define GMBUS_HW_WAIT_PHASE (1<<14) +#define GMBUS_STALL_TIMEOUT (1<<13) +#define GMBUS_INT (1<<12) +#define GMBUS_HW_RDY (1<<11) +#define GMBUS_SATOER (1<<10) +#define GMBUS_ACTIVE (1<<9) #define GMBUS3 0x510c /* data buffer bytes 3-0 */ #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ -#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) -#define GMBUS_NAK_EN (1<<3) -#define GMBUS_IDLE_EN (1<<2) -#define GMBUS_HW_WAIT_EN (1<<1) -#define GMBUS_HW_RDY_EN (1<<0) +#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) +#define GMBUS_NAK_EN (1<<3) +#define GMBUS_IDLE_EN (1<<2) +#define GMBUS_HW_WAIT_EN (1<<1) +#define GMBUS_HW_RDY_EN (1<<0) #define GMBUS5 0x5120 /* byte index */ -#define GMBUS_2BYTE_INDEX_EN (1<<31) +#define GMBUS_2BYTE_INDEX_EN (1<<31)
/* * Clock control & power management @@ -786,31 +786,31 @@ #define VGA0 0x6000 #define VGA1 0x6004 #define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) +#define VGA0_PD_P2_DIV_4 (1 << 7) +#define VGA0_PD_P1_DIV_2 (1 << 5) +#define VGA0_PD_P1_SHIFT 0 +#define VGA0_PD_P1_MASK (0x1f << 0) +#define VGA1_PD_P2_DIV_4 (1 << 15) +#define VGA1_PD_P1_DIV_2 (1 << 13) +#define VGA1_PD_P1_SHIFT 8 +#define VGA1_PD_P1_MASK (0x1f << 8) #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_DVO_HIGH_SPEED (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
#define SRX_INDEX 0x3c4 #define SRX_DATA 0x3c5 @@ -829,29 +829,29 @@
/* Scratch pad debug 0 reg: */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 /* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 /* Ironlake */ -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
/* * Parallel to Serial Load Pulse phase selection. @@ -859,25 +859,25 @@ * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) /* * SDVO multiplier for 945G/GM. Not used on 965. */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 +#define SDVO_MULTIPLIER_MASK 0x000000ff +#define SDVO_MULTIPLIER_SHIFT_HIRES 4 +#define SDVO_MULTIPLIER_SHIFT_VGA 0 #define _DPLL_A_MD 0x0601c /* 965+ only */ /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 /* * SDVO/UDI pixel multiplier. * @@ -895,15 +895,15 @@ * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 #define _DPLL_B_MD 0x06020 /* 965+ only */ #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) #define _FPA0 0x06040 @@ -912,25 +912,25 @@ #define _FPB1 0x0604c #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 #define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +#define DPLLB_TEST_N_BYPASS (1 << 19) +#define DPLLB_TEST_M_BYPASS (1 << 18) +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +#define DPLLA_TEST_N_BYPASS (1 << 3) +#define DPLLA_TEST_M_BYPASS (1 << 2) +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 #define DSTATE_GFX_RESET_I830 (1<<6) #define DSTATE_PLL_D3_OFF (1<<3) @@ -1044,7 +1044,7 @@ #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) #define RAMCLK_GATE_D 0x6210 /* CRL only */ -#define DEUC 0x6214 /* CRL only */ +#define DEUC 0x6214 /* CRL only */
/* * Palette regs @@ -1078,7 +1078,7 @@ #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** Pineview MCH register contains DDR3 setting */ -#define CSHRDDR3CTL 0x101a8 +#define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL_DDR3 (1 << 2)
/** 965 MCH register controlling DRAM channel configuration */ @@ -1089,23 +1089,23 @@ #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) -#define MAD_DIMM_ECC_MASK (0x3 << 24) -#define MAD_DIMM_ECC_OFF (0x0 << 24) -#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) -#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) -#define MAD_DIMM_ECC_ON (0x3 << 24) -#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) -#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) -#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ -#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ -#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) -#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) -#define MAD_DIMM_A_SELECT (0x1 << 16) +#define MAD_DIMM_ECC_MASK (0x3 << 24) +#define MAD_DIMM_ECC_OFF (0x0 << 24) +#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) +#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) +#define MAD_DIMM_ECC_ON (0x3 << 24) +#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) +#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) +#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ +#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ +#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) +#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) +#define MAD_DIMM_A_SELECT (0x1 << 16) /* DIMM sizes are in multiples of 256mb. */ -#define MAD_DIMM_B_SIZE_SHIFT 8 -#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) -#define MAD_DIMM_A_SIZE_SHIFT 0 -#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) +#define MAD_DIMM_B_SIZE_SHIFT 8 +#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) +#define MAD_DIMM_A_SIZE_SHIFT 0 +#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
/* Clocking configuration register */ @@ -1126,194 +1126,194 @@ #define CLKCFG_MEM_MASK (7 << 4)
#define TSC1 0x11001 -#define TSE (1<<0) +#define TSE (1<<0) #define TR1 0x11006 #define TSFS 0x11020 -#define TSFS_SLOPE_MASK 0x0000ff00 -#define TSFS_SLOPE_SHIFT 8 -#define TSFS_INTR_MASK 0x000000ff +#define TSFS_SLOPE_MASK 0x0000ff00 +#define TSFS_SLOPE_SHIFT 8 +#define TSFS_INTR_MASK 0x000000ff
#define CRSTANDVID 0x11100 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ -#define PXVFREQ_PX_MASK 0x7f000000 -#define PXVFREQ_PX_SHIFT 24 +#define PXVFREQ_PX_MASK 0x7f000000 +#define PXVFREQ_PX_SHIFT 24 #define VIDFREQ_BASE 0x11110 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ #define VIDFREQ2 0x11114 #define VIDFREQ3 0x11118 #define VIDFREQ4 0x1111c -#define VIDFREQ_P0_MASK 0x1f000000 -#define VIDFREQ_P0_SHIFT 24 -#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 -#define VIDFREQ_P0_CSCLK_SHIFT 20 -#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 -#define VIDFREQ_P0_CRCLK_SHIFT 16 -#define VIDFREQ_P1_MASK 0x00001f00 -#define VIDFREQ_P1_SHIFT 8 -#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 -#define VIDFREQ_P1_CSCLK_SHIFT 4 -#define VIDFREQ_P1_CRCLK_MASK 0x0000000f +#define VIDFREQ_P0_MASK 0x1f000000 +#define VIDFREQ_P0_SHIFT 24 +#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 +#define VIDFREQ_P0_CSCLK_SHIFT 20 +#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 +#define VIDFREQ_P0_CRCLK_SHIFT 16 +#define VIDFREQ_P1_MASK 0x00001f00 +#define VIDFREQ_P1_SHIFT 8 +#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 +#define VIDFREQ_P1_CSCLK_SHIFT 4 +#define VIDFREQ_P1_CRCLK_MASK 0x0000000f #define INTTOEXT_BASE_ILK 0x11300 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ -#define INTTOEXT_MAP3_SHIFT 24 -#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) -#define INTTOEXT_MAP2_SHIFT 16 -#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) -#define INTTOEXT_MAP1_SHIFT 8 -#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) -#define INTTOEXT_MAP0_SHIFT 0 -#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) +#define INTTOEXT_MAP3_SHIFT 24 +#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) +#define INTTOEXT_MAP2_SHIFT 16 +#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) +#define INTTOEXT_MAP1_SHIFT 8 +#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) +#define INTTOEXT_MAP0_SHIFT 0 +#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) #define MEMSWCTL 0x11170 /* Ironlake only */ -#define MEMCTL_CMD_MASK 0xe000 -#define MEMCTL_CMD_SHIFT 13 -#define MEMCTL_CMD_RCLK_OFF 0 -#define MEMCTL_CMD_RCLK_ON 1 -#define MEMCTL_CMD_CHFREQ 2 -#define MEMCTL_CMD_CHVID 3 -#define MEMCTL_CMD_VMMOFF 4 -#define MEMCTL_CMD_VMMON 5 -#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears - when command complete */ -#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ -#define MEMCTL_FREQ_SHIFT 8 -#define MEMCTL_SFCAVM (1<<7) -#define MEMCTL_TGT_VID_MASK 0x007f +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears + when command complete */ +#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ +#define MEMCTL_FREQ_SHIFT 8 +#define MEMCTL_SFCAVM (1<<7) +#define MEMCTL_TGT_VID_MASK 0x007f #define MEMIHYST 0x1117c #define MEMINTREN 0x11180 /* 16 bits */ -#define MEMINT_RSEXIT_EN (1<<8) -#define MEMINT_CX_SUPR_EN (1<<7) -#define MEMINT_CONT_BUSY_EN (1<<6) -#define MEMINT_AVG_BUSY_EN (1<<5) -#define MEMINT_EVAL_CHG_EN (1<<4) -#define MEMINT_MON_IDLE_EN (1<<3) -#define MEMINT_UP_EVAL_EN (1<<2) -#define MEMINT_DOWN_EVAL_EN (1<<1) -#define MEMINT_SW_CMD_EN (1<<0) +#define MEMINT_RSEXIT_EN (1<<8) +#define MEMINT_CX_SUPR_EN (1<<7) +#define MEMINT_CONT_BUSY_EN (1<<6) +#define MEMINT_AVG_BUSY_EN (1<<5) +#define MEMINT_EVAL_CHG_EN (1<<4) +#define MEMINT_MON_IDLE_EN (1<<3) +#define MEMINT_UP_EVAL_EN (1<<2) +#define MEMINT_DOWN_EVAL_EN (1<<1) +#define MEMINT_SW_CMD_EN (1<<0) #define MEMINTRSTR 0x11182 /* 16 bits */ -#define MEM_RSEXIT_MASK 0xc000 -#define MEM_RSEXIT_SHIFT 14 -#define MEM_CONT_BUSY_MASK 0x3000 -#define MEM_CONT_BUSY_SHIFT 12 -#define MEM_AVG_BUSY_MASK 0x0c00 -#define MEM_AVG_BUSY_SHIFT 10 -#define MEM_EVAL_CHG_MASK 0x0300 -#define MEM_EVAL_BUSY_SHIFT 8 -#define MEM_MON_IDLE_MASK 0x00c0 -#define MEM_MON_IDLE_SHIFT 6 -#define MEM_UP_EVAL_MASK 0x0030 -#define MEM_UP_EVAL_SHIFT 4 -#define MEM_DOWN_EVAL_MASK 0x000c -#define MEM_DOWN_EVAL_SHIFT 2 -#define MEM_SW_CMD_MASK 0x0003 -#define MEM_INT_STEER_GFX 0 -#define MEM_INT_STEER_CMR 1 -#define MEM_INT_STEER_SMI 2 -#define MEM_INT_STEER_SCI 3 +#define MEM_RSEXIT_MASK 0xc000 +#define MEM_RSEXIT_SHIFT 14 +#define MEM_CONT_BUSY_MASK 0x3000 +#define MEM_CONT_BUSY_SHIFT 12 +#define MEM_AVG_BUSY_MASK 0x0c00 +#define MEM_AVG_BUSY_SHIFT 10 +#define MEM_EVAL_CHG_MASK 0x0300 +#define MEM_EVAL_BUSY_SHIFT 8 +#define MEM_MON_IDLE_MASK 0x00c0 +#define MEM_MON_IDLE_SHIFT 6 +#define MEM_UP_EVAL_MASK 0x0030 +#define MEM_UP_EVAL_SHIFT 4 +#define MEM_DOWN_EVAL_MASK 0x000c +#define MEM_DOWN_EVAL_SHIFT 2 +#define MEM_SW_CMD_MASK 0x0003 +#define MEM_INT_STEER_GFX 0 +#define MEM_INT_STEER_CMR 1 +#define MEM_INT_STEER_SMI 2 +#define MEM_INT_STEER_SCI 3 #define MEMINTRSTS 0x11184 -#define MEMINT_RSEXIT (1<<7) -#define MEMINT_CONT_BUSY (1<<6) -#define MEMINT_AVG_BUSY (1<<5) -#define MEMINT_EVAL_CHG (1<<4) -#define MEMINT_MON_IDLE (1<<3) -#define MEMINT_UP_EVAL (1<<2) -#define MEMINT_DOWN_EVAL (1<<1) -#define MEMINT_SW_CMD (1<<0) +#define MEMINT_RSEXIT (1<<7) +#define MEMINT_CONT_BUSY (1<<6) +#define MEMINT_AVG_BUSY (1<<5) +#define MEMINT_EVAL_CHG (1<<4) +#define MEMINT_MON_IDLE (1<<3) +#define MEMINT_UP_EVAL (1<<2) +#define MEMINT_DOWN_EVAL (1<<1) +#define MEMINT_SW_CMD (1<<0) #define MEMMODECTL 0x11190 -#define MEMMODE_BOOST_EN (1<<31) -#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ -#define MEMMODE_BOOST_FREQ_SHIFT 24 -#define MEMMODE_IDLE_MODE_MASK 0x00030000 -#define MEMMODE_IDLE_MODE_SHIFT 16 -#define MEMMODE_IDLE_MODE_EVAL 0 -#define MEMMODE_IDLE_MODE_CONT 1 -#define MEMMODE_HWIDLE_EN (1<<15) -#define MEMMODE_SWMODE_EN (1<<14) -#define MEMMODE_RCLK_GATE (1<<13) -#define MEMMODE_HW_UPDATE (1<<12) -#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ -#define MEMMODE_FSTART_SHIFT 8 -#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ -#define MEMMODE_FMAX_SHIFT 4 -#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ +#define MEMMODE_BOOST_EN (1<<31) +#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ +#define MEMMODE_BOOST_FREQ_SHIFT 24 +#define MEMMODE_IDLE_MODE_MASK 0x00030000 +#define MEMMODE_IDLE_MODE_SHIFT 16 +#define MEMMODE_IDLE_MODE_EVAL 0 +#define MEMMODE_IDLE_MODE_CONT 1 +#define MEMMODE_HWIDLE_EN (1<<15) +#define MEMMODE_SWMODE_EN (1<<14) +#define MEMMODE_RCLK_GATE (1<<13) +#define MEMMODE_HW_UPDATE (1<<12) +#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ +#define MEMMODE_FSTART_SHIFT 8 +#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ +#define MEMMODE_FMAX_SHIFT 4 +#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ #define RCBMAXAVG 0x1119c #define MEMSWCTL2 0x1119e /* Cantiga only */ -#define SWMEMCMD_RENDER_OFF (0 << 13) -#define SWMEMCMD_RENDER_ON (1 << 13) -#define SWMEMCMD_SWFREQ (2 << 13) -#define SWMEMCMD_TARVID (3 << 13) -#define SWMEMCMD_VRM_OFF (4 << 13) -#define SWMEMCMD_VRM_ON (5 << 13) -#define CMDSTS (1<<12) -#define SFCAVM (1<<11) -#define SWFREQ_MASK 0x0380 /* P0-7 */ -#define SWFREQ_SHIFT 7 -#define TARVID_MASK 0x001f +#define SWMEMCMD_RENDER_OFF (0 << 13) +#define SWMEMCMD_RENDER_ON (1 << 13) +#define SWMEMCMD_SWFREQ (2 << 13) +#define SWMEMCMD_TARVID (3 << 13) +#define SWMEMCMD_VRM_OFF (4 << 13) +#define SWMEMCMD_VRM_ON (5 << 13) +#define CMDSTS (1<<12) +#define SFCAVM (1<<11) +#define SWFREQ_MASK 0x0380 /* P0-7 */ +#define SWFREQ_SHIFT 7 +#define TARVID_MASK 0x001f #define MEMSTAT_CTG 0x111a0 #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 #define RSTDBYCTL 0x111b8 -#define RS1EN (1<<31) -#define RS2EN (1<<30) -#define RS3EN (1<<29) -#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ -#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ -#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ -#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ -#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ -#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ -#define RSX_STATUS_MASK (7<<20) -#define RSX_STATUS_ON (0<<20) -#define RSX_STATUS_RC1 (1<<20) -#define RSX_STATUS_RC1E (2<<20) -#define RSX_STATUS_RS1 (3<<20) -#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ -#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ -#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ -#define RSX_STATUS_RSVD2 (7<<20) -#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ -#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ -#define JRSC (1<<17) /* rsx coupled to cpu c-state */ -#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ -#define RS1CONTSAV_MASK (3<<14) -#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ -#define RS1CONTSAV_RSVD (1<<14) -#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ -#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ -#define NORMSLEXLAT_MASK (3<<12) -#define SLOW_RS123 (0<<12) -#define SLOW_RS23 (1<<12) -#define SLOW_RS3 (2<<12) -#define NORMAL_RS123 (3<<12) -#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ -#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ -#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ -#define RS_CSTATE_MASK (3<<4) -#define RS_CSTATE_C367_RS1 (0<<4) -#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) -#define RS_CSTATE_RSVD (2<<4) -#define RS_CSTATE_C367_RS2 (3<<4) -#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ -#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ +#define RS1EN (1<<31) +#define RS2EN (1<<30) +#define RS3EN (1<<29) +#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ +#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ +#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ +#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ +#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ +#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ +#define RSX_STATUS_MASK (7<<20) +#define RSX_STATUS_ON (0<<20) +#define RSX_STATUS_RC1 (1<<20) +#define RSX_STATUS_RC1E (2<<20) +#define RSX_STATUS_RS1 (3<<20) +#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ +#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ +#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ +#define RSX_STATUS_RSVD2 (7<<20) +#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ +#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ +#define JRSC (1<<17) /* rsx coupled to cpu c-state */ +#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ +#define RS1CONTSAV_MASK (3<<14) +#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ +#define RS1CONTSAV_RSVD (1<<14) +#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ +#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ +#define NORMSLEXLAT_MASK (3<<12) +#define SLOW_RS123 (0<<12) +#define SLOW_RS23 (1<<12) +#define SLOW_RS3 (2<<12) +#define NORMAL_RS123 (3<<12) +#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ +#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ +#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ +#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ +#define RS_CSTATE_MASK (3<<4) +#define RS_CSTATE_C367_RS1 (0<<4) +#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) +#define RS_CSTATE_RSVD (2<<4) +#define RS_CSTATE_C367_RS2 (3<<4) +#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ +#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ #define VIDCTL 0x111c0 #define VIDSTS 0x111c8 #define VIDSTART 0x111cc /* 8 bits */ #define MEMSTAT_ILK 0x111f8 -#define MEMSTAT_VID_MASK 0x7f00 -#define MEMSTAT_VID_SHIFT 8 -#define MEMSTAT_PSTATE_MASK 0x00f8 -#define MEMSTAT_PSTATE_SHIFT 3 -#define MEMSTAT_MON_ACTV (1<<2) -#define MEMSTAT_SRC_CTL_MASK 0x0003 -#define MEMSTAT_SRC_CTL_CORE 0 -#define MEMSTAT_SRC_CTL_TRB 1 -#define MEMSTAT_SRC_CTL_THM 2 -#define MEMSTAT_SRC_CTL_STDBY 3 +#define MEMSTAT_VID_MASK 0x7f00 +#define MEMSTAT_VID_SHIFT 8 +#define MEMSTAT_PSTATE_MASK 0x00f8 +#define MEMSTAT_PSTATE_SHIFT 3 +#define MEMSTAT_MON_ACTV (1<<2) +#define MEMSTAT_SRC_CTL_MASK 0x0003 +#define MEMSTAT_SRC_CTL_CORE 0 +#define MEMSTAT_SRC_CTL_TRB 1 +#define MEMSTAT_SRC_CTL_THM 2 +#define MEMSTAT_SRC_CTL_STDBY 3 #define RCPREVBSYTUPAVG 0x113b8 #define RCPREVBSYTDNAVG 0x113bc #define PMMISC 0x11214 -#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ +#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ #define SDEW 0x1124c #define CSIEW0 0x11250 #define CSIEW1 0x11254 @@ -1330,9 +1330,9 @@ #define RPPREVBSYTUPAVG 0x113b8 #define RPPREVBSYTDNAVG 0x113bc #define ECR 0x11600 -#define ECR_GPFE (1<<31) -#define ECR_IMONE (1<<30) -#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ +#define ECR_GPFE (1<<31) +#define ECR_IMONE (1<<30) +#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ #define OGW0 0x11608 #define OGW1 0x1160c #define EG0 0x11610 @@ -1346,7 +1346,7 @@ #define PXW 0x11664 #define PXWL 0x11680 #define LCFUSE02 0x116c0 -#define LCFUSE_HIV_MASK 0x000000ff +#define LCFUSE_HIV_MASK 0x000000ff #define CSIPLL0 0x12c10 #define DDRMPLL1 0X12c20 #define PEG_BAND_GAP_DATA 0x14d68 @@ -1362,7 +1362,7 @@ * Logical Context regs */ #define CCID 0x2180 -#define CCID_EN (1<<0) +#define CCID_EN (1<<0) /* * Overlay regs */ @@ -1415,42 +1415,42 @@
/* VGA port control */ #define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 +#define ADPA_DPMS_MASK (~(3<<10)) +#define ADPA_DPMS_ON (0<<10) +#define ADPA_DPMS_SUSPEND (1<<10) +#define ADPA_DPMS_STANDBY (2<<10) +#define ADPA_DPMS_OFF (3<<10)
/* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 -#define HDMIB_HOTPLUG_INT_EN (1 << 29) -#define DPB_HOTPLUG_INT_EN (1 << 29) -#define HDMIC_HOTPLUG_INT_EN (1 << 28) -#define DPC_HOTPLUG_INT_EN (1 << 28) -#define HDMID_HOTPLUG_INT_EN (1 << 27) -#define DPD_HOTPLUG_INT_EN (1 << 27) -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +#define HDMIB_HOTPLUG_INT_EN (1 << 29) +#define DPB_HOTPLUG_INT_EN (1 << 29) +#define HDMIC_HOTPLUG_INT_EN (1 << 28) +#define DPC_HOTPLUG_INT_EN (1 << 28) +#define HDMID_HOTPLUG_INT_EN (1 << 27) +#define DPD_HOTPLUG_INT_EN (1 << 27) +#define SDVOB_HOTPLUG_INT_EN (1 << 26) +#define SDVOC_HOTPLUG_INT_EN (1 << 25) +#define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_HOTPLUG_INT_EN (1 << 9) +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) /* must use period 64 on GM45 according to docs */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) @@ -1467,28 +1467,28 @@ #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
#define PORT_HOTPLUG_STAT 0x61114 -#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) -#define DPB_HOTPLUG_INT_STATUS (1 << 29) -#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) -#define DPC_HOTPLUG_INT_STATUS (1 << 28) -#define HDMID_HOTPLUG_INT_STATUS (1 << 27) -#define DPD_HOTPLUG_INT_STATUS (1 << 27) -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) +#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +#define DPB_HOTPLUG_INT_STATUS (1 << 29) +#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +#define DPC_HOTPLUG_INT_STATUS (1 << 28) +#define HDMID_HOTPLUG_INT_STATUS (1 << 27) +#define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_HOTPLUG_INT_STATUS (1 << 11) +#define TV_HOTPLUG_INT_STATUS (1 << 10) +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
/* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) /** * 915G/GM SDVO pixel multiplier. * @@ -1496,62 +1496,62 @@ * * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_ENCODING_SDVO (0x0 << 10) -#define SDVO_ENCODING_HDMI (0x2 << 10) +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) /** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) -#define SDVO_COLOR_RANGE_16_235 (1 << 8) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVO_AUDIO_ENABLE (1 << 6) +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) +#define SDVO_COLOR_RANGE_16_235 (1 << 8) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) /** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) /** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
/* DVO port control */ #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) +#define DVO_ENABLE (1 << 31) +#define DVO_PIPE_B_SELECT (1 << 30) +#define DVO_PIPE_STALL_UNUSED (0 << 28) +#define DVO_PIPE_STALL (1 << 28) +#define DVO_PIPE_STALL_TV (2 << 28) +#define DVO_PIPE_STALL_MASK (3 << 28) +#define DVO_USE_VGA_SYNC (1 << 15) +#define DVO_DATA_ORDER_I740 (0 << 14) +#define DVO_DATA_ORDER_FP (1 << 14) +#define DVO_VSYNC_DISABLE (1 << 11) +#define DVO_HSYNC_DISABLE (1 << 10) +#define DVO_VSYNC_TRISTATE (1 << 9) +#define DVO_HSYNC_TRISTATE (1 << 8) +#define DVO_BORDER_ENABLE (1 << 7) +#define DVO_DATA_ORDER_GBRG (1 << 6) +#define DVO_DATA_ORDER_RGGB (0 << 6) +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define DVO_BLANK_ACTIVE_HIGH (1 << 2) +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ +#define DVO_PRESERVE_MASK (0x7<<24) #define DVOA_SRCDIM 0x61124 #define DVOB_SRCDIM 0x61144 #define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */ #define LVDS 0x61180 @@ -1559,70 +1559,70 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1 << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -#define LVDS_PIPE_MASK (1 << 30) -#define LVDS_PIPE(pipe) ((pipe) << 30) +#define LVDS_PIPEB_SELECT (1 << 30) +#define LVDS_PIPE_MASK (1 << 30) +#define LVDS_PIPE(pipe) ((pipe) << 30) /* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) +#define LVDS_ENABLE_DITHER (1 << 25) /* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) +#define LVDS_VSYNC_POLARITY (1 << 21) +#define LVDS_HSYNC_POLARITY (1 << 20)
/* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_BORDER_ENABLE (1 << 15) /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) +#define LVDS_A3_POWER_MASK (3 << 6) +#define LVDS_A3_POWER_DOWN (0 << 6) +#define LVDS_A3_POWER_UP (3 << 6) /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) +#define LVDS_CLKB_POWER_MASK (3 << 4) +#define LVDS_CLKB_POWER_DOWN (0 << 4) +#define LVDS_CLKB_POWER_UP (3 << 4) /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) +#define LVDS_B0B3_POWER_MASK (3 << 2) +#define LVDS_B0B3_POWER_DOWN (0 << 2) +#define LVDS_B0B3_POWER_UP (3 << 2)
/* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT_B (1 << 29) -#define VIDEO_DIP_PORT_C (2 << 29) -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT_B (1 << 29) +#define VIDEO_DIP_PORT_C (2 << 29) +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
/* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1 << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1630,51 +1630,51 @@ * - pipe enabled * - LVDS/DVOB/DVOC on */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_POWER_UP (1 << 28) -#define PP_SEQUENCE_POWER_DOWN (2 << 28) -#define PP_SEQUENCE_MASK (3 << 28) -#define PP_SEQUENCE_SHIFT 28 -#define PP_CYCLE_DELAY_ACTIVE (1 << 27) -#define PP_SEQUENCE_STATE_MASK 0x0000000f -#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) -#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) -#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) -#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) -#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) -#define PP_SEQUENCE_STATE_RESET (0xf << 0) +#define PP_READY (1 << 30) +#define PP_SEQUENCE_NONE (0 << 28) +#define PP_SEQUENCE_POWER_UP (1 << 28) +#define PP_SEQUENCE_POWER_DOWN (2 << 28) +#define PP_SEQUENCE_MASK (3 << 28) +#define PP_SEQUENCE_SHIFT 28 +#define PP_CYCLE_DELAY_ACTIVE (1 << 27) +#define PP_SEQUENCE_STATE_MASK 0x0000000f +#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) +#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) +#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) +#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) +#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) +#define PP_SEQUENCE_STATE_RESET (0xf << 0) #define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) +#define POWER_TARGET_ON (1 << 0) #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210
/* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_FILTER_FUZZY (0 << 24) -#define PFIT_SCALING_AUTO (0 << 26) -#define PFIT_SCALING_PROGRAMMED (1 << 26) -#define PFIT_SCALING_PILLAR (2 << 26) -#define PFIT_SCALING_LETTER (3 << 26) +#define PFIT_ENABLE (1 << 31) +#define PFIT_PIPE_MASK (3 << 29) +#define PFIT_PIPE_SHIFT 29 +#define VERT_INTERP_DISABLE (0 << 10) +#define VERT_INTERP_BILINEAR (1 << 10) +#define VERT_INTERP_MASK (3 << 10) +#define VERT_AUTO_SCALE (1 << 9) +#define HORIZ_INTERP_DISABLE (0 << 6) +#define HORIZ_INTERP_BILINEAR (1 << 6) +#define HORIZ_INTERP_MASK (3 << 6) +#define HORIZ_AUTO_SCALE (1 << 5) +#define PANEL_8TO6_DITHER_ENABLE (1 << 3) +#define PFIT_FILTER_FUZZY (0 << 24) +#define PFIT_SCALING_AUTO (0 << 26) +#define PFIT_SCALING_PROGRAMMED (1 << 26) +#define PFIT_SCALING_PILLAR (2 << 26) +#define PFIT_SCALING_LETTER (3 << 26) #define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 +#define PFIT_VERT_SCALE_MASK 0xfff00000 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 /* Pre-965 */ #define PFIT_VERT_SCALE_SHIFT 20 #define PFIT_VERT_SCALE_MASK 0xfff00000 @@ -1690,17 +1690,17 @@
/* Backlight control */ #define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) +#define BLM_COMBINATION_MODE (1 << 30) /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. @@ -1708,8 +1708,8 @@ * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
#define BLC_HIST_CTL 0x61260
@@ -2199,82 +2199,82 @@ #define DP_C 0x64200 #define DP_D 0x64300
-#define DP_PORT_EN (1 << 31) -#define DP_PIPEB_SELECT (1 << 30) -#define DP_PIPE_MASK (1 << 30) +#define DP_PORT_EN (1 << 31) +#define DP_PIPEB_SELECT (1 << 30) +#define DP_PIPE_MASK (1 << 30)
/* Link training mode - select a suitable mode for each stage */ -#define DP_LINK_TRAIN_PAT_1 (0 << 28) -#define DP_LINK_TRAIN_PAT_2 (1 << 28) -#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) -#define DP_LINK_TRAIN_OFF (3 << 28) -#define DP_LINK_TRAIN_MASK (3 << 28) -#define DP_LINK_TRAIN_SHIFT 28 +#define DP_LINK_TRAIN_PAT_1 (0 << 28) +#define DP_LINK_TRAIN_PAT_2 (1 << 28) +#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) +#define DP_LINK_TRAIN_OFF (3 << 28) +#define DP_LINK_TRAIN_MASK (3 << 28) +#define DP_LINK_TRAIN_SHIFT 28
/* CPT Link training mode */ -#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) -#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) -#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) -#define DP_LINK_TRAIN_OFF_CPT (3 << 8) -#define DP_LINK_TRAIN_MASK_CPT (7 << 8) -#define DP_LINK_TRAIN_SHIFT_CPT 8 +#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) +#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) +#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) +#define DP_LINK_TRAIN_OFF_CPT (3 << 8) +#define DP_LINK_TRAIN_MASK_CPT (7 << 8) +#define DP_LINK_TRAIN_SHIFT_CPT 8
/* Signal voltages. These are mostly controlled by the other end */ -#define DP_VOLTAGE_0_4 (0 << 25) -#define DP_VOLTAGE_0_6 (1 << 25) -#define DP_VOLTAGE_0_8 (2 << 25) -#define DP_VOLTAGE_1_2 (3 << 25) -#define DP_VOLTAGE_MASK (7 << 25) -#define DP_VOLTAGE_SHIFT 25 +#define DP_VOLTAGE_0_4 (0 << 25) +#define DP_VOLTAGE_0_6 (1 << 25) +#define DP_VOLTAGE_0_8 (2 << 25) +#define DP_VOLTAGE_1_2 (3 << 25) +#define DP_VOLTAGE_MASK (7 << 25) +#define DP_VOLTAGE_SHIFT 25
/* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ -#define DP_PRE_EMPHASIS_0 (0 << 22) -#define DP_PRE_EMPHASIS_3_5 (1 << 22) -#define DP_PRE_EMPHASIS_6 (2 << 22) -#define DP_PRE_EMPHASIS_9_5 (3 << 22) -#define DP_PRE_EMPHASIS_MASK (7 << 22) -#define DP_PRE_EMPHASIS_SHIFT 22 +#define DP_PRE_EMPHASIS_0 (0 << 22) +#define DP_PRE_EMPHASIS_3_5 (1 << 22) +#define DP_PRE_EMPHASIS_6 (2 << 22) +#define DP_PRE_EMPHASIS_9_5 (3 << 22) +#define DP_PRE_EMPHASIS_MASK (7 << 22) +#define DP_PRE_EMPHASIS_SHIFT 22
/* How many wires to use. I guess 3 was too hard */ -#define DP_PORT_WIDTH_1 (0 << 19) -#define DP_PORT_WIDTH_2 (1 << 19) -#define DP_PORT_WIDTH_4 (3 << 19) -#define DP_PORT_WIDTH_MASK (7 << 19) +#define DP_PORT_WIDTH_1 (0 << 19) +#define DP_PORT_WIDTH_2 (1 << 19) +#define DP_PORT_WIDTH_4 (3 << 19) +#define DP_PORT_WIDTH_MASK (7 << 19)
/* Mystic DPCD version 1.1 special mode */ -#define DP_ENHANCED_FRAMING (1 << 18) +#define DP_ENHANCED_FRAMING (1 << 18)
/* eDP */ -#define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) -#define DP_PLL_FREQ_MASK (3 << 16) +#define DP_PLL_FREQ_270MHZ (0 << 16) +#define DP_PLL_FREQ_160MHZ (1 << 16) +#define DP_PLL_FREQ_MASK (3 << 16)
/** locked once port is enabled */ -#define DP_PORT_REVERSAL (1 << 15) +#define DP_PORT_REVERSAL (1 << 15)
/* eDP */ -#define DP_PLL_ENABLE (1 << 14) +#define DP_PLL_ENABLE (1 << 14)
/** sends the clock on lane 15 of the PEG for debug */ -#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) +#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
-#define DP_SCRAMBLING_DISABLE (1 << 12) -#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) +#define DP_SCRAMBLING_DISABLE (1 << 12) +#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
/** limit RGB values to avoid confusing TVs */ -#define DP_COLOR_RANGE_16_235 (1 << 8) +#define DP_COLOR_RANGE_16_235 (1 << 8)
/** Turn on the audio link */ -#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) +#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
/** vs and hs sync polarity */ -#define DP_SYNC_VS_HIGH (1 << 4) -#define DP_SYNC_HS_HIGH (1 << 3) +#define DP_SYNC_VS_HIGH (1 << 4) +#define DP_SYNC_HS_HIGH (1 << 3)
/** A fantasy */ -#define DP_DETECTED (1 << 2) +#define DP_DETECTED (1 << 2)
/** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported @@ -2309,27 +2309,27 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_DONE (1 << 30) +#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) +#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) +#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) +#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) +#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) +#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) +#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) +#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) +#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
/* * Computing GMCH M and N values for the Display Port link @@ -2348,14 +2348,14 @@ #define _PIPEB_GMCH_DATA_M 0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
-#define PIPE_GMCH_DATA_M_MASK (0xffffff) +#define PIPE_GMCH_DATA_M_MASK (0xffffff)
#define _PIPEA_GMCH_DATA_N 0x70054 #define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) +#define PIPE_GMCH_DATA_N_MASK (0xffffff)
/* * Computing Link M and N values for the Display Port link @@ -2370,11 +2370,11 @@
#define _PIPEA_DP_LINK_M 0x70060 #define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) +#define PIPEA_DP_LINK_M_MASK (0xffffff)
#define _PIPEA_DP_LINK_N 0x70064 #define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) +#define PIPEA_DP_LINK_N_MASK (0xffffff)
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) @@ -2385,81 +2385,81 @@
/* Pipe A */ #define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff +#define DSL_LINEMASK 0x00000fff #define _PIPEACONF 0x70008 -#define PIPECONF_ENABLE (1<<31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1<<25) -#define PIPECONF_PALETTE 0 -#define PIPECONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_ENABLE (1<<31) +#define PIPECONF_DISABLE 0 +#define PIPECONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) +#define PIPECONF_SINGLE_WIDE 0 +#define PIPECONF_PIPE_UNLOCKED 0 +#define PIPECONF_PIPE_LOCKED (1<<25) +#define PIPECONF_PALETTE 0 +#define PIPECONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_INTERLACE_MASK (7 << 21) /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ /* Ironlake and later have a complete new set of values for interlaced. PFIT * means panel fitter required, PF means progressive fetch, DBL means power * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_CXSR_DOWNCLOCK (1<<16) -#define PIPECONF_BPP_MASK (0x000000e0) -#define PIPECONF_BPP_8 (0<<5) -#define PIPECONF_BPP_10 (1<<5) -#define PIPECONF_BPP_6 (2<<5) -#define PIPECONF_BPP_12 (3<<5) -#define PIPECONF_DITHER_EN (1<<4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0<<2) -#define PIPECONF_DITHER_TYPE_ST1 (1<<2) -#define PIPECONF_DITHER_TYPE_ST2 (2<<2) -#define PIPECONF_DITHER_TYPE_TEMP (3<<2) +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) +#define PIPECONF_INTERLACED_ILK (3 << 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_BPP_MASK (0x000000e0) +#define PIPECONF_BPP_8 (0<<5) +#define PIPECONF_BPP_10 (1<<5) +#define PIPECONF_BPP_6 (2<<5) +#define PIPECONF_BPP_12 (3<<5) +#define PIPECONF_DITHER_EN (1<<4) +#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) +#define PIPECONF_DITHER_TYPE_SP (0<<2) +#define PIPECONF_DITHER_TYPE_ST1 (1<<2) +#define PIPECONF_DITHER_TYPE_ST2 (2<<2) +#define PIPECONF_DITHER_TYPE_TEMP (3<<2) #define _PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ -#define PIPE_8BPC (0 << 5) -#define PIPE_10BPC (1 << 5) -#define PIPE_6BPC (2 << 5) -#define PIPE_12BPC (3 << 5) +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) +#define PIPE_CRC_ERROR_ENABLE (1UL<<29) +#define PIPE_CRC_DONE_ENABLE (1UL<<28) +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) +#define PIPE_DPST_EVENT_ENABLE (1UL<<23) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) +#define PIPE_DPST_EVENT_STATUS (1UL<<7) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) @@ -2469,33 +2469,33 @@ #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -#define DSPARB_BEND_SHIFT 9 /* on 855 */ -#define DSPARB_AEND_SHIFT 0 +#define DSPARB_CSTART_MASK (0x7f << 7) +#define DSPARB_CSTART_SHIFT 7 +#define DSPARB_BSTART_MASK (0x7f) +#define DSPARB_BSTART_SHIFT 0 +#define DSPARB_BEND_SHIFT 9 /* on 855 */ +#define DSPARB_AEND_SHIFT 0
#define DSPFW1 0x70034 -#define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) -#define DSPFW_CURSORB_SHIFT 16 -#define DSPFW_CURSORB_MASK (0x3f<<16) -#define DSPFW_PLANEB_SHIFT 8 -#define DSPFW_PLANEB_MASK (0x7f<<8) -#define DSPFW_PLANEA_MASK (0x7f) +#define DSPFW_SR_SHIFT 23 +#define DSPFW_SR_MASK (0x1ff<<23) +#define DSPFW_CURSORB_SHIFT 16 +#define DSPFW_CURSORB_MASK (0x3f<<16) +#define DSPFW_PLANEB_SHIFT 8 +#define DSPFW_PLANEB_MASK (0x7f<<8) +#define DSPFW_PLANEA_MASK (0x7f) #define DSPFW2 0x70038 -#define DSPFW_CURSORA_MASK 0x00003f00 -#define DSPFW_CURSORA_SHIFT 8 -#define DSPFW_PLANEC_MASK (0x7f) +#define DSPFW_CURSORA_MASK 0x00003f00 +#define DSPFW_CURSORA_SHIFT 8 +#define DSPFW_PLANEC_MASK (0x7f) #define DSPFW3 0x7003c -#define DSPFW_HPLL_SR_EN (1<<31) -#define DSPFW_CURSOR_SR_SHIFT 24 -#define PINEVIEW_SELF_REFRESH_EN (1<<30) -#define DSPFW_CURSOR_SR_MASK (0x3f<<24) -#define DSPFW_HPLL_CURSOR_SHIFT 16 -#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) -#define DSPFW_HPLL_SR_MASK (0x1ff) +#define DSPFW_HPLL_SR_EN (1<<31) +#define DSPFW_CURSOR_SR_SHIFT 24 +#define PINEVIEW_SELF_REFRESH_EN (1<<30) +#define DSPFW_CURSOR_SR_MASK (0x3f<<24) +#define DSPFW_HPLL_CURSOR_SHIFT 16 +#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) +#define DSPFW_HPLL_SR_MASK (0x1ff)
/* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 @@ -2623,22 +2623,22 @@ * * do { * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; + * PIPE_FRAME_HIGH_SHIFT; * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); + * PIPE_FRAME_LOW_SHIFT); * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); + * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; */ -#define _PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define _PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 +#define _PIPEAFRAMEHIGH 0x70040 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 +#define _PIPEAFRAMEPIXEL 0x70044 +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_GM45 0x70040 #define _PIPEA_FLIPCOUNT_GM45 0x70044 @@ -2647,31 +2647,31 @@ /* Cursor A & B regs */ #define _CURACNTR 0x70080 /* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE 0x80000000 -#define CURSOR_GAMMA_ENABLE 0x40000000 -#define CURSOR_STRIDE_MASK 0x30000000 -#define CURSOR_FORMAT_SHIFT 24 -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) +#define CURSOR_ENABLE 0x80000000 +#define CURSOR_GAMMA_ENABLE 0x40000000 +#define CURSOR_STRIDE_MASK 0x30000000 +#define CURSOR_FORMAT_SHIFT 24 +#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) /* New style CUR*CNTR flags */ -#define CURSOR_MODE 0x27 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_PIPE_SELECT (1 << 28) -#define MCURSOR_PIPE_A 0x00 -#define MCURSOR_PIPE_B (1 << 28) -#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define CURSOR_MODE 0x27 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) +#define MCURSOR_PIPE_SELECT (1 << 28) +#define MCURSOR_PIPE_A 0x00 +#define MCURSOR_PIPE_B (1 << 28) +#define MCURSOR_GAMMA_ENABLE (1 << 26) #define _CURABASE 0x70084 #define _CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 #define CURSIZE 0x700a0 #define _CURBCNTR 0x700c0 #define _CURBBASE 0x700c4 @@ -2690,32 +2690,32 @@ #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */ -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_SHIFT 24 -#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ -#define DISPPLANE_TILED (1<<10) +#define _DSPACNTR 0x70180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_SHIFT 24 +#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ +#define DISPPLANE_TILED (1<<10) #define _DSPAADDR 0x70184 #define _DSPASTRIDE 0x70188 #define _DSPAPOS 0x7018C /* reserved */ @@ -2758,10 +2758,10 @@
/* Display B control */ #define _DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define _DSPBADDR 0x71184 #define _DSPBSTRIDE 0x71188 #define _DSPBPOS 0x7118C @@ -2771,23 +2771,23 @@
/* Sprite A control */ #define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) -#define DVS_GAMMA_ENABLE (1<<30) -#define DVS_PIXFORMAT_MASK (3<<25) -#define DVS_FORMAT_YUV422 (0<<25) -#define DVS_FORMAT_RGBX101010 (1<<25) -#define DVS_FORMAT_RGBX888 (2<<25) -#define DVS_FORMAT_RGBX161616 (3<<25) -#define DVS_SOURCE_KEY (1<<22) -#define DVS_RGB_ORDER_XBGR (1<<20) -#define DVS_YUV_BYTE_ORDER_MASK (3<<16) -#define DVS_YUV_ORDER_YUYV (0<<16) -#define DVS_YUV_ORDER_UYVY (1<<16) -#define DVS_YUV_ORDER_YVYU (2<<16) -#define DVS_YUV_ORDER_VYUY (3<<16) -#define DVS_DEST_KEY (1<<2) -#define DVS_TRICKLE_FEED_DISABLE (1<<14) -#define DVS_TILED (1<<10) +#define DVS_ENABLE (1<<31) +#define DVS_GAMMA_ENABLE (1<<30) +#define DVS_PIXFORMAT_MASK (3<<25) +#define DVS_FORMAT_YUV422 (0<<25) +#define DVS_FORMAT_RGBX101010 (1<<25) +#define DVS_FORMAT_RGBX888 (2<<25) +#define DVS_FORMAT_RGBX161616 (3<<25) +#define DVS_SOURCE_KEY (1<<22) +#define DVS_RGB_ORDER_XBGR (1<<20) +#define DVS_YUV_BYTE_ORDER_MASK (3<<16) +#define DVS_YUV_ORDER_YUYV (0<<16) +#define DVS_YUV_ORDER_UYVY (1<<16) +#define DVS_YUV_ORDER_YVYU (2<<16) +#define DVS_YUV_ORDER_VYUY (3<<16) +#define DVS_DEST_KEY (1<<2) +#define DVS_TRICKLE_FEED_DISABLE (1<<14) +#define DVS_TILED (1<<10) #define _DVSALINOFF 0x72184 #define _DVSASTRIDE 0x72188 #define _DVSAPOS 0x7218c @@ -2799,13 +2799,13 @@ #define _DVSATILEOFF 0x721a4 #define _DVSASURFLIVE 0x721ac #define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE (1<<31) -#define DVS_FILTER_MASK (3<<29) -#define DVS_FILTER_MEDIUM (0<<29) -#define DVS_FILTER_ENHANCING (1<<29) -#define DVS_FILTER_SOFTENING (2<<29) -#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) +#define DVS_SCALE_ENABLE (1<<31) +#define DVS_FILTER_MASK (3<<29) +#define DVS_FILTER_MEDIUM (0<<29) +#define DVS_FILTER_ENHANCING (1<<29) +#define DVS_FILTER_SOFTENING (2<<29) +#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) #define _DVSAGAMC 0x72300
#define _DVSBCNTR 0x73180 @@ -2835,29 +2835,29 @@ #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE (1<<31) -#define SPRITE_GAMMA_ENABLE (1<<30) -#define SPRITE_PIXFORMAT_MASK (7<<25) -#define SPRITE_FORMAT_YUV422 (0<<25) -#define SPRITE_FORMAT_RGBX101010 (1<<25) -#define SPRITE_FORMAT_RGBX888 (2<<25) -#define SPRITE_FORMAT_RGBX161616 (3<<25) -#define SPRITE_FORMAT_YUV444 (4<<25) -#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ -#define SPRITE_CSC_ENABLE (1<<24) -#define SPRITE_SOURCE_KEY (1<<22) -#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) -#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ -#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) -#define SPRITE_YUV_ORDER_YUYV (0<<16) -#define SPRITE_YUV_ORDER_UYVY (1<<16) -#define SPRITE_YUV_ORDER_YVYU (2<<16) -#define SPRITE_YUV_ORDER_VYUY (3<<16) -#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) -#define SPRITE_INT_GAMMA_ENABLE (1<<13) -#define SPRITE_TILED (1<<10) -#define SPRITE_DEST_KEY (1<<2) +#define SPRITE_ENABLE (1<<31) +#define SPRITE_GAMMA_ENABLE (1<<30) +#define SPRITE_PIXFORMAT_MASK (7<<25) +#define SPRITE_FORMAT_YUV422 (0<<25) +#define SPRITE_FORMAT_RGBX101010 (1<<25) +#define SPRITE_FORMAT_RGBX888 (2<<25) +#define SPRITE_FORMAT_RGBX161616 (3<<25) +#define SPRITE_FORMAT_YUV444 (4<<25) +#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ +#define SPRITE_CSC_ENABLE (1<<24) +#define SPRITE_SOURCE_KEY (1<<22) +#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) +#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ +#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) +#define SPRITE_YUV_ORDER_YUYV (0<<16) +#define SPRITE_YUV_ORDER_UYVY (1<<16) +#define SPRITE_YUV_ORDER_YVYU (2<<16) +#define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) +#define SPRITE_INT_GAMMA_ENABLE (1<<13) +#define SPRITE_TILED (1<<10) +#define SPRITE_DEST_KEY (1<<2) #define _SPRA_LINOFF 0x70284 #define _SPRA_STRIDE 0x70288 #define _SPRA_POS 0x7028c @@ -2868,13 +2868,13 @@ #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 #define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE (1<<31) -#define SPRITE_FILTER_MASK (3<<29) -#define SPRITE_FILTER_MEDIUM (0<<29) -#define SPRITE_FILTER_ENHANCING (1<<29) -#define SPRITE_FILTER_SOFTENING (2<<29) -#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) +#define SPRITE_SCALE_ENABLE (1<<31) +#define SPRITE_FILTER_MASK (3<<29) +#define SPRITE_FILTER_MEDIUM (0<<29) +#define SPRITE_FILTER_ENHANCING (1<<29) +#define SPRITE_FILTER_SOFTENING (2<<29) +#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) #define _SPRA_GAMC 0x70400
#define _SPRB_CTL 0x71280 @@ -2913,28 +2913,28 @@
#define CPU_VGACNTRL 0x41000
-#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) -#define DIGITAL_PORTA_NO_DETECT (0 << 0) -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) +#define DIGITAL_PORTA_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
/* refresh rate hardware control */ -#define RR_HW_CTL 0x45300 -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 +#define RR_HW_CTL 0x45300 +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
#define FDI_PLL_BIOS_0 0x46000 #define FDI_PLL_FB_CLOCK_MASK 0xff #define FDI_PLL_BIOS_1 0x46004 #define FDI_PLL_BIOS_2 0x46008 -#define DISPLAY_PORT_PLL_BIOS_0 0x4600c -#define DISPLAY_PORT_PLL_BIOS_1 0x46010 -#define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define DISPLAY_PORT_PLL_BIOS_0 0x4600c +#define DISPLAY_PORT_PLL_BIOS_1 0x46010 +#define DISPLAY_PORT_PLL_BIOS_2 0x46014
#define PCH_DSPCLK_GATE_D 0x42020 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) @@ -2949,47 +2949,47 @@ #define PCH_3DCGDIS1 0x46024 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define FDI_PLL_FREQ_CTL 0x46030 -#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) -#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 +#define FDI_PLL_FREQ_CTL 0x46030 +#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) +#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 -#define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 0x60034 -#define PIPE_DATA_N1_OFFSET 0 +#define _PIPEA_DATA_M1 0x60030 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK 0x7e000000 +#define PIPE_DATA_M1_OFFSET 0 +#define _PIPEA_DATA_N1 0x60034 +#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 0x60038 -#define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 0x6003c -#define PIPE_DATA_N2_OFFSET 0 +#define _PIPEA_DATA_M2 0x60038 +#define PIPE_DATA_M2_OFFSET 0 +#define _PIPEA_DATA_N2 0x6003c +#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 0x60040 -#define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 0x60044 -#define PIPE_LINK_N1_OFFSET 0 +#define _PIPEA_LINK_M1 0x60040 +#define PIPE_LINK_M1_OFFSET 0 +#define _PIPEA_LINK_N1 0x60044 +#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 0x60048 -#define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 0x6004c -#define PIPE_LINK_N2_OFFSET 0 +#define _PIPEA_LINK_M2 0x60048 +#define PIPE_LINK_M2_OFFSET 0 +#define _PIPEA_LINK_N2 0x6004c +#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 0x61030 -#define _PIPEB_DATA_N1 0x61034 +#define _PIPEB_DATA_M1 0x61030 +#define _PIPEB_DATA_N1 0x61034
-#define _PIPEB_DATA_M2 0x61038 -#define _PIPEB_DATA_N2 0x6103c +#define _PIPEB_DATA_M2 0x61038 +#define _PIPEB_DATA_N2 0x6103c
-#define _PIPEB_LINK_M1 0x61040 -#define _PIPEB_LINK_N1 0x61044 +#define _PIPEB_LINK_M1 0x61040 +#define _PIPEB_LINK_N1 0x61044
-#define _PIPEB_LINK_M2 0x61048 -#define _PIPEB_LINK_N2 0x6104c +#define _PIPEB_LINK_M2 0x61048 +#define _PIPEB_LINK_N2 0x6104c
#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) @@ -3002,9 +3002,9 @@
/* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_ENABLE (1<<31) +#define _PFA_CTL_1 0x68080 +#define _PFB_CTL_1 0x68880 +#define PF_ENABLE (1<<31) #define PF_FILTER_MASK (3<<23) #define PF_FILTER_PROGRAMMED (0<<23) #define PF_FILTER_MED_3x3 (1<<23) @@ -3026,35 +3026,35 @@ #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
/* legacy palette */ -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) -#define DE_SPRITEB_FLIP_DONE (1 << 29) -#define DE_SPRITEA_FLIP_DONE (1 << 28) -#define DE_PLANEB_FLIP_DONE (1 << 27) -#define DE_PLANEA_FLIP_DONE (1 << 26) -#define DE_PCU_EVENT (1 << 25) -#define DE_GTT_FAULT (1 << 24) -#define DE_POISON (1 << 23) -#define DE_PERFORM_COUNTER (1 << 22) -#define DE_PCH_EVENT (1 << 21) -#define DE_AUX_CHANNEL_A (1 << 20) -#define DE_DP_A_HOTPLUG (1 << 19) -#define DE_GSE (1 << 18) -#define DE_PIPEB_VBLANK (1 << 15) -#define DE_PIPEB_EVEN_FIELD (1 << 14) -#define DE_PIPEB_ODD_FIELD (1 << 13) -#define DE_PIPEB_LINE_COMPARE (1 << 12) -#define DE_PIPEB_VSYNC (1 << 11) +#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_SPRITEB_FLIP_DONE (1 << 29) +#define DE_SPRITEA_FLIP_DONE (1 << 28) +#define DE_PLANEB_FLIP_DONE (1 << 27) +#define DE_PLANEA_FLIP_DONE (1 << 26) +#define DE_PCU_EVENT (1 << 25) +#define DE_GTT_FAULT (1 << 24) +#define DE_POISON (1 << 23) +#define DE_PERFORM_COUNTER (1 << 22) +#define DE_PCH_EVENT (1 << 21) +#define DE_AUX_CHANNEL_A (1 << 20) +#define DE_DP_A_HOTPLUG (1 << 19) +#define DE_GSE (1 << 18) +#define DE_PIPEB_VBLANK (1 << 15) +#define DE_PIPEB_EVEN_FIELD (1 << 14) +#define DE_PIPEB_ODD_FIELD (1 << 13) +#define DE_PIPEB_LINE_COMPARE (1 << 12) +#define DE_PIPEB_VSYNC (1 << 11) #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) -#define DE_PIPEA_VBLANK (1 << 7) -#define DE_PIPEA_EVEN_FIELD (1 << 6) -#define DE_PIPEA_ODD_FIELD (1 << 5) -#define DE_PIPEA_LINE_COMPARE (1 << 4) -#define DE_PIPEA_VSYNC (1 << 3) +#define DE_PIPEA_VBLANK (1 << 7) +#define DE_PIPEA_EVEN_FIELD (1 << 6) +#define DE_PIPEA_ODD_FIELD (1 << 5) +#define DE_PIPEA_LINE_COMPARE (1 << 4) +#define DE_PIPEA_VSYNC (1 << 3) #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
/* More Ivybridge lolz */ @@ -3070,23 +3070,23 @@ #define DE_PIPEB_VBLANK_IVB (1<<5) #define DE_PIPEA_VBLANK_IVB (1<<0)
-#define DEISR 0x44000 -#define DEIMR 0x44004 -#define DEIIR 0x44008 -#define DEIER 0x4400c +#define DEISR 0x44000 +#define DEIMR 0x44004 +#define DEIIR 0x44008 +#define DEIER 0x4400c
/* GT interrupt */ #define GT_PIPE_NOTIFY (1 << 4) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) -#define GT_BSD_USER_INTERRUPT (1 << 5) +#define GT_SYNC_STATUS (1 << 2) +#define GT_USER_INTERRUPT (1 << 0) +#define GT_BSD_USER_INTERRUPT (1 << 5) #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) #define GT_BLT_USER_INTERRUPT (1 << 22)
-#define GTISR 0x44010 -#define GTIMR 0x44014 -#define GTIIR 0x44018 -#define GTIER 0x4401c +#define GTISR 0x44010 +#define GTIMR 0x44014 +#define GTIIR 0x44018 +#define GTIER 0x4401c
#define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ @@ -3106,9 +3106,9 @@ #define ILK_DPFD_CLK_GATE (1<<7)
/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ -#define ILK_CLK_FBC (1<<7) -#define ILK_DPFC_DIS1 (1<<8) -#define ILK_DPFC_DIS2 (1<<9) +#define ILK_CLK_FBC (1<<7) +#define ILK_DPFC_DIS1 (1<<8) +#define ILK_DPFC_DIS2 (1<<9)
#define IVB_CHICKEN3 0x4200c # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) @@ -3157,11 +3157,11 @@ #define SDE_AUXB (1 << 13) #define SDE_AUX_MASK (7 << 13) /* 12 reserved */ -#define SDE_CRT_HOTPLUG (1 << 11) -#define SDE_PORTD_HOTPLUG (1 << 10) -#define SDE_PORTC_HOTPLUG (1 << 9) -#define SDE_PORTB_HOTPLUG (1 << 8) -#define SDE_SDVOB_HOTPLUG (1 << 6) +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) #define SDE_HOTPLUG_MASK (0xf << 8) #define SDE_TRANSB_CRC_DONE (1 << 5) #define SDE_TRANSB_CRC_ERR (1 << 4) @@ -3186,41 +3186,41 @@ #define SDEIER 0xc400c
/* digital port hotplug */ -#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ -#define PORTD_HOTPLUG_ENABLE (1 << 20) -#define PORTD_PULSE_DURATION_2ms (0) -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) -#define PORTD_PULSE_DURATION_6ms (2 << 18) -#define PORTD_PULSE_DURATION_100ms (3 << 18) +#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0) +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) +#define PORTD_PULSE_DURATION_6ms (2 << 18) +#define PORTD_PULSE_DURATION_100ms (3 << 18) #define PORTD_PULSE_DURATION_MASK (3 << 18) -#define PORTD_HOTPLUG_NO_DETECT (0) -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) -#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) -#define PORTC_HOTPLUG_ENABLE (1 << 12) -#define PORTC_PULSE_DURATION_2ms (0) -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) -#define PORTC_PULSE_DURATION_6ms (2 << 10) -#define PORTC_PULSE_DURATION_100ms (3 << 10) +#define PORTD_HOTPLUG_NO_DETECT (0) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define PORTC_PULSE_DURATION_2ms (0) +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) +#define PORTC_PULSE_DURATION_6ms (2 << 10) +#define PORTC_PULSE_DURATION_100ms (3 << 10) #define PORTC_PULSE_DURATION_MASK (3 << 10) -#define PORTC_HOTPLUG_NO_DETECT (0) -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) -#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) -#define PORTB_HOTPLUG_ENABLE (1 << 4) -#define PORTB_PULSE_DURATION_2ms (0) -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) -#define PORTB_PULSE_DURATION_6ms (2 << 2) -#define PORTB_PULSE_DURATION_100ms (3 << 2) +#define PORTC_HOTPLUG_NO_DETECT (0) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define PORTB_PULSE_DURATION_2ms (0) +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) +#define PORTB_PULSE_DURATION_6ms (2 << 2) +#define PORTB_PULSE_DURATION_100ms (3 << 2) #define PORTB_PULSE_DURATION_MASK (3 << 2) -#define PORTB_HOTPLUG_NO_DETECT (0) -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) -#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) +#define PORTB_HOTPLUG_NO_DETECT (0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
-#define PCH_GPIOA 0xc5010 -#define PCH_GPIOB 0xc5014 -#define PCH_GPIOC 0xc5018 -#define PCH_GPIOD 0xc501c -#define PCH_GPIOE 0xc5020 -#define PCH_GPIOF 0xc5024 +#define PCH_GPIOA 0xc5010 +#define PCH_GPIOB 0xc5014 +#define PCH_GPIOC 0xc5018 +#define PCH_GPIOD 0xc501c +#define PCH_GPIOE 0xc5020 +#define PCH_GPIOF 0xc5024
#define PCH_GMBUS0 0xc5100 #define PCH_GMBUS1 0xc5104 @@ -3229,54 +3229,54 @@ #define PCH_GMBUS4 0xc5110 #define PCH_GMBUS5 0xc5120
-#define _PCH_DPLL_A 0xc6014 -#define _PCH_DPLL_B 0xc6018 +#define _PCH_DPLL_A 0xc6014 +#define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-#define _PCH_FPA0 0xc6040 +#define _PCH_FPA0 0xc6040 #define FP_CB_TUNE (0x3<<22) -#define _PCH_FPA1 0xc6044 -#define _PCH_FPB0 0xc6048 -#define _PCH_FPB1 0xc604c +#define _PCH_FPA1 0xc6044 +#define _PCH_FPB0 0xc6048 +#define _PCH_FPB1 0xc604c #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
-#define PCH_DPLL_TEST 0xc606c +#define PCH_DPLL_TEST 0xc606c
-#define PCH_DREF_CONTROL 0xC6200 -#define DREF_CONTROL_MASK 0x7fc3 -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) +#define PCH_DREF_CONTROL 0xC6200 +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) -#define DREF_SSC_SOURCE_DISABLE (0<<11) -#define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_DISABLE (0<<11) +#define DREF_SSC_SOURCE_ENABLE (2<<11) #define DREF_SSC_SOURCE_MASK (3<<11) -#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) #define DREF_NONSPREAD_CK505_ENABLE (1<<9) -#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) #define DREF_NONSPREAD_SOURCE_MASK (3<<9) -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) -#define DREF_SSC4_DOWNSPREAD (0<<6) -#define DREF_SSC4_CENTERSPREAD (1<<6) -#define DREF_SSC1_DISABLE (0<<1) -#define DREF_SSC1_ENABLE (1<<1) -#define DREF_SSC4_DISABLE (0) -#define DREF_SSC4_ENABLE (1) +#define DREF_SSC4_DOWNSPREAD (0<<6) +#define DREF_SSC4_CENTERSPREAD (1<<6) +#define DREF_SSC1_DISABLE (0<<1) +#define DREF_SSC1_ENABLE (1<<1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1)
-#define PCH_RAWCLK_FREQ 0xc6204 -#define FDL_TP1_TIMER_SHIFT 12 -#define FDL_TP1_TIMER_MASK (3<<12) -#define FDL_TP2_TIMER_SHIFT 10 -#define FDL_TP2_TIMER_MASK (3<<10) -#define RAWCLK_FREQ_MASK 0x3ff +#define PCH_RAWCLK_FREQ 0xc6204 +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3<<12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3<<10) +#define RAWCLK_FREQ_MASK 0x3ff
-#define PCH_DPLL_TMR_CFG 0xc6208 +#define PCH_DPLL_TMR_CFG 0xc6208
-#define PCH_SSC4_PARMS 0xc6210 -#define PCH_SSC4_AUX_PARMS 0xc6214 +#define PCH_SSC4_PARMS 0xc6210 +#define PCH_SSC4_AUX_PARMS 0xc6214
#define PCH_DPLL_SEL 0xc7000 #define TRANSA_DPLL_ENABLE (1<<3) @@ -3291,55 +3291,55 @@
/* transcoder */
-#define _TRANS_HTOTAL_A 0xe0000 -#define TRANS_HTOTAL_SHIFT 16 -#define TRANS_HACTIVE_SHIFT 0 -#define _TRANS_HBLANK_A 0xe0004 +#define _TRANS_HTOTAL_A 0xe0000 +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 +#define _TRANS_HBLANK_A 0xe0004 #define TRANS_HBLANK_END_SHIFT 16 #define TRANS_HBLANK_START_SHIFT 0 -#define _TRANS_HSYNC_A 0xe0008 +#define _TRANS_HSYNC_A 0xe0008 #define TRANS_HSYNC_END_SHIFT 16 #define TRANS_HSYNC_START_SHIFT 0 -#define _TRANS_VTOTAL_A 0xe000c -#define TRANS_VTOTAL_SHIFT 16 -#define TRANS_VACTIVE_SHIFT 0 -#define _TRANS_VBLANK_A 0xe0010 +#define _TRANS_VTOTAL_A 0xe000c +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 +#define _TRANS_VBLANK_A 0xe0010 #define TRANS_VBLANK_END_SHIFT 16 #define TRANS_VBLANK_START_SHIFT 0 -#define _TRANS_VSYNC_A 0xe0014 +#define _TRANS_VSYNC_A 0xe0014 #define TRANS_VSYNC_END_SHIFT 16 #define TRANS_VSYNC_START_SHIFT 0 #define _TRANS_VSYNCSHIFT_A 0xe0028
-#define _TRANSA_DATA_M1 0xe0030 -#define _TRANSA_DATA_N1 0xe0034 -#define _TRANSA_DATA_M2 0xe0038 -#define _TRANSA_DATA_N2 0xe003c -#define _TRANSA_DP_LINK_M1 0xe0040 -#define _TRANSA_DP_LINK_N1 0xe0044 -#define _TRANSA_DP_LINK_M2 0xe0048 -#define _TRANSA_DP_LINK_N2 0xe004c +#define _TRANSA_DATA_M1 0xe0030 +#define _TRANSA_DATA_N1 0xe0034 +#define _TRANSA_DATA_M2 0xe0038 +#define _TRANSA_DATA_N2 0xe003c +#define _TRANSA_DP_LINK_M1 0xe0040 +#define _TRANSA_DP_LINK_N1 0xe0044 +#define _TRANSA_DP_LINK_M2 0xe0048 +#define _TRANSA_DP_LINK_N2 0xe004c
/* Per-transcoder DIP controls */
-#define _VIDEO_DIP_CTL_A 0xe0200 -#define _VIDEO_DIP_DATA_A 0xe0208 -#define _VIDEO_DIP_GCP_A 0xe0210 +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_GCP_A 0xe0210
-#define _VIDEO_DIP_CTL_B 0xe1200 -#define _VIDEO_DIP_DATA_B 0xe1208 -#define _VIDEO_DIP_GCP_B 0xe1210 +#define _VIDEO_DIP_CTL_B 0xe1200 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define _VIDEO_DIP_GCP_B 0xe1210
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define _TRANS_HTOTAL_B 0xe1000 -#define _TRANS_HBLANK_B 0xe1004 -#define _TRANS_HSYNC_B 0xe1008 -#define _TRANS_VTOTAL_B 0xe100c -#define _TRANS_VBLANK_B 0xe1010 -#define _TRANS_VSYNC_B 0xe1014 +#define _TRANS_HTOTAL_B 0xe1000 +#define _TRANS_HBLANK_B 0xe1004 +#define _TRANS_HSYNC_B 0xe1008 +#define _TRANS_VTOTAL_B 0xe100c +#define _TRANS_VBLANK_B 0xe1010 +#define _TRANS_VSYNC_B 0xe1014 #define _TRANS_VSYNCSHIFT_B 0xe1028
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) @@ -3349,16 +3349,16 @@ #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ - _TRANS_VSYNCSHIFT_B) + _TRANS_VSYNCSHIFT_B)
-#define _TRANSB_DATA_M1 0xe1030 -#define _TRANSB_DATA_N1 0xe1034 -#define _TRANSB_DATA_M2 0xe1038 -#define _TRANSB_DATA_N2 0xe103c -#define _TRANSB_DP_LINK_M1 0xe1040 -#define _TRANSB_DP_LINK_N1 0xe1044 -#define _TRANSB_DP_LINK_M2 0xe1048 -#define _TRANSB_DP_LINK_N2 0xe104c +#define _TRANSB_DATA_M1 0xe1030 +#define _TRANSB_DATA_N1 0xe1034 +#define _TRANSB_DATA_M2 0xe1038 +#define _TRANSB_DATA_N2 0xe103c +#define _TRANSB_DP_LINK_M1 0xe1040 +#define _TRANSB_DP_LINK_N1 0xe1044 +#define _TRANSB_DP_LINK_M2 0xe1048 +#define _TRANSB_DP_LINK_N2 0xe104c
#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) @@ -3369,33 +3369,33 @@ #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
-#define _TRANSACONF 0xf0008 -#define _TRANSBCONF 0xf1008 +#define _TRANSACONF 0xf0008 +#define _TRANSBCONF 0xf1008 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) -#define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) -#define TRANS_STATE_MASK (1<<30) -#define TRANS_STATE_DISABLE (0<<30) -#define TRANS_STATE_ENABLE (1<<30) +#define TRANS_DISABLE (0<<31) +#define TRANS_ENABLE (1<<31) +#define TRANS_STATE_MASK (1<<30) +#define TRANS_STATE_DISABLE (0<<30) +#define TRANS_STATE_ENABLE (1<<30) #define TRANS_FSYNC_DELAY_HB1 (0<<27) #define TRANS_FSYNC_DELAY_HB2 (1<<27) #define TRANS_FSYNC_DELAY_HB3 (2<<27) #define TRANS_FSYNC_DELAY_HB4 (3<<27) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_VIDEO_AUDIO (0<<26) -#define TRANS_INTERLACE_MASK (7<<21) -#define TRANS_PROGRESSIVE (0<<21) -#define TRANS_INTERLACED (3<<21) +#define TRANS_DP_AUDIO_ONLY (1<<26) +#define TRANS_DP_VIDEO_AUDIO (0<<26) +#define TRANS_INTERLACE_MASK (7<<21) +#define TRANS_PROGRESSIVE (0<<21) +#define TRANS_INTERLACED (3<<21) #define TRANS_LEGACY_INTERLACED_ILK (2<<21) -#define TRANS_8BPC (0<<5) -#define TRANS_10BPC (1<<5) -#define TRANS_6BPC (2<<5) -#define TRANS_12BPC (3<<5) +#define TRANS_8BPC (0<<5) +#define TRANS_10BPC (1<<5) +#define TRANS_6BPC (2<<5) +#define TRANS_12BPC (3<<5)
#define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
#define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 @@ -3405,8 +3405,8 @@ #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
-#define _FDI_RXA_CHICKEN 0xc200c -#define _FDI_RXB_CHICKEN 0xc2010 +#define _FDI_RXA_CHICKEN 0xc200c +#define _FDI_RXB_CHICKEN 0xc2010 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) @@ -3415,23 +3415,23 @@ #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
/* CPU: FDI_TX */ -#define _FDI_TXA_CTL 0x60100 -#define _FDI_TXB_CTL 0x61100 +#define _FDI_TXA_CTL 0x60100 +#define _FDI_TXB_CTL 0x61100 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) -#define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) -#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) -#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) -#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) -#define FDI_LINK_TRAIN_NONE (3<<28) -#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) -#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) +#define FDI_TX_DISABLE (0<<31) +#define FDI_TX_ENABLE (1<<31) +#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) +#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) +#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) +#define FDI_LINK_TRAIN_NONE (3<<28) +#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) +#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* SNB A-stepping */ @@ -3445,48 +3445,48 @@ #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) -#define FDI_DP_PORT_WIDTH_X1 (0<<19) -#define FDI_DP_PORT_WIDTH_X2 (1<<19) -#define FDI_DP_PORT_WIDTH_X3 (2<<19) -#define FDI_DP_PORT_WIDTH_X4 (3<<19) -#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) +#define FDI_DP_PORT_WIDTH_X1 (0<<19) +#define FDI_DP_PORT_WIDTH_X2 (1<<19) +#define FDI_DP_PORT_WIDTH_X3 (2<<19) +#define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) /* Ironlake: hardwired to 1 */ -#define FDI_TX_PLL_ENABLE (1<<14) +#define FDI_TX_PLL_ENABLE (1<<14)
/* Ivybridge has different bits for lolz */ -#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) +#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) +#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) -#define FDI_LINK_TRAIN_NONE_IVB (3<<8) +#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
/* both Tx and Rx */ #define FDI_COMPOSITE_SYNC (1<<11) #define FDI_LINK_TRAIN_AUTO (1<<10) -#define FDI_SCRAMBLING_ENABLE (0<<7) -#define FDI_SCRAMBLING_DISABLE (1<<7) +#define FDI_SCRAMBLING_ENABLE (0<<7) +#define FDI_SCRAMBLING_DISABLE (1<<7)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ -#define _FDI_RXA_CTL 0xf000c -#define _FDI_RXB_CTL 0xf100c +#define _FDI_RXA_CTL 0xf000c +#define _FDI_RXB_CTL 0xf100c #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_ENABLE (1<<31) /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE (1<<27) #define FDI_FE_ERRC_ENABLE (1<<26) -#define FDI_DP_PORT_WIDTH_X8 (7<<19) -#define FDI_8BPC (0<<16) -#define FDI_10BPC (1<<16) -#define FDI_6BPC (2<<16) -#define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) -#define FDI_DMI_LINK_REVERSE_MASK (1<<14) -#define FDI_RX_PLL_ENABLE (1<<13) -#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) -#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) -#define FDI_FS_ERR_REPORT_ENABLE (1<<9) -#define FDI_FE_ERR_REPORT_ENABLE (1<<8) -#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) -#define FDI_PCDCLK (1<<4) +#define FDI_DP_PORT_WIDTH_X8 (7<<19) +#define FDI_8BPC (0<<16) +#define FDI_10BPC (1<<16) +#define FDI_6BPC (2<<16) +#define FDI_12BPC (3<<16) +#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_DMI_LINK_REVERSE_MASK (1<<14) +#define FDI_RX_PLL_ENABLE (1<<13) +#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) +#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) +#define FDI_FS_ERR_REPORT_ENABLE (1<<9) +#define FDI_FE_ERR_REPORT_ENABLE (1<<8) +#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) +#define FDI_PCDCLK (1<<4) /* CPT */ #define FDI_AUTO_TRAINING (1<<10) #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) @@ -3495,91 +3495,91 @@ #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
-#define _FDI_RXA_MISC 0xf0010 -#define _FDI_RXB_MISC 0xf1010 -#define _FDI_RXA_TUSIZE1 0xf0030 -#define _FDI_RXA_TUSIZE2 0xf0038 -#define _FDI_RXB_TUSIZE1 0xf1030 -#define _FDI_RXB_TUSIZE2 0xf1038 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define _FDI_RXA_TUSIZE1 0xf0030 +#define _FDI_RXA_TUSIZE2 0xf0038 +#define _FDI_RXB_TUSIZE1 0xf1030 +#define _FDI_RXB_TUSIZE2 0xf1038 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
/* FDI_RX interrupt register format */ -#define FDI_RX_INTER_LANE_ALIGN (1<<10) -#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ -#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ -#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) -#define FDI_RX_FS_CODE_ERR (1<<6) -#define FDI_RX_FE_CODE_ERR (1<<5) -#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) -#define FDI_RX_HDCP_LINK_FAIL (1<<3) -#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) -#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) -#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) - -#define _FDI_RXA_IIR 0xf0014 -#define _FDI_RXA_IMR 0xf0018 -#define _FDI_RXB_IIR 0xf1014 -#define _FDI_RXB_IMR 0xf1018 +#define FDI_RX_INTER_LANE_ALIGN (1<<10) +#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ +#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ +#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) +#define FDI_RX_FS_CODE_ERR (1<<6) +#define FDI_RX_FE_CODE_ERR (1<<5) +#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) +#define FDI_RX_HDCP_LINK_FAIL (1<<3) +#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) +#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) +#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) + +#define _FDI_RXA_IIR 0xf0014 +#define _FDI_RXA_IMR 0xf0018 +#define _FDI_RXB_IIR 0xf1014 +#define _FDI_RXB_IMR 0xf1018 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
-#define FDI_PLL_CTL_1 0xfe000 -#define FDI_PLL_CTL_2 0xfe004 +#define FDI_PLL_CTL_1 0xfe000 +#define FDI_PLL_CTL_2 0xfe004
/* CRT */ -#define PCH_ADPA 0xe1100 +#define PCH_ADPA 0xe1100 #define ADPA_TRANS_SELECT_MASK (1<<30) -#define ADPA_TRANS_A_SELECT 0 -#define ADPA_TRANS_B_SELECT (1<<30) +#define ADPA_TRANS_A_SELECT 0 +#define ADPA_TRANS_B_SELECT (1<<30) #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) -#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) -#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) -#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) -#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) -#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) -#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) -#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) -#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) +#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) +#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) +#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) +#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) +#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) +#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) +#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) +#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
/* or SDVOB */ -#define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) -#define TRANSCODER(pipe) ((pipe) << 30) -#define TRANSCODER_CPT(pipe) ((pipe) << 29) -#define TRANSCODER_MASK (1 << 30) -#define TRANSCODER_MASK_CPT (3 << 29) -#define COLOR_FORMAT_8bpc (0) -#define COLOR_FORMAT_12bpc (3 << 26) -#define SDVOB_HOTPLUG_ENABLE (1 << 23) -#define SDVO_ENCODING (0) -#define TMDS_ENCODING (2 << 10) -#define NULL_PACKET_VSYNC_ENABLE (1 << 9) +#define HDMIB 0xe1140 +#define PORT_ENABLE (1 << 31) +#define TRANSCODER(pipe) ((pipe) << 30) +#define TRANSCODER_CPT(pipe) ((pipe) << 29) +#define TRANSCODER_MASK (1 << 30) +#define TRANSCODER_MASK_CPT (3 << 29) +#define COLOR_FORMAT_8bpc (0) +#define COLOR_FORMAT_12bpc (3 << 26) +#define SDVOB_HOTPLUG_ENABLE (1 << 23) +#define SDVO_ENCODING (0) +#define TMDS_ENCODING (2 << 10) +#define NULL_PACKET_VSYNC_ENABLE (1 << 9) /* CPT */ #define HDMI_MODE_SELECT (1 << 9) #define DVI_MODE_SELECT (0) -#define SDVOB_BORDER_ENABLE (1 << 7) -#define AUDIO_ENABLE (1 << 6) -#define VSYNC_ACTIVE_HIGH (1 << 4) -#define HSYNC_ACTIVE_HIGH (1 << 3) -#define PORT_DETECTED (1 << 2) +#define SDVOB_BORDER_ENABLE (1 << 7) +#define AUDIO_ENABLE (1 << 6) +#define VSYNC_ACTIVE_HIGH (1 << 4) +#define HSYNC_ACTIVE_HIGH (1 << 3) +#define PORT_DETECTED (1 << 2)
/* PCH SDVOB multiplex with HDMIB */ #define PCH_SDVOB HDMIB
-#define HDMIC 0xe1150 -#define HDMID 0xe1160 +#define HDMIC 0xe1150 +#define HDMID 0xe1160
#define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) @@ -3723,16 +3723,16 @@ #define FORCEWAKE_MT 0xa188 /* multi-threaded */ #define FORCEWAKE_MT_ACK 0x130040 #define ECOBUS 0xa180 -#define FORCEWAKE_MT_ENABLE (1<<5) +#define FORCEWAKE_MT_ENABLE (1<<5)
#define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 -#define GT_FIFO_OVFERR (1<<2) -#define GT_FIFO_IAWRERR (1<<1) -#define GT_FIFO_IARDERR (1<<0) +#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_OVFERR (1<<2) +#define GT_FIFO_IAWRERR (1<<1) +#define GT_FIFO_IARDERR (1<<0)
#define GT_FIFO_FREE_ENTRIES 0x120008 -#define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL1 0x9400 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) @@ -3743,46 +3743,46 @@ # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
#define GEN6_RPNSWREQ 0xA008 -#define GEN6_TURBO_DISABLE (1<<31) -#define GEN6_FREQUENCY(x) ((x)<<25) -#define GEN6_OFFSET(x) ((x)<<19) -#define GEN6_AGGRESSIVE_TURBO (0<<15) +#define GEN6_TURBO_DISABLE (1<<31) +#define GEN6_FREQUENCY(x) ((x)<<25) +#define GEN6_OFFSET(x) ((x)<<19) +#define GEN6_AGGRESSIVE_TURBO (0<<15) #define GEN6_RC_VIDEO_FREQ 0xA00C #define GEN6_RC_CONTROL 0xA090 -#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) -#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) -#define GEN6_RC_CTL_RC6_ENABLE (1<<18) -#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) -#define GEN6_RC_CTL_RC7_ENABLE (1<<22) -#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) -#define GEN6_RC_CTL_HW_ENABLE (1<<31) +#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) +#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) +#define GEN6_RC_CTL_RC6_ENABLE (1<<18) +#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) +#define GEN6_RC_CTL_RC7_ENABLE (1<<22) +#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) +#define GEN6_RC_CTL_HW_ENABLE (1<<31) #define GEN6_RP_DOWN_TIMEOUT 0xA010 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 #define GEN6_RPSTAT1 0xA01C -#define GEN6_CAGF_SHIFT 8 -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) +#define GEN6_CAGF_SHIFT 8 +#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) #define GEN6_RP_CONTROL 0xA024 -#define GEN6_RP_MEDIA_TURBO (1<<11) -#define GEN6_RP_MEDIA_MODE_MASK (3<<9) -#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) -#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) -#define GEN6_RP_MEDIA_HW_MODE (1<<9) -#define GEN6_RP_MEDIA_SW_MODE (0<<9) -#define GEN6_RP_MEDIA_IS_GFX (1<<8) -#define GEN6_RP_ENABLE (1<<7) -#define GEN6_RP_UP_IDLE_MIN (0x1<<3) -#define GEN6_RP_UP_BUSY_AVG (0x2<<3) -#define GEN6_RP_UP_BUSY_CONT (0x4<<3) -#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) +#define GEN6_RP_MEDIA_TURBO (1<<11) +#define GEN6_RP_MEDIA_MODE_MASK (3<<9) +#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) +#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) +#define GEN6_RP_MEDIA_HW_MODE (1<<9) +#define GEN6_RP_MEDIA_SW_MODE (0<<9) +#define GEN6_RP_MEDIA_IS_GFX (1<<8) +#define GEN6_RP_ENABLE (1<<7) +#define GEN6_RP_UP_IDLE_MIN (0x1<<3) +#define GEN6_RP_UP_BUSY_AVG (0x2<<3) +#define GEN6_RP_UP_BUSY_CONT (0x4<<3) +#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) #define GEN6_RP_UP_THRESHOLD 0xA02C #define GEN6_RP_DOWN_THRESHOLD 0xA030 #define GEN6_RP_CUR_UP_EI 0xA050 -#define GEN6_CURICONT_MASK 0xffffff +#define GEN6_CURICONT_MASK 0xffffff #define GEN6_RP_CUR_UP 0xA054 -#define GEN6_CURBSYTAVG_MASK 0xffffff +#define GEN6_CURBSYTAVG_MASK 0xffffff #define GEN6_RP_PREV_UP 0xA058 #define GEN6_RP_CUR_DOWN_EI 0xA05C -#define GEN6_CURIAVG_MASK 0xffffff +#define GEN6_CURIAVG_MASK 0xffffff #define GEN6_RP_CUR_DOWN 0xA060 #define GEN6_RP_PREV_DOWN 0xA064 #define GEN6_RP_UP_EI 0xA068 @@ -3817,20 +3817,20 @@ GEN6_PM_RP_DOWN_TIMEOUT)
#define GEN6_PCODE_MAILBOX 0x138124 -#define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 +#define GEN6_PCODE_READY (1<<31) +#define GEN6_READ_OC_PARAMS 0xc +#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 +#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_DATA 0x138128 -#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_GT_CORE_STATUS 0x138060 -#define GEN6_CORE_CPD_STATE_MASK (7<<4) -#define GEN6_RCn_MASK 7 -#define GEN6_RC0 0 -#define GEN6_RC3 2 -#define GEN6_RC6 3 -#define GEN6_RC7 4 +#define GEN6_CORE_CPD_STATE_MASK (7<<4) +#define GEN6_RCn_MASK 7 +#define GEN6_RC0 0 +#define GEN6_RC3 2 +#define GEN6_RC6 3 +#define GEN6_RC7 4
#define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB @@ -3865,14 +3865,14 @@
#define IBX_AUD_CONFIG_A 0xe2000 #define CPT_AUD_CONFIG_A 0xe5000 -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) -#define AUD_CONFIG_UPPER_N_SHIFT 20 -#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) -#define AUD_CONFIG_LOWER_N_SHIFT 4 -#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) +#define AUD_CONFIG_UPPER_N_SHIFT 20 +#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) +#define AUD_CONFIG_LOWER_N_SHIFT 4 +#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 +#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) +#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
#endif /* _I915_REG_H_ */ diff --git a/src/mainboard/google/link/intel_dp.c b/src/mainboard/google/link/intel_dp.c index 9fb66f6..1ff361c 100644 --- a/src/mainboard/google/link/intel_dp.c +++ b/src/mainboard/google/link/intel_dp.c @@ -123,7 +123,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) + DP_AUX_CH_CTL_RECEIVE_ERROR)) continue; if (status & DP_AUX_CH_CTL_DONE) break; @@ -154,7 +154,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
/* Unload any bytes sent back from the other side */ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); if (recv_bytes > recv_size) recv_bytes = recv_size;
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 08b1c02..b6da207 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -76,7 +76,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ @@ -140,7 +140,7 @@ static int int15_handler(void) case 0x5fac: res = 1; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } @@ -181,7 +181,7 @@ static void mainboard_init(device_t dev) }
static int link_onboard_smbios_data(device_t dev, int *handle, - unsigned long *current) + unsigned long *current) { int len = 0;
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..d439388 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -78,17 +78,17 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P3IP WLAN INTA -> PIRQB - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQF - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D27IP_ZIP HDA INTA -> PIRQA (MSI) * - * TRACKPAD -> PIRQE (Edge Triggered) - * TOUCHSCREEN -> PIRQG (Edge Triggered) + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) */
/* Device interrupt pin register (board specific) */ @@ -142,9 +142,9 @@ static void copy_spd(struct pei_data *peid) die("Missing SPD data.");
memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); }
void main(unsigned long bist) @@ -185,14 +185,14 @@ void main(unsigned long bist) { 0, 3, 0x0000 }, /* P0: Empty */ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ - { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ + { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ { 0, 3, 0x0000 }, /* P4: Empty */ - { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ + { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ { 0, 3, 0x0000 }, /* P6: Empty */ { 0, 3, 0x0000 }, /* P7: Empty */ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ - { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ + { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ { 0, 4, 0x0000 }, /* P10: Empty */ { 0, 4, 0x0000 }, /* P11: Empty */ { 0, 4, 0x0000 }, /* P12: Empty */ diff --git a/src/mainboard/google/parrot/acpi/chromeos.asl b/src/mainboard/google/parrot/acpi/chromeos.asl index 622b5d9..d325f1c 100644 --- a/src/mainboard/google/parrot/acpi/chromeos.asl +++ b/src/mainboard/google/parrot/acpi/chromeos.asl @@ -20,6 +20,6 @@ Name(OIPG, Package() { Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect + Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect })
diff --git a/src/mainboard/google/parrot/acpi/superio.asl b/src/mainboard/google/parrot/acpi/superio.asl index e4856fc..1f43127 100644 --- a/src/mainboard/google/parrot/acpi/superio.asl +++ b/src/mainboard/google/parrot/acpi/superio.asl @@ -21,7 +21,7 @@ #include "../ec.h"
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
/* ACPI code for EC SuperIO functions */ #include "../../../../ec/compal/ene932/acpi/superio.asl" diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 45a9948..cce325e 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -224,7 +224,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h index 5245920..3a4af20 100644 --- a/src/mainboard/google/parrot/ec.h +++ b/src/mainboard/google/parrot/ec.h @@ -20,8 +20,8 @@ #ifndef PARROT_EC_H #define PARROT_EC_H
-#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */ -#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ +#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */ +#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ #define EC_LID_GPI 15 /* GPIO15 is EC_LID_OUT# */
/* EC SMI sources TODO - make defines diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h index a9eb99b..08908b8 100644 --- a/src/mainboard/google/parrot/gpio.h +++ b/src/mainboard/google/parrot/gpio.h @@ -260,18 +260,18 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map parrot_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 34cb24e..1f0c9f7 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -64,7 +64,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ @@ -126,7 +126,7 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } @@ -157,7 +157,7 @@ static void mainboard_init(device_t dev) }
static int parrot_onboard_smbios_data(device_t dev, int *handle, - unsigned long *current) + unsigned long *current) { int len = 0; u8 hardware_version = parrot_rev(); diff --git a/src/mainboard/google/parrot/onboard.h b/src/mainboard/google/parrot/onboard.h index f3d200d..818f263 100644 --- a/src/mainboard/google/parrot/onboard.h +++ b/src/mainboard/google/parrot/onboard.h @@ -22,8 +22,8 @@
#include <arch/smp/mpspec.h>
-#define PARROT_TRACKPAD_NAME "trackpad" +#define PARROT_TRACKPAD_NAME "trackpad" #define PARROT_TRACKPAD_I2C_ADDR 0x67 -#define PARROT_TRACKPAD_IRQ_DVT 16 -#define PARROT_TRACKPAD_IRQ_PVT 20 +#define PARROT_TRACKPAD_IRQ_DVT 16 +#define PARROT_TRACKPAD_IRQ_PVT 20 #endif diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 2fe61d6..8de242f 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -62,15 +62,15 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P2IP WLAN INTA -> PIRQB * D28IP_P3IP ETH0 INTC -> PIRQD - * D29IP_E1P EHCI1 INTA -> PIRQE - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQE + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) * * Trackpad DVT PIRQA (16) * Trackpad DVT PIRQE (20) diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index 4a189f8..c8b6ba1 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -107,7 +107,7 @@ static u8 mainboard_smi_ec(void) #if CONFIG_ELOG_GSMI if (!battery_critical_logged) elog_add_event_byte(ELOG_TYPE_EC_EVENT, - EC_EVENT_BATTERY_CRITICAL); + EC_EVENT_BATTERY_CRITICAL); battery_critical_logged = 1; #endif break; diff --git a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl index 82a2eba..881675b 100644 --- a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl @@ -42,12 +42,12 @@ Method(_PRT) Package() { 0x001fffff, 1, 0, 18 }, Package() { 0x001fffff, 2, 0, 17 }, Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, 0, 20 }, Package() { 0x0015ffff, 1, 0, 21 }, Package() { 0x0015ffff, 2, 0, 21 }, Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, 0, 23 }, }) } Else { @@ -70,12 +70,12 @@ Method(_PRT) Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, Package() { 0x0015ffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 2, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 3, _SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, }) } diff --git a/src/mainboard/google/peppy/acpi/superio.asl b/src/mainboard/google/peppy/acpi/superio.asl index c652f4f..de45fdc 100644 --- a/src/mainboard/google/peppy/acpi/superio.asl +++ b/src/mainboard/google/peppy/acpi/superio.asl @@ -20,10 +20,10 @@ /* mainboard configuration */ #include <mainboard/google/peppy/ec.h>
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
/* ACPI code for EC SuperIO functions */ #include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/peppy/acpi_tables.c b/src/mainboard/google/peppy/acpi_tables.c index 7a3ccea..313a939 100644 --- a/src/mainboard/google/peppy/acpi_tables.c +++ b/src/mainboard/google/peppy/acpi_tables.c @@ -241,7 +241,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; acpi_save_gnvs((unsigned long)gnvs); break; diff --git a/src/mainboard/google/peppy/cmos.layout b/src/mainboard/google/peppy/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/peppy/cmos.layout +++ b/src/mainboard/google/peppy/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/peppy/ec.c b/src/mainboard/google/peppy/ec.c index 0919f0f..74bb385 100644 --- a/src/mainboard/google/peppy/ec.c +++ b/src/mainboard/google/peppy/ec.c @@ -32,7 +32,7 @@ void mainboard_ec_init(void) /* Restore SCI event mask on resume. */ if (acpi_slp_type == 3) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); + MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */ google_chromeec_set_smi_mask(0); @@ -42,7 +42,7 @@ void mainboard_ec_init(void) google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); + MAINBOARD_EC_S5_WAKE_EVENTS); }
/* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/peppy/ec.h b/src/mainboard/google/peppy/ec.h index 11d2453..86be0df 100644 --- a/src/mainboard/google/peppy/ec.h +++ b/src/mainboard/google/peppy/ec.h @@ -22,17 +22,17 @@
#include <ec/google/chromeec/ec_commands.h>
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ +#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ +#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) @@ -42,7 +42,7 @@
/* EC can wake from S5 with lid or power button */ #define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */ diff --git a/src/mainboard/google/peppy/gpio.h b/src/mainboard/google/peppy/gpio.h index 6dfb98f..cdcc6d7 100644 --- a/src/mainboard/google/peppy/gpio.h +++ b/src/mainboard/google/peppy/gpio.h @@ -23,101 +23,101 @@ struct pch_lp_gpio_map;
const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - LP_GPIO_INPUT, /* 9: RAM_ID1 */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 12: TRACKPAD_INT_L */ - LP_GPIO_INPUT, /* 13: RAM_ID0 */ - LP_GPIO_INPUT, /* 14: EC_IN_RW */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ - LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ - LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_UNUSED, /* 20: UNUSED */ - LP_GPIO_UNUSED, /* 21: UNUSED */ - LP_GPIO_UNUSED, /* 22: UNUSED */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_UNUSED, /* 24: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 25: TOUCH_INT_L */ - LP_GPIO_UNUSED, /* 26: UNUSED */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_UNUSED, /* 41: UNUSED */ - LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - LP_GPIO_UNUSED, /* 43: UNUSED */ - LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ - LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ - LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - LP_GPIO_INPUT, /* 47: RAM_ID2 */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ - LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ - LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ - LP_GPIO_ACPI_SCI, /* 53: TRACKPAD_INT_DX (WAKE) */ - LP_GPIO_ACPI_SCI, /* 54: TOUCH_INT_L_DX (WAKE) */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_UNUSED, /* 56: UNUSED */ - LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ - LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ - LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 12: TRACKPAD_INT_L */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ + LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 25: TOUCH_INT_L */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_IRQ_EDGE, /* 51: ALS_INT_L */ + LP_GPIO_IRQ_EDGE, /* 52: SIM_DET */ + LP_GPIO_ACPI_SCI, /* 53: TRACKPAD_INT_DX (WAKE) */ + LP_GPIO_ACPI_SCI, /* 54: TOUCH_INT_L_DX (WAKE) */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ + LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END };
diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index 0159bd0..f01da1d 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -49,7 +49,7 @@ static int int15_handler(void) int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f34: @@ -58,7 +58,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CX = 0x0001; @@ -115,13 +115,13 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 8679adb..3a5423a 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -34,14 +34,14 @@ const struct rcba_config_instruction rcba_config[] = {
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD + * D29IP_E1P EHCI INTA -> PIRQD * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ @@ -93,9 +93,9 @@ static void copy_spd(struct pei_data *peid) die("Missing SPD data.");
memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); }
/* @@ -103,10 +103,10 @@ static void copy_spd(struct pei_data *peid) * * Must be sequenced in this order with specified timing. * - * 1. VCC_IO : 30us - 100ms + * 1. VCC_IO : 30us - 100ms * 2. VCC_FLASH : 70us - 10ms - * 3. VCCQ : 70us - 10ms - * 4. VDDC : 30us - 100ms + * 3. VCCQ : 70us - 10ms + * 4. VDDC : 30us - 100ms * * There is no feedback to know if the voltage has stabilized * so this implementation will use the max ramp times. That @@ -120,8 +120,8 @@ static void issd_power_sequence(void) } issd_gpio_seq[] = { { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ - { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ - { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ + { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ + { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ }; int step;
@@ -161,18 +161,18 @@ void mainboard_romstage_entry(unsigned long bist) usb2_ports: { /* Length, Enable, OCn# */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ + { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN6 */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN6 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index b91040c..658ad27 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -167,7 +167,7 @@ static void tps65090_thru_ec_fet_set(int index)
if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { printk(BIOS_ERR, - "Error sending i2c pass through command to EC.\n"); + "Error sending i2c pass through command to EC.\n"); return; } } diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index a757615..3d9f245 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -62,16 +62,16 @@ struct pmic_write pmic_writes[] = MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | - MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | - MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, { 1, MAX77802_REG_PMIC_LDO35CTRL1, MAX77802_LDO35CTRL1_1_2V }, };
@@ -153,10 +153,10 @@ static void setup_gpio(void) static void setup_memory(struct mem_timings *mem, int is_resume) { printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz);
/* FIXME Currently memory initialization with mem_reset on normal boot * will cause resume to fail (even if we don't do mem_reset on resume), @@ -234,14 +234,14 @@ static void simple_spi_test(void) if (data[i/4] != in){ errors++; printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", - i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); /* reread it to see which is wrong. */ if (media->read(media, &in, (size_t) i, 4) < 1){ printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; } printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", - i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); + i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); }
} diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl index 82a2eba..881675b 100644 --- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl @@ -42,12 +42,12 @@ Method(_PRT) Package() { 0x001fffff, 1, 0, 18 }, Package() { 0x001fffff, 2, 0, 17 }, Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, 0, 20 }, Package() { 0x0015ffff, 1, 0, 21 }, Package() { 0x0015ffff, 2, 0, 21 }, Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, 0, 23 }, }) } Else { @@ -70,12 +70,12 @@ Method(_PRT) Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKC, 0 }, Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKB, 0 }, Package() { 0x001fffff, 3, _SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, _SB.PCI0.LPCB.LNKE, 0 }, Package() { 0x0015ffff, 1, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 2, _SB.PCI0.LPCB.LNKF, 0 }, Package() { 0x0015ffff, 3, _SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, }) } diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl index a83f23e..34244e3 100644 --- a/src/mainboard/google/slippy/acpi/superio.asl +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -20,10 +20,10 @@ /* mainboard configuration */ #include <mainboard/google/slippy/ec.h>
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
/* ACPI code for EC SuperIO functions */ #include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 7a3ccea..313a939 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -241,7 +241,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; acpi_save_gnvs((unsigned long)gnvs); break; diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index 0919f0f..74bb385 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -32,7 +32,7 @@ void mainboard_ec_init(void) /* Restore SCI event mask on resume. */ if (acpi_slp_type == 3) { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S3_WAKE_EVENTS); + MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */ google_chromeec_set_smi_mask(0); @@ -42,7 +42,7 @@ void mainboard_ec_init(void) google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); } else { google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | - MAINBOARD_EC_S5_WAKE_EVENTS); + MAINBOARD_EC_S5_WAKE_EVENTS); }
/* Clear wake events, these are enabled on entry to sleep */ diff --git a/src/mainboard/google/slippy/ec.h b/src/mainboard/google/slippy/ec.h index 11d2453..86be0df 100644 --- a/src/mainboard/google/slippy/ec.h +++ b/src/mainboard/google/slippy/ec.h @@ -22,17 +22,17 @@
#include <ec/google/chromeec/ec_commands.h>
-#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ -#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ +#define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ +#define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) @@ -42,7 +42,7 @@
/* EC can wake from S5 with lid or power button */ #define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/* EC can wake from S3 with lid or power button or key press */ diff --git a/src/mainboard/google/slippy/gpio.h b/src/mainboard/google/slippy/gpio.h index 2d47ea7..8922efa 100644 --- a/src/mainboard/google/slippy/gpio.h +++ b/src/mainboard/google/slippy/gpio.h @@ -23,101 +23,101 @@ struct pch_lp_gpio_map;
const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_UNUSED, /* 0: UNUSED */ - LP_GPIO_UNUSED, /* 1: UNUSED */ - LP_GPIO_UNUSED, /* 2: UNUSED */ - LP_GPIO_UNUSED, /* 3: UNUSED */ - LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - LP_GPIO_INPUT, /* 9: RAM_ID1 */ - LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - LP_GPIO_UNUSED, /* 11: UNUSED */ + LP_GPIO_UNUSED, /* 0: UNUSED */ + LP_GPIO_UNUSED, /* 1: UNUSED */ + LP_GPIO_UNUSED, /* 2: UNUSED */ + LP_GPIO_UNUSED, /* 3: UNUSED */ + LP_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + LP_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + LP_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + LP_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + LP_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ + LP_GPIO_INPUT, /* 9: RAM_ID1 */ + LP_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + LP_GPIO_UNUSED, /* 11: UNUSED */ LP_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ - LP_GPIO_INPUT, /* 13: RAM_ID0 */ - LP_GPIO_INPUT, /* 14: EC_IN_RW */ - LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ - LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ - LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ - LP_GPIO_UNUSED, /* 20: UNUSED */ - LP_GPIO_UNUSED, /* 21: UNUSED */ - LP_GPIO_UNUSED, /* 22: UNUSED */ - LP_GPIO_UNUSED, /* 23: UNUSED */ - LP_GPIO_UNUSED, /* 24: UNUSED */ + LP_GPIO_INPUT, /* 13: RAM_ID0 */ + LP_GPIO_INPUT, /* 14: EC_IN_RW */ + LP_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + LP_GPIO_OUT_LOW, /* 16: PCH_SSD_12_EN (iSSD VDDC) */ + LP_GPIO_OUT_LOW, /* 17: PCH_SSD_18_EN (iSSD VCCQ) */ + LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ + LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_UNUSED, /* 20: UNUSED */ + LP_GPIO_UNUSED, /* 21: UNUSED */ + LP_GPIO_UNUSED, /* 22: UNUSED */ + LP_GPIO_UNUSED, /* 23: UNUSED */ + LP_GPIO_UNUSED, /* 24: UNUSED */ LP_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ - LP_GPIO_UNUSED, /* 26: UNUSED */ - LP_GPIO_UNUSED, /* 27: UNUSED */ - LP_GPIO_UNUSED, /* 28: UNUSED */ - LP_GPIO_UNUSED, /* 29: UNUSED */ - LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - LP_GPIO_UNUSED, /* 37: UNUSED */ - LP_GPIO_UNUSED, /* 38: UNUSED */ - LP_GPIO_UNUSED, /* 39: UNUSED */ - LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - LP_GPIO_UNUSED, /* 41: UNUSED */ - LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - LP_GPIO_UNUSED, /* 43: UNUSED */ - LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ - LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ - LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - LP_GPIO_INPUT, /* 47: RAM_ID2 */ - LP_GPIO_UNUSED, /* 48: UNUSED */ - LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ - LP_GPIO_UNUSED, /* 50: UNUSED */ - LP_GPIO_INPUT, /* 51: ALS_INT_L */ - LP_GPIO_INPUT, /* 52: SIM_DET */ - LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ - LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ - LP_GPIO_UNUSED, /* 55: UNUSED */ - LP_GPIO_UNUSED, /* 56: UNUSED */ - LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ - LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ - LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ - LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - LP_GPIO_UNUSED, /* 64: UNUSED */ - LP_GPIO_UNUSED, /* 65: UNUSED */ - LP_GPIO_UNUSED, /* 66: UNUSED */ - LP_GPIO_UNUSED, /* 67: UNUSED */ - LP_GPIO_UNUSED, /* 68: UNUSED */ - LP_GPIO_UNUSED, /* 69: UNUSED */ - LP_GPIO_UNUSED, /* 70: UNUSED */ - LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ - LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ - LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - LP_GPIO_UNUSED, /* 76: UNUSED */ - LP_GPIO_UNUSED, /* 77: UNUSED */ - LP_GPIO_UNUSED, /* 78: UNUSED */ - LP_GPIO_UNUSED, /* 79: UNUSED */ - LP_GPIO_UNUSED, /* 80: UNUSED */ - LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - LP_GPIO_UNUSED, /* 83: UNUSED */ - LP_GPIO_UNUSED, /* 84: UNUSED */ - LP_GPIO_UNUSED, /* 85: UNUSED */ - LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - LP_GPIO_UNUSED, /* 87: UNUSED */ - LP_GPIO_UNUSED, /* 88: UNUSED */ - LP_GPIO_UNUSED, /* 89: UNUSED */ - LP_GPIO_UNUSED, /* 90: UNUSED */ - LP_GPIO_UNUSED, /* 91: UNUSED */ - LP_GPIO_UNUSED, /* 92: UNUSED */ - LP_GPIO_UNUSED, /* 93: UNUSED */ - LP_GPIO_UNUSED, /* 94: UNUSED */ + LP_GPIO_UNUSED, /* 26: UNUSED */ + LP_GPIO_UNUSED, /* 27: UNUSED */ + LP_GPIO_UNUSED, /* 28: UNUSED */ + LP_GPIO_UNUSED, /* 29: UNUSED */ + LP_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + LP_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ + LP_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + LP_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + LP_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + LP_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + LP_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + LP_GPIO_UNUSED, /* 37: UNUSED */ + LP_GPIO_UNUSED, /* 38: UNUSED */ + LP_GPIO_UNUSED, /* 39: UNUSED */ + LP_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + LP_GPIO_UNUSED, /* 41: UNUSED */ + LP_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + LP_GPIO_UNUSED, /* 43: UNUSED */ + LP_GPIO_OUT_LOW, /* 44: PP3300_SSD_EN (iSSD VCC_FLASH) */ + LP_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ + LP_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ + LP_GPIO_INPUT, /* 47: RAM_ID2 */ + LP_GPIO_UNUSED, /* 48: UNUSED */ + LP_GPIO_OUT_LOW, /* 49: PP3300_SSD_IO_EN (iSSD VCC_IO) */ + LP_GPIO_UNUSED, /* 50: UNUSED */ + LP_GPIO_INPUT, /* 51: ALS_INT_L */ + LP_GPIO_INPUT, /* 52: SIM_DET */ + LP_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX (PIRQV) */ + LP_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX (PIRQW) */ + LP_GPIO_UNUSED, /* 55: UNUSED */ + LP_GPIO_UNUSED, /* 56: UNUSED */ + LP_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ + LP_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + LP_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + LP_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ + LP_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ + LP_GPIO_NATIVE, /* 62: NATIVE: PCH_SUS_CLK */ + LP_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + LP_GPIO_UNUSED, /* 64: UNUSED */ + LP_GPIO_UNUSED, /* 65: UNUSED */ + LP_GPIO_UNUSED, /* 66: UNUSED */ + LP_GPIO_UNUSED, /* 67: UNUSED */ + LP_GPIO_UNUSED, /* 68: UNUSED */ + LP_GPIO_UNUSED, /* 69: UNUSED */ + LP_GPIO_UNUSED, /* 70: UNUSED */ + LP_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + LP_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ + LP_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ + LP_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + LP_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + LP_GPIO_UNUSED, /* 76: UNUSED */ + LP_GPIO_UNUSED, /* 77: UNUSED */ + LP_GPIO_UNUSED, /* 78: UNUSED */ + LP_GPIO_UNUSED, /* 79: UNUSED */ + LP_GPIO_UNUSED, /* 80: UNUSED */ + LP_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + LP_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + LP_GPIO_UNUSED, /* 83: UNUSED */ + LP_GPIO_UNUSED, /* 84: UNUSED */ + LP_GPIO_UNUSED, /* 85: UNUSED */ + LP_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + LP_GPIO_UNUSED, /* 87: UNUSED */ + LP_GPIO_UNUSED, /* 88: UNUSED */ + LP_GPIO_UNUSED, /* 89: UNUSED */ + LP_GPIO_UNUSED, /* 90: UNUSED */ + LP_GPIO_UNUSED, /* 91: UNUSED */ + LP_GPIO_UNUSED, /* 92: UNUSED */ + LP_GPIO_UNUSED, /* 93: UNUSED */ + LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END };
diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 3bf26e3..dc4338a 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -51,7 +51,7 @@ static int int15_handler(void) int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f34: @@ -60,7 +60,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CX = 0x0001; @@ -117,13 +117,13 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 8679adb..3a5423a 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -34,14 +34,14 @@ const struct rcba_config_instruction rcba_config[] = {
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD + * D29IP_E1P EHCI INTA -> PIRQD * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ @@ -93,9 +93,9 @@ static void copy_spd(struct pei_data *peid) die("Missing SPD data.");
memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + ((char*)CBFS_SUBHEADER(spd_file)) + + spd_index * sizeof(peid->spd_data[0]), + sizeof(peid->spd_data[0])); }
/* @@ -103,10 +103,10 @@ static void copy_spd(struct pei_data *peid) * * Must be sequenced in this order with specified timing. * - * 1. VCC_IO : 30us - 100ms + * 1. VCC_IO : 30us - 100ms * 2. VCC_FLASH : 70us - 10ms - * 3. VCCQ : 70us - 10ms - * 4. VDDC : 30us - 100ms + * 3. VCCQ : 70us - 10ms + * 4. VDDC : 30us - 100ms * * There is no feedback to know if the voltage has stabilized * so this implementation will use the max ramp times. That @@ -120,8 +120,8 @@ static void issd_power_sequence(void) } issd_gpio_seq[] = { { 49, 100 }, /* VCC_IO: GPIO 49, wait 100ms */ { 44, 10 }, /* VCC_FLASH: GPIO 44, wait 10ms */ - { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ - { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ + { 17, 10 }, /* VCCQ: GPIO 17, wait 10ms */ + { 16, 100 }, /* VDDC: GPIO 16, wait 100ms */ }; int step;
@@ -161,18 +161,18 @@ void mainboard_romstage_entry(unsigned long bist) usb2_ports: { /* Length, Enable, OCn# */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */ - { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ + { 0x0040, 1, 0 }, /* P1: Port A, CN10 */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */ - { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ + { 0x0040, 1, 2 }, /* P4: Port B, CN6 */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */ { 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */ { 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */ }, usb3_ports: { /* Enable, OCn# */ - { 1, 0 }, /* P1; Port A, CN10 */ - { 1, 2 }, /* P2; Port B, CN6 */ + { 1, 0 }, /* P1; Port A, CN10 */ + { 1, 2 }, /* P2; Port B, CN6 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c index 977dbbc..1d144bd 100644 --- a/src/mainboard/google/snow/memory.c +++ b/src/mainboard/google/snow/memory.c @@ -468,7 +468,7 @@ struct { enum mvl3 id0, id1; enum board_config config; } id_map[] = { - /* ID0 ID1 config */ + /* ID0 ID1 config */ { LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP }, { LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP }, { LOGIC_1, LOGIC_0, SNOW_CONFIG_SAMSUNG_DVT }, diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7442f7a..8df9122 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -135,10 +135,10 @@ static void setup_gpio(void) static void setup_memory(struct mem_timings *mem, int is_resume) { printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", - mem->mem_manuf, - mem->mem_type, - mem->mpll_mdiv, - mem->frequency_mhz); + mem->mem_manuf, + mem->mem_type, + mem->mpll_mdiv, + mem->frequency_mhz);
/* FIXME Currently memory initialization with mem_reset on normal boot * will cause resume to fail (even if we don't do mem_reset on resume), diff --git a/src/mainboard/google/stout/acpi/superio.asl b/src/mainboard/google/stout/acpi/superio.asl index feb4210..33dcec3 100644 --- a/src/mainboard/google/stout/acpi/superio.asl +++ b/src/mainboard/google/stout/acpi/superio.asl @@ -20,8 +20,8 @@ /* mainboard configuration */ #include "../ec.h"
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
/* ACPI code for EC SuperIO functions */ #include <ec/quanta/it8518/acpi/superio.asl> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 62d5891..fb5dd7e 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -230,7 +230,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 7a861ec..828c98e 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -121,16 +121,16 @@ int get_recovery_mode_switch(void) u8 ec_status = ec_read(EC_STATUS_REG); u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
- printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", + printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD);
#ifdef __PRE_RAM__ return (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); + ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); #else if (!ec_rec_flag_good) { ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); + ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); ec_rec_flag_good = 1; } return ec_in_rec_mode; diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..d45a5a8 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -4,10 +4,10 @@ chip northbridge/intel/sandybridge register "gpu_dp_d_hotplug" = "0x06"
# Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms - register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms - register "gpu_panel_power_down_delay" = "150" # T3: 15ms + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms + register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms + register "gpu_panel_power_down_delay" = "150" # T3: 15ms register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 925dfd1..dbba2b5 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -21,7 +21,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 + 0x02, // DSDT revision: ACPI v2.0 "COREv4", // OEM id "COREBOOT", // OEM table id 0x20110725 // OEM revision diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c index 474d96f..c80e3db 100644 --- a/src/mainboard/google/stout/ec.c +++ b/src/mainboard/google/stout/ec.c @@ -54,7 +54,7 @@ void stout_ec_init(void) * 0/0 All USB port off * 1/0 USB on, all USB port didn’t support wake up * 0/1 USB on, yellow port support wake up charge, but may not support - * charge smart phone. + * charge smart phone. * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system. */ ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) & 0xE); diff --git a/src/mainboard/google/stout/ec.h b/src/mainboard/google/stout/ec.h index 6a9ef4f..e63e45c 100644 --- a/src/mainboard/google/stout/ec.h +++ b/src/mainboard/google/stout/ec.h @@ -20,8 +20,8 @@ #ifndef STOUT_EC_H #define STOUT_EC_H
-#define EC_SCI_GPI 6 /* GPIO6 is EC_SCI# */ -#define EC_SMI_GPI 1 /* GPIO1 is EC_SMI# */ +#define EC_SCI_GPI 6 /* GPIO6 is EC_SCI# */ +#define EC_SMI_GPI 1 /* GPIO1 is EC_SMI# */
#define EC_SMI_LID_CLOSED 0x2B
diff --git a/src/mainboard/google/stout/fadt.c b/src/mainboard/google/stout/fadt.c index 5ce9ab1..1a09ccc 100644 --- a/src/mainboard/google/stout/fadt.c +++ b/src/mainboard/google/stout/fadt.c @@ -26,11 +26,11 @@ * code and the mainboard fadt. */ #define APM_CNT 0xb2 -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x80 -#define ACPI_DISABLE 0x1e -#define ACPI_ENABLE 0xe1 -#define GNVS_UPDATE 0xea +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 +#define ACPI_DISABLE 0x1e +#define ACPI_ENABLE 0xe1 +#define GNVS_UPDATE 0xea
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h index 7bc4667..eec72cf 100644 --- a/src/mainboard/google/stout/gpio.h +++ b/src/mainboard/google/stout/gpio.h @@ -60,7 +60,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { const struct pch_gpio_set1 pch_gpio_set1_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. + * direction configured. */ .gpio0 = GPIO_DIR_OUTPUT, .gpio1 = GPIO_DIR_INPUT, @@ -93,7 +93,7 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { const struct pch_gpio_set1 pch_gpio_set1_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. + * level set. */ .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_LOW, @@ -167,7 +167,7 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { const struct pch_gpio_set2 pch_gpio_set2_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. + * direction configured. */ .gpio33 = GPIO_DIR_OUTPUT, .gpio34 = GPIO_DIR_OUTPUT, @@ -197,7 +197,7 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { const struct pch_gpio_set2 pch_gpio_set2_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. + * level set. */ .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_HIGH, @@ -242,7 +242,7 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { const struct pch_gpio_set3 pch_gpio_set3_direction = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * direction configured. + * direction configured. */ .gpio64 = GPIO_DIR_OUTPUT, .gpio65 = GPIO_DIR_OUTPUT, @@ -258,7 +258,7 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { const struct pch_gpio_set3 pch_gpio_set3_level = { /* * Note: Only gpio configured as "gpio" or "none" need to have the - * level set. + * level set. */ .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_LOW, @@ -273,18 +273,18 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map stout_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/google/stout/i915.c b/src/mainboard/google/stout/i915.c index 89a8594..1581076 100644 --- a/src/mainboard/google/stout/i915.c +++ b/src/mainboard/google/stout/i915.c @@ -77,12 +77,12 @@ PTEs static void setgtt(int start, int end, unsigned long base, int inc) { - int i; + int i;
for(i = start; i < end; i++){ - u32 word = base + i*inc; - WRITE32(word|1,(i*4)|1); - } + u32 word = base + i*inc; + WRITE32(word|1,(i*4)|1); + } }
static char *regname(unsigned long addr) diff --git a/src/mainboard/google/stout/i915_reg.h b/src/mainboard/google/stout/i915_reg.h index 11c198a..a47370b 100644 --- a/src/mainboard/google/stout/i915_reg.h +++ b/src/mainboard/google/stout/i915_reg.h @@ -39,36 +39,36 @@ /* PCI config space */
#define HPLLCC 0xc0 /* 855 only */ -#define GC_CLOCK_CONTROL_MASK (0xf << 0) -#define GC_CLOCK_133_200 (0 << 0) -#define GC_CLOCK_100_200 (1 << 0) -#define GC_CLOCK_100_133 (2 << 0) -#define GC_CLOCK_166_250 (3 << 0) +#define GC_CLOCK_CONTROL_MASK (0xf << 0) +#define GC_CLOCK_133_200 (0 << 0) +#define GC_CLOCK_100_200 (1 << 0) +#define GC_CLOCK_100_133 (2 << 0) +#define GC_CLOCK_166_250 (3 << 0) #define GCFGC2 0xda #define GCFGC 0xf0 /* 915+ only */ -#define GC_LOW_FREQUENCY_ENABLE (1 << 7) -#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) -#define GC_DISPLAY_CLOCK_MASK (7 << 4) -#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) -#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) -#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) -#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) -#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) -#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) -#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) -#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) -#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) -#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) -#define I945_GC_RENDER_CLOCK_MASK (7 << 0) -#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) -#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) -#define I915_GC_RENDER_CLOCK_MASK (7 << 0) -#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) -#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) -#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) +#define GC_LOW_FREQUENCY_ENABLE (1 << 7) +#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_MASK (7 << 4) +#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) +#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) +#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) +#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) +#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) +#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) +#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) +#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) +#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) +#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) +#define I945_GC_RENDER_CLOCK_MASK (7 << 0) +#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) +#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) +#define I915_GC_RENDER_CLOCK_MASK (7 << 0) +#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) +#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) +#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) #define LBB 0xf4
/* Graphics reset regs */ @@ -79,19 +79,19 @@ #define GRDOM_MEDIA (3<<2)
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ -#define GEN6_MBC_SNPCR_SHIFT 21 -#define GEN6_MBC_SNPCR_MASK (3<<21) -#define GEN6_MBC_SNPCR_MAX (0<<21) -#define GEN6_MBC_SNPCR_MED (1<<21) -#define GEN6_MBC_SNPCR_LOW (2<<21) -#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ +#define GEN6_MBC_SNPCR_SHIFT 21 +#define GEN6_MBC_SNPCR_MASK (3<<21) +#define GEN6_MBC_SNPCR_MAX (0<<21) +#define GEN6_MBC_SNPCR_MED (1<<21) +#define GEN6_MBC_SNPCR_LOW (2<<21) +#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
#define GEN6_MBCTL 0x0907c -#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) -#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) -#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) -#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) -#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) +#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) +#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) +#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) +#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) +#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
#define GEN6_GDRST 0x941c #define GEN6_GRDOM_FULL (1 << 0) @@ -118,12 +118,12 @@ #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) -#define PP_DIR_DCLV_2G 0xffffffff +#define PP_DIR_DCLV_2G 0xffffffff
#define GAM_ECOCHK 0x4090 -#define ECOCHK_SNB_BIT (1<<10) -#define ECOCHK_PPGTT_CACHE64B (0x3<<3) -#define ECOCHK_PPGTT_CACHE4B (0x0<<3) +#define ECOCHK_SNB_BIT (1<<10) +#define ECOCHK_PPGTT_CACHE64B (0x3<<3) +#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
/* VGA stuff */
@@ -132,29 +132,29 @@
#define VGA_MSR_WRITE 0x3c2 #define VGA_MSR_READ 0x3cc -#define VGA_MSR_MEM_EN (1<<1) -#define VGA_MSR_CGA_MODE (1<<0) +#define VGA_MSR_MEM_EN (1<<1) +#define VGA_MSR_CGA_MODE (1<<0)
#define VGA_SR_INDEX 0x3c4 #define VGA_SR_DATA 0x3c5
#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) +#define VGA_AR_VID_EN (1<<5) #define VGA_AR_DATA_WRITE 0x3c0 #define VGA_AR_DATA_READ 0x3c1
#define VGA_GR_INDEX 0x3ce #define VGA_GR_DATA 0x3cf /* GR05 */ -#define VGA_GR_MEM_READ_MODE_SHIFT 3 -#define VGA_GR_MEM_READ_MODE_PLANE 1 +#define VGA_GR_MEM_READ_MODE_SHIFT 3 +#define VGA_GR_MEM_READ_MODE_PLANE 1 /* GR06 */ -#define VGA_GR_MEM_MODE_MASK 0xc -#define VGA_GR_MEM_MODE_SHIFT 2 -#define VGA_GR_MEM_A0000_AFFFF 0 -#define VGA_GR_MEM_A0000_BFFFF 1 -#define VGA_GR_MEM_B0000_B7FFF 2 -#define VGA_GR_MEM_B0000_BFFFF 3 +#define VGA_GR_MEM_MODE_MASK 0xc +#define VGA_GR_MEM_MODE_SHIFT 2 +#define VGA_GR_MEM_A0000_AFFFF 0 +#define VGA_GR_MEM_A0000_BFFFF 1 +#define VGA_GR_MEM_B0000_B7FFF 2 +#define VGA_GR_MEM_B0000_BFFFF 3
#define VGA_DACMASK 0x3c6 #define VGA_DACRX 0x3c7 @@ -173,41 +173,41 @@
#define MI_NOOP MI_INSTR(0, 0) #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ +#define MI_READ_FLUSH (1 << 0) +#define MI_EXE_FLUSH (1 << 1) +#define MI_NO_WRITE_FLUSH (1 << 2) +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ +#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) +#define MI_SUSPEND_FLUSH_EN (1<<0) #define MI_REPORT_HEAD MI_INSTR(0x07, 0) #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON (0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) +#define MI_OVERLAY_CONTINUE (0x0<<21) +#define MI_OVERLAY_ON (0x1<<21) +#define MI_OVERLAY_OFF (0x2<<21) #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) +#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) #define MI_SET_CONTEXT MI_INSTR(0x18, 0) -#define MI_MM_SPACE_GTT (1<<8) -#define MI_MM_SPACE_PHYSICAL (0<<8) -#define MI_SAVE_EXT_STATE_EN (1<<3) -#define MI_RESTORE_EXT_STATE_EN (1<<2) -#define MI_FORCE_RESTORE (1<<1) -#define MI_RESTORE_INHIBIT (1<<0) +#define MI_MM_SPACE_GTT (1<<8) +#define MI_MM_SPACE_PHYSICAL (0<<8) +#define MI_SAVE_EXT_STATE_EN (1<<3) +#define MI_RESTORE_EXT_STATE_EN (1<<2) +#define MI_FORCE_RESTORE (1<<1) +#define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 +#define MI_STORE_DWORD_INDEX_SHIFT 2 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. @@ -216,23 +216,23 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) +#define MI_INVALIDATE_TLB (1<<18) +#define MI_INVALIDATE_BSD (1<<7) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER (1<<18) -#define MI_SEMAPHORE_SYNC_RV (2<<16) -#define MI_SEMAPHORE_SYNC_RB (0<<16) -#define MI_SEMAPHORE_SYNC_VR (0<<16) -#define MI_SEMAPHORE_SYNC_VB (2<<16) -#define MI_SEMAPHORE_SYNC_BR (2<<16) -#define MI_SEMAPHORE_SYNC_BV (0<<16) +#define MI_SEMAPHORE_UPDATE (1<<21) +#define MI_SEMAPHORE_COMPARE (1<<20) +#define MI_SEMAPHORE_REGISTER (1<<18) +#define MI_SEMAPHORE_SYNC_RV (2<<16) +#define MI_SEMAPHORE_SYNC_RB (0<<16) +#define MI_SEMAPHORE_SYNC_VR (0<<16) +#define MI_SEMAPHORE_SYNC_VB (2<<16) +#define MI_SEMAPHORE_SYNC_BR (2<<16) +#define MI_SEMAPHORE_SYNC_BV (0<<16) #define MI_SEMAPHORE_SYNC_INVALID (1<<0) /* * 3D instructions used by the kernel @@ -240,57 +240,57 @@ #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) +#define BLT_DEPTH_8 (0<<24) +#define BLT_DEPTH_16_565 (1<<24) +#define BLT_DEPTH_16_1555 (2<<24) +#define BLT_DEPTH_32 (3<<24) +#define BLT_ROP_GXCOPY (0xcc<<16) #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) +#define ASYNC_FLIP (1<<22) +#define DISPLAY_PLANE_A (0<<20) +#define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) -#define PIPE_CONTROL_CS_STALL (1<<20) -#define PIPE_CONTROL_QW_WRITE (1<<14) -#define PIPE_CONTROL_DEPTH_STALL (1<<13) -#define PIPE_CONTROL_WRITE_FLUSH (1<<12) -#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ -#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ -#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ -#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_NOTIFY (1<<8) -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_CS_STALL (1<<20) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WRITE_FLUSH (1<<12) +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ +#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) +#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) +#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
/* @@ -307,32 +307,32 @@ */ #define FENCE_REG_830_0 0x2000 #define FENCE_REG_945_8 0x3000 -#define I830_FENCE_START_MASK 0x07f80000 -#define I830_FENCE_TILING_Y_SHIFT 12 -#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) -#define I830_FENCE_PITCH_SHIFT 4 -#define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 4 -#define I830_FENCE_MAX_PITCH_VAL 6 -#define I830_FENCE_MAX_SIZE_VAL (1<<8) - -#define I915_FENCE_START_MASK 0x0ff00000 -#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) +#define I915_FENCE_MAX_PITCH_VAL 4 +#define I830_FENCE_MAX_PITCH_VAL 6 +#define I830_FENCE_MAX_SIZE_VAL (1<<8) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
#define FENCE_REG_965_0 0x03000 -#define I965_FENCE_PITCH_SHIFT 2 -#define I965_FENCE_TILING_Y_SHIFT 1 -#define I965_FENCE_REG_VALID (1<<0) -#define I965_FENCE_MAX_PITCH_VAL 0x0400 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) +#define I965_FENCE_MAX_PITCH_VAL 0x0400
#define FENCE_REG_SANDYBRIDGE_0 0x100000 -#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
/* control register for cpu gtt access */ #define TILECTL 0x101000 -#define TILECTL_SWZCTL (1 << 0) -#define TILECTL_TLB_PREFETCH_DIS (1 << 2) -#define TILECTL_BACKSNOOP_DIS (1 << 3) +#define TILECTL_SWZCTL (1 << 0) +#define TILECTL_TLB_PREFETCH_DIS (1 << 2) +#define TILECTL_BACKSNOOP_DIS (1 << 3)
/* * Instruction and interrupt control regs @@ -358,10 +358,10 @@ #define RING_HWS_PGA(base) ((base)+0x80) #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) #define ARB_MODE 0x04030 -#define ARB_MODE_SWIZZLE_SNB (1<<4) -#define ARB_MODE_SWIZZLE_IVB (1<<5) -#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) -#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) +#define ARB_MODE_SWIZZLE_SNB (1<<4) +#define ARB_MODE_SWIZZLE_IVB (1<<5) +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) #define RENDER_HWS_PGA_GEN7 (0x04080) #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) #define DONE_REG 0x40b0 @@ -370,21 +370,21 @@ #define RING_ACTHD(base) ((base)+0x74) #define RING_NOPID(base) ((base)+0x94) #define RING_IMR(base) ((base)+0xa8) -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ -#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ -#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ +#define TAIL_ADDR 0x001FFFF8 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ +#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 #define PRB0_START 0x02038 @@ -411,7 +411,7 @@ #define HWS_ADDRESS_MASK 0xfffff000 #define HWS_START_ADDRESS_SHIFT 4 #define PWRCTXA 0x2088 /* 965GM+ only */ -#define PWRCTX_EN (1<<0) +#define PWRCTX_EN (1<<0) #define IPEIR 0x02088 #define IPEHR 0x0208c #define INSTDONE 0x02090 @@ -440,12 +440,12 @@ #define GFX_MODE 0x02520 #define GFX_MODE_GEN7 0x0229c #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) -#define GFX_RUN_LIST_ENABLE (1<<15) -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) -#define GFX_SURFACE_FAULT_ENABLE (1<<12) -#define GFX_REPLAY_MODE (1<<11) -#define GFX_PSMI_GRANULARITY (1<<10) -#define GFX_PPGTT_ENABLE (1<<9) +#define GFX_RUN_LIST_ENABLE (1<<15) +#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) +#define GFX_SURFACE_FAULT_ENABLE (1<<12) +#define GFX_REPLAY_MODE (1<<11) +#define GFX_PSMI_GRANULARITY (1<<10) +#define GFX_PPGTT_ENABLE (1<<9)
#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) @@ -455,163 +455,163 @@ #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) +#define I915_DISPLAY_PORT_INTERRUPT (1<<17) +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ +#define I915_HWB_OOM_INTERRUPT (1<<13) +#define I915_SYNC_STATUS_INTERRUPT (1<<12) +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) +#define I915_DEBUG_INTERRUPT (1<<2) +#define I915_USER_INTERRUPT (1<<1) +#define I915_ASLE_INTERRUPT (1<<0) +#define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 #define ESR 0x020b8 -#define GM45_ERROR_PAGE_TABLE (1<<5) -#define GM45_ERROR_MEM_PRIV (1<<4) -#define I915_ERROR_PAGE_TABLE (1<<4) -#define GM45_ERROR_CP_PRIV (1<<3) -#define I915_ERROR_MEMORY_REFRESH (1<<1) -#define I915_ERROR_INSTRUCTION (1<<0) -#define INSTPM 0x020c0 -#define INSTPM_SELF_EN (1<<12) /* 915GM only */ -#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts +#define GM45_ERROR_PAGE_TABLE (1<<5) +#define GM45_ERROR_MEM_PRIV (1<<4) +#define I915_ERROR_PAGE_TABLE (1<<4) +#define GM45_ERROR_CP_PRIV (1<<3) +#define I915_ERROR_MEMORY_REFRESH (1<<1) +#define I915_ERROR_INSTRUCTION (1<<0) +#define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ +#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts will not assert AGPBUSY# and will only be delivered when out of C3. */ -#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ -#define ACTHD 0x020c8 +#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ +#define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1<<31) -#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ -#define MM_BURST_LENGTH 0x00700000 +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ +#define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 -#define LM_BURST_LENGTH 0x00000700 +#define LM_BURST_LENGTH 0x00000700 #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ +#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) +#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
/* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) */ -#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) +#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
/* Block grant count for isoch requests when block count is * set to a finite value. */ -#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) -#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ -#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ -#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ -#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ +#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) +#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ +#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ +#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ +#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
/* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. */ -#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) +#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
/* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. */ -#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) +#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
/* Enables non-sequential data reads through arbiter */ -#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) +#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
/* Disable FSB snooping of cacheable write cycles from binner/render * command stream */ -#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) +#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
/* Arbiter time slice for non-isoch streams */ -#define MI_ARB_TIME_SLICE_MASK (7 << 5) -#define MI_ARB_TIME_SLICE_1 (0 << 5) -#define MI_ARB_TIME_SLICE_2 (1 << 5) -#define MI_ARB_TIME_SLICE_4 (2 << 5) -#define MI_ARB_TIME_SLICE_6 (3 << 5) -#define MI_ARB_TIME_SLICE_8 (4 << 5) -#define MI_ARB_TIME_SLICE_10 (5 << 5) -#define MI_ARB_TIME_SLICE_14 (6 << 5) -#define MI_ARB_TIME_SLICE_16 (7 << 5) +#define MI_ARB_TIME_SLICE_MASK (7 << 5) +#define MI_ARB_TIME_SLICE_1 (0 << 5) +#define MI_ARB_TIME_SLICE_2 (1 << 5) +#define MI_ARB_TIME_SLICE_4 (2 << 5) +#define MI_ARB_TIME_SLICE_6 (3 << 5) +#define MI_ARB_TIME_SLICE_8 (4 << 5) +#define MI_ARB_TIME_SLICE_10 (5 << 5) +#define MI_ARB_TIME_SLICE_14 (6 << 5) +#define MI_ARB_TIME_SLICE_16 (7 << 5)
/* Low priority grace period page size */ -#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ -#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) +#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ +#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
/* Disable display A/B trickle feed */ -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
/* Set display plane priority */ -#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ -#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ +#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ +#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_MASK_SHIFT 16 +#define CM0_IZ_OPT_DISABLE (1<<6) +#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) +#define CM0_DEPTH_EVICT_DISABLE (1<<4) +#define CM0_COLOR_EVICT_DISABLE (1<<3) +#define CM0_DEPTH_WRITE_DISABLE (1<<1) +#define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ #define ECOSKPD 0x021d0 -#define ECO_GATING_CX_ONLY (1<<3) -#define ECO_FLIP_DONE (1<<0) +#define ECO_GATING_CX_ONLY (1<<3) +#define ECO_FLIP_DONE (1<<0)
/* GEN6 interrupt control */ #define GEN6_RENDER_HWSTAM 0x2098 #define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
#define GEN6_BLITTER_HWSTAM 0x22098 #define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
#define GEN6_BLITTER_ECOSKPD 0x221d0 -#define GEN6_BLITTER_LOCK_SHIFT 16 -#define GEN6_BLITTER_FBC_NOTIFY (1<<3) +#define GEN6_BLITTER_LOCK_SHIFT 16 +#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 +#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
#define GEN6_BSD_HWSTAM 0x12098 #define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) +#define GEN6_BSD_USER_INTERRUPT (1 << 12)
#define GEN6_BSD_RNCID 0x12198
@@ -622,29 +622,29 @@ #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ #define FBC_LL_BASE 0x03204 /* 4k page aligned */ #define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_C3_IDLE (1<<13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_C3_IDLE (1<<13) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) +#define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) #define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) #define FBC_FENCE_OFF 0x0321b #define FBC_TAG 0x03300
@@ -653,45 +653,45 @@ /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE 0x3200 #define DPFC_CONTROL 0x3208 -#define DPFC_CTL_EN (1<<31) -#define DPFC_CTL_PLANEA (0<<30) -#define DPFC_CTL_PLANEB (1<<30) -#define DPFC_CTL_FENCE_EN (1<<29) -#define DPFC_CTL_PERSISTENT_MODE (1<<25) -#define DPFC_SR_EN (1<<10) -#define DPFC_CTL_LIMIT_1X (0<<6) -#define DPFC_CTL_LIMIT_2X (1<<6) -#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_PERSISTENT_MODE (1<<25) +#define DPFC_SR_EN (1<<10) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) #define DPFC_RECOMP_CTL 0x320c -#define DPFC_RECOMP_STALL_EN (1<<27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) #define DPFC_STATUS 0x3210 -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) #define DPFC_STATUS2 0x3214 #define DPFC_FENCE_YOFF 0x3218 #define DPFC_CHICKEN 0x3224 -#define DPFC_HT_MODIFY (1<<31) +#define DPFC_HT_MODIFY (1<<31)
/* Framebuffer compression for Ironlake */ #define ILK_DPFC_CB_BASE 0x43200 #define ILK_DPFC_CONTROL 0x43208 /* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) +#define DPFC_RESERVED (0x1FFFFF00) #define ILK_DPFC_RECOMP_CTL 0x4320c #define ILK_DPFC_STATUS 0x43210 #define ILK_DPFC_FENCE_YOFF 0x43218 #define ILK_DPFC_CHICKEN 0x43224 #define ILK_FBC_RT_BASE 0x2128 -#define ILK_FBC_RT_VALID (1<<0) +#define ILK_FBC_RT_VALID (1<<0)
#define ILK_DISPLAY_CHICKEN1 0x42000 -#define ILK_FBCQ_DIS (1<<22) +#define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21)
@@ -701,7 +701,7 @@ * The following two registers are of type GTTMMADR */ #define SNB_DPFC_CTL_SA 0x100100 -#define SNB_CPU_FENCE_ENABLE (1<<29) +#define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104
@@ -732,52 +732,52 @@ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
#define GMBUS0 0x5100 /* clock/port select */ -#define GMBUS_RATE_100KHZ (0<<8) -#define GMBUS_RATE_50KHZ (1<<8) -#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ -#define GMBUS_RATE_MASK (3<<8) -#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) -#define GMBUS_PORT_MASK 7 +#define GMBUS_RATE_100KHZ (0<<8) +#define GMBUS_RATE_50KHZ (1<<8) +#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ +#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ +#define GMBUS_RATE_MASK (3<<8) +#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ +#define GMBUS_PORT_DISABLED 0 +#define GMBUS_PORT_SSC 1 +#define GMBUS_PORT_VGADDC 2 +#define GMBUS_PORT_PANEL 3 +#define GMBUS_PORT_DPC 4 /* HDMIC */ +#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PORT_DPD 6 /* HDMID */ +#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ +#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PORT_MASK 7 #define GMBUS1 0x5104 /* command/status */ -#define GMBUS_SW_CLR_INT (1<<31) -#define GMBUS_SW_RDY (1<<30) -#define GMBUS_ENT (1<<29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0<<25) -#define GMBUS_CYCLE_WAIT (1<<25) -#define GMBUS_CYCLE_INDEX (2<<25) -#define GMBUS_CYCLE_STOP (4<<25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1<<0) -#define GMBUS_SLAVE_WRITE (0<<0) +#define GMBUS_SW_CLR_INT (1<<31) +#define GMBUS_SW_RDY (1<<30) +#define GMBUS_ENT (1<<29) /* enable timeout */ +#define GMBUS_CYCLE_NONE (0<<25) +#define GMBUS_CYCLE_WAIT (1<<25) +#define GMBUS_CYCLE_INDEX (2<<25) +#define GMBUS_CYCLE_STOP (4<<25) +#define GMBUS_BYTE_COUNT_SHIFT 16 +#define GMBUS_SLAVE_INDEX_SHIFT 8 +#define GMBUS_SLAVE_ADDR_SHIFT 1 +#define GMBUS_SLAVE_READ (1<<0) +#define GMBUS_SLAVE_WRITE (0<<0) #define GMBUS2 0x5108 /* status */ -#define GMBUS_INUSE (1<<15) -#define GMBUS_HW_WAIT_PHASE (1<<14) -#define GMBUS_STALL_TIMEOUT (1<<13) -#define GMBUS_INT (1<<12) -#define GMBUS_HW_RDY (1<<11) -#define GMBUS_SATOER (1<<10) -#define GMBUS_ACTIVE (1<<9) +#define GMBUS_INUSE (1<<15) +#define GMBUS_HW_WAIT_PHASE (1<<14) +#define GMBUS_STALL_TIMEOUT (1<<13) +#define GMBUS_INT (1<<12) +#define GMBUS_HW_RDY (1<<11) +#define GMBUS_SATOER (1<<10) +#define GMBUS_ACTIVE (1<<9) #define GMBUS3 0x510c /* data buffer bytes 3-0 */ #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ -#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) -#define GMBUS_NAK_EN (1<<3) -#define GMBUS_IDLE_EN (1<<2) -#define GMBUS_HW_WAIT_EN (1<<1) -#define GMBUS_HW_RDY_EN (1<<0) +#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) +#define GMBUS_NAK_EN (1<<3) +#define GMBUS_IDLE_EN (1<<2) +#define GMBUS_HW_WAIT_EN (1<<1) +#define GMBUS_HW_RDY_EN (1<<0) #define GMBUS5 0x5120 /* byte index */ -#define GMBUS_2BYTE_INDEX_EN (1<<31) +#define GMBUS_2BYTE_INDEX_EN (1<<31)
/* * Clock control & power management @@ -786,31 +786,31 @@ #define VGA0 0x6000 #define VGA1 0x6004 #define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) +#define VGA0_PD_P2_DIV_4 (1 << 7) +#define VGA0_PD_P1_DIV_2 (1 << 5) +#define VGA0_PD_P1_SHIFT 0 +#define VGA0_PD_P1_MASK (0x1f << 0) +#define VGA1_PD_P2_DIV_4 (1 << 15) +#define VGA1_PD_P1_DIV_2 (1 << 13) +#define VGA1_PD_P1_SHIFT 8 +#define VGA1_PD_P1_MASK (0x1f << 8) #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_DVO_HIGH_SPEED (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
#define SRX_INDEX 0x3c4 #define SRX_DATA 0x3c5 @@ -829,29 +829,29 @@
/* Scratch pad debug 0 reg: */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 /* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 /* Ironlake */ -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
/* * Parallel to Serial Load Pulse phase selection. @@ -859,25 +859,25 @@ * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) /* * SDVO multiplier for 945G/GM. Not used on 965. */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 +#define SDVO_MULTIPLIER_MASK 0x000000ff +#define SDVO_MULTIPLIER_SHIFT_HIRES 4 +#define SDVO_MULTIPLIER_SHIFT_VGA 0 #define _DPLL_A_MD 0x0601c /* 965+ only */ /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 /* * SDVO/UDI pixel multiplier. * @@ -895,15 +895,15 @@ * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 #define _DPLL_B_MD 0x06020 /* 965+ only */ #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) #define _FPA0 0x06040 @@ -912,25 +912,25 @@ #define _FPB1 0x0604c #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 #define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +#define DPLLB_TEST_N_BYPASS (1 << 19) +#define DPLLB_TEST_M_BYPASS (1 << 18) +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +#define DPLLA_TEST_N_BYPASS (1 << 3) +#define DPLLA_TEST_M_BYPASS (1 << 2) +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 #define DSTATE_GFX_RESET_I830 (1<<6) #define DSTATE_PLL_D3_OFF (1<<3) @@ -1044,7 +1044,7 @@ #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) #define RAMCLK_GATE_D 0x6210 /* CRL only */ -#define DEUC 0x6214 /* CRL only */ +#define DEUC 0x6214 /* CRL only */
/* * Palette regs @@ -1078,7 +1078,7 @@ #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** Pineview MCH register contains DDR3 setting */ -#define CSHRDDR3CTL 0x101a8 +#define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL_DDR3 (1 << 2)
/** 965 MCH register controlling DRAM channel configuration */ @@ -1089,23 +1089,23 @@ #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) -#define MAD_DIMM_ECC_MASK (0x3 << 24) -#define MAD_DIMM_ECC_OFF (0x0 << 24) -#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) -#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) -#define MAD_DIMM_ECC_ON (0x3 << 24) -#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) -#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) -#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ -#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ -#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) -#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) -#define MAD_DIMM_A_SELECT (0x1 << 16) +#define MAD_DIMM_ECC_MASK (0x3 << 24) +#define MAD_DIMM_ECC_OFF (0x0 << 24) +#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) +#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) +#define MAD_DIMM_ECC_ON (0x3 << 24) +#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) +#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) +#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ +#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ +#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) +#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) +#define MAD_DIMM_A_SELECT (0x1 << 16) /* DIMM sizes are in multiples of 256mb. */ -#define MAD_DIMM_B_SIZE_SHIFT 8 -#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) -#define MAD_DIMM_A_SIZE_SHIFT 0 -#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) +#define MAD_DIMM_B_SIZE_SHIFT 8 +#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) +#define MAD_DIMM_A_SIZE_SHIFT 0 +#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
/* Clocking configuration register */ @@ -1126,194 +1126,194 @@ #define CLKCFG_MEM_MASK (7 << 4)
#define TSC1 0x11001 -#define TSE (1<<0) +#define TSE (1<<0) #define TR1 0x11006 #define TSFS 0x11020 -#define TSFS_SLOPE_MASK 0x0000ff00 -#define TSFS_SLOPE_SHIFT 8 -#define TSFS_INTR_MASK 0x000000ff +#define TSFS_SLOPE_MASK 0x0000ff00 +#define TSFS_SLOPE_SHIFT 8 +#define TSFS_INTR_MASK 0x000000ff
#define CRSTANDVID 0x11100 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ -#define PXVFREQ_PX_MASK 0x7f000000 -#define PXVFREQ_PX_SHIFT 24 +#define PXVFREQ_PX_MASK 0x7f000000 +#define PXVFREQ_PX_SHIFT 24 #define VIDFREQ_BASE 0x11110 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ #define VIDFREQ2 0x11114 #define VIDFREQ3 0x11118 #define VIDFREQ4 0x1111c -#define VIDFREQ_P0_MASK 0x1f000000 -#define VIDFREQ_P0_SHIFT 24 -#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 -#define VIDFREQ_P0_CSCLK_SHIFT 20 -#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 -#define VIDFREQ_P0_CRCLK_SHIFT 16 -#define VIDFREQ_P1_MASK 0x00001f00 -#define VIDFREQ_P1_SHIFT 8 -#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 -#define VIDFREQ_P1_CSCLK_SHIFT 4 -#define VIDFREQ_P1_CRCLK_MASK 0x0000000f +#define VIDFREQ_P0_MASK 0x1f000000 +#define VIDFREQ_P0_SHIFT 24 +#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 +#define VIDFREQ_P0_CSCLK_SHIFT 20 +#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 +#define VIDFREQ_P0_CRCLK_SHIFT 16 +#define VIDFREQ_P1_MASK 0x00001f00 +#define VIDFREQ_P1_SHIFT 8 +#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 +#define VIDFREQ_P1_CSCLK_SHIFT 4 +#define VIDFREQ_P1_CRCLK_MASK 0x0000000f #define INTTOEXT_BASE_ILK 0x11300 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ -#define INTTOEXT_MAP3_SHIFT 24 -#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) -#define INTTOEXT_MAP2_SHIFT 16 -#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) -#define INTTOEXT_MAP1_SHIFT 8 -#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) -#define INTTOEXT_MAP0_SHIFT 0 -#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) +#define INTTOEXT_MAP3_SHIFT 24 +#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) +#define INTTOEXT_MAP2_SHIFT 16 +#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) +#define INTTOEXT_MAP1_SHIFT 8 +#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) +#define INTTOEXT_MAP0_SHIFT 0 +#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) #define MEMSWCTL 0x11170 /* Ironlake only */ -#define MEMCTL_CMD_MASK 0xe000 -#define MEMCTL_CMD_SHIFT 13 -#define MEMCTL_CMD_RCLK_OFF 0 -#define MEMCTL_CMD_RCLK_ON 1 -#define MEMCTL_CMD_CHFREQ 2 -#define MEMCTL_CMD_CHVID 3 -#define MEMCTL_CMD_VMMOFF 4 -#define MEMCTL_CMD_VMMON 5 -#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears - when command complete */ -#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ -#define MEMCTL_FREQ_SHIFT 8 -#define MEMCTL_SFCAVM (1<<7) -#define MEMCTL_TGT_VID_MASK 0x007f +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears + when command complete */ +#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ +#define MEMCTL_FREQ_SHIFT 8 +#define MEMCTL_SFCAVM (1<<7) +#define MEMCTL_TGT_VID_MASK 0x007f #define MEMIHYST 0x1117c #define MEMINTREN 0x11180 /* 16 bits */ -#define MEMINT_RSEXIT_EN (1<<8) -#define MEMINT_CX_SUPR_EN (1<<7) -#define MEMINT_CONT_BUSY_EN (1<<6) -#define MEMINT_AVG_BUSY_EN (1<<5) -#define MEMINT_EVAL_CHG_EN (1<<4) -#define MEMINT_MON_IDLE_EN (1<<3) -#define MEMINT_UP_EVAL_EN (1<<2) -#define MEMINT_DOWN_EVAL_EN (1<<1) -#define MEMINT_SW_CMD_EN (1<<0) +#define MEMINT_RSEXIT_EN (1<<8) +#define MEMINT_CX_SUPR_EN (1<<7) +#define MEMINT_CONT_BUSY_EN (1<<6) +#define MEMINT_AVG_BUSY_EN (1<<5) +#define MEMINT_EVAL_CHG_EN (1<<4) +#define MEMINT_MON_IDLE_EN (1<<3) +#define MEMINT_UP_EVAL_EN (1<<2) +#define MEMINT_DOWN_EVAL_EN (1<<1) +#define MEMINT_SW_CMD_EN (1<<0) #define MEMINTRSTR 0x11182 /* 16 bits */ -#define MEM_RSEXIT_MASK 0xc000 -#define MEM_RSEXIT_SHIFT 14 -#define MEM_CONT_BUSY_MASK 0x3000 -#define MEM_CONT_BUSY_SHIFT 12 -#define MEM_AVG_BUSY_MASK 0x0c00 -#define MEM_AVG_BUSY_SHIFT 10 -#define MEM_EVAL_CHG_MASK 0x0300 -#define MEM_EVAL_BUSY_SHIFT 8 -#define MEM_MON_IDLE_MASK 0x00c0 -#define MEM_MON_IDLE_SHIFT 6 -#define MEM_UP_EVAL_MASK 0x0030 -#define MEM_UP_EVAL_SHIFT 4 -#define MEM_DOWN_EVAL_MASK 0x000c -#define MEM_DOWN_EVAL_SHIFT 2 -#define MEM_SW_CMD_MASK 0x0003 -#define MEM_INT_STEER_GFX 0 -#define MEM_INT_STEER_CMR 1 -#define MEM_INT_STEER_SMI 2 -#define MEM_INT_STEER_SCI 3 +#define MEM_RSEXIT_MASK 0xc000 +#define MEM_RSEXIT_SHIFT 14 +#define MEM_CONT_BUSY_MASK 0x3000 +#define MEM_CONT_BUSY_SHIFT 12 +#define MEM_AVG_BUSY_MASK 0x0c00 +#define MEM_AVG_BUSY_SHIFT 10 +#define MEM_EVAL_CHG_MASK 0x0300 +#define MEM_EVAL_BUSY_SHIFT 8 +#define MEM_MON_IDLE_MASK 0x00c0 +#define MEM_MON_IDLE_SHIFT 6 +#define MEM_UP_EVAL_MASK 0x0030 +#define MEM_UP_EVAL_SHIFT 4 +#define MEM_DOWN_EVAL_MASK 0x000c +#define MEM_DOWN_EVAL_SHIFT 2 +#define MEM_SW_CMD_MASK 0x0003 +#define MEM_INT_STEER_GFX 0 +#define MEM_INT_STEER_CMR 1 +#define MEM_INT_STEER_SMI 2 +#define MEM_INT_STEER_SCI 3 #define MEMINTRSTS 0x11184 -#define MEMINT_RSEXIT (1<<7) -#define MEMINT_CONT_BUSY (1<<6) -#define MEMINT_AVG_BUSY (1<<5) -#define MEMINT_EVAL_CHG (1<<4) -#define MEMINT_MON_IDLE (1<<3) -#define MEMINT_UP_EVAL (1<<2) -#define MEMINT_DOWN_EVAL (1<<1) -#define MEMINT_SW_CMD (1<<0) +#define MEMINT_RSEXIT (1<<7) +#define MEMINT_CONT_BUSY (1<<6) +#define MEMINT_AVG_BUSY (1<<5) +#define MEMINT_EVAL_CHG (1<<4) +#define MEMINT_MON_IDLE (1<<3) +#define MEMINT_UP_EVAL (1<<2) +#define MEMINT_DOWN_EVAL (1<<1) +#define MEMINT_SW_CMD (1<<0) #define MEMMODECTL 0x11190 -#define MEMMODE_BOOST_EN (1<<31) -#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ -#define MEMMODE_BOOST_FREQ_SHIFT 24 -#define MEMMODE_IDLE_MODE_MASK 0x00030000 -#define MEMMODE_IDLE_MODE_SHIFT 16 -#define MEMMODE_IDLE_MODE_EVAL 0 -#define MEMMODE_IDLE_MODE_CONT 1 -#define MEMMODE_HWIDLE_EN (1<<15) -#define MEMMODE_SWMODE_EN (1<<14) -#define MEMMODE_RCLK_GATE (1<<13) -#define MEMMODE_HW_UPDATE (1<<12) -#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ -#define MEMMODE_FSTART_SHIFT 8 -#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ -#define MEMMODE_FMAX_SHIFT 4 -#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ +#define MEMMODE_BOOST_EN (1<<31) +#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ +#define MEMMODE_BOOST_FREQ_SHIFT 24 +#define MEMMODE_IDLE_MODE_MASK 0x00030000 +#define MEMMODE_IDLE_MODE_SHIFT 16 +#define MEMMODE_IDLE_MODE_EVAL 0 +#define MEMMODE_IDLE_MODE_CONT 1 +#define MEMMODE_HWIDLE_EN (1<<15) +#define MEMMODE_SWMODE_EN (1<<14) +#define MEMMODE_RCLK_GATE (1<<13) +#define MEMMODE_HW_UPDATE (1<<12) +#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ +#define MEMMODE_FSTART_SHIFT 8 +#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ +#define MEMMODE_FMAX_SHIFT 4 +#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ #define RCBMAXAVG 0x1119c #define MEMSWCTL2 0x1119e /* Cantiga only */ -#define SWMEMCMD_RENDER_OFF (0 << 13) -#define SWMEMCMD_RENDER_ON (1 << 13) -#define SWMEMCMD_SWFREQ (2 << 13) -#define SWMEMCMD_TARVID (3 << 13) -#define SWMEMCMD_VRM_OFF (4 << 13) -#define SWMEMCMD_VRM_ON (5 << 13) -#define CMDSTS (1<<12) -#define SFCAVM (1<<11) -#define SWFREQ_MASK 0x0380 /* P0-7 */ -#define SWFREQ_SHIFT 7 -#define TARVID_MASK 0x001f +#define SWMEMCMD_RENDER_OFF (0 << 13) +#define SWMEMCMD_RENDER_ON (1 << 13) +#define SWMEMCMD_SWFREQ (2 << 13) +#define SWMEMCMD_TARVID (3 << 13) +#define SWMEMCMD_VRM_OFF (4 << 13) +#define SWMEMCMD_VRM_ON (5 << 13) +#define CMDSTS (1<<12) +#define SFCAVM (1<<11) +#define SWFREQ_MASK 0x0380 /* P0-7 */ +#define SWFREQ_SHIFT 7 +#define TARVID_MASK 0x001f #define MEMSTAT_CTG 0x111a0 #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 #define RSTDBYCTL 0x111b8 -#define RS1EN (1<<31) -#define RS2EN (1<<30) -#define RS3EN (1<<29) -#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ -#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ -#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ -#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ -#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ -#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ -#define RSX_STATUS_MASK (7<<20) -#define RSX_STATUS_ON (0<<20) -#define RSX_STATUS_RC1 (1<<20) -#define RSX_STATUS_RC1E (2<<20) -#define RSX_STATUS_RS1 (3<<20) -#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ -#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ -#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ -#define RSX_STATUS_RSVD2 (7<<20) -#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ -#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ -#define JRSC (1<<17) /* rsx coupled to cpu c-state */ -#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ -#define RS1CONTSAV_MASK (3<<14) -#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ -#define RS1CONTSAV_RSVD (1<<14) -#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ -#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ -#define NORMSLEXLAT_MASK (3<<12) -#define SLOW_RS123 (0<<12) -#define SLOW_RS23 (1<<12) -#define SLOW_RS3 (2<<12) -#define NORMAL_RS123 (3<<12) -#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ -#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ -#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ -#define RS_CSTATE_MASK (3<<4) -#define RS_CSTATE_C367_RS1 (0<<4) -#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) -#define RS_CSTATE_RSVD (2<<4) -#define RS_CSTATE_C367_RS2 (3<<4) -#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ -#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ +#define RS1EN (1<<31) +#define RS2EN (1<<30) +#define RS3EN (1<<29) +#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ +#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ +#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ +#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ +#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ +#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ +#define RSX_STATUS_MASK (7<<20) +#define RSX_STATUS_ON (0<<20) +#define RSX_STATUS_RC1 (1<<20) +#define RSX_STATUS_RC1E (2<<20) +#define RSX_STATUS_RS1 (3<<20) +#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ +#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ +#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ +#define RSX_STATUS_RSVD2 (7<<20) +#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ +#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ +#define JRSC (1<<17) /* rsx coupled to cpu c-state */ +#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ +#define RS1CONTSAV_MASK (3<<14) +#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ +#define RS1CONTSAV_RSVD (1<<14) +#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ +#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ +#define NORMSLEXLAT_MASK (3<<12) +#define SLOW_RS123 (0<<12) +#define SLOW_RS23 (1<<12) +#define SLOW_RS3 (2<<12) +#define NORMAL_RS123 (3<<12) +#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ +#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ +#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ +#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ +#define RS_CSTATE_MASK (3<<4) +#define RS_CSTATE_C367_RS1 (0<<4) +#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) +#define RS_CSTATE_RSVD (2<<4) +#define RS_CSTATE_C367_RS2 (3<<4) +#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ +#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ #define VIDCTL 0x111c0 #define VIDSTS 0x111c8 #define VIDSTART 0x111cc /* 8 bits */ #define MEMSTAT_ILK 0x111f8 -#define MEMSTAT_VID_MASK 0x7f00 -#define MEMSTAT_VID_SHIFT 8 -#define MEMSTAT_PSTATE_MASK 0x00f8 -#define MEMSTAT_PSTATE_SHIFT 3 -#define MEMSTAT_MON_ACTV (1<<2) -#define MEMSTAT_SRC_CTL_MASK 0x0003 -#define MEMSTAT_SRC_CTL_CORE 0 -#define MEMSTAT_SRC_CTL_TRB 1 -#define MEMSTAT_SRC_CTL_THM 2 -#define MEMSTAT_SRC_CTL_STDBY 3 +#define MEMSTAT_VID_MASK 0x7f00 +#define MEMSTAT_VID_SHIFT 8 +#define MEMSTAT_PSTATE_MASK 0x00f8 +#define MEMSTAT_PSTATE_SHIFT 3 +#define MEMSTAT_MON_ACTV (1<<2) +#define MEMSTAT_SRC_CTL_MASK 0x0003 +#define MEMSTAT_SRC_CTL_CORE 0 +#define MEMSTAT_SRC_CTL_TRB 1 +#define MEMSTAT_SRC_CTL_THM 2 +#define MEMSTAT_SRC_CTL_STDBY 3 #define RCPREVBSYTUPAVG 0x113b8 #define RCPREVBSYTDNAVG 0x113bc #define PMMISC 0x11214 -#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ +#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ #define SDEW 0x1124c #define CSIEW0 0x11250 #define CSIEW1 0x11254 @@ -1330,9 +1330,9 @@ #define RPPREVBSYTUPAVG 0x113b8 #define RPPREVBSYTDNAVG 0x113bc #define ECR 0x11600 -#define ECR_GPFE (1<<31) -#define ECR_IMONE (1<<30) -#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ +#define ECR_GPFE (1<<31) +#define ECR_IMONE (1<<30) +#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ #define OGW0 0x11608 #define OGW1 0x1160c #define EG0 0x11610 @@ -1346,7 +1346,7 @@ #define PXW 0x11664 #define PXWL 0x11680 #define LCFUSE02 0x116c0 -#define LCFUSE_HIV_MASK 0x000000ff +#define LCFUSE_HIV_MASK 0x000000ff #define CSIPLL0 0x12c10 #define DDRMPLL1 0X12c20 #define PEG_BAND_GAP_DATA 0x14d68 @@ -1362,7 +1362,7 @@ * Logical Context regs */ #define CCID 0x2180 -#define CCID_EN (1<<0) +#define CCID_EN (1<<0) /* * Overlay regs */ @@ -1415,42 +1415,42 @@
/* VGA port control */ #define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 +#define ADPA_DPMS_MASK (~(3<<10)) +#define ADPA_DPMS_ON (0<<10) +#define ADPA_DPMS_SUSPEND (1<<10) +#define ADPA_DPMS_STANDBY (2<<10) +#define ADPA_DPMS_OFF (3<<10)
/* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 -#define HDMIB_HOTPLUG_INT_EN (1 << 29) -#define DPB_HOTPLUG_INT_EN (1 << 29) -#define HDMIC_HOTPLUG_INT_EN (1 << 28) -#define DPC_HOTPLUG_INT_EN (1 << 28) -#define HDMID_HOTPLUG_INT_EN (1 << 27) -#define DPD_HOTPLUG_INT_EN (1 << 27) -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +#define HDMIB_HOTPLUG_INT_EN (1 << 29) +#define DPB_HOTPLUG_INT_EN (1 << 29) +#define HDMIC_HOTPLUG_INT_EN (1 << 28) +#define DPC_HOTPLUG_INT_EN (1 << 28) +#define HDMID_HOTPLUG_INT_EN (1 << 27) +#define DPD_HOTPLUG_INT_EN (1 << 27) +#define SDVOB_HOTPLUG_INT_EN (1 << 26) +#define SDVOC_HOTPLUG_INT_EN (1 << 25) +#define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_HOTPLUG_INT_EN (1 << 9) +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) /* must use period 64 on GM45 according to docs */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) @@ -1467,28 +1467,28 @@ #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
#define PORT_HOTPLUG_STAT 0x61114 -#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) -#define DPB_HOTPLUG_INT_STATUS (1 << 29) -#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) -#define DPC_HOTPLUG_INT_STATUS (1 << 28) -#define HDMID_HOTPLUG_INT_STATUS (1 << 27) -#define DPD_HOTPLUG_INT_STATUS (1 << 27) -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) +#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +#define DPB_HOTPLUG_INT_STATUS (1 << 29) +#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +#define DPC_HOTPLUG_INT_STATUS (1 << 28) +#define HDMID_HOTPLUG_INT_STATUS (1 << 27) +#define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_HOTPLUG_INT_STATUS (1 << 11) +#define TV_HOTPLUG_INT_STATUS (1 << 10) +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
/* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) /** * 915G/GM SDVO pixel multiplier. * @@ -1496,62 +1496,62 @@ * * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_ENCODING_SDVO (0x0 << 10) -#define SDVO_ENCODING_HDMI (0x2 << 10) +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) /** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) -#define SDVO_COLOR_RANGE_16_235 (1 << 8) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVO_AUDIO_ENABLE (1 << 6) +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) +#define SDVO_COLOR_RANGE_16_235 (1 << 8) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) /** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) /** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
/* DVO port control */ #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) +#define DVO_ENABLE (1 << 31) +#define DVO_PIPE_B_SELECT (1 << 30) +#define DVO_PIPE_STALL_UNUSED (0 << 28) +#define DVO_PIPE_STALL (1 << 28) +#define DVO_PIPE_STALL_TV (2 << 28) +#define DVO_PIPE_STALL_MASK (3 << 28) +#define DVO_USE_VGA_SYNC (1 << 15) +#define DVO_DATA_ORDER_I740 (0 << 14) +#define DVO_DATA_ORDER_FP (1 << 14) +#define DVO_VSYNC_DISABLE (1 << 11) +#define DVO_HSYNC_DISABLE (1 << 10) +#define DVO_VSYNC_TRISTATE (1 << 9) +#define DVO_HSYNC_TRISTATE (1 << 8) +#define DVO_BORDER_ENABLE (1 << 7) +#define DVO_DATA_ORDER_GBRG (1 << 6) +#define DVO_DATA_ORDER_RGGB (0 << 6) +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define DVO_BLANK_ACTIVE_HIGH (1 << 2) +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ +#define DVO_PRESERVE_MASK (0x7<<24) #define DVOA_SRCDIM 0x61124 #define DVOB_SRCDIM 0x61144 #define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */ #define LVDS 0x61180 @@ -1559,70 +1559,70 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1 << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -#define LVDS_PIPE_MASK (1 << 30) -#define LVDS_PIPE(pipe) ((pipe) << 30) +#define LVDS_PIPEB_SELECT (1 << 30) +#define LVDS_PIPE_MASK (1 << 30) +#define LVDS_PIPE(pipe) ((pipe) << 30) /* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) +#define LVDS_ENABLE_DITHER (1 << 25) /* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) +#define LVDS_VSYNC_POLARITY (1 << 21) +#define LVDS_HSYNC_POLARITY (1 << 20)
/* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_BORDER_ENABLE (1 << 15) /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) +#define LVDS_A3_POWER_MASK (3 << 6) +#define LVDS_A3_POWER_DOWN (0 << 6) +#define LVDS_A3_POWER_UP (3 << 6) /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) +#define LVDS_CLKB_POWER_MASK (3 << 4) +#define LVDS_CLKB_POWER_DOWN (0 << 4) +#define LVDS_CLKB_POWER_UP (3 << 4) /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) +#define LVDS_B0B3_POWER_MASK (3 << 2) +#define LVDS_B0B3_POWER_DOWN (0 << 2) +#define LVDS_B0B3_POWER_UP (3 << 2)
/* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT_B (1 << 29) -#define VIDEO_DIP_PORT_C (2 << 29) -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT_B (1 << 29) +#define VIDEO_DIP_PORT_C (2 << 29) +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
/* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1 << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1630,51 +1630,51 @@ * - pipe enabled * - LVDS/DVOB/DVOC on */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_POWER_UP (1 << 28) -#define PP_SEQUENCE_POWER_DOWN (2 << 28) -#define PP_SEQUENCE_MASK (3 << 28) -#define PP_SEQUENCE_SHIFT 28 -#define PP_CYCLE_DELAY_ACTIVE (1 << 27) -#define PP_SEQUENCE_STATE_MASK 0x0000000f -#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) -#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) -#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) -#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) -#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) -#define PP_SEQUENCE_STATE_RESET (0xf << 0) +#define PP_READY (1 << 30) +#define PP_SEQUENCE_NONE (0 << 28) +#define PP_SEQUENCE_POWER_UP (1 << 28) +#define PP_SEQUENCE_POWER_DOWN (2 << 28) +#define PP_SEQUENCE_MASK (3 << 28) +#define PP_SEQUENCE_SHIFT 28 +#define PP_CYCLE_DELAY_ACTIVE (1 << 27) +#define PP_SEQUENCE_STATE_MASK 0x0000000f +#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) +#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) +#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) +#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) +#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) +#define PP_SEQUENCE_STATE_RESET (0xf << 0) #define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) +#define POWER_TARGET_ON (1 << 0) #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210
/* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_FILTER_FUZZY (0 << 24) -#define PFIT_SCALING_AUTO (0 << 26) -#define PFIT_SCALING_PROGRAMMED (1 << 26) -#define PFIT_SCALING_PILLAR (2 << 26) -#define PFIT_SCALING_LETTER (3 << 26) +#define PFIT_ENABLE (1 << 31) +#define PFIT_PIPE_MASK (3 << 29) +#define PFIT_PIPE_SHIFT 29 +#define VERT_INTERP_DISABLE (0 << 10) +#define VERT_INTERP_BILINEAR (1 << 10) +#define VERT_INTERP_MASK (3 << 10) +#define VERT_AUTO_SCALE (1 << 9) +#define HORIZ_INTERP_DISABLE (0 << 6) +#define HORIZ_INTERP_BILINEAR (1 << 6) +#define HORIZ_INTERP_MASK (3 << 6) +#define HORIZ_AUTO_SCALE (1 << 5) +#define PANEL_8TO6_DITHER_ENABLE (1 << 3) +#define PFIT_FILTER_FUZZY (0 << 24) +#define PFIT_SCALING_AUTO (0 << 26) +#define PFIT_SCALING_PROGRAMMED (1 << 26) +#define PFIT_SCALING_PILLAR (2 << 26) +#define PFIT_SCALING_LETTER (3 << 26) #define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 +#define PFIT_VERT_SCALE_MASK 0xfff00000 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 /* Pre-965 */ #define PFIT_VERT_SCALE_SHIFT 20 #define PFIT_VERT_SCALE_MASK 0xfff00000 @@ -1690,17 +1690,17 @@
/* Backlight control */ #define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) +#define BLM_COMBINATION_MODE (1 << 30) /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. @@ -1708,8 +1708,8 @@ * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
#define BLC_HIST_CTL 0x61260
@@ -2199,82 +2199,82 @@ #define DP_C 0x64200 #define DP_D 0x64300
-#define DP_PORT_EN (1 << 31) -#define DP_PIPEB_SELECT (1 << 30) -#define DP_PIPE_MASK (1 << 30) +#define DP_PORT_EN (1 << 31) +#define DP_PIPEB_SELECT (1 << 30) +#define DP_PIPE_MASK (1 << 30)
/* Link training mode - select a suitable mode for each stage */ -#define DP_LINK_TRAIN_PAT_1 (0 << 28) -#define DP_LINK_TRAIN_PAT_2 (1 << 28) -#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) -#define DP_LINK_TRAIN_OFF (3 << 28) -#define DP_LINK_TRAIN_MASK (3 << 28) -#define DP_LINK_TRAIN_SHIFT 28 +#define DP_LINK_TRAIN_PAT_1 (0 << 28) +#define DP_LINK_TRAIN_PAT_2 (1 << 28) +#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) +#define DP_LINK_TRAIN_OFF (3 << 28) +#define DP_LINK_TRAIN_MASK (3 << 28) +#define DP_LINK_TRAIN_SHIFT 28
/* CPT Link training mode */ -#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) -#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) -#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) -#define DP_LINK_TRAIN_OFF_CPT (3 << 8) -#define DP_LINK_TRAIN_MASK_CPT (7 << 8) -#define DP_LINK_TRAIN_SHIFT_CPT 8 +#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) +#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) +#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) +#define DP_LINK_TRAIN_OFF_CPT (3 << 8) +#define DP_LINK_TRAIN_MASK_CPT (7 << 8) +#define DP_LINK_TRAIN_SHIFT_CPT 8
/* Signal voltages. These are mostly controlled by the other end */ -#define DP_VOLTAGE_0_4 (0 << 25) -#define DP_VOLTAGE_0_6 (1 << 25) -#define DP_VOLTAGE_0_8 (2 << 25) -#define DP_VOLTAGE_1_2 (3 << 25) -#define DP_VOLTAGE_MASK (7 << 25) -#define DP_VOLTAGE_SHIFT 25 +#define DP_VOLTAGE_0_4 (0 << 25) +#define DP_VOLTAGE_0_6 (1 << 25) +#define DP_VOLTAGE_0_8 (2 << 25) +#define DP_VOLTAGE_1_2 (3 << 25) +#define DP_VOLTAGE_MASK (7 << 25) +#define DP_VOLTAGE_SHIFT 25
/* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ -#define DP_PRE_EMPHASIS_0 (0 << 22) -#define DP_PRE_EMPHASIS_3_5 (1 << 22) -#define DP_PRE_EMPHASIS_6 (2 << 22) -#define DP_PRE_EMPHASIS_9_5 (3 << 22) -#define DP_PRE_EMPHASIS_MASK (7 << 22) -#define DP_PRE_EMPHASIS_SHIFT 22 +#define DP_PRE_EMPHASIS_0 (0 << 22) +#define DP_PRE_EMPHASIS_3_5 (1 << 22) +#define DP_PRE_EMPHASIS_6 (2 << 22) +#define DP_PRE_EMPHASIS_9_5 (3 << 22) +#define DP_PRE_EMPHASIS_MASK (7 << 22) +#define DP_PRE_EMPHASIS_SHIFT 22
/* How many wires to use. I guess 3 was too hard */ -#define DP_PORT_WIDTH_1 (0 << 19) -#define DP_PORT_WIDTH_2 (1 << 19) -#define DP_PORT_WIDTH_4 (3 << 19) -#define DP_PORT_WIDTH_MASK (7 << 19) +#define DP_PORT_WIDTH_1 (0 << 19) +#define DP_PORT_WIDTH_2 (1 << 19) +#define DP_PORT_WIDTH_4 (3 << 19) +#define DP_PORT_WIDTH_MASK (7 << 19)
/* Mystic DPCD version 1.1 special mode */ -#define DP_ENHANCED_FRAMING (1 << 18) +#define DP_ENHANCED_FRAMING (1 << 18)
/* eDP */ -#define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) -#define DP_PLL_FREQ_MASK (3 << 16) +#define DP_PLL_FREQ_270MHZ (0 << 16) +#define DP_PLL_FREQ_160MHZ (1 << 16) +#define DP_PLL_FREQ_MASK (3 << 16)
/** locked once port is enabled */ -#define DP_PORT_REVERSAL (1 << 15) +#define DP_PORT_REVERSAL (1 << 15)
/* eDP */ -#define DP_PLL_ENABLE (1 << 14) +#define DP_PLL_ENABLE (1 << 14)
/** sends the clock on lane 15 of the PEG for debug */ -#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) +#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
-#define DP_SCRAMBLING_DISABLE (1 << 12) -#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) +#define DP_SCRAMBLING_DISABLE (1 << 12) +#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
/** limit RGB values to avoid confusing TVs */ -#define DP_COLOR_RANGE_16_235 (1 << 8) +#define DP_COLOR_RANGE_16_235 (1 << 8)
/** Turn on the audio link */ -#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) +#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
/** vs and hs sync polarity */ -#define DP_SYNC_VS_HIGH (1 << 4) -#define DP_SYNC_HS_HIGH (1 << 3) +#define DP_SYNC_VS_HIGH (1 << 4) +#define DP_SYNC_HS_HIGH (1 << 3)
/** A fantasy */ -#define DP_DETECTED (1 << 2) +#define DP_DETECTED (1 << 2)
/** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported @@ -2309,27 +2309,27 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_DONE (1 << 30) +#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) +#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) +#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) +#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) +#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) +#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) +#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) +#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) +#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
/* * Computing GMCH M and N values for the Display Port link @@ -2348,14 +2348,14 @@ #define _PIPEB_GMCH_DATA_M 0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
-#define PIPE_GMCH_DATA_M_MASK (0xffffff) +#define PIPE_GMCH_DATA_M_MASK (0xffffff)
#define _PIPEA_GMCH_DATA_N 0x70054 #define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) +#define PIPE_GMCH_DATA_N_MASK (0xffffff)
/* * Computing Link M and N values for the Display Port link @@ -2370,11 +2370,11 @@
#define _PIPEA_DP_LINK_M 0x70060 #define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) +#define PIPEA_DP_LINK_M_MASK (0xffffff)
#define _PIPEA_DP_LINK_N 0x70064 #define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) +#define PIPEA_DP_LINK_N_MASK (0xffffff)
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) @@ -2385,81 +2385,81 @@
/* Pipe A */ #define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff +#define DSL_LINEMASK 0x00000fff #define _PIPEACONF 0x70008 -#define PIPECONF_ENABLE (1<<31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1<<25) -#define PIPECONF_PALETTE 0 -#define PIPECONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_ENABLE (1<<31) +#define PIPECONF_DISABLE 0 +#define PIPECONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) +#define PIPECONF_SINGLE_WIDE 0 +#define PIPECONF_PIPE_UNLOCKED 0 +#define PIPECONF_PIPE_LOCKED (1<<25) +#define PIPECONF_PALETTE 0 +#define PIPECONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_INTERLACE_MASK (7 << 21) /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ /* Ironlake and later have a complete new set of values for interlaced. PFIT * means panel fitter required, PF means progressive fetch, DBL means power * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_CXSR_DOWNCLOCK (1<<16) -#define PIPECONF_BPP_MASK (0x000000e0) -#define PIPECONF_BPP_8 (0<<5) -#define PIPECONF_BPP_10 (1<<5) -#define PIPECONF_BPP_6 (2<<5) -#define PIPECONF_BPP_12 (3<<5) -#define PIPECONF_DITHER_EN (1<<4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0<<2) -#define PIPECONF_DITHER_TYPE_ST1 (1<<2) -#define PIPECONF_DITHER_TYPE_ST2 (2<<2) -#define PIPECONF_DITHER_TYPE_TEMP (3<<2) +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) +#define PIPECONF_INTERLACED_ILK (3 << 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_BPP_MASK (0x000000e0) +#define PIPECONF_BPP_8 (0<<5) +#define PIPECONF_BPP_10 (1<<5) +#define PIPECONF_BPP_6 (2<<5) +#define PIPECONF_BPP_12 (3<<5) +#define PIPECONF_DITHER_EN (1<<4) +#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) +#define PIPECONF_DITHER_TYPE_SP (0<<2) +#define PIPECONF_DITHER_TYPE_ST1 (1<<2) +#define PIPECONF_DITHER_TYPE_ST2 (2<<2) +#define PIPECONF_DITHER_TYPE_TEMP (3<<2) #define _PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ -#define PIPE_8BPC (0 << 5) -#define PIPE_10BPC (1 << 5) -#define PIPE_6BPC (2 << 5) -#define PIPE_12BPC (3 << 5) +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) +#define PIPE_CRC_ERROR_ENABLE (1UL<<29) +#define PIPE_CRC_DONE_ENABLE (1UL<<28) +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) +#define PIPE_DPST_EVENT_ENABLE (1UL<<23) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) +#define PIPE_DPST_EVENT_STATUS (1UL<<7) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) @@ -2469,33 +2469,33 @@ #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -#define DSPARB_BEND_SHIFT 9 /* on 855 */ -#define DSPARB_AEND_SHIFT 0 +#define DSPARB_CSTART_MASK (0x7f << 7) +#define DSPARB_CSTART_SHIFT 7 +#define DSPARB_BSTART_MASK (0x7f) +#define DSPARB_BSTART_SHIFT 0 +#define DSPARB_BEND_SHIFT 9 /* on 855 */ +#define DSPARB_AEND_SHIFT 0
#define DSPFW1 0x70034 -#define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) -#define DSPFW_CURSORB_SHIFT 16 -#define DSPFW_CURSORB_MASK (0x3f<<16) -#define DSPFW_PLANEB_SHIFT 8 -#define DSPFW_PLANEB_MASK (0x7f<<8) -#define DSPFW_PLANEA_MASK (0x7f) +#define DSPFW_SR_SHIFT 23 +#define DSPFW_SR_MASK (0x1ff<<23) +#define DSPFW_CURSORB_SHIFT 16 +#define DSPFW_CURSORB_MASK (0x3f<<16) +#define DSPFW_PLANEB_SHIFT 8 +#define DSPFW_PLANEB_MASK (0x7f<<8) +#define DSPFW_PLANEA_MASK (0x7f) #define DSPFW2 0x70038 -#define DSPFW_CURSORA_MASK 0x00003f00 -#define DSPFW_CURSORA_SHIFT 8 -#define DSPFW_PLANEC_MASK (0x7f) +#define DSPFW_CURSORA_MASK 0x00003f00 +#define DSPFW_CURSORA_SHIFT 8 +#define DSPFW_PLANEC_MASK (0x7f) #define DSPFW3 0x7003c -#define DSPFW_HPLL_SR_EN (1<<31) -#define DSPFW_CURSOR_SR_SHIFT 24 -#define PINEVIEW_SELF_REFRESH_EN (1<<30) -#define DSPFW_CURSOR_SR_MASK (0x3f<<24) -#define DSPFW_HPLL_CURSOR_SHIFT 16 -#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) -#define DSPFW_HPLL_SR_MASK (0x1ff) +#define DSPFW_HPLL_SR_EN (1<<31) +#define DSPFW_CURSOR_SR_SHIFT 24 +#define PINEVIEW_SELF_REFRESH_EN (1<<30) +#define DSPFW_CURSOR_SR_MASK (0x3f<<24) +#define DSPFW_HPLL_CURSOR_SHIFT 16 +#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) +#define DSPFW_HPLL_SR_MASK (0x1ff)
/* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 @@ -2623,22 +2623,22 @@ * * do { * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; + * PIPE_FRAME_HIGH_SHIFT; * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); + * PIPE_FRAME_LOW_SHIFT); * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); + * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; */ -#define _PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define _PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 +#define _PIPEAFRAMEHIGH 0x70040 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 +#define _PIPEAFRAMEPIXEL 0x70044 +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_GM45 0x70040 #define _PIPEA_FLIPCOUNT_GM45 0x70044 @@ -2647,31 +2647,31 @@ /* Cursor A & B regs */ #define _CURACNTR 0x70080 /* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE 0x80000000 -#define CURSOR_GAMMA_ENABLE 0x40000000 -#define CURSOR_STRIDE_MASK 0x30000000 -#define CURSOR_FORMAT_SHIFT 24 -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) +#define CURSOR_ENABLE 0x80000000 +#define CURSOR_GAMMA_ENABLE 0x40000000 +#define CURSOR_STRIDE_MASK 0x30000000 +#define CURSOR_FORMAT_SHIFT 24 +#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) /* New style CUR*CNTR flags */ -#define CURSOR_MODE 0x27 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_PIPE_SELECT (1 << 28) -#define MCURSOR_PIPE_A 0x00 -#define MCURSOR_PIPE_B (1 << 28) -#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define CURSOR_MODE 0x27 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) +#define MCURSOR_PIPE_SELECT (1 << 28) +#define MCURSOR_PIPE_A 0x00 +#define MCURSOR_PIPE_B (1 << 28) +#define MCURSOR_GAMMA_ENABLE (1 << 26) #define _CURABASE 0x70084 #define _CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 #define CURSIZE 0x700a0 #define _CURBCNTR 0x700c0 #define _CURBBASE 0x700c4 @@ -2690,32 +2690,32 @@ #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */ -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_SHIFT 24 -#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ -#define DISPPLANE_TILED (1<<10) +#define _DSPACNTR 0x70180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_SHIFT 24 +#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ +#define DISPPLANE_TILED (1<<10) #define _DSPAADDR 0x70184 #define _DSPASTRIDE 0x70188 #define _DSPAPOS 0x7018C /* reserved */ @@ -2758,10 +2758,10 @@
/* Display B control */ #define _DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define _DSPBADDR 0x71184 #define _DSPBSTRIDE 0x71188 #define _DSPBPOS 0x7118C @@ -2771,23 +2771,23 @@
/* Sprite A control */ #define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) -#define DVS_GAMMA_ENABLE (1<<30) -#define DVS_PIXFORMAT_MASK (3<<25) -#define DVS_FORMAT_YUV422 (0<<25) -#define DVS_FORMAT_RGBX101010 (1<<25) -#define DVS_FORMAT_RGBX888 (2<<25) -#define DVS_FORMAT_RGBX161616 (3<<25) -#define DVS_SOURCE_KEY (1<<22) -#define DVS_RGB_ORDER_XBGR (1<<20) -#define DVS_YUV_BYTE_ORDER_MASK (3<<16) -#define DVS_YUV_ORDER_YUYV (0<<16) -#define DVS_YUV_ORDER_UYVY (1<<16) -#define DVS_YUV_ORDER_YVYU (2<<16) -#define DVS_YUV_ORDER_VYUY (3<<16) -#define DVS_DEST_KEY (1<<2) -#define DVS_TRICKLE_FEED_DISABLE (1<<14) -#define DVS_TILED (1<<10) +#define DVS_ENABLE (1<<31) +#define DVS_GAMMA_ENABLE (1<<30) +#define DVS_PIXFORMAT_MASK (3<<25) +#define DVS_FORMAT_YUV422 (0<<25) +#define DVS_FORMAT_RGBX101010 (1<<25) +#define DVS_FORMAT_RGBX888 (2<<25) +#define DVS_FORMAT_RGBX161616 (3<<25) +#define DVS_SOURCE_KEY (1<<22) +#define DVS_RGB_ORDER_XBGR (1<<20) +#define DVS_YUV_BYTE_ORDER_MASK (3<<16) +#define DVS_YUV_ORDER_YUYV (0<<16) +#define DVS_YUV_ORDER_UYVY (1<<16) +#define DVS_YUV_ORDER_YVYU (2<<16) +#define DVS_YUV_ORDER_VYUY (3<<16) +#define DVS_DEST_KEY (1<<2) +#define DVS_TRICKLE_FEED_DISABLE (1<<14) +#define DVS_TILED (1<<10) #define _DVSALINOFF 0x72184 #define _DVSASTRIDE 0x72188 #define _DVSAPOS 0x7218c @@ -2799,13 +2799,13 @@ #define _DVSATILEOFF 0x721a4 #define _DVSASURFLIVE 0x721ac #define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE (1<<31) -#define DVS_FILTER_MASK (3<<29) -#define DVS_FILTER_MEDIUM (0<<29) -#define DVS_FILTER_ENHANCING (1<<29) -#define DVS_FILTER_SOFTENING (2<<29) -#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) +#define DVS_SCALE_ENABLE (1<<31) +#define DVS_FILTER_MASK (3<<29) +#define DVS_FILTER_MEDIUM (0<<29) +#define DVS_FILTER_ENHANCING (1<<29) +#define DVS_FILTER_SOFTENING (2<<29) +#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) #define _DVSAGAMC 0x72300
#define _DVSBCNTR 0x73180 @@ -2835,29 +2835,29 @@ #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE (1<<31) -#define SPRITE_GAMMA_ENABLE (1<<30) -#define SPRITE_PIXFORMAT_MASK (7<<25) -#define SPRITE_FORMAT_YUV422 (0<<25) -#define SPRITE_FORMAT_RGBX101010 (1<<25) -#define SPRITE_FORMAT_RGBX888 (2<<25) -#define SPRITE_FORMAT_RGBX161616 (3<<25) -#define SPRITE_FORMAT_YUV444 (4<<25) -#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ -#define SPRITE_CSC_ENABLE (1<<24) -#define SPRITE_SOURCE_KEY (1<<22) -#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) -#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ -#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) -#define SPRITE_YUV_ORDER_YUYV (0<<16) -#define SPRITE_YUV_ORDER_UYVY (1<<16) -#define SPRITE_YUV_ORDER_YVYU (2<<16) -#define SPRITE_YUV_ORDER_VYUY (3<<16) -#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) -#define SPRITE_INT_GAMMA_ENABLE (1<<13) -#define SPRITE_TILED (1<<10) -#define SPRITE_DEST_KEY (1<<2) +#define SPRITE_ENABLE (1<<31) +#define SPRITE_GAMMA_ENABLE (1<<30) +#define SPRITE_PIXFORMAT_MASK (7<<25) +#define SPRITE_FORMAT_YUV422 (0<<25) +#define SPRITE_FORMAT_RGBX101010 (1<<25) +#define SPRITE_FORMAT_RGBX888 (2<<25) +#define SPRITE_FORMAT_RGBX161616 (3<<25) +#define SPRITE_FORMAT_YUV444 (4<<25) +#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ +#define SPRITE_CSC_ENABLE (1<<24) +#define SPRITE_SOURCE_KEY (1<<22) +#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) +#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ +#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) +#define SPRITE_YUV_ORDER_YUYV (0<<16) +#define SPRITE_YUV_ORDER_UYVY (1<<16) +#define SPRITE_YUV_ORDER_YVYU (2<<16) +#define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) +#define SPRITE_INT_GAMMA_ENABLE (1<<13) +#define SPRITE_TILED (1<<10) +#define SPRITE_DEST_KEY (1<<2) #define _SPRA_LINOFF 0x70284 #define _SPRA_STRIDE 0x70288 #define _SPRA_POS 0x7028c @@ -2868,13 +2868,13 @@ #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 #define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE (1<<31) -#define SPRITE_FILTER_MASK (3<<29) -#define SPRITE_FILTER_MEDIUM (0<<29) -#define SPRITE_FILTER_ENHANCING (1<<29) -#define SPRITE_FILTER_SOFTENING (2<<29) -#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) +#define SPRITE_SCALE_ENABLE (1<<31) +#define SPRITE_FILTER_MASK (3<<29) +#define SPRITE_FILTER_MEDIUM (0<<29) +#define SPRITE_FILTER_ENHANCING (1<<29) +#define SPRITE_FILTER_SOFTENING (2<<29) +#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) #define _SPRA_GAMC 0x70400
#define _SPRB_CTL 0x71280 @@ -2913,28 +2913,28 @@
#define CPU_VGACNTRL 0x41000
-#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) -#define DIGITAL_PORTA_NO_DETECT (0 << 0) -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) +#define DIGITAL_PORTA_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
/* refresh rate hardware control */ -#define RR_HW_CTL 0x45300 -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 +#define RR_HW_CTL 0x45300 +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
#define FDI_PLL_BIOS_0 0x46000 #define FDI_PLL_FB_CLOCK_MASK 0xff #define FDI_PLL_BIOS_1 0x46004 #define FDI_PLL_BIOS_2 0x46008 -#define DISPLAY_PORT_PLL_BIOS_0 0x4600c -#define DISPLAY_PORT_PLL_BIOS_1 0x46010 -#define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define DISPLAY_PORT_PLL_BIOS_0 0x4600c +#define DISPLAY_PORT_PLL_BIOS_1 0x46010 +#define DISPLAY_PORT_PLL_BIOS_2 0x46014
#define PCH_DSPCLK_GATE_D 0x42020 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) @@ -2949,47 +2949,47 @@ #define PCH_3DCGDIS1 0x46024 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define FDI_PLL_FREQ_CTL 0x46030 -#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) -#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 +#define FDI_PLL_FREQ_CTL 0x46030 +#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) +#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 -#define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 0x60034 -#define PIPE_DATA_N1_OFFSET 0 +#define _PIPEA_DATA_M1 0x60030 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK 0x7e000000 +#define PIPE_DATA_M1_OFFSET 0 +#define _PIPEA_DATA_N1 0x60034 +#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 0x60038 -#define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 0x6003c -#define PIPE_DATA_N2_OFFSET 0 +#define _PIPEA_DATA_M2 0x60038 +#define PIPE_DATA_M2_OFFSET 0 +#define _PIPEA_DATA_N2 0x6003c +#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 0x60040 -#define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 0x60044 -#define PIPE_LINK_N1_OFFSET 0 +#define _PIPEA_LINK_M1 0x60040 +#define PIPE_LINK_M1_OFFSET 0 +#define _PIPEA_LINK_N1 0x60044 +#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 0x60048 -#define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 0x6004c -#define PIPE_LINK_N2_OFFSET 0 +#define _PIPEA_LINK_M2 0x60048 +#define PIPE_LINK_M2_OFFSET 0 +#define _PIPEA_LINK_N2 0x6004c +#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 0x61030 -#define _PIPEB_DATA_N1 0x61034 +#define _PIPEB_DATA_M1 0x61030 +#define _PIPEB_DATA_N1 0x61034
-#define _PIPEB_DATA_M2 0x61038 -#define _PIPEB_DATA_N2 0x6103c +#define _PIPEB_DATA_M2 0x61038 +#define _PIPEB_DATA_N2 0x6103c
-#define _PIPEB_LINK_M1 0x61040 -#define _PIPEB_LINK_N1 0x61044 +#define _PIPEB_LINK_M1 0x61040 +#define _PIPEB_LINK_N1 0x61044
-#define _PIPEB_LINK_M2 0x61048 -#define _PIPEB_LINK_N2 0x6104c +#define _PIPEB_LINK_M2 0x61048 +#define _PIPEB_LINK_N2 0x6104c
#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) @@ -3002,9 +3002,9 @@
/* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_ENABLE (1<<31) +#define _PFA_CTL_1 0x68080 +#define _PFB_CTL_1 0x68880 +#define PF_ENABLE (1<<31) #define PF_FILTER_MASK (3<<23) #define PF_FILTER_PROGRAMMED (0<<23) #define PF_FILTER_MED_3x3 (1<<23) @@ -3026,35 +3026,35 @@ #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
/* legacy palette */ -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) -#define DE_SPRITEB_FLIP_DONE (1 << 29) -#define DE_SPRITEA_FLIP_DONE (1 << 28) -#define DE_PLANEB_FLIP_DONE (1 << 27) -#define DE_PLANEA_FLIP_DONE (1 << 26) -#define DE_PCU_EVENT (1 << 25) -#define DE_GTT_FAULT (1 << 24) -#define DE_POISON (1 << 23) -#define DE_PERFORM_COUNTER (1 << 22) -#define DE_PCH_EVENT (1 << 21) -#define DE_AUX_CHANNEL_A (1 << 20) -#define DE_DP_A_HOTPLUG (1 << 19) -#define DE_GSE (1 << 18) -#define DE_PIPEB_VBLANK (1 << 15) -#define DE_PIPEB_EVEN_FIELD (1 << 14) -#define DE_PIPEB_ODD_FIELD (1 << 13) -#define DE_PIPEB_LINE_COMPARE (1 << 12) -#define DE_PIPEB_VSYNC (1 << 11) +#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_SPRITEB_FLIP_DONE (1 << 29) +#define DE_SPRITEA_FLIP_DONE (1 << 28) +#define DE_PLANEB_FLIP_DONE (1 << 27) +#define DE_PLANEA_FLIP_DONE (1 << 26) +#define DE_PCU_EVENT (1 << 25) +#define DE_GTT_FAULT (1 << 24) +#define DE_POISON (1 << 23) +#define DE_PERFORM_COUNTER (1 << 22) +#define DE_PCH_EVENT (1 << 21) +#define DE_AUX_CHANNEL_A (1 << 20) +#define DE_DP_A_HOTPLUG (1 << 19) +#define DE_GSE (1 << 18) +#define DE_PIPEB_VBLANK (1 << 15) +#define DE_PIPEB_EVEN_FIELD (1 << 14) +#define DE_PIPEB_ODD_FIELD (1 << 13) +#define DE_PIPEB_LINE_COMPARE (1 << 12) +#define DE_PIPEB_VSYNC (1 << 11) #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) -#define DE_PIPEA_VBLANK (1 << 7) -#define DE_PIPEA_EVEN_FIELD (1 << 6) -#define DE_PIPEA_ODD_FIELD (1 << 5) -#define DE_PIPEA_LINE_COMPARE (1 << 4) -#define DE_PIPEA_VSYNC (1 << 3) +#define DE_PIPEA_VBLANK (1 << 7) +#define DE_PIPEA_EVEN_FIELD (1 << 6) +#define DE_PIPEA_ODD_FIELD (1 << 5) +#define DE_PIPEA_LINE_COMPARE (1 << 4) +#define DE_PIPEA_VSYNC (1 << 3) #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
/* More Ivybridge lolz */ @@ -3070,23 +3070,23 @@ #define DE_PIPEB_VBLANK_IVB (1<<5) #define DE_PIPEA_VBLANK_IVB (1<<0)
-#define DEISR 0x44000 -#define DEIMR 0x44004 -#define DEIIR 0x44008 -#define DEIER 0x4400c +#define DEISR 0x44000 +#define DEIMR 0x44004 +#define DEIIR 0x44008 +#define DEIER 0x4400c
/* GT interrupt */ #define GT_PIPE_NOTIFY (1 << 4) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) -#define GT_BSD_USER_INTERRUPT (1 << 5) +#define GT_SYNC_STATUS (1 << 2) +#define GT_USER_INTERRUPT (1 << 0) +#define GT_BSD_USER_INTERRUPT (1 << 5) #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) #define GT_BLT_USER_INTERRUPT (1 << 22)
-#define GTISR 0x44010 -#define GTIMR 0x44014 -#define GTIIR 0x44018 -#define GTIER 0x4401c +#define GTISR 0x44010 +#define GTIMR 0x44014 +#define GTIIR 0x44018 +#define GTIER 0x4401c
#define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ @@ -3106,9 +3106,9 @@ #define ILK_DPFD_CLK_GATE (1<<7)
/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ -#define ILK_CLK_FBC (1<<7) -#define ILK_DPFC_DIS1 (1<<8) -#define ILK_DPFC_DIS2 (1<<9) +#define ILK_CLK_FBC (1<<7) +#define ILK_DPFC_DIS1 (1<<8) +#define ILK_DPFC_DIS2 (1<<9)
#define IVB_CHICKEN3 0x4200c # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) @@ -3157,11 +3157,11 @@ #define SDE_AUXB (1 << 13) #define SDE_AUX_MASK (7 << 13) /* 12 reserved */ -#define SDE_CRT_HOTPLUG (1 << 11) -#define SDE_PORTD_HOTPLUG (1 << 10) -#define SDE_PORTC_HOTPLUG (1 << 9) -#define SDE_PORTB_HOTPLUG (1 << 8) -#define SDE_SDVOB_HOTPLUG (1 << 6) +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) #define SDE_HOTPLUG_MASK (0xf << 8) #define SDE_TRANSB_CRC_DONE (1 << 5) #define SDE_TRANSB_CRC_ERR (1 << 4) @@ -3186,41 +3186,41 @@ #define SDEIER 0xc400c
/* digital port hotplug */ -#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ -#define PORTD_HOTPLUG_ENABLE (1 << 20) -#define PORTD_PULSE_DURATION_2ms (0) -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) -#define PORTD_PULSE_DURATION_6ms (2 << 18) -#define PORTD_PULSE_DURATION_100ms (3 << 18) +#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0) +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) +#define PORTD_PULSE_DURATION_6ms (2 << 18) +#define PORTD_PULSE_DURATION_100ms (3 << 18) #define PORTD_PULSE_DURATION_MASK (3 << 18) -#define PORTD_HOTPLUG_NO_DETECT (0) -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) -#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) -#define PORTC_HOTPLUG_ENABLE (1 << 12) -#define PORTC_PULSE_DURATION_2ms (0) -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) -#define PORTC_PULSE_DURATION_6ms (2 << 10) -#define PORTC_PULSE_DURATION_100ms (3 << 10) +#define PORTD_HOTPLUG_NO_DETECT (0) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define PORTC_PULSE_DURATION_2ms (0) +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) +#define PORTC_PULSE_DURATION_6ms (2 << 10) +#define PORTC_PULSE_DURATION_100ms (3 << 10) #define PORTC_PULSE_DURATION_MASK (3 << 10) -#define PORTC_HOTPLUG_NO_DETECT (0) -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) -#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) -#define PORTB_HOTPLUG_ENABLE (1 << 4) -#define PORTB_PULSE_DURATION_2ms (0) -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) -#define PORTB_PULSE_DURATION_6ms (2 << 2) -#define PORTB_PULSE_DURATION_100ms (3 << 2) +#define PORTC_HOTPLUG_NO_DETECT (0) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define PORTB_PULSE_DURATION_2ms (0) +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) +#define PORTB_PULSE_DURATION_6ms (2 << 2) +#define PORTB_PULSE_DURATION_100ms (3 << 2) #define PORTB_PULSE_DURATION_MASK (3 << 2) -#define PORTB_HOTPLUG_NO_DETECT (0) -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) -#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) +#define PORTB_HOTPLUG_NO_DETECT (0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
-#define PCH_GPIOA 0xc5010 -#define PCH_GPIOB 0xc5014 -#define PCH_GPIOC 0xc5018 -#define PCH_GPIOD 0xc501c -#define PCH_GPIOE 0xc5020 -#define PCH_GPIOF 0xc5024 +#define PCH_GPIOA 0xc5010 +#define PCH_GPIOB 0xc5014 +#define PCH_GPIOC 0xc5018 +#define PCH_GPIOD 0xc501c +#define PCH_GPIOE 0xc5020 +#define PCH_GPIOF 0xc5024
#define PCH_GMBUS0 0xc5100 #define PCH_GMBUS1 0xc5104 @@ -3229,54 +3229,54 @@ #define PCH_GMBUS4 0xc5110 #define PCH_GMBUS5 0xc5120
-#define _PCH_DPLL_A 0xc6014 -#define _PCH_DPLL_B 0xc6018 +#define _PCH_DPLL_A 0xc6014 +#define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-#define _PCH_FPA0 0xc6040 +#define _PCH_FPA0 0xc6040 #define FP_CB_TUNE (0x3<<22) -#define _PCH_FPA1 0xc6044 -#define _PCH_FPB0 0xc6048 -#define _PCH_FPB1 0xc604c +#define _PCH_FPA1 0xc6044 +#define _PCH_FPB0 0xc6048 +#define _PCH_FPB1 0xc604c #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
-#define PCH_DPLL_TEST 0xc606c +#define PCH_DPLL_TEST 0xc606c
-#define PCH_DREF_CONTROL 0xC6200 -#define DREF_CONTROL_MASK 0x7fc3 -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) +#define PCH_DREF_CONTROL 0xC6200 +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) -#define DREF_SSC_SOURCE_DISABLE (0<<11) -#define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_DISABLE (0<<11) +#define DREF_SSC_SOURCE_ENABLE (2<<11) #define DREF_SSC_SOURCE_MASK (3<<11) -#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) #define DREF_NONSPREAD_CK505_ENABLE (1<<9) -#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) #define DREF_NONSPREAD_SOURCE_MASK (3<<9) -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) -#define DREF_SSC4_DOWNSPREAD (0<<6) -#define DREF_SSC4_CENTERSPREAD (1<<6) -#define DREF_SSC1_DISABLE (0<<1) -#define DREF_SSC1_ENABLE (1<<1) -#define DREF_SSC4_DISABLE (0) -#define DREF_SSC4_ENABLE (1) +#define DREF_SSC4_DOWNSPREAD (0<<6) +#define DREF_SSC4_CENTERSPREAD (1<<6) +#define DREF_SSC1_DISABLE (0<<1) +#define DREF_SSC1_ENABLE (1<<1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1)
-#define PCH_RAWCLK_FREQ 0xc6204 -#define FDL_TP1_TIMER_SHIFT 12 -#define FDL_TP1_TIMER_MASK (3<<12) -#define FDL_TP2_TIMER_SHIFT 10 -#define FDL_TP2_TIMER_MASK (3<<10) -#define RAWCLK_FREQ_MASK 0x3ff +#define PCH_RAWCLK_FREQ 0xc6204 +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3<<12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3<<10) +#define RAWCLK_FREQ_MASK 0x3ff
-#define PCH_DPLL_TMR_CFG 0xc6208 +#define PCH_DPLL_TMR_CFG 0xc6208
-#define PCH_SSC4_PARMS 0xc6210 -#define PCH_SSC4_AUX_PARMS 0xc6214 +#define PCH_SSC4_PARMS 0xc6210 +#define PCH_SSC4_AUX_PARMS 0xc6214
#define PCH_DPLL_SEL 0xc7000 #define TRANSA_DPLL_ENABLE (1<<3) @@ -3291,55 +3291,55 @@
/* transcoder */
-#define _TRANS_HTOTAL_A 0xe0000 -#define TRANS_HTOTAL_SHIFT 16 -#define TRANS_HACTIVE_SHIFT 0 -#define _TRANS_HBLANK_A 0xe0004 +#define _TRANS_HTOTAL_A 0xe0000 +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 +#define _TRANS_HBLANK_A 0xe0004 #define TRANS_HBLANK_END_SHIFT 16 #define TRANS_HBLANK_START_SHIFT 0 -#define _TRANS_HSYNC_A 0xe0008 +#define _TRANS_HSYNC_A 0xe0008 #define TRANS_HSYNC_END_SHIFT 16 #define TRANS_HSYNC_START_SHIFT 0 -#define _TRANS_VTOTAL_A 0xe000c -#define TRANS_VTOTAL_SHIFT 16 -#define TRANS_VACTIVE_SHIFT 0 -#define _TRANS_VBLANK_A 0xe0010 +#define _TRANS_VTOTAL_A 0xe000c +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 +#define _TRANS_VBLANK_A 0xe0010 #define TRANS_VBLANK_END_SHIFT 16 #define TRANS_VBLANK_START_SHIFT 0 -#define _TRANS_VSYNC_A 0xe0014 +#define _TRANS_VSYNC_A 0xe0014 #define TRANS_VSYNC_END_SHIFT 16 #define TRANS_VSYNC_START_SHIFT 0 #define _TRANS_VSYNCSHIFT_A 0xe0028
-#define _TRANSA_DATA_M1 0xe0030 -#define _TRANSA_DATA_N1 0xe0034 -#define _TRANSA_DATA_M2 0xe0038 -#define _TRANSA_DATA_N2 0xe003c -#define _TRANSA_DP_LINK_M1 0xe0040 -#define _TRANSA_DP_LINK_N1 0xe0044 -#define _TRANSA_DP_LINK_M2 0xe0048 -#define _TRANSA_DP_LINK_N2 0xe004c +#define _TRANSA_DATA_M1 0xe0030 +#define _TRANSA_DATA_N1 0xe0034 +#define _TRANSA_DATA_M2 0xe0038 +#define _TRANSA_DATA_N2 0xe003c +#define _TRANSA_DP_LINK_M1 0xe0040 +#define _TRANSA_DP_LINK_N1 0xe0044 +#define _TRANSA_DP_LINK_M2 0xe0048 +#define _TRANSA_DP_LINK_N2 0xe004c
/* Per-transcoder DIP controls */
-#define _VIDEO_DIP_CTL_A 0xe0200 -#define _VIDEO_DIP_DATA_A 0xe0208 -#define _VIDEO_DIP_GCP_A 0xe0210 +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_GCP_A 0xe0210
-#define _VIDEO_DIP_CTL_B 0xe1200 -#define _VIDEO_DIP_DATA_B 0xe1208 -#define _VIDEO_DIP_GCP_B 0xe1210 +#define _VIDEO_DIP_CTL_B 0xe1200 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define _VIDEO_DIP_GCP_B 0xe1210
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define _TRANS_HTOTAL_B 0xe1000 -#define _TRANS_HBLANK_B 0xe1004 -#define _TRANS_HSYNC_B 0xe1008 -#define _TRANS_VTOTAL_B 0xe100c -#define _TRANS_VBLANK_B 0xe1010 -#define _TRANS_VSYNC_B 0xe1014 +#define _TRANS_HTOTAL_B 0xe1000 +#define _TRANS_HBLANK_B 0xe1004 +#define _TRANS_HSYNC_B 0xe1008 +#define _TRANS_VTOTAL_B 0xe100c +#define _TRANS_VBLANK_B 0xe1010 +#define _TRANS_VSYNC_B 0xe1014 #define _TRANS_VSYNCSHIFT_B 0xe1028
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) @@ -3349,16 +3349,16 @@ #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ - _TRANS_VSYNCSHIFT_B) + _TRANS_VSYNCSHIFT_B)
-#define _TRANSB_DATA_M1 0xe1030 -#define _TRANSB_DATA_N1 0xe1034 -#define _TRANSB_DATA_M2 0xe1038 -#define _TRANSB_DATA_N2 0xe103c -#define _TRANSB_DP_LINK_M1 0xe1040 -#define _TRANSB_DP_LINK_N1 0xe1044 -#define _TRANSB_DP_LINK_M2 0xe1048 -#define _TRANSB_DP_LINK_N2 0xe104c +#define _TRANSB_DATA_M1 0xe1030 +#define _TRANSB_DATA_N1 0xe1034 +#define _TRANSB_DATA_M2 0xe1038 +#define _TRANSB_DATA_N2 0xe103c +#define _TRANSB_DP_LINK_M1 0xe1040 +#define _TRANSB_DP_LINK_N1 0xe1044 +#define _TRANSB_DP_LINK_M2 0xe1048 +#define _TRANSB_DP_LINK_N2 0xe104c
#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) @@ -3369,33 +3369,33 @@ #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
-#define _TRANSACONF 0xf0008 -#define _TRANSBCONF 0xf1008 +#define _TRANSACONF 0xf0008 +#define _TRANSBCONF 0xf1008 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) -#define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) -#define TRANS_STATE_MASK (1<<30) -#define TRANS_STATE_DISABLE (0<<30) -#define TRANS_STATE_ENABLE (1<<30) +#define TRANS_DISABLE (0<<31) +#define TRANS_ENABLE (1<<31) +#define TRANS_STATE_MASK (1<<30) +#define TRANS_STATE_DISABLE (0<<30) +#define TRANS_STATE_ENABLE (1<<30) #define TRANS_FSYNC_DELAY_HB1 (0<<27) #define TRANS_FSYNC_DELAY_HB2 (1<<27) #define TRANS_FSYNC_DELAY_HB3 (2<<27) #define TRANS_FSYNC_DELAY_HB4 (3<<27) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_VIDEO_AUDIO (0<<26) -#define TRANS_INTERLACE_MASK (7<<21) -#define TRANS_PROGRESSIVE (0<<21) -#define TRANS_INTERLACED (3<<21) +#define TRANS_DP_AUDIO_ONLY (1<<26) +#define TRANS_DP_VIDEO_AUDIO (0<<26) +#define TRANS_INTERLACE_MASK (7<<21) +#define TRANS_PROGRESSIVE (0<<21) +#define TRANS_INTERLACED (3<<21) #define TRANS_LEGACY_INTERLACED_ILK (2<<21) -#define TRANS_8BPC (0<<5) -#define TRANS_10BPC (1<<5) -#define TRANS_6BPC (2<<5) -#define TRANS_12BPC (3<<5) +#define TRANS_8BPC (0<<5) +#define TRANS_10BPC (1<<5) +#define TRANS_6BPC (2<<5) +#define TRANS_12BPC (3<<5)
#define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
#define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 @@ -3405,8 +3405,8 @@ #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
-#define _FDI_RXA_CHICKEN 0xc200c -#define _FDI_RXB_CHICKEN 0xc2010 +#define _FDI_RXA_CHICKEN 0xc200c +#define _FDI_RXB_CHICKEN 0xc2010 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) @@ -3415,23 +3415,23 @@ #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
/* CPU: FDI_TX */ -#define _FDI_TXA_CTL 0x60100 -#define _FDI_TXB_CTL 0x61100 +#define _FDI_TXA_CTL 0x60100 +#define _FDI_TXB_CTL 0x61100 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) -#define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) -#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) -#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) -#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) -#define FDI_LINK_TRAIN_NONE (3<<28) -#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) -#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) +#define FDI_TX_DISABLE (0<<31) +#define FDI_TX_ENABLE (1<<31) +#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) +#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) +#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) +#define FDI_LINK_TRAIN_NONE (3<<28) +#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) +#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* SNB A-stepping */ @@ -3445,48 +3445,48 @@ #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) -#define FDI_DP_PORT_WIDTH_X1 (0<<19) -#define FDI_DP_PORT_WIDTH_X2 (1<<19) -#define FDI_DP_PORT_WIDTH_X3 (2<<19) -#define FDI_DP_PORT_WIDTH_X4 (3<<19) -#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) +#define FDI_DP_PORT_WIDTH_X1 (0<<19) +#define FDI_DP_PORT_WIDTH_X2 (1<<19) +#define FDI_DP_PORT_WIDTH_X3 (2<<19) +#define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) /* Ironlake: hardwired to 1 */ -#define FDI_TX_PLL_ENABLE (1<<14) +#define FDI_TX_PLL_ENABLE (1<<14)
/* Ivybridge has different bits for lolz */ -#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) +#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) +#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) -#define FDI_LINK_TRAIN_NONE_IVB (3<<8) +#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
/* both Tx and Rx */ #define FDI_COMPOSITE_SYNC (1<<11) #define FDI_LINK_TRAIN_AUTO (1<<10) -#define FDI_SCRAMBLING_ENABLE (0<<7) -#define FDI_SCRAMBLING_DISABLE (1<<7) +#define FDI_SCRAMBLING_ENABLE (0<<7) +#define FDI_SCRAMBLING_DISABLE (1<<7)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ -#define _FDI_RXA_CTL 0xf000c -#define _FDI_RXB_CTL 0xf100c +#define _FDI_RXA_CTL 0xf000c +#define _FDI_RXB_CTL 0xf100c #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_ENABLE (1<<31) /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE (1<<27) #define FDI_FE_ERRC_ENABLE (1<<26) -#define FDI_DP_PORT_WIDTH_X8 (7<<19) -#define FDI_8BPC (0<<16) -#define FDI_10BPC (1<<16) -#define FDI_6BPC (2<<16) -#define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) -#define FDI_DMI_LINK_REVERSE_MASK (1<<14) -#define FDI_RX_PLL_ENABLE (1<<13) -#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) -#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) -#define FDI_FS_ERR_REPORT_ENABLE (1<<9) -#define FDI_FE_ERR_REPORT_ENABLE (1<<8) -#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) -#define FDI_PCDCLK (1<<4) +#define FDI_DP_PORT_WIDTH_X8 (7<<19) +#define FDI_8BPC (0<<16) +#define FDI_10BPC (1<<16) +#define FDI_6BPC (2<<16) +#define FDI_12BPC (3<<16) +#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_DMI_LINK_REVERSE_MASK (1<<14) +#define FDI_RX_PLL_ENABLE (1<<13) +#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) +#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) +#define FDI_FS_ERR_REPORT_ENABLE (1<<9) +#define FDI_FE_ERR_REPORT_ENABLE (1<<8) +#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) +#define FDI_PCDCLK (1<<4) /* CPT */ #define FDI_AUTO_TRAINING (1<<10) #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) @@ -3495,91 +3495,91 @@ #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
-#define _FDI_RXA_MISC 0xf0010 -#define _FDI_RXB_MISC 0xf1010 -#define _FDI_RXA_TUSIZE1 0xf0030 -#define _FDI_RXA_TUSIZE2 0xf0038 -#define _FDI_RXB_TUSIZE1 0xf1030 -#define _FDI_RXB_TUSIZE2 0xf1038 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define _FDI_RXA_TUSIZE1 0xf0030 +#define _FDI_RXA_TUSIZE2 0xf0038 +#define _FDI_RXB_TUSIZE1 0xf1030 +#define _FDI_RXB_TUSIZE2 0xf1038 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
/* FDI_RX interrupt register format */ -#define FDI_RX_INTER_LANE_ALIGN (1<<10) -#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ -#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ -#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) -#define FDI_RX_FS_CODE_ERR (1<<6) -#define FDI_RX_FE_CODE_ERR (1<<5) -#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) -#define FDI_RX_HDCP_LINK_FAIL (1<<3) -#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) -#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) -#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) - -#define _FDI_RXA_IIR 0xf0014 -#define _FDI_RXA_IMR 0xf0018 -#define _FDI_RXB_IIR 0xf1014 -#define _FDI_RXB_IMR 0xf1018 +#define FDI_RX_INTER_LANE_ALIGN (1<<10) +#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ +#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ +#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) +#define FDI_RX_FS_CODE_ERR (1<<6) +#define FDI_RX_FE_CODE_ERR (1<<5) +#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) +#define FDI_RX_HDCP_LINK_FAIL (1<<3) +#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) +#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) +#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) + +#define _FDI_RXA_IIR 0xf0014 +#define _FDI_RXA_IMR 0xf0018 +#define _FDI_RXB_IIR 0xf1014 +#define _FDI_RXB_IMR 0xf1018 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
-#define FDI_PLL_CTL_1 0xfe000 -#define FDI_PLL_CTL_2 0xfe004 +#define FDI_PLL_CTL_1 0xfe000 +#define FDI_PLL_CTL_2 0xfe004
/* CRT */ -#define PCH_ADPA 0xe1100 +#define PCH_ADPA 0xe1100 #define ADPA_TRANS_SELECT_MASK (1<<30) -#define ADPA_TRANS_A_SELECT 0 -#define ADPA_TRANS_B_SELECT (1<<30) +#define ADPA_TRANS_A_SELECT 0 +#define ADPA_TRANS_B_SELECT (1<<30) #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) -#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) -#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) -#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) -#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) -#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) -#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) -#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) -#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) +#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) +#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) +#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) +#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) +#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) +#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) +#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) +#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
/* or SDVOB */ -#define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) -#define TRANSCODER(pipe) ((pipe) << 30) -#define TRANSCODER_CPT(pipe) ((pipe) << 29) -#define TRANSCODER_MASK (1 << 30) -#define TRANSCODER_MASK_CPT (3 << 29) -#define COLOR_FORMAT_8bpc (0) -#define COLOR_FORMAT_12bpc (3 << 26) -#define SDVOB_HOTPLUG_ENABLE (1 << 23) -#define SDVO_ENCODING (0) -#define TMDS_ENCODING (2 << 10) -#define NULL_PACKET_VSYNC_ENABLE (1 << 9) +#define HDMIB 0xe1140 +#define PORT_ENABLE (1 << 31) +#define TRANSCODER(pipe) ((pipe) << 30) +#define TRANSCODER_CPT(pipe) ((pipe) << 29) +#define TRANSCODER_MASK (1 << 30) +#define TRANSCODER_MASK_CPT (3 << 29) +#define COLOR_FORMAT_8bpc (0) +#define COLOR_FORMAT_12bpc (3 << 26) +#define SDVOB_HOTPLUG_ENABLE (1 << 23) +#define SDVO_ENCODING (0) +#define TMDS_ENCODING (2 << 10) +#define NULL_PACKET_VSYNC_ENABLE (1 << 9) /* CPT */ #define HDMI_MODE_SELECT (1 << 9) #define DVI_MODE_SELECT (0) -#define SDVOB_BORDER_ENABLE (1 << 7) -#define AUDIO_ENABLE (1 << 6) -#define VSYNC_ACTIVE_HIGH (1 << 4) -#define HSYNC_ACTIVE_HIGH (1 << 3) -#define PORT_DETECTED (1 << 2) +#define SDVOB_BORDER_ENABLE (1 << 7) +#define AUDIO_ENABLE (1 << 6) +#define VSYNC_ACTIVE_HIGH (1 << 4) +#define HSYNC_ACTIVE_HIGH (1 << 3) +#define PORT_DETECTED (1 << 2)
/* PCH SDVOB multiplex with HDMIB */ #define PCH_SDVOB HDMIB
-#define HDMIC 0xe1150 -#define HDMID 0xe1160 +#define HDMIC 0xe1150 +#define HDMID 0xe1160
#define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) @@ -3723,16 +3723,16 @@ #define FORCEWAKE_MT 0xa188 /* multi-threaded */ #define FORCEWAKE_MT_ACK 0x130040 #define ECOBUS 0xa180 -#define FORCEWAKE_MT_ENABLE (1<<5) +#define FORCEWAKE_MT_ENABLE (1<<5)
#define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 -#define GT_FIFO_OVFERR (1<<2) -#define GT_FIFO_IAWRERR (1<<1) -#define GT_FIFO_IARDERR (1<<0) +#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_OVFERR (1<<2) +#define GT_FIFO_IAWRERR (1<<1) +#define GT_FIFO_IARDERR (1<<0)
#define GT_FIFO_FREE_ENTRIES 0x120008 -#define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL1 0x9400 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) @@ -3743,46 +3743,46 @@ # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
#define GEN6_RPNSWREQ 0xA008 -#define GEN6_TURBO_DISABLE (1<<31) -#define GEN6_FREQUENCY(x) ((x)<<25) -#define GEN6_OFFSET(x) ((x)<<19) -#define GEN6_AGGRESSIVE_TURBO (0<<15) +#define GEN6_TURBO_DISABLE (1<<31) +#define GEN6_FREQUENCY(x) ((x)<<25) +#define GEN6_OFFSET(x) ((x)<<19) +#define GEN6_AGGRESSIVE_TURBO (0<<15) #define GEN6_RC_VIDEO_FREQ 0xA00C #define GEN6_RC_CONTROL 0xA090 -#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) -#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) -#define GEN6_RC_CTL_RC6_ENABLE (1<<18) -#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) -#define GEN6_RC_CTL_RC7_ENABLE (1<<22) -#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) -#define GEN6_RC_CTL_HW_ENABLE (1<<31) +#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) +#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) +#define GEN6_RC_CTL_RC6_ENABLE (1<<18) +#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) +#define GEN6_RC_CTL_RC7_ENABLE (1<<22) +#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) +#define GEN6_RC_CTL_HW_ENABLE (1<<31) #define GEN6_RP_DOWN_TIMEOUT 0xA010 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 #define GEN6_RPSTAT1 0xA01C -#define GEN6_CAGF_SHIFT 8 -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) +#define GEN6_CAGF_SHIFT 8 +#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) #define GEN6_RP_CONTROL 0xA024 -#define GEN6_RP_MEDIA_TURBO (1<<11) -#define GEN6_RP_MEDIA_MODE_MASK (3<<9) -#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) -#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) -#define GEN6_RP_MEDIA_HW_MODE (1<<9) -#define GEN6_RP_MEDIA_SW_MODE (0<<9) -#define GEN6_RP_MEDIA_IS_GFX (1<<8) -#define GEN6_RP_ENABLE (1<<7) -#define GEN6_RP_UP_IDLE_MIN (0x1<<3) -#define GEN6_RP_UP_BUSY_AVG (0x2<<3) -#define GEN6_RP_UP_BUSY_CONT (0x4<<3) -#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) +#define GEN6_RP_MEDIA_TURBO (1<<11) +#define GEN6_RP_MEDIA_MODE_MASK (3<<9) +#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) +#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) +#define GEN6_RP_MEDIA_HW_MODE (1<<9) +#define GEN6_RP_MEDIA_SW_MODE (0<<9) +#define GEN6_RP_MEDIA_IS_GFX (1<<8) +#define GEN6_RP_ENABLE (1<<7) +#define GEN6_RP_UP_IDLE_MIN (0x1<<3) +#define GEN6_RP_UP_BUSY_AVG (0x2<<3) +#define GEN6_RP_UP_BUSY_CONT (0x4<<3) +#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) #define GEN6_RP_UP_THRESHOLD 0xA02C #define GEN6_RP_DOWN_THRESHOLD 0xA030 #define GEN6_RP_CUR_UP_EI 0xA050 -#define GEN6_CURICONT_MASK 0xffffff +#define GEN6_CURICONT_MASK 0xffffff #define GEN6_RP_CUR_UP 0xA054 -#define GEN6_CURBSYTAVG_MASK 0xffffff +#define GEN6_CURBSYTAVG_MASK 0xffffff #define GEN6_RP_PREV_UP 0xA058 #define GEN6_RP_CUR_DOWN_EI 0xA05C -#define GEN6_CURIAVG_MASK 0xffffff +#define GEN6_CURIAVG_MASK 0xffffff #define GEN6_RP_CUR_DOWN 0xA060 #define GEN6_RP_PREV_DOWN 0xA064 #define GEN6_RP_UP_EI 0xA068 @@ -3817,20 +3817,20 @@ GEN6_PM_RP_DOWN_TIMEOUT)
#define GEN6_PCODE_MAILBOX 0x138124 -#define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 +#define GEN6_PCODE_READY (1<<31) +#define GEN6_READ_OC_PARAMS 0xc +#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 +#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_DATA 0x138128 -#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_GT_CORE_STATUS 0x138060 -#define GEN6_CORE_CPD_STATE_MASK (7<<4) -#define GEN6_RCn_MASK 7 -#define GEN6_RC0 0 -#define GEN6_RC3 2 -#define GEN6_RC6 3 -#define GEN6_RC7 4 +#define GEN6_CORE_CPD_STATE_MASK (7<<4) +#define GEN6_RCn_MASK 7 +#define GEN6_RC0 0 +#define GEN6_RC3 2 +#define GEN6_RC6 3 +#define GEN6_RC7 4
#define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB @@ -3865,14 +3865,14 @@
#define IBX_AUD_CONFIG_A 0xe2000 #define CPT_AUD_CONFIG_A 0xe5000 -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) -#define AUD_CONFIG_UPPER_N_SHIFT 20 -#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) -#define AUD_CONFIG_LOWER_N_SHIFT 4 -#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) +#define AUD_CONFIG_UPPER_N_SHIFT 20 +#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) +#define AUD_CONFIG_LOWER_N_SHIFT 4 +#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 +#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) +#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
#endif /* _I915_REG_H_ */ diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 7f6b7dd..c9be9f9 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -64,7 +64,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x00; /* Use video bios default */ @@ -126,7 +126,7 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } @@ -162,7 +162,7 @@ static void mainboard_init(device_t dev) * enable CLKREQ: LAN pci config space 0x81h=01 */ ethernet_dev = dev_find_device(STOUT_NIC_VENDOR_ID, - STOUT_NIC_DEVICE_ID, dev); + STOUT_NIC_DEVICE_ID, dev);
if (ethernet_dev != NULL) pci_write_config8(ethernet_dev, 0x81, 0x01); diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 44dc46e..b34adce 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -88,7 +88,7 @@ void mainboard_smi_sleep(u8 slp_typ) * 0/0 All USB port off * 1/0 USB on, all USB port didn’t support wake up * 0/1 USB on, yellow port support wake up charge, but may not support - * charge smart phone. + * charge smart phone. * 1/1 USB on, yellow port in AUTO mode and didn’t support wake up system. */ if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) { diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 8a961ea..8d04387 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -67,16 +67,16 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) - * D20IP_XHCI XHCI INTA -> PIRQD (MSI) - * D26IP_E2P EHCI #2 INTA -> PIRQF - * D27IP_ZIP HDA INTA -> PIRQA (MSI) - * D28IP_P2IP WLAN INTA -> PIRQD + * GFX INTA -> PIRQA (MSI) + * D20IP_XHCI XHCI INTA -> PIRQD (MSI) + * D26IP_E2P EHCI #2 INTA -> PIRQF + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * D28IP_P2IP WLAN INTA -> PIRQD * D28IP_P3IP Card Reader INTB -> PIRQE - * D28IP_P6IP LAN INTC -> PIRQB - * D29IP_E1P EHCI #1 INTA -> PIRQD - * D31IP_SIP SATA INTA -> PIRQB (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQH + * D28IP_P6IP LAN INTC -> PIRQB + * D29IP_E1P EHCI #1 INTA -> PIRQD + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH */
/* Device interrupt pin register (board specific) */ @@ -185,7 +185,7 @@ void main(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb_port_config: { - /* enabled usb oc pin length */ + /* enabled usb oc pin length */ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */ { 0, 1, 0x0000 }, /* P2: Empty */ diff --git a/src/mainboard/google/stout/thermal.h b/src/mainboard/google/stout/thermal.h index d93fbef..fe7b736 100644 --- a/src/mainboard/google/stout/thermal.h +++ b/src/mainboard/google/stout/thermal.h @@ -23,12 +23,12 @@ /* Active Thermal and fans are controlled by the EC. */
/* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 99 +#define CRITICAL_TEMPERATURE 99
/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +#define PASSIVE_TEMPERATURE 90
/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 +#define MAX_TEMPERATURE 100
#endif /* STOUT_THERMAL_H */ diff --git a/src/mainboard/hp/dl145_g1/cmos.layout b/src/mainboard/hp/dl145_g1/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/hp/dl145_g1/cmos.layout +++ b/src/mainboard/hp/dl145_g1/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb index c955ac3..0609d62 100644 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ b/src/mainboard/hp/dl145_g1/devicetree.cb @@ -9,14 +9,14 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 device pci 18.0 on end # link 0 device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 + device pci 18.0 on # link 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on # PCIX Bridge A # PCI-X expansion slot cards auto-detected here end device pci 0.1 on end # IOAPIC A - device pci 1.0 on # PCIX Bridge B + device pci 1.0 on # PCIX Bridge B # On-board BCM5704 dual port ethernet chip auto-detected here # Optional SCSI board also (?) end @@ -124,7 +124,7 @@ chip northbridge/amd/amdk8/root_complex device i2c 69 on end # Texas Instruments cdc960 clock synthesizer end end # SMBus 2.0 controller - device pci 1.3 on # System management registers (ACPI) + device pci 1.3 on # System management registers (ACPI) end # System management #device pci 1.4 off end device pci 1.5 off end # AC97 Audio diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c index 9a9fb10..6189754 100644 --- a/src/mainboard/hp/dl145_g1/resourcemap.c +++ b/src/mainboard/hp/dl145_g1/resourcemap.c @@ -203,11 +203,11 @@ static void setup_dl145g1_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/hp/dl145_g3/cmos.layout b/src/mainboard/hp/dl145_g3/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/hp/dl145_g3/cmos.layout +++ b/src/mainboard/hp/dl145_g3/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb index 7012cf9..592cfc5 100644 --- a/src/mainboard/hp/dl145_g3/devicetree.cb +++ b/src/mainboard/hp/dl145_g3/devicetree.cb @@ -30,7 +30,7 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on end # Legacy pci main 0x0205 device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.2 on # LPC 0x0234 chip superio/nsc/pc87417 device pnp 4e.0 off # Floppy io 0x60 = 0x3f0 @@ -64,8 +64,8 @@ chip northbridge/amd/amdk8/root_complex end end # end superio end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 device pci 1.5 on end # XIOAPIC1 device pci 1.6 on end # XIOAPIC2 device pci 2.0 on end # USB 0x0223 diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index cef2886..69007b0 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -126,7 +126,7 @@ void get_bus_conf(void) }
-/*I/O APICs: APIC ID Version State Address*/ +/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c index 2d2394b..b79aa24 100644 --- a/src/mainboard/hp/dl145_g3/irq_tables.c +++ b/src/mainboard/hp/dl145_g3/irq_tables.c @@ -14,46 +14,46 @@ #endif
static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x0, /* Where the interrupt router lies (bus) */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x0, /* Where the interrupt router lies (bus) */ (0x2<<3)|0x4, - 0, /* IRQs devoted exclusively to PCI usage */ - 0, /* Vendor */ - 0, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x2a, /* u8 checksum. This has to be set to some - value that would give 0 after the sum of all - bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge - {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb - {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr - {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge - {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA - {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge - //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, - {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, - {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge - //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, - {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet - {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge - //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, - {0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot - } + 0, /* IRQs devoted exclusively to PCI usage */ + 0, /* Vendor */ + 0, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x2a, /* u8 checksum. This has to be set to some + value that would give 0 after the sum of all + bytes for this structure (including checksum) */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge + {0x00,(0x02<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge + {0x00,(0x03<<3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb + {0x00,(0x04<<3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr + {0x00,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge + {0x01,(0x0e<<3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA + {0x01,(0x0d<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge + //{0x02,(0x01<<3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0}, + {0x00,(0x06<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x03,(0x00<<3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0}, + {0x00,(0x07<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + {0x00,(0x08<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + {0x00,(0x09<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x06,(0x00<<3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge + //{0x07,(0x00<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, + {0x08,(0x04<<3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet + {0x00,(0x18<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge + //{0x10,(0x01<<3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0}, + {0x40,(0x01<<3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot + } };
unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); }
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index bbd8405..380966b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /*I/O APICs: APIC ID Version State Address*/ + /*I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; int i; @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) } }
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa); mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 7250017..54a144f 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -1,7 +1,7 @@ if BOARD_HP_DL165_G6_FAM10
config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y + def_bool y select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 479e0b6..a6ce051 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -1,6 +1,6 @@ #include <device/pnp_def.h>
-#define SCH4307_CONFIG_PORT 0x162e +#define SCH4307_CONFIG_PORT 0x162e static inline void shc4307_enter_ext_func_mode(device_t dev) { unsigned port = dev >> 8; @@ -19,7 +19,7 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa)
/* FIXME: This appears to be a super-io initialisation, - * placed in the mainboard directory. + * placed in the mainboard directory. */ void shc4307_init(void) { diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 1c6a3cd..2cee094 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb index 2dbcb9b..5d7510e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb +++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/amd/amdfam10/root_complex end device pci 1.0 on end # Legacy pci main 0x0205 device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 + device pci 1.2 on # LPC 0x0234 chip superio/nsc/pc87417 device pnp 4e.0 off # Floppy io 0x60 = 0x3f0 @@ -66,8 +66,8 @@ chip northbridge/amd/amdfam10/root_complex end end # end superio end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 device pci 1.5 on end # XIOAPIC1 device pci 1.6 on end # XIOAPIC2 device pci 2.0 on end # USB 0x0223 diff --git a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c index 1784aec..c4f49a0 100644 --- a/src/mainboard/hp/dl165_g6_fam10/irq_tables.c +++ b/src/mainboard/hp/dl165_g6_fam10/irq_tables.c @@ -29,7 +29,7 @@ static const struct irq_routing_table intel_irq_routing_table = { * for this structure (including checksum). */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x01, (0x0e << 3) | 0x0, {{0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}, {0x07, 0x0020}}, 0x0, 0x0}, /* 1166:024a */ {0x00, (0x03 << 3) | 0x0, {{0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}, {0x01, 0x0400}}, 0x0, 0x0}, /* 1166:0223 */ {0x00, (0x06 << 3) | 0x0, {{0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}, {0x24, 0xdac0}}, 0x0, 0x0}, /* 1166:0140 */ diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..d6f25f4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &isa_bus);
- /*I/O APICs: APIC ID Version State Address*/ + /*I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; int i; diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 11a8d08..2c4366e 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -181,10 +181,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 }
post_code(0x3A); @@ -233,8 +233,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index 7de0c83..3e41197 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -14,39 +14,39 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge - # TODO: PC87364 actually! - # TODO: Check Super I/O settings and compare to superiotool -d. - chip superio/nsc/pc87360 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # PS/2 mouse - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # ACB - device pnp 2e.9 off end # FSCM - device pnp 2e.a off end # WDT - end + # TODO: PC87364 actually! + # TODO: Check Super I/O settings and compare to superiotool -d. + chip superio/nsc/pc87360 # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # PS/2 mouse + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # ACB + device pnp 2e.9 off end # FSCM + device pnp 2e.a off end # WDT + end end device pci 1f.1 on end # IDE device pci 1f.2 on end # USB diff --git a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c b/src/mainboard/hp/e_vectra_p2706t/irq_tables.c index d333a4c..b80d508 100644 --- a/src/mainboard/hp/e_vectra_p2706t/irq_tables.c +++ b/src/mainboard/hp/e_vectra_p2706t/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x59, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0}, {0x00, (0x1f << 3) | 0x0, {{0xfe, 0x4000}, {0x61, 0xdeb8}, {0x00, 0x0000}, {0x63, 0xdeb8}}, 0x0, 0x0}, diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index b3e8c4e..9591b0d 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -21,165 +21,165 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -#928 40 r 0 unused +416 512 s 0 boot_devices +#928 40 r 0 unused
# coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature
-968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3
-#971 13 r 0 unused +#971 13 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed +8 0 Disabled +8 1 Speed #8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (�C/�F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 #10 10 60/140 #10 11 63/145 #10 12 66/150 diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 7e5076d..fe41dd4 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -1,18 +1,18 @@ chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end
- device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -28,41 +28,41 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
- register "ide_legacy_combined" = "0x0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1"
- #device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + #device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627ehg + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627ehg device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 4e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 @@ -98,13 +98,13 @@ chip northbridge/intel/i945 irq 0x70 = 0 end
- end + end
- end + end device pci 1f.1 on end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index c206bf1..9b10537 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -21,10 +21,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b9, /* Device */ @@ -32,7 +32,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf, /* u8 checksum. */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c index 1baf728..6349739 100644 --- a/src/mainboard/ibase/mb899/mptable.c +++ b/src/mainboard/ibase/mb899/mptable.c @@ -27,16 +27,16 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; struct device *riser = NULL, *firewire = NULL; int firewire_bus = 0, riser_bus = 0, isa_bus; int ioapic_id;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
firewire = dev_find_device(0x104c, 0x8023, 0); if (firewire) { @@ -69,7 +69,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, ioapic_id, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x3, ioapic_id, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x4, ioapic_id, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x8, ioapic_id, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x9, ioapic_id, 0x9); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xa, ioapic_id, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0xb, ioapic_id, 0xb); @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/ibm/e325/cmos.layout b/src/mainboard/ibm/e325/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/ibm/e325/cmos.layout +++ b/src/mainboard/ibm/e325/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb index bdaee50..104dfe7 100644 --- a/src/mainboard/ibm/e325/devicetree.cb +++ b/src/mainboard/ibm/e325/devicetree.cb @@ -7,7 +7,7 @@ chip northbridge/amd/amdk8/root_complex device domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end diff --git a/src/mainboard/ibm/e325/irq_tables.c b/src/mainboard/ibm/e325/irq_tables.c index 24987b7..8886455 100644 --- a/src/mainboard/ibm/e325/irq_tables.c +++ b/src/mainboard/ibm/e325/irq_tables.c @@ -17,7 +17,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ @@ -56,5 +56,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 7d1b8f3..a339f07 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { - bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); + bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -82,39 +82,39 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
- /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ + /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ /* Integrated SMBus 2.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); /* Integrated AMD AC97 Audio */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
/* Integrated AMD USB */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
/* On board ATI Rage XL */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
/* On board Broadcom nics */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
/* On board LSI SCSI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
/* PCI Slot 1 PCIX */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
/* PCI Slot 2 PCIX */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
/* Standard local interrupt assignments: - * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */ diff --git a/src/mainboard/ibm/e325/resourcemap.c b/src/mainboard/ibm/e325/resourcemap.c index 85aafbf..da7f4e5 100644 --- a/src/mainboard/ibm/e325/resourcemap.c +++ b/src/mainboard/ibm/e325/resourcemap.c @@ -206,11 +206,11 @@ static void setup_ibm_e325_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n @@ -264,8 +264,8 @@ static void setup_ibm_e325_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, - }; - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); + }; + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); } diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index e4dea5f..dec51ee 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -85,31 +85,31 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_ibm_e325_resource_map(); + setup_ibm_e325_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/ibm/e326/cmos.layout b/src/mainboard/ibm/e326/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/ibm/e326/cmos.layout +++ b/src/mainboard/ibm/e326/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index 1888987..f815fc5 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -8,7 +8,7 @@ chip northbridge/amd/amdk8/root_complex device domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -21,7 +21,7 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 on end device pci 1.0 off end - device pci 5.0 on end # ATI Rage XL + device pci 5.0 on end # ATI Rage XL end device pci 1.0 on chip superio/nsc/pc87366 diff --git a/src/mainboard/ibm/e326/irq_tables.c b/src/mainboard/ibm/e326/irq_tables.c index 24987b7..8886455 100644 --- a/src/mainboard/ibm/e326/irq_tables.c +++ b/src/mainboard/ibm/e326/irq_tables.c @@ -17,7 +17,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT table entries */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */ @@ -56,5 +56,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index b963a0c..6c83376 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); if (dev) { - bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); + bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); @@ -81,39 +81,39 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
- /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ + /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */ /* Integrated SMBus 2.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13); /* Integrated AMD AC97 Audio */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
/* Integrated AMD USB */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
/* On board ATI Rage XL */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
/* On board Broadcom nics */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
/* On board LSI SCSI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
/* PCI Slot 1 PCIX */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
/* PCI Slot 2 PCIX */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
/* Standard local interrupt assignments: - * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */ diff --git a/src/mainboard/ibm/e326/resourcemap.c b/src/mainboard/ibm/e326/resourcemap.c index 98fdcc0..44244aa 100644 --- a/src/mainboard/ibm/e326/resourcemap.c +++ b/src/mainboard/ibm/e326/resourcemap.c @@ -206,11 +206,11 @@ static void setup_ibm_e326_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n @@ -264,8 +264,8 @@ static void setup_ibm_e326_resource_map(void) PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xe8), 0x0000FC88, 0, PCI_ADDR(0, 0x18, 1, 0xec), 0x0000FC88, 0, - }; - int max; - max = ARRAY_SIZE(register_values); - setup_resource_map(register_values, max); + }; + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); } diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 3462fcb..0b34a61 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -85,31 +85,31 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_ibm_e326_resource_map(); + setup_ibm_e326_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/iei/juki-511p/cmos.layout b/src/mainboard/iei/juki-511p/cmos.layout index 67a3ce4..4c889ba 100644 --- a/src/mainboard/iei/juki-511p/cmos.layout +++ b/src/mainboard/iei/juki-511p/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/iei/juki-511p/devicetree.cb b/src/mainboard/iei/juki-511p/devicetree.cb index 4706ff5..a2d215a 100644 --- a/src/mainboard/iei/juki-511p/devicetree.cb +++ b/src/mainboard/iei/juki-511p/devicetree.cb @@ -3,44 +3,44 @@ chip northbridge/amd/gx1 device pci 0.0 on end chip southbridge/amd/cs5530
- device pci 12.0 on - chip superio/winbond/w83977f - device pnp 3f0.0 on # FDC - irq 0x70 = 6 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.4 on # RTC - io 0x60 = 0x070 - irq 0x70 = 8 - end - device pnp 3f0.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Int 1 for PS/2 keyboard - irq 0x72 = 12 # Int 12 for PS/2 mouse - end - device pnp 3f0.6 off # IR - end - device pnp 3f0.7 off # GPIO1 - end - device pnp 3f0.8 off # GPIO - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard + device pci 12.0 on + chip superio/winbond/w83977f + device pnp 3f0.0 on # FDC + irq 0x70 = 6 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.4 on # RTC + io 0x60 = 0x070 + irq 0x70 = 8 + end + device pnp 3f0.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Int 1 for PS/2 keyboard + irq 0x72 = 12 # Int 12 for PS/2 mouse + end + device pnp 3f0.6 off # IR + end + device pnp 3f0.7 off # GPIO1 + end + device pnp 3f0.8 off # GPIO + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard
end
diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/iei/kino-780am2-fam10/cmos.layout b/src/mainboard/iei/kino-780am2-fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/iei/kino-780am2-fam10/cmos.layout +++ b/src/mainboard/iei/kino-780am2-fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index d5c7033..825624e 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -21,7 +21,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 923a828..afd50c3 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "IEI ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "IEI ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1455,7 +1455,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1652,23 +1652,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1677,7 +1677,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 64274de..a761f74 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/iei/kino-780am2-fam10/resourcemap.c +++ b/src/mainboard/iei/kino-780am2-fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 21ddab3..79c6843 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -238,8 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/iei/nova4899r/cmos.layout b/src/mainboard/iei/nova4899r/cmos.layout index 67a3ce4..4c889ba 100644 --- a/src/mainboard/iei/nova4899r/cmos.layout +++ b/src/mainboard/iei/nova4899r/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/iei/nova4899r/devicetree.cb b/src/mainboard/iei/nova4899r/devicetree.cb index f27662e..53378c3 100644 --- a/src/mainboard/iei/nova4899r/devicetree.cb +++ b/src/mainboard/iei/nova4899r/devicetree.cb @@ -2,56 +2,56 @@ chip northbridge/amd/gx1 device domain 0 on device pci 0.0 on end chip southbridge/amd/cs5530 - device pci 0a.0 on end # ETH0 - device pci 0b.0 off end # ETH1 - device pci 0c.0 on end # ETH2 - device pci 0f.0 on end # PCI slot - device pci 12.0 on - chip superio/winbond/w83977tf - device pnp 2e.0 on # FDC - irq 0x70 = 6 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.4 off # Reserved - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 # Int 1 for PS/2 keyboard - irq 0x72 = 0x0c # Int 12 for PS/2 mouse - end - device pnp 2e.6 on # IR - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.7 on # GAME/MIDI/GPIO1 - io 0x60 = 0x290 - end - device pnp 2e.8 on # GPIO2 - io 0x60 = 0x110 - end - device pnp 2e.9 on # GPIO3 - io 0x60 = 0x120 - end - device pnp 2e.A on # Power Management - io 0x60 = 0xe800 - end - end - device pci 12.1 on end # SMI - device pci 12.2 on end # IDE - device pci 12.3 on end # Audio - device pci 12.4 on end # VGA onboard + device pci 0a.0 on end # ETH0 + device pci 0b.0 off end # ETH1 + device pci 0c.0 on end # ETH2 + device pci 0f.0 on end # PCI slot + device pci 12.0 on + chip superio/winbond/w83977tf + device pnp 2e.0 on # FDC + irq 0x70 = 6 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 off # Reserved + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 # Int 1 for PS/2 keyboard + irq 0x72 = 0x0c # Int 12 for PS/2 mouse + end + device pnp 2e.6 on # IR + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.7 on # GAME/MIDI/GPIO1 + io 0x60 = 0x290 + end + device pnp 2e.8 on # GPIO2 + io 0x60 = 0x110 + end + device pnp 2e.9 on # GPIO3 + io 0x60 = 0x120 + end + device pnp 2e.A on # Power Management + io 0x60 = 0xe800 + end + end + device pci 12.1 on end # SMI + device pci 12.2 on end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA onboard end device pci 13.0 on end # USB end diff --git a/src/mainboard/iei/nova4899r/irq_tables.c b/src/mainboard/iei/nova4899r/irq_tables.c index 785e0f3..bdde5e0 100644 --- a/src/mainboard/iei/nova4899r/irq_tables.c +++ b/src/mainboard/iei/nova4899r/irq_tables.c @@ -21,14 +21,14 @@ #include <arch/pirq_routing.h>
/* - * IRQ 5530 USB Network Network Network free + * IRQ 5530 USB Network Network Network free * controller northbridge device device#0 device#1 device#2 slot - * 00.13.0 00.0a.00 00.0b.00 00.0c.00 00.0f.00 + * 00.13.0 00.0a.00 00.0b.00 00.0c.00 00.0f.00 * ------------------------------------------------------------------------ - * 14 INTA# INTA# n.c. n.c. n.c. INTA# - * 5 INTB# n.c. n.c. n.c. INTA# n.c. - * 10 INTC# n.c. n.c. INTA# n.c. n.c. - * 11 INTD# n.c. INTA# n.c. n.c. n.c. + * 14 INTA# INTA# n.c. n.c. n.c. INTA# + * 5 INTB# n.c. n.c. n.c. INTA# n.c. + * 10 INTC# n.c. n.c. INTA# n.c. n.c. + * 11 INTD# n.c. INTA# n.c. n.c. n.c. */
/* diff --git a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c index 9396058..c558530 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ diff --git a/src/mainboard/iei/pm-lx-800-r11/devicetree.cb b/src/mainboard/iei/pm-lx-800-r11/devicetree.cb index 2bf4b7f..92de40a 100644 --- a/src/mainboard/iei/pm-lx-800-r11/devicetree.cb +++ b/src/mainboard/iei/pm-lx-800-r11/devicetree.cb @@ -32,7 +32,7 @@ chip northbridge/amd/lx register "enable_ide_nand_flash" = "0" register "enable_USBP4_device" = "0" # 0:host, 1:device register "enable_USBP4_overcurrent" = "0" - register "com1_enable" = "1" # CN10 (RS422/486 COM3) + register "com1_enable" = "1" # CN10 (RS422/486 COM3) register "com1_address" = "0x3e8" register "com1_irq" = "5" register "com2_enable" = "0" @@ -49,7 +49,7 @@ chip northbridge/amd/lx device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 7 - drq 0x74 = 3 + drq 0x74 = 3 end
device pnp 2e.2 on # COM1 @@ -72,7 +72,7 @@ chip northbridge/amd/lx device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 0 - end + end
device pnp 2e.6 off end # Serial Flash Interface device pnp 2e.7 off end # GPIO1, GPIO6, Game Port & MIDI Port diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl index a50c4b3..ec52284 100644 --- a/src/mainboard/intel/baskingridge/acpi/superio.asl +++ b/src/mainboard/intel/baskingridge/acpi/superio.asl @@ -19,17 +19,17 @@
/* Values should match those defined in devicetree.cb */
-#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
-#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 #define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index f4b74bc..9397080 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -253,7 +253,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; acpi_save_gnvs((unsigned long)gnvs); break; diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index e8a088d..0e4aab0 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -21,112 +21,112 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index a56562e..7783770 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -25,7 +25,7 @@ DefinitionBlock( "DSDT", 0x02, // DSDT revision: ACPI v2.0 "COREv4", // OEM id - "COREBOOT", // OEM table id + "COREBOOT", // OEM table id 0x20110725 // OEM revision ) { diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h index d271644..8df0ec6 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.h @@ -227,18 +227,18 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map mainboard_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 69943cb..4bca269 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -48,7 +48,7 @@ static int int15_handler(void) int res = 0;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f34: @@ -57,7 +57,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CX = 0x0001; @@ -114,13 +114,13 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h index 52f53e0..4b9cd9e 100644 --- a/src/mainboard/intel/baskingridge/onboard.h +++ b/src/mainboard/intel/baskingridge/onboard.h @@ -22,16 +22,16 @@
#include <arch/smp/mpspec.h>
-#define LUMPY_LIGHTSENSOR_NAME "lightsensor" +#define LUMPY_LIGHTSENSOR_NAME "lightsensor" #define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_GSI 20 -#define LUMPY_LIGHTSENSOR_IRQ 14 +#define LUMPY_LIGHTSENSOR_GSI 20 +#define LUMPY_LIGHTSENSOR_IRQ 14 #define LUMPY_LIGHTSENSOR_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
-#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_GSI 21 -#define LUMPY_TRACKPAD_IRQ 15 -#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) +#define LUMPY_TRACKPAD_NAME "trackpad" +#define LUMPY_TRACKPAD_I2C_ADDR 0x67 +#define LUMPY_TRACKPAD_GSI 21 +#define LUMPY_TRACKPAD_IRQ 15 +#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
#endif diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 8b18e6d..57b73d9 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -28,24 +28,24 @@
const struct rcba_config_instruction rcba_config[] = { /* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), + (INTB << D28IP_P4IP)), RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), diff --git a/src/mainboard/intel/d810e2cb/devicetree.cb b/src/mainboard/intel/d810e2cb/devicetree.cb index 8b67c5a..e7852fd 100644 --- a/src/mainboard/intel/d810e2cb/devicetree.cb +++ b/src/mainboard/intel/d810e2cb/devicetree.cb @@ -18,16 +18,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_FC_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FC_PGA370 # CPU + device lapic 0 on end # APIC end end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) + device domain 0 on # PCI domain + device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801bx # Southbridge + chip southbridge/intel/i82801bx # Southbridge register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x06" register "pirqc_routing" = "0x07" @@ -41,42 +41,42 @@ chip northbridge/intel/i82810 # Northbridge register "ide1_enable" = "1"
device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 off end # COM2 - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 off end # Game port - device pnp 4e.a on # Runtime registers - io 0x60 = 0x800 - end - device pnp 4e.b off end # MPU-401 - end + device pci 1f.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47M102) + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 off end # COM2 + device pnp 4e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 4e.9 off end # Game port + device pnp 4e.a on # Runtime registers + io 0x60 = 0x800 + end + device pnp 4e.b off end # MPU-401 + end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.4 on end # USB - device pci 1f.5 on end # Audio controller - device pci 1f.6 off end # Modem controller + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMbus + device pci 1f.4 on end # USB + device pci 1f.5 on end # Audio controller + device pci 1f.6 off end # Modem controller end end end diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c index a95fc9a..9aed98a 100644 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ b/src/mainboard/intel/d810e2cb/gpio.c @@ -19,7 +19,7 @@ */
#define PME_DEV PNP_DEV(0x4e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
/* Early mainboard specific GPIO setup. */ static void mb_gpio_init(void) diff --git a/src/mainboard/intel/d810e2cb/irq_tables.c b/src/mainboard/intel/d810e2cb/irq_tables.c index 107ba86..2665b0f 100644 --- a/src/mainboard/intel/d810e2cb/irq_tables.c +++ b/src/mainboard/intel/d810e2cb/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xd9, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 9997584..5028b76 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -21,118 +21,118 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused +416 512 s 0 boot_devices +#928 80 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index d389d8a..2e5b33f 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -19,20 +19,20 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_441 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_441 + device lapic 0 on end + end + end
- device domain 0 on - subsystemid 0x8086 0x464c inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x8086 0x464c inherit + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -49,41 +49,41 @@ chip northbridge/intel/i945 register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
- register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47m15x + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47m15x device pnp 2e.0 off # Floppy end device pnp 2e.3 off # Parport end - device pnp 2e.4 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.4 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 2e.7 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 @@ -98,12 +98,12 @@ chip northbridge/intel/i945 end device pnp 2e.b on # MPU end - end - end + end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/intel/d945gclf/irq_tables.c b/src/mainboard/intel/d945gclf/irq_tables.c index ce2a14a..612455c 100644 --- a/src/mainboard/intel/d945gclf/irq_tables.c +++ b/src/mainboard/intel/d945gclf/irq_tables.c @@ -21,10 +21,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -32,7 +32,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf, /* u8 checksum. */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c index b0360bf..f606374 100644 --- a/src/mainboard/intel/d945gclf/mptable.c +++ b/src/mainboard/intel/d945gclf/mptable.c @@ -27,14 +27,14 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 248aa3b..b88401f 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -211,7 +211,7 @@ void main(unsigned long bist) */ i945_early_initialization();
- /* Read PM1_CNT */ + /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { diff --git a/src/mainboard/intel/eagleheights/cmos.layout b/src/mainboard/intel/eagleheights/cmos.layout index ae6f942..c7670cc 100644 --- a/src/mainboard/intel/eagleheights/cmos.layout +++ b/src/mainboard/intel/eagleheights/cmos.layout @@ -23,108 +23,108 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 1 e 1 power_on_after_fail -#410 6 r 0 unused +408 1 e 1 nmi +409 1 e 1 power_on_after_fail +#410 6 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -#928 80 r 0 unused +416 512 s 0 boot_devices +#928 80 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c index e5795b6..18bf88a 100644 --- a/src/mainboard/intel/eagleheights/debug.c +++ b/src/mainboard/intel/eagleheights/debug.c @@ -24,111 +24,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static inline void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static inline void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -227,27 +227,27 @@ static inline void dump_pci_devices(void)
static inline void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -259,22 +259,22 @@ static inline void dump_spd_registers(void)
static inline void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { + for(i = 0; (i < 8) ; i++) { status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index b37750c..993f293 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -1,34 +1,34 @@ chip northbridge/intel/i3100 - device domain 0 on - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings + device domain 0 on + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings register "pirq_a_d" = "0x8b808a8a" - register "pirq_e_h" = "0x85808080" + register "pirq_e_h" = "0x85808080"
- device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 off end # PCIe port B1 - device pci 1c.2 off end # PCIe port B2 - device pci 1c.3 off end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end + device pci 1c.0 on end # PCIe port B0 + device pci 1c.1 off end # PCIe port B1 + device pci 1c.2 off end # PCIe port B2 + device pci 1c.3 off end # PCIe port B3 + device pci 1d.0 on end # USB (UHCI) 1 + device pci 1d.1 on end # USB (UHCI) 2 + device pci 1d.7 on end # USB (EHCI) + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end chip superio/smsc/smscsuperio device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -55,19 +55,19 @@ chip northbridge/intel/i3100 irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 2e.a off # Runtime registers - io 0x60 = 0x600 + io 0x60 = 0x600 end end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus device pci 1f.4 on end # Performance counters - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_BGA956 - device lapic 0 on end - end - end + end + end + device cpu_cluster 0 on + chip cpu/intel/socket_BGA956 + device lapic 0 on end + end + end end
diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl index cb9ec8e..ec3d422 100644 --- a/src/mainboard/intel/eagleheights/dsdt.asl +++ b/src/mainboard/intel/eagleheights/dsdt.asl @@ -269,8 +269,8 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) Name (CRS, ResourceTemplate () { Memory32Fixed (ReadOnly, - 0xE0000000, // Address Base - 0x10000000, // Address Length + 0xE0000000, // Address Base + 0x10000000, // Address Length _Y10) }) Method (_CRS, 0, NotSerialized) @@ -479,10 +479,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) Name (BFU1, ResourceTemplate () { IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length _Y03) IRQNoFlags (_Y04) {5} @@ -510,10 +510,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) StartDependentFnNoPri () { IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length ) IRQNoFlags () {5} @@ -521,10 +521,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) StartDependentFnNoPri () { IO (Decode16, - 0x02F8, // Range Minimum - 0x02F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x02F8, // Range Minimum + 0x02F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length ) IRQNoFlags () {9} @@ -591,10 +591,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) Name (BFU1, ResourceTemplate () { IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length _Y05) IRQNoFlags (_Y06) {9} @@ -622,10 +622,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) StartDependentFnNoPri () { IO (Decode16, - 0x03F8, // Range Minimum - 0x03F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length ) IRQNoFlags () {5} @@ -633,10 +633,10 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) StartDependentFnNoPri () { IO (Decode16, - 0x02F8, // Range Minimum - 0x02F8, // Range Maximum - 0x08, // Alignment - 0x08, // Length + 0x02F8, // Range Minimum + 0x02F8, // Range Maximum + 0x08, // Alignment + 0x08, // Length ) IRQNoFlags () {9} @@ -672,15 +672,15 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C) Field (_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve) { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8, + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8, Offset (0x08), - PIRE, 8, - PIRF, 8, - PIRG, 8, - PIRH, 8 + PIRE, 8, + PIRF, 8, + PIRG, 8, + PIRH, 8 }
Scope (_SB) diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c index c584c62..9d6153e 100644 --- a/src/mainboard/intel/eagleheights/fadt.c +++ b/src/mainboard/intel/eagleheights/fadt.c @@ -25,29 +25,29 @@ #include <arch/acpi.h> #include <cpu/x86/smm.h>
-#define ACPI_PM1_STS (pmbase + 0x00) -#define ACPI_PM1_EN (pmbase + 0x02) -#define ACPI_PM1_CNT (pmbase + 0x04) -#define ACPI_PM1_TMR (pmbase + 0x08) -#define ACPI_PROC_CNT (pmbase + 0x10) -#define ACPI_LV2 (pmbase + 0x14) -#define ACPI_GPE0_STS (pmbase + 0x28) -#define ACPI_GPE0_EN (pmbase + 0x2C) -#define ACPI_SMI_EN (pmbase + 0x30) -#define ACPI_SMI_STS (pmbase + 0x34) +#define ACPI_PM1_STS (pmbase + 0x00) +#define ACPI_PM1_EN (pmbase + 0x02) +#define ACPI_PM1_CNT (pmbase + 0x04) +#define ACPI_PM1_TMR (pmbase + 0x08) +#define ACPI_PROC_CNT (pmbase + 0x10) +#define ACPI_LV2 (pmbase + 0x14) +#define ACPI_GPE0_STS (pmbase + 0x28) +#define ACPI_GPE0_EN (pmbase + 0x2C) +#define ACPI_SMI_EN (pmbase + 0x30) +#define ACPI_SMI_STS (pmbase + 0x34) #define ACPI_ALT_GP_SMI_EN (pmbase + 0x38) #define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A) -#define ACPI_MON_SMI (pmbase + 0x40) -#define ACPI_DEVACT_STS (pmbase + 0x44) -#define ACPI_DEVTRAP_EN (pmbase + 0x48) +#define ACPI_MON_SMI (pmbase + 0x40) +#define ACPI_DEVACT_STS (pmbase + 0x44) +#define ACPI_DEVTRAP_EN (pmbase + 0x48) #define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C) #define ACPI_BUS_CYC_TRACK (pmbase + 0x4E)
#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS #define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT -#define ACPI_PM_TMR_BLK ACPI_PM1_TMR -#define ACPI_P_BLK ACPI_PROC_CNT -#define ACPI_GPE0_BLK ACPI_GPE0_STS +#define ACPI_PM_TMR_BLK ACPI_PM1_TMR +#define ACPI_P_BLK ACPI_PROC_CNT +#define ACPI_GPE0_BLK ACPI_GPE0_STS
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { diff --git a/src/mainboard/intel/eagleheights/irq_tables.c b/src/mainboard/intel/eagleheights/irq_tables.c index 3ad326f..976c61e 100644 --- a/src/mainboard/intel/eagleheights/irq_tables.c +++ b/src/mainboard/intel/eagleheights/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x4b, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, {0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..30e5512 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -60,7 +60,7 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; unsigned char bus_chipset, bus_pci; unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; @@ -76,11 +76,11 @@ static void *smp_write_config_table(void *v) } rcba = res->base;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
/* Get bus numbers */ bus_chipset = 0; @@ -125,7 +125,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa);
/* Internal PCI device for i3100 */ diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..07f3293 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -58,7 +58,7 @@ #define RCBA_HPTC 0x3404 /* 32 bit */ #define RCBA_GCS 0x3410 /* 32 bit */ #define RCBA_BUC 0x3414 /* 8 bit */ -#define RCBA_FD 0x3418 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ #define RCBA_PRC 0x341C /* 32 bit */
static inline int spd_read_byte(u16 device, u8 address) @@ -102,12 +102,12 @@ static void early_config(void) write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7));
/* Improve interrupt routing - * D31:F2 SATA INTB# -> PIRQD + * D31:F2 SATA INTB# -> PIRQD * D31:F3 SMBUS INTB# -> PIRQD - * D31:F4 CHAP INTD# -> PIRQA + * D31:F4 CHAP INTD# -> PIRQA * D29:F0 USB1#1 INTA# -> PIRQH * D29:F1 USB1#2 INTB# -> PIRQD - * D29:F7 USB2 INTA# -> PIRQH + * D29:F7 USB2 INTA# -> PIRQH * D28:F0 PCIe Port 1 INTA# -> PIRQE */
diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index a50c4b3..ec52284 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -19,17 +19,17 @@
/* Values should match those defined in devicetree.cb */
-#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
-#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 #define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/smsc/sio1007/acpi/superio.asl" diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 6e32779..d42c67f 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -245,7 +245,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/intel/emeraldlake2/ec.h b/src/mainboard/intel/emeraldlake2/ec.h index 94a9a89..0f64cb4 100644 --- a/src/mainboard/intel/emeraldlake2/ec.h +++ b/src/mainboard/intel/emeraldlake2/ec.h @@ -21,32 +21,32 @@ #define LUMPY_EC_H
/* Commands */ -#define EC_SMI_ENABLE 0x74 -#define EC_SMI_DISABLE 0x75 -#define EC_ACPI_ENABLE 0x76 /* Enter ACPI mode */ -#define EC_ACPI_DISABLE 0x77 /* Exit ACPI mode */ +#define EC_SMI_ENABLE 0x74 +#define EC_SMI_DISABLE 0x75 +#define EC_ACPI_ENABLE 0x76 /* Enter ACPI mode */ +#define EC_ACPI_DISABLE 0x77 /* Exit ACPI mode */
/* Commands with data */ -#define EC_AUX_PORT_MODE 0x64 /* PS/2 control mode */ +#define EC_AUX_PORT_MODE 0x64 /* PS/2 control mode */ #define EC_AUX_PORT_MODE_ENABLE 0x00 #define EC_AUX_PORT_MODE_DISABLE 0x01 -#define EC_POWER_BUTTON_MODE 0x63 +#define EC_POWER_BUTTON_MODE 0x63 #define EC_POWER_BUTTON_MODE_OS 0x00 /* OS control, 8 second override */ #define EC_POWER_BUTTON_MODE_EC 0x00 /* EC control */ -#define EC_BACKLIGHT_OFF 0x67 /* Turn Backlight Off */ -#define EC_BACKLIGHT_ON 0x68 /* Turn Backlight On */ -#define EC_BATTERY_MODE 0x13 -#define EC_BATTERY_MODE_NORMAL 0x00 /* Normal mode */ -#define EC_BATTERY_MODE_EXTEND 0x01 /* Battery Life Cycle Extension */ +#define EC_BACKLIGHT_OFF 0x67 /* Turn Backlight Off */ +#define EC_BACKLIGHT_ON 0x68 /* Turn Backlight On */ +#define EC_BATTERY_MODE 0x13 +#define EC_BATTERY_MODE_NORMAL 0x00 /* Normal mode */ +#define EC_BATTERY_MODE_EXTEND 0x01 /* Battery Life Cycle Extension */
/* EC RAM */ -#define EC_FAN_SPEED 0xca -#define EC_FAN_SPEED_LEVEL_0 0x01 /* Level 0 is fastest */ -#define EC_FAN_SPEED_LEVEL_1 0x02 /* Level 1 is fast */ -#define EC_FAN_SPEED_LEVEL_2 0x04 /* Level 2 is slow */ -#define EC_FAN_SPEED_LEVEL_3 0x08 /* Level 3 is slowest */ -#define EC_FAN_SPEED_LEVEL_4 0x10 /* Level 4 is off */ -#define EC_FAN_SPEED_FLAG_OS 0x80 /* OS control of fan speed */ +#define EC_FAN_SPEED 0xca +#define EC_FAN_SPEED_LEVEL_0 0x01 /* Level 0 is fastest */ +#define EC_FAN_SPEED_LEVEL_1 0x02 /* Level 1 is fast */ +#define EC_FAN_SPEED_LEVEL_2 0x04 /* Level 2 is slow */ +#define EC_FAN_SPEED_LEVEL_3 0x08 /* Level 3 is slowest */ +#define EC_FAN_SPEED_LEVEL_4 0x10 /* Level 4 is off */ +#define EC_FAN_SPEED_FLAG_OS 0x80 /* OS control of fan speed */
extern void lumpy_ec_init(void);
diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h index 05b9164..be558aa 100644 --- a/src/mainboard/intel/emeraldlake2/gpio.h +++ b/src/mainboard/intel/emeraldlake2/gpio.h @@ -23,35 +23,35 @@ #include "southbridge/intel/bd82x6x/gpio.h"
const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, - .gpio1 = GPIO_MODE_GPIO, - .gpio3 = GPIO_MODE_GPIO, - .gpio5 = GPIO_MODE_GPIO, - .gpio6 = GPIO_MODE_GPIO, - .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_GPIO, - .gpio12 = GPIO_MODE_GPIO, - .gpio15 = GPIO_MODE_GPIO, - .gpio21 = GPIO_MODE_GPIO, + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, .gpio22 = GPIO_MODE_GPIO, - .gpio24 = GPIO_MODE_GPIO, - .gpio27 = GPIO_MODE_GPIO, - .gpio28 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, };
const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, .gpio22 = GPIO_DIR_INPUT, - .gpio27 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, };
const struct pch_gpio_set1 pch_gpio_set1_level = { @@ -61,15 +61,15 @@ const struct pch_gpio_set1 pch_gpio_set1_invert = { };
const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, .gpio48 = GPIO_MODE_GPIO, - .gpio57 = GPIO_MODE_GPIO, - .gpio60 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, };
const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio48 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, };
const struct pch_gpio_set2 pch_gpio_set2_level = { @@ -86,18 +86,18 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map emeraldlake2_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5f7d224..cb441e5 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -57,7 +57,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; @@ -131,7 +131,7 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h index 52f53e0..4b9cd9e 100644 --- a/src/mainboard/intel/emeraldlake2/onboard.h +++ b/src/mainboard/intel/emeraldlake2/onboard.h @@ -22,16 +22,16 @@
#include <arch/smp/mpspec.h>
-#define LUMPY_LIGHTSENSOR_NAME "lightsensor" +#define LUMPY_LIGHTSENSOR_NAME "lightsensor" #define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_GSI 20 -#define LUMPY_LIGHTSENSOR_IRQ 14 +#define LUMPY_LIGHTSENSOR_GSI 20 +#define LUMPY_LIGHTSENSOR_IRQ 14 #define LUMPY_LIGHTSENSOR_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
-#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_GSI 21 -#define LUMPY_TRACKPAD_IRQ 15 -#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW) +#define LUMPY_TRACKPAD_NAME "trackpad" +#define LUMPY_TRACKPAD_I2C_ADDR 0x67 +#define LUMPY_TRACKPAD_GSI 21 +#define LUMPY_TRACKPAD_IRQ 15 +#define LUMPY_TRACKPAD_IRQ_MODE (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
#endif diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index f116668..77eff53 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -73,15 +73,15 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ @@ -196,15 +196,15 @@ void main(unsigned long bist) max_ddr3_freq: 1600, usb_port_config: { { 1, 0, 0x0040 }, /* P0: Front port (OC0) */ - { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0040 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ - { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ diff --git a/src/mainboard/intel/jarrell/cmos.layout b/src/mainboard/intel/jarrell/cmos.layout index 1f225f8..9b6bc25 100644 --- a/src/mainboard/intel/jarrell/cmos.layout +++ b/src/mainboard/intel/jarrell/cmos.layout @@ -1,77 +1,77 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 376 r 0 reserved_memory -376 1 e 1 power_up_watchdog -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -397 1 e 1 pxhd_bus_speed_100 -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 376 r 0 reserved_memory +376 1 e 1 power_up_watchdog +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +397 1 e 1 pxhd_bus_speed_100 +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/intel/jarrell/debug.c b/src/mainboard/intel/jarrell/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/intel/jarrell/debug.c +++ b/src/mainboard/intel/jarrell/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/intel/jarrell/irq_tables.c b/src/mainboard/intel/jarrell/irq_tables.c index 6e88d48..b3c899a 100644 --- a/src/mainboard/intel/jarrell/irq_tables.c +++ b/src/mainboard/intel/jarrell/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x24d0, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x38, /* u8 checksum - mod 256 checksum must give zero */ + 0x38, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, 0x08, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c index 9a57746..bed3912 100644 --- a/src/mainboard/intel/jarrell/jarrell_fixups.c +++ b/src/mainboard/intel/jarrell/jarrell_fixups.c @@ -2,32 +2,32 @@
static void mch_reset(void) { - device_t dev; - unsigned long value, base; - dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0); - if (dev != PCI_DEV_INVALID) { - /* I/O space is always enables */ + device_t dev; + unsigned long value, base; + dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0); + if (dev != PCI_DEV_INVALID) { + /* I/O space is always enables */
- /* Set gpio base */ - pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); - base = ICH5_GPIOBASE; + /* Set gpio base */ + pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1); + base = ICH5_GPIOBASE;
- /* Enable GPIO Bar */ - value = pci_read_config32(dev, 0x5c); - value |= 0x10; - pci_write_config32(dev, 0x5c, value); + /* Enable GPIO Bar */ + value = pci_read_config32(dev, 0x5c); + value |= 0x10; + pci_write_config32(dev, 0x5c, value);
/* Set GPIO 19 mux to IO usage */ value = inl(base); value |= (1 <<19); outl(value, base);
- /* Pull GPIO 19 low */ - value = inl(base + 0x0c); - value &= ~(1 << 19); - outl(value, base + 0x0c); - } - return; + /* Pull GPIO 19 low */ + value = inl(base + 0x0c); + value &= ~(1 << 19); + outl(value, base + 0x0c); + } + return; }
static void mainboard_set_e7520_pll(unsigned bits) diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 6662329..f96db42 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) } /* test for active riser with 2nd pxh device */ dev = dev_find_slot(0, PCI_DEVFN(0x06,0)); - if (dev) { + if (dev) { bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); if(bus_pxhd_id == 0x35998086) { bus_pxhd_x = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -69,15 +69,15 @@ static void *smp_write_config_table(void *v) if (dev) { bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); if(bus_pxhd_id == 0x03298086) { - bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS); } } /* pxhd-4 */ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_id = pci_read_config32(dev, PCI_VENDOR_ID); - if(bus_pxhd_id == 0x032a8086) { - bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(bus_pxhd_id == 0x032a8086) { + bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS); } } } @@ -195,13 +195,13 @@ static void *smp_write_config_table(void *v) /* PCI Slot 3 (if active riser) */ if(bus_pxhd_3) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pxhd_3, (1<<2)|0, 0xb, 0x0); + bus_pxhd_3, (1<<2)|0, 0xb, 0x0); }
/* PCI Slot 4 (if active riser) */ if(bus_pxhd_4) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pxhd_4, (1<<2)|0, 0xc, 0x0); + bus_pxhd_4, (1<<2)|0, 0xc, 0x0); }
/* Onboard SCSI 0 */ diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index c6f014c..8f3a49b 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -59,9 +59,9 @@ static void main(unsigned long bist) pc87427_disable_dev(CONSOLE_SERIAL_DEV); pc87427_disable_dev(HIDDEN_SERIAL_DEV); pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); - /* Enable Serial 2 lines instead of GPIO */ - outb(0x2c, 0x2e); - outb((inb(0x2f) & (~1<<1)), 0x2f); + /* Enable Serial 2 lines instead of GPIO */ + outb(0x2c, 0x2e); + outb((inb(0x2f) & (~1<<1)), 0x2f); console_init();
/* Halt if there was a built in self test failure */ @@ -74,12 +74,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) - die("Missing ich5?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) + die("Missing ich5?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 print_pci_devices(); diff --git a/src/mainboard/intel/mtarvon/devicetree.cb b/src/mainboard/intel/mtarvon/devicetree.cb index c1ff1d5..3a1e96d 100644 --- a/src/mainboard/intel/mtarvon/devicetree.cb +++ b/src/mainboard/intel/mtarvon/devicetree.cb @@ -1,45 +1,45 @@ chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" + device domain 0 on + subsystemid 0x8086 0x2680 inherit + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080"
- device pci 1c.0 on end # PCIe port B0 - device pci 1c.1 on end # PCIe port B1 - device pci 1c.2 on end # PCIe port B2 - device pci 1c.3 on end # PCIe port B3 - device pci 1d.0 on end # USB (UHCI) 1 - device pci 1d.1 on end # USB (UHCI) 2 - device pci 1d.7 on end # USB (EHCI) - device pci 1e.0 on end # PCI bridge - device pci 1e.2 on end # audio - device pci 1e.3 on end # modem - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - end - end - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA479M - device lapic 0 on end - end - end + device pci 1c.0 on end # PCIe port B0 + device pci 1c.1 on end # PCIe port B1 + device pci 1c.2 on end # PCIe port B2 + device pci 1c.3 on end # PCIe port B3 + device pci 1d.0 on end # USB (UHCI) 1 + device pci 1d.1 on end # USB (UHCI) 2 + device pci 1d.7 on end # USB (EHCI) + device pci 1e.0 on end # PCI bridge + device pci 1e.2 on end # audio + device pci 1e.3 on end # modem + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + end + end + device cpu_cluster 0 on + chip cpu/intel/socket_mPGA479M + device lapic 0 on end + end + end end diff --git a/src/mainboard/intel/mtarvon/irq_tables.c b/src/mainboard/intel/mtarvon/irq_tables.c index 424f4f3..50af61e 100644 --- a/src/mainboard/intel/mtarvon/irq_tables.c +++ b/src/mainboard/intel/mtarvon/irq_tables.c @@ -22,16 +22,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ + 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x2670, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x49, /* u8 checksum - mod 256 checksum must give zero */ + 0x49, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, } diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb index 05fb05e..6230ca3 100644 --- a/src/mainboard/intel/truxton/devicetree.cb +++ b/src/mainboard/intel/truxton/devicetree.cb @@ -1,32 +1,32 @@ chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - device pci 04.0 on end # ? - device pci 08.0 off end # must be off to boot - device pci 0d.0 off end # must be off to boot - device pci 0d.1 off end # must be off to boot - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" + device domain 0 on + subsystemid 0x8086 0x2680 inherit + device pci 00.0 on end # IMCH + device pci 00.1 on end # IMCH error status + device pci 01.0 on end # IMCH EDMA engine + device pci 02.0 on end # PCIe port A/A0 + device pci 03.0 on end # PCIe port A1 + device pci 04.0 on end # ? + device pci 08.0 off end # must be off to boot + device pci 0d.0 off end # must be off to boot + device pci 0d.1 off end # must be off to boot + chip southbridge/intel/i3100 + # PIRQ line -> legacy IRQ mappings + register "pirq_a_d" = "0x0b070a05" + register "pirq_e_h" = "0x0a808080"
- device pci 1d.0 on end # USB (UHCI) - device pci 1d.7 on end # USB (EHCI) - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pci 1d.0 on end # USB (UHCI) + device pci 1d.7 on end # USB (EHCI) + device pci 1f.0 on # LPC bridge + chip superio/intel/i3100 + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end end chip superio/smsc/smscsuperio device pnp 2e.0 off end @@ -34,22 +34,22 @@ chip northbridge/intel/i3100 device pnp 2e.4 off end device pnp 2e.5 off end device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt end device pnp 2e.a off end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # ? - end - end - device cpu_cluster 0 on - chip cpu/intel/ep80579 - device lapic 0 on end - end - end + end + end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + device pci 1f.4 on end # ? + end + end + device cpu_cluster 0 on + chip cpu/intel/ep80579 + device lapic 0 on end + end + end end diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c index 9c5ca41..e857f22 100644 --- a/src/mainboard/intel/truxton/irq_tables.c +++ b/src/mainboard/intel/truxton/irq_tables.c @@ -22,16 +22,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ + 0x00, /* u8 Bus 0 */ (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x5031, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum - mod 256 checksum must give zero */ + 0x5e, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, } diff --git a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl index a8b6b5f..168dfb8 100644 --- a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl +++ b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl @@ -42,12 +42,12 @@ Method(_PRT) Package() { 0x001fffff, 1, 0, 22 }, Package() { 0x001fffff, 2, 0, 23 }, Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 + // Serial IO 0:15.0 Package() { 0x0015ffff, 0, 0, 16 }, Package() { 0x0015ffff, 1, 0, 17 }, Package() { 0x0015ffff, 2, 0, 18 }, Package() { 0x0015ffff, 3, 0, 19 }, - // SDIO 0:17.0 + // SDIO 0:17.0 Package() { 0x0017ffff, 0, 0, 16 }, }) } Else { diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 357e710..2acd6f2 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -250,7 +250,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> %p\n", i, gnvs); + "DSDT at offset 0x%04x -> %p\n", i, gnvs); *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; acpi_save_gnvs((unsigned long)gnvs); break; diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index afdd3c6..d091d35 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h index 884fd66..0b8c919 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.h @@ -23,101 +23,101 @@ #include "southbridge/intel/lynxpoint/lp_gpio.h"
static const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ - LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ - LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ - LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ - LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ - LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ - LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ - LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ - LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ - LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ - LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ - LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ - LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ - LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ - LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ - LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ - LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ - LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ - LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ - LP_GPIO_INPUT, /* 19: EC_IN_RW */ - LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ - LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ - LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ - LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ - LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ - LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ - LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ - LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ - LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ - LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ - LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ - LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ - LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ - LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ - LP_GPIO_INPUT, /* 34: ESATA_DET_N */ - LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ - LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ - LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ - LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ - LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ - LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ - LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ - LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ - LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ - LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ - LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ - LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ - LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ - LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ - LP_GPIO_INPUT, /* 49: COMBO_JD */ - LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ - LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ - LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ - LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ - LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ - LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ - LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ - LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ - LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ - LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ - LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ - LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ - LP_GPIO_NATIVE, /* 62: SUS_CK */ - LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ - LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ - LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ - LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ - LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ - LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ - LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ - LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ - LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ - LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ - LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ - LP_GPIO_NATIVE, /* 74: SML1_DATA */ - LP_GPIO_NATIVE, /* 75: SML1_CK */ - LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ - LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ - LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ - LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ - LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ - LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ - LP_GPIO_NATIVE, /* 82: H_RCIN_N */ - LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ - LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ - LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ - LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ - LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ - LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ - LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ - LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ - LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ - LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ - LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ - LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ + LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ + LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ + LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ + LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ + LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ + LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ + LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ + LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ + LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ + LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ + LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ + LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ + LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ + LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ + LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ + LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ + LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ + LP_GPIO_INPUT, /* 19: EC_IN_RW */ + LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ + LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ + LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ + LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ + LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ + LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ + LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ + LP_GPIO_INPUT, /* 34: ESATA_DET_N */ + LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ + LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ + LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ + LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ + LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ + LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ + LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ + LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ + LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ + LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ + LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ + LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ + LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ + LP_GPIO_INPUT, /* 49: COMBO_JD */ + LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ + LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ + LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ + LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ + LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ + LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ + LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ + LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ + LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ + LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ + LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ + LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + LP_GPIO_NATIVE, /* 62: SUS_CK */ + LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ + LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ + LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ + LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ + LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ + LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ + LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ + LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ + LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ + LP_GPIO_NATIVE, /* 74: SML1_DATA */ + LP_GPIO_NATIVE, /* 75: SML1_CK */ + LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ + LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ + LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ + LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ + LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ + LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + LP_GPIO_NATIVE, /* 82: H_RCIN_N */ + LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ + LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ + LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ + LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ + LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ + LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ + LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ + LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ + LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ + LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ + LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ + LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ LP_GPIO_END };
diff --git a/src/mainboard/intel/wtm2/i915.c b/src/mainboard/intel/wtm2/i915.c index df88138..71a78c8 100644 --- a/src/mainboard/intel/wtm2/i915.c +++ b/src/mainboard/intel/wtm2/i915.c @@ -177,9 +177,9 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, physbase = pphysbase; graphics = pgfx; printk(BIOS_SPEW, - "i915lightup: graphics %p mmio %p" - "addrport %04x physbase %08x\n", - (void *)graphics, mmio, addrport, physbase); + "i915lightup: graphics %p mmio %p" + "addrport %04x physbase %08x\n", + (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll();
/* turn it on. The VBIOS does it this way, so we hope that's ok. */ @@ -192,7 +192,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, * and set the global translation table (GTT) */ printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff, - FRAME_BUFFER_BYTES/sizeof(u32)); + FRAME_BUFFER_BYTES/sizeof(u32)); for(l = (u32 *)graphics, i = 0; i < FRAME_BUFFER_BYTES/sizeof(u32); i++){ l[i] = 0x1122ff; diff --git a/src/mainboard/intel/wtm2/intel_dp.c b/src/mainboard/intel/wtm2/intel_dp.c index e7222a3..c41dc35 100644 --- a/src/mainboard/intel/wtm2/intel_dp.c +++ b/src/mainboard/intel/wtm2/intel_dp.c @@ -124,7 +124,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) + DP_AUX_CH_CTL_RECEIVE_ERROR)) continue; if (status & DP_AUX_CH_CTL_DONE) break; @@ -155,7 +155,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
/* Unload any bytes sent back from the other side */ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); if (recv_bytes > recv_size) recv_bytes = recv_size;
diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index e7650fa..1d3e372 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -48,7 +48,7 @@ static int int15_handler(void) int res = 1;
printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f34: @@ -57,7 +57,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CX = 0x0001; @@ -114,13 +114,13 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index f38389c..d789dbd 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -30,15 +30,15 @@ const struct rcba_config_instruction rcba_config[] = {
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD * D20IP_XHCI XHCI INTA -> PIRQA - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c index b3c20ba..3c9c836 100644 --- a/src/mainboard/intel/xe7501devkit/acpi_tables.c +++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c @@ -103,7 +103,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_madt_t *madt;
/* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); + start = ALIGN(start, 16); current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout index 322f1c9..6c25e4d 100644 --- a/src/mainboard/intel/xe7501devkit/cmos.layout +++ b/src/mainboard/intel/xe7501devkit/cmos.layout @@ -1,50 +1,50 @@ entries
#start-bit length config config-ID name -0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS -512 512 r 0 reserved_memory2 # More factory BIOS +0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS +512 512 r 0 reserved_memory2 # More factory BIOS
# Work in progress. # This is where we would put the LB RTC_BOOT_BYTE options once the code # supports finding them there. -#1024 1 e 4 boot_option -#1025 1 e 4 last_boot -#1026 1 e 1 ECC_memory -#1028 4 r 0 reboot_bits +#1024 1 e 4 boot_option +#1025 1 e 4 last_boot +#1026 1 e 1 ECC_memory +#1028 4 r 0 reboot_bits
# Options used by XE7501DevKit -#1032 3 e 5 baud_rate -#1035 1 e 2 hyper_threading -#1036 1 e 1 power_on_after_fail -#1037 1 e 1 nmi +#1032 3 e 5 baud_rate +#1035 1 e 2 hyper_threading +#1036 1 e 1 power_on_after_fail +#1037 1 e 1 nmi
-#1040 4 e 6 debug_level +#1040 4 e 6 debug_level
-#1048 16 h 0 check_sum +#1048 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew
checksums
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c index 7af7a9f..99c7424 100644 --- a/src/mainboard/intel/xe7501devkit/irq_tables.c +++ b/src/mainboard/intel/xe7501devkit/irq_tables.c @@ -28,7 +28,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router 0, // Additional miniport information { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero - 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) + 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0) { // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space // This was determined from linux-2.6.11/arch/x86/pci/irq.c @@ -36,11 +36,11 @@ static const struct irq_routing_table intel_irq_routing_table = { // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
- // INTA# INTB# INTC# INTD# + // INTA# INTB# INTC# INTD# // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
- {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus - {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1 + {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus + {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
// P64H2#2 Bus A {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI @@ -63,7 +63,7 @@ static const struct irq_routing_table intel_irq_routing_table = { // NOTE: Hotplug disabled on this bus
// ICH-3 PCI bus - {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video + {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11) } }; diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index cc7eda5..22875c4 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -69,39 +69,39 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
// P64H2#2 Bus B - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
// P64H2#2 Bus A smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
// P64H2#1 Bus B - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
// P64H2#1 Bus A - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20) - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
// ICH-3
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 342e6f1..4f21381 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -20,7 +20,7 @@
static void hard_reset(void) { - outb(0x0e, 0x0cf9); + outb(0x0e, 0x0cf9); }
static inline int spd_read_byte(unsigned device, unsigned address) diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c index 8095ab0..3713304 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c @@ -62,7 +62,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* IOAPIC */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + 2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) @@ -76,7 +76,7 @@ unsigned long acpi_fill_madt(unsigned long current) }
unsigned long acpi_fill_ssdt_generator(unsigned long current, - const char *oem_table_id) + const char *oem_table_id) { generate_cpu_entries(); return (unsigned long)(acpigen_get_current()); @@ -185,8 +185,8 @@ unsigned long write_acpi_tables(unsigned long start) for (i = 0; i < dsdt->length; i++) { if (*(u32 *) (((u32) dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", - i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", + i, current); *(u32 *) (((u32) dsdt) + i) = current; // 0x92 bytes break; } @@ -206,7 +206,7 @@ unsigned long write_acpi_tables(unsigned long start) dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, - dsdt->length); + dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC printk(BIOS_DEBUG, "ACPI: * SLIC\n"); diff --git a/src/mainboard/iwave/iWRainbowG6/cmos.layout b/src/mainboard/iwave/iWRainbowG6/cmos.layout index ce98ffd..a1332b7 100644 --- a/src/mainboard/iwave/iWRainbowG6/cmos.layout +++ b/src/mainboard/iwave/iWRainbowG6/cmos.layout @@ -23,124 +23,124 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -#928 40 r 0 unused +416 512 s 0 boot_devices +#928 40 r 0 unused
-968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3
-#971 13 r 0 unused +#971 13 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/iwave/iWRainbowG6/fadt.c b/src/mainboard/iwave/iWRainbowG6/fadt.c index 8111672..a4a2292 100644 --- a/src/mainboard/iwave/iWRainbowG6/fadt.c +++ b/src/mainboard/iwave/iWRainbowG6/fadt.c @@ -26,7 +26,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), - 0x40) & 0xfffe; + 0x40) & 0xfffe;
memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); diff --git a/src/mainboard/iwave/iWRainbowG6/irq_tables.c b/src/mainboard/iwave/iWRainbowG6/irq_tables.c index 940ff52..745e8a4 100644 --- a/src/mainboard/iwave/iWRainbowG6/irq_tables.c +++ b/src/mainboard/iwave/iWRainbowG6/irq_tables.c @@ -20,22 +20,22 @@ #include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x8119, /* Device*/ - 0, /* Miniport */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x8119, /* Device*/ + 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ + 0xdf, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 39fce07..8512cb3 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -133,7 +133,7 @@ void transaction1(unsigned char dev_addr) printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp); //sch_SMbus_regs (); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); if (temp > 0) break; } while (1); @@ -149,7 +149,7 @@ void transaction1(unsigned char dev_addr) } sch_SMbus_regs(); printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n", - inb(SMBusBase + SMBHSTCMD)); + inb(SMBusBase + SMBHSTCMD)); }
void transaction2(unsigned char dev_addr) @@ -182,7 +182,7 @@ void transaction2(unsigned char dev_addr) printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp); //sch_SMbus_regs (); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); if (temp > 0) break; } while (1); @@ -199,7 +199,7 @@ void transaction2(unsigned char dev_addr) sch_SMbus_regs();
printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n", - inb(SMBusBase + SMBHSTCMD)); + inb(SMBusBase + SMBHSTCMD)); }
void transaction3(unsigned char dev_addr) @@ -229,7 +229,7 @@ void transaction3(unsigned char dev_addr) do { temp = inb(SMBusBase + SMBHSTSTS); printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", - inb(SMBusBase + SMBHSTSTS)); + inb(SMBusBase + SMBHSTSTS)); //sch_SMbus_regs (); if (temp > 0) break; @@ -255,7 +255,7 @@ void transaction3(unsigned char dev_addr) printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1)); for (index = 0; index < length; index++) printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index, - inb(SMBusBase + SMBHSTDATB + index)); + inb(SMBusBase + SMBHSTDATB + index)); }
int selectcard(void) @@ -302,7 +302,7 @@ static void sch_shadow_CMC(void) reg32 = cpuid_eax(0x80000008); printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF)); printk(BIOS_INFO, "Virtual Address size: %d.\n", - ((reg32 & 0xFF00) >> 8)); + ((reg32 & 0xFF00) >> 8)); sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000); printk(BIOS_DEBUG, "1 "); sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32); diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl index 38aaea1..727c6ed 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111.asl @@ -2,171 +2,171 @@ * Copyright 2005 AMD */ //AMD8111 - Name (APIC, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} - }) - - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00}, - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00}, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00}, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00} - }) + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11}, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12}, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13} + }) + + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00}, + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00}, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00}, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00} + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { + Method (_PRT, 0, NotSerialized) + { If (LEqual (^DNCG, Ones)) { Store (DADD(_SB.PCI0.SBDN, 0x0001ffff), Local0) // Update the Device Number according to SBDN - Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) - Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0)) + Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
Store (0x00, ^DNCG)
}
- If (LNot (PICF)) { + If (LNot (PICF)) { Return (PICM) } - Else { + Else { Return (APIC) } - } + }
- Device (SBC3) - { - /* acpi smbus it should be 0x00040003 if 8131 present */ + Device (SBC3) + { + /* acpi smbus it should be 0x00040003 if 8131 present */ Method (_ADR, 0, NotSerialized) { Return (DADD(_SB.PCI0.SBDN, 0x00010003)) } - OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) - Field (PIRQ, ByteAcc, Lock, Preserve) - { - PIBA, 8, - PIDC, 8 - } + OperationRegion (PIRQ, PCI_Config, 0x56, 0x02) + Field (PIRQ, ByteAcc, Lock, Preserve) + { + PIBA, 8, + PIDC, 8 + } /* - OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) - Field (TS3_, DWordAcc, NoLock, Preserve) - { - PTS3, 16 - } + OperationRegion (TS3_, PCI_Config, 0xC4, 0x02) + Field (TS3_, DWordAcc, NoLock, Preserve) + { + PTS3, 16 + } */ - } - - Device (HPET) - { - Name (HPT, 0x00) - Name (_HID, EisaId ("PNP0103")) - Name (_UID, 0x00) - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) - }) - Return (BUF0) - } - } + } + + Device (HPET) + { + Name (HPT, 0x00) + Name (_HID, EisaId ("PNP0103")) + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400) + }) + Return (BUF0) + } + }
#include "amd8111_pic.asl"
#include "amd8111_isa.asl"
- Device (TP2P) - { - /* 8111 P2P and it should 0x00030000 when 8131 present*/ - Method (_ADR, 0, NotSerialized) - { + Device (TP2P) + { + /* 8111 P2P and it should 0x00030000 when 8131 present*/ + Method (_ADR, 0, NotSerialized) + { Return (DADD(_SB.PCI0.SBDN, 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } - Else { Return (Package (0x02) { 0x08, 0x01 }) } - } - - Device (USB0) - { - Name (_ADR, 0x00000000) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Device (USB1) - { - Name (_ADR, 0x00000001) - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } - Else { Return (Package (0x02) { 0x0F, 0x01 }) } - } - } - - Name (APIC, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, - - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } - }) - - Name (PICM, Package (0x0C) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //USB - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //Slot 6 - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - - Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, //Slot 5 - Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } - }) - - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) } + Else { Return (Package (0x02) { 0x08, 0x01 }) } + } + + Device (USB0) + { + Name (_ADR, 0x00000000) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Device (USB1) + { + Name (_ADR, 0x00000001) + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) } + Else { Return (Package (0x02) { 0x0F, 0x01 }) } + } + } + + Name (APIC, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 }, + + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 } + }) + + Name (PICM, Package (0x0C) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //USB + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, //Slot 6 + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + + Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, //Slot 5 + Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } + }) + + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl index 56c0a16..883bfd8 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl @@ -6,174 +6,174 @@ */ //AMD8111 isa
- Device (ISA) - { - /* lpc 0x00040000 */ - Method (_ADR, 0, NotSerialized) - { + Device (ISA) + { + /* lpc 0x00040000 */ + Method (_ADR, 0, NotSerialized) + { Return (DADD(_SB.PCI0.SBDN, 0x00010000)) - } - - OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers - Field (PIRY, ByteAcc, NoLock, Preserve) - { - Z000, 2, // Parallel Port Range - , 1, - ECP, 1, // ECP Enable - FDC1, 1, // Floppy Drive Controller 1 - FDC2, 1, // Floppy Drive Controller 2 - Offset (0x01), - Z001, 3, // Serial Port A Range - SAEN, 1, // Serial Post A Enabled - Z002, 3, // Serial Port B Range - SBEN, 1 // Serial Post B Enabled - } - - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) - IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) - IRQ (Edge, ActiveHigh, Exclusive) {2} - }) - } - - Device (DMA1) - { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) - IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) - IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) - DMA (Compatibility, NotBusMaster, Transfer16) {4} - }) - } - - Device (TMR) - { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) - IRQ (Edge, ActiveHigh, Exclusive) {0} - }) - } - - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) - IRQ (Edge, ActiveHigh, Exclusive) {8} - }) - } - - Device (SPKR) - { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) - }) - } - - Device (COPR) - { - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) - IRQ (Edge, ActiveHigh, Exclusive) {13} - }) - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x00) - Name (SYR1, ResourceTemplate () - { - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM - IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) - IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) - IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) - IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) - IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error - }) - Method (_CRS, 0, NotSerialized) - { - Return (SYR1) - } - } - - Device (MEM) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF - Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 - Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM - Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) - Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS - }) + } + + OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers + Field (PIRY, ByteAcc, NoLock, Preserve) + { + Z000, 2, // Parallel Port Range + , 1, + ECP, 1, // ECP Enable + FDC1, 1, // Floppy Drive Controller 1 + FDC2, 1, // Floppy Drive Controller 2 + Offset (0x01), + Z001, 3, // Serial Port A Range + SAEN, 1, // Serial Post A Enabled + Z002, 3, // Serial Port B Range + SBEN, 1 // Serial Post B Enabled + } + + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) + IRQ (Edge, ActiveHigh, Exclusive) {2} + }) + } + + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer16) {4} + }) + } + + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) + IRQ (Edge, ActiveHigh, Exclusive) {0} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0070, 0x0070, 0x01, 0x06) + IRQ (Edge, ActiveHigh, Exclusive) {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) + }) + } + + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) + IRQ (Edge, ActiveHigh, Exclusive) {13} + }) + } + + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x00) + Name (SYR1, ResourceTemplate () + { + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM + IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B) + IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A) + IO (Decode16, 0x0090, 0x0090, 0x01, 0x10) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10) + IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error + }) + Method (_CRS, 0, NotSerialized) + { + Return (SYR1) + } + } + + Device (MEM) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF + Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404 + Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000) + Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM + Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000) + Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS + }) // Read the Video Memory length - CreateDWordField (BUF0, 0x14, CLEN) - CreateDWordField (BUF0, 0x10, CBAS) - - ShiftLeft (VGA1, 0x09, Local0) - Store (Local0, CLEN) - - Return (BUF0) - } - } - - Device (PS2M) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQNoFlags () {12} - }) - Method (_STA, 0, NotSerialized) - { - And (FLG0, 0x04, Local0) - If (LEqual (Local0, 0x04)) { Return (0x0F) } - Else { Return (0x00) } - } - } - - Device (PS2K) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - } + CreateDWordField (BUF0, 0x14, CLEN) + CreateDWordField (BUF0, 0x10, CBAS) + + ShiftLeft (VGA1, 0x09, Local0) + Store (Local0, CLEN) + + Return (BUF0) + } + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) + { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { Return (0x0F) } + Else { Return (0x00) } + } + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } #include "superio.asl"
- } + }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl index 228f3f8..5ad094a 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_pic.asl @@ -3,358 +3,358 @@ */ //AMD8111 pic LNKA B C D
- Device (LNKA) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x01) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled - Else { Return (0x0B) } //Enabled - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { // Routing enable - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) - Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKB) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) - ShiftLeft (Local1, 0x04, Local1) - Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) - } - } - - Device (LNKC) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x03) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFA) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFA, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFA, 0x01, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } - - Return (BUFA) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRA1) - CreateByteField (Arg0, 0x02, IRA2) - ShiftLeft (IRA2, 0x08, Local0) - Or (Local0, IRA1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) - Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) - } - } - - Device (LNKD) - { - Name (_HID, EisaId ("PNP0C0F")) - Name (_UID, 0x04) - Method (_STA, 0, NotSerialized) - { - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local0) - If (LEqual (Local0, 0x00)) { Return (0x09) } - Else { Return (0x0B) } - } - - Method (_PRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {3,5,10,11} - }) - Return (BUFB) - } - - Method (_DIS, 0, NotSerialized) - { - Store (0x01, Local3) - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - Store (Local1, Local2) - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local1) - } - - ShiftLeft (Local3, Local1, Local3) - Not (Local3, Local3) - And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUFB, ResourceTemplate () - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateByteField (BUFB, 0x01, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNot (LEqual (Local1, 0x00))) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } - - Return (BUFB) - } - - Method (_SRS, 1, NotSerialized) - { - CreateByteField (Arg0, 0x01, IRB1) - CreateByteField (Arg0, 0x02, IRB2) - ShiftLeft (IRB2, 0x08, Local0) - Or (Local0, IRB1, Local0) - Store (0x00, Local1) - ShiftRight (Local0, 0x01, Local0) - While (LGreater (Local0, 0x00)) - { - Increment (Local1) - ShiftRight (Local0, 0x01, Local0) - } - - And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) - ShiftLeft (Local1, 0x04, Local1) - Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) - } - } + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x01) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled + Else { Return (0x0B) } //Enabled + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIBA, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { // Routing enable + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIBA, 0xF0, _SB.PCI0.SBC3.PIBA) + Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIBA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIBA, 0x0F, _SB.PCI0.SBC3.PIBA) + ShiftLeft (Local1, 0x04, Local1) + Or (_SB.PCI0.SBC3.PIBA, Local1, _SB.PCI0.SBC3.PIBA) + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x03) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFA) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFA, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFA, 0x01, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIDC, 0x0F, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } + + Return (BUFA) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRA1) + CreateByteField (Arg0, 0x02, IRA2) + ShiftLeft (IRA2, 0x08, Local0) + Or (Local0, IRA1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIDC, 0xF0, _SB.PCI0.SBC3.PIDC) + Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F")) + Name (_UID, 0x04) + Method (_STA, 0, NotSerialized) + { + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local0) + If (LEqual (Local0, 0x00)) { Return (0x09) } + Else { Return (0x0B) } + } + + Method (_PRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {3,5,10,11} + }) + Return (BUFB) + } + + Method (_DIS, 0, NotSerialized) + { + Store (0x01, Local3) + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + Store (Local1, Local2) + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local1) + } + + ShiftLeft (Local3, Local1, Local3) + Not (Local3, Local3) + And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUFB, ResourceTemplate () + { + IRQ (Level, ActiveLow, Shared) {} + }) + CreateByteField (BUFB, 0x01, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (_SB.PCI0.SBC3.PIDC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNot (LEqual (Local1, 0x00))) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } + + Return (BUFB) + } + + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x01, IRB1) + CreateByteField (Arg0, 0x02, IRB2) + ShiftLeft (IRB2, 0x08, Local0) + Or (Local0, IRB1, Local0) + Store (0x00, Local1) + ShiftRight (Local0, 0x01, Local0) + While (LGreater (Local0, 0x00)) + { + Increment (Local1) + ShiftRight (Local0, 0x01, Local0) + } + + And (_SB.PCI0.SBC3.PIDC, 0x0F, _SB.PCI0.SBC3.PIDC) + ShiftLeft (Local1, 0x04, Local1) + Or (_SB.PCI0.SBC3.PIDC, Local1, _SB.PCI0.SBC3.PIDC) + } + }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl index dd82e38..4484c19 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131.asl @@ -2,118 +2,118 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + }
- Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + }
- Name (APIC, Package (0x14) - { + Name (APIC, Package (0x14) + { // Slot 3 - PIRQ BCDA ---- verified - Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
//Slot 4 - PIRQ CDAB ---- verified - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //? + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
//Onboard NIC 1 - PIRQ DABC - Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? - Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, - Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, - Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A }, + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //? + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
// NIC 2 - PIRQ ABCD -- verified - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //? + Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
//SERIAL ATA - PIRQ BCDA - Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? - Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, - Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, - Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } - }) - Name (PICM, Package (0x14) - { - Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKB, 0x00 },//Slot 3 - Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //? + Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A }, + Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 } + }) + Name (PICM, Package (0x14) + { + Package (0x04) { 0x0001FFFF, 0x00, _SB.PCI0.LNKB, 0x00 },//Slot 3 + Package (0x04) { 0x0001FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, _SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, _SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x00, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x01, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x02, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0003FFFF, 0x03, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x00, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, _SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0004FFFF, 0x03, _SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0005FFFF, 0x00, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x01, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x02, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0005FFFF, 0x03, _SB.PCI0.LNKA, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
- Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + }
- Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + }
- Name (APIC, Package (0x04) - { + Name (APIC, Package (0x04) + { // Slot A - PIRQ CDAB -- verfied - Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, - Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, - Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0002FFFF, 0x00, _SB.PCI0.LNKC, 0x00 },//Slot 2 - Package (0x04) { 0x0002FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0002FFFF, 0x03, _SB.PCI0.LNKB, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2 + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0002FFFF, 0x00, _SB.PCI0.LNKC, 0x00 },//Slot 2 + Package (0x04) { 0x0002FFFF, 0x01, _SB.PCI0.LNKD, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, _SB.PCI0.LNKB, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl index 8b8bc9f..dbcc381 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8131_2.asl @@ -2,113 +2,113 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - }) + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl index e5cfe3c..1a7cd2f 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8132_2.asl @@ -2,113 +2,113 @@ * Copyright 2005 AMD */
- Device (PG0A) - { - /* 8132 pcix bridge*/ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Device (PG0A) + { + /* 8132 pcix bridge*/ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ BCDA - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, - - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, - }) + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B }, + + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 2 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 }, + })
Name (DNCG, Ones)
- Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } - - Device (PG0B) - { - /* 8132 pcix bridge 2 */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } - - Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } - Else { Return (Package (0x02) { 0x22, 0x01 }) } - } - - Name (APIC, Package (0x04) - { + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } + + Device (PG0B) + { + /* 8132 pcix bridge 2 */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) } + Else { Return (Package (0x02) { 0x22, 0x01 }) } + } + + Name (APIC, Package (0x04) + { // Slot A - PIRQ ABCD - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - - Name (DNCG, Ones) - - Method (_PRT, 0, NotSerialized) - { - If (LEqual (^DNCG, Ones)) { - Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 - Store (0x00, Local1) - While (LLess (Local1, 0x04)) - { - // Update the GSI according to HCIN - Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) - Add(Local2, Local0, Local0) - Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) - Increment (Local1) - } - - Store (0x00, ^DNCG) - - } - - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 },//Slot 1 + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + + Name (DNCG, Ones) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (^DNCG, Ones)) { + Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14 + Store (0x00, Local1) + While (LLess (Local1, 0x04)) + { + // Update the GSI according to HCIN + Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0) + Add(Local2, Local0, Local0) + Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3)) + Increment (Local1) + } + + Store (0x00, ^DNCG) + + } + + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + } diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl index ce85502..577d35a 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/amd8151.asl @@ -1,29 +1,29 @@ // AMD8151 - Device (AGPB) - { - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00010000)) - } + Device (AGPB) + { + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00010000)) + }
- Name (APIC, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, - Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, - Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, - Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } - }) - Name (PICM, Package (0x04) - { - Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, - Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } - }) - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) { Return (PICM) } - Else { Return (APIC) } - } - } + Name (APIC, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 } + }) + Name (PICM, Package (0x04) + { + Package (0x04) { 0x0000FFFF, 0x00, _SB.PCI0.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, _SB.PCI0.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, _SB.PCI0.LNKC, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, _SB.PCI0.LNKD, 0x00 } + }) + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) { Return (PICM) } + Else { Return (APIC) } + } + }
diff --git a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl index 1035a7e..48a24ed 100644 --- a/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl +++ b/src/mainboard/iwill/dk8_htx/acpi/htx_no_ioapic.asl @@ -2,19 +2,19 @@ * Copyright 2006 AMD */
- Device (HTXA) - { - /* HTX */ - Method (_ADR, 0, NotSerialized) - { - Return (DADD(GHCD(HCIN, 0), 0x00000000)) - } + Device (HTXA) + { + /* HTX */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + }
- Method (_PRW, 0, NotSerialized) - { - If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } - Else { Return (Package (0x02) { 0x29, 0x01 }) } - } + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + }
- } + }
diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index b021214..e2407d5 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -27,14 +27,14 @@ static void dump_mem(unsigned start, unsigned end) {
unsigned i; - print_debug("dump_mem:"); - for(i=start;i<end;i++) { - if((i & 0xf)==0) { - printk(BIOS_DEBUG, "\n%08x:", i); - } - printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - print_debug("\n"); + print_debug("dump_mem:"); + for(i=start;i<end;i++) { + if((i & 0xf)==0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); + } + print_debug("\n"); } #endif
@@ -58,9 +58,9 @@ unsigned long acpi_fill_madt(unsigned long current) { unsigned int gsi_base=0x18;
- struct mb_sysconf_t *m; + struct mb_sysconf_t *m;
- m = sysconf.mb; + m = sysconf.mb;
/* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -69,75 +69,75 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111, IO_APIC_ADDR, 0);
- /* Write all 8131 IOAPICs */ - { - device_t dev; - struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + /* Write all 8131 IOAPICs */ + { + device_t dev; + struct resource *res; + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, + res->base, gsi_base ); gsi_base+=4;
- } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); - gsi_base+=4; - } - } - - int i; - int j = 0; - - for(i=1; i< sysconf.hc_possible_num; i++) { + } + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, + res->base, gsi_base ); + gsi_base+=4; + } + } + + int i; + int j = 0; + + for(i=1; i< sysconf.hc_possible_num; i++) { unsigned d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; - // 8131 need to use +4 + if(!(sysconf.pci1234[i] & 0x1) ) continue; + // 8131 need to use +4
- switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: d = 7; break; case 3: d = 4; break; } - switch (sysconf.hcid[i]) { - case 1: + switch (sysconf.hcid[i]) { + case 1: case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); - gsi_base+=d; - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); - gsi_base+=d; - - } - } - break; - } - - j++; - } - - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], + res->base, gsi_base ); + gsi_base+=d; + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], + res->base, gsi_base ); + gsi_base+=d; + + } + } + break; + } + + j++; + } + + }
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); @@ -147,8 +147,8 @@ unsigned long acpi_fill_madt(unsigned long current) /* 5 mean: 0101 --> Edige-triggered, Active high*/
- /* create all subtables for processors */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); + /* create all subtables for processors */ + current = acpi_create_madt_lapic_nmis(current, 5, 1); /* 1: LINT1 connect to NMI */
@@ -181,7 +181,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
/* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); + start = ALIGN(start, 16); current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -216,18 +216,18 @@ unsigned long write_acpi_tables(unsigned long start)
/* SRAT */ - printk(BIOS_DEBUG, "ACPI: * SRAT\n"); - srat = (acpi_srat_t *) current; - acpi_create_srat(srat); - current+=srat->header.length; - acpi_add_table(rsdp,srat); + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current+=srat->header.length; + acpi_add_table(rsdp,srat);
/* SLIT */ - printk(BIOS_DEBUG, "ACPI: * SLIT\n"); - slit = (acpi_slit_t *) current; - acpi_create_slit(slit); - current+=slit->header.length; - acpi_add_table(rsdp,slit); + printk(BIOS_DEBUG, "ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit);
/* SSDT */ printk(BIOS_DEBUG, "ACPI: * SSDT\n"); @@ -239,43 +239,43 @@ unsigned long write_acpi_tables(unsigned long start)
#if CONFIG_ACPI_SSDTX_NUM >= 1
- //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - uint8_t c; - if(i<7) { - c = (uint8_t) ('4' + i - 1); - } - else { - c = (uint8_t) ('A' + i - 1 - 6); - } - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt - current = ALIGN(current, 8); - ssdtx = (acpi_header_t *)current; - switch(sysconf.hcid[i]) { - case 1: //8132 - p = &AmlCode_ssdt2; - break; - case 2: //8151 - p = &AmlCode_ssdt3; - break; + //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table + + for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + if((sysconf.pci1234[i] & 1) != 1 ) continue; + uint8_t c; + if(i<7) { + c = (uint8_t) ('4' + i - 1); + } + else { + c = (uint8_t) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt + current = ALIGN(current, 8); + ssdtx = (acpi_header_t *)current; + switch(sysconf.hcid[i]) { + case 1: //8132 + p = &AmlCode_ssdt2; + break; + case 2: //8151 + p = &AmlCode_ssdt3; + break; case 3: //8131 - p = &AmlCode_ssdt4; - break; - default: + p = &AmlCode_ssdt4; + break; + default: //HTX no io apic - p = &AmlCode_ssdt5; + p = &AmlCode_ssdt5; break; - } + } memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); - acpi_add_table(rsdp,ssdtx); - } + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length); + acpi_add_table(rsdp,ssdtx); + } #endif
/* FACS */ @@ -304,23 +304,23 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "rsdp\n"); dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
- printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
- printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length);
- printk(BIOS_DEBUG, "srat\n"); - dump_mem(srat, ((void *)srat) + srat->header.length); + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length);
- printk(BIOS_DEBUG, "slit\n"); - dump_mem(slit, ((void *)slit) + slit->header.length); + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length);
- printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
- printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); #endif
printk(BIOS_INFO, "ACPI: done.\n"); diff --git a/src/mainboard/iwill/dk8_htx/cmos.layout b/src/mainboard/iwill/dk8_htx/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/iwill/dk8_htx/cmos.layout +++ b/src/mainboard/iwill/dk8_htx/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index 544390d..feedef7 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdk8 @@ -29,32 +29,32 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off # CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 @@ -65,12 +65,12 @@ chip northbridge/amd/amdk8/root_complex io 0x2b = 0xd0ff io 0xf0 = 0xef16 end - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 - end + end end end device pci 1.1 on end @@ -103,8 +103,8 @@ chip northbridge/amd/amdk8/root_complex end # acpi device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
@@ -114,16 +114,16 @@ chip northbridge/amd/amdk8/root_complex end
end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end
end
diff --git a/src/mainboard/iwill/dk8_htx/dsdt.asl b/src/mainboard/iwill/dk8_htx/dsdt.asl index da14fe8..160e1bb 100644 --- a/src/mainboard/iwill/dk8_htx/dsdt.asl +++ b/src/mainboard/iwill/dk8_htx/dsdt.asl @@ -5,10 +5,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) { Scope (_PR) { - Processor (CPU0, 0x00, 0x0000C010, 0x06) {} - Processor (CPU1, 0x01, 0x00000000, 0x00) {} - Processor (CPU2, 0x02, 0x00000000, 0x00) {} - Processor (CPU3, 0x03, 0x00000000, 0x00) {} + Processor (CPU0, 0x00, 0x0000C010, 0x06) {} + Processor (CPU1, 0x01, 0x00000000, 0x00) {} + Processor (CPU2, 0x02, 0x00000000, 0x00) {} + Processor (CPU3, 0x03, 0x00000000, 0x00) {}
}
@@ -21,8 +21,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Scope (_SB) { - Device (PCI0) - { + Device (PCI0) + { /* BUS0 root bus */
External (BUSN) @@ -36,174 +36,174 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (CBST)
- Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00180000) - Name (_UID, 0x01) - - Name (HCIN, 0x00) // HC1 - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () - { - IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh - IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h - IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x8100, // Address Range Minimum - 0xFFFF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x7F00,,, - , TypeStatic) //8100h-FFFFh - - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Address Space Granularity - 0x000C0000, // Address Range Minimum - 0x000CFFFF, // Address Range Maximum - 0x00000000, // Address Translation Offset - 0x00010000,,, - , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh - - Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x03AF, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x03B0,,, - , TypeStatic) //0-CF7h - - WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x03E0, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0918,,, - , TypeStatic) //0-CF7h - }) - _SB.OSTP () - CreateDWordField (BUF0, 0x3E, VLEN) - CreateDWordField (BUF0, 0x36, VMAX) - CreateDWordField (BUF0, 0x32, VMIN) - ShiftLeft (VGA1, 0x09, Local0) - Add (VMIN, Local0, VMAX) - Decrement (VMAX) - Store (Local0, VLEN) - Concatenate (_SB.GMEM (0x00, _SB.PCI0.SBLK), BUF0, Local1) - Concatenate (_SB.GIOR (0x00, _SB.PCI0.SBLK), Local1, Local2) - Concatenate (_SB.GWBN (0x00, _SB.PCI0.SBLK), Local2, Local3) - Return (Local3) + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_UID, 0x01) + + Name (HCIN, 0x00) // HC1 + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh + IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h + IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x8100, // Address Range Minimum + 0xFFFF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x7F00,,, + , TypeStatic) //8100h-FFFFh + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x000C0000, // Address Range Minimum + 0x000CFFFF, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00010000,,, + , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh + + Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x03AF, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x03B0,,, + , TypeStatic) //0-CF7h + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x03E0, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0918,,, + , TypeStatic) //0-CF7h + }) + _SB.OSTP () + CreateDWordField (BUF0, 0x3E, VLEN) + CreateDWordField (BUF0, 0x36, VMAX) + CreateDWordField (BUF0, 0x32, VMIN) + ShiftLeft (VGA1, 0x09, Local0) + Add (VMIN, Local0, VMAX) + Decrement (VMAX) + Store (Local0, VLEN) + Concatenate (_SB.GMEM (0x00, _SB.PCI0.SBLK), BUF0, Local1) + Concatenate (_SB.GIOR (0x00, _SB.PCI0.SBLK), Local1, Local2) + Concatenate (_SB.GWBN (0x00, _SB.PCI0.SBLK), Local2, Local3) + Return (Local3) }
#include "acpi/pci0_hc.asl"
- } - Device (PCI1) - { - Name (_HID, "PNP0A03") - Name (_ADR, 0x00000000) - Name (_UID, 0x02) - Method (_STA, 0, NotSerialized) - { - Return (_SB.PCI0.CBST) - } + } + Device (PCI1) + { + Name (_HID, "PNP0A03") + Name (_ADR, 0x00000000) + Name (_UID, 0x02) + Method (_STA, 0, NotSerialized) + { + Return (_SB.PCI0.CBST) + } Name (_BBN, 0x00) - } + }
}
Scope (_GPE) { - Method (_L08, 0, NotSerialized) - { - Notify (_SB.PCI0, 0x02) //PME# Wakeup - } - - Method (_L0F, 0, NotSerialized) - { - Notify (_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup - } - - Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B - { - Notify (_SB.PCI0.PG0B, 0x02) - } - - Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A - { - Notify (_SB.PCI0.PG0A, 0x02) - } + Method (_L08, 0, NotSerialized) + { + Notify (_SB.PCI0, 0x02) //PME# Wakeup + } + + Method (_L0F, 0, NotSerialized) + { + Notify (_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup + } + + Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B + { + Notify (_SB.PCI0.PG0B, 0x02) + } + + Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A + { + Notify (_SB.PCI0.PG0A, 0x02) + } }
Method (_PTS, 1, NotSerialized) { - Or (Arg0, 0xF0, Local0) - Store (Local0, DBG1) + Or (Arg0, 0xF0, Local0) + Store (Local0, DBG1) } /* Method (_WAK, 1, NotSerialized) { - Or (Arg0, 0xE0, Local0) - Store (Local0, DBG1) + Or (Arg0, 0xE0, Local0) + Store (Local0, DBG1) } */ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method { - Store (Arg0, PICF) + Store (Arg0, PICF) }
OperationRegion (DEBG, SystemIO, 0x80, 0x01) Field (DEBG, ByteAcc, Lock, Preserve) { - DBG1, 8 + DBG1, 8 }
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04) Field (EXTM, WordAcc, Lock, Preserve) { - AMEM, 32 + AMEM, 32 }
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01) Field (VGAM, ByteAcc, Lock, Preserve) { - VGA1, 8 + VGA1, 8 }
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) Field (GRAM, ByteAcc, Lock, Preserve) { - Offset (0x10), - FLG0, 8 + Offset (0x10), + FLG0, 8 }
OperationRegion (GSTS, SystemIO, 0xC028, 0x02) Field (GSTS, ByteAcc, NoLock, Preserve) { - , 4, - IRQR, 1 + , 4, + IRQR, 1 }
OperationRegion (Z007, SystemIO, 0x21, 0x01) Field (Z007, ByteAcc, NoLock, Preserve) { - Z008, 8 + Z008, 8 }
OperationRegion (Z009, SystemIO, 0xA1, 0x01) Field (Z009, ByteAcc, NoLock, Preserve) { - Z00A, 8 + Z00A, 8 }
#include "northbridge/amd/amdk8/util.asl" diff --git a/src/mainboard/iwill/dk8_htx/fadt.c b/src/mainboard/iwill/dk8_htx/fadt.c index f677b4e..d6ff1f3 100644 --- a/src/mainboard/iwill/dk8_htx/fadt.c +++ b/src/mainboard/iwill/dk8_htx/fadt.c @@ -43,8 +43,8 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->pm1b_cnt_blk = 0x0000; fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = pm_base+0x08; - fadt->gpe0_blk = pm_base+0x20; - fadt->gpe1_blk = pm_base+0xb0; + fadt->gpe0_blk = pm_base+0x20; + fadt->gpe1_blk = pm_base+0xb0;
fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; @@ -54,7 +54,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){ fadt->gpe1_blk_len = 8; fadt->gpe1_base = 16;
- fadt->cst_cnt = 0xe3; + fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; fadt->flush_size = 0; diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 8868f46..c22c01c 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -20,22 +20,22 @@ static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for 0x0000ff0, // SB chain m 0x0000000, // HTX 0x0000100, // co processor on socket 1 -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -109,8 +109,8 @@ void get_bus_conf(void) m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8111_0, sysconf.sbdn); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8111_0, sysconf.sbdn); }
/* 8132-1 */ @@ -119,8 +119,8 @@ void get_bus_conf(void) m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3); }
/* 8132-2 */ @@ -129,8 +129,8 @@ void get_bus_conf(void) m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132_0, m->sbdn3 + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132_0, m->sbdn3 + 1); }
/* HT chain 1 */ @@ -157,11 +157,11 @@ void get_bus_conf(void) PCI_DEVFN(m->sbdn3a[j], 0)); if (dev) { m->bus_8132a[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j]); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j]); }
/* 8132-2 */ @@ -170,11 +170,11 @@ void get_bus_conf(void) PCI_DEVFN(m->sbdn3a[j] + 1, 0)); if (dev) { m->bus_8132a[j][2] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8132a[j][0], m->sbdn3a[j] + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8132a[j][0], m->sbdn3a[j] + 1); }
break; @@ -190,11 +190,11 @@ void get_bus_conf(void)
if (dev) { m->bus_8151[j][1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_8151[j][0], m->sbdn5[j] + 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_8151[j][0], m->sbdn5[j] + 1); }
break; diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index 637f980..d2e46dd 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -17,8 +17,8 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; + pirq_info->bus = bus; + pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -30,7 +30,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->rfu = rfu; }
@@ -44,8 +44,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
struct mb_sysconf_t *m;
@@ -53,12 +53,12 @@ unsigned long write_pirq_routing_table(unsigned long addr)
m = sysconf.mb;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -81,62 +81,62 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0;
- { - device_t dev; - dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ3 - PINTB = IRQ5 - PINTC = IRQ10 - PINTD = IRQ11 - */ - pci_write_config16(dev, 0x56, 0xba53); - } - } + { + device_t dev; + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3)); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ3 + PINTB = IRQ5 + PINTC = IRQ10 + PINTD = IRQ11 + */ + pci_write_config16(dev, 0x56, 0xba53); + } + }
//pci bridge - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; - pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; + pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; - pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; + printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; + pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); + write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++;
//pcix bridge -// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++;
int j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff;
- write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; - j++; + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; + j++;
- } + }
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/iwill/dk8_htx/mb_sysconf.h b/src/mainboard/iwill/dk8_htx/mb_sysconf.h index 3042dd0..402ac68 100644 --- a/src/mainboard/iwill/dk8_htx/mb_sysconf.h +++ b/src/mainboard/iwill/dk8_htx/mb_sysconf.h @@ -9,18 +9,18 @@ struct mb_sysconf_t { unsigned char bus_8111_0; unsigned char bus_8111_1;
- unsigned char bus_8132a[7][3]; + unsigned char bus_8132a[7][3];
- unsigned char bus_8151[7][2]; + unsigned char bus_8151[7][2];
- unsigned apicid_8111; - unsigned apicid_8132_1; - unsigned apicid_8132_2; - unsigned apicid_8132a[7][2]; + unsigned apicid_8111; + unsigned apicid_8132_1; + unsigned apicid_8132_2; + unsigned apicid_8132a[7][2];
- unsigned sbdn3; - unsigned sbdn3a[7]; - unsigned sbdn5[7]; + unsigned sbdn3; + unsigned sbdn3a[7]; + unsigned sbdn5[7];
};
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index ff6e582..ff14da3 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -12,15 +12,15 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, j, bus_isa; struct mb_sysconf_t *m;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
@@ -30,139 +30,139 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 - { - device_t dev; + { + device_t dev; struct resource *res; - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); - if (dev) { + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); } - } - dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); - if (dev) { + } + dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); } - } + }
- j = 0; + j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue;
- switch(sysconf.hcid[i]) { - case 1: // 8132 + switch(sysconf.hcid[i]) { + case 1: // 8132 case 3: // 8131 - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); - } - } - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); - } - } - break; - } - j++; - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base); + } + } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base); + } + } + break; + } + j++; + }
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
//??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
// Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
// Onboard VGA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
//Slot 5 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16 + }
//Slot 6 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16 + } //Slot 1: HTX
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30 + }
//Slot 3 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25 + }
//Slot 4 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26 + }
//Onboard NICS - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
//Onboard SATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
- j = 0; + j = 0;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - int ii; - device_t dev; - struct resource *res; - switch(sysconf.hcid[i]) { - case 1: + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + int ii; + device_t dev; + struct resource *res; + switch(sysconf.hcid[i]) { + case 1: case 3: - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 1 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // - } - } - } - - dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - //Slot 2 PCI-X 133/100/66 - for(ii=0;ii<4;ii++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 - } - } - } - - break; - case 2: - - // Slot AGP - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); - break; - } - - j++; - } + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 1 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); // + } + } + } + + dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + //Slot 2 PCI-X 133/100/66 + for(ii=0;ii<4;ii++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25 + } + } + } + + break; + case 2: + + // Slot AGP + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11); + break; + } + + j++; + }
diff --git a/src/mainboard/iwill/dk8_htx/resourcemap.c b/src/mainboard/iwill/dk8_htx/resourcemap.c index d60c379..7b8fa7c 100644 --- a/src/mainboard/iwill/dk8_htx/resourcemap.c +++ b/src/mainboard/iwill/dk8_htx/resourcemap.c @@ -16,21 +16,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -50,25 +50,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -89,27 +89,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -130,21 +130,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -161,23 +161,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, @@ -191,23 +191,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -221,35 +221,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 6944df0..d09ebd7 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -55,7 +55,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/amdk8.h" @@ -82,72 +82,72 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) };
struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0;
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_mb_resource_map(); + setup_mb_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + }
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -159,13 +159,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + /* all ap stopped? */ + init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - dump_pci_devices(); + dump_pci_devices(); #endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/iwill/dk8_htx/ssdt2.asl b/src/mainboard/iwill/dk8_htx/ssdt2.asl index 791454c..da53836 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt2.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt2.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci2_hc.asl" - } + } }
} diff --git a/src/mainboard/iwill/dk8_htx/ssdt3.asl b/src/mainboard/iwill/dk8_htx/ssdt3.asl index 28fe5f4..5d297f0 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt3.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt3.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci3_hc.asl" - } + } }
} diff --git a/src/mainboard/iwill/dk8_htx/ssdt4.asl b/src/mainboard/iwill/dk8_htx/ssdt4.asl index 93abb7f..917a205 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt4.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt4.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci4_hc.asl" - } + } }
} diff --git a/src/mainboard/iwill/dk8_htx/ssdt5.asl b/src/mainboard/iwill/dk8_htx/ssdt5.asl index 5910e0f..224bcec 100644 --- a/src/mainboard/iwill/dk8_htx/ssdt5.asl +++ b/src/mainboard/iwill/dk8_htx/ssdt5.asl @@ -23,8 +23,8 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) External (_SB.PCI0.LNKC, DeviceObj) External (_SB.PCI0.LNKD, DeviceObj)
- Device (PCIX) - { + Device (PCIX) + {
// BUS ? Second HT Chain Name (HCIN, 0xcc) // HC2 0x01 @@ -33,35 +33,35 @@ DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
Name (_HID, "PNP0A03")
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 { Return (DADD(GHCN(HCIN), 0x00000000)) }
- Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + }
- Method (_STA, 0, NotSerialized) - { - Return (_SB.GHCE(HCIN)) - } + Method (_STA, 0, NotSerialized) + { + Return (_SB.GHCE(HCIN)) + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) Store( GHCN(HCIN), Local4) Store( GHCL(HCIN), Local5)
- Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } + Concatenate (_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + }
#include "acpi/pci5_hc.asl" - } + } }
} diff --git a/src/mainboard/iwill/dk8s2/cmos.layout b/src/mainboard/iwill/dk8s2/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/iwill/dk8s2/cmos.layout +++ b/src/mainboard/iwill/dk8s2/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb index fda8ca2..97b90d1 100644 --- a/src/mainboard/iwill/dk8s2/devicetree.cb +++ b/src/mainboard/iwill/dk8s2/devicetree.cb @@ -25,27 +25,27 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy + device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 + device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.3 off # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard + device pnp 2e.5 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 - irq 0x70 = 1 + irq 0x70 = 1 irq 0x72 = 12 end device pnp 2e.6 off end # CIR @@ -53,7 +53,7 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end end diff --git a/src/mainboard/iwill/dk8s2/irq_tables.c b/src/mainboard/iwill/dk8s2/irq_tables.c index 3e1424c..04a7667 100644 --- a/src/mainboard/iwill/dk8s2/irq_tables.c +++ b/src/mainboard/iwill/dk8s2/irq_tables.c @@ -9,18 +9,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */ + (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x1022, /* Vendor */ 0x746b, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0}, {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0}, {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0}, @@ -37,5 +37,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 940e8a6..21d4e75 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -55,7 +55,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/amdk8.h" @@ -74,81 +74,81 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0,
// second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0;
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_default_resource_map(); + setup_default_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + }
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -160,13 +160,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + /* all ap stopped? */ + init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - dump_pci_devices(); + dump_pci_devices(); #endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/iwill/dk8x/cmos.layout b/src/mainboard/iwill/dk8x/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/iwill/dk8x/cmos.layout +++ b/src/mainboard/iwill/dk8x/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/iwill/dk8x/irq_tables.c b/src/mainboard/iwill/dk8x/irq_tables.c index 1b7b92b..3c5e0db 100644 --- a/src/mainboard/iwill/dk8x/irq_tables.c +++ b/src/mainboard/iwill/dk8x/irq_tables.c @@ -17,7 +17,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT * devices on the bus */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */ @@ -52,5 +52,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index bab7760..c2e0958 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -55,7 +55,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/amdk8.h" @@ -83,72 +83,72 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) };
struct sys_info *sysinfo = &sysinfo_car; - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0;
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_default_resource_map(); + setup_default_resource_map();
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_other_cores(); + start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + }
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -160,13 +160,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ - init_timer(); // Need to use TMICT to synconize FID/VID + /* all ap stopped? */ + init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - dump_pci_devices(); + dump_pci_devices(); #endif
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/jetway/j7f24/cmos.layout b/src/mainboard/jetway/j7f24/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/jetway/j7f24/cmos.layout +++ b/src/mainboard/jetway/j7f24/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/jetway/j7f24/devicetree.cb b/src/mainboard/jetway/j7f24/devicetree.cb index 3b99b9c..f6b2c7d 100644 --- a/src/mainboard/jetway/j7f24/devicetree.cb +++ b/src/mainboard/jetway/j7f24/devicetree.cb @@ -25,29 +25,29 @@ chip northbridge/via/cn700 # Northbridge device pci 10.3 on end # OHCI device pci 10.4 on end # EHCI device pci 11.0 on # Southbridge LPC - chip superio/fintek/f71805f # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end + chip superio/fintek/f71805f # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end end device pci 11.5 on end # AC'97 audio # device pci 11.6 off end # AC'97 Modem diff --git a/src/mainboard/jetway/j7f24/irq_tables.c b/src/mainboard/jetway/j7f24/irq_tables.c index 888cf48..8cff836 100644 --- a/src/mainboard/jetway/j7f24/irq_tables.c +++ b/src/mainboard/jetway/j7f24/irq_tables.c @@ -34,7 +34,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x3e, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, diff --git a/src/mainboard/jetway/pa78vm5/acpi/ide.asl b/src/mainboard/jetway/pa78vm5/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/jetway/pa78vm5/acpi/ide.asl +++ b/src/mainboard/jetway/pa78vm5/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/jetway/pa78vm5/acpi_tables.c b/src/mainboard/jetway/pa78vm5/acpi_tables.c index b783862..0e9f05f 100644 --- a/src/mainboard/jetway/pa78vm5/acpi_tables.c +++ b/src/mainboard/jetway/pa78vm5/acpi_tables.c @@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/jetway/pa78vm5/cmos.layout b/src/mainboard/jetway/pa78vm5/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/jetway/pa78vm5/cmos.layout +++ b/src/mainboard/jetway/pa78vm5/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 783e4ae..d935dad 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -22,7 +22,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 9.0 on end # device pci a.0 on end # register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default + register "gpp_configuration" = "3" # Configuration D default register "port_enable" = "0x6fc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "1" diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 848d43e..34aab64 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "JETWAY", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "JETWAY", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -113,7 +113,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -134,13 +134,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -159,7 +159,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -284,8 +284,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -421,16 +421,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -801,7 +801,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1454,7 +1454,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1634,23 +1634,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1659,7 +1659,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index 47342fb..3622248 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 373ebb5..fb59744 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -62,7 +62,7 @@ void set_pcie_reset() pci_write_config16(sm_dev, 0xA8, word); }
-#if 0 /* not tested yet. */ +#if 0 /* not tested yet. */ /******************************************************** * board uses SB700 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 949501b..603203d 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -155,7 +155,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/jetway/pa78vm5/resourcemap.c b/src/mainboard/jetway/pa78vm5/resourcemap.c index f4717b5..7dfebf3 100644 --- a/src/mainboard/jetway/pa78vm5/resourcemap.c +++ b/src/mainboard/jetway/pa78vm5/resourcemap.c @@ -34,21 +34,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 2487b2f..e3269e2 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -243,8 +243,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 4ae8834..4535cb8 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -21,176 +21,176 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 11 cmos_defaults_loaded -#937 11 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 11 cmos_defaults_loaded +#937 11 r 0 unused
# coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature
-968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 -971 1 e 1 lpt +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 +971 1 e 1 lpt
-#972 12 r 0 unused +#972 12 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed +8 0 Disabled +8 1 Speed #8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (°C/°F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 #10 10 60/140 #10 11 63/145 #10 12 66/150 #10 13 69/156 #10 14 72/161 #10 15 75/167 -11 0 No -11 1 Yes +11 0 No +11 1 Yes # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 65a96a0..a9b0b25 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -1,18 +1,18 @@ chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end
- device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -28,43 +28,43 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
- register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x1" + register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627thg + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627thg device pnp 2e.0 off # Floppy end device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 2e.5 on # Keyboard+Mouse io 0x60 = 0x60 io 0x62 = 0x64 @@ -91,21 +91,21 @@ chip northbridge/intel/i945 irq 0x70 = 0 end
- end - chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy + end + chip superio/winbond/w83627thg + device pnp 4e.0 off # Floppy end device pnp 4e.1 off # Parport end - device pnp 4e.2 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 11 - end - device pnp 4e.3 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 10 + device pnp 4e.2 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 11 + end + device pnp 4e.3 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 10 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 4e.5 off # Keyboard end device pnp 4e.7 off # GPIO1, GAME, MIDI @@ -118,13 +118,13 @@ chip northbridge/intel/i945 end device pnp 4e.b off # HWM end - end + end
- end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/kontron/986lcd-m/irq_tables.c b/src/mainboard/kontron/986lcd-m/irq_tables.c index ab1f2e5..7befa10 100644 --- a/src/mainboard/kontron/986lcd-m/irq_tables.c +++ b/src/mainboard/kontron/986lcd-m/irq_tables.c @@ -21,10 +21,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -32,7 +32,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf, /* u8 checksum. */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c index 03f7370..217ea18 100644 --- a/src/mainboard/kontron/986lcd-m/mptable.c +++ b/src/mainboard/kontron/986lcd-m/mptable.c @@ -27,16 +27,16 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; struct device *riser = NULL, *firewire = NULL; int firewire_bus = 0, riser_bus = 0, isa_bus; int ioapic_id;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
firewire = dev_find_device(0x104c, 0x8023, 0); if (firewire) { @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, ioapic_id, 0x10);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/kontron/kt690/acpi/ide.asl b/src/mainboard/kontron/kt690/acpi/ide.asl index 7cee00d..5e6d207 100644 --- a/src/mainboard/kontron/kt690/acpi/ide.asl +++ b/src/mainboard/kontron/kt690/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/kontron/kt690/acpi_tables.c b/src/mainboard/kontron/kt690/acpi_tables.c index 0465c1b..96429b5 100644 --- a/src/mainboard/kontron/kt690/acpi_tables.c +++ b/src/mainboard/kontron/kt690/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/kontron/kt690/cmos.layout b/src/mainboard/kontron/kt690/cmos.layout index 86aadf5..981f476 100644 --- a/src/mainboard/kontron/kt690/cmos.layout +++ b/src/mainboard/kontron/kt690/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index 22bdae9..b1b5bf7 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -1,7 +1,7 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. #Define gfx_dual_slot, 0: single slot, 1: dual slot #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable #Define gfx_tmds, 0: didn't support TMDS, 1: support @@ -48,7 +48,7 @@ chip northbridge/amd/amdk8/root_complex device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index c221e0a..23a3482 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "dsdt.aml", /* Output filename */ - "DSDT", /* Signature */ + "dsdt.aml", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "COREv2", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "COREv2", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -380,16 +380,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -762,7 +762,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1142,7 +1142,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1164,8 +1164,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1175,8 +1175,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1184,8 +1184,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1193,8 +1193,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1396,7 +1396,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1411,7 +1411,7 @@ DefinitionBlock ( Offset (0xF0), APC0, 8, /* APC/PME Event Enable Register */ APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ + APC2, 8, /* APC/PME Control Register 1 */ APC3, 8, /* Environment Controller Special Configuration Register */ APC4, 8 /* APC/PME Control Register 2 */ } @@ -1435,7 +1435,7 @@ DefinitionBlock ( * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1577,23 +1577,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1602,7 +1602,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 717c399..02cc1d9 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -27,12 +27,12 @@ #include <southbridge/amd/sb600/sb600.h>
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); + u8 val); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 6a94479..f0280de 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -147,7 +147,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl index b93aa96..4ab38bd 100644 --- a/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl +++ b/src/mainboard/kontron/ktqm77/acpi/sandybridge_pci_irqs.asl @@ -25,19 +25,19 @@ Method(_PRT) If (PICM) { Return (Package() { // LPC devices 0:1f.x - // D31IP_TTIP THRT INTC -> PIRQC + // D31IP_TTIP THRT INTC -> PIRQC Package() { 0x001fffff, 2, 0, 18 },// D31IP_SMIP SMBUS INTC -> PIRQC Package() { 0x001fffff, 1, 0, 19 },// D31IP_SIP SATA INTB -> PIRQD (MSI) // EHCI #1 0:1d.0 Package() { 0x001dffff, 0, 0, 23 },// D29IP_E1P EHCI1 INTA -> PIRQH // PCIe Root Ports 0:1c.x - // D28IP_P8IP Slot? INTD -> PIRQD + // D28IP_P8IP Slot? INTD -> PIRQD Package() { 0x001cffff, 3, 0, 19 },// D28IP_P4IP ETH2 INTD -> PIRQD (MSI) - // D28IP_P7IP PCIEx1 INTC -> PIRQC + // D28IP_P7IP PCIEx1 INTC -> PIRQC Package() { 0x001cffff, 2, 0, 18 },// D28IP_P3IP ETH1 INTC -> PIRQC (MSI) - // D28IP_P6IP 1394 INTB -> PIRQB (MSI) + // D28IP_P6IP 1394 INTB -> PIRQB (MSI) Package() { 0x001cffff, 1, 0, 17 },// D28IP_P2IP Slot? INTB -> PIRQB - // D28IP_P5IP GbEPHY INTA -> PIRQA + // D28IP_P5IP GbEPHY INTA -> PIRQA Package() { 0x001cffff, 0, 0, 16 },// D28IP_P1IP Slot? INTA -> PIRQA // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, 0, 22 },// D27IP_ZIP HDA INTA -> PIRQG (MSI) @@ -48,12 +48,12 @@ Method(_PRT) // xHCI 0:14.0 Package() { 0x0014ffff, 0, 0, 16 },// D20IP_XHCIIP xHCI INTA -> PIRQA (MSI) // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) // PCIe PEG x16 0:1.0 - Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD - Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC - Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB - Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA + Package() { 0x0001ffff, 3, 0, 19 },// PEGx16 INTD -> PIRQD + Package() { 0x0001ffff, 2, 0, 18 },// PEGx16 INTC -> PIRQC + Package() { 0x0001ffff, 1, 0, 17 },// PEGx16 INTB -> PIRQB + Package() { 0x0001ffff, 0, 0, 16 },// PEGx16 INTA -> PIRQA }) } Else { Return (Package() { diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index ed6d357..5108e6b 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -210,7 +210,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..69d92f0 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -21,147 +21,147 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +416 4 e 10 systemp_type +420 7 h 0 fan1_min +427 7 h 0 fan1_max +434 7 h 0 fan2_min +441 7 h 0 fan2_max
# coreboot config options: bootloader -448 64 r 0 write_protected_by_bios -512 328 s 0 boot_devices -840 8 h 0 boot_default -848 1 e 9 cmos_defaults_loaded -849 1 e 2 ethernet1 -850 1 e 2 ethernet2 -#851 5 r 0 unused +448 64 r 0 write_protected_by_bios +512 328 s 0 boot_devices +840 8 h 0 boot_default +848 1 e 9 cmos_defaults_loaded +849 1 e 2 ethernet1 +850 1 e 2 ethernet2 +#851 5 r 0 unused
# coreboot config options: mainboard specific options -856 2 e 8 fan1_mode -858 2 r 0 fan1_reserved -860 2 e 8 fan2_mode -862 2 r 0 fan2_reserved -864 16 h 0 fan1_target -880 16 h 0 fan2_target +856 2 e 8 fan1_mode +858 2 r 0 fan1_reserved +860 2 e 8 fan2_mode +862 2 r 0 fan2_reserved +864 16 h 0 fan1_target +880 16 h 0 fan2_target
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Auto -8 1 PWM -8 2 Speed -8 3 Thermal -9 0 No -9 1 Yes -10 0 None -10 1 AMD -10 2 LM75@90 -10 3 GPIO16 -10 4 LM75@9e +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Auto +8 1 PWM +8 2 Speed +8 3 Thermal +9 0 No +9 1 Yes +10 0 None +10 1 AMD +10 2 LM75@90 +10 3 GPIO16 +10 4 LM75@9e # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/kontron/ktqm77/gpio.h b/src/mainboard/kontron/ktqm77/gpio.h index f99e028..065a7be 100644 --- a/src/mainboard/kontron/ktqm77/gpio.h +++ b/src/mainboard/kontron/ktqm77/gpio.h @@ -24,7 +24,7 @@
/* * TODO: Investigate somehow... Current values are taken from a running - * system with vendor supplied firmware. + * system with vendor supplied firmware. */
const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -56,7 +56,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio25 = GPIO_MODE_GPIO, /* Unknown Input */ .gpio26 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ4# pin */ .gpio27 = GPIO_MODE_GPIO, /* Unknown Input */ /* Vendor supplied DSDT sets this conditionally - when going to suspend (S3, S4, S5). */ + when going to suspend (S3, S4, S5). */ .gpio28 = GPIO_MODE_GPIO, /* Unknown Output HIGH */ .gpio29 = GPIO_MODE_NATIVE, /* Native - SLP_LAN# pin, forced by soft strap */ .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# pin */ diff --git a/src/mainboard/kontron/ktqm77/hda_verb.h b/src/mainboard/kontron/ktqm77/hda_verb.h index 53b3fc9..24e1b17 100644 --- a/src/mainboard/kontron/ktqm77/hda_verb.h +++ b/src/mainboard/kontron/ktqm77/hda_verb.h @@ -21,8 +21,8 @@ /* * Pin widget configuration: * - * Port-Con. Location Def.-Dev. Con.-Type Color Misc Def.-Aso. Seq - * 31..30 29..24 23..20 19..16 15..12 11..00 07..04 03..00 + * Port-Con. Location Def.-Dev. Con.-Type Color Misc Def.-Aso. Seq + * 31..30 29..24 23..20 19..16 15..12 11..00 07..04 03..00 */ #define PIN_CFG(pin, val) \ (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ @@ -46,67 +46,67 @@ static const u32 mainboard_cim_verb_data[] = {
/* * NID 0x19 [Port A (SURR)]: - * Jack Internal Speaker N/A Black + * Jack Internal Speaker N/A Black */ PIN_CFG(0x19, 0x10101112)
/* * NID 0x1a [Port B (MIC1/2)]: - * Jack Rear Mic In 1/8" Pink + * Jack Rear Mic In 1/8" Pink */ PIN_CFG(0x1a, 0x01a19036)
/* * NID 0x1b [Port C (LINEIN)]: - * Jack Rear Line In 1/8" Blue + * Jack Rear Line In 1/8" Blue */ PIN_CFG(0x1b, 0x0181303e)
/* * NID 0x1c [Port D (Front)]: - * Jack Rear Line Out 1/8" Green + * Jack Rear Line Out 1/8" Green */ PIN_CFG(0x1c, 0x01014010)
/* * NID 0x1d [Port E (Front HP/MIC)]: - * Jack Front HP Out 1/8" Green + * Jack Front HP Out 1/8" Green */ PIN_CFG(0x1d, 0x022141f0)
/* * NID 0x1e [Port F (Front HP/MIC)]: - * Jack Front Mic In 1/8" Pink + * Jack Front Mic In 1/8" Pink */ PIN_CFG(0x1e, 0x02a19138)
/* * NID 0x1f [CD]: - * Jack Int.(ATAPI) CD ATAPI internal Black + * Jack Int.(ATAPI) CD ATAPI internal Black */ PIN_CFG(0x1f, 0x19331137)
/* * NID 0x20 [N/A]: - * Jack Rear S/PDIF Out RCA Unknown + * Jack Rear S/PDIF Out RCA Unknown */ PIN_CFG(0x20, 0x014401f0)
/* * NID 0x21 [N/A]: - * None Internal S/PDIF Out Other Digital Unknown + * None Internal S/PDIF Out Other Digital Unknown */ PIN_CFG(0x21, 0x504600f0)
/* * NID 0x22 [Port G (C/LFE)]: - * Jack Internal Speaker Unknown Orange + * Jack Internal Speaker Unknown Orange */ PIN_CFG(0x22, 0x10106111)
/* * NID 0x23 [Port H (SSL/SSR)]: - * Jack Internal Speaker Unknown Grey + * Jack Internal Speaker Unknown Grey */ PIN_CFG(0x23, 0x10102114)
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 3829d72..d772589 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -57,7 +57,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_EAX &= 0xffff0000; X86_EAX |= 0x005f; @@ -131,9 +131,9 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); + X86_EAX & 0xffff); break; } return res; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 773079d..4e6c91a 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -44,9 +44,9 @@ static void pch_enable_lpc(void) pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);
/* Enable KBC on 0x06/0x64 (KBC), - * EC on 0x62/0x66 (MC), - * EC on 0x20c-0x20f (GAMEH), - * Super I/O on 0x2e/0x2f (CNF1), + * EC on 0x62/0x66 (MC), + * EC on 0x20c-0x20f (GAMEH), + * Super I/O on 0x2e/0x2f (CNF1), * COM1/COM3 decode ranges. */ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | @@ -59,32 +59,32 @@ static void rcba_config(void) u32 reg32;
/* - * D31IP_TTIP THRT INTC -> PIRQC - * D31IP_SIP2 SATA2 NOINT - * D31IP_SMIP SMBUS INTC -> PIRQC - * D31IP_SIP SATA INTB -> PIRQD (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQH - * D28IP_P8IP Slot? INTD -> PIRQD - * D28IP_P7IP PCIEx1 INTC -> PIRQC - * D28IP_P6IP 1394 INTB -> PIRQB (MSI) - * D28IP_P5IP GbEPHY INTA -> PIRQA - * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) - * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) - * D28IP_P2IP Slot? INTB -> PIRQB - * D28IP_P1IP Slot? INTA -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - * D26IP_E2P EHCI2 INTA -> PIRQA - * D25IP_LIP ETH0 INTA -> PIRQE (MSI) - * D22IP_KTIP MEI NOINT - * D22IP_IDERIP MEI NOINT - * D22IP_MEI2IP MEI NOINT - * D22IP_MEI1IP MEI NOINT - * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) - * GFX INTA -> PIRQA (MSI) - * PEGx16 INTA -> PIRQA - * INTB -> PIRQB - * INTC -> PIRQC - * INTD -> PIRQD + * D31IP_TTIP THRT INTC -> PIRQC + * D31IP_SIP2 SATA2 NOINT + * D31IP_SMIP SMBUS INTC -> PIRQC + * D31IP_SIP SATA INTB -> PIRQD (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQH + * D28IP_P8IP Slot? INTD -> PIRQD + * D28IP_P7IP PCIEx1 INTC -> PIRQC + * D28IP_P6IP 1394 INTB -> PIRQB (MSI) + * D28IP_P5IP GbEPHY INTA -> PIRQA + * D28IP_P4IP ETH2 INTD -> PIRQD (MSI) + * D28IP_P3IP ETH1 INTC -> PIRQC (MSI) + * D28IP_P2IP Slot? INTB -> PIRQB + * D28IP_P1IP Slot? INTA -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D26IP_E2P EHCI2 INTA -> PIRQA + * D25IP_LIP ETH0 INTA -> PIRQE (MSI) + * D22IP_KTIP MEI NOINT + * D22IP_IDERIP MEI NOINT + * D22IP_MEI2IP MEI NOINT + * D22IP_MEI1IP MEI NOINT + * D20IP_XHCIIP XHCI INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) + * PEGx16 INTA -> PIRQA + * INTB -> PIRQB + * INTC -> PIRQC + * INTD -> PIRQD */
/* Device interrupt pin register (board specific) */ @@ -185,7 +185,7 @@ void main(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1600, usb_port_config: { - /* enabled usb oc pin length */ + /* enabled usb oc pin length */ { 1, 0, 0x0040 }, /* P0: lower left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P1: upper left USB 3.0 (OC0) */ { 1, 0, 0x0040 }, /* P2: lower right USB 3.0 (OC0) */ diff --git a/src/mainboard/lanner/em8510/cmos.layout b/src/mainboard/lanner/em8510/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/lanner/em8510/cmos.layout +++ b/src/mainboard/lanner/em8510/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/lanner/em8510/devicetree.cb b/src/mainboard/lanner/em8510/devicetree.cb index 257d894..caa92fb 100644 --- a/src/mainboard/lanner/em8510/devicetree.cb +++ b/src/mainboard/lanner/em8510/devicetree.cb @@ -14,38 +14,38 @@ chip northbridge/intel/i855 register "enable_native_ide" = "0" device pci 1f.0 on chip superio/winbond/w83627thg # link 1 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 end end - end + end end end device cpu_cluster 0 on diff --git a/src/mainboard/lanner/em8510/irq_tables.c b/src/mainboard/lanner/em8510/irq_tables.c index cfba92c..c0fde84 100644 --- a/src/mainboard/lanner/em8510/irq_tables.c +++ b/src/mainboard/lanner/em8510/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x39, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x01, (0x0f << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x1, 0x0}, {0x01, (0x0a << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x2, 0x0}, {0x01, (0x05 << 3) | 0x0, {{0x68, 0xdeb8}, {0x69, 0xdeb8}, {0x6a, 0xdeb8}, {0x6b, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 9a7314d..3f61f3e 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -56,8 +56,8 @@ void main(unsigned long bist) #endif }
- w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -67,7 +67,7 @@ void main(unsigned long bist) #endif
if (!bios_reset_detected()) { - enable_smbus(); + enable_smbus(); #if 1 dump_spd_registers(); dump_smbus_registers(); diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 8ee2778..eb625d9 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -16,7 +16,7 @@ config BOARD_LENOVO_T60 bool "ThinkPad T60 / T60p" help The following T60 series ThinkPad machines have been verified to - work correctly: + work correctly:
Thinkpad T60p (Model 2007)
diff --git a/src/mainboard/lenovo/t60/acpi/dock.asl b/src/mainboard/lenovo/t60/acpi/dock.asl index ba50609..f7a7ee5 100644 --- a/src/mainboard/lenovo/t60/acpi/dock.asl +++ b/src/mainboard/lenovo/t60/acpi/dock.asl @@ -77,7 +77,7 @@ Scope(_SB.PCI0.LPCB.EC)
Method(_Q18, 0, NotSerialized) { - Notify(_SB.DOCK, 3) + Notify(_SB.DOCK, 3) }
Method(_Q37, 0, NotSerialized) diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index de76dea..3c42628 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -151,13 +151,13 @@ Scope(_SB) * We have to do this in order to be able to work around * certain windows bugs. * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 */
/* Let's assume we're running at least Windows 2000 */ diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index 9a458e9..c7c7a3d 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -28,7 +28,7 @@ Device (DSPC) Field (DSPC, ByteAcc, NoLock, Preserve) { Offset (0xf4), - BRTC, 8 + BRTC, 8 }
Method(BRTD, 0, NotSerialized) diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 670c515..6e47d68 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -23,127 +23,127 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 - -1060 1 e 1 touchpad -1061 1 e 1 bluetooth -1064 8 h 0 volume -1072 1 e 9 first_battery +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +1060 1 e 1 touchpad +1061 1 e 1 bluetooth +1064 8 h 0 volume +1072 1 e 9 first_battery # -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes 9 0 Secondary 9 1 Primary # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t60/irq_tables.c b/src/mainboard/lenovo/t60/irq_tables.c index 8991d7f..b52c515 100644 --- a/src/mainboard/lenovo/t60/irq_tables.c +++ b/src/mainboard/lenovo/t60/irq_tables.c @@ -35,22 +35,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf5, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ - {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ - {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ - {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ - {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ - {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ - {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ + {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ + {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ + {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ + {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ + {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ + {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ } }; diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c index 744ef30..cb7063d 100644 --- a/src/mainboard/lenovo/t60/mptable.c +++ b/src/mainboard/lenovo/t60/mptable.c @@ -29,14 +29,14 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
@@ -48,20 +48,20 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x06, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */
mptable_lintsrc(mc, isa_bus); diff --git a/src/mainboard/lenovo/x60/acpi/dock.asl b/src/mainboard/lenovo/x60/acpi/dock.asl index 136f888..18f8a14 100644 --- a/src/mainboard/lenovo/x60/acpi/dock.asl +++ b/src/mainboard/lenovo/x60/acpi/dock.asl @@ -61,17 +61,17 @@ Scope(_SB.PCI0.LPCB.EC) { Method(_Q18, 0, NotSerialized) { - Notify(_SB.DOCK, 3) + Notify(_SB.DOCK, 3) }
Method(_Q50, 0, NotSerialized) { - Notify(_SB.DOCK, 3) + Notify(_SB.DOCK, 3) }
Method(_Q58, 0, NotSerialized) { - Notify(_SB.DOCK, 0) + Notify(_SB.DOCK, 0) }
} diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index de76dea..3c42628 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -151,13 +151,13 @@ Scope(_SB) * We have to do this in order to be able to work around * certain windows bugs. * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 */
/* Let's assume we're running at least Windows 2000 */ diff --git a/src/mainboard/lenovo/x60/acpi/video.asl b/src/mainboard/lenovo/x60/acpi/video.asl index b38d82b..45b6015 100644 --- a/src/mainboard/lenovo/x60/acpi/video.asl +++ b/src/mainboard/lenovo/x60/acpi/video.asl @@ -28,7 +28,7 @@ Device (DSPC) Field (DSPC, ByteAcc, NoLock, Preserve) { Offset (0xf4), - BRTC, 8 + BRTC, 8 }
Method(BRTD, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index ef49d0e..2dd76b9 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -23,127 +23,127 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 h 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 h 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 - -1064 8 h 0 volume -1072 8 h 0 tft_brightness -1080 1 e 9 first_battery -1081 1 e 1 bluetooth +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +1064 8 h 0 volume +1072 8 h 0 tft_brightness +1080 1 e 9 first_battery +1081 1 e 1 bluetooth # -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes 9 0 Secondary 9 1 Primary
diff --git a/src/mainboard/lenovo/x60/drm_dp_helper.h b/src/mainboard/lenovo/x60/drm_dp_helper.h index f2e06c3..fa9e6fc 100644 --- a/src/mainboard/lenovo/x60/drm_dp_helper.h +++ b/src/mainboard/lenovo/x60/drm_dp_helper.h @@ -45,120 +45,120 @@
/* AUX CH addresses */ /* DPCD */ -#define DP_DPCD_REV 0x000 +#define DP_DPCD_REV 0x000
-#define DP_MAX_LINK_RATE 0x001 +#define DP_MAX_LINK_RATE 0x001
-#define DP_MAX_LANE_COUNT 0x002 +#define DP_MAX_LANE_COUNT 0x002 # define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) +# define DP_TPS3_SUPPORTED (1 << 6) # define DP_ENHANCED_FRAME_CAP (1 << 7)
-#define DP_MAX_DOWNSPREAD 0x003 +#define DP_MAX_DOWNSPREAD 0x003 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
-#define DP_NORP 0x004 +#define DP_NORP 0x004
-#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 /* 00b = DisplayPort */ /* 01b = Analog */ /* 10b = TMDS or HDMI */ /* 11b = Other */ -# define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 - -#define DP_EDP_CONFIGURATION_CAP 0x00d -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_PSR_SUPPORT 0x070 -# define DP_PSR_IS_SUPPORTED 1 -#define DP_PSR_CAPS 0x071 -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 +# define DP_FORMAT_CONVERSION (1 << 3) + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_EDP_CONFIGURATION_CAP 0x00d +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e + +#define DP_PSR_SUPPORT 0x070 +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1
/* link configuration */ -#define DP_LINK_BW_SET 0x100 +#define DP_LINK_BW_SET 0x100 # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14
-#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
-#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 # define DP_TRAINING_PATTERN_1 1 # define DP_TRAINING_PATTERN_2 2 # define DP_TRAINING_PATTERN_3 3 # define DP_TRAINING_PATTERN_MASK 0x3
-# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
-# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
-# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
-#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4)
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) +# define DP_SET_ANSI_8B10B (1 << 0)
#define DP_PSR_EN_CFG 0x170 # define DP_PSR_ENABLE (1 << 0) # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) # define DP_PSR_CRC_VERIFICATION (1 << 2) -# define DP_PSR_FRAME_CAPTURE (1 << 3) +# define DP_PSR_FRAME_CAPTURE (1 << 3)
-#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) # define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_SINK_SPECIFIC_IRQ (1 << 6) +# define DP_CP_IRQ (1 << 2) +# define DP_SINK_SPECIFIC_IRQ (1 << 6)
-#define DP_EDP_CONFIGURATION_SET 0x10a +#define DP_EDP_CONFIGURATION_SET 0x10a
#define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 @@ -170,7 +170,7 @@ DP_LANE_CHANNEL_EQ_DONE | \ DP_LANE_SYMBOL_LOCKED)
-#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
#define DP_INTERLANE_ALIGN_DONE (1 << 0) #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) @@ -194,42 +194,42 @@
#define DP_TEST_REQUEST 0x218 # define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_PATTERN (1 << 1) +# define DP_TEST_LINK_PATTERN (1 << 1) # define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
#define DP_TEST_LINK_RATE 0x219 # define DP_LINK_RATE_162 (0x6) # define DP_LINK_RATE_27 (0xa)
-#define DP_TEST_LANE_COUNT 0x220 +#define DP_TEST_LANE_COUNT 0x220
#define DP_TEST_PATTERN 0x221
#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 - -#define DP_PSR_ERROR_STATUS 0x2006 -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) - -#define DP_PSR_ESI 0x2007 -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 + +#define DP_PSR_ERROR_STATUS 0x2006 +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07
#define MODE_I2C_START 1 #define MODE_I2C_WRITE 2 diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index f130c5c..00c9cfe 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -200,7 +200,7 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n", - (void *)graphics); + (void *)graphics); framebuffer->physical_address = graphics; framebuffer->x_resolution = 1024; framebuffer->y_resolution = 768; @@ -250,7 +250,7 @@ static int run(int index)
if (verbose & vspin) printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", + "%s: # loops %ld got %08lx want %08lx\n", regname(id->addr), t, u, id->data); } @@ -270,7 +270,7 @@ static int run(int index) udelay(100000); if (verbose & vio) printk(BIOS_SPEW, "U %d\n", - 100000); + 100000); } } break; @@ -289,7 +289,7 @@ static int run(int index) break; default: printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", - id->op, i); + id->op, i); return -1; } if (id->udelay) diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h index 382b822..11b44e8 100644 --- a/src/mainboard/lenovo/x60/i915_reg.h +++ b/src/mainboard/lenovo/x60/i915_reg.h @@ -139,7 +139,7 @@ #define VGA_SR_DATA 0x3c5
#define VGA_AR_INDEX 0x3c0 -#define VGA_AR_VID_EN (1<<5) +#define VGA_AR_VID_EN (1<<5) #define VGA_AR_DATA_WRITE 0x3c0 #define VGA_AR_DATA_READ 0x3c1
@@ -173,41 +173,41 @@
#define MI_NOOP MI_INSTR(0, 0) #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) -#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) -#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) +#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_FLUSH MI_INSTR(0x04, 0) -#define MI_READ_FLUSH (1 << 0) -#define MI_EXE_FLUSH (1 << 1) -#define MI_NO_WRITE_FLUSH (1 << 2) -#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ -#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ -#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ +#define MI_READ_FLUSH (1 << 0) +#define MI_EXE_FLUSH (1 << 1) +#define MI_NO_WRITE_FLUSH (1 << 2) +#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ +#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ +#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) -#define MI_SUSPEND_FLUSH_EN (1<<0) +#define MI_SUSPEND_FLUSH_EN (1<<0) #define MI_REPORT_HEAD MI_INSTR(0x07, 0) #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) -#define MI_OVERLAY_CONTINUE (0x0<<21) -#define MI_OVERLAY_ON (0x1<<21) -#define MI_OVERLAY_OFF (0x2<<21) +#define MI_OVERLAY_CONTINUE (0x0<<21) +#define MI_OVERLAY_ON (0x1<<21) +#define MI_OVERLAY_OFF (0x2<<21) #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) -#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) +#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) #define MI_SET_CONTEXT MI_INSTR(0x18, 0) -#define MI_MM_SPACE_GTT (1<<8) -#define MI_MM_SPACE_PHYSICAL (0<<8) -#define MI_SAVE_EXT_STATE_EN (1<<3) -#define MI_RESTORE_EXT_STATE_EN (1<<2) -#define MI_FORCE_RESTORE (1<<1) -#define MI_RESTORE_INHIBIT (1<<0) +#define MI_MM_SPACE_GTT (1<<8) +#define MI_MM_SPACE_PHYSICAL (0<<8) +#define MI_SAVE_EXT_STATE_EN (1<<3) +#define MI_RESTORE_EXT_STATE_EN (1<<2) +#define MI_FORCE_RESTORE (1<<1) +#define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) -#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ +#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) -#define MI_STORE_DWORD_INDEX_SHIFT 2 +#define MI_STORE_DWORD_INDEX_SHIFT 2 /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw * simply ignores the register load under certain conditions. @@ -216,23 +216,23 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) +#define MI_INVALIDATE_TLB (1<<18) +#define MI_INVALIDATE_BSD (1<<7) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) -#define MI_BATCH_NON_SECURE (1) -#define MI_BATCH_NON_SECURE_I965 (1<<8) +#define MI_BATCH_NON_SECURE (1) +#define MI_BATCH_NON_SECURE_I965 (1<<8) #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */ #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) -#define MI_SEMAPHORE_UPDATE (1<<21) -#define MI_SEMAPHORE_COMPARE (1<<20) -#define MI_SEMAPHORE_REGISTER (1<<18) -#define MI_SEMAPHORE_SYNC_RV (2<<16) -#define MI_SEMAPHORE_SYNC_RB (0<<16) -#define MI_SEMAPHORE_SYNC_VR (0<<16) -#define MI_SEMAPHORE_SYNC_VB (2<<16) -#define MI_SEMAPHORE_SYNC_BR (2<<16) -#define MI_SEMAPHORE_SYNC_BV (0<<16) +#define MI_SEMAPHORE_UPDATE (1<<21) +#define MI_SEMAPHORE_COMPARE (1<<20) +#define MI_SEMAPHORE_REGISTER (1<<18) +#define MI_SEMAPHORE_SYNC_RV (2<<16) +#define MI_SEMAPHORE_SYNC_RB (0<<16) +#define MI_SEMAPHORE_SYNC_VR (0<<16) +#define MI_SEMAPHORE_SYNC_VB (2<<16) +#define MI_SEMAPHORE_SYNC_BR (2<<16) +#define MI_SEMAPHORE_SYNC_BV (0<<16) #define MI_SEMAPHORE_SYNC_INVALID (1<<0) /* * 3D instructions used by the kernel @@ -240,57 +240,57 @@ #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) -#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) -#define SC_UPDATE_SCISSOR (0x1<<1) -#define SC_ENABLE_MASK (0x1<<0) -#define SC_ENABLE (0x1<<0) +#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) +#define SC_UPDATE_SCISSOR (0x1<<1) +#define SC_ENABLE_MASK (0x1<<0) +#define SC_ENABLE (0x1<<0) #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) -#define SCI_YMIN_MASK (0xffff<<16) -#define SCI_XMIN_MASK (0xffff<<0) -#define SCI_YMAX_MASK (0xffff<<16) -#define SCI_XMAX_MASK (0xffff<<0) +#define SCI_YMIN_MASK (0xffff<<16) +#define SCI_XMIN_MASK (0xffff<<0) +#define SCI_YMAX_MASK (0xffff<<16) +#define SCI_XMAX_MASK (0xffff<<0) #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) -#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) -#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) -#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) -#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) +#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) +#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) +#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) +#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) -#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) +#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) -#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) +#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) -#define BLT_DEPTH_8 (0<<24) -#define BLT_DEPTH_16_565 (1<<24) -#define BLT_DEPTH_16_1555 (2<<24) -#define BLT_DEPTH_32 (3<<24) -#define BLT_ROP_GXCOPY (0xcc<<16) +#define BLT_DEPTH_8 (0<<24) +#define BLT_DEPTH_16_565 (1<<24) +#define BLT_DEPTH_16_1555 (2<<24) +#define BLT_DEPTH_32 (3<<24) +#define BLT_ROP_GXCOPY (0xcc<<16) #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) -#define ASYNC_FLIP (1<<22) -#define DISPLAY_PLANE_A (0<<20) -#define DISPLAY_PLANE_B (1<<20) +#define ASYNC_FLIP (1<<22) +#define DISPLAY_PLANE_A (0<<20) +#define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) -#define PIPE_CONTROL_CS_STALL (1<<20) -#define PIPE_CONTROL_QW_WRITE (1<<14) -#define PIPE_CONTROL_DEPTH_STALL (1<<13) -#define PIPE_CONTROL_WRITE_FLUSH (1<<12) -#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ -#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ -#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ -#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) -#define PIPE_CONTROL_NOTIFY (1<<8) -#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) -#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) -#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) -#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) -#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) -#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_CS_STALL (1<<20) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WRITE_FLUSH (1<<12) +#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ +#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) +#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) +#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) +#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) +#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
/* @@ -307,32 +307,32 @@ */ #define FENCE_REG_830_0 0x2000 #define FENCE_REG_945_8 0x3000 -#define I830_FENCE_START_MASK 0x07f80000 -#define I830_FENCE_TILING_Y_SHIFT 12 -#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) -#define I830_FENCE_PITCH_SHIFT 4 -#define I830_FENCE_REG_VALID (1<<0) -#define I915_FENCE_MAX_PITCH_VAL 4 -#define I830_FENCE_MAX_PITCH_VAL 6 -#define I830_FENCE_MAX_SIZE_VAL (1<<8) - -#define I915_FENCE_START_MASK 0x0ff00000 -#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) +#define I915_FENCE_MAX_PITCH_VAL 4 +#define I830_FENCE_MAX_PITCH_VAL 6 +#define I830_FENCE_MAX_SIZE_VAL (1<<8) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
#define FENCE_REG_965_0 0x03000 -#define I965_FENCE_PITCH_SHIFT 2 -#define I965_FENCE_TILING_Y_SHIFT 1 -#define I965_FENCE_REG_VALID (1<<0) -#define I965_FENCE_MAX_PITCH_VAL 0x0400 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) +#define I965_FENCE_MAX_PITCH_VAL 0x0400
#define FENCE_REG_SANDYBRIDGE_0 0x100000 -#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 +#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
/* control register for cpu gtt access */ #define TILECTL 0x101000 -#define TILECTL_SWZCTL (1 << 0) -#define TILECTL_TLB_PREFETCH_DIS (1 << 2) -#define TILECTL_BACKSNOOP_DIS (1 << 3) +#define TILECTL_SWZCTL (1 << 0) +#define TILECTL_TLB_PREFETCH_DIS (1 << 2) +#define TILECTL_BACKSNOOP_DIS (1 << 3)
/* * Instruction and interrupt control regs @@ -358,10 +358,10 @@ #define RING_HWS_PGA(base) ((base)+0x80) #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) #define ARB_MODE 0x04030 -#define ARB_MODE_SWIZZLE_SNB (1<<4) -#define ARB_MODE_SWIZZLE_IVB (1<<5) -#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) -#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) +#define ARB_MODE_SWIZZLE_SNB (1<<4) +#define ARB_MODE_SWIZZLE_IVB (1<<5) +#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x) +#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x) #define RENDER_HWS_PGA_GEN7 (0x04080) #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) #define DONE_REG 0x40b0 @@ -370,21 +370,21 @@ #define RING_ACTHD(base) ((base)+0x74) #define RING_NOPID(base) ((base)+0x94) #define RING_IMR(base) ((base)+0xa8) -#define TAIL_ADDR 0x001FFFF8 -#define HEAD_WRAP_COUNT 0xFFE00000 -#define HEAD_WRAP_ONE 0x00200000 -#define HEAD_ADDR 0x001FFFFC -#define RING_NR_PAGES 0x001FF000 -#define RING_REPORT_MASK 0x00000006 -#define RING_REPORT_64K 0x00000002 -#define RING_REPORT_128K 0x00000004 -#define RING_NO_REPORT 0x00000000 -#define RING_VALID_MASK 0x00000001 -#define RING_VALID 0x00000001 -#define RING_INVALID 0x00000000 -#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ -#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ -#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ +#define TAIL_ADDR 0x001FFFF8 +#define HEAD_WRAP_COUNT 0xFFE00000 +#define HEAD_WRAP_ONE 0x00200000 +#define HEAD_ADDR 0x001FFFFC +#define RING_NR_PAGES 0x001FF000 +#define RING_REPORT_MASK 0x00000006 +#define RING_REPORT_64K 0x00000002 +#define RING_REPORT_128K 0x00000004 +#define RING_NO_REPORT 0x00000000 +#define RING_VALID_MASK 0x00000001 +#define RING_VALID 0x00000001 +#define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ +#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ #if 1 #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 @@ -411,7 +411,7 @@ #define HWS_ADDRESS_MASK 0xfffff000 #define HWS_START_ADDRESS_SHIFT 4 #define PWRCTXA 0x2088 /* 965GM+ only */ -#define PWRCTX_EN (1<<0) +#define PWRCTX_EN (1<<0) #define IPEIR 0x02088 #define IPEHR 0x0208c #define INSTDONE 0x02090 @@ -440,12 +440,12 @@ #define GFX_MODE 0x02520 #define GFX_MODE_GEN7 0x0229c #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) -#define GFX_RUN_LIST_ENABLE (1<<15) -#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) -#define GFX_SURFACE_FAULT_ENABLE (1<<12) -#define GFX_REPLAY_MODE (1<<11) -#define GFX_PSMI_GRANULARITY (1<<10) -#define GFX_PPGTT_ENABLE (1<<9) +#define GFX_RUN_LIST_ENABLE (1<<15) +#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) +#define GFX_SURFACE_FAULT_ENABLE (1<<12) +#define GFX_REPLAY_MODE (1<<11) +#define GFX_PSMI_GRANULARITY (1<<10) +#define GFX_PPGTT_ENABLE (1<<9)
#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) @@ -455,163 +455,163 @@ #define IIR 0x020a4 #define IMR 0x020a8 #define ISR 0x020ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) +#define I915_DISPLAY_PORT_INTERRUPT (1<<17) +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ +#define I915_HWB_OOM_INTERRUPT (1<<13) +#define I915_SYNC_STATUS_INTERRUPT (1<<12) +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) +#define I915_DEBUG_INTERRUPT (1<<2) +#define I915_USER_INTERRUPT (1<<1) +#define I915_ASLE_INTERRUPT (1<<0) +#define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 #define ESR 0x020b8 -#define GM45_ERROR_PAGE_TABLE (1<<5) -#define GM45_ERROR_MEM_PRIV (1<<4) -#define I915_ERROR_PAGE_TABLE (1<<4) -#define GM45_ERROR_CP_PRIV (1<<3) -#define I915_ERROR_MEMORY_REFRESH (1<<1) -#define I915_ERROR_INSTRUCTION (1<<0) -#define INSTPM 0x020c0 -#define INSTPM_SELF_EN (1<<12) /* 915GM only */ -#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts +#define GM45_ERROR_PAGE_TABLE (1<<5) +#define GM45_ERROR_MEM_PRIV (1<<4) +#define I915_ERROR_PAGE_TABLE (1<<4) +#define GM45_ERROR_CP_PRIV (1<<3) +#define I915_ERROR_MEMORY_REFRESH (1<<1) +#define I915_ERROR_INSTRUCTION (1<<0) +#define INSTPM 0x020c0 +#define INSTPM_SELF_EN (1<<12) /* 915GM only */ +#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts will not assert AGPBUSY# and will only be delivered when out of C3. */ -#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ -#define ACTHD 0x020c8 +#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ +#define ACTHD 0x020c8 #define FW_BLC 0x020d8 #define FW_BLC2 0x020dc #define FW_BLC_SELF 0x020e0 /* 915+ only */ -#define FW_BLC_SELF_EN_MASK (1<<31) -#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ -#define FW_BLC_SELF_EN (1<<15) /* 945 only */ -#define MM_BURST_LENGTH 0x00700000 +#define FW_BLC_SELF_EN_MASK (1<<31) +#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ +#define FW_BLC_SELF_EN (1<<15) /* 945 only */ +#define MM_BURST_LENGTH 0x00700000 #define MM_FIFO_WATERMARK 0x0001F000 -#define LM_BURST_LENGTH 0x00000700 +#define LM_BURST_LENGTH 0x00000700 #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE 0x020e4 /* 915+ only */ -#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */ +#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
/* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */ -#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) +#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
/* Isoch request wait on GTT enable (Display A/B/C streams). * Make isoch requests stall on the TLB update. May cause * display underruns (test mode only) */ -#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) +#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
/* Block grant count for isoch requests when block count is * set to a finite value. */ -#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) -#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ -#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ -#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ -#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ +#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) +#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ +#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ +#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ +#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
/* Enable render writes to complete in C2/C3/C4 power states. * If this isn't enabled, render writes are prevented in low * power states. That seems bad to me. */ -#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) +#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
/* This acknowledges an async flip immediately instead * of waiting for 2TLB fetches. */ -#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) +#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
/* Enables non-sequential data reads through arbiter */ -#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) +#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
/* Disable FSB snooping of cacheable write cycles from binner/render * command stream */ -#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) +#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
/* Arbiter time slice for non-isoch streams */ -#define MI_ARB_TIME_SLICE_MASK (7 << 5) -#define MI_ARB_TIME_SLICE_1 (0 << 5) -#define MI_ARB_TIME_SLICE_2 (1 << 5) -#define MI_ARB_TIME_SLICE_4 (2 << 5) -#define MI_ARB_TIME_SLICE_6 (3 << 5) -#define MI_ARB_TIME_SLICE_8 (4 << 5) -#define MI_ARB_TIME_SLICE_10 (5 << 5) -#define MI_ARB_TIME_SLICE_14 (6 << 5) -#define MI_ARB_TIME_SLICE_16 (7 << 5) +#define MI_ARB_TIME_SLICE_MASK (7 << 5) +#define MI_ARB_TIME_SLICE_1 (0 << 5) +#define MI_ARB_TIME_SLICE_2 (1 << 5) +#define MI_ARB_TIME_SLICE_4 (2 << 5) +#define MI_ARB_TIME_SLICE_6 (3 << 5) +#define MI_ARB_TIME_SLICE_8 (4 << 5) +#define MI_ARB_TIME_SLICE_10 (5 << 5) +#define MI_ARB_TIME_SLICE_14 (6 << 5) +#define MI_ARB_TIME_SLICE_16 (7 << 5)
/* Low priority grace period page size */ -#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ -#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) +#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ +#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
/* Disable display A/B trickle feed */ -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
/* Set display plane priority */ -#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ -#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ +#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ +#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
#define CACHE_MODE_0 0x02120 /* 915+ only */ -#define CM0_MASK_SHIFT 16 -#define CM0_IZ_OPT_DISABLE (1<<6) -#define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_MASK_SHIFT 16 +#define CM0_IZ_OPT_DISABLE (1<<6) +#define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) -#define CM0_DEPTH_EVICT_DISABLE (1<<4) -#define CM0_COLOR_EVICT_DISABLE (1<<3) -#define CM0_DEPTH_WRITE_DISABLE (1<<1) -#define CM0_RC_OP_FLUSH_DISABLE (1<<0) +#define CM0_DEPTH_EVICT_DISABLE (1<<4) +#define CM0_COLOR_EVICT_DISABLE (1<<3) +#define CM0_DEPTH_WRITE_DISABLE (1<<1) +#define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ #define ECOSKPD 0x021d0 -#define ECO_GATING_CX_ONLY (1<<3) -#define ECO_FLIP_DONE (1<<0) +#define ECO_GATING_CX_ONLY (1<<3) +#define ECO_FLIP_DONE (1<<0)
/* GEN6 interrupt control */ #define GEN6_RENDER_HWSTAM 0x2098 #define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) +#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) +#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) +#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) +#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) +#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) +#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) +#define GEN6_RENDER_SYNC_STATUS (1 << 2) +#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) +#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
#define GEN6_BLITTER_HWSTAM 0x22098 #define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) +#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) +#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) +#define GEN6_BLITTER_SYNC_STATUS (1 << 24) +#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
#define GEN6_BLITTER_ECOSKPD 0x221d0 -#define GEN6_BLITTER_LOCK_SHIFT 16 -#define GEN6_BLITTER_FBC_NOTIFY (1<<3) +#define GEN6_BLITTER_LOCK_SHIFT 16 +#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) -#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 -#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0) +#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 +#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
#define GEN6_BSD_HWSTAM 0x12098 #define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) +#define GEN6_BSD_USER_INTERRUPT (1 << 12)
#define GEN6_BSD_RNCID 0x12198
@@ -622,29 +622,29 @@ #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ #define FBC_LL_BASE 0x03204 /* 4k page aligned */ #define FBC_CONTROL 0x03208 -#define FBC_CTL_EN (1<<31) -#define FBC_CTL_PERIODIC (1<<30) -#define FBC_CTL_INTERVAL_SHIFT (16) -#define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_CTL_C3_IDLE (1<<13) -#define FBC_CTL_STRIDE_SHIFT (5) -#define FBC_CTL_FENCENO (1<<0) +#define FBC_CTL_EN (1<<31) +#define FBC_CTL_PERIODIC (1<<30) +#define FBC_CTL_INTERVAL_SHIFT (16) +#define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_CTL_C3_IDLE (1<<13) +#define FBC_CTL_STRIDE_SHIFT (5) +#define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c -#define FBC_CMD_COMPRESS (1<<0) +#define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 -#define FBC_STAT_COMPRESSING (1<<31) -#define FBC_STAT_COMPRESSED (1<<30) -#define FBC_STAT_MODIFIED (1<<29) -#define FBC_STAT_CURRENT_LINE (1<<0) +#define FBC_STAT_COMPRESSING (1<<31) +#define FBC_STAT_COMPRESSED (1<<30) +#define FBC_STAT_MODIFIED (1<<29) +#define FBC_STAT_CURRENT_LINE (1<<0) #define FBC_CONTROL2 0x03214 -#define FBC_CTL_FENCE_DBL (0<<4) -#define FBC_CTL_IDLE_IMM (0<<2) -#define FBC_CTL_IDLE_FULL (1<<2) -#define FBC_CTL_IDLE_LINE (2<<2) -#define FBC_CTL_IDLE_DEBUG (3<<2) -#define FBC_CTL_CPU_FENCE (1<<1) -#define FBC_CTL_PLANEA (0<<0) -#define FBC_CTL_PLANEB (1<<0) +#define FBC_CTL_FENCE_DBL (0<<4) +#define FBC_CTL_IDLE_IMM (0<<2) +#define FBC_CTL_IDLE_FULL (1<<2) +#define FBC_CTL_IDLE_LINE (2<<2) +#define FBC_CTL_IDLE_DEBUG (3<<2) +#define FBC_CTL_CPU_FENCE (1<<1) +#define FBC_CTL_PLANEA (0<<0) +#define FBC_CTL_PLANEB (1<<0) #define FBC_FENCE_OFF 0x0321b #define FBC_TAG 0x03300
@@ -653,45 +653,45 @@ /* Framebuffer compression for GM45+ */ #define DPFC_CB_BASE 0x3200 #define DPFC_CONTROL 0x3208 -#define DPFC_CTL_EN (1<<31) -#define DPFC_CTL_PLANEA (0<<30) -#define DPFC_CTL_PLANEB (1<<30) -#define DPFC_CTL_FENCE_EN (1<<29) -#define DPFC_CTL_PERSISTENT_MODE (1<<25) -#define DPFC_SR_EN (1<<10) -#define DPFC_CTL_LIMIT_1X (0<<6) -#define DPFC_CTL_LIMIT_2X (1<<6) -#define DPFC_CTL_LIMIT_4X (2<<6) +#define DPFC_CTL_EN (1<<31) +#define DPFC_CTL_PLANEA (0<<30) +#define DPFC_CTL_PLANEB (1<<30) +#define DPFC_CTL_FENCE_EN (1<<29) +#define DPFC_CTL_PERSISTENT_MODE (1<<25) +#define DPFC_SR_EN (1<<10) +#define DPFC_CTL_LIMIT_1X (0<<6) +#define DPFC_CTL_LIMIT_2X (1<<6) +#define DPFC_CTL_LIMIT_4X (2<<6) #define DPFC_RECOMP_CTL 0x320c -#define DPFC_RECOMP_STALL_EN (1<<27) -#define DPFC_RECOMP_STALL_WM_SHIFT (16) -#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) -#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) -#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) +#define DPFC_RECOMP_STALL_EN (1<<27) +#define DPFC_RECOMP_STALL_WM_SHIFT (16) +#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) +#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) +#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) #define DPFC_STATUS 0x3210 -#define DPFC_INVAL_SEG_SHIFT (16) -#define DPFC_INVAL_SEG_MASK (0x07ff0000) -#define DPFC_COMP_SEG_SHIFT (0) -#define DPFC_COMP_SEG_MASK (0x000003ff) +#define DPFC_INVAL_SEG_SHIFT (16) +#define DPFC_INVAL_SEG_MASK (0x07ff0000) +#define DPFC_COMP_SEG_SHIFT (0) +#define DPFC_COMP_SEG_MASK (0x000003ff) #define DPFC_STATUS2 0x3214 #define DPFC_FENCE_YOFF 0x3218 #define DPFC_CHICKEN 0x3224 -#define DPFC_HT_MODIFY (1<<31) +#define DPFC_HT_MODIFY (1<<31)
/* Framebuffer compression for Ironlake */ #define ILK_DPFC_CB_BASE 0x43200 #define ILK_DPFC_CONTROL 0x43208 /* The bit 28-8 is reserved */ -#define DPFC_RESERVED (0x1FFFFF00) +#define DPFC_RESERVED (0x1FFFFF00) #define ILK_DPFC_RECOMP_CTL 0x4320c #define ILK_DPFC_STATUS 0x43210 #define ILK_DPFC_FENCE_YOFF 0x43218 #define ILK_DPFC_CHICKEN 0x43224 #define ILK_FBC_RT_BASE 0x2128 -#define ILK_FBC_RT_VALID (1<<0) +#define ILK_FBC_RT_VALID (1<<0)
#define ILK_DISPLAY_CHICKEN1 0x42000 -#define ILK_FBCQ_DIS (1<<22) +#define ILK_FBCQ_DIS (1<<22) #define ILK_PABSTRETCH_DIS (1<<21)
@@ -701,7 +701,7 @@ * The following two registers are of type GTTMMADR */ #define SNB_DPFC_CTL_SA 0x100100 -#define SNB_CPU_FENCE_ENABLE (1<<29) +#define SNB_CPU_FENCE_ENABLE (1<<29) #define DPFC_CPU_FENCE_OFFSET 0x100104
@@ -732,52 +732,52 @@ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
#define GMBUS0 0x5100 /* clock/port select */ -#define GMBUS_RATE_100KHZ (0<<8) -#define GMBUS_RATE_50KHZ (1<<8) -#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ -#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ -#define GMBUS_RATE_MASK (3<<8) -#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ -#define GMBUS_PORT_DISABLED 0 -#define GMBUS_PORT_SSC 1 -#define GMBUS_PORT_VGADDC 2 -#define GMBUS_PORT_PANEL 3 -#define GMBUS_PORT_DPC 4 /* HDMIC */ -#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ -#define GMBUS_PORT_DPD 6 /* HDMID */ -#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ -#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) -#define GMBUS_PORT_MASK 7 +#define GMBUS_RATE_100KHZ (0<<8) +#define GMBUS_RATE_50KHZ (1<<8) +#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ +#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ +#define GMBUS_RATE_MASK (3<<8) +#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ +#define GMBUS_PORT_DISABLED 0 +#define GMBUS_PORT_SSC 1 +#define GMBUS_PORT_VGADDC 2 +#define GMBUS_PORT_PANEL 3 +#define GMBUS_PORT_DPC 4 /* HDMIC */ +#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ +#define GMBUS_PORT_DPD 6 /* HDMID */ +#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ +#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PORT_MASK 7 #define GMBUS1 0x5104 /* command/status */ -#define GMBUS_SW_CLR_INT (1<<31) -#define GMBUS_SW_RDY (1<<30) -#define GMBUS_ENT (1<<29) /* enable timeout */ -#define GMBUS_CYCLE_NONE (0<<25) -#define GMBUS_CYCLE_WAIT (1<<25) -#define GMBUS_CYCLE_INDEX (2<<25) -#define GMBUS_CYCLE_STOP (4<<25) -#define GMBUS_BYTE_COUNT_SHIFT 16 -#define GMBUS_SLAVE_INDEX_SHIFT 8 -#define GMBUS_SLAVE_ADDR_SHIFT 1 -#define GMBUS_SLAVE_READ (1<<0) -#define GMBUS_SLAVE_WRITE (0<<0) +#define GMBUS_SW_CLR_INT (1<<31) +#define GMBUS_SW_RDY (1<<30) +#define GMBUS_ENT (1<<29) /* enable timeout */ +#define GMBUS_CYCLE_NONE (0<<25) +#define GMBUS_CYCLE_WAIT (1<<25) +#define GMBUS_CYCLE_INDEX (2<<25) +#define GMBUS_CYCLE_STOP (4<<25) +#define GMBUS_BYTE_COUNT_SHIFT 16 +#define GMBUS_SLAVE_INDEX_SHIFT 8 +#define GMBUS_SLAVE_ADDR_SHIFT 1 +#define GMBUS_SLAVE_READ (1<<0) +#define GMBUS_SLAVE_WRITE (0<<0) #define GMBUS2 0x5108 /* status */ -#define GMBUS_INUSE (1<<15) -#define GMBUS_HW_WAIT_PHASE (1<<14) -#define GMBUS_STALL_TIMEOUT (1<<13) -#define GMBUS_INT (1<<12) -#define GMBUS_HW_RDY (1<<11) -#define GMBUS_SATOER (1<<10) -#define GMBUS_ACTIVE (1<<9) +#define GMBUS_INUSE (1<<15) +#define GMBUS_HW_WAIT_PHASE (1<<14) +#define GMBUS_STALL_TIMEOUT (1<<13) +#define GMBUS_INT (1<<12) +#define GMBUS_HW_RDY (1<<11) +#define GMBUS_SATOER (1<<10) +#define GMBUS_ACTIVE (1<<9) #define GMBUS3 0x510c /* data buffer bytes 3-0 */ #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ -#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) -#define GMBUS_NAK_EN (1<<3) -#define GMBUS_IDLE_EN (1<<2) -#define GMBUS_HW_WAIT_EN (1<<1) -#define GMBUS_HW_RDY_EN (1<<0) +#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) +#define GMBUS_NAK_EN (1<<3) +#define GMBUS_IDLE_EN (1<<2) +#define GMBUS_HW_WAIT_EN (1<<1) +#define GMBUS_HW_RDY_EN (1<<0) #define GMBUS5 0x5120 /* byte index */ -#define GMBUS_2BYTE_INDEX_EN (1<<31) +#define GMBUS_2BYTE_INDEX_EN (1<<31)
/* * Clock control & power management @@ -786,31 +786,31 @@ #define VGA0 0x6000 #define VGA1 0x6004 #define VGA_PD 0x6010 -#define VGA0_PD_P2_DIV_4 (1 << 7) -#define VGA0_PD_P1_DIV_2 (1 << 5) -#define VGA0_PD_P1_SHIFT 0 -#define VGA0_PD_P1_MASK (0x1f << 0) -#define VGA1_PD_P2_DIV_4 (1 << 15) -#define VGA1_PD_P1_DIV_2 (1 << 13) -#define VGA1_PD_P1_SHIFT 8 -#define VGA1_PD_P1_MASK (0x1f << 8) +#define VGA0_PD_P2_DIV_4 (1 << 7) +#define VGA0_PD_P1_DIV_2 (1 << 5) +#define VGA0_PD_P1_SHIFT 0 +#define VGA0_PD_P1_MASK (0x1f << 0) +#define VGA1_PD_P2_DIV_4 (1 << 15) +#define VGA1_PD_P1_DIV_2 (1 << 13) +#define VGA1_PD_P1_SHIFT 8 +#define VGA1_PD_P1_MASK (0x1f << 8) #define _DPLL_A 0x06014 #define _DPLL_B 0x06018 #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) -#define DPLL_VCO_ENABLE (1 << 31) -#define DPLL_DVO_HIGH_SPEED (1 << 30) -#define DPLL_SYNCLOCK_ENABLE (1 << 29) -#define DPLL_VGA_MODE_DIS (1 << 28) -#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ -#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ -#define DPLL_MODE_MASK (3 << 26) -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ -#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ -#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ -#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ -#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ +#define DPLL_VCO_ENABLE (1 << 31) +#define DPLL_DVO_HIGH_SPEED (1 << 30) +#define DPLL_SYNCLOCK_ENABLE (1 << 29) +#define DPLL_VGA_MODE_DIS (1 << 28) +#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +#define DPLL_MODE_MASK (3 << 26) +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
#define SRX_INDEX 0x3c4 #define SRX_DATA 0x3c5 @@ -829,29 +829,29 @@
/* Scratch pad debug 0 reg: */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 /* * The i830 generation, in LVDS mode, defines P1 as the bit number set within * this field (only one bit may be set). */ -#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 -#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 -#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 +#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 /* i830, required in DVO non-gang */ -#define PLL_P2_DIVIDE_BY_4 (1 << 23) -#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ -#define PLL_REF_INPUT_DREFCLK (0 << 13) -#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ -#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) -#define PLL_REF_INPUT_MASK (3 << 13) -#define PLL_LOAD_PULSE_PHASE_SHIFT 9 +#define PLL_P2_DIVIDE_BY_4 (1 << 23) +#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +#define PLL_REF_INPUT_DREFCLK (0 << 13) +#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ +#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +#define PLL_REF_INPUT_MASK (3 << 13) +#define PLL_LOAD_PULSE_PHASE_SHIFT 9 /* Ironlake */ -# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 -# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) +# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 +# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) -# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 -# define DPLL_FPA1_P1_POST_DIV_MASK 0xff +# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 +# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
/* * Parallel to Serial Load Pulse phase selection. @@ -859,25 +859,25 @@ * digital display port. The range is 4 to 13; 10 or more * is just a flip delay. The default is 6 */ -#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) -#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) +#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) /* * SDVO multiplier for 945G/GM. Not used on 965. */ -#define SDVO_MULTIPLIER_MASK 0x000000ff -#define SDVO_MULTIPLIER_SHIFT_HIRES 4 -#define SDVO_MULTIPLIER_SHIFT_VGA 0 +#define SDVO_MULTIPLIER_MASK 0x000000ff +#define SDVO_MULTIPLIER_SHIFT_HIRES 4 +#define SDVO_MULTIPLIER_SHIFT_VGA 0 #define _DPLL_A_MD 0x0601c /* 965+ only */ /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. * * Value is pixels minus 1. Must be set to 1 pixel for SDVO. */ -#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 -#define DPLL_MD_UDI_DIVIDER_SHIFT 24 +#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +#define DPLL_MD_UDI_DIVIDER_SHIFT 24 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ -#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 -#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 /* * SDVO/UDI pixel multiplier. * @@ -895,15 +895,15 @@ * This register field has values of multiplication factor minus 1, with * a maximum multiplier of 5 for SDVO. */ -#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 -#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 /* * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. * This best be set to the default value (3) or the CRT won't work. No, * I don't entirely understand what this does... */ -#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f -#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 #define _DPLL_B_MD 0x06020 /* 965+ only */ #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) #define _FPA0 0x06040 @@ -912,25 +912,25 @@ #define _FPB1 0x0604c #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) -#define FP_N_DIV_MASK 0x003f0000 -#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 -#define FP_N_DIV_SHIFT 16 -#define FP_M1_DIV_MASK 0x00003f00 -#define FP_M1_DIV_SHIFT 8 -#define FP_M2_DIV_MASK 0x0000003f -#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff -#define FP_M2_DIV_SHIFT 0 +#define FP_N_DIV_MASK 0x003f0000 +#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 +#define FP_N_DIV_SHIFT 16 +#define FP_M1_DIV_MASK 0x00003f00 +#define FP_M1_DIV_SHIFT 8 +#define FP_M2_DIV_MASK 0x0000003f +#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff +#define FP_M2_DIV_SHIFT 0 #define DPLL_TEST 0x606c -#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) -#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) -#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) -#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) -#define DPLLB_TEST_N_BYPASS (1 << 19) -#define DPLLB_TEST_M_BYPASS (1 << 18) -#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) -#define DPLLA_TEST_N_BYPASS (1 << 3) -#define DPLLA_TEST_M_BYPASS (1 << 2) -#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) +#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +#define DPLLB_TEST_N_BYPASS (1 << 19) +#define DPLLB_TEST_M_BYPASS (1 << 18) +#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +#define DPLLA_TEST_N_BYPASS (1 << 3) +#define DPLLA_TEST_M_BYPASS (1 << 2) +#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) #define D_STATE 0x6104 #define DSTATE_GFX_RESET_I830 (1<<6) #define DSTATE_PLL_D3_OFF (1<<3) @@ -1044,7 +1044,7 @@ #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) #define RAMCLK_GATE_D 0x6210 /* CRL only */ -#define DEUC 0x6214 /* CRL only */ +#define DEUC 0x6214 /* CRL only */
/* * Palette regs @@ -1078,7 +1078,7 @@ #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
/** Pineview MCH register contains DDR3 setting */ -#define CSHRDDR3CTL 0x101a8 +#define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL_DDR3 (1 << 2)
/** 965 MCH register controlling DRAM channel configuration */ @@ -1089,23 +1089,23 @@ #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) -#define MAD_DIMM_ECC_MASK (0x3 << 24) -#define MAD_DIMM_ECC_OFF (0x0 << 24) -#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) -#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) -#define MAD_DIMM_ECC_ON (0x3 << 24) -#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) -#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) -#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ -#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ -#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) -#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) -#define MAD_DIMM_A_SELECT (0x1 << 16) +#define MAD_DIMM_ECC_MASK (0x3 << 24) +#define MAD_DIMM_ECC_OFF (0x0 << 24) +#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) +#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) +#define MAD_DIMM_ECC_ON (0x3 << 24) +#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) +#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) +#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ +#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ +#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) +#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) +#define MAD_DIMM_A_SELECT (0x1 << 16) /* DIMM sizes are in multiples of 256mb. */ -#define MAD_DIMM_B_SIZE_SHIFT 8 -#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) -#define MAD_DIMM_A_SIZE_SHIFT 0 -#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) +#define MAD_DIMM_B_SIZE_SHIFT 8 +#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) +#define MAD_DIMM_A_SIZE_SHIFT 0 +#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
/* Clocking configuration register */ @@ -1126,194 +1126,194 @@ #define CLKCFG_MEM_MASK (7 << 4)
#define TSC1 0x11001 -#define TSE (1<<0) +#define TSE (1<<0) #define TR1 0x11006 #define TSFS 0x11020 -#define TSFS_SLOPE_MASK 0x0000ff00 -#define TSFS_SLOPE_SHIFT 8 -#define TSFS_INTR_MASK 0x000000ff +#define TSFS_SLOPE_MASK 0x0000ff00 +#define TSFS_SLOPE_SHIFT 8 +#define TSFS_INTR_MASK 0x000000ff
#define CRSTANDVID 0x11100 #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ -#define PXVFREQ_PX_MASK 0x7f000000 -#define PXVFREQ_PX_SHIFT 24 +#define PXVFREQ_PX_MASK 0x7f000000 +#define PXVFREQ_PX_SHIFT 24 #define VIDFREQ_BASE 0x11110 #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ #define VIDFREQ2 0x11114 #define VIDFREQ3 0x11118 #define VIDFREQ4 0x1111c -#define VIDFREQ_P0_MASK 0x1f000000 -#define VIDFREQ_P0_SHIFT 24 -#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 -#define VIDFREQ_P0_CSCLK_SHIFT 20 -#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 -#define VIDFREQ_P0_CRCLK_SHIFT 16 -#define VIDFREQ_P1_MASK 0x00001f00 -#define VIDFREQ_P1_SHIFT 8 -#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 -#define VIDFREQ_P1_CSCLK_SHIFT 4 -#define VIDFREQ_P1_CRCLK_MASK 0x0000000f +#define VIDFREQ_P0_MASK 0x1f000000 +#define VIDFREQ_P0_SHIFT 24 +#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 +#define VIDFREQ_P0_CSCLK_SHIFT 20 +#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 +#define VIDFREQ_P0_CRCLK_SHIFT 16 +#define VIDFREQ_P1_MASK 0x00001f00 +#define VIDFREQ_P1_SHIFT 8 +#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 +#define VIDFREQ_P1_CSCLK_SHIFT 4 +#define VIDFREQ_P1_CRCLK_MASK 0x0000000f #define INTTOEXT_BASE_ILK 0x11300 #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ -#define INTTOEXT_MAP3_SHIFT 24 -#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) -#define INTTOEXT_MAP2_SHIFT 16 -#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) -#define INTTOEXT_MAP1_SHIFT 8 -#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) -#define INTTOEXT_MAP0_SHIFT 0 -#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) +#define INTTOEXT_MAP3_SHIFT 24 +#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) +#define INTTOEXT_MAP2_SHIFT 16 +#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) +#define INTTOEXT_MAP1_SHIFT 8 +#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) +#define INTTOEXT_MAP0_SHIFT 0 +#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) #define MEMSWCTL 0x11170 /* Ironlake only */ -#define MEMCTL_CMD_MASK 0xe000 -#define MEMCTL_CMD_SHIFT 13 -#define MEMCTL_CMD_RCLK_OFF 0 -#define MEMCTL_CMD_RCLK_ON 1 -#define MEMCTL_CMD_CHFREQ 2 -#define MEMCTL_CMD_CHVID 3 -#define MEMCTL_CMD_VMMOFF 4 -#define MEMCTL_CMD_VMMON 5 -#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears - when command complete */ -#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ -#define MEMCTL_FREQ_SHIFT 8 -#define MEMCTL_SFCAVM (1<<7) -#define MEMCTL_TGT_VID_MASK 0x007f +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ 2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF 4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears + when command complete */ +#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ +#define MEMCTL_FREQ_SHIFT 8 +#define MEMCTL_SFCAVM (1<<7) +#define MEMCTL_TGT_VID_MASK 0x007f #define MEMIHYST 0x1117c #define MEMINTREN 0x11180 /* 16 bits */ -#define MEMINT_RSEXIT_EN (1<<8) -#define MEMINT_CX_SUPR_EN (1<<7) -#define MEMINT_CONT_BUSY_EN (1<<6) -#define MEMINT_AVG_BUSY_EN (1<<5) -#define MEMINT_EVAL_CHG_EN (1<<4) -#define MEMINT_MON_IDLE_EN (1<<3) -#define MEMINT_UP_EVAL_EN (1<<2) -#define MEMINT_DOWN_EVAL_EN (1<<1) -#define MEMINT_SW_CMD_EN (1<<0) +#define MEMINT_RSEXIT_EN (1<<8) +#define MEMINT_CX_SUPR_EN (1<<7) +#define MEMINT_CONT_BUSY_EN (1<<6) +#define MEMINT_AVG_BUSY_EN (1<<5) +#define MEMINT_EVAL_CHG_EN (1<<4) +#define MEMINT_MON_IDLE_EN (1<<3) +#define MEMINT_UP_EVAL_EN (1<<2) +#define MEMINT_DOWN_EVAL_EN (1<<1) +#define MEMINT_SW_CMD_EN (1<<0) #define MEMINTRSTR 0x11182 /* 16 bits */ -#define MEM_RSEXIT_MASK 0xc000 -#define MEM_RSEXIT_SHIFT 14 -#define MEM_CONT_BUSY_MASK 0x3000 -#define MEM_CONT_BUSY_SHIFT 12 -#define MEM_AVG_BUSY_MASK 0x0c00 -#define MEM_AVG_BUSY_SHIFT 10 -#define MEM_EVAL_CHG_MASK 0x0300 -#define MEM_EVAL_BUSY_SHIFT 8 -#define MEM_MON_IDLE_MASK 0x00c0 -#define MEM_MON_IDLE_SHIFT 6 -#define MEM_UP_EVAL_MASK 0x0030 -#define MEM_UP_EVAL_SHIFT 4 -#define MEM_DOWN_EVAL_MASK 0x000c -#define MEM_DOWN_EVAL_SHIFT 2 -#define MEM_SW_CMD_MASK 0x0003 -#define MEM_INT_STEER_GFX 0 -#define MEM_INT_STEER_CMR 1 -#define MEM_INT_STEER_SMI 2 -#define MEM_INT_STEER_SCI 3 +#define MEM_RSEXIT_MASK 0xc000 +#define MEM_RSEXIT_SHIFT 14 +#define MEM_CONT_BUSY_MASK 0x3000 +#define MEM_CONT_BUSY_SHIFT 12 +#define MEM_AVG_BUSY_MASK 0x0c00 +#define MEM_AVG_BUSY_SHIFT 10 +#define MEM_EVAL_CHG_MASK 0x0300 +#define MEM_EVAL_BUSY_SHIFT 8 +#define MEM_MON_IDLE_MASK 0x00c0 +#define MEM_MON_IDLE_SHIFT 6 +#define MEM_UP_EVAL_MASK 0x0030 +#define MEM_UP_EVAL_SHIFT 4 +#define MEM_DOWN_EVAL_MASK 0x000c +#define MEM_DOWN_EVAL_SHIFT 2 +#define MEM_SW_CMD_MASK 0x0003 +#define MEM_INT_STEER_GFX 0 +#define MEM_INT_STEER_CMR 1 +#define MEM_INT_STEER_SMI 2 +#define MEM_INT_STEER_SCI 3 #define MEMINTRSTS 0x11184 -#define MEMINT_RSEXIT (1<<7) -#define MEMINT_CONT_BUSY (1<<6) -#define MEMINT_AVG_BUSY (1<<5) -#define MEMINT_EVAL_CHG (1<<4) -#define MEMINT_MON_IDLE (1<<3) -#define MEMINT_UP_EVAL (1<<2) -#define MEMINT_DOWN_EVAL (1<<1) -#define MEMINT_SW_CMD (1<<0) +#define MEMINT_RSEXIT (1<<7) +#define MEMINT_CONT_BUSY (1<<6) +#define MEMINT_AVG_BUSY (1<<5) +#define MEMINT_EVAL_CHG (1<<4) +#define MEMINT_MON_IDLE (1<<3) +#define MEMINT_UP_EVAL (1<<2) +#define MEMINT_DOWN_EVAL (1<<1) +#define MEMINT_SW_CMD (1<<0) #define MEMMODECTL 0x11190 -#define MEMMODE_BOOST_EN (1<<31) -#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ -#define MEMMODE_BOOST_FREQ_SHIFT 24 -#define MEMMODE_IDLE_MODE_MASK 0x00030000 -#define MEMMODE_IDLE_MODE_SHIFT 16 -#define MEMMODE_IDLE_MODE_EVAL 0 -#define MEMMODE_IDLE_MODE_CONT 1 -#define MEMMODE_HWIDLE_EN (1<<15) -#define MEMMODE_SWMODE_EN (1<<14) -#define MEMMODE_RCLK_GATE (1<<13) -#define MEMMODE_HW_UPDATE (1<<12) -#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ -#define MEMMODE_FSTART_SHIFT 8 -#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ -#define MEMMODE_FMAX_SHIFT 4 -#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ +#define MEMMODE_BOOST_EN (1<<31) +#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ +#define MEMMODE_BOOST_FREQ_SHIFT 24 +#define MEMMODE_IDLE_MODE_MASK 0x00030000 +#define MEMMODE_IDLE_MODE_SHIFT 16 +#define MEMMODE_IDLE_MODE_EVAL 0 +#define MEMMODE_IDLE_MODE_CONT 1 +#define MEMMODE_HWIDLE_EN (1<<15) +#define MEMMODE_SWMODE_EN (1<<14) +#define MEMMODE_RCLK_GATE (1<<13) +#define MEMMODE_HW_UPDATE (1<<12) +#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ +#define MEMMODE_FSTART_SHIFT 8 +#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ +#define MEMMODE_FMAX_SHIFT 4 +#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ #define RCBMAXAVG 0x1119c #define MEMSWCTL2 0x1119e /* Cantiga only */ -#define SWMEMCMD_RENDER_OFF (0 << 13) -#define SWMEMCMD_RENDER_ON (1 << 13) -#define SWMEMCMD_SWFREQ (2 << 13) -#define SWMEMCMD_TARVID (3 << 13) -#define SWMEMCMD_VRM_OFF (4 << 13) -#define SWMEMCMD_VRM_ON (5 << 13) -#define CMDSTS (1<<12) -#define SFCAVM (1<<11) -#define SWFREQ_MASK 0x0380 /* P0-7 */ -#define SWFREQ_SHIFT 7 -#define TARVID_MASK 0x001f +#define SWMEMCMD_RENDER_OFF (0 << 13) +#define SWMEMCMD_RENDER_ON (1 << 13) +#define SWMEMCMD_SWFREQ (2 << 13) +#define SWMEMCMD_TARVID (3 << 13) +#define SWMEMCMD_VRM_OFF (4 << 13) +#define SWMEMCMD_VRM_ON (5 << 13) +#define CMDSTS (1<<12) +#define SFCAVM (1<<11) +#define SWFREQ_MASK 0x0380 /* P0-7 */ +#define SWFREQ_SHIFT 7 +#define TARVID_MASK 0x001f #define MEMSTAT_CTG 0x111a0 #define RCBMINAVG 0x111a0 #define RCUPEI 0x111b0 #define RCDNEI 0x111b4 #define RSTDBYCTL 0x111b8 -#define RS1EN (1<<31) -#define RS2EN (1<<30) -#define RS3EN (1<<29) -#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ -#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ -#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ -#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ -#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ -#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ -#define RSX_STATUS_MASK (7<<20) -#define RSX_STATUS_ON (0<<20) -#define RSX_STATUS_RC1 (1<<20) -#define RSX_STATUS_RC1E (2<<20) -#define RSX_STATUS_RS1 (3<<20) -#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ -#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ -#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ -#define RSX_STATUS_RSVD2 (7<<20) -#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ -#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ -#define JRSC (1<<17) /* rsx coupled to cpu c-state */ -#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ -#define RS1CONTSAV_MASK (3<<14) -#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ -#define RS1CONTSAV_RSVD (1<<14) -#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ -#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ -#define NORMSLEXLAT_MASK (3<<12) -#define SLOW_RS123 (0<<12) -#define SLOW_RS23 (1<<12) -#define SLOW_RS3 (2<<12) -#define NORMAL_RS123 (3<<12) -#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ -#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ -#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ -#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ -#define RS_CSTATE_MASK (3<<4) -#define RS_CSTATE_C367_RS1 (0<<4) -#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) -#define RS_CSTATE_RSVD (2<<4) -#define RS_CSTATE_C367_RS2 (3<<4) -#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ -#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ +#define RS1EN (1<<31) +#define RS2EN (1<<30) +#define RS3EN (1<<29) +#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ +#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ +#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ +#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ +#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ +#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ +#define RSX_STATUS_MASK (7<<20) +#define RSX_STATUS_ON (0<<20) +#define RSX_STATUS_RC1 (1<<20) +#define RSX_STATUS_RC1E (2<<20) +#define RSX_STATUS_RS1 (3<<20) +#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ +#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ +#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ +#define RSX_STATUS_RSVD2 (7<<20) +#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ +#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ +#define JRSC (1<<17) /* rsx coupled to cpu c-state */ +#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ +#define RS1CONTSAV_MASK (3<<14) +#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ +#define RS1CONTSAV_RSVD (1<<14) +#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ +#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ +#define NORMSLEXLAT_MASK (3<<12) +#define SLOW_RS123 (0<<12) +#define SLOW_RS23 (1<<12) +#define SLOW_RS3 (2<<12) +#define NORMAL_RS123 (3<<12) +#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ +#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ +#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ +#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ +#define RS_CSTATE_MASK (3<<4) +#define RS_CSTATE_C367_RS1 (0<<4) +#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) +#define RS_CSTATE_RSVD (2<<4) +#define RS_CSTATE_C367_RS2 (3<<4) +#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ +#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ #define VIDCTL 0x111c0 #define VIDSTS 0x111c8 #define VIDSTART 0x111cc /* 8 bits */ #define MEMSTAT_ILK 0x111f8 -#define MEMSTAT_VID_MASK 0x7f00 -#define MEMSTAT_VID_SHIFT 8 -#define MEMSTAT_PSTATE_MASK 0x00f8 -#define MEMSTAT_PSTATE_SHIFT 3 -#define MEMSTAT_MON_ACTV (1<<2) -#define MEMSTAT_SRC_CTL_MASK 0x0003 -#define MEMSTAT_SRC_CTL_CORE 0 -#define MEMSTAT_SRC_CTL_TRB 1 -#define MEMSTAT_SRC_CTL_THM 2 -#define MEMSTAT_SRC_CTL_STDBY 3 +#define MEMSTAT_VID_MASK 0x7f00 +#define MEMSTAT_VID_SHIFT 8 +#define MEMSTAT_PSTATE_MASK 0x00f8 +#define MEMSTAT_PSTATE_SHIFT 3 +#define MEMSTAT_MON_ACTV (1<<2) +#define MEMSTAT_SRC_CTL_MASK 0x0003 +#define MEMSTAT_SRC_CTL_CORE 0 +#define MEMSTAT_SRC_CTL_TRB 1 +#define MEMSTAT_SRC_CTL_THM 2 +#define MEMSTAT_SRC_CTL_STDBY 3 #define RCPREVBSYTUPAVG 0x113b8 #define RCPREVBSYTDNAVG 0x113bc #define PMMISC 0x11214 -#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ +#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ #define SDEW 0x1124c #define CSIEW0 0x11250 #define CSIEW1 0x11254 @@ -1330,9 +1330,9 @@ #define RPPREVBSYTUPAVG 0x113b8 #define RPPREVBSYTDNAVG 0x113bc #define ECR 0x11600 -#define ECR_GPFE (1<<31) -#define ECR_IMONE (1<<30) -#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ +#define ECR_GPFE (1<<31) +#define ECR_IMONE (1<<30) +#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ #define OGW0 0x11608 #define OGW1 0x1160c #define EG0 0x11610 @@ -1346,7 +1346,7 @@ #define PXW 0x11664 #define PXWL 0x11680 #define LCFUSE02 0x116c0 -#define LCFUSE_HIV_MASK 0x000000ff +#define LCFUSE_HIV_MASK 0x000000ff #define CSIPLL0 0x12c10 #define DDRMPLL1 0X12c20 #define PEG_BAND_GAP_DATA 0x14d68 @@ -1362,7 +1362,7 @@ * Logical Context regs */ #define CCID 0x2180 -#define CCID_EN (1<<0) +#define CCID_EN (1<<0) /* * Overlay regs */ @@ -1415,42 +1415,42 @@
/* VGA port control */ #define ADPA 0x61100 -#define ADPA_DAC_ENABLE (1<<31) -#define ADPA_DAC_DISABLE 0 -#define ADPA_PIPE_SELECT_MASK (1<<30) -#define ADPA_PIPE_A_SELECT 0 -#define ADPA_PIPE_B_SELECT (1<<30) -#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) -#define ADPA_USE_VGA_HVPOLARITY (1<<15) -#define ADPA_SETS_HVPOLARITY 0 -#define ADPA_VSYNC_CNTL_DISABLE (1<<11) -#define ADPA_VSYNC_CNTL_ENABLE 0 -#define ADPA_HSYNC_CNTL_DISABLE (1<<10) -#define ADPA_HSYNC_CNTL_ENABLE 0 -#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) -#define ADPA_VSYNC_ACTIVE_LOW 0 -#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) -#define ADPA_HSYNC_ACTIVE_LOW 0 -#define ADPA_DPMS_MASK (~(3<<10)) -#define ADPA_DPMS_ON (0<<10) -#define ADPA_DPMS_SUSPEND (1<<10) -#define ADPA_DPMS_STANDBY (2<<10) -#define ADPA_DPMS_OFF (3<<10) +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 +#define ADPA_DPMS_MASK (~(3<<10)) +#define ADPA_DPMS_ON (0<<10) +#define ADPA_DPMS_SUSPEND (1<<10) +#define ADPA_DPMS_STANDBY (2<<10) +#define ADPA_DPMS_OFF (3<<10)
/* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 -#define HDMIB_HOTPLUG_INT_EN (1 << 29) -#define DPB_HOTPLUG_INT_EN (1 << 29) -#define HDMIC_HOTPLUG_INT_EN (1 << 28) -#define DPC_HOTPLUG_INT_EN (1 << 28) -#define HDMID_HOTPLUG_INT_EN (1 << 27) -#define DPD_HOTPLUG_INT_EN (1 << 27) -#define SDVOB_HOTPLUG_INT_EN (1 << 26) -#define SDVOC_HOTPLUG_INT_EN (1 << 25) -#define TV_HOTPLUG_INT_EN (1 << 18) -#define CRT_HOTPLUG_INT_EN (1 << 9) -#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) +#define HDMIB_HOTPLUG_INT_EN (1 << 29) +#define DPB_HOTPLUG_INT_EN (1 << 29) +#define HDMIC_HOTPLUG_INT_EN (1 << 28) +#define DPC_HOTPLUG_INT_EN (1 << 28) +#define HDMID_HOTPLUG_INT_EN (1 << 27) +#define DPD_HOTPLUG_INT_EN (1 << 27) +#define SDVOB_HOTPLUG_INT_EN (1 << 26) +#define SDVOC_HOTPLUG_INT_EN (1 << 25) +#define TV_HOTPLUG_INT_EN (1 << 18) +#define CRT_HOTPLUG_INT_EN (1 << 9) +#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) /* must use period 64 on GM45 according to docs */ #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) @@ -1467,28 +1467,28 @@ #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
#define PORT_HOTPLUG_STAT 0x61114 -#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) -#define DPB_HOTPLUG_INT_STATUS (1 << 29) -#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) -#define DPC_HOTPLUG_INT_STATUS (1 << 28) -#define HDMID_HOTPLUG_INT_STATUS (1 << 27) -#define DPD_HOTPLUG_INT_STATUS (1 << 27) -#define CRT_HOTPLUG_INT_STATUS (1 << 11) -#define TV_HOTPLUG_INT_STATUS (1 << 10) -#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) -#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) -#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) -#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) -#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) -#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) +#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +#define DPB_HOTPLUG_INT_STATUS (1 << 29) +#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +#define DPC_HOTPLUG_INT_STATUS (1 << 28) +#define HDMID_HOTPLUG_INT_STATUS (1 << 27) +#define DPD_HOTPLUG_INT_STATUS (1 << 27) +#define CRT_HOTPLUG_INT_STATUS (1 << 11) +#define TV_HOTPLUG_INT_STATUS (1 << 10) +#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
/* SDVO port control */ #define SDVOB 0x61140 #define SDVOC 0x61160 -#define SDVO_ENABLE (1 << 31) -#define SDVO_PIPE_B_SELECT (1 << 30) -#define SDVO_STALL_SELECT (1 << 29) -#define SDVO_INTERRUPT_ENABLE (1 << 26) +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) /** * 915G/GM SDVO pixel multiplier. * @@ -1496,62 +1496,62 @@ * * \sa DPLL_MD_UDI_MULTIPLIER_MASK */ -#define SDVO_PORT_MULTIPLY_MASK (7 << 23) -#define SDVO_PORT_MULTIPLY_SHIFT 23 -#define SDVO_PHASE_SELECT_MASK (15 << 19) -#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) -#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) -#define SDVOC_GANG_MODE (1 << 16) -#define SDVO_ENCODING_SDVO (0x0 << 10) -#define SDVO_ENCODING_HDMI (0x2 << 10) +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) /** Requird for HDMI operation */ -#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) -#define SDVO_COLOR_RANGE_16_235 (1 << 8) -#define SDVO_BORDER_ENABLE (1 << 7) -#define SDVO_AUDIO_ENABLE (1 << 6) +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) +#define SDVO_COLOR_RANGE_16_235 (1 << 8) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) /** New with 965, default is to be set */ -#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) /** New with 965, default is to be set */ -#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define SDVOB_PCIE_CONCURRENCY (1 << 3) -#define SDVO_DETECTED (1 << 2) +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ -#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) -#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26)) +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26)) +#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
/* DVO port control */ #define DVOA 0x61120 #define DVOB 0x61140 #define DVOC 0x61160 -#define DVO_ENABLE (1 << 31) -#define DVO_PIPE_B_SELECT (1 << 30) -#define DVO_PIPE_STALL_UNUSED (0 << 28) -#define DVO_PIPE_STALL (1 << 28) -#define DVO_PIPE_STALL_TV (2 << 28) -#define DVO_PIPE_STALL_MASK (3 << 28) -#define DVO_USE_VGA_SYNC (1 << 15) -#define DVO_DATA_ORDER_I740 (0 << 14) -#define DVO_DATA_ORDER_FP (1 << 14) -#define DVO_VSYNC_DISABLE (1 << 11) -#define DVO_HSYNC_DISABLE (1 << 10) -#define DVO_VSYNC_TRISTATE (1 << 9) -#define DVO_HSYNC_TRISTATE (1 << 8) -#define DVO_BORDER_ENABLE (1 << 7) -#define DVO_DATA_ORDER_GBRG (1 << 6) -#define DVO_DATA_ORDER_RGGB (0 << 6) -#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) -#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) -#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) -#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) -#define DVO_BLANK_ACTIVE_HIGH (1 << 2) -#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ -#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ -#define DVO_PRESERVE_MASK (0x7<<24) +#define DVO_ENABLE (1 << 31) +#define DVO_PIPE_B_SELECT (1 << 30) +#define DVO_PIPE_STALL_UNUSED (0 << 28) +#define DVO_PIPE_STALL (1 << 28) +#define DVO_PIPE_STALL_TV (2 << 28) +#define DVO_PIPE_STALL_MASK (3 << 28) +#define DVO_USE_VGA_SYNC (1 << 15) +#define DVO_DATA_ORDER_I740 (0 << 14) +#define DVO_DATA_ORDER_FP (1 << 14) +#define DVO_VSYNC_DISABLE (1 << 11) +#define DVO_HSYNC_DISABLE (1 << 10) +#define DVO_VSYNC_TRISTATE (1 << 9) +#define DVO_HSYNC_TRISTATE (1 << 8) +#define DVO_BORDER_ENABLE (1 << 7) +#define DVO_DATA_ORDER_GBRG (1 << 6) +#define DVO_DATA_ORDER_RGGB (0 << 6) +#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) +#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) +#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) +#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) +#define DVO_BLANK_ACTIVE_HIGH (1 << 2) +#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ +#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ +#define DVO_PRESERVE_MASK (0x7<<24) #define DVOA_SRCDIM 0x61124 #define DVOB_SRCDIM 0x61144 #define DVOC_SRCDIM 0x61164 -#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 -#define DVO_SRCDIM_VERTICAL_SHIFT 0 +#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 +#define DVO_SRCDIM_VERTICAL_SHIFT 0
/* LVDS port control */ #define LVDS 0x61180 @@ -1559,70 +1559,70 @@ * Enables the LVDS port. This bit must be set before DPLLs are enabled, as * the DPLL semantics change when the LVDS is assigned to that pipe. */ -#define LVDS_PORT_EN (1 << 31) +#define LVDS_PORT_EN (1 << 31) /* Selects pipe B for LVDS data. Must be set on pre-965. */ -#define LVDS_PIPEB_SELECT (1 << 30) -#define LVDS_PIPE_MASK (1 << 30) -#define LVDS_PIPE(pipe) ((pipe) << 30) +#define LVDS_PIPEB_SELECT (1 << 30) +#define LVDS_PIPE_MASK (1 << 30) +#define LVDS_PIPE(pipe) ((pipe) << 30) /* LVDS dithering flag on 965/g4x platform */ -#define LVDS_ENABLE_DITHER (1 << 25) +#define LVDS_ENABLE_DITHER (1 << 25) /* LVDS sync polarity flags. Set to invert (i.e. negative) */ -#define LVDS_VSYNC_POLARITY (1 << 21) -#define LVDS_HSYNC_POLARITY (1 << 20) +#define LVDS_VSYNC_POLARITY (1 << 21) +#define LVDS_HSYNC_POLARITY (1 << 20)
/* Enable border for unscaled (or aspect-scaled) display */ -#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_BORDER_ENABLE (1 << 15) /* * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per * pixel. */ -#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) -#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) -#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) /* * Controls the A3 data pair, which contains the additional LSBs for 24 bit * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be * on. */ -#define LVDS_A3_POWER_MASK (3 << 6) -#define LVDS_A3_POWER_DOWN (0 << 6) -#define LVDS_A3_POWER_UP (3 << 6) +#define LVDS_A3_POWER_MASK (3 << 6) +#define LVDS_A3_POWER_DOWN (0 << 6) +#define LVDS_A3_POWER_UP (3 << 6) /* * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP * is set. */ -#define LVDS_CLKB_POWER_MASK (3 << 4) -#define LVDS_CLKB_POWER_DOWN (0 << 4) -#define LVDS_CLKB_POWER_UP (3 << 4) +#define LVDS_CLKB_POWER_MASK (3 << 4) +#define LVDS_CLKB_POWER_DOWN (0 << 4) +#define LVDS_CLKB_POWER_UP (3 << 4) /* * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 * setting for whether we are in dual-channel mode. The B3 pair will * additionally only be powered up when LVDS_A3_POWER_UP is set. */ -#define LVDS_B0B3_POWER_MASK (3 << 2) -#define LVDS_B0B3_POWER_DOWN (0 << 2) -#define LVDS_B0B3_POWER_UP (3 << 2) +#define LVDS_B0B3_POWER_MASK (3 << 2) +#define LVDS_B0B3_POWER_DOWN (0 << 2) +#define LVDS_B0B3_POWER_UP (3 << 2)
/* Video Data Island Packet control */ #define VIDEO_DIP_DATA 0x61178 #define VIDEO_DIP_CTL 0x61170 -#define VIDEO_DIP_ENABLE (1 << 31) -#define VIDEO_DIP_PORT_B (1 << 29) -#define VIDEO_DIP_PORT_C (2 << 29) -#define VIDEO_DIP_ENABLE_AVI (1 << 21) -#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) -#define VIDEO_DIP_ENABLE_SPD (8 << 21) -#define VIDEO_DIP_SELECT_AVI (0 << 19) -#define VIDEO_DIP_SELECT_VENDOR (1 << 19) -#define VIDEO_DIP_SELECT_SPD (3 << 19) -#define VIDEO_DIP_SELECT_MASK (3 << 19) -#define VIDEO_DIP_FREQ_ONCE (0 << 16) -#define VIDEO_DIP_FREQ_VSYNC (1 << 16) -#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_ENABLE (1 << 31) +#define VIDEO_DIP_PORT_B (1 << 29) +#define VIDEO_DIP_PORT_C (2 << 29) +#define VIDEO_DIP_ENABLE_AVI (1 << 21) +#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) +#define VIDEO_DIP_ENABLE_SPD (8 << 21) +#define VIDEO_DIP_SELECT_AVI (0 << 19) +#define VIDEO_DIP_SELECT_VENDOR (1 << 19) +#define VIDEO_DIP_SELECT_SPD (3 << 19) +#define VIDEO_DIP_SELECT_MASK (3 << 19) +#define VIDEO_DIP_FREQ_ONCE (0 << 16) +#define VIDEO_DIP_FREQ_VSYNC (1 << 16) +#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
/* Panel power sequencing */ #define PP_STATUS 0x61200 -#define PP_ON (1 << 31) +#define PP_ON (1 << 31) /* * Indicates that all dependencies of the panel are on: * @@ -1630,51 +1630,51 @@ * - pipe enabled * - LVDS/DVOB/DVOC on */ -#define PP_READY (1 << 30) -#define PP_SEQUENCE_NONE (0 << 28) -#define PP_SEQUENCE_POWER_UP (1 << 28) -#define PP_SEQUENCE_POWER_DOWN (2 << 28) -#define PP_SEQUENCE_MASK (3 << 28) -#define PP_SEQUENCE_SHIFT 28 -#define PP_CYCLE_DELAY_ACTIVE (1 << 27) -#define PP_SEQUENCE_STATE_MASK 0x0000000f -#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) -#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) -#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) -#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) -#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) -#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) -#define PP_SEQUENCE_STATE_RESET (0xf << 0) +#define PP_READY (1 << 30) +#define PP_SEQUENCE_NONE (0 << 28) +#define PP_SEQUENCE_POWER_UP (1 << 28) +#define PP_SEQUENCE_POWER_DOWN (2 << 28) +#define PP_SEQUENCE_MASK (3 << 28) +#define PP_SEQUENCE_SHIFT 28 +#define PP_CYCLE_DELAY_ACTIVE (1 << 27) +#define PP_SEQUENCE_STATE_MASK 0x0000000f +#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) +#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) +#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) +#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) +#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) +#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) +#define PP_SEQUENCE_STATE_RESET (0xf << 0) #define PP_CONTROL 0x61204 -#define POWER_TARGET_ON (1 << 0) +#define POWER_TARGET_ON (1 << 0) #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210
/* Panel fitting */ #define PFIT_CONTROL 0x61230 -#define PFIT_ENABLE (1 << 31) -#define PFIT_PIPE_MASK (3 << 29) -#define PFIT_PIPE_SHIFT 29 -#define VERT_INTERP_DISABLE (0 << 10) -#define VERT_INTERP_BILINEAR (1 << 10) -#define VERT_INTERP_MASK (3 << 10) -#define VERT_AUTO_SCALE (1 << 9) -#define HORIZ_INTERP_DISABLE (0 << 6) -#define HORIZ_INTERP_BILINEAR (1 << 6) -#define HORIZ_INTERP_MASK (3 << 6) -#define HORIZ_AUTO_SCALE (1 << 5) -#define PANEL_8TO6_DITHER_ENABLE (1 << 3) -#define PFIT_FILTER_FUZZY (0 << 24) -#define PFIT_SCALING_AUTO (0 << 26) -#define PFIT_SCALING_PROGRAMMED (1 << 26) -#define PFIT_SCALING_PILLAR (2 << 26) -#define PFIT_SCALING_LETTER (3 << 26) +#define PFIT_ENABLE (1 << 31) +#define PFIT_PIPE_MASK (3 << 29) +#define PFIT_PIPE_SHIFT 29 +#define VERT_INTERP_DISABLE (0 << 10) +#define VERT_INTERP_BILINEAR (1 << 10) +#define VERT_INTERP_MASK (3 << 10) +#define VERT_AUTO_SCALE (1 << 9) +#define HORIZ_INTERP_DISABLE (0 << 6) +#define HORIZ_INTERP_BILINEAR (1 << 6) +#define HORIZ_INTERP_MASK (3 << 6) +#define HORIZ_AUTO_SCALE (1 << 5) +#define PANEL_8TO6_DITHER_ENABLE (1 << 3) +#define PFIT_FILTER_FUZZY (0 << 24) +#define PFIT_SCALING_AUTO (0 << 26) +#define PFIT_SCALING_PROGRAMMED (1 << 26) +#define PFIT_SCALING_PILLAR (2 << 26) +#define PFIT_SCALING_LETTER (3 << 26) #define PFIT_PGM_RATIOS 0x61234 -#define PFIT_VERT_SCALE_MASK 0xfff00000 -#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 +#define PFIT_VERT_SCALE_MASK 0xfff00000 +#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 /* Pre-965 */ #define PFIT_VERT_SCALE_SHIFT 20 #define PFIT_VERT_SCALE_MASK 0xfff00000 @@ -1690,17 +1690,17 @@
/* Backlight control */ #define BLC_PWM_CTL 0x61254 -#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) #define BLC_PWM_CTL2 0x61250 /* 965+ only */ -#define BLM_COMBINATION_MODE (1 << 30) +#define BLM_COMBINATION_MODE (1 << 30) /* * This is the most significant 15 bits of the number of backlight cycles in a * complete cycle of the modulated backlight control. * * The actual value is this field multiplied by two. */ -#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) -#define BLM_LEGACY_MODE (1 << 16) +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) /* * This is the number of cycles out of the backlight modulation cycle for which * the backlight is on. @@ -1708,8 +1708,8 @@ * This field must be no greater than the number of cycles in the complete * backlight modulation cycle. */ -#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) -#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
#define BLC_HIST_CTL 0x61260
@@ -2199,82 +2199,82 @@ #define DP_C 0x64200 #define DP_D 0x64300
-#define DP_PORT_EN (1 << 31) -#define DP_PIPEB_SELECT (1 << 30) -#define DP_PIPE_MASK (1 << 30) +#define DP_PORT_EN (1 << 31) +#define DP_PIPEB_SELECT (1 << 30) +#define DP_PIPE_MASK (1 << 30)
/* Link training mode - select a suitable mode for each stage */ -#define DP_LINK_TRAIN_PAT_1 (0 << 28) -#define DP_LINK_TRAIN_PAT_2 (1 << 28) -#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) -#define DP_LINK_TRAIN_OFF (3 << 28) -#define DP_LINK_TRAIN_MASK (3 << 28) -#define DP_LINK_TRAIN_SHIFT 28 +#define DP_LINK_TRAIN_PAT_1 (0 << 28) +#define DP_LINK_TRAIN_PAT_2 (1 << 28) +#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) +#define DP_LINK_TRAIN_OFF (3 << 28) +#define DP_LINK_TRAIN_MASK (3 << 28) +#define DP_LINK_TRAIN_SHIFT 28
/* CPT Link training mode */ -#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) -#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) -#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) -#define DP_LINK_TRAIN_OFF_CPT (3 << 8) -#define DP_LINK_TRAIN_MASK_CPT (7 << 8) -#define DP_LINK_TRAIN_SHIFT_CPT 8 +#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) +#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) +#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) +#define DP_LINK_TRAIN_OFF_CPT (3 << 8) +#define DP_LINK_TRAIN_MASK_CPT (7 << 8) +#define DP_LINK_TRAIN_SHIFT_CPT 8
/* Signal voltages. These are mostly controlled by the other end */ -#define DP_VOLTAGE_0_4 (0 << 25) -#define DP_VOLTAGE_0_6 (1 << 25) -#define DP_VOLTAGE_0_8 (2 << 25) -#define DP_VOLTAGE_1_2 (3 << 25) -#define DP_VOLTAGE_MASK (7 << 25) -#define DP_VOLTAGE_SHIFT 25 +#define DP_VOLTAGE_0_4 (0 << 25) +#define DP_VOLTAGE_0_6 (1 << 25) +#define DP_VOLTAGE_0_8 (2 << 25) +#define DP_VOLTAGE_1_2 (3 << 25) +#define DP_VOLTAGE_MASK (7 << 25) +#define DP_VOLTAGE_SHIFT 25
/* Signal pre-emphasis levels, like voltages, the other end tells us what * they want */ -#define DP_PRE_EMPHASIS_0 (0 << 22) -#define DP_PRE_EMPHASIS_3_5 (1 << 22) -#define DP_PRE_EMPHASIS_6 (2 << 22) -#define DP_PRE_EMPHASIS_9_5 (3 << 22) -#define DP_PRE_EMPHASIS_MASK (7 << 22) -#define DP_PRE_EMPHASIS_SHIFT 22 +#define DP_PRE_EMPHASIS_0 (0 << 22) +#define DP_PRE_EMPHASIS_3_5 (1 << 22) +#define DP_PRE_EMPHASIS_6 (2 << 22) +#define DP_PRE_EMPHASIS_9_5 (3 << 22) +#define DP_PRE_EMPHASIS_MASK (7 << 22) +#define DP_PRE_EMPHASIS_SHIFT 22
/* How many wires to use. I guess 3 was too hard */ -#define DP_PORT_WIDTH_1 (0 << 19) -#define DP_PORT_WIDTH_2 (1 << 19) -#define DP_PORT_WIDTH_4 (3 << 19) -#define DP_PORT_WIDTH_MASK (7 << 19) +#define DP_PORT_WIDTH_1 (0 << 19) +#define DP_PORT_WIDTH_2 (1 << 19) +#define DP_PORT_WIDTH_4 (3 << 19) +#define DP_PORT_WIDTH_MASK (7 << 19)
/* Mystic DPCD version 1.1 special mode */ -#define DP_ENHANCED_FRAMING (1 << 18) +#define DP_ENHANCED_FRAMING (1 << 18)
/* eDP */ -#define DP_PLL_FREQ_270MHZ (0 << 16) -#define DP_PLL_FREQ_160MHZ (1 << 16) -#define DP_PLL_FREQ_MASK (3 << 16) +#define DP_PLL_FREQ_270MHZ (0 << 16) +#define DP_PLL_FREQ_160MHZ (1 << 16) +#define DP_PLL_FREQ_MASK (3 << 16)
/** locked once port is enabled */ -#define DP_PORT_REVERSAL (1 << 15) +#define DP_PORT_REVERSAL (1 << 15)
/* eDP */ -#define DP_PLL_ENABLE (1 << 14) +#define DP_PLL_ENABLE (1 << 14)
/** sends the clock on lane 15 of the PEG for debug */ -#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) +#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
-#define DP_SCRAMBLING_DISABLE (1 << 12) -#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) +#define DP_SCRAMBLING_DISABLE (1 << 12) +#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
/** limit RGB values to avoid confusing TVs */ -#define DP_COLOR_RANGE_16_235 (1 << 8) +#define DP_COLOR_RANGE_16_235 (1 << 8)
/** Turn on the audio link */ -#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) +#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
/** vs and hs sync polarity */ -#define DP_SYNC_VS_HIGH (1 << 4) -#define DP_SYNC_HS_HIGH (1 << 3) +#define DP_SYNC_VS_HIGH (1 << 4) +#define DP_SYNC_HS_HIGH (1 << 3)
/** A fantasy */ -#define DP_DETECTED (1 << 2) +#define DP_DETECTED (1 << 2)
/** The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported @@ -2309,27 +2309,27 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324
-#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) -#define DP_AUX_CH_CTL_DONE (1 << 30) -#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) -#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) -#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) -#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) -#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) -#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 -#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) -#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 -#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) -#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) -#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) -#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) -#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) -#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) +#define DP_AUX_CH_CTL_DONE (1 << 30) +#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) +#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) +#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) +#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) +#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) +#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 +#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) +#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 +#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) +#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) +#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) +#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) +#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) +#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
/* * Computing GMCH M and N values for the Display Port link @@ -2348,14 +2348,14 @@ #define _PIPEB_GMCH_DATA_M 0x71050
/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ -#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) -#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 +#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) +#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
-#define PIPE_GMCH_DATA_M_MASK (0xffffff) +#define PIPE_GMCH_DATA_M_MASK (0xffffff)
#define _PIPEA_GMCH_DATA_N 0x70054 #define _PIPEB_GMCH_DATA_N 0x71054 -#define PIPE_GMCH_DATA_N_MASK (0xffffff) +#define PIPE_GMCH_DATA_N_MASK (0xffffff)
/* * Computing Link M and N values for the Display Port link @@ -2370,11 +2370,11 @@
#define _PIPEA_DP_LINK_M 0x70060 #define _PIPEB_DP_LINK_M 0x71060 -#define PIPEA_DP_LINK_M_MASK (0xffffff) +#define PIPEA_DP_LINK_M_MASK (0xffffff)
#define _PIPEA_DP_LINK_N 0x70064 #define _PIPEB_DP_LINK_N 0x71064 -#define PIPEA_DP_LINK_N_MASK (0xffffff) +#define PIPEA_DP_LINK_N_MASK (0xffffff)
#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) @@ -2385,81 +2385,81 @@
/* Pipe A */ #define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff +#define DSL_LINEMASK 0x00000fff #define _PIPEACONF 0x70008 -#define PIPECONF_ENABLE (1<<31) -#define PIPECONF_DISABLE 0 -#define PIPECONF_DOUBLE_WIDE (1<<30) -#define I965_PIPECONF_ACTIVE (1<<30) -#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) -#define PIPECONF_SINGLE_WIDE 0 -#define PIPECONF_PIPE_UNLOCKED 0 -#define PIPECONF_PIPE_LOCKED (1<<25) -#define PIPECONF_PALETTE 0 -#define PIPECONF_GAMMA (1<<24) -#define PIPECONF_FORCE_BORDER (1<<25) -#define PIPECONF_INTERLACE_MASK (7 << 21) +#define PIPECONF_ENABLE (1<<31) +#define PIPECONF_DISABLE 0 +#define PIPECONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) +#define PIPECONF_SINGLE_WIDE 0 +#define PIPECONF_PIPE_UNLOCKED 0 +#define PIPECONF_PIPE_LOCKED (1<<25) +#define PIPECONF_PALETTE 0 +#define PIPECONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_INTERLACE_MASK (7 << 21) /* Note that pre-gen3 does not support interlaced display directly. Panel * fitting must be disabled on pre-ilk for interlaced. */ -#define PIPECONF_PROGRESSIVE (0 << 21) -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ -#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ /* Ironlake and later have a complete new set of values for interlaced. PFIT * means panel fitter required, PF means progressive fetch, DBL means power * saving pixel doubling. */ -#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) -#define PIPECONF_INTERLACED_ILK (3 << 21) -#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ -#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ -#define PIPECONF_CXSR_DOWNCLOCK (1<<16) -#define PIPECONF_BPP_MASK (0x000000e0) -#define PIPECONF_BPP_8 (0<<5) -#define PIPECONF_BPP_10 (1<<5) -#define PIPECONF_BPP_6 (2<<5) -#define PIPECONF_BPP_12 (3<<5) -#define PIPECONF_DITHER_EN (1<<4) -#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) -#define PIPECONF_DITHER_TYPE_SP (0<<2) -#define PIPECONF_DITHER_TYPE_ST1 (1<<2) -#define PIPECONF_DITHER_TYPE_ST2 (2<<2) -#define PIPECONF_DITHER_TYPE_TEMP (3<<2) +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) +#define PIPECONF_INTERLACED_ILK (3 << 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ +#define PIPECONF_CXSR_DOWNCLOCK (1<<16) +#define PIPECONF_BPP_MASK (0x000000e0) +#define PIPECONF_BPP_8 (0<<5) +#define PIPECONF_BPP_10 (1<<5) +#define PIPECONF_BPP_6 (2<<5) +#define PIPECONF_BPP_12 (3<<5) +#define PIPECONF_DITHER_EN (1<<4) +#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) +#define PIPECONF_DITHER_TYPE_SP (0<<2) +#define PIPECONF_DITHER_TYPE_ST1 (1<<2) +#define PIPECONF_DITHER_TYPE_ST2 (2<<2) +#define PIPECONF_DITHER_TYPE_TEMP (3<<2) #define _PIPEASTAT 0x70024 -#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) -#define PIPE_CRC_ERROR_ENABLE (1UL<<29) -#define PIPE_CRC_DONE_ENABLE (1UL<<28) -#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) -#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) -#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) -#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) -#define PIPE_DPST_EVENT_ENABLE (1UL<<23) -#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) -#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) -#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) -#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) -#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) -#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) -#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) -#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) -#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) -#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) -#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) -#define PIPE_DPST_EVENT_STATUS (1UL<<7) -#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) -#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) -#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) -#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ -#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ -#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) -#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) -#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ -#define PIPE_8BPC (0 << 5) -#define PIPE_10BPC (1 << 5) -#define PIPE_6BPC (2 << 5) -#define PIPE_12BPC (3 << 5) +#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) +#define PIPE_CRC_ERROR_ENABLE (1UL<<29) +#define PIPE_CRC_DONE_ENABLE (1UL<<28) +#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) +#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) +#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) +#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) +#define PIPE_DPST_EVENT_ENABLE (1UL<<23) +#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) +#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) +#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) +#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) +#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) +#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) +#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) +#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) +#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) +#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) +#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) +#define PIPE_DPST_EVENT_STATUS (1UL<<7) +#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) +#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) +#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) +#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ +#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ +#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) +#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) +#define PIPE_BPC_MASK (7 << 5) /* Ironlake */ +#define PIPE_8BPC (0 << 5) +#define PIPE_10BPC (1 << 5) +#define PIPE_6BPC (2 << 5) +#define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) @@ -2469,33 +2469,33 @@ #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
#define DSPARB 0x70030 -#define DSPARB_CSTART_MASK (0x7f << 7) -#define DSPARB_CSTART_SHIFT 7 -#define DSPARB_BSTART_MASK (0x7f) -#define DSPARB_BSTART_SHIFT 0 -#define DSPARB_BEND_SHIFT 9 /* on 855 */ -#define DSPARB_AEND_SHIFT 0 +#define DSPARB_CSTART_MASK (0x7f << 7) +#define DSPARB_CSTART_SHIFT 7 +#define DSPARB_BSTART_MASK (0x7f) +#define DSPARB_BSTART_SHIFT 0 +#define DSPARB_BEND_SHIFT 9 /* on 855 */ +#define DSPARB_AEND_SHIFT 0
#define DSPFW1 0x70034 -#define DSPFW_SR_SHIFT 23 -#define DSPFW_SR_MASK (0x1ff<<23) -#define DSPFW_CURSORB_SHIFT 16 -#define DSPFW_CURSORB_MASK (0x3f<<16) -#define DSPFW_PLANEB_SHIFT 8 -#define DSPFW_PLANEB_MASK (0x7f<<8) -#define DSPFW_PLANEA_MASK (0x7f) +#define DSPFW_SR_SHIFT 23 +#define DSPFW_SR_MASK (0x1ff<<23) +#define DSPFW_CURSORB_SHIFT 16 +#define DSPFW_CURSORB_MASK (0x3f<<16) +#define DSPFW_PLANEB_SHIFT 8 +#define DSPFW_PLANEB_MASK (0x7f<<8) +#define DSPFW_PLANEA_MASK (0x7f) #define DSPFW2 0x70038 -#define DSPFW_CURSORA_MASK 0x00003f00 -#define DSPFW_CURSORA_SHIFT 8 -#define DSPFW_PLANEC_MASK (0x7f) +#define DSPFW_CURSORA_MASK 0x00003f00 +#define DSPFW_CURSORA_SHIFT 8 +#define DSPFW_PLANEC_MASK (0x7f) #define DSPFW3 0x7003c -#define DSPFW_HPLL_SR_EN (1<<31) -#define DSPFW_CURSOR_SR_SHIFT 24 -#define PINEVIEW_SELF_REFRESH_EN (1<<30) -#define DSPFW_CURSOR_SR_MASK (0x3f<<24) -#define DSPFW_HPLL_CURSOR_SHIFT 16 -#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) -#define DSPFW_HPLL_SR_MASK (0x1ff) +#define DSPFW_HPLL_SR_EN (1<<31) +#define DSPFW_CURSOR_SR_SHIFT 24 +#define PINEVIEW_SELF_REFRESH_EN (1<<30) +#define DSPFW_CURSOR_SR_MASK (0x3f<<24) +#define DSPFW_HPLL_CURSOR_SHIFT 16 +#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) +#define DSPFW_HPLL_SR_MASK (0x1ff)
/* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 @@ -2623,22 +2623,22 @@ * * do { * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT; + * PIPE_FRAME_HIGH_SHIFT; * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> - * PIPE_FRAME_LOW_SHIFT); + * PIPE_FRAME_LOW_SHIFT); * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> - * PIPE_FRAME_HIGH_SHIFT); + * PIPE_FRAME_HIGH_SHIFT); * } while (high1 != high2); * frame = (high1 << 8) | low1; */ -#define _PIPEAFRAMEHIGH 0x70040 -#define PIPE_FRAME_HIGH_MASK 0x0000ffff -#define PIPE_FRAME_HIGH_SHIFT 0 -#define _PIPEAFRAMEPIXEL 0x70044 -#define PIPE_FRAME_LOW_MASK 0xff000000 -#define PIPE_FRAME_LOW_SHIFT 24 -#define PIPE_PIXEL_MASK 0x00ffffff -#define PIPE_PIXEL_SHIFT 0 +#define _PIPEAFRAMEHIGH 0x70040 +#define PIPE_FRAME_HIGH_MASK 0x0000ffff +#define PIPE_FRAME_HIGH_SHIFT 0 +#define _PIPEAFRAMEPIXEL 0x70044 +#define PIPE_FRAME_LOW_MASK 0xff000000 +#define PIPE_FRAME_LOW_SHIFT 24 +#define PIPE_PIXEL_MASK 0x00ffffff +#define PIPE_PIXEL_SHIFT 0 /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_GM45 0x70040 #define _PIPEA_FLIPCOUNT_GM45 0x70044 @@ -2647,31 +2647,31 @@ /* Cursor A & B regs */ #define _CURACNTR 0x70080 /* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE 0x80000000 -#define CURSOR_GAMMA_ENABLE 0x40000000 -#define CURSOR_STRIDE_MASK 0x30000000 -#define CURSOR_FORMAT_SHIFT 24 -#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) -#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) +#define CURSOR_ENABLE 0x80000000 +#define CURSOR_GAMMA_ENABLE 0x40000000 +#define CURSOR_STRIDE_MASK 0x30000000 +#define CURSOR_FORMAT_SHIFT 24 +#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) +#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) /* New style CUR*CNTR flags */ -#define CURSOR_MODE 0x27 -#define CURSOR_MODE_DISABLE 0x00 -#define CURSOR_MODE_64_32B_AX 0x07 -#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) -#define MCURSOR_PIPE_SELECT (1 << 28) -#define MCURSOR_PIPE_A 0x00 -#define MCURSOR_PIPE_B (1 << 28) -#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define CURSOR_MODE 0x27 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) +#define MCURSOR_PIPE_SELECT (1 << 28) +#define MCURSOR_PIPE_A 0x00 +#define MCURSOR_PIPE_B (1 << 28) +#define MCURSOR_GAMMA_ENABLE (1 << 26) #define _CURABASE 0x70084 #define _CURAPOS 0x70088 -#define CURSOR_POS_MASK 0x007FF -#define CURSOR_POS_SIGN 0x8000 -#define CURSOR_X_SHIFT 0 -#define CURSOR_Y_SHIFT 16 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 #define CURSIZE 0x700a0 #define _CURBCNTR 0x700c0 #define _CURBBASE 0x700c4 @@ -2690,32 +2690,32 @@ #define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
/* Display A control */ -#define _DSPACNTR 0x70180 -#define DISPLAY_PLANE_ENABLE (1<<31) -#define DISPLAY_PLANE_DISABLE 0 -#define DISPPLANE_GAMMA_ENABLE (1<<30) -#define DISPPLANE_GAMMA_DISABLE 0 -#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) -#define DISPPLANE_8BPP (0x2<<26) -#define DISPPLANE_15_16BPP (0x4<<26) -#define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) -#define DISPPLANE_32BPP (0x7<<26) -#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) -#define DISPPLANE_STEREO_ENABLE (1<<25) -#define DISPPLANE_STEREO_DISABLE 0 -#define DISPPLANE_SEL_PIPE_SHIFT 24 -#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SEL_PIPE_A 0 -#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) -#define DISPPLANE_SRC_KEY_ENABLE (1<<22) -#define DISPPLANE_SRC_KEY_DISABLE 0 -#define DISPPLANE_LINE_DOUBLE (1<<20) -#define DISPPLANE_NO_LINE_DOUBLE 0 -#define DISPPLANE_STEREO_POLARITY_FIRST 0 -#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) -#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ -#define DISPPLANE_TILED (1<<10) +#define _DSPACNTR 0x70180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_SHIFT 24 +#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ +#define DISPPLANE_TILED (1<<10) #define _DSPAADDR 0x70184 #define _DSPASTRIDE 0x70188 #define _DSPAPOS 0x7018C /* reserved */ @@ -2758,10 +2758,10 @@
/* Display B control */ #define _DSPBCNTR 0x71180 -#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) -#define DISPPLANE_ALPHA_TRANS_DISABLE 0 -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) #define _DSPBADDR 0x71184 #define _DSPBSTRIDE 0x71188 #define _DSPBPOS 0x7118C @@ -2771,23 +2771,23 @@
/* Sprite A control */ #define _DVSACNTR 0x72180 -#define DVS_ENABLE (1<<31) -#define DVS_GAMMA_ENABLE (1<<30) -#define DVS_PIXFORMAT_MASK (3<<25) -#define DVS_FORMAT_YUV422 (0<<25) -#define DVS_FORMAT_RGBX101010 (1<<25) -#define DVS_FORMAT_RGBX888 (2<<25) -#define DVS_FORMAT_RGBX161616 (3<<25) -#define DVS_SOURCE_KEY (1<<22) -#define DVS_RGB_ORDER_XBGR (1<<20) -#define DVS_YUV_BYTE_ORDER_MASK (3<<16) -#define DVS_YUV_ORDER_YUYV (0<<16) -#define DVS_YUV_ORDER_UYVY (1<<16) -#define DVS_YUV_ORDER_YVYU (2<<16) -#define DVS_YUV_ORDER_VYUY (3<<16) -#define DVS_DEST_KEY (1<<2) -#define DVS_TRICKLE_FEED_DISABLE (1<<14) -#define DVS_TILED (1<<10) +#define DVS_ENABLE (1<<31) +#define DVS_GAMMA_ENABLE (1<<30) +#define DVS_PIXFORMAT_MASK (3<<25) +#define DVS_FORMAT_YUV422 (0<<25) +#define DVS_FORMAT_RGBX101010 (1<<25) +#define DVS_FORMAT_RGBX888 (2<<25) +#define DVS_FORMAT_RGBX161616 (3<<25) +#define DVS_SOURCE_KEY (1<<22) +#define DVS_RGB_ORDER_XBGR (1<<20) +#define DVS_YUV_BYTE_ORDER_MASK (3<<16) +#define DVS_YUV_ORDER_YUYV (0<<16) +#define DVS_YUV_ORDER_UYVY (1<<16) +#define DVS_YUV_ORDER_YVYU (2<<16) +#define DVS_YUV_ORDER_VYUY (3<<16) +#define DVS_DEST_KEY (1<<2) +#define DVS_TRICKLE_FEED_DISABLE (1<<14) +#define DVS_TILED (1<<10) #define _DVSALINOFF 0x72184 #define _DVSASTRIDE 0x72188 #define _DVSAPOS 0x7218c @@ -2799,13 +2799,13 @@ #define _DVSATILEOFF 0x721a4 #define _DVSASURFLIVE 0x721ac #define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE (1<<31) -#define DVS_FILTER_MASK (3<<29) -#define DVS_FILTER_MEDIUM (0<<29) -#define DVS_FILTER_ENHANCING (1<<29) -#define DVS_FILTER_SOFTENING (2<<29) -#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) +#define DVS_SCALE_ENABLE (1<<31) +#define DVS_FILTER_MASK (3<<29) +#define DVS_FILTER_MEDIUM (0<<29) +#define DVS_FILTER_ENHANCING (1<<29) +#define DVS_FILTER_SOFTENING (2<<29) +#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) #define _DVSAGAMC 0x72300
#define _DVSBCNTR 0x73180 @@ -2835,29 +2835,29 @@ #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE (1<<31) -#define SPRITE_GAMMA_ENABLE (1<<30) -#define SPRITE_PIXFORMAT_MASK (7<<25) -#define SPRITE_FORMAT_YUV422 (0<<25) -#define SPRITE_FORMAT_RGBX101010 (1<<25) -#define SPRITE_FORMAT_RGBX888 (2<<25) -#define SPRITE_FORMAT_RGBX161616 (3<<25) -#define SPRITE_FORMAT_YUV444 (4<<25) -#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ -#define SPRITE_CSC_ENABLE (1<<24) -#define SPRITE_SOURCE_KEY (1<<22) -#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) -#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ -#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) -#define SPRITE_YUV_ORDER_YUYV (0<<16) -#define SPRITE_YUV_ORDER_UYVY (1<<16) -#define SPRITE_YUV_ORDER_YVYU (2<<16) -#define SPRITE_YUV_ORDER_VYUY (3<<16) -#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) -#define SPRITE_INT_GAMMA_ENABLE (1<<13) -#define SPRITE_TILED (1<<10) -#define SPRITE_DEST_KEY (1<<2) +#define SPRITE_ENABLE (1<<31) +#define SPRITE_GAMMA_ENABLE (1<<30) +#define SPRITE_PIXFORMAT_MASK (7<<25) +#define SPRITE_FORMAT_YUV422 (0<<25) +#define SPRITE_FORMAT_RGBX101010 (1<<25) +#define SPRITE_FORMAT_RGBX888 (2<<25) +#define SPRITE_FORMAT_RGBX161616 (3<<25) +#define SPRITE_FORMAT_YUV444 (4<<25) +#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ +#define SPRITE_CSC_ENABLE (1<<24) +#define SPRITE_SOURCE_KEY (1<<22) +#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) +#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ +#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) +#define SPRITE_YUV_ORDER_YUYV (0<<16) +#define SPRITE_YUV_ORDER_UYVY (1<<16) +#define SPRITE_YUV_ORDER_YVYU (2<<16) +#define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) +#define SPRITE_INT_GAMMA_ENABLE (1<<13) +#define SPRITE_TILED (1<<10) +#define SPRITE_DEST_KEY (1<<2) #define _SPRA_LINOFF 0x70284 #define _SPRA_STRIDE 0x70288 #define _SPRA_POS 0x7028c @@ -2868,13 +2868,13 @@ #define _SPRA_KEYMAX 0x702a0 #define _SPRA_TILEOFF 0x702a4 #define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE (1<<31) -#define SPRITE_FILTER_MASK (3<<29) -#define SPRITE_FILTER_MEDIUM (0<<29) -#define SPRITE_FILTER_ENHANCING (1<<29) -#define SPRITE_FILTER_SOFTENING (2<<29) -#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) +#define SPRITE_SCALE_ENABLE (1<<31) +#define SPRITE_FILTER_MASK (3<<29) +#define SPRITE_FILTER_MEDIUM (0<<29) +#define SPRITE_FILTER_ENHANCING (1<<29) +#define SPRITE_FILTER_SOFTENING (2<<29) +#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ +#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) #define _SPRA_GAMC 0x70400
#define _SPRB_CTL 0x71280 @@ -2913,28 +2913,28 @@
#define CPU_VGACNTRL 0x41000
-#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 -#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) -#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) -#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) -#define DIGITAL_PORTA_NO_DETECT (0 << 0) -#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) +#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 +#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) +#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) +#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) +#define DIGITAL_PORTA_NO_DETECT (0 << 0) +#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) #define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
/* refresh rate hardware control */ -#define RR_HW_CTL 0x45300 -#define RR_HW_LOW_POWER_FRAMES_MASK 0xff -#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 +#define RR_HW_CTL 0x45300 +#define RR_HW_LOW_POWER_FRAMES_MASK 0xff +#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
#define FDI_PLL_BIOS_0 0x46000 #define FDI_PLL_FB_CLOCK_MASK 0xff #define FDI_PLL_BIOS_1 0x46004 #define FDI_PLL_BIOS_2 0x46008 -#define DISPLAY_PORT_PLL_BIOS_0 0x4600c -#define DISPLAY_PORT_PLL_BIOS_1 0x46010 -#define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define DISPLAY_PORT_PLL_BIOS_0 0x4600c +#define DISPLAY_PORT_PLL_BIOS_1 0x46010 +#define DISPLAY_PORT_PLL_BIOS_2 0x46014
#define PCH_DSPCLK_GATE_D 0x42020 # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) @@ -2949,47 +2949,47 @@ #define PCH_3DCGDIS1 0x46024 # define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-#define FDI_PLL_FREQ_CTL 0x46030 -#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) -#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 +#define FDI_PLL_FREQ_CTL 0x46030 +#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) +#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 #define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
-#define _PIPEA_DATA_M1 0x60030 -#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ -#define TU_SIZE_MASK 0x7e000000 -#define PIPE_DATA_M1_OFFSET 0 -#define _PIPEA_DATA_N1 0x60034 -#define PIPE_DATA_N1_OFFSET 0 +#define _PIPEA_DATA_M1 0x60030 +#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ +#define TU_SIZE_MASK 0x7e000000 +#define PIPE_DATA_M1_OFFSET 0 +#define _PIPEA_DATA_N1 0x60034 +#define PIPE_DATA_N1_OFFSET 0
-#define _PIPEA_DATA_M2 0x60038 -#define PIPE_DATA_M2_OFFSET 0 -#define _PIPEA_DATA_N2 0x6003c -#define PIPE_DATA_N2_OFFSET 0 +#define _PIPEA_DATA_M2 0x60038 +#define PIPE_DATA_M2_OFFSET 0 +#define _PIPEA_DATA_N2 0x6003c +#define PIPE_DATA_N2_OFFSET 0
-#define _PIPEA_LINK_M1 0x60040 -#define PIPE_LINK_M1_OFFSET 0 -#define _PIPEA_LINK_N1 0x60044 -#define PIPE_LINK_N1_OFFSET 0 +#define _PIPEA_LINK_M1 0x60040 +#define PIPE_LINK_M1_OFFSET 0 +#define _PIPEA_LINK_N1 0x60044 +#define PIPE_LINK_N1_OFFSET 0
-#define _PIPEA_LINK_M2 0x60048 -#define PIPE_LINK_M2_OFFSET 0 -#define _PIPEA_LINK_N2 0x6004c -#define PIPE_LINK_N2_OFFSET 0 +#define _PIPEA_LINK_M2 0x60048 +#define PIPE_LINK_M2_OFFSET 0 +#define _PIPEA_LINK_N2 0x6004c +#define PIPE_LINK_N2_OFFSET 0
/* PIPEB timing regs are same start from 0x61000 */
-#define _PIPEB_DATA_M1 0x61030 -#define _PIPEB_DATA_N1 0x61034 +#define _PIPEB_DATA_M1 0x61030 +#define _PIPEB_DATA_N1 0x61034
-#define _PIPEB_DATA_M2 0x61038 -#define _PIPEB_DATA_N2 0x6103c +#define _PIPEB_DATA_M2 0x61038 +#define _PIPEB_DATA_N2 0x6103c
-#define _PIPEB_LINK_M1 0x61040 -#define _PIPEB_LINK_N1 0x61044 +#define _PIPEB_LINK_M1 0x61040 +#define _PIPEB_LINK_N1 0x61044
-#define _PIPEB_LINK_M2 0x61048 -#define _PIPEB_LINK_N2 0x6104c +#define _PIPEB_LINK_M2 0x61048 +#define _PIPEB_LINK_N2 0x6104c
#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1) #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1) @@ -3002,9 +3002,9 @@
/* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_ENABLE (1<<31) +#define _PFA_CTL_1 0x68080 +#define _PFB_CTL_1 0x68880 +#define PF_ENABLE (1<<31) #define PF_FILTER_MASK (3<<23) #define PF_FILTER_PROGRAMMED (0<<23) #define PF_FILTER_MED_3x3 (1<<23) @@ -3026,35 +3026,35 @@ #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
/* legacy palette */ -#define _LGC_PALETTE_A 0x4a000 -#define _LGC_PALETTE_B 0x4a800 +#define _LGC_PALETTE_A 0x4a000 +#define _LGC_PALETTE_B 0x4a800 #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
/* interrupts */ -#define DE_MASTER_IRQ_CONTROL (1 << 31) -#define DE_SPRITEB_FLIP_DONE (1 << 29) -#define DE_SPRITEA_FLIP_DONE (1 << 28) -#define DE_PLANEB_FLIP_DONE (1 << 27) -#define DE_PLANEA_FLIP_DONE (1 << 26) -#define DE_PCU_EVENT (1 << 25) -#define DE_GTT_FAULT (1 << 24) -#define DE_POISON (1 << 23) -#define DE_PERFORM_COUNTER (1 << 22) -#define DE_PCH_EVENT (1 << 21) -#define DE_AUX_CHANNEL_A (1 << 20) -#define DE_DP_A_HOTPLUG (1 << 19) -#define DE_GSE (1 << 18) -#define DE_PIPEB_VBLANK (1 << 15) -#define DE_PIPEB_EVEN_FIELD (1 << 14) -#define DE_PIPEB_ODD_FIELD (1 << 13) -#define DE_PIPEB_LINE_COMPARE (1 << 12) -#define DE_PIPEB_VSYNC (1 << 11) +#define DE_MASTER_IRQ_CONTROL (1 << 31) +#define DE_SPRITEB_FLIP_DONE (1 << 29) +#define DE_SPRITEA_FLIP_DONE (1 << 28) +#define DE_PLANEB_FLIP_DONE (1 << 27) +#define DE_PLANEA_FLIP_DONE (1 << 26) +#define DE_PCU_EVENT (1 << 25) +#define DE_GTT_FAULT (1 << 24) +#define DE_POISON (1 << 23) +#define DE_PERFORM_COUNTER (1 << 22) +#define DE_PCH_EVENT (1 << 21) +#define DE_AUX_CHANNEL_A (1 << 20) +#define DE_DP_A_HOTPLUG (1 << 19) +#define DE_GSE (1 << 18) +#define DE_PIPEB_VBLANK (1 << 15) +#define DE_PIPEB_EVEN_FIELD (1 << 14) +#define DE_PIPEB_ODD_FIELD (1 << 13) +#define DE_PIPEB_LINE_COMPARE (1 << 12) +#define DE_PIPEB_VSYNC (1 << 11) #define DE_PIPEB_FIFO_UNDERRUN (1 << 8) -#define DE_PIPEA_VBLANK (1 << 7) -#define DE_PIPEA_EVEN_FIELD (1 << 6) -#define DE_PIPEA_ODD_FIELD (1 << 5) -#define DE_PIPEA_LINE_COMPARE (1 << 4) -#define DE_PIPEA_VSYNC (1 << 3) +#define DE_PIPEA_VBLANK (1 << 7) +#define DE_PIPEA_EVEN_FIELD (1 << 6) +#define DE_PIPEA_ODD_FIELD (1 << 5) +#define DE_PIPEA_LINE_COMPARE (1 << 4) +#define DE_PIPEA_VSYNC (1 << 3) #define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
/* More Ivybridge lolz */ @@ -3070,23 +3070,23 @@ #define DE_PIPEB_VBLANK_IVB (1<<5) #define DE_PIPEA_VBLANK_IVB (1<<0)
-#define DEISR 0x44000 -#define DEIMR 0x44004 -#define DEIIR 0x44008 -#define DEIER 0x4400c +#define DEISR 0x44000 +#define DEIMR 0x44004 +#define DEIIR 0x44008 +#define DEIER 0x4400c
/* GT interrupt */ #define GT_PIPE_NOTIFY (1 << 4) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) -#define GT_BSD_USER_INTERRUPT (1 << 5) +#define GT_SYNC_STATUS (1 << 2) +#define GT_USER_INTERRUPT (1 << 0) +#define GT_BSD_USER_INTERRUPT (1 << 5) #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) #define GT_BLT_USER_INTERRUPT (1 << 22)
-#define GTISR 0x44010 -#define GTIMR 0x44014 -#define GTIIR 0x44018 -#define GTIER 0x4401c +#define GTISR 0x44010 +#define GTIMR 0x44014 +#define GTIIR 0x44018 +#define GTIER 0x4401c
#define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ @@ -3106,9 +3106,9 @@ #define ILK_DPFD_CLK_GATE (1<<7)
/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ -#define ILK_CLK_FBC (1<<7) -#define ILK_DPFC_DIS1 (1<<8) -#define ILK_DPFC_DIS2 (1<<9) +#define ILK_CLK_FBC (1<<7) +#define ILK_DPFC_DIS1 (1<<8) +#define ILK_DPFC_DIS2 (1<<9)
#define IVB_CHICKEN3 0x4200c # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) @@ -3157,11 +3157,11 @@ #define SDE_AUXB (1 << 13) #define SDE_AUX_MASK (7 << 13) /* 12 reserved */ -#define SDE_CRT_HOTPLUG (1 << 11) -#define SDE_PORTD_HOTPLUG (1 << 10) -#define SDE_PORTC_HOTPLUG (1 << 9) -#define SDE_PORTB_HOTPLUG (1 << 8) -#define SDE_SDVOB_HOTPLUG (1 << 6) +#define SDE_CRT_HOTPLUG (1 << 11) +#define SDE_PORTD_HOTPLUG (1 << 10) +#define SDE_PORTC_HOTPLUG (1 << 9) +#define SDE_PORTB_HOTPLUG (1 << 8) +#define SDE_SDVOB_HOTPLUG (1 << 6) #define SDE_HOTPLUG_MASK (0xf << 8) #define SDE_TRANSB_CRC_DONE (1 << 5) #define SDE_TRANSB_CRC_ERR (1 << 4) @@ -3186,41 +3186,41 @@ #define SDEIER 0xc400c
/* digital port hotplug */ -#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ -#define PORTD_HOTPLUG_ENABLE (1 << 20) -#define PORTD_PULSE_DURATION_2ms (0) -#define PORTD_PULSE_DURATION_4_5ms (1 << 18) -#define PORTD_PULSE_DURATION_6ms (2 << 18) -#define PORTD_PULSE_DURATION_100ms (3 << 18) +#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ +#define PORTD_HOTPLUG_ENABLE (1 << 20) +#define PORTD_PULSE_DURATION_2ms (0) +#define PORTD_PULSE_DURATION_4_5ms (1 << 18) +#define PORTD_PULSE_DURATION_6ms (2 << 18) +#define PORTD_PULSE_DURATION_100ms (3 << 18) #define PORTD_PULSE_DURATION_MASK (3 << 18) -#define PORTD_HOTPLUG_NO_DETECT (0) -#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) -#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) -#define PORTC_HOTPLUG_ENABLE (1 << 12) -#define PORTC_PULSE_DURATION_2ms (0) -#define PORTC_PULSE_DURATION_4_5ms (1 << 10) -#define PORTC_PULSE_DURATION_6ms (2 << 10) -#define PORTC_PULSE_DURATION_100ms (3 << 10) +#define PORTD_HOTPLUG_NO_DETECT (0) +#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) +#define PORTD_HOTPLUG_LONG_DETECT (1 << 17) +#define PORTC_HOTPLUG_ENABLE (1 << 12) +#define PORTC_PULSE_DURATION_2ms (0) +#define PORTC_PULSE_DURATION_4_5ms (1 << 10) +#define PORTC_PULSE_DURATION_6ms (2 << 10) +#define PORTC_PULSE_DURATION_100ms (3 << 10) #define PORTC_PULSE_DURATION_MASK (3 << 10) -#define PORTC_HOTPLUG_NO_DETECT (0) -#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) -#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) -#define PORTB_HOTPLUG_ENABLE (1 << 4) -#define PORTB_PULSE_DURATION_2ms (0) -#define PORTB_PULSE_DURATION_4_5ms (1 << 2) -#define PORTB_PULSE_DURATION_6ms (2 << 2) -#define PORTB_PULSE_DURATION_100ms (3 << 2) +#define PORTC_HOTPLUG_NO_DETECT (0) +#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) +#define PORTC_HOTPLUG_LONG_DETECT (1 << 9) +#define PORTB_HOTPLUG_ENABLE (1 << 4) +#define PORTB_PULSE_DURATION_2ms (0) +#define PORTB_PULSE_DURATION_4_5ms (1 << 2) +#define PORTB_PULSE_DURATION_6ms (2 << 2) +#define PORTB_PULSE_DURATION_100ms (3 << 2) #define PORTB_PULSE_DURATION_MASK (3 << 2) -#define PORTB_HOTPLUG_NO_DETECT (0) -#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) -#define PORTB_HOTPLUG_LONG_DETECT (1 << 1) +#define PORTB_HOTPLUG_NO_DETECT (0) +#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) +#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
-#define PCH_GPIOA 0xc5010 -#define PCH_GPIOB 0xc5014 -#define PCH_GPIOC 0xc5018 -#define PCH_GPIOD 0xc501c -#define PCH_GPIOE 0xc5020 -#define PCH_GPIOF 0xc5024 +#define PCH_GPIOA 0xc5010 +#define PCH_GPIOB 0xc5014 +#define PCH_GPIOC 0xc5018 +#define PCH_GPIOD 0xc501c +#define PCH_GPIOE 0xc5020 +#define PCH_GPIOF 0xc5024
#define PCH_GMBUS0 0xc5100 #define PCH_GMBUS1 0xc5104 @@ -3229,54 +3229,54 @@ #define PCH_GMBUS4 0xc5110 #define PCH_GMBUS5 0xc5120
-#define _PCH_DPLL_A 0xc6014 -#define _PCH_DPLL_B 0xc6018 +#define _PCH_DPLL_A 0xc6014 +#define _PCH_DPLL_B 0xc6018 #define PCH_DPLL(pipe) (pipe == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-#define _PCH_FPA0 0xc6040 +#define _PCH_FPA0 0xc6040 #define FP_CB_TUNE (0x3<<22) -#define _PCH_FPA1 0xc6044 -#define _PCH_FPB0 0xc6048 -#define _PCH_FPB1 0xc604c +#define _PCH_FPA1 0xc6044 +#define _PCH_FPB0 0xc6048 +#define _PCH_FPB1 0xc604c #define PCH_FP0(pipe) (pipe == 0 ? _PCH_FPA0 : _PCH_FPB0) #define PCH_FP1(pipe) (pipe == 0 ? _PCH_FPA1 : _PCH_FPB1)
-#define PCH_DPLL_TEST 0xc606c +#define PCH_DPLL_TEST 0xc606c
-#define PCH_DREF_CONTROL 0xC6200 -#define DREF_CONTROL_MASK 0x7fc3 -#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) -#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) -#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) +#define PCH_DREF_CONTROL 0xC6200 +#define DREF_CONTROL_MASK 0x7fc3 +#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) +#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) +#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) #define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) -#define DREF_SSC_SOURCE_DISABLE (0<<11) -#define DREF_SSC_SOURCE_ENABLE (2<<11) +#define DREF_SSC_SOURCE_DISABLE (0<<11) +#define DREF_SSC_SOURCE_ENABLE (2<<11) #define DREF_SSC_SOURCE_MASK (3<<11) -#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) +#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) #define DREF_NONSPREAD_CK505_ENABLE (1<<9) -#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) +#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) #define DREF_NONSPREAD_SOURCE_MASK (3<<9) -#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) -#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) +#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) #define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) -#define DREF_SSC4_DOWNSPREAD (0<<6) -#define DREF_SSC4_CENTERSPREAD (1<<6) -#define DREF_SSC1_DISABLE (0<<1) -#define DREF_SSC1_ENABLE (1<<1) -#define DREF_SSC4_DISABLE (0) -#define DREF_SSC4_ENABLE (1) +#define DREF_SSC4_DOWNSPREAD (0<<6) +#define DREF_SSC4_CENTERSPREAD (1<<6) +#define DREF_SSC1_DISABLE (0<<1) +#define DREF_SSC1_ENABLE (1<<1) +#define DREF_SSC4_DISABLE (0) +#define DREF_SSC4_ENABLE (1)
-#define PCH_RAWCLK_FREQ 0xc6204 -#define FDL_TP1_TIMER_SHIFT 12 -#define FDL_TP1_TIMER_MASK (3<<12) -#define FDL_TP2_TIMER_SHIFT 10 -#define FDL_TP2_TIMER_MASK (3<<10) -#define RAWCLK_FREQ_MASK 0x3ff +#define PCH_RAWCLK_FREQ 0xc6204 +#define FDL_TP1_TIMER_SHIFT 12 +#define FDL_TP1_TIMER_MASK (3<<12) +#define FDL_TP2_TIMER_SHIFT 10 +#define FDL_TP2_TIMER_MASK (3<<10) +#define RAWCLK_FREQ_MASK 0x3ff
-#define PCH_DPLL_TMR_CFG 0xc6208 +#define PCH_DPLL_TMR_CFG 0xc6208
-#define PCH_SSC4_PARMS 0xc6210 -#define PCH_SSC4_AUX_PARMS 0xc6214 +#define PCH_SSC4_PARMS 0xc6210 +#define PCH_SSC4_AUX_PARMS 0xc6214
#define PCH_DPLL_SEL 0xc7000 #define TRANSA_DPLL_ENABLE (1<<3) @@ -3291,55 +3291,55 @@
/* transcoder */
-#define _TRANS_HTOTAL_A 0xe0000 -#define TRANS_HTOTAL_SHIFT 16 -#define TRANS_HACTIVE_SHIFT 0 -#define _TRANS_HBLANK_A 0xe0004 +#define _TRANS_HTOTAL_A 0xe0000 +#define TRANS_HTOTAL_SHIFT 16 +#define TRANS_HACTIVE_SHIFT 0 +#define _TRANS_HBLANK_A 0xe0004 #define TRANS_HBLANK_END_SHIFT 16 #define TRANS_HBLANK_START_SHIFT 0 -#define _TRANS_HSYNC_A 0xe0008 +#define _TRANS_HSYNC_A 0xe0008 #define TRANS_HSYNC_END_SHIFT 16 #define TRANS_HSYNC_START_SHIFT 0 -#define _TRANS_VTOTAL_A 0xe000c -#define TRANS_VTOTAL_SHIFT 16 -#define TRANS_VACTIVE_SHIFT 0 -#define _TRANS_VBLANK_A 0xe0010 +#define _TRANS_VTOTAL_A 0xe000c +#define TRANS_VTOTAL_SHIFT 16 +#define TRANS_VACTIVE_SHIFT 0 +#define _TRANS_VBLANK_A 0xe0010 #define TRANS_VBLANK_END_SHIFT 16 #define TRANS_VBLANK_START_SHIFT 0 -#define _TRANS_VSYNC_A 0xe0014 +#define _TRANS_VSYNC_A 0xe0014 #define TRANS_VSYNC_END_SHIFT 16 #define TRANS_VSYNC_START_SHIFT 0 #define _TRANS_VSYNCSHIFT_A 0xe0028
-#define _TRANSA_DATA_M1 0xe0030 -#define _TRANSA_DATA_N1 0xe0034 -#define _TRANSA_DATA_M2 0xe0038 -#define _TRANSA_DATA_N2 0xe003c -#define _TRANSA_DP_LINK_M1 0xe0040 -#define _TRANSA_DP_LINK_N1 0xe0044 -#define _TRANSA_DP_LINK_M2 0xe0048 -#define _TRANSA_DP_LINK_N2 0xe004c +#define _TRANSA_DATA_M1 0xe0030 +#define _TRANSA_DATA_N1 0xe0034 +#define _TRANSA_DATA_M2 0xe0038 +#define _TRANSA_DATA_N2 0xe003c +#define _TRANSA_DP_LINK_M1 0xe0040 +#define _TRANSA_DP_LINK_N1 0xe0044 +#define _TRANSA_DP_LINK_M2 0xe0048 +#define _TRANSA_DP_LINK_N2 0xe004c
/* Per-transcoder DIP controls */
-#define _VIDEO_DIP_CTL_A 0xe0200 -#define _VIDEO_DIP_DATA_A 0xe0208 -#define _VIDEO_DIP_GCP_A 0xe0210 +#define _VIDEO_DIP_CTL_A 0xe0200 +#define _VIDEO_DIP_DATA_A 0xe0208 +#define _VIDEO_DIP_GCP_A 0xe0210
-#define _VIDEO_DIP_CTL_B 0xe1200 -#define _VIDEO_DIP_DATA_B 0xe1208 -#define _VIDEO_DIP_GCP_B 0xe1210 +#define _VIDEO_DIP_CTL_B 0xe1200 +#define _VIDEO_DIP_DATA_B 0xe1208 +#define _VIDEO_DIP_GCP_B 0xe1210
#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
-#define _TRANS_HTOTAL_B 0xe1000 -#define _TRANS_HBLANK_B 0xe1004 -#define _TRANS_HSYNC_B 0xe1008 -#define _TRANS_VTOTAL_B 0xe100c -#define _TRANS_VBLANK_B 0xe1010 -#define _TRANS_VSYNC_B 0xe1014 +#define _TRANS_HTOTAL_B 0xe1000 +#define _TRANS_HBLANK_B 0xe1004 +#define _TRANS_HSYNC_B 0xe1008 +#define _TRANS_VTOTAL_B 0xe100c +#define _TRANS_VBLANK_B 0xe1010 +#define _TRANS_VSYNC_B 0xe1014 #define _TRANS_VSYNCSHIFT_B 0xe1028
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) @@ -3349,16 +3349,16 @@ #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) #define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \ - _TRANS_VSYNCSHIFT_B) + _TRANS_VSYNCSHIFT_B)
-#define _TRANSB_DATA_M1 0xe1030 -#define _TRANSB_DATA_N1 0xe1034 -#define _TRANSB_DATA_M2 0xe1038 -#define _TRANSB_DATA_N2 0xe103c -#define _TRANSB_DP_LINK_M1 0xe1040 -#define _TRANSB_DP_LINK_N1 0xe1044 -#define _TRANSB_DP_LINK_M2 0xe1048 -#define _TRANSB_DP_LINK_N2 0xe104c +#define _TRANSB_DATA_M1 0xe1030 +#define _TRANSB_DATA_N1 0xe1034 +#define _TRANSB_DATA_M2 0xe1038 +#define _TRANSB_DATA_N2 0xe103c +#define _TRANSB_DP_LINK_M1 0xe1040 +#define _TRANSB_DP_LINK_N1 0xe1044 +#define _TRANSB_DP_LINK_M2 0xe1048 +#define _TRANSB_DP_LINK_N2 0xe104c
#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1) #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1) @@ -3369,33 +3369,33 @@ #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2) #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
-#define _TRANSACONF 0xf0008 -#define _TRANSBCONF 0xf1008 +#define _TRANSACONF 0xf0008 +#define _TRANSBCONF 0xf1008 #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF) -#define TRANS_DISABLE (0<<31) -#define TRANS_ENABLE (1<<31) -#define TRANS_STATE_MASK (1<<30) -#define TRANS_STATE_DISABLE (0<<30) -#define TRANS_STATE_ENABLE (1<<30) +#define TRANS_DISABLE (0<<31) +#define TRANS_ENABLE (1<<31) +#define TRANS_STATE_MASK (1<<30) +#define TRANS_STATE_DISABLE (0<<30) +#define TRANS_STATE_ENABLE (1<<30) #define TRANS_FSYNC_DELAY_HB1 (0<<27) #define TRANS_FSYNC_DELAY_HB2 (1<<27) #define TRANS_FSYNC_DELAY_HB3 (2<<27) #define TRANS_FSYNC_DELAY_HB4 (3<<27) -#define TRANS_DP_AUDIO_ONLY (1<<26) -#define TRANS_DP_VIDEO_AUDIO (0<<26) -#define TRANS_INTERLACE_MASK (7<<21) -#define TRANS_PROGRESSIVE (0<<21) -#define TRANS_INTERLACED (3<<21) +#define TRANS_DP_AUDIO_ONLY (1<<26) +#define TRANS_DP_VIDEO_AUDIO (0<<26) +#define TRANS_INTERLACE_MASK (7<<21) +#define TRANS_PROGRESSIVE (0<<21) +#define TRANS_INTERLACED (3<<21) #define TRANS_LEGACY_INTERLACED_ILK (2<<21) -#define TRANS_8BPC (0<<5) -#define TRANS_10BPC (1<<5) -#define TRANS_6BPC (2<<5) -#define TRANS_12BPC (3<<5) +#define TRANS_8BPC (0<<5) +#define TRANS_10BPC (1<<5) +#define TRANS_6BPC (2<<5) +#define TRANS_12BPC (3<<5)
#define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
#define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 @@ -3405,8 +3405,8 @@ #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0)
-#define _FDI_RXA_CHICKEN 0xc200c -#define _FDI_RXB_CHICKEN 0xc2010 +#define _FDI_RXA_CHICKEN 0xc200c +#define _FDI_RXB_CHICKEN 0xc2010 #define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) #define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) @@ -3415,23 +3415,23 @@ #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
/* CPU: FDI_TX */ -#define _FDI_TXA_CTL 0x60100 -#define _FDI_TXB_CTL 0x61100 +#define _FDI_TXA_CTL 0x60100 +#define _FDI_TXB_CTL 0x61100 #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) -#define FDI_TX_DISABLE (0<<31) -#define FDI_TX_ENABLE (1<<31) -#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) -#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) -#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) -#define FDI_LINK_TRAIN_NONE (3<<28) -#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) -#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) -#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) +#define FDI_TX_DISABLE (0<<31) +#define FDI_TX_ENABLE (1<<31) +#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) +#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) +#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) +#define FDI_LINK_TRAIN_NONE (3<<28) +#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) +#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) +#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) #define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) #define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) -#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) +#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. SNB has different settings. */ /* SNB A-stepping */ @@ -3445,48 +3445,48 @@ #define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) #define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) -#define FDI_DP_PORT_WIDTH_X1 (0<<19) -#define FDI_DP_PORT_WIDTH_X2 (1<<19) -#define FDI_DP_PORT_WIDTH_X3 (2<<19) -#define FDI_DP_PORT_WIDTH_X4 (3<<19) -#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) +#define FDI_DP_PORT_WIDTH_X1 (0<<19) +#define FDI_DP_PORT_WIDTH_X2 (1<<19) +#define FDI_DP_PORT_WIDTH_X3 (2<<19) +#define FDI_DP_PORT_WIDTH_X4 (3<<19) +#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) /* Ironlake: hardwired to 1 */ -#define FDI_TX_PLL_ENABLE (1<<14) +#define FDI_TX_PLL_ENABLE (1<<14)
/* Ivybridge has different bits for lolz */ -#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) -#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) +#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) +#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) #define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) -#define FDI_LINK_TRAIN_NONE_IVB (3<<8) +#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
/* both Tx and Rx */ #define FDI_COMPOSITE_SYNC (1<<11) #define FDI_LINK_TRAIN_AUTO (1<<10) -#define FDI_SCRAMBLING_ENABLE (0<<7) -#define FDI_SCRAMBLING_DISABLE (1<<7) +#define FDI_SCRAMBLING_ENABLE (0<<7) +#define FDI_SCRAMBLING_DISABLE (1<<7)
/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ -#define _FDI_RXA_CTL 0xf000c -#define _FDI_RXB_CTL 0xf100c +#define _FDI_RXA_CTL 0xf000c +#define _FDI_RXB_CTL 0xf100c #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) -#define FDI_RX_ENABLE (1<<31) +#define FDI_RX_ENABLE (1<<31) /* train, dp width same as FDI_TX */ #define FDI_FS_ERRC_ENABLE (1<<27) #define FDI_FE_ERRC_ENABLE (1<<26) -#define FDI_DP_PORT_WIDTH_X8 (7<<19) -#define FDI_8BPC (0<<16) -#define FDI_10BPC (1<<16) -#define FDI_6BPC (2<<16) -#define FDI_12BPC (3<<16) -#define FDI_LINK_REVERSE_OVERWRITE (1<<15) -#define FDI_DMI_LINK_REVERSE_MASK (1<<14) -#define FDI_RX_PLL_ENABLE (1<<13) -#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) -#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) -#define FDI_FS_ERR_REPORT_ENABLE (1<<9) -#define FDI_FE_ERR_REPORT_ENABLE (1<<8) -#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) -#define FDI_PCDCLK (1<<4) +#define FDI_DP_PORT_WIDTH_X8 (7<<19) +#define FDI_8BPC (0<<16) +#define FDI_10BPC (1<<16) +#define FDI_6BPC (2<<16) +#define FDI_12BPC (3<<16) +#define FDI_LINK_REVERSE_OVERWRITE (1<<15) +#define FDI_DMI_LINK_REVERSE_MASK (1<<14) +#define FDI_RX_PLL_ENABLE (1<<13) +#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) +#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) +#define FDI_FS_ERR_REPORT_ENABLE (1<<9) +#define FDI_FE_ERR_REPORT_ENABLE (1<<8) +#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) +#define FDI_PCDCLK (1<<4) /* CPT */ #define FDI_AUTO_TRAINING (1<<10) #define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) @@ -3495,91 +3495,91 @@ #define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) #define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
-#define _FDI_RXA_MISC 0xf0010 -#define _FDI_RXB_MISC 0xf1010 -#define _FDI_RXA_TUSIZE1 0xf0030 -#define _FDI_RXA_TUSIZE2 0xf0038 -#define _FDI_RXB_TUSIZE1 0xf1030 -#define _FDI_RXB_TUSIZE2 0xf1038 +#define _FDI_RXA_MISC 0xf0010 +#define _FDI_RXB_MISC 0xf1010 +#define _FDI_RXA_TUSIZE1 0xf0030 +#define _FDI_RXA_TUSIZE2 0xf0038 +#define _FDI_RXB_TUSIZE1 0xf1030 +#define _FDI_RXB_TUSIZE2 0xf1038 #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
/* FDI_RX interrupt register format */ -#define FDI_RX_INTER_LANE_ALIGN (1<<10) -#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ -#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ -#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) -#define FDI_RX_FS_CODE_ERR (1<<6) -#define FDI_RX_FE_CODE_ERR (1<<5) -#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) -#define FDI_RX_HDCP_LINK_FAIL (1<<3) -#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) -#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) -#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) - -#define _FDI_RXA_IIR 0xf0014 -#define _FDI_RXA_IMR 0xf0018 -#define _FDI_RXB_IIR 0xf1014 -#define _FDI_RXB_IMR 0xf1018 +#define FDI_RX_INTER_LANE_ALIGN (1<<10) +#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ +#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ +#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) +#define FDI_RX_FS_CODE_ERR (1<<6) +#define FDI_RX_FE_CODE_ERR (1<<5) +#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) +#define FDI_RX_HDCP_LINK_FAIL (1<<3) +#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) +#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) +#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) + +#define _FDI_RXA_IIR 0xf0014 +#define _FDI_RXA_IMR 0xf0018 +#define _FDI_RXB_IIR 0xf1014 +#define _FDI_RXB_IMR 0xf1018 #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
-#define FDI_PLL_CTL_1 0xfe000 -#define FDI_PLL_CTL_2 0xfe004 +#define FDI_PLL_CTL_1 0xfe000 +#define FDI_PLL_CTL_2 0xfe004
/* CRT */ -#define PCH_ADPA 0xe1100 +#define PCH_ADPA 0xe1100 #define ADPA_TRANS_SELECT_MASK (1<<30) -#define ADPA_TRANS_A_SELECT 0 -#define ADPA_TRANS_B_SELECT (1<<30) +#define ADPA_TRANS_A_SELECT 0 +#define ADPA_TRANS_B_SELECT (1<<30) #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) -#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) -#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) -#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) -#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) -#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) -#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) -#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) -#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) -#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) +#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) +#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) +#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) +#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) +#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) +#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) +#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) +#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) +#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
/* or SDVOB */ -#define HDMIB 0xe1140 -#define PORT_ENABLE (1 << 31) -#define TRANSCODER(pipe) ((pipe) << 30) -#define TRANSCODER_CPT(pipe) ((pipe) << 29) -#define TRANSCODER_MASK (1 << 30) -#define TRANSCODER_MASK_CPT (3 << 29) -#define COLOR_FORMAT_8bpc (0) -#define COLOR_FORMAT_12bpc (3 << 26) -#define SDVOB_HOTPLUG_ENABLE (1 << 23) -#define SDVO_ENCODING (0) -#define TMDS_ENCODING (2 << 10) -#define NULL_PACKET_VSYNC_ENABLE (1 << 9) +#define HDMIB 0xe1140 +#define PORT_ENABLE (1 << 31) +#define TRANSCODER(pipe) ((pipe) << 30) +#define TRANSCODER_CPT(pipe) ((pipe) << 29) +#define TRANSCODER_MASK (1 << 30) +#define TRANSCODER_MASK_CPT (3 << 29) +#define COLOR_FORMAT_8bpc (0) +#define COLOR_FORMAT_12bpc (3 << 26) +#define SDVOB_HOTPLUG_ENABLE (1 << 23) +#define SDVO_ENCODING (0) +#define TMDS_ENCODING (2 << 10) +#define NULL_PACKET_VSYNC_ENABLE (1 << 9) /* CPT */ #define HDMI_MODE_SELECT (1 << 9) #define DVI_MODE_SELECT (0) -#define SDVOB_BORDER_ENABLE (1 << 7) -#define AUDIO_ENABLE (1 << 6) -#define VSYNC_ACTIVE_HIGH (1 << 4) -#define HSYNC_ACTIVE_HIGH (1 << 3) -#define PORT_DETECTED (1 << 2) +#define SDVOB_BORDER_ENABLE (1 << 7) +#define AUDIO_ENABLE (1 << 6) +#define VSYNC_ACTIVE_HIGH (1 << 4) +#define HSYNC_ACTIVE_HIGH (1 << 3) +#define PORT_DETECTED (1 << 2)
/* PCH SDVOB multiplex with HDMIB */ #define PCH_SDVOB HDMIB
-#define HDMIC 0xe1150 -#define HDMID 0xe1160 +#define HDMIC 0xe1150 +#define HDMID 0xe1160
#define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) @@ -3723,16 +3723,16 @@ #define FORCEWAKE_MT 0xa188 /* multi-threaded */ #define FORCEWAKE_MT_ACK 0x130040 #define ECOBUS 0xa180 -#define FORCEWAKE_MT_ENABLE (1<<5) +#define FORCEWAKE_MT_ENABLE (1<<5)
#define GTFIFODBG 0x120000 -#define GT_FIFO_CPU_ERROR_MASK 7 -#define GT_FIFO_OVFERR (1<<2) -#define GT_FIFO_IAWRERR (1<<1) -#define GT_FIFO_IARDERR (1<<0) +#define GT_FIFO_CPU_ERROR_MASK 7 +#define GT_FIFO_OVFERR (1<<2) +#define GT_FIFO_IAWRERR (1<<1) +#define GT_FIFO_IARDERR (1<<0)
#define GT_FIFO_FREE_ENTRIES 0x120008 -#define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL1 0x9400 # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) @@ -3743,46 +3743,46 @@ # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
#define GEN6_RPNSWREQ 0xA008 -#define GEN6_TURBO_DISABLE (1<<31) -#define GEN6_FREQUENCY(x) ((x)<<25) -#define GEN6_OFFSET(x) ((x)<<19) -#define GEN6_AGGRESSIVE_TURBO (0<<15) +#define GEN6_TURBO_DISABLE (1<<31) +#define GEN6_FREQUENCY(x) ((x)<<25) +#define GEN6_OFFSET(x) ((x)<<19) +#define GEN6_AGGRESSIVE_TURBO (0<<15) #define GEN6_RC_VIDEO_FREQ 0xA00C #define GEN6_RC_CONTROL 0xA090 -#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) -#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) -#define GEN6_RC_CTL_RC6_ENABLE (1<<18) -#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) -#define GEN6_RC_CTL_RC7_ENABLE (1<<22) -#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) -#define GEN6_RC_CTL_HW_ENABLE (1<<31) +#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) +#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) +#define GEN6_RC_CTL_RC6_ENABLE (1<<18) +#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) +#define GEN6_RC_CTL_RC7_ENABLE (1<<22) +#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) +#define GEN6_RC_CTL_HW_ENABLE (1<<31) #define GEN6_RP_DOWN_TIMEOUT 0xA010 #define GEN6_RP_INTERRUPT_LIMITS 0xA014 #define GEN6_RPSTAT1 0xA01C -#define GEN6_CAGF_SHIFT 8 -#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) +#define GEN6_CAGF_SHIFT 8 +#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) #define GEN6_RP_CONTROL 0xA024 -#define GEN6_RP_MEDIA_TURBO (1<<11) -#define GEN6_RP_MEDIA_MODE_MASK (3<<9) -#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) -#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) -#define GEN6_RP_MEDIA_HW_MODE (1<<9) -#define GEN6_RP_MEDIA_SW_MODE (0<<9) -#define GEN6_RP_MEDIA_IS_GFX (1<<8) -#define GEN6_RP_ENABLE (1<<7) -#define GEN6_RP_UP_IDLE_MIN (0x1<<3) -#define GEN6_RP_UP_BUSY_AVG (0x2<<3) -#define GEN6_RP_UP_BUSY_CONT (0x4<<3) -#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) +#define GEN6_RP_MEDIA_TURBO (1<<11) +#define GEN6_RP_MEDIA_MODE_MASK (3<<9) +#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) +#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) +#define GEN6_RP_MEDIA_HW_MODE (1<<9) +#define GEN6_RP_MEDIA_SW_MODE (0<<9) +#define GEN6_RP_MEDIA_IS_GFX (1<<8) +#define GEN6_RP_ENABLE (1<<7) +#define GEN6_RP_UP_IDLE_MIN (0x1<<3) +#define GEN6_RP_UP_BUSY_AVG (0x2<<3) +#define GEN6_RP_UP_BUSY_CONT (0x4<<3) +#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) #define GEN6_RP_UP_THRESHOLD 0xA02C #define GEN6_RP_DOWN_THRESHOLD 0xA030 #define GEN6_RP_CUR_UP_EI 0xA050 -#define GEN6_CURICONT_MASK 0xffffff +#define GEN6_CURICONT_MASK 0xffffff #define GEN6_RP_CUR_UP 0xA054 -#define GEN6_CURBSYTAVG_MASK 0xffffff +#define GEN6_CURBSYTAVG_MASK 0xffffff #define GEN6_RP_PREV_UP 0xA058 #define GEN6_RP_CUR_DOWN_EI 0xA05C -#define GEN6_CURIAVG_MASK 0xffffff +#define GEN6_CURIAVG_MASK 0xffffff #define GEN6_RP_CUR_DOWN 0xA060 #define GEN6_RP_PREV_DOWN 0xA064 #define GEN6_RP_UP_EI 0xA068 @@ -3817,20 +3817,20 @@ GEN6_PM_RP_DOWN_TIMEOUT)
#define GEN6_PCODE_MAILBOX 0x138124 -#define GEN6_PCODE_READY (1<<31) -#define GEN6_READ_OC_PARAMS 0xc -#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 -#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 +#define GEN6_PCODE_READY (1<<31) +#define GEN6_READ_OC_PARAMS 0xc +#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 +#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 #define GEN6_PCODE_DATA 0x138128 -#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 +#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_GT_CORE_STATUS 0x138060 -#define GEN6_CORE_CPD_STATE_MASK (7<<4) -#define GEN6_RCn_MASK 7 -#define GEN6_RC0 0 -#define GEN6_RC3 2 -#define GEN6_RC6 3 -#define GEN6_RC7 4 +#define GEN6_CORE_CPD_STATE_MASK (7<<4) +#define GEN6_RCn_MASK 7 +#define GEN6_RC0 0 +#define GEN6_RC3 2 +#define GEN6_RC6 3 +#define GEN6_RC7 4
#define G4X_AUD_VID_DID 0x62020 #define INTEL_AUDIO_DEVCL 0x808629FB @@ -3865,14 +3865,14 @@
#define IBX_AUD_CONFIG_A 0xe2000 #define CPT_AUD_CONFIG_A 0xe5000 -#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) -#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) -#define AUD_CONFIG_UPPER_N_SHIFT 20 -#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) -#define AUD_CONFIG_LOWER_N_SHIFT 4 -#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) -#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 -#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -#define AUD_CONFIG_DISABLE_NCTS (1 << 3) +#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) +#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) +#define AUD_CONFIG_UPPER_N_SHIFT 20 +#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) +#define AUD_CONFIG_LOWER_N_SHIFT 4 +#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) +#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 +#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) +#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
#endif /* _I915_REG_H_ */ diff --git a/src/mainboard/lenovo/x60/intel_dp.c b/src/mainboard/lenovo/x60/intel_dp.c index e48f4f8..9dd6d81 100644 --- a/src/mainboard/lenovo/x60/intel_dp.c +++ b/src/mainboard/lenovo/x60/intel_dp.c @@ -123,7 +123,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | - DP_AUX_CH_CTL_RECEIVE_ERROR)) + DP_AUX_CH_CTL_RECEIVE_ERROR)) continue; if (status & DP_AUX_CH_CTL_DONE) break; @@ -141,7 +141,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); printk(BIOS_SPEW, - "dp_aux_ch receive error status 0x%08x\n", status); + "dp_aux_ch receive error status 0x%08x\n", status); return -1; }
@@ -155,7 +155,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
/* Unload any bytes sent back from the other side */ recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> - DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); if (recv_bytes > recv_size) recv_bytes = recv_size;
diff --git a/src/mainboard/lenovo/x60/irq_tables.c b/src/mainboard/lenovo/x60/irq_tables.c index 8991d7f..b52c515 100644 --- a/src/mainboard/lenovo/x60/irq_tables.c +++ b/src/mainboard/lenovo/x60/irq_tables.c @@ -35,22 +35,22 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xf5, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x02 << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */ {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */ {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */ {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */ {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */ {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */ - {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ - {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ - {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ - {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ - {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ - {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ - {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */ + {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */ + {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */ + {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */ + {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */ + {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */ + {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */ {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */ } }; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d425cd2..c07aba8 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -56,7 +56,7 @@ static int int15_handler(void) * TODO: completely move to mainboards / chipsets. */ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX);
switch (X86_AX) { case 0x5f35: /* Boot Display */ diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c index 8ade71b..7ffbfe1 100644 --- a/src/mainboard/lenovo/x60/mptable.c +++ b/src/mainboard/lenovo/x60/mptable.c @@ -29,14 +29,14 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
@@ -48,23 +48,23 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */
mptable_lintsrc(mc, isa_bus); return mptable_finalize(mc); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 26a7b9b..472e7d5 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -251,7 +251,7 @@ void main(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, - "Soft reset detected, rebooting properly.\n"); + "Soft reset detected, rebooting properly.\n"); outb(0x6, 0xcf9); while (1) asm("hlt"); @@ -339,7 +339,7 @@ void main(unsigned long bist) */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); + HIGH_MEMORY_SAVE);
/* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index fdb228c..eacab70 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -98,14 +98,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -230,12 +230,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ b/src/mainboard/lippert/frontrunner-af/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/lippert/frontrunner-af/acpi/ide.asl b/src/mainboard/lippert/frontrunner-af/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/ide.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.c b/src/mainboard/lippert/frontrunner-af/agesawrapper.c index 0572335..401c88a 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.c +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.c @@ -474,9 +474,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -505,8 +505,8 @@ agesawrapper_amdinitlate ( AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
@@ -526,12 +526,12 @@ agesawrapper_amdinitresume ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -565,15 +565,15 @@ agesawrapper_amds3laterestore ( ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -609,12 +609,12 @@ agesawrapper_amdS3Save ( AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index a02366e..294be8d 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -123,13 +123,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -148,7 +148,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -273,8 +273,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -410,16 +410,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -790,7 +790,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1270,32 +1270,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1560,8 +1560,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1605,42 +1605,42 @@ DefinitionBlock ( } #endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1649,7 +1649,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index 258d895..d729d55 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 57543c2..9fe16c6 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -40,12 +40,12 @@ static const u16 sio_init_table[] = { // hi=offset, lo=value 0x2400, // GP11: COM2 termination = push/pull output 0x2500, // GP12: COM1 RS485 mode = push/pull output 0x2600, // GP13: COM2 RS485 mode = push/pull output - 0x2700, // GP14: COM1 speed A = push/pull output - 0x2900, // GP15: COM1 speed B = push/pull output - 0x2A00, // GP16: COM2 speed A = push/pull output - 0x2B00, // GP17: COM2 speed B = push/pull output + 0x2700, // GP14: COM1 speed A = push/pull output + 0x2900, // GP15: COM1 speed B = push/pull output + 0x2A00, // GP16: COM2 speed A = push/pull output + 0x2B00, // GP17: COM2 speed B = push/pull output
- 0x3904, // GP36 = KBDRST# function + 0x3904, // GP36 = KBDRST# function
0x4E74, // GP4x: Ethernet enable = on 0x6E84, // GP44: Ethernet enable = open drain output @@ -53,14 +53,14 @@ static const u16 sio_init_table[] = { // hi=offset, lo=value // GP5x = COM2 function instead of GPIO 0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
- 0x470C, // GP60 = WDT function - 0x5E00, // LED2: Live LED = off - 0x4884, // GP61: Live LED = LED2 function + 0x470C, // GP60 = WDT function + 0x5E00, // LED2: Live LED = off + 0x4884, // GP61: Live LED = LED2 function
- 0x5038, // GP6x: USB power = 3x on - 0x5580, // GP63: USB power 0/1 = open drain output - 0x5680, // GP64: USB power 2/3 = open drain output - 0x5780, // GP65: USB power 4/5 = open drain output + 0x5038, // GP6x: USB power = 3x on + 0x5580, // GP63: USB power 0/1 = open drain output + 0x5680, // GP64: USB power 2/3 = open drain output + 0x5780, // GP65: USB power 4/5 = open drain output };
/* Write data block to slave on SMBUS0. */ @@ -93,18 +93,18 @@ static void init(struct device *dev)
/* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed - FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU) - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 + FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU) + FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups FCH_IOMUX( 57) = 1; FCH_GPIO ( 57) = 0x28; FCH_IOMUX( 58) = 1; FCH_GPIO ( 58) = 0x28; - FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) - FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector - FCH_IOMUX( 61) = 2; // default to inputs with int. PU + FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) + FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector + FCH_IOMUX( 61) = 2; // default to inputs with int. PU FCH_IOMUX( 62) = 2; FCH_IOMUX(187) = 2; FCH_IOMUX(188) = 2; @@ -115,7 +115,7 @@ static void init(struct device *dev) if (!fch_gpio_state(197)) // just in case anyone cares printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); printk(BIOS_INFO, "Board revision ID: %u\n", - fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); + fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
/* Init SIO GPIOs. */ printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE); diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 1e6617b..4f831c0 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -220,7 +220,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ @@ -260,15 +260,15 @@ static const CODECTBLLIST codec_tablelist[] =
/* set up an ACPI prefered power management profile */ /* from acpi.h - * PM_UNSPECIFIED = 0, - * PM_DESKTOP = 1, - * PM_MOBILE = 2, - * PM_WORKSTATION = 3, - * PM_ENTERPRISE_SERVER = 4, - * PM_SOHO_SERVER = 5, - * PM_APPLIANCE_PC = 6, + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, * PM_PERFORMANCE_SERVER = 7, - * PM_TABLET = 8 + * PM_TABLET = 8 */ #define FADT_PM_PROFILE 1
diff --git a/src/mainboard/lippert/frontrunner/cmos.layout b/src/mainboard/lippert/frontrunner/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/lippert/frontrunner/cmos.layout +++ b/src/mainboard/lippert/frontrunner/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index a35c91c..f1f23ba 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -9,11 +9,11 @@ chip northbridge/amd/gx2 device pci 0.0 on end chip southbridge/amd/cs5535 register "setupflash" = "0" - device pci 12.0 on - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA + device pci 12.0 on + device pci 12.1 off end # SMI + device pci 12.2 on end # IDE + device pci 12.3 off end # Audio + device pci 12.4 off end # VGA end end end diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index 5c045cc..57444f4 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -27,23 +27,23 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x800, /* IRQs devoted exclusively to PCI usage */ 0x1078, /* Vendor */ 0x2, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index bdbf059..23111a8 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -99,7 +99,7 @@ void main(unsigned long bist)
print_err("Done sdram_initialize\n"); print_err("Disable watchdog\n"); - outb( 0x87, 0x4E); //enter SuperIO configuration mode + outb( 0x87, 0x4E); //enter SuperIO configuration mode outb( 0x87, 0x4E);
outb(0x20, 0x4e); @@ -112,17 +112,17 @@ void main(unsigned long bist) outb(0x29, 0x4e); outb(0x7c, 0x4f);
- outb( 0x07, 0x4E); //enable logical device 9 + outb( 0x07, 0x4E); //enable logical device 9 outb( 0x09, 0x4F); outb(0x30, 0x4e); outb(1, 0x4f); - outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019 + outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019 outb( 0xC7, 0x4F); - outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables - temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! + outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables + temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! print_debug_hex8(temp);print_debug(":"); temp = temp & ~8; outb( temp, 0x4F); - temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! + temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! print_debug_hex8(temp);print_debug("\n"); } diff --git a/src/mainboard/lippert/hurricane-lx/devicetree.cb b/src/mainboard/lippert/hurricane-lx/devicetree.cb index 59aaa65..ca20035 100644 --- a/src/mainboard/lippert/hurricane-lx/devicetree.cb +++ b/src/mainboard/lippert/hurricane-lx/devicetree.cb @@ -8,20 +8,20 @@ chip northbridge/amd/lx # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0:host, 1:device register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero device pci 8.0 on end # Slot4 device pci 9.0 on end # Slot3 device pci a.0 on end # Slot2 @@ -30,50 +30,50 @@ chip northbridge/amd/lx device pci d.0 on end # Mini-PCI device pci e.0 on end # Ethernet device pci f.0 on # ISA Bridge - chip superio/ite/it8712f - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end + chip superio/ite/it8712f + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 # Simple I/O + io 0x64 = 0x1228 # SPI + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end end device pci f.2 on end # IDE device pci f.3 on end # Audio diff --git a/src/mainboard/lippert/hurricane-lx/irq_tables.c b/src/mainboard/lippert/hurricane-lx/irq_tables.c index 10fefcb..3f00e16 100644 --- a/src/mainboard/lippert/hurricane-lx/irq_tables.c +++ b/src/mainboard/lippert/hurricane-lx/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -58,15 +58,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x36, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}}, 0x4, 0x0}, /* slot4 */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x5, 0x0}, /* Mini-PCI */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x5, 0x0}, /* Mini-PCI */ } };
diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c index 56f6a0a..5205fff 100644 --- a/src/mainboard/lippert/hurricane-lx/mainboard.c +++ b/src/mainboard/lippert/hurricane-lx/mainboard.c @@ -53,16 +53,16 @@ static void init(struct device *dev) gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# outl(0x00000040, gpio_base + 0x08); // GPIO6 open drain 1 - LAN_PD# (jumpered GPIO per default) - outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# - outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# #if !CONFIG_BOARD_OLD_REVISION - outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz - outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz + outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz + outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz #endif - outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old) + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz (new) / PM-LED (old)
/* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { diff --git a/src/mainboard/lippert/literunner-lx/devicetree.cb b/src/mainboard/lippert/literunner-lx/devicetree.cb index 088ebca..6e2c0aa 100644 --- a/src/mainboard/lippert/literunner-lx/devicetree.cb +++ b/src/mainboard/lippert/literunner-lx/devicetree.cb @@ -8,69 +8,69 @@ chip northbridge/amd/lx # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010 - register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device + register "lpc_serirq_enable" = "0x0000129A" # 00010010 10011010 + register "lpc_serirq_polarity" = "0x0000ED65" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0:host, 1:device register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "1" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero + register "com1_enable" = "1" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero device pci 8.0 on end # Ethernet 2 device pci c.0 on end # IT8888 device pci d.0 on end # Mini-PCI device pci e.0 on end # Ethernet 1 device pci f.0 on # ISA Bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 # Simple I/O + io 0x64 = 0x1228 # SPI + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end end device pci f.2 on end # IDE device pci f.3 on end # Audio diff --git a/src/mainboard/lippert/literunner-lx/irq_tables.c b/src/mainboard/lippert/literunner-lx/irq_tables.c index 0de7919..4e2fe3e 100644 --- a/src/mainboard/lippert/literunner-lx/irq_tables.c +++ b/src/mainboard/lippert/literunner-lx/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -58,12 +58,12 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xB8, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1 */ - {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2 */ - {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* Mini-PCI */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 1 */ + {0x00, (0x08 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 2 */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* Mini-PCI */ } };
diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c index 368665e..6ff3a4e 100644 --- a/src/mainboard/lippert/literunner-lx/mainboard.c +++ b/src/mainboard/lippert/literunner-lx/mainboard.c @@ -57,14 +57,14 @@ static void init(struct device *dev) gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# - outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# - outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# - outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz - outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz - outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz + outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
/* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { diff --git a/src/mainboard/lippert/roadrunner-lx/devicetree.cb b/src/mainboard/lippert/roadrunner-lx/devicetree.cb index 6599844..2d5e7c4 100644 --- a/src/mainboard/lippert/roadrunner-lx/devicetree.cb +++ b/src/mainboard/lippert/roadrunner-lx/devicetree.cb @@ -8,20 +8,20 @@ chip northbridge/amd/lx # SIRQ Mode = Active(Quiet) mode. Save power... # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0: host, 1:device + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0: host, 1:device register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0" # End of list has a zero + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0" # End of list has a zero device pci 8.0 on end # Slot4 device pci 9.0 on end # Slot3 device pci a.0 on end # Slot2 @@ -29,50 +29,50 @@ chip northbridge/amd/lx device pci c.0 on end # IT8888 device pci e.0 on end # Ethernet device pci f.0 on # ISA bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - # io 0x64 = 0x1228 # SPI - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 # Simple I/O + # io 0x64 = 0x1228 # SPI + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end end device pci f.2 on end # IDE controller device pci f.3 on end # Audio diff --git a/src/mainboard/lippert/roadrunner-lx/irq_tables.c b/src/mainboard/lippert/roadrunner-lx/irq_tables.c index 77fc58a..3619168 100644 --- a/src/mainboard/lippert/roadrunner-lx/irq_tables.c +++ b/src/mainboard/lippert/roadrunner-lx/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -58,10 +58,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c index b8c7e4a..f966b4c 100644 --- a/src/mainboard/lippert/roadrunner-lx/mainboard.c +++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c @@ -53,11 +53,11 @@ static void init(struct device *dev) gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# - outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# - outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# - outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - PM-LED
/* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { diff --git a/src/mainboard/lippert/spacerunner-lx/devicetree.cb b/src/mainboard/lippert/spacerunner-lx/devicetree.cb index 9a56521..d9aef9d 100644 --- a/src/mainboard/lippert/spacerunner-lx/devicetree.cb +++ b/src/mainboard/lippert/spacerunner-lx/devicetree.cb @@ -8,21 +8,21 @@ chip northbridge/amd/lx # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse, # UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 - register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above - register "lpc_serirq_mode" = "1" - register "enable_gpio_int_route" = "0x0D0C0700" - register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash - register "enable_USBP4_device" = "0" # 0:host, 1:device + register "lpc_serirq_enable" = "0x000012DA" # 00010010 11011010 + register "lpc_serirq_polarity" = "0x0000ED25" # inverse of above + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "0" # 0:host, 1:device register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) - register "com1_enable" = "0" - register "com1_address" = "0x3E8" - register "com1_irq" = "6" - register "com2_enable" = "0" - register "com2_address" = "0x2E8" - register "com2_irq" = "6" - register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 - register "unwanted_vpci[1]" = "0" # End of list has a zero + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "6" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "6" + register "unwanted_vpci[0]" = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8 + register "unwanted_vpci[1]" = "0" # End of list has a zero device pci 8.0 on end # Slot4 device pci 9.0 on end # Slot3 device pci a.0 on end # Slot2 @@ -30,50 +30,50 @@ chip northbridge/amd/lx device pci c.0 on end # IT8888 device pci e.0 on end # Ethernet device pci f.0 on # ISA Bridge - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 # EC - io 0x62 = 0x298 # PME - irq 0x70 = 9 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x62 = 0x1220 # Simple I/O - io 0x64 = 0x1228 # SPI - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 # EC + io 0x62 = 0x298 # PME + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x1220 # Simple I/O + io 0x64 = 0x1228 # SPI + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end end device pci f.2 on end # IDE device pci f.3 off end # Audio diff --git a/src/mainboard/lippert/spacerunner-lx/irq_tables.c b/src/mainboard/lippert/spacerunner-lx/irq_tables.c index af7df0a..40d3e31 100644 --- a/src/mainboard/lippert/spacerunner-lx/irq_tables.c +++ b/src/mainboard/lippert/spacerunner-lx/irq_tables.c @@ -46,7 +46,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -58,10 +58,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xE0, /* u8 checksum, this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ - {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + {0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0}, /* slot1 */ {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}}, 0x2, 0x0}, /* slot2 */ {0x00, (0x09 << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}}, 0x3, 0x0}, /* slot3 */ diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c index a1be78f..704f07f 100644 --- a/src/mainboard/lippert/spacerunner-lx/mainboard.c +++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c @@ -54,14 +54,14 @@ static void init(struct device *dev) gpio_base = pci_read_config32(dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0), PCI_BASE_ADDRESS_1) - 1;
- outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# - outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# - outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# - outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# - outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz - outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz - outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz + outl(0x00000040, gpio_base + 0x00); // GPIO6 value 1 - LAN_PD# + outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD# + outl(0x04000000, gpio_base + 0x18); // GPIO10 pull up 0 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM# + outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM# + outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz + outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz + outl(0x08000000, gpio_base + 0x98); // GPIO27 pull up 0 - 32kHz
/* Init Environment Controller. */ for (i = 0; i < ARRAY_SIZE(ec_init_table); i++) { diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 6398e31..6faf1e2 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -98,14 +98,14 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -230,12 +230,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h index cf0a4be..0351773 100644 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ b/src/mainboard/lippert/toucan-af/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -56,9 +56,9 @@
//#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/lippert/toucan-af/acpi/ide.asl b/src/mainboard/lippert/toucan-af/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/lippert/toucan-af/acpi/ide.asl +++ b/src/mainboard/lippert/toucan-af/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.c b/src/mainboard/lippert/toucan-af/agesawrapper.c index 0572335..401c88a 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.c +++ b/src/mainboard/lippert/toucan-af/agesawrapper.c @@ -474,9 +474,9 @@ agesawrapper_amdinitlate ( AMD_LATE_PARAMS * AmdLateParamsPtr;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -505,8 +505,8 @@ agesawrapper_amdinitlate ( AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
@@ -526,12 +526,12 @@ agesawrapper_amdinitresume ( AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -565,15 +565,15 @@ agesawrapper_amds3laterestore ( ) { AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -609,12 +609,12 @@ agesawrapper_amdS3Save ( AGESA_STATUS Status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; + S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; diff --git a/src/mainboard/lippert/toucan-af/cmos.layout b/src/mainboard/lippert/toucan-af/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/lippert/toucan-af/cmos.layout +++ b/src/mainboard/lippert/toucan-af/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 53e12af..4fd3019 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -123,13 +123,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -148,7 +148,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -273,8 +273,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -410,16 +410,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -790,7 +790,7 @@ DefinitionBlock ( } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1181,7 +1181,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1214,8 +1214,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1223,8 +1223,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1242,8 +1242,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1252,8 +1252,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1261,8 +1261,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1270,32 +1270,32 @@ DefinitionBlock ( Name(_ADR, 0x00150000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE0) } /* APIC mode */ - Return (PE0) /* PIC Mode */ + If(PMOD){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ } /* end _PRT */ } /* end PE20 */ Device(PE21) { Name(_ADR, 0x00150001) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE1) } /* APIC mode */ - Return (PE1) /* PIC Mode */ + If(PMOD){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ } /* end _PRT */ } /* end PE21 */ Device(PE22) { Name(_ADR, 0x00150002) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE2) } /* APIC mode */ - Return (APE2) /* PIC Mode */ + If(PMOD){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ } /* end _PRT */ } /* end PE22 */ Device(PE23) { Name(_ADR, 0x00150003) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APE3) } /* APIC mode */ - Return (PE3) /* PIC Mode */ + If(PMOD){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ } /* end _PRT */ } /* end PE23 */
@@ -1559,8 +1559,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { @@ -1604,42 +1604,42 @@ DefinitionBlock ( } #endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L)
Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1648,7 +1648,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index 258d895..d729d55 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) bus_type[j] = 1;
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index f6cf09c..fc9df29 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -62,17 +62,17 @@ static void init(struct device *dev)
/* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed - FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# + FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# FCH_GPIO (197) = 0x28; // = input, disable int. pull-up - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 + FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups FCH_IOMUX( 57) = 1; FCH_GPIO ( 57) = 0x28; FCH_IOMUX( 58) = 1; FCH_GPIO ( 58) = 0x28; - FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector + FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0 FCH_IOMUX(188) = 2; FCH_GPIO (188) = 0x08; @@ -82,14 +82,14 @@ static void init(struct device *dev) FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01; FCH_IOMUX(160) = 1; FCH_GPIO (160) = 0x08; - FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector - FCH_IOMUX(190) = 1; // default to inputs with int. PU + FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector + FCH_IOMUX(190) = 1; // default to inputs with int. PU FCH_IOMUX(191) = 1; FCH_IOMUX(192) = 1; if (!fch_gpio_state(197)) // just in case anyone cares printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); printk(BIOS_INFO, "Board revision ID: %u\n", - fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); + fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
/* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */ spi_base = (u8*)(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0); diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 1c2a044..f5e5f23 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -143,13 +143,13 @@
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ #define AZALIA_AUTO 0 @@ -220,7 +220,7 @@ #define SB_GPP_UNHIDE_PORTS FALSE
/** - * @def GEC_CONFIG + * @def GEC_CONFIG * 0 - Enable * 1 - Disable */ @@ -260,15 +260,15 @@ static const CODECTBLLIST codec_tablelist[] =
/* set up an ACPI prefered power management profile */ /* from acpi.h - * PM_UNSPECIFIED = 0, - * PM_DESKTOP = 1, - * PM_MOBILE = 2, - * PM_WORKSTATION = 3, - * PM_ENTERPRISE_SERVER = 4, - * PM_SOHO_SERVER = 5, - * PM_APPLIANCE_PC = 6, + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, * PM_PERFORMANCE_SERVER = 7, - * PM_TABLET = 8 + * PM_TABLET = 8 */ #define FADT_PM_PROFILE 1
diff --git a/src/mainboard/mitac/6513wu/devicetree.cb b/src/mainboard/mitac/6513wu/devicetree.cb index 9694fc4..187d03e 100644 --- a/src/mainboard/mitac/6513wu/devicetree.cb +++ b/src/mainboard/mitac/6513wu/devicetree.cb @@ -18,16 +18,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
-chip northbridge/intel/i82810 # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device lapic 0 on end # APIC +chip northbridge/intel/i82810 # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device lapic 0 on end # APIC end end - device domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) + device domain 0 on # PCI domain + device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end - chip southbridge/intel/i82801ax # Southbridge + chip southbridge/intel/i82801ax # Southbridge register "pirqa_routing" = "0x03" register "pirqb_routing" = "0x05" register "pirqc_routing" = "0x09" @@ -36,49 +36,49 @@ chip northbridge/intel/i82810 # Northbridge register "ide0_enable" = "1" register "ide1_enable" = "1"
- device pci 1e.0 on # PCI bridge - device pci 5.0 on end # Audio controller (ESS ES1988) + device pci 1e.0 on # PCI bridge + device pci 5.0 on end # Audio controller (ESS ES1988) end - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 10 - end - device pnp 4e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 # XXX: not relocatable - io 0x62 = 0x64 # XXX: not relocatable - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 4e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 4e.a on # Runtime registers - io 0x60 = 0x400 - end - device pnp 4e.b off end # SMBus - end + device pci 1f.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47U332) + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # MIDI port (MPU-401) + io 0x60 = 0x330 + irq 0x70 = 10 + end + device pnp 4e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 # XXX: not relocatable + io 0x62 = 0x64 # XXX: not relocatable + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 4e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 4e.a on # Runtime registers + io 0x60 = 0x400 + end + device pnp 4e.b off end # SMBus + end end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # Audio controller - device pci 1f.6 off end # Modem + device pci 1f.1 on end # IDE + device pci 1f.2 on end # USB + device pci 1f.3 on end # SMbus + device pci 1f.5 off end # Audio controller + device pci 1f.6 off end # Modem end end end diff --git a/src/mainboard/mitac/6513wu/irq_tables.c b/src/mainboard/mitac/6513wu/irq_tables.c index 8e1dbfa..61bac2f 100644 --- a/src/mainboard/mitac/6513wu/irq_tables.c +++ b/src/mainboard/mitac/6513wu/irq_tables.c @@ -30,22 +30,22 @@ */
static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ - 0x00, /* Interrupt router bus */ - (0x1f << 3) | 0x0, /* Interrupt router dev */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x7000, /* Device */ - 0, /* Miniport */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb6, /* Checksum (has to be set to some value that - * would give 0 after the sum of all bytes - * for this structure (including checksum). - */ + 0xb6, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0}, {0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0}, {0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, diff --git a/src/mainboard/msi/ms6119/devicetree.cb b/src/mainboard/msi/ms6119/devicetree.cb index 159a444..d845849 100644 --- a/src/mainboard/msi/ms6119/devicetree.cb +++ b/src/mainboard/msi/ms6119/devicetree.cb @@ -9,40 +9,40 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 on # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/msi/ms6119/irq_tables.c b/src/mainboard/msi/ms6119/irq_tables.c index 89c32e7..1708d6f 100644 --- a/src/mainboard/msi/ms6119/irq_tables.c +++ b/src/mainboard/msi/ms6119/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x9c, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/msi/ms6147/devicetree.cb b/src/mainboard/msi/ms6147/devicetree.cb index 55f2745..49d39ff 100644 --- a/src/mainboard/msi/ms6147/devicetree.cb +++ b/src/mainboard/msi/ms6147/devicetree.cb @@ -9,40 +9,40 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a on # ACPI + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/msi/ms6147/irq_tables.c b/src/mainboard/msi/ms6147/irq_tables.c index c8978d1..1b00d4a 100644 --- a/src/mainboard/msi/ms6147/irq_tables.c +++ b/src/mainboard/msi/ms6147/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x20, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x0e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x12<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/msi/ms6156/devicetree.cb b/src/mainboard/msi/ms6156/devicetree.cb index 9cd1cb6..ec8e7a7 100644 --- a/src/mainboard/msi/ms6156/devicetree.cb +++ b/src/mainboard/msi/ms6156/devicetree.cb @@ -29,40 +29,40 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 off # GPIO 1 - end - device pnp 3f0.8 off # GPIO 2 - end - device pnp 3f0.9 off # GPIO 3 - end - device pnp 3f0.a off # ACPI - end - end + chip superio/winbond/w83977tf # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.7 off # GPIO 1 + end + device pnp 3f0.8 off # GPIO 2 + end + device pnp 3f0.9 off # GPIO 3 + end + device pnp 3f0.a off # ACPI + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/msi/ms6156/irq_tables.c b/src/mainboard/msi/ms6156/irq_tables.c index 816ef1a..f47c1b3 100644 --- a/src/mainboard/msi/ms6156/irq_tables.c +++ b/src/mainboard/msi/ms6156/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xb3, /* Checksum */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, {0x00, (0x12 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index 26e0e0a..87f6bff 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -33,45 +33,45 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 (only header on board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.6 off end # Consumer IR (TODO) - device pnp 2e.7 on # Game port / MIDI / GPIO 1 - io 0x60 = 0x201 - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on end # GPIO 2 - device pnp 2e.9 on end # GPIO 3 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 (only header on board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.6 off end # Consumer IR (TODO) + device pnp 2e.7 on # Game port / MIDI / GPIO 1 + io 0x60 = 0x201 + io 0x62 = 0x330 + irq 0x70 = 9 + end + device pnp 2e.8 on end # GPIO 2 + device pnp 2e.9 on end # GPIO 3 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end end device pci 1f.1 on end # IDE device pci 1f.2 on end # USB diff --git a/src/mainboard/msi/ms6178/irq_tables.c b/src/mainboard/msi/ms6178/irq_tables.c index a2c6483..1c30f9d 100644 --- a/src/mainboard/msi/ms6178/irq_tables.c +++ b/src/mainboard/msi/ms6178/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x1a, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x1e<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x10<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, diff --git a/src/mainboard/msi/ms7135/cmos.layout b/src/mainboard/msi/ms7135/cmos.layout index 694554d..76a87b1 100644 --- a/src/mainboard/msi/ms7135/cmos.layout +++ b/src/mainboard/msi/ms7135/cmos.layout @@ -1,107 +1,107 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -448 4 e 10 ram_voltage -452 4 e 11 nf4_voltage -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +448 4 e 10 ram_voltage +452 4 e 11 nf4_voltage +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy #7 3 ROM -7 8 Fallback_Network -7 9 Fallback_HDD +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
-10 0 2.55 -10 1 2.50 -10 2 2.60 -10 3 2.65 -10 4 2.70 +10 0 2.55 +10 1 2.50 +10 2 2.60 +10 3 2.65 +10 4 2.70
-11 0 1.50 -11 1 1.55 -11 2 1.60 +11 0 1.50 +11 1 1.55 +11 2 1.60
checksums
diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index a0c39b4..906e16e 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -9,63 +9,63 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1462 0x7135 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 4e.8 off end # GPIO 2 - device pnp 4e.9 off end # GPIO 3, GPIO 4 - device pnp 4e.a off end # ACPI - device pnp 4e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end # SMbus - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 (N/A) - device pci c.0 off end # PCI E 2 (N/A) - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 4e.8 off end # GPIO 2 + device pnp 4e.9 off end # GPIO 3, GPIO 4 + device pnp 4e.a off end # ACPI + device pnp 4e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end # SMbus + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 (N/A) + device pci c.0 off end # PCI E 2 (N/A) + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/msi/ms7260/cmos.layout b/src/mainboard/msi/ms7260/cmos.layout index da4de0a..e3a9bde 100644 --- a/src/mainboard/msi/ms7260/cmos.layout +++ b/src/mainboard/msi/ms7260/cmos.layout @@ -23,95 +23,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb index b35bb58..445965c 100644 --- a/src/mainboard/msi/ms7260/devicetree.cb +++ b/src/mainboard/msi/ms7260/devicetree.cb @@ -8,130 +8,130 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1462 0x7260 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 / IrDA - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - irq 0x72 = 12 # PS/2 mouse IRQ - end - device pnp 4e.106 off # Serial flash interface (SFI) - # io 0x62 = 0x100 - end - device pnp 4e.007 off # GPIO 1 - end - device pnp 4e.107 off # Game port - # io 0x60 = 0x220 # Datasheet: 0x201 - end - device pnp 4e.207 off # MIDI - # io 0x62 = 0x300 # Datasheet: 0x330 - # irq 0x70 = 9 - end - device pnp 4e.307 off # GPIO 6 - end - device pnp 4e.8 off # WDTO#, PLED - end - device pnp 4e.009 off # GPIO 2 - end - device pnp 4e.109 off # GPIO 3 - end - device pnp 4e.209 off # GPIO 4 - end - device pnp 4e.309 off # GPIO 5 - end - device pnp 4e.a off # ACPI - end - device pnp 4e.b on # Hardware monitor - io 0x60 = 0xa10 - # TODO: IRQ? - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - end - # TODO: Check if the stuff below is correct / needed. - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 (N/A on this board) - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A on this board) - device pci a.0 off end # PCI E 5 (N/A on this board?) - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # TODO: Check the two lines below. - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 / IrDA + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard IRQ + irq 0x72 = 12 # PS/2 mouse IRQ + end + device pnp 4e.106 off # Serial flash interface (SFI) + # io 0x62 = 0x100 + end + device pnp 4e.007 off # GPIO 1 + end + device pnp 4e.107 off # Game port + # io 0x60 = 0x220 # Datasheet: 0x201 + end + device pnp 4e.207 off # MIDI + # io 0x62 = 0x300 # Datasheet: 0x330 + # irq 0x70 = 9 + end + device pnp 4e.307 off # GPIO 6 + end + device pnp 4e.8 off # WDTO#, PLED + end + device pnp 4e.009 off # GPIO 2 + end + device pnp 4e.109 off # GPIO 3 + end + device pnp 4e.209 off # GPIO 4 + end + device pnp 4e.309 off # GPIO 5 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b on # Hardware monitor + io 0x60 = 0xa10 + # TODO: IRQ? + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + end + # TODO: Check if the stuff below is correct / needed. + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 off end # SATA 2 (N/A on this board) + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA (HD Audio) + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC (N/A on this board) + device pci a.0 off end # PCI E 5 (N/A on this board?) + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # TODO: Check the two lines below. + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # Link 1 device pci 18.0 on end diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index 34d3834..e5dbbb1 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -41,13 +41,13 @@ unsigned pci1234x[] = { * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c. */ 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { @@ -55,13 +55,13 @@ unsigned hcdnx[] = { * device in chain, assume every chain only have 4 ht device at most. */ 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -110,7 +110,7 @@ void get_bus_conf(void)
for (i = 2; i < 8; i++) { dev = dev_find_slot(bus_mcp55[0], - PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); if (dev) { bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..1f61109 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -71,15 +71,15 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
- /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22 + /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 1) << 2) | 1, apicid_mcp55, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 0, apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 2) << 2) | 1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 6) << 2) | 1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 0, apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 5) << 2) | 2, apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn + 8) << 2) | 0, apicid_mcp55, 0x16); // 22
for (j = 7; j >= 2; j--) { if (!bus_mcp55[j]) @@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06 + j) << 2) | i, apicid_mcp55, 0x10 + (2 + i + j) % 4); }
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_isa);
/* There is no extension information... */ diff --git a/src/mainboard/msi/ms7260/resourcemap.c b/src/mainboard/msi/ms7260/resourcemap.c index 6a9329a..51f1404 100644 --- a/src/mainboard/msi/ms7260/resourcemap.c +++ b/src/mainboard/msi/ms7260/resourcemap.c @@ -35,21 +35,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -70,25 +70,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -109,27 +109,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -150,21 +150,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -181,23 +181,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -211,23 +211,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -241,35 +241,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 96a0c1b..73065f0 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -68,12 +68,12 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/dualcore/dualcore.c"
#define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/early_setup_ss.h" #include "southbridge/nvidia/mcp55/early_setup_car.c" diff --git a/src/mainboard/msi/ms9185/cmos.layout b/src/mainboard/msi/ms9185/cmos.layout index 1c6a3cd..2cee094 100644 --- a/src/mainboard/msi/ms9185/cmos.layout +++ b/src/mainboard/msi/ms9185/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 75822ea..c3267ae 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -1,97 +1,97 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end + end + end device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - device pci e.1 on end # SATA 0x024a bx_a001 - device pci e.2 on end # SATA 0x024a bx_a001 - device pci e.3 on end # SATA 0x024a bx_a001 - end - device pci 1.0 on # Legacy pci main 0x0205 - end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end - end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # it is in bcm5785_0 bus - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # northbridge + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + device pci e.1 on end # SATA 0x024a bx_a001 + device pci e.2 on end # SATA 0x024a bx_a001 + device pci e.3 on end # SATA 0x024a bx_a001 + end + device pci 1.0 on # Legacy pci main 0x0205 + end + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # it is in bcm5785_0 bus + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # amdk8 end #domain -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 on end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 off end # cpuid +# device pnp 0.4 off end # smbus_regs_all +# device pnp 0.5 off end # dual core msr +# device pnp 0.6 off end # cache size +# device pnp 0.7 off end # tsc +# end
end
diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 3a70d83..94effe3 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -42,23 +42,23 @@ static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -107,8 +107,8 @@ void get_bus_conf(void) } } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_bcm5785_0, sysconf.sbdn); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_bcm5785_0, sysconf.sbdn); }
/* bcm5780 */ @@ -121,12 +121,12 @@ void get_bus_conf(void) pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_bcm5780[0], m->sbdn2 + i - 1); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_bcm5780[0], m->sbdn2 + i - 1); } }
-/*I/O APICs: APIC ID Version State Address*/ +/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else diff --git a/src/mainboard/msi/ms9185/irq_tables.c b/src/mainboard/msi/ms9185/irq_tables.c index a3de0ab..fb99d1b 100644 --- a/src/mainboard/msi/ms9185/irq_tables.c +++ b/src/mainboard/msi/ms9185/irq_tables.c @@ -39,11 +39,11 @@
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; + pirq_info->bus = bus; + pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -68,8 +68,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
struct mb_sysconf_t *m;
@@ -77,12 +77,12 @@ unsigned long write_pirq_routing_table(unsigned long addr)
m = sysconf.mb;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -110,14 +110,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..7e07449 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -38,35 +38,35 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc;
int i, bus_isa; struct mb_sysconf_t *m;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
-/*I/O APICs: APIC ID Version State Address*/ - { +/*I/O APICs: APIC ID Version State Address*/ + { device_t dev = 0; - struct resource *res; - for(i=0; i<3; i++) { - dev = dev_find_device(0x1166, 0x0235, dev); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); - } - } - } + struct resource *res; + for(i=0; i<3; i++) { + dev = dev_find_device(0x1166, 0x0235, dev); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base); + } + } + }
}
@@ -79,73 +79,73 @@ static void *smp_write_config_table(void *v)
//SATA outb(0x07, 0xc00); outb(0x0f, 0xc01); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
//USB outb(0x01, 0xc00); outb(0x0a, 0xc01); - for(i=0;i<3;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // - } + for(i=0;i<3;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); // + }
- /* enable int */ - /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ - { - device_t dev; - dev = dev_find_device(0x1166, 0x0205, 0); - if(dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0x6c); - dword |= (1<<4); // enable interrupts - pci_write_config32(dev, 0x6c, dword); - } - } + /* enable int */ + /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ + { + device_t dev; + dev = dev_find_device(0x1166, 0x0205, 0); + if(dev) { + uint32_t dword; + dword = pci_read_config32(dev, 0x6c); + dword |= (1<<4); // enable interrupts + pci_write_config32(dev, 0x6c, dword); + } + }
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0 // AIC 8130 Galileo Technology... - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); // + }
//pci slot (on bcm5785) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); // + }
//onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); // + }
//onboard Broadcom - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // - } + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); // + }
// First PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); // + }
// Second PCI-E x8 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); // + }
// Third PCI-E x1 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); // + }
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
diff --git a/src/mainboard/msi/ms9185/resourcemap.c b/src/mainboard/msi/ms9185/resourcemap.c index 2bac8d0..abc8dee 100644 --- a/src/mainboard/msi/ms9185/resourcemap.c +++ b/src/mainboard/msi/ms9185/resourcemap.c @@ -32,256 +32,256 @@ static void setup_ms9185_resource_map(void) { static const unsigned int register_values[] = { - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
- /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
- /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
- /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
- /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
- /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i - */ - PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203, - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, };
int max; diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 75231d6..a0e0d72 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -55,9 +55,9 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 - unsigned device = (ctrl->channel0[0]) >> 8; - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); + unsigned device = (ctrl->channel0[0]) >> 8; + smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); }
#if 0 @@ -65,14 +65,14 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); + smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } #endif
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdk8/f.h" @@ -94,33 +94,33 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node - RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, - RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, - //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + //first node + RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, + RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, + //second node + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, };
struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); //enable RTC pc87417_enable_dev(RTC_DEV); - } + }
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
@@ -141,12 +141,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); //bx_a010- wait_all_other_cores_started(bsp_apicid); #endif
@@ -157,40 +157,40 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } #endif
#if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } #endif allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); @@ -198,32 +198,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if 0 int i; for(i=0;i<2;i++) { - activate_spd_rom(sysinfo->ctrl+i); - dump_smbus_registers(); + activate_spd_rom(sysinfo->ctrl+i); + dump_smbus_registers(); } #endif
#if 0 int i; - for(i=1;i<256;i<<=1) { - change_i2c_mux(i); - dump_smbus_registers(); - } + for(i=1;i<256;i<<=1) { + change_i2c_mux(i); + dump_smbus_registers(); + } #endif
//do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
#if 0 - print_pci_devices(); + print_pci_devices(); #endif
#if 0 -// dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif
diff --git a/src/mainboard/msi/ms9282/cmos.layout b/src/mainboard/msi/ms9282/cmos.layout index 238b4ce..25e5ce5 100644 --- a/src/mainboard/msi/ms9282/cmos.layout +++ b/src/mainboard/msi/ms9282/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb index f61d6a3..513c8fd 100644 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ b/src/mainboard/msi/ms9282/devicetree.cb @@ -8,169 +8,169 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1462 0x9282 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off end # WDTO#, PLED - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux - device i2c 70 on # 0 pca9554 1 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end - end - device i2c 70 on # 0 pca9554 2 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end - end - end - end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 SMBus mux - device i2c 72 on # PCA9554 channel 1 - chip drivers/i2c/adm1027 # HWM ADT7476 1 - device i2c 2e on end - end - end - device i2c 72 on # PCA9545 channel 2 - chip drivers/i2c/adm1027 # HWM ADT7463 - device i2c 2e on end - end - end - device i2c 72 on end # PCA9545 channel 3 - device i2c 72 on # PCA9545 channel 4 - chip drivers/i2c/adm1027 # HWM ADT7476 2 - device i2c 2e on end - end - end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # P2P - device pci 4.0 on end - end - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 - device pci a.0 on - device pci 0.0 on - device pci 4.0 on end # PCI-E LAN1 - device pci 4.1 on end # PCI-E LAN2 - end - end # 0x376 - device pci b.0 on end # PCI E 0x374 - device pci c.0 on end - device pci d.0 on # SAS - device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end # PCI E 0x377, PCI-E slot - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off end # WDTO#, PLED + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux + device i2c 70 on # 0 pca9554 1 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end + end + end + device i2c 70 on # 0 pca9554 2 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end + end + end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/i2cmux2 # pca9554 SMBus mux + device i2c 72 on # PCA9554 channel 1 + chip drivers/i2c/adm1027 # HWM ADT7476 1 + device i2c 2e on end + end + end + device i2c 72 on # PCA9545 channel 2 + chip drivers/i2c/adm1027 # HWM ADT7463 + device i2c 2e on end + end + end + device i2c 72 on end # PCA9545 channel 3 + device i2c 72 on # PCA9545 channel 4 + chip drivers/i2c/adm1027 # HWM ADT7476 2 + device i2c 2e on end + end + end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # P2P + device pci 4.0 on end + end + device pci 7.0 on end # reserve + device pci 8.0 on end # MAC0 + device pci 9.0 on end # MAC1 + device pci a.0 on + device pci 0.0 on + device pci 4.0 on end # PCI-E LAN1 + device pci 4.1 on end # PCI-E LAN2 + end + end # 0x376 + device pci b.0 on end # PCI E 0x374 + device pci c.0 on end + device pci d.0 on # SAS + device pci 0.0 on end + end # PCI E 1 0x378 + device pci e.0 on end # PCI E 0 0x375 + device pci f.0 on end # PCI E 0x377, PCI-E slot + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.0 on end # Link 1 device pci 18.0 on end diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 4ab124d..06b3c31 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -44,22 +44,22 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO 0x0000ff0, 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
static unsigned get_bus_conf_done = 0; @@ -101,8 +101,8 @@ void get_bus_conf(void) m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sysconf.sbdn + 0x06); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sysconf.sbdn + 0x06); }
for (i = 2; i < 8; i++) { @@ -114,12 +114,12 @@ void get_bus_conf(void) pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } }
-/*I/O APICs: APIC ID Version State Address*/ +/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/msi/ms9282/irq_tables.c b/src/mainboard/msi/ms9282/irq_tables.c index c7cabf5..7bb9c98 100644 --- a/src/mainboard/msi/ms9282/irq_tables.c +++ b/src/mainboard/msi/ms9282/irq_tables.c @@ -38,21 +38,21 @@ #include "mb_sysconf.h"
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) + uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, + uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; }
@@ -67,19 +67,19 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c sbdn = sysconf.sbdn; m = sysconf.mb;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -105,25 +105,25 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++;
- for(i=1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - unsigned devn = sysconf.hcdn[i] & 0xff; + for(i=1; i< sysconf.hc_possible_num; i++) { + if(!(sysconf.pci1234[i] & 0x1) ) continue; + unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; + unsigned devn = sysconf.hcdn[i] & 0xff;
- write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++; }
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/msi/ms9282/mb_sysconf.h b/src/mainboard/msi/ms9282/mb_sysconf.h index 5346fc4..42e99dd 100644 --- a/src/mainboard/msi/ms9282/mb_sysconf.h +++ b/src/mainboard/msi/ms9282/mb_sysconf.h @@ -26,8 +26,8 @@ #define MB_SYSCONF_H
struct mb_sysconf_t { - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; + unsigned char bus_mcp55[8]; //1 + unsigned apicid_mcp55; };
#endif diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index c22ec18..20adaac 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -32,17 +32,17 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn;
int i, j, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); sbdn = sysconf.sbdn; @@ -50,29 +50,29 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
-/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; - struct resource *res; - uint32_t dword; +/*I/O APICs: APIC ID Version State Address*/ + { + device_t dev; + struct resource *res; + uint32_t dword;
- dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) { - smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); - } + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_1); + if (res) { + smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); + }
- dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); + dword = 0x43c6c643; + pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword);
- dword = 0xd00002d2; - pci_write_config32(dev, 0x84, dword); + dword = 0xd00002d2; + pci_write_config32(dev, 0x84, dword);
- } + }
} @@ -80,41 +80,41 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
//SMBUS - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
//USB1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
//USB2.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
//SATA1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
//SATA2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
//SATA3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
//NIC1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 //NIC2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) { - if(!m->bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } + if(!m->bus_mcp55[j]) continue; + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + } }
for(j=0; j<1; j++) - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); + }
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ +/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
diff --git a/src/mainboard/msi/ms9282/resourcemap.c b/src/mainboard/msi/ms9282/resourcemap.c index a16eb2e..7f89292 100644 --- a/src/mainboard/msi/ms9282/resourcemap.c +++ b/src/mainboard/msi/ms9282/resourcemap.c @@ -33,261 +33,261 @@ static void setup_ms9282_resource_map(void) { static const unsigned int register_values[] = { #if 1 - /* Careful set limit registers before base registers which contain the enables */ - /* DRAM Limit i Registers - * F1:0x44 i = 0 - * F1:0x4C i = 1 - * F1:0x54 i = 2 - * F1:0x5C i = 3 - * F1:0x64 i = 4 - * F1:0x6C i = 5 - * F1:0x74 i = 6 - * F1:0x7C i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 3] Reserved - * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. - * [15:11] Reserved - * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, - /* DRAM Base i Registers - * F1:0x40 i = 0 - * F1:0x48 i = 1 - * F1:0x50 i = 2 - * F1:0x58 i = 3 - * F1:0x60 i = 4 - * F1:0x68 i = 5 - * F1:0x70 i = 6 - * F1:0x78 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 7: 2] Reserved - * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) - * [15:11] Reserved - * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. - */ - PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, #endif #if 1
- /* Memory-Mapped I/O Limit i Registers - * F1:0x84 i = 0 - * F1:0x8C i = 1 - * F1:0x94 i = 2 - * F1:0x9C i = 3 - * F1:0xA4 i = 4 - * F1:0xAC i = 5 - * F1:0xB4 i = 6 - * F1:0xBC i = 7 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved - * [ 6: 6] Reserved - * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted - * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n - */ - PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
- /* Memory-Mapped I/O Base i Registers - * F1:0x80 i = 0 - * F1:0x88 i = 1 - * F1:0x90 i = 2 - * F1:0x98 i = 3 - * F1:0xA0 i = 4 - * F1:0xA8 i = 5 - * F1:0xB0 i = 6 - * F1:0xB8 i = 7 - * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled - * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range - * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only - * [ 7: 4] Reserved - * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i - */ - PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, -// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, #endif #if 1
- /* PCI I/O Limit i Registers - * F1:0xC4 i = 0 - * F1:0xCC i = 1 - * F1:0xD4 i = 2 - * F1:0xDC i = 3 - * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 3: 3] Reserved - * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved - * [11: 6] Reserved - * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
- /* PCI I/O Base i Registers - * F1:0xC0 i = 0 - * F1:0xC8 i = 1 - * F1:0xD0 i = 2 - * F1:0xD8 i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 3: 2] Reserved - * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers - * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair - * [11: 6] Reserved - * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n - * [31:25] Reserved - */ - PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, - PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, #endif - /* Config Base and Limit i Registers - * F1:0xE0 i = 0 - * F1:0xE4 i = 1 - * F1:0xE8 i = 2 - * F1:0xEC i = 3 - * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled - * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled - * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 - * [ 3: 3] Reserved - * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 - * [ 7: 7] Reserved - * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved - * [15:10] Reserved - * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i - * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i - */ + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration region i + */ #if 1 -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, -// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, - PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, +// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, #endif
}; diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index dffcf1b..d165d31 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -53,9 +53,9 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITCH2 0x72 - unsigned device=(ctrl->channel0[0])>>8; - smbus_send_byte(SMBUS_SWITCH1, device); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + unsigned device=(ctrl->channel0[0])>>8; + smbus_send_byte(SMBUS_SWITCH1, device); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); }
#if 0 @@ -63,8 +63,8 @@ static inline void change_i2c_mux(unsigned device) { #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITHC2 0x72 - smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } #endif
@@ -84,10 +84,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//set GPIO to input mode #define MCP55_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -98,16 +98,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte;
- byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); }
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. @@ -126,20 +126,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) };
unsigned bsp_apicid = 0; - int needs_reset; + int needs_reset; struct sys_info *sysinfo = &sysinfo_car;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + }
- if (bist == 0) { - //init_cpus(cpu_init_detectedx); - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } + if (bist == 0) { + //init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + }
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -154,33 +154,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - //wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + //wait_all_other_cores_started(bsp_apicid); #endif - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + }
- //It's the time to set ctrl now; - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + //It's the time to set ctrl now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
#if 0 - int i; - for(i=4;i<8;i++) { - change_i2c_mux(i); - dump_smbus_registers(); - } + int i; + for(i=4;i<8;i++) { + change_i2c_mux(i); + dump_smbus_registers(); + } #endif
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 89b6a1e..9881eda 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -31,132 +31,132 @@ chip northbridge/amd/amdfam10/root_complex # Root complex subsystemid 0x1462 0x9652 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + # chip drivers/generic/generic # MAC EEPROM + # device i2c 51 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # HT 1.0 device pci 18.0 on end # HT 2.0 diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index 8717f19..62a6a24 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -53,21 +53,21 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) External (HCDN)
Method (_CRS, 0, NotSerialized) - { + { Name (BUF0, ResourceTemplate () { IO (Decode16, - 0x0CF8, // Address Range Minimum - 0x0CF8, // Address Range Maximum - 0x01, // Address Alignment - 0x08, // Address Length + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Address Space Granularity - 0x0000, // Address Range Minimum - 0x0CF7, // Address Range Maximum - 0x0000, // Address Translation Offset - 0x0CF8, // Address Length + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length ,, , TypeStatic) }) /* Methods bellow use SSDT to get actual MMIO regs diff --git a/src/mainboard/msi/ms9652_fam10/resourcemap.c b/src/mainboard/msi/ms9652_fam10/resourcemap.c index 56522b9..a84ae52 100644 --- a/src/mainboard/msi/ms9652_fam10/resourcemap.c +++ b/src/mainboard/msi/ms9652_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00004000, @@ -210,23 +210,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ /* Verified against board configuration registers after normal proprietary BIOS boot */ @@ -242,35 +242,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ /* Verified against board configuration registers after normal proprietary BIOS boot */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 2571215..c090969 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -256,8 +256,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index cd4aefe..b0af345 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -13,35 +13,35 @@ chip northbridge/intel/i82810 # Northbridge
device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off end # Com2 (N/A) - device pnp 2e.7 on # PS/2 keyboard - irq 0x70 = 1 - irq 0x72 = 0 - end - device pnp 2e.9 off end # Game port (N/A) - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x800 - end - device pnp 2e.b on # MIDI port - io 0x60 = 0x330 - irq 0x70 = 5 - end - end + chip superio/smsc/smscsuperio # Super I/O (SMSC LPC47B27x) + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off end # Com2 (N/A) + device pnp 2e.7 on # PS/2 keyboard + irq 0x70 = 1 + irq 0x72 = 0 + end + device pnp 2e.9 off end # Game port (N/A) + device pnp 2e.a on # Power-management events (PME) + io 0x60 = 0x800 + end + device pnp 2e.b on # MIDI port + io 0x60 = 0x330 + irq 0x70 = 5 + end + end end device pci 1f.1 on end # IDE device pci 1f.2 on end # USB diff --git a/src/mainboard/nec/powermate2000/irq_tables.c b/src/mainboard/nec/powermate2000/irq_tables.c index f209786..342b0fb 100644 --- a/src/mainboard/nec/powermate2000/irq_tables.c +++ b/src/mainboard/nec/powermate2000/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x6e, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x1e << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0}, {0x01, (0x03 << 3) | 0x0, {{0x61, 0xdef8}, {0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, {0x01, (0x04 << 3) | 0x0, {{0x62, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, diff --git a/src/mainboard/newisys/khepri/cmos.layout b/src/mainboard/newisys/khepri/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/newisys/khepri/cmos.layout +++ b/src/mainboard/newisys/khepri/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index bd00d28..6e96719 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -9,7 +9,7 @@ chip northbridge/amd/amdk8/root_complex subsystemid 0x17c2 0x0010 inherit chip northbridge/amd/amdk8 device pci 18.0 on end # LDT 0 - device pci 18.0 on # LDT 1 + device pci 18.0 on # LDT 1 chip southbridge/amd/amd8131 device pci 0.0 on end device pci 0.1 on end @@ -26,43 +26,43 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off # CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 - end + end end end device pci 1.1 on end diff --git a/src/mainboard/newisys/khepri/irq_tables.c b/src/mainboard/newisys/khepri/irq_tables.c index bbdb7e6..ce8e2d9 100644 --- a/src/mainboard/newisys/khepri/irq_tables.c +++ b/src/mainboard/newisys/khepri/irq_tables.c @@ -2,16 +2,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0x0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0x0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xb0, /* u8 checksum , mod 256 checksum must give zero */ + 0xb0, /* u8 checksum , mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ /* PCI Slot 1 */ {0x03, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0}, @@ -35,5 +35,5 @@ static const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/newisys/khepri/resourcemap.c b/src/mainboard/newisys/khepri/resourcemap.c index 81bdefa..ddb74a2c 100644 --- a/src/mainboard/newisys/khepri/resourcemap.c +++ b/src/mainboard/newisys/khepri/resourcemap.c @@ -208,11 +208,11 @@ static void setup_khepri_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 7af39e4..2c8696b 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -77,53 +77,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8];
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_khepri_resource_map(); + setup_khepri_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
- enable_smbus(); + enable_smbus();
- memreset_setup(); - sdram_initialize(nodes, ctrl); + memreset_setup(); + sdram_initialize(nodes, ctrl);
#if 0 dump_pci_devices(); diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index 181155a..e6ab353 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -29,7 +29,7 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci f.0 on - chip southbridge/ti/pci1x2x + chip southbridge/ti/pci1x2x device pci 00.0 on subsystemid 0x13b8 0x0000 end @@ -38,67 +38,67 @@ chip northbridge/intel/i440bx # Northbridge end end device pci 7.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) - device pnp 3f0.0 off end # Floppy (No connector) - device pnp 3f0.3 off end # Parallel port (No connector) - device pnp 3f0.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.6 on # RTC - irq 0x63 = 0x72 - end - device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) - end - device pnp 3f0.8 on # AUX I/O - irq 0x24 = 0x84 # OSC + chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37B787) + device pnp 3f0.0 off end # Floppy (No connector) + device pnp 3f0.3 off end # Parallel port (No connector) + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.6 on # RTC + irq 0x63 = 0x72 + end + device pnp 3f0.7 off # PS/2 keyboard / mouse (No connector) + end + device pnp 3f0.8 on # AUX I/O + irq 0x24 = 0x84 # OSC
- irq 0xB2 = 0x0C # Soft power status 1 - irq 0xB3 = 0x05 # Soft power status 2 - irq 0xC0 = 0x03 # IRQ MUX control + irq 0xB2 = 0x0C # Soft power status 1 + irq 0xB3 = 0x05 # Soft power status 2 + irq 0xC0 = 0x03 # IRQ MUX control
- irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable - irq 0xCA = 0x09 # GP52 = IRQ8 (output) - irq 0xCB = 0x01 # GP53 = nROMCS (output) - irq 0xCC = 0x11 # GP54 = (I/O) input - irq 0xF9 = 0x00 # read/write GP5x lines (0x1C) + irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable + irq 0xCA = 0x09 # GP52 = IRQ8 (output) + irq 0xCB = 0x01 # GP53 = nROMCS (output) + irq 0xCC = 0x11 # GP54 = (I/O) input + irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
- irq 0xD0 = 0x08 # GP60 = IRQ1 - irq 0xD1 = 0x08 # GP61 = IRQ3 - irq 0xD2 = 0x08 # GP62 = IRQ4 - irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board - irq 0xD4 = 0x11 # GP64 = (I/O) input - irq 0xD5 = 0x11 # GP65 = (I/O) input - irq 0xD6 = 0x08 # GP66 = IRQ8 - irq 0xD7 = 0x11 # GP67 = (I/O) input - irq 0xFA = 0x00 # read/write GP6x lines (0x88) + irq 0xD0 = 0x08 # GP60 = IRQ1 + irq 0xD1 = 0x08 # GP61 = IRQ3 + irq 0xD2 = 0x08 # GP62 = IRQ4 + irq 0xD3 = 0x11 # GP63 = (I/O) input = JP901 on board + irq 0xD4 = 0x11 # GP64 = (I/O) input + irq 0xD5 = 0x11 # GP65 = (I/O) input + irq 0xD6 = 0x08 # GP66 = IRQ8 + irq 0xD7 = 0x11 # GP67 = (I/O) input + irq 0xFA = 0x00 # read/write GP6x lines (0x88)
- irq 0xE0 = 0x00 # GP10 (I/O) = output - irq 0xE1 = 0x01 # GP11 (I/O) = input - irq 0xE2 = 0x08 # GP12 = P17 - irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low - irq 0xE4 = 0x00 # GP14 (I/O) = output - irq 0xE5 = 0x00 # GP15 (I/O) = output - irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open - irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low - irq 0xF6 = 0xFF # read/write GP1x lines (0xCA) + irq 0xE0 = 0x00 # GP10 (I/O) = output + irq 0xE1 = 0x01 # GP11 (I/O) = input + irq 0xE2 = 0x08 # GP12 = P17 + irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low + irq 0xE4 = 0x00 # GP14 (I/O) = output + irq 0xE5 = 0x00 # GP15 (I/O) = output + irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open + irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low + irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
- irq 0xEF = 0x00 # GP_INT2 disable - irq 0xF0 = 0x00 # GP_INT1 disable - irq 0xF1 = 0x00 # WDT_UNITS - irq 0xF2 = 0x00 # WDT_VAL - irq 0xF3 = 0x00 # WDT_CFG - irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) - end - device pnp 3f0.a off # ACPI (No support yet) - # irq 0x60 = 0x0C - # irq 0x61 = 0x80 - end - end + irq 0xEF = 0x00 # GP_INT2 disable + irq 0xF0 = 0x00 # GP_INT1 disable + irq 0xF1 = 0x00 # WDT_UNITS + irq 0xF2 = 0x00 # WDT_VAL + irq 0xF3 = 0x00 # WDT_CFG + irq 0xF4 = 0x20 # WDT_CTRL (stop-cnt) + end + device pnp 3f0.a off # ACPI (No support yet) + # irq 0x60 = 0x0C + # irq 0x61 = 0x80 + end + end end device pci 7.1 on end # IDE device pci 7.2 off end # USB (No connector) diff --git a/src/mainboard/nokia/ip530/irq_tables.c b/src/mainboard/nokia/ip530/irq_tables.c index 89ed775..e55873b 100644 --- a/src/mainboard/nokia/ip530/irq_tables.c +++ b/src/mainboard/nokia/ip530/irq_tables.c @@ -37,7 +37,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { /** * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller. - * FEDCBA9876543210 + * FEDCBA9876543210 * 0x1E20 = 0001111000100000 * 0x0C60 = 0000110001100000 */ diff --git a/src/mainboard/nvidia/l1_2pvv/cmos.layout b/src/mainboard/nvidia/l1_2pvv/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/nvidia/l1_2pvv/cmos.layout +++ b/src/mainboard/nvidia/l1_2pvv/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 363d1a8..ef11371 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -8,169 +8,169 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x1022 0x2b80 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/nvidia/l1_2pvv/resourcemap.c b/src/mainboard/nvidia/l1_2pvv/resourcemap.c index b06aaf3..8bf2b58 100644 --- a/src/mainboard/nvidia/l1_2pvv/resourcemap.c +++ b/src/mainboard/nvidia/l1_2pvv/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ diff --git a/src/mainboard/pcengines/alix1c/cmos.layout b/src/mainboard/pcengines/alix1c/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/pcengines/alix1c/cmos.layout +++ b/src/mainboard/pcengines/alix1c/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 85e967a..8bc7b5a 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/lx register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0" # End of list has a zero - device pci f.0 on # ISA Bridge + device pci f.0 on # ISA Bridge chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 @@ -69,8 +69,8 @@ chip northbridge/amd/lx end device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI + device pci f.3 on end # Audio + device pci f.4 on end # OHCI device pci f.5 on end # EHCI end end diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c index 9ee8a07..095ce6a 100644 --- a/src/mainboard/pcengines/alix1c/irq_tables.c +++ b/src/mainboard/pcengines/alix1c/irq_tables.c @@ -57,15 +57,15 @@ * * The only devices that interrupt are: * - * What Device IRQ PIN PIN WIRED TO + * What Device IRQ PIN PIN WIRED TO * ------------------------------------------------- - * AES 00:01.2 0a 01 A A - * 3VPCI 00:0c.0 0a 01 A A - * eth0 00:0d.0 0b 01 A B - * mpci 00:0e.0 0a 01 A A - * usb 00:0f.3 0b 02 B B - * usb 00:0f.4 0b 04 D D - * usb 00:0f.5 0b 04 D D + * AES 00:01.2 0a 01 A A + * 3VPCI 00:0c.0 0a 01 A A + * eth0 00:0d.0 0b 01 A B + * mpci 00:0e.0 0a 01 A A + * usb 00:0f.3 0b 02 B B + * usb 00:0f.4 0b 04 D D + * usb 00:0f.5 0b 04 D D * * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B. */ @@ -75,7 +75,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ 0x100B, /* Vendor */ 0x002B, /* Device */ @@ -85,7 +85,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
/* CPU */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, diff --git a/src/mainboard/pcengines/alix2d/cmos.layout b/src/mainboard/pcengines/alix2d/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/pcengines/alix2d/cmos.layout +++ b/src/mainboard/pcengines/alix2d/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index d8aa3bc..114f2f7 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -21,12 +21,12 @@ chip northbridge/amd/lx register "com1_enable" = "1" register "com1_address" = "0x3F8" register "com1_irq" = "4" - register "com2_enable" = "1" # Wired on Alix.2D13 only + register "com2_enable" = "1" # Wired on Alix.2D13 only register "com2_address" = "0x2F8" register "com2_irq" = "3" register "unwanted_vpci[0]" = "0x80000900" # Disable VGA controller (not wired) register "unwanted_vpci[1]" = "0x80007B00" # Disable AC97 controller (not wired) - register "unwanted_vpci[2]" = "0" # End of list has a zero + register "unwanted_vpci[2]" = "0" # End of list has a zero device pci f.0 on end # ISA Bridge device pci f.1 on end # Flash controller device pci f.2 on end # IDE controller diff --git a/src/mainboard/pcengines/alix2d/irq_tables.c b/src/mainboard/pcengines/alix2d/irq_tables.c index cdfaa88..99b4993 100644 --- a/src/mainboard/pcengines/alix2d/irq_tables.c +++ b/src/mainboard/pcengines/alix2d/irq_tables.c @@ -56,16 +56,16 @@
* The only devices that interrupt are: * - * What Device IRQ PIN PIN WIRED TO + * What Device IRQ PIN PIN WIRED TO * ------------------------------------------------- - * AES 00:01.2 0a 01 A A - * eth0 00:09.0 0b 01 A B - * eth1 00:0a.0 0b 01 A C - * eth2 00:0b.0 0b 01 A D - * mpci 00:0c.0 0a 01 A A - * mpci 00:0c.0 0b 02 B B - * usb 00:0f.4 0b 04 D D - * usb 00:0f.5 0b 04 D D + * AES 00:01.2 0a 01 A A + * eth0 00:09.0 0b 01 A B + * eth1 00:0a.0 0b 01 A C + * eth2 00:0b.0 0b 01 A D + * mpci 00:0c.0 0a 01 A A + * mpci 00:0c.0 0b 02 B B + * usb 00:0f.4 0b 04 D D + * usb 00:0f.5 0b 04 D D * * The only swizzled interrupts are the ethernet controllers, where INTA is wired to * interrupt controller lines B, C and D. @@ -76,7 +76,7 @@ static const struct irq_routing_table intel_irq_routing_table = { PIRQ_VERSION, 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ 0x00, /* IRQs devoted exclusively to PCI usage */ 0x100B, /* Vendor */ 0x002B, /* Device */ @@ -86,7 +86,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
/* CPU */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6946900..20b4ddd 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -111,22 +111,22 @@ static void mb_gpio_init(void) * Enable LEDs GPIO outputs to light up the leds * This is how the original tinyBIOS sets them after boot. * Info: GPIO_IO_BASE, 0x6100, is only valid before PCI init, so it - * may be used here, but not after PCI Init. + * may be used here, but not after PCI Init. * Note: Prior to a certain release, Linux used a hardwired 0x6100 in the - * leds-alix2.c driver. Coreboot dynamically assigns this space, - * so the driver does not work anymore. - * Good workaround: use the newer driver - * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100 - * This resets the GPIO I/O space to 0x6100. - * This may break other things, though. + * leds-alix2.c driver. Coreboot dynamically assigns this space, + * so the driver does not work anymore. + * Good workaround: use the newer driver + * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100 + * This resets the GPIO I/O space to 0x6100. + * This may break other things, though. */ outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */ - outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */ - outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ + outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */ + outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ }
void main(unsigned long bist) diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index d39126c..2433042 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -26,37 +26,37 @@ chip northbridge/intel/i82830 # Northbridge device pci 1d.7 on end # USB2 EHCI Controller device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # Com2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME - io 0x60 = 0x800 - end - device pnp 2e.b off end # MPU-401 - end + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.9 off end # Game port + device pnp 2e.a on # PME + io 0x60 = 0x800 + end + device pnp 2e.b off end # MPU-401 + end end device pci 1f.1 on end # IDE device pci 1f.3 on end # SMBus diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index 0527b68..2d7d27d 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -19,7 +19,7 @@ */
#define PME_DEV PNP_DEV(0x2e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ #define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
/* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c index 767ab75..4641fdb 100644 --- a/src/mainboard/rca/rm4100/irq_tables.c +++ b/src/mainboard/rca/rm4100/irq_tables.c @@ -22,18 +22,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x24c0, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h index 050bf72..9a1a5b9 100644 --- a/src/mainboard/rca/rm4100/spd_table.h +++ b/src/mainboard/rca/rm4100/spd_table.h @@ -30,11 +30,11 @@ struct spd_entry { * have to be set manually, the onboard memory is located in socket1 (0x51). */ const struct spd_entry spd_table [] = { - {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ - {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ - {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ - {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ + {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ + {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ + {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ + {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ - {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ + {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */ }; diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index 5de4a83..4e704b0 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -151,13 +151,13 @@ Scope(_SB) * We have to do this in order to be able to work around * certain windows bugs. * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 */
/* Let's assume we're running at least Windows 2000 */ diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index c879078..4b2deb6 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -23,123 +23,123 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# ram initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 7b9d7a1..a22c201 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -21,21 +21,21 @@
chip northbridge/intel/i945
- device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end
- device domain 0 on - subsystemid 0x4352 0x6886 inherit - device pci 00.0 on end # host bridge + device domain 0 on + subsystemid 0x4352 0x6886 inherit + device pci 00.0 on end # host bridge # auto detection: #device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller
- chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" register "pirqc_routing" = "0x0b" @@ -54,26 +54,26 @@ chip northbridge/intel/i945 register "gpi7_routing" = "2" register "gpe0_en" = "0x20800007"
- register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0"
- device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on chip southbridge/ti/pci7420 - register "smartcard_enabled" = "0x0" + register "smartcard_enabled" = "0x0" device pci 3.0 on end device pci 3.1 on end device pci 3.2 on end @@ -82,19 +82,19 @@ chip northbridge/intel/i945 end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47n227 + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 irq 0x70 = 5 end device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + io 0x60 = 0x3f8 + irq 0x70 = 4 end device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + io 0x60 = 0x2f8 + irq 0x70 = 3 end device pnp 2e.5 off # Keyboard+Mouse # io 0x60 = 0x60 @@ -102,7 +102,7 @@ chip northbridge/intel/i945 # irq 0x70 = 1 # irq 0x72 = 12 end - end + end chip superio/renesas/m3885x device pnp ff.1 on # dummy address end @@ -110,11 +110,11 @@ chip northbridge/intel/i945 chip ec/acpi end
- end + end #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus #device pci 1f.4 off end # Realtek ID Codec - end - end + end + end end diff --git a/src/mainboard/roda/rk886ex/irq_tables.c b/src/mainboard/roda/rk886ex/irq_tables.c index d2e4f78..bda513c 100644 --- a/src/mainboard/roda/rk886ex/irq_tables.c +++ b/src/mainboard/roda/rk886ex/irq_tables.c @@ -23,10 +23,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*18, /* There can be total 18 devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x27b0, /* Device */ @@ -34,7 +34,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xf, /* u8 checksum. */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01<<3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02<<3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA {0x00,(0x1e<<3)|0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // PCI bridge diff --git a/src/mainboard/roda/rk886ex/m3885.c b/src/mainboard/roda/rk886ex/m3885.c index 29d12bc..7f5e2e5 100644 --- a/src/mainboard/roda/rk886ex/m3885.c +++ b/src/mainboard/roda/rk886ex/m3885.c @@ -107,8 +107,8 @@ static u8 function_ram[] = { #define KBD_DATA 0x60 #define KBD_SC 0x64
-#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
static int send_kbd_command(u8 command) { diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c index 9b59bb4..69f8f60 100644 --- a/src/mainboard/roda/rk886ex/mptable.c +++ b/src/mainboard/roda/rk886ex/mptable.c @@ -29,14 +29,14 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* Onboard Ethernet */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index cb141f9..16a43a3 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -69,7 +69,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { - lpt_en = 1<<2; // enable LPT + lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl index 3e6cb98..4b566fa 100644 --- a/src/mainboard/roda/rk9/acpi/ec.asl +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -33,17 +33,17 @@ Device(EC0) Field (ERAM, ByteAcc, NoLock, Preserve) { Offset(0xb1), - CPWR, 1, - ACCH, 1, // AC connected (charger present) - B1PR, 1, // battery 1 present - B2PR, 1, // battery 2 present - B1CH, 1, // battery 1 charged - B2CH, 1, // battery 2 charged + CPWR, 1, + ACCH, 1, // AC connected (charger present) + B1PR, 1, // battery 1 present + B2PR, 1, // battery 2 present + B1CH, 1, // battery 1 charged + B2CH, 1, // battery 2 charged Offset(0xb2), - B1CG, 1, // battery 1 charging - B2CG, 1, // battery 2 charging - B1LO, 1, // battery 1 low - B2LO, 1, // battery 2 low + B1CG, 1, // battery 1 charging + B2CG, 1, // battery 2 charging + B1LO, 1, // battery 1 low + B2LO, 1, // battery 2 low Offset(0xb3), B1DW, 16, // battery 1 design capacity B1FW, 16, // battery 1 last full charge capacity @@ -59,16 +59,16 @@ Device(EC0) Offset(0xcb), B2PV, 16, // battery 2 present voltage Offset(0xcf), - FDDI, 1, // floppy on lpt indicator? - LIDC, 1, // LID switch + FDDI, 1, // floppy on lpt indicator? + LIDC, 1, // LID switch Offset(0xd0), - TCPU, 8, // T_CPU in deg Celcius + TCPU, 8, // T_CPU in deg Celcius Offset(0xd6), /* exact purpose of these three is guessed, but it's something about cooling */ - ALRL, 1, // active cooling low limit - ALRH, 1, // active cooling high limit - ALRC, 1, // active cooling clear + ALRL, 1, // active cooling low limit + ALRH, 1, // active cooling high limit + ALRC, 1, // active cooling clear Offset(0xe8), B1RW, 16, // battery 1 remaining capacity B2RW, 16, // battery 2 remaining capacity diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl index b85433f..2bbc951 100644 --- a/src/mainboard/roda/rk9/acpi/platform.asl +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -154,13 +154,13 @@ Scope(_SB) * We have to do this in order to be able to work around * certain windows bugs. * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 */
/* Let's assume we're running at least Windows 2000 */ diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index 5c82567..fad3ca0 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -2,7 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2007-2008 coresystems GmbH -# 2012 secunet Security Networks AG +# 2012 secunet Security Networks AG # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -24,115 +24,115 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -#400 8 r 0 unused +#400 8 r 0 unused
# coreboot config options: southbridge -#408 8 r 0 unused +#408 8 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -#937 7 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +#937 7 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 unused +984 16 h 0 check_sum +#1000 24 r 0 unused
# ram initialization internal data -1024 128 r 0 read_training_results +1024 128 r 0 read_training_results
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index fef9721..f111523 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -92,7 +92,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ - /* then FIRMWARE_CTRL must be zero. */ + /* then FIRMWARE_CTRL must be zero. */ fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0;
diff --git a/src/mainboard/roda/rk9/hda_verb.h b/src/mainboard/roda/rk9/hda_verb.h index f99d097..81d5f05 100644 --- a/src/mainboard/roda/rk9/hda_verb.h +++ b/src/mainboard/roda/rk9/hda_verb.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 075790d..89ff658 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -45,8 +45,8 @@ static void default_southbridge_gpio_setup(void) /* Set input/output mode [31:0] (0 == out, 1 == in). */ outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, - WLAN, ~ANTMUX, ~GPIO12, - ~SUSPWR, SMBALERT) */ + WLAN, ~ANTMUX, ~GPIO12, + ~SUSPWR, SMBALERT) */ outl(0x00000800, DEFAULT_GPIOBASE + 0x0c);
/* Disable blink [31:0]. */ @@ -59,8 +59,8 @@ static void default_southbridge_gpio_setup(void) /* Set input/output mode [60:32] (0 == out, 1 == in). */ outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, - DMITERM, TXT, ~CLKSATA, - GPS, AUDIO) */ + DMITERM, TXT, ~CLKSATA, + GPS, AUDIO) */ outl(0x10020042, DEFAULT_GPIOBASE + 0x38); }
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl index 01d9447..27abe9d 100644 --- a/src/mainboard/samsung/lumpy/acpi/superio.asl +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -19,20 +19,20 @@
/* Values should match those defined in devicetree.cb */
-#define SIO_ENABLE_SPM1 // pnp 2e.1: Enable ACPI PM1 Block -#define SIO_SPM1_IO0 0xb00 // pnp 2e.1: io 0x60 +#define SIO_ENABLE_SPM1 // pnp 2e.1: Enable ACPI PM1 Block +#define SIO_SPM1_IO0 0xb00 // pnp 2e.1: io 0x60
-#undef SIO_ENABLE_SEC1 // pnp 2e.2: Disable EC 1 +#undef SIO_ENABLE_SEC1 // pnp 2e.2: Disable EC 1
-#undef SIO_ENABLE_SEC2 // pnp 2e.3: Disable EC 2 +#undef SIO_ENABLE_SEC2 // pnp 2e.3: Disable EC 2
-#undef SIO_ENABLE_SSP1 // pnp 2e.4: Disable UART +#undef SIO_ENABLE_SSP1 // pnp 2e.4: Disable UART
-#define SIO_ENABLE_SKBC // pnp 2e.7: Enable Keyboard +#define SIO_ENABLE_SKBC // pnp 2e.7: Enable Keyboard
-#undef SIO_ENABLE_SEC0 // pnp 2e.8: Already exported as EC +#undef SIO_ENABLE_SEC0 // pnp 2e.8: Already exported as EC
-#define SIO_ENABLE_SMBX // pnp 2e.9: Enable Mailbox -#define SIO_SMBX_IO0 0xa00 // pnp 2e.9: io 0xa00 +#define SIO_ENABLE_SMBX // pnp 2e.9: Enable Mailbox +#define SIO_SMBX_IO0 0xa00 // pnp 2e.9: io 0xa00
#include "superio/smsc/mec1308/acpi/superio.asl" diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 13e9e0f..ca0dcf2 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -242,7 +242,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..088ac8f 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..17c89c4 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -117,11 +117,11 @@ chip northbridge/intel/sandybridge end
chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "irq_on_fsb" = "1" - register "enable_virtual_wire" = "1" - register "base" = "0xfec00000" - device ioapic 4 on end + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 4 on end end end device pci 1f.2 on # SATA Controller 1 diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index c1c9685..163b0ed 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock( "DSDT", 0x02, // DSDT revision: ACPI v2.0 "COREv4", // OEM id - "COREBOOT", // OEM table id + "COREBOOT", // OEM table id 0x20110725 // OEM revision ) { diff --git a/src/mainboard/samsung/lumpy/ec.h b/src/mainboard/samsung/lumpy/ec.h index 3f90211..30f6725 100644 --- a/src/mainboard/samsung/lumpy/ec.h +++ b/src/mainboard/samsung/lumpy/ec.h @@ -20,41 +20,41 @@ #ifndef LUMPY_EC_H #define LUMPY_EC_H
-#define EC_MAILBOX_PORT 0xa00 /* Mailbox IO address */ -#define EC_SMI_GPI 1 /* GPIO 1 is KBC3_EXTSMI# */ +#define EC_MAILBOX_PORT 0xa00 /* Mailbox IO address */ +#define EC_SMI_GPI 1 /* GPIO 1 is KBC3_EXTSMI# */
/* Commands */ -#define EC_SMI_ENABLE 0x74 -#define EC_SMI_DISABLE 0x75 -#define EC_ACPI_ENABLE 0x76 /* Enter ACPI mode */ -#define EC_ACPI_DISABLE 0x77 /* Exit ACPI mode */ +#define EC_SMI_ENABLE 0x74 +#define EC_SMI_DISABLE 0x75 +#define EC_ACPI_ENABLE 0x76 /* Enter ACPI mode */ +#define EC_ACPI_DISABLE 0x77 /* Exit ACPI mode */
/* Commands with data */ -#define EC_AUX_PORT_MODE 0x64 /* PS/2 control mode */ +#define EC_AUX_PORT_MODE 0x64 /* PS/2 control mode */ #define EC_AUX_PORT_MODE_ENABLE 0x00 #define EC_AUX_PORT_MODE_DISABLE 0x01 -#define EC_POWER_BUTTON_MODE 0x63 +#define EC_POWER_BUTTON_MODE 0x63 #define EC_POWER_BUTTON_MODE_OS 0x00 /* OS control, 8 second override */ #define EC_POWER_BUTTON_MODE_EC 0x01 /* EC control */ -#define EC_BACKLIGHT_OFF 0x67 /* Turn Backlight Off */ -#define EC_BACKLIGHT_ON 0x68 /* Turn Backlight On */ -#define EC_BATTERY_MODE 0x13 -#define EC_BATTERY_MODE_NORMAL 0x00 /* Normal mode */ -#define EC_BATTERY_MODE_EXTEND 0x01 /* Battery Life Cycle Extension */ -#define EC_GET_SMI_CAUSE 0x72 /* Get cause of SMI */ +#define EC_BACKLIGHT_OFF 0x67 /* Turn Backlight Off */ +#define EC_BACKLIGHT_ON 0x68 /* Turn Backlight On */ +#define EC_BATTERY_MODE 0x13 +#define EC_BATTERY_MODE_NORMAL 0x00 /* Normal mode */ +#define EC_BATTERY_MODE_EXTEND 0x01 /* Battery Life Cycle Extension */ +#define EC_GET_SMI_CAUSE 0x72 /* Get cause of SMI */
/* EC RAM */ -#define EC_FAN_SPEED 0xca -#define EC_FAN_SPEED_LEVEL_0 0x01 /* Level 0 is fastest */ -#define EC_FAN_SPEED_LEVEL_1 0x02 /* Level 1 is fast */ -#define EC_FAN_SPEED_LEVEL_2 0x04 /* Level 2 is slow */ -#define EC_FAN_SPEED_LEVEL_3 0x08 /* Level 3 is slowest */ -#define EC_FAN_SPEED_LEVEL_4 0x10 /* Level 4 is off */ -#define EC_FAN_SPEED_FLAG_OS 0x80 /* OS control of fan speed */ +#define EC_FAN_SPEED 0xca +#define EC_FAN_SPEED_LEVEL_0 0x01 /* Level 0 is fastest */ +#define EC_FAN_SPEED_LEVEL_1 0x02 /* Level 1 is fast */ +#define EC_FAN_SPEED_LEVEL_2 0x04 /* Level 2 is slow */ +#define EC_FAN_SPEED_LEVEL_3 0x08 /* Level 3 is slowest */ +#define EC_FAN_SPEED_LEVEL_4 0x10 /* Level 4 is off */ +#define EC_FAN_SPEED_FLAG_OS 0x80 /* OS control of fan speed */
/* EC SMI */ -#define EC_LID_CLOSE 0x9c /* Lid close event */ -#define EC_LID_OPEN 0x9d /* Lid open event */ +#define EC_LID_CLOSE 0x9c /* Lid close event */ +#define EC_LID_OPEN 0x9d /* Lid open event */
extern void lumpy_ec_init(void);
diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h index af5f3e2..fcde7da 100644 --- a/src/mainboard/samsung/lumpy/gpio.h +++ b/src/mainboard/samsung/lumpy/gpio.h @@ -315,19 +315,19 @@ const struct pch_gpio_set2 pch_gpio_set2_reset = {
const struct pch_gpio_map lumpy_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, .invert = &pch_gpio_set1_invert, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, .reset = &pch_gpio_set2_reset, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index c1749f7..becb004 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -64,7 +64,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x00; @@ -126,7 +126,7 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } @@ -182,19 +182,19 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
static int lumpy_onboard_smbios_data(device_t dev, int *handle, - unsigned long *current) + unsigned long *current) { int len = 0;
len += lumpy_smbios_type41_irq(handle, current, - LUMPY_LIGHTSENSOR_NAME, - LUMPY_LIGHTSENSOR_IRQ, - LUMPY_LIGHTSENSOR_I2C_ADDR); + LUMPY_LIGHTSENSOR_NAME, + LUMPY_LIGHTSENSOR_IRQ, + LUMPY_LIGHTSENSOR_I2C_ADDR);
len += lumpy_smbios_type41_irq(handle, current, - LUMPY_TRACKPAD_NAME, - LUMPY_TRACKPAD_IRQ, - LUMPY_TRACKPAD_I2C_ADDR); + LUMPY_TRACKPAD_NAME, + LUMPY_TRACKPAD_IRQ, + LUMPY_TRACKPAD_I2C_ADDR);
return len; } diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h index 6bdf057..9f750e6 100644 --- a/src/mainboard/samsung/lumpy/onboard.h +++ b/src/mainboard/samsung/lumpy/onboard.h @@ -22,12 +22,12 @@
#include <arch/smp/mpspec.h>
-#define LUMPY_LIGHTSENSOR_NAME "lightsensor" +#define LUMPY_LIGHTSENSOR_NAME "lightsensor" #define LUMPY_LIGHTSENSOR_I2C_ADDR 0x44 -#define LUMPY_LIGHTSENSOR_IRQ 20 +#define LUMPY_LIGHTSENSOR_IRQ 20
-#define LUMPY_TRACKPAD_NAME "trackpad" -#define LUMPY_TRACKPAD_I2C_ADDR 0x67 -#define LUMPY_TRACKPAD_IRQ 21 +#define LUMPY_TRACKPAD_NAME "trackpad" +#define LUMPY_TRACKPAD_I2C_ADDR 0x67 +#define LUMPY_TRACKPAD_IRQ 21
#endif diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..14da075 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -74,18 +74,18 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQB - * D31IP_SIP SATA INTA -> PIRQA (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQB + * D31IP_SIP SATA INTA -> PIRQA (MSI) * D31IP_SMIP SMBUS INTC -> PIRQH * D31IP_TTIP THRT INTB -> PIRQG - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) * - * LIGHTSENSOR -> PIRQE (Edge Triggered) - * TRACKPAD -> PIRQF (Edge Triggered) + * LIGHTSENSOR -> PIRQE (Edge Triggered) + * TRACKPAD -> PIRQF (Edge Triggered) */
/* Device interrupt pin register (board specific) */ @@ -164,18 +164,18 @@ void main(unsigned long bist) dimm_channel1_disabled: 2, max_ddr3_freq: 1333, usb_port_config: { - { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ - { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ + { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 0, 0, 0x0000 }, /* P4: Empty */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ + { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ { 0, 4, 0x0000 }, /* P9: Empty */ { 0, 4, 0x0000 }, /* P10: Empty */ - { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ + { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ { 0, 4, 0x0000 }, /* P12: Empty */ { 0, 4, 0x0000 }, /* P13: Empty */ }, diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl index 75869ca..e7853cc 100644 --- a/src/mainboard/samsung/stumpy/acpi/superio.asl +++ b/src/mainboard/samsung/stumpy/acpi/superio.asl @@ -19,17 +19,17 @@
/* Values should match those defined in devicetree.cb */
-#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
-#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 #define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
#include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b68edcd..c1691b9 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -246,7 +246,7 @@ unsigned long write_acpi_tables(unsigned long start) for (i=0; i < dsdt->length; i++) { if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " - "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes acpi_save_gnvs(current); break; diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..1be60bb 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -21,116 +21,116 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# Stumpy USB reset workaround disable -400 8 r 0 stumpy_usb_reset_disable +400 8 r 0 stumpy_usb_reset_disable
# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused +416 128 r 0 vbnv +#544 440 r 0 unused
# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums
diff --git a/src/mainboard/samsung/stumpy/gpio.h b/src/mainboard/samsung/stumpy/gpio.h index c72548e..377a05c 100644 --- a/src/mainboard/samsung/stumpy/gpio.h +++ b/src/mainboard/samsung/stumpy/gpio.h @@ -291,17 +291,17 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
const struct pch_gpio_map stumpy_gpio_map = { .set1 = { - .mode = &pch_gpio_set1_mode, + .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, }, .set2 = { - .mode = &pch_gpio_set2_mode, + .mode = &pch_gpio_set2_mode, .direction = &pch_gpio_set2_direction, .level = &pch_gpio_set2_level, }, .set3 = { - .mode = &pch_gpio_set3_mode, + .mode = &pch_gpio_set3_mode, .direction = &pch_gpio_set3_direction, .level = &pch_gpio_set3_level, }, diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 30612db..1ecb062 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -57,7 +57,7 @@ static int int15_handler(void) * bit 2 = Graphics Stretching * bit 1 = Text Stretching * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default + * 0 = video bios default */ X86_AX = 0x005f; X86_CL = 0x01; @@ -119,7 +119,7 @@ static int int15_handler(void) } break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index ee715e7..78d9823 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -82,15 +82,15 @@ static void rcba_config(void) u32 reg32;
/* - * GFX INTA -> PIRQA (MSI) + * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQE + * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) + * D27IP_ZIP HDA INTA -> PIRQG (MSI) */
/* Device interrupt pin register (board specific) */ @@ -201,15 +201,15 @@ void main(unsigned long bist) max_ddr3_freq: 1333, usb_port_config: { { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ - { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ - { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ + { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ + { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ { 0, 0, 0x0000 }, /* P5: Empty */ { 0, 0, 0x0000 }, /* P6: Empty */ { 0, 0, 0x0000 }, /* P7: Empty */ - { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ - { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ + { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ { 0, 4, 0x0000 }, /* P11: Empty */ { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ @@ -235,7 +235,7 @@ void main(unsigned long bist) it8772f_kill_watchdog(); it8772f_ac_resume_southbridge(); it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), - CONFIG_TTYS0_BASE); + CONFIG_TTYS0_BASE); console_init();
#if CONFIG_CHROMEOS diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl index 7b8c3bb..4646e19 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl @@ -201,8 +201,8 @@ Device(PRIM) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -237,8 +237,8 @@ Device(PRIM) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl b/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl index d9f1f83..0c155d5 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl +++ b/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl @@ -20,26 +20,26 @@
/* Status and notification definitions */
-#define STA_MISSING 0x00 -#define STA_PRESENT 0x01 -#define STA_ENABLED 0x03 -#define STA_DISABLED 0x09 -#define STA_INVISIBLE 0x0B +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B #define STA_UNAVAILABLE 0x0D -#define STA_VISIBLE 0x0F +#define STA_VISIBLE 0x0F
/* SMBus status codes */ -#define SMB_OK 0x00 -#define SMB_UnknownFail 0x07 -#define SMB_DevAddrNAK 0x10 -#define SMB_DeviceError 0x11 -#define SMB_DevCmdDenied 0x12 -#define SMB_UnknownErr 0x13 -#define SMB_DevAccDenied 0x17 -#define SMB_Timeout 0x18 -#define SMB_HstUnsuppProtocol 0x19 -#define SMB_Busy 0x1A -#define SMB_PktChkError 0x1F +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F
/* Device Object Notification Values */ #define NOTIFY_BUS_CHECK 0x00 @@ -57,14 +57,14 @@ /* Battery Device Notification Values */ #define NOTIFY_BAT_STATUSCHG 0x80 #define NOTIFY_BAT_INFOCHG 0x81 -#define NOTIFY_BAT_MAINTDATA 0x82 +#define NOTIFY_BAT_MAINTDATA 0x82
/* Power Source Object Notification Values */ #define NOTIFY_PWR_STATUSCHG 0x80
/* Thermal Zone Object Notification Values */ -#define NOTIFY_TZ_STATUSCHG 0x80 -#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 #define NOTIFY_TZ_DEVLISTCHG 0x82 #define NOTIFY_TZ_RELTBLCHG 0x83
@@ -80,7 +80,7 @@ /* Processor Device Notification Values */ #define NOTIFY_CPU_PPCCHG 0x80 #define NOTIFY_CPU_CSTATECHG 0x81 -#define NOTIFY_CPU_THROTLCHG 0x82 +#define NOTIFY_CPU_THROTLCHG 0x82
/* User Presence Device Notification Values */ #define NOTIFY_USR_PRESNCECHG 0x80 @@ -88,6 +88,6 @@ /* Battery Device Notification Values */ #define NOTIFY_ALS_ILLUMCHG 0x80 #define NOTIFY_ALS_COLORTMPCHG 0x81 -#define NOTIFY_ALS_RESPCHG 0x82 +#define NOTIFY_ALS_RESPCHG 0x82
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index 28bf5e9..9943a05 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -112,7 +112,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0); #if !CONFIG_LINT01_CONVERSION current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/siemens/sitemp_g1p1/cmos.layout b/src/mainboard/siemens/sitemp_g1p1/cmos.layout index 52a8b4f..34f97cb 100644 --- a/src/mainboard/siemens/sitemp_g1p1/cmos.layout +++ b/src/mainboard/siemens/sitemp_g1p1/cmos.layout @@ -24,95 +24,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ======================================================= -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ======================================================= -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ======================================================== -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory # ======================================================== -#384 1 e 4 unused -385 1 r 4 last_boot -#386 1 r 1 unused -387 1 e 16 cmos_defaults_loaded -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -#395 1 r 1 unused -#396 1 r 1 unused -#397 2 r 8 unused -399 1 e 2 multi_core -#400 8 r 18 reserved -408 4 e 6 debug_level -412 1 e 1 power_on_after_fail -#413 1 r 1 unused -414 1 e 17 sata_mode -415 1 e 1 nmi -416 1 e 1 cpu_fan_control -417 1 e 1 chassis_fan_control -418 1 e 13 cpu_fan_polarity -419 1 e 13 chassis_fan_polarity -420 4 e 14 cpu_t_min -424 4 e 14 cpu_t_max -428 4 e 15 cpu_dutycycle_min -432 4 e 15 cpu_dutycycle_max -436 4 e 14 chassis_t_min -440 4 e 14 chassis_t_max -444 4 e 15 chassis_dutycycle_min -448 4 e 15 chassis_dutycycle_max -#452 4 r 9 unused -456 4 e 10 boot_delay -460 4 e 11 lcd_panel_id +#384 1 e 4 unused +385 1 r 4 last_boot +#386 1 r 1 unused +387 1 e 16 cmos_defaults_loaded +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +#395 1 r 1 unused +#396 1 r 1 unused +#397 2 r 8 unused +399 1 e 2 multi_core +#400 8 r 18 reserved +408 4 e 6 debug_level +412 1 e 1 power_on_after_fail +#413 1 r 1 unused +414 1 e 17 sata_mode +415 1 e 1 nmi +416 1 e 1 cpu_fan_control +417 1 e 1 chassis_fan_control +418 1 e 13 cpu_fan_polarity +419 1 e 13 chassis_fan_polarity +420 4 e 14 cpu_t_min +424 4 e 14 cpu_t_max +428 4 e 15 cpu_dutycycle_min +432 4 e 15 cpu_dutycycle_max +436 4 e 14 chassis_t_min +440 4 e 14 chassis_t_max +444 4 e 15 chassis_dutycycle_min +448 4 e 15 chassis_dutycycle_max +#452 4 r 9 unused +456 4 e 10 boot_delay +460 4 e 11 lcd_panel_id #=========================================================== -464 512 s 0 boot_devices -976 8 h 0 boot_default -984 16 h 0 check_sum +464 512 s 0 boot_devices +976 8 h 0 boot_default +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew #7 0 Network #7 1 HDD #7 2 Floppy @@ -120,21 +120,21 @@ enumerations #7 9 Fallback_HDD #7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 # boot delay -10 0 off -10 1 1s -10 2 2s -10 3 3s -10 4 4s -10 5 5s -10 6 6s -10 7 7s -10 8 8s -10 9 9s +10 0 off +10 1 1s +10 2 2s +10 3 3s +10 4 4s +10 5 5s +10 6 6s +10 7 7s +10 8 8s +10 9 9s 10 10 10s # LCD Panel ID 11 0 no_panel @@ -158,35 +158,35 @@ enumerations #12 9 SCART-RGB #12 15 no_tv # CPU/Chassis FAN Control: polarity -13 0 Active_high -13 1 Active_low +13 0 Active_high +13 1 Active_low # Temperature �C -14 0 30 -14 1 35 -14 2 40 -14 3 45 -14 4 50 -14 5 55 -14 6 60 -14 7 65 -14 8 70 -14 9 75 +14 0 30 +14 1 35 +14 2 40 +14 3 45 +14 4 50 +14 5 55 +14 6 60 +14 7 65 +14 8 70 +14 9 75 14 10 80 14 11 85 14 12 90 14 13 95 14 14 100 # Dutycycle % -15 0 25% -15 1 30% -15 2 35% -15 3 40% -15 4 45% -15 5 50% -15 6 55% -15 7 60% -15 8 65% -15 9 70% +15 0 25% +15 1 30% +15 2 35% +15 3 40% +15 4 45% +15 5 50% +15 6 55% +15 7 60% +15 8 65% +15 9 70% 15 10 75% 15 11 80% 15 12 85% @@ -194,11 +194,11 @@ enumerations 15 14 95% 15 15 100% # cmos_defaults_loaded -16 0 No -16 1 Yes +16 0 No +16 1 Yes # sata_mode -17 0 AHCI -17 1 IDE +17 0 AHCI +17 1 IDE # reserved 18 32 2000 # ============================== diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl index 7890df7..dc56097 100644 --- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl +++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl @@ -74,13 +74,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -99,7 +99,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -224,8 +224,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -251,7 +251,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Offset (0x00), OSYS, 16, LINX, 16, - PCBA, 32, + PCBA, 32, MPEN, 8 }
@@ -398,48 +398,48 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Return(0x0B) /* Status is visible */ }
- Device (MEMR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (MEM1, ResourceTemplate () - { - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x00000000, // Address Length - _Y1A) - Memory32Fixed (ReadWrite, - 0x00000000, // Address Base - 0x00000000, // Address Length - _Y1B) - }) - Method (_CRS, 0, NotSerialized) - { - CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1A._BAS, MB01) - CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1A._LEN, ML01) - CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1B._BAS, MB02) - CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1B._LEN, ML02) - If (PCIF) - { - Store (IO_APIC_ADDR, MB01) - Store (LOCAL_APIC_ADDR, MB02) - Store (0x1000, ML01) - Store (0x1000, ML02) - } - - Return (MEM1) - } - } + Device (MEMR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (MEM1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1A) + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1B) + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1A._BAS, MB01) + CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1A._LEN, ML01) + CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1B._BAS, MB02) + CreateDWordField (MEM1, _SB.PCI0.MEMR._Y1B._LEN, ML02) + If (PCIF) + { + Store (IO_APIC_ADDR, MB01) + Store (LOCAL_APIC_ADDR, MB02) + Store (0x1000, ML01) + Store (0x1000, ML02) + } + + Return (MEM1) + } + }
Method(_PRT,0) { If(PCIF){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
- OperationRegion (BAR1, PCI_Config, 0x14, 0x04) - Field (BAR1, ByteAcc, NoLock, Preserve) - { - Z009, 32 - } + OperationRegion (BAR1, PCI_Config, 0x14, 0x04) + Field (BAR1, ByteAcc, NoLock, Preserve) + { + Z009, 32 + }
/* Describe the Northbridge devices */ Device(AMRT) { @@ -453,8 +453,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Method(_PRT,0) { Return (APR1) }
Device (VGA) - { - Name (_ADR, 0x00050000) + { + Name (_ADR, 0x00050000) Method (_DOS, 1) { /* Windows 2000 and Windows XP call _DOS to enable/disable @@ -463,11 +463,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) */ Store (And(Arg0, 7), DSEN) } - Method (_STA, 0, NotSerialized) - { - Return (0x0F) - } - } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } } /* end AGPB */
/* The external GFX bridge */ @@ -475,8 +475,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PCIF){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PCIF){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -486,8 +486,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PCIF){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PCIF){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -495,8 +495,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PCIF){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PCIF){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -504,8 +504,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PCIF){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PCIF){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -514,8 +514,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PCIF){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PCIF){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -525,7 +525,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Name(_PRW, Package() {4, 5}) // Phoenix doeas it so Method(_PRT, 0) { If(PCIF){ Return(AP2P) } /* APIC Mode */ - Return (PCIB) /* PIC Mode */ + Return (PCIB) /* PIC Mode */ } }
@@ -612,8 +612,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
Device(LPC0) { - Name (_ADR, 0x00140003) - Mutex (PSMX, 0x00) + Name (_ADR, 0x00140003) + Mutex (PSMX, 0x00)
/* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) @@ -961,7 +961,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Device(TMR) { /* Timer */ Name(_HID,EISAID("PNP0100")) /* System Timer */ Name(_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive, ) {0} + IRQ (Edge, ActiveHigh, Exclusive, ) {0} IO(Decode16, 0x0040, 0x0040, 1, 4) /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) @@ -1019,62 +1019,62 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Store(HPBA, HPBA) Return(CRS) } - } - - Device (KBC0) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0060, // Range Minimum - 0x0060, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IO (Decode16, - 0x0064, // Range Minimum - 0x0064, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IRQ (Edge, ActiveHigh, Exclusive, ) {1} - }) + } + + Device (KBC0) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) {1} + }) }
- Device (MSE0) - { - Name (_HID, EisaId ("PNP0F13")) - Name (_CRS, ResourceTemplate () - { - IRQ (Edge, ActiveHigh, Exclusive, ) {12} - }) + Device (MSE0) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQ (Edge, ActiveHigh, Exclusive, ) {12} + }) } } /* end LPC0 */
Device(ACAD) { Name(_ADR, 0x00140005) Name (_PRW, Package (0x02) - { - 0x0C, - 0x04 - }) + { + 0x0C, + 0x04 + }) } /* end Ac97audio */
Device(ACMD) { Name(_ADR, 0x00140006) Name (_PRW, Package (0x02) - { - 0x0C, - 0x04 - }) + { + 0x0C, + 0x04 + }) } /* end Ac97modem */
/* ITE IT8712F Support */ OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1089,7 +1089,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) Offset (0xF0), APC0, 8, /* APC/PME Event Enable Register */ APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ + APC2, 8, /* APC/PME Control Register 1 */ APC3, 8, /* Environment Controller Special Configuration Register */ APC4, 8 /* APC/PME Control Register 2 */ } @@ -1113,7 +1113,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1226,9 +1226,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) SEVT, 8, /* SMBUS slave event */ SDAT, 8, /* SMBUS slave data */ SMK1, 8, - SLMC, 8, - RADD, 8, - SADD, 8 + SLMC, 8, + RADD, 8, + SADD, 8 }
Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.c b/src/mainboard/siemens/sitemp_g1p1/int15_func.c index 31dd6e2..817dce3 100644 --- a/src/mainboard/siemens/sitemp_g1p1/int15_func.c +++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.c @@ -41,15 +41,15 @@ int sbios_INT15_handler(void) printk(BIOS_DEBUG, "System BIOS INT 15h\n");
switch (X86_EAX & 0xffff) { -#define BOOT_DISPLAY_DEFAULT 0 -#define BOOT_DISPLAY_CRT (1 << 0) -#define BOOT_DISPLAY_TV (1 << 1) -#define BOOT_DISPLAY_EFP (1 << 2) -#define BOOT_DISPLAY_LCD (1 << 3) -#define BOOT_DISPLAY_CRT2 (1 << 4) -#define BOOT_DISPLAY_TV2 (1 << 5) -#define BOOT_DISPLAY_EFP2 (1 << 6) -#define BOOT_DISPLAY_LCD2 (1 << 7) +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) case 0x5f35: X86_EAX = 0x5f; X86_ECX = BOOT_DISPLAY_DEFAULT; @@ -62,20 +62,20 @@ int sbios_INT15_handler(void) res = 0; break; case 0x4e08: - switch (X86_EBX & 0xff) { - case 0x00: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func00_LCD_panel_id; + switch (X86_EBX & 0xff) { + case 0x00: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func00_LCD_panel_id; printk(BIOS_DEBUG, "DISPLAY = %x\n", X86_EBX & 0xff); - res = 0; + res = 0; break; case 0x02: break; - case 0x05: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func05_TV_standard; + case 0x05: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | __int15_func.regs.func05_TV_standard; printk(BIOS_DEBUG, "TV = %x\n", X86_EBX & 0xff); - res = 0; + res = 0; break; case 0x80: X86_EAX &= ~(0xff); @@ -92,10 +92,10 @@ int sbios_INT15_handler(void) break; default: break; - } - break; + } + break; default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; }
diff --git a/src/mainboard/siemens/sitemp_g1p1/int15_func.h b/src/mainboard/siemens/sitemp_g1p1/int15_func.h index 26f679e..dfbdbbb 100644 --- a/src/mainboard/siemens/sitemp_g1p1/int15_func.h +++ b/src/mainboard/siemens/sitemp_g1p1/int15_func.h @@ -22,14 +22,14 @@ */
typedef struct { - u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID + u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID u8 func02_set_expansion; - u8 func05_TV_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard + u8 func05_TV_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard u16 func80_sysinfo_table; }INT15_regs;
typedef struct { - INT15_regs regs; + INT15_regs regs; }INT15_function_extensions;
extern void install_INT15_function_extensions(INT15_function_extensions *); diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 4fc6855..421f49d 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -66,67 +66,67 @@ #define PLX_VIDDID 0x861610b5
/* 7475 Common Registers */ -#define REG_DEVREV2 0x12 /* ADT7490 only */ -#define REG_VTT 0x1E /* ADT7490 only */ -#define REG_EXTEND3 0x1F /* ADT7490 only */ -#define REG_VOLTAGE_BASE 0x20 -#define REG_TEMP_BASE 0x25 -#define REG_TACH_BASE 0x28 -#define REG_PWM_BASE 0x30 -#define REG_PWM_MAX_BASE 0x38 -#define REG_DEVID 0x3D -#define REG_VENDID 0x3E -#define REG_DEVID2 0x3F -#define REG_STATUS1 0x41 -#define REG_STATUS2 0x42 -#define REG_VID 0x43 /* ADT7476 only */ -#define REG_VOLTAGE_MIN_BASE 0x44 -#define REG_VOLTAGE_MAX_BASE 0x45 -#define REG_TEMP_MIN_BASE 0x4E -#define REG_TEMP_MAX_BASE 0x4F -#define REG_TACH_MIN_BASE 0x54 -#define REG_PWM_CONFIG_BASE 0x5C -#define REG_TEMP_TRANGE_BASE 0x5F -#define REG_PWM_MIN_BASE 0x64 -#define REG_TEMP_TMIN_BASE 0x67 -#define REG_TEMP_THERM_BASE 0x6A -#define REG_REMOTE1_HYSTERSIS 0x6D -#define REG_REMOTE2_HYSTERSIS 0x6E -#define REG_TEMP_OFFSET_BASE 0x70 -#define REG_CONFIG2 0x73 -#define REG_EXTEND1 0x76 -#define REG_EXTEND2 0x77 +#define REG_DEVREV2 0x12 /* ADT7490 only */ +#define REG_VTT 0x1E /* ADT7490 only */ +#define REG_EXTEND3 0x1F /* ADT7490 only */ +#define REG_VOLTAGE_BASE 0x20 +#define REG_TEMP_BASE 0x25 +#define REG_TACH_BASE 0x28 +#define REG_PWM_BASE 0x30 +#define REG_PWM_MAX_BASE 0x38 +#define REG_DEVID 0x3D +#define REG_VENDID 0x3E +#define REG_DEVID2 0x3F +#define REG_STATUS1 0x41 +#define REG_STATUS2 0x42 +#define REG_VID 0x43 /* ADT7476 only */ +#define REG_VOLTAGE_MIN_BASE 0x44 +#define REG_VOLTAGE_MAX_BASE 0x45 +#define REG_TEMP_MIN_BASE 0x4E +#define REG_TEMP_MAX_BASE 0x4F +#define REG_TACH_MIN_BASE 0x54 +#define REG_PWM_CONFIG_BASE 0x5C +#define REG_TEMP_TRANGE_BASE 0x5F +#define REG_PWM_MIN_BASE 0x64 +#define REG_TEMP_TMIN_BASE 0x67 +#define REG_TEMP_THERM_BASE 0x6A +#define REG_REMOTE1_HYSTERSIS 0x6D +#define REG_REMOTE2_HYSTERSIS 0x6E +#define REG_TEMP_OFFSET_BASE 0x70 +#define REG_CONFIG2 0x73 +#define REG_EXTEND1 0x76 +#define REG_EXTEND2 0x77 #define REG_CONFIG1 0x40 // ADT7475 -#define REG_CONFIG3 0x78 -#define REG_CONFIG5 0x7C +#define REG_CONFIG3 0x78 +#define REG_CONFIG5 0x7C #define REG_CONFIG6 0x10 // ADT7475 #define REG_CONFIG7 0x11 // ADT7475 -#define REG_CONFIG4 0x7D -#define REG_STATUS4 0x81 /* ADT7490 only */ -#define REG_VTT_MIN 0x84 /* ADT7490 only */ -#define REG_VTT_MAX 0x86 /* ADT7490 only */ - -#define VID_VIDSEL 0x80 /* ADT7476 only */ - -#define CONFIG2_ATTN 0x20 -#define CONFIG3_SMBALERT 0x01 -#define CONFIG3_THERM 0x02 -#define CONFIG4_PINFUNC 0x03 -#define CONFIG4_MAXDUTY 0x08 -#define CONFIG4_ATTN_IN10 0x30 -#define CONFIG4_ATTN_IN43 0xC0 -#define CONFIG5_TWOSCOMP 0x01 -#define CONFIG5_TEMPOFFSET 0x02 -#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */ +#define REG_CONFIG4 0x7D +#define REG_STATUS4 0x81 /* ADT7490 only */ +#define REG_VTT_MIN 0x84 /* ADT7490 only */ +#define REG_VTT_MAX 0x86 /* ADT7490 only */ + +#define VID_VIDSEL 0x80 /* ADT7476 only */ + +#define CONFIG2_ATTN 0x20 +#define CONFIG3_SMBALERT 0x01 +#define CONFIG3_THERM 0x02 +#define CONFIG4_PINFUNC 0x03 +#define CONFIG4_MAXDUTY 0x08 +#define CONFIG4_ATTN_IN10 0x30 +#define CONFIG4_ATTN_IN43 0xC0 +#define CONFIG5_TWOSCOMP 0x01 +#define CONFIG5_TEMPOFFSET 0x02 +#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */ #define REMOTE1 0 #define LOCAL 1 #define REMOTE2 2
/* ADT7475 Settings */ -#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */ -#define ADT7475_TEMP_COUNT 3 -#define ADT7475_TACH_COUNT 4 -#define ADT7475_PWM_COUNT 3 +#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */ +#define ADT7475_TEMP_COUNT 3 +#define ADT7475_TACH_COUNT 4 +#define ADT7475_PWM_COUNT 3
/* Macros to easily index the registers */ #define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2)) @@ -152,11 +152,11 @@ #define SMBUS_IO_BASE 0x1000 #define ADT7475_ADDRESS 0x2E
-#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); @@ -343,27 +343,27 @@ static void cable_detect(void)
static const char * adt7475_detect( void ) {
- int vendid, devid, devid2; - const char *name = NULL; + int vendid, devid, devid2; + const char *name = NULL;
- vendid = adt7475_read_byte(REG_VENDID); - devid2 = adt7475_read_byte(REG_DEVID2); - if (vendid != 0x41 || /* Analog Devices */ - (devid2 & 0xf8) != 0x68) { - return name; + vendid = adt7475_read_byte(REG_VENDID); + devid2 = adt7475_read_byte(REG_DEVID2); + if (vendid != 0x41 || /* Analog Devices */ + (devid2 & 0xf8) != 0x68) { + return name; }
- devid = adt7475_read_byte(REG_DEVID); - if (devid == 0x73) - name = "adt7473"; - else if (devid == 0x75 && adt7475_address == 0x2e) - name = "adt7475"; - else if (devid == 0x76) - name = "adt7476"; - else if ((devid2 & 0xfc) == 0x6c) - name = "adt7490"; - - return name; + devid = adt7475_read_byte(REG_DEVID); + if (devid == 0x73) + name = "adt7473"; + else if (devid == 0x75 && adt7475_address == 0x2e) + name = "adt7475"; + else if (devid == 0x76) + name = "adt7476"; + else if ((devid2 & 0xfc) == 0x6c) + name = "adt7490"; + + return name; }
// thermal control defaults @@ -537,15 +537,15 @@ static void set_thermal_config(void)
/* remote 1 low temp limit */ adt7475_write_byte(TEMP_MIN_REG(0), 0x00); - /* remote 1 High temp limit (90C) */ + /* remote 1 High temp limit (90C) */ adt7475_write_byte(TEMP_MAX_REG(0), 0x9a);
/* local Low Temp Limit */ adt7475_write_byte(TEMP_MIN_REG(1), 0x00); - /* local High Limit (90C) */ + /* local High Limit (90C) */ adt7475_write_byte(TEMP_MAX_REG(1), 0x9a);
- /* remote 1 therm temp limit (95C) */ + /* remote 1 therm temp limit (95C) */ adt7475_write_byte(TEMP_THERM_REG(0), 0x9f); /* local therm temp limit (95C) */ adt7475_write_byte(TEMP_THERM_REG(1), 0x9f); @@ -556,26 +556,26 @@ static void set_thermal_config(void) adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf);
if( cpu_fan_control.enable ) { - /* PWM 1 minimum duty cycle (37%) */ + /* PWM 1 minimum duty cycle (37%) */ adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min); - /* PWM 1 Maximum duty cycle (100%) */ + /* PWM 1 Maximum duty cycle (100%) */ adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max); - /* Remote 1 temperature Tmin (32C) */ + /* Remote 1 temperature Tmin (32C) */ adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min); - /* remote 1 Trange (53C ramp range) */ + /* remote 1 Trange (53C ramp range) */ adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range); } else { adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max); }
if( case_fan_control.enable ) { - /* PWM 2 minimum duty cycle (37%) */ + /* PWM 2 minimum duty cycle (37%) */ adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min); - /* PWM 2 Maximum Duty Cycle (100%) */ + /* PWM 2 Maximum Duty Cycle (100%) */ adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max); - /* local temperature Tmin (32C) */ + /* local temperature Tmin (32C) */ adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min); - /* local Trange (53C ramp range) */ + /* local Trange (53C ramp range) */ adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq } else { diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index de5151d..30cb9d5 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc);
@@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600);
mptable_write_buses(mc, NULL, &isa_bus); - /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev;
@@ -115,7 +115,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12);
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus);
/* Compute the checksums */ diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb index c7c9ec3..27d097c 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb +++ b/src/mainboard/soyo/sy-6ba-plus-iii/devicetree.cb @@ -29,33 +29,33 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/ite/it8671f # Super I/O - device pnp 370.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 370.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 370.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 370.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 370.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 370.6 on # PS/2 mouse - irq 0x70 = 12 - end - end + chip superio/ite/it8671f # Super I/O + device pnp 370.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 370.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 370.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 370.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 370.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 370.6 on # PS/2 mouse + irq 0x70 = 12 + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c index 55a46b3..3990069 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/irq_tables.c @@ -36,7 +36,7 @@ static const struct irq_routing_table intel_irq_routing_table = { * for this structure (including checksum). */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0f << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0}, {0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0}, {0x00, (0x11 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/sunw/ultra40/cmos.layout b/src/mainboard/sunw/ultra40/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/sunw/ultra40/cmos.layout +++ b/src/mainboard/sunw/ultra40/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb index 9f9bb67..135a48c 100644 --- a/src/mainboard/sunw/ultra40/devicetree.cb +++ b/src/mainboard/sunw/ultra40/devicetree.cb @@ -9,108 +9,108 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47m10x # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 off # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master CK804 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave CK804 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47m10x # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master CK804 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave CK804 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # Link 2 device pci 18.1 on end @@ -120,27 +120,27 @@ chip northbridge/amd/amdk8/root_complex # Root complex chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 19.0 on end # Link 0 device pci 19.0 on # Link 1 == LDT 1 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 19.0 on end device pci 19.1 on end diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index f57719a..a6a0cd9 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -37,11 +37,11 @@ unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO t 0x0000ff0, 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hc_possible_num; @@ -50,11 +50,11 @@ unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every 0x20202020, 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -84,7 +84,7 @@ void get_bus_conf(void)
sbdnb = (hcdn[2] & 0xff); // first byte of second chain
-// bus_ck804_0 = node_link_to_bus(0, sblk); +// bus_ck804_0 = node_link_to_bus(0, sblk); bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
/* CK804 */ @@ -100,8 +100,8 @@ void get_bus_conf(void) #endif } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09);
bus_ck804_1 = 2; #if 0 @@ -119,8 +119,8 @@ void get_bus_conf(void) bus_ck804_3++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0b); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2 + 1; } @@ -132,8 +132,8 @@ void get_bus_conf(void) bus_ck804_4++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0c); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3 + 1; } @@ -145,8 +145,8 @@ void get_bus_conf(void) bus_ck804_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0d); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4 + 1; } @@ -157,8 +157,8 @@ void get_bus_conf(void) bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0e); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); }
bus_8131_0 = (pci1234[1] >> 16) & 0xff; @@ -170,8 +170,8 @@ void get_bus_conf(void) bus_8131_2++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0);
bus_8131_1 = bus_8131_0 + 1; bus_8131_2 = bus_8131_0 + 2; @@ -182,8 +182,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0);
bus_8131_2 = bus_8131_1 + 1; } @@ -201,8 +201,8 @@ void get_bus_conf(void) bus_ck804b_2++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x09); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x09);
bus_ck804b_1 = bus_ck804b_0 + 1; bus_ck804b_2 = bus_ck804b_0 + 2; @@ -216,8 +216,8 @@ void get_bus_conf(void) bus_ck804b_3++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x0b); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0b);
bus_ck804b_2 = bus_ck804b_0 + 1; bus_ck804b_3 = bus_ck804b_0 + 2; @@ -231,8 +231,8 @@ void get_bus_conf(void) bus_ck804b_4++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x0c); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0c);
bus_ck804b_4 = bus_ck804b_3 + 1; } @@ -244,8 +244,8 @@ void get_bus_conf(void) bus_ck804b_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x0d); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0d);
bus_ck804b_5 = bus_ck804b_4 + 1; } @@ -256,8 +256,8 @@ void get_bus_conf(void) bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x0e); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0e); #if 1 bus_ck804b_5 = bus_ck804b_4 + 1; #endif diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c index 324c87d..d945990 100644 --- a/src/mainboard/sunw/ultra40/irq_tables.c +++ b/src/mainboard/sunw/ultra40/irq_tables.c @@ -15,18 +15,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; }
extern unsigned char bus_ck804_0; //1 @@ -62,17 +62,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -98,81 +98,81 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge - write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + pirq_info++; slot_num++;
if(pci1234[2] & 0xf) { //second pci beidge - write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); + pirq_info++; slot_num++; } #if 0 //smbus write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + pirq_info++; slot_num++;
//usb write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + pirq_info++; slot_num++;
//audio write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + pirq_info++; slot_num++; //sata write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + pirq_info++; slot_num++; //sata - write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; //nic - write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++;
//Slot1 PCIE x16 - write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); + pirq_info++; slot_num++;
//firewire - write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++;
//Slot2 pci - write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); + pirq_info++; slot_num++; //nic - write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++; //Slot3 PCIE x16 - write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); + pirq_info++; slot_num++;
//Slot4 PCIX - write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); + pirq_info++; slot_num++;
//Slot5 PCIX - write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); + pirq_info++; slot_num++;
//onboard scsi - write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0); + pirq_info++; slot_num++;
//Slot6 PCIX - write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); - pirq_info++; slot_num++; + write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); + pirq_info++; slot_num++; #endif
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..e7db4ab 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -34,27 +34,27 @@ extern unsigned sbdnb;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; + { + device_t dev; struct resource *res; uint32_t dword;
- dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); @@ -63,49 +63,49 @@ static void *smp_write_config_table(void *v) /* Initialize interrupt mapping*/
dword = 0x0120d218; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword);
- dword = 0x12008a00; - pci_write_config32(dev, 0x80, dword); + dword = 0x12008a00; + pci_write_config32(dev, 0x80, dword);
- dword = 0x00080d7d; - pci_write_config32(dev, 0x84, dword); + dword = 0x00080d7d; + pci_write_config32(dev, 0x84, dword);
- } + }
- dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { + } + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } - } + }
if(pci1234[2] & 0xf) { - dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base); }
dword = 0x0000d218; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword);
- dword = 0x00000000; - pci_write_config32(dev, 0x80, dword); + dword = 0x00000000; + pci_write_config32(dev, 0x80, dword);
- dword = 0x00000d00; - pci_write_config32(dev, 0x84, dword); + dword = 0x00000d00; + pci_write_config32(dev, 0x84, dword);
- } + } }
} @@ -113,73 +113,73 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
// Onboard ck804 USB 1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 Audio - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
// Onboard ck804 NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
//Slot 1 PCIE x16 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); + }
//Onboard Firewire - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
//Slot 2 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); + }
if(pci1234[2] & 0xf) { //Onboard ck804b NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
//Slot 3 PCIE x16 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); + } }
//Channel B of 8131
//Slot 4 PCI-X 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); + }
//Slot 5 PCIX 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 + }
//OnBoard LSI SCSI - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 - } + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 + }
//Channel A of 8131
//Slot 6 PCIX 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 + }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/sunw/ultra40/resourcemap.c b/src/mainboard/sunw/ultra40/resourcemap.c index eae21b4..2de15e9 100644 --- a/src/mainboard/sunw/ultra40/resourcemap.c +++ b/src/mainboard/sunw/ultra40/resourcemap.c @@ -17,21 +17,21 @@ static void setup_ultra40_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -52,25 +52,25 @@ static void setup_ultra40_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -91,27 +91,27 @@ static void setup_ultra40_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -132,21 +132,21 @@ static void setup_ultra40_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -163,23 +163,23 @@ static void setup_ultra40_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -193,23 +193,23 @@ static void setup_ultra40_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -223,35 +223,35 @@ static void setup_ultra40_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xe0), 0x0000, 0x7f000103, PCI_ADDR(0, 0x18, 1, 0xe4), 0x0000, 0xff800113, diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index bc37d25..75b4c3c 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -31,12 +31,12 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) { - unsigned value; + unsigned value;
- /*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L - value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); + /*Enable onboard scsi*/ + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); } #endif
@@ -56,12 +56,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//set GPIO to input mode #define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -70,25 +70,25 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - unsigned value; - uint32_t dword; - uint8_t byte; + unsigned value; + uint32_t dword; + uint8_t byte;
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
- byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<29)|(1<<0); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<29)|(1<<0); + pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
- lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); + lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
- value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); - value &= 0xbf; - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); + value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); + value &= 0xbf; + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -102,49 +102,49 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, };
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8];
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + }
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx);
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_ultra40_resource_map(); + setup_ultra40_resource_map();
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); + needs_reset |= ht_setup_chains_x(); + needs_reset |= ck804_early_setup_x(); if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index ef4d3bc..2a5f77f 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -14,7 +14,7 @@ config BOARD_SUPERMICRO_H8QME_FAM10 config BOARD_SUPERMICRO_H8SCM_FAM10 bool "H8SCM (Fam10)" config BOARD_SUPERMICRO_H8SCM - bool "H8SCM" + bool "H8SCM" config BOARD_SUPERMICRO_H8QGI bool "H8QGI" config BOARD_SUPERMICRO_X6DAI_G diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/supermicro/h8dme/cmos.layout +++ b/src/mainboard/supermicro/h8dme/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 9efbaf7..20c4cda 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -10,113 +10,113 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 - device i2c 48 off end - device i2c 49 off end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 + device i2c 48 off end + device i2c 49 off end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 0279f8f..a35c45e 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -42,23 +42,23 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdnb; @@ -110,8 +110,8 @@ void get_bus_conf(void) bus_mcp55[2]++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x06); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06);
bus_mcp55[1] = 2; bus_mcp55[2] = 3; @@ -125,8 +125,8 @@ void get_bus_conf(void) bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_mcp55[0], sbdn + 0x0a + i - 2); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_mcp55[0], sbdn + 0x0a + i - 2); } }
@@ -136,7 +136,7 @@ void get_bus_conf(void) if (dev) { bus_pcix[0] = bus_mcp55[2]; bus_pcix[i + 1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } } } diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index a25e504..03dbd37 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -37,18 +37,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; } extern unsigned char bus_isa; extern unsigned char bus_mcp55[8]; //1 @@ -64,18 +64,18 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v; unsigned sbdn;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -103,14 +103,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..4e691ba 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -34,15 +34,15 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; unsigned sbdn; int i, j, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); sbdn = sysconf.sbdn; @@ -50,28 +50,28 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; + { + device_t dev; struct resource *res; uint32_t dword;
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); }
dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword);
- dword = 0xd00012d2; - pci_write_config32(dev, 0x84, dword); + dword = 0xd00012d2; + pci_write_config32(dev, 0x84, dword);
- } + }
@@ -79,31 +79,31 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + } }
- for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); + }
if(bus_pcix[0]) { diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c index 4451521..93235f2 100644 --- a/src/mainboard/supermicro/h8dme/resourcemap.c +++ b/src/mainboard/supermicro/h8dme/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 9363c63..ea696ac 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -102,13 +102,13 @@ static inline void change_i2c_mux(unsigned device) smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); dump_smbus_registers(); - ret = smbus_send_byte(SMBUS_SWITCH1, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); + ret = smbus_send_byte(SMBUS_SWITCH1, device); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); - ret = smbus_send_byte_one(SMBUS_SWITCH2, device); - print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); + ret = smbus_send_byte_one(SMBUS_SWITCH2, device); + print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); } #endif @@ -138,7 +138,7 @@ static void sio_setup(void) uint8_t byte;
enable_smbus(); -// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ +// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); diff --git a/src/mainboard/supermicro/h8dmr/cmos.layout b/src/mainboard/supermicro/h8dmr/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/supermicro/h8dmr/cmos.layout +++ b/src/mainboard/supermicro/h8dmr/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index 51ad94f..4c6bec3 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -10,133 +10,133 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 0279f8f..a35c45e 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -42,23 +42,23 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdnb; @@ -110,8 +110,8 @@ void get_bus_conf(void) bus_mcp55[2]++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x06); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06);
bus_mcp55[1] = 2; bus_mcp55[2] = 3; @@ -125,8 +125,8 @@ void get_bus_conf(void) bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_mcp55[0], sbdn + 0x0a + i - 2); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_mcp55[0], sbdn + 0x0a + i - 2); } }
@@ -136,7 +136,7 @@ void get_bus_conf(void) if (dev) { bus_pcix[0] = bus_mcp55[2]; bus_pcix[i + 1] = - pci_read_config8(dev, PCI_SECONDARY_BUS); + pci_read_config8(dev, PCI_SECONDARY_BUS); } } } diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index a25e504..03dbd37 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -37,18 +37,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; } extern unsigned char bus_isa; extern unsigned char bus_mcp55[8]; //1 @@ -64,18 +64,18 @@ unsigned long write_pirq_routing_table(unsigned long addr) uint8_t *v; unsigned sbdn;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c + get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c sbdn = sysconf.sbdn;
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -103,14 +103,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..af693be 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -34,15 +34,15 @@ extern unsigned char bus_pcix[3]; // under bus_mcp55_2
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; unsigned sbdn; int i, j, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf(); sbdn = sysconf.sbdn; @@ -50,28 +50,28 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ - { - device_t dev; + { + device_t dev; struct resource *res; uint32_t dword;
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); - if (dev) { + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base); }
dword = 0x43c6c643; - pci_write_config32(dev, 0x7c, dword); + pci_write_config32(dev, 0x7c, dword);
- dword = 0x81001a00; - pci_write_config32(dev, 0x80, dword); + dword = 0x81001a00; + pci_write_config32(dev, 0x80, dword);
- dword = 0xd00012d2; - pci_write_config32(dev, 0x84, dword); + dword = 0xd00012d2; + pci_write_config32(dev, 0x84, dword);
- } + }
@@ -79,32 +79,32 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa); + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) { if(!bus_mcp55[j]) continue; - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); + } }
- for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); + }
if(bus_pcix[0]) { diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c index 4451521..93235f2 100644 --- a/src/mainboard/supermicro/h8dmr/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index daae389..e4b031d 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -75,24 +75,24 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + uint32_t dword; + uint8_t byte;
- enable_smbus(); + enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -106,92 +106,92 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) DIMM5, DIMM7, 0, 0, };
- struct sys_info *sysinfo = &sysinfo_car; - int needs_reset = 0; - unsigned bsp_apicid = 0; + struct sys_info *sysinfo = &sysinfo_car; + int needs_reset = 0; + unsigned bsp_apicid = 0;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - } + }
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_set_clksel_48(DUMMY_DEV); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- setup_mb_resource_map(); + setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); + print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif - setup_coherent_ht_domain(); // routing table and start other core0 + setup_coherent_ht_domain(); // routing table and start other core0
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, - * So here need to make sure last core0 is started, esp for two way system, - * (there may be apic id conflicts in that case) - */ - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { - msr_t msr; - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - msr_t msr; - msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); - } + { + msr_t msr; + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); + } + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); + } #endif
init_timer(); // Need to use TMICT to synconize FID/VID
- needs_reset |= optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - needs_reset |= mcp55_early_setup_x(); + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x();
- // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + }
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-// enable_smbus(); /* enable in sio_setup */ +// enable_smbus(); /* enable in sio_setup */
- /* all ap stopped? */ + /* all ap stopped? */
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index c8a8bc5..8be0b0e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -10,133 +10,133 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..60272b4 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 4692ea0..3b9005d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -210,23 +210,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -241,35 +241,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index e2f76cf..c82fa2e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -203,7 +203,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", - msr.hi, msr.lo); + msr.hi, msr.lo); #endif
init_timer(); // Need to use TMICT to synconize FID/VID @@ -254,8 +254,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 2fbe70a..f07d5c9 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -30,11 +30,11 @@ /* These defines are used to select the appropriate socket for the SPD read * because this is a multi-socket design. */ -#define PCI_REG_GPIO_56_to_53_CNTRL (0x52) -#define GPIO_OUT_BIT_GPIO53 (BIT0) -#define GPIO_OUT_BIT_GPIO54 (BIT1) -#define GPIO_OUT_ENABLE_BIT_GPIO53 (BIT4) -#define GPIO_OUT_ENABLE_BIT_GPIO54 (BIT5) +#define PCI_REG_GPIO_56_to_53_CNTRL (0x52) +#define GPIO_OUT_BIT_GPIO53 (BIT0) +#define GPIO_OUT_BIT_GPIO54 (BIT1) +#define GPIO_OUT_ENABLE_BIT_GPIO53 (BIT4) +#define GPIO_OUT_ENABLE_BIT_GPIO54 (BIT5)
#define GPIO_OUT_BIT_GPIO54_to_53_MASK \ (GPIO_OUT_BIT_GPIO54 | GPIO_OUT_BIT_GPIO53) @@ -44,8 +44,8 @@ static UINT8 select_socket(UINT8 socket_id) { device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus - UINT8 value = 0; - UINT8 gpio56_to_53 = 0; + UINT8 value = 0; + UINT8 gpio56_to_53 = 0;
/* Configure GPIO54,53 to select the desired socket * GPIO54,53 control the HC4052 S1,S0 @@ -184,11 +184,11 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -205,14 +205,14 @@ AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -335,12 +335,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -453,8 +453,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -487,7 +487,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); return Status; @@ -495,9 +495,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h index 53c23a9..b0da979 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h @@ -65,13 +65,13 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h index cdf1701..aa62192 100644 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -53,14 +53,14 @@ #define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED TRUE #define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 3199575..3047dc1 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -41,38 +41,38 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); @@ -173,9 +173,9 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
UINT32 agesawrapper_amdinitmmio(VOID) { - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader;
/* * Set the MMIO Configuration Base Address and Bus Range onto @@ -431,9 +431,9 @@ UINT32 agesawrapper_amdinitlate(VOID) AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -461,8 +461,8 @@ UINT32 agesawrapper_amdinitlate(VOID) AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index a553ea8..7fc25c5 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,25 +31,25 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 7584e4f..bf43a648 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -55,90 +55,90 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -////#define BLDOPT_REMOVE_SRAT TRUE -////#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +////#define BLDOPT_REMOVE_SRAT TRUE +////#define BLDOPT_REMOVE_SLIT TRUE +//#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE
/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +//#define BLDOPT_REMOVE_HT_ASSIST TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
/* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_POWER_DOWN FALSE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_POWER_DOWN FALSE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/** * Enable Message Based C1e CPU feature in multi-socket systems. * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value, * else the feature cannot be enabled. */ -#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased -#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 - -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#define BLDCFG_1GB_ALIGN FALSE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define BLDCFG_1GB_ALIGN FALSE +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' //
// Select the platform control flow mode for performance tuning. @@ -151,8 +151,8 @@ * * This feature may interact with other performance features. * TRUE -Enable the feature (default) if supported by all processors, - * based on revision and presence of L3 cache. - * The feature is not enabled if there are no coherent HT links. + * based on revision and presence of L3 cache. + * The feature is not enabled if there are no coherent HT links. * FALSE -Do not enable the feature regardless of the configuration. */ //TODO enable it, @@ -426,32 +426,32 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/* #if CONFIG_CPU_AMD_AGESA_FAMILY15 - #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif #if CONFIG_CPU_AMD_AGESA_FAMILY10 - #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */
-//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "MaranelloInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -476,64 +476,64 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. //
/* Specifies the write leveling seed for a channel of a socket. * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, - * ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) */ WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, @@ -542,8 +542,8 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { F15_WL_SEED),
/* HW_RXEN_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) */ HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -583,8 +583,8 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -610,7 +610,7 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/supermicro/h8qgi/cmos.layout +++ b/src/mainboard/supermicro/h8qgi/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index d99a6ba..27a206f 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -26,7 +26,7 @@ chip northbridge/amd/agesa/family15/root_complex device domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index c854067..4f47a4f 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) @@ -313,8 +313,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -454,7 +454,7 @@ DefinitionBlock ( if(CondRefOf(_OSI,Local1)) { Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } @@ -833,7 +833,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -988,17 +988,17 @@ DefinitionBlock ( Scope(_GPE) { /* Start Scope GPE */ /* General event 0 */ Method(_L00) { - //DBGO("\_GPE\_L00\n") + //DBGO("\_GPE\_L00\n") }
/* General event 1 */ Method(_L01) { - //DBGO("\_GPE\_L01\n") + //DBGO("\_GPE\_L01\n") }
/* General event 2 */ Method(_L02) { - //DBGO("\_GPE\_L02\n") + //DBGO("\_GPE\_L02\n") }
/* General event 3 */ @@ -1009,12 +1009,12 @@ DefinitionBlock (
/* General event 4 */ Method(_L04) { - //DBGO("\_GPE\_L04\n") + //DBGO("\_GPE\_L04\n") }
/* General event 5 */ Method(_L05) { - //DBGO("\_GPE\_L05\n") + //DBGO("\_GPE\_L05\n") }
/* _L06 General event 6 - Used for GPM6, moved to USB.asl */ @@ -1033,7 +1033,7 @@ DefinitionBlock (
/* Reserved */ Method(_L0A) { - //DBGO("\_GPE\_L0A\n") + //DBGO("\_GPE\_L0A\n") }
/* USB controller PME# */ @@ -1050,12 +1050,12 @@ DefinitionBlock (
/* AC97 controller PME# */ Method(_L0C) { - //DBGO("\_GPE\_L0C\n") + //DBGO("\_GPE\_L0C\n") }
/* OtherTherm PME# */ Method(_L0D) { - //DBGO("\_GPE\_L0D\n") + //DBGO("\_GPE\_L0D\n") }
/* _L0E GPM9 SCI event - Moved to USB.asl */ @@ -1078,7 +1078,7 @@ DefinitionBlock (
/* PCIe PME# event */ Method(_L12) { - //DBGO("\_GPE\_L12\n") + //DBGO("\_GPE\_L12\n") }
/* _L13 GPM0 SCI event - Moved to USB.asl */ @@ -1110,12 +1110,12 @@ DefinitionBlock (
/* GPM6 SCI event - Reassigned to _L06 */ Method(_L1C) { - //DBGO("\_GPE\_L1C\n") + //DBGO("\_GPE\_L1C\n") }
/* GPM7 SCI event - Reassigned to _L07 */ Method(_L1D) { - //DBGO("\_GPE\_L1D\n") + //DBGO("\_GPE\_L1D\n") }
/* GPIO2 or GPIO66 SCI event */ @@ -1423,7 +1423,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1497,60 +1497,60 @@ DefinitionBlock ( Name (CRS, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length ,,) IO (Decode16, - 0x0CF8, // Range Minimum - 0x0CF8, // Range Maximum - 0x01, // Alignment - 0x08, // Length + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length )
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x03AF, // Range Maximum - 0x0000, // Translation Offset - 0x03B0, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x03AF, // Range Maximum + 0x0000, // Translation Offset + 0x03B0, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03E0, // Range Minimum - 0x0CF7, // Range Maximum - 0x0000, // Translation Offset - 0x0918, // Length + 0x0000, // Granularity + 0x03E0, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0918, // Length ,, , TypeStatic)
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03B0, // Range Minimum - 0x03BB, // Range Maximum - 0x0000, // Translation Offset - 0x000C, // Length + 0x0000, // Granularity + 0x03B0, // Range Minimum + 0x03BB, // Range Maximum + 0x0000, // Translation Offset + 0x000C, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03C0, // Range Minimum - 0x03DF, // Range Maximum - 0x0000, // Translation Offset - 0x0020, // Length + 0x0000, // Granularity + 0x03C0, // Range Minimum + 0x03DF, // Range Maximum + 0x0000, // Translation Offset + 0x0020, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0D00, // Range Minimum - 0xFFFF, // Range Maximum - 0x0000, // Translation Offset - 0xF300, // Length + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
Memory32Fixed (ReadOnly, - 0xE0000000, // Address Base - 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) + 0xE0000000, // Address Base + 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) })
@@ -1559,18 +1559,18 @@ DefinitionBlock ( CreateDWordField (CRS, _SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, _SB.PCI0.MMIO._LEN, LEN1)
- /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1)
Return (CRS) @@ -1578,23 +1578,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1602,7 +1602,7 @@ DefinitionBlock ( CkOT() /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) *} */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index 45f1555..48cb526 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pstate_cnt = 0xe2;
/* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 25dc2a2..50e1b37 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) */
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10;
#if CONFIG_AMD_SB_CIMX diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index c10a219..fca029f 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
}
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c index aeb91a7..924c692 100644 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ b/src/mainboard/supermicro/h8qgi/platform_oem.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index 07cd3d4..d1a23a6 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -104,8 +104,8 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); * - * @param[in] u32 func Northbridge CIMx CallBackId - * @param[in] u32 data Northbridge Input Data. + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. * */ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h index 8547faa..0dc141c 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -66,7 +66,7 @@ /** * Bitmap of ports that have slot or onboard device connected. * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) - * #define DEFAULT_PORT_FORCE_GEN1 0x604 + * #define DEFAULT_PORT_FORCE_GEN1 0x604 */ #ifndef DEFAULT_PORT_FORCE_GEN1 #define DEFAULT_PORT_FORCE_GEN1 0x0 @@ -107,12 +107,12 @@
/** * Default GPP3a core configuraton on NB #0/1/2/3. - * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 - * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 - * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 - * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 - * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 - * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 */ #ifndef DEFAULT_GPP3A_CONFIG #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 @@ -153,17 +153,17 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. } NB_PLATFORM_CONFIG;
/** diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c index ff2334f..fcdb796 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.c +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -19,7 +19,7 @@
#include <string.h> -#include <console/console.h> /* printk */ +#include <console/console.h> /* printk */ #include "Platform.h" #include "sb700_cfg.h"
@@ -96,7 +96,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER;
/* USB */ - sb_config->UsbIntClock = 0; // Use external clock + sb_config->UsbIntClock = 0; // Use external clock sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index 1df3fc5..a91d0d3 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -30,10 +30,10 @@ * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7
/* In SB700, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -57,7 +57,7 @@ * 0 - Disable Spread Spectrum function * 1 - Enable Spread Spectrum function */ -#define SPREAD_SPECTRUM 0 +#define SPREAD_SPECTRUM 0
/** * @def SB_HPET_TIMER @@ -65,7 +65,7 @@ * 0 - Disable hpet * 1 - Enable hpet */ -#define HPET_TIMER 1 +#define HPET_TIMER 1
/** * @def USB_CONFIG @@ -80,7 +80,7 @@ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 */ -#define USB_CINFIG 0x7F +#define USB_CINFIG 0x7F
/** * @def PCI_CLOCK_CTRL @@ -93,14 +93,14 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x1F
/** * @def SATA_CONTROLLER * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER -#define SATA_CONTROLLER 1 +#define SATA_CONTROLLER 1 #endif
/** @@ -109,14 +109,14 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE NATIVE_IDE_MODE #endif
/** * @brief INCHIP Sata IDE Controller Mode */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1
/** * @def SATA_IDE_MODE @@ -124,7 +124,7 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE -#define SATA_IDE_MODE IDE_LEGACY_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE #endif
/** @@ -136,37 +136,37 @@ * @brief 01/11: Reference clock from internal clock through * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01
-#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK
/** * @def SATA_PORT_MULT_CAP_RESERVED * @brief 1 ON, 0 0FF */ -#define SATA_PORT_MULT_CAP_RESERVED 1 +#define SATA_PORT_MULT_CAP_RESERVED 1
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2
/** * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER -#define AZALIA_CONTROLLER AZALIA_AUTO +#define AZALIA_CONTROLLER AZALIA_AUTO #endif
/** @@ -176,7 +176,7 @@ * 1 - enable */ #ifndef AZALIA_PIN_CONFIG -#define AZALIA_PIN_CONFIG 1 +#define AZALIA_PIN_CONFIG 1 #endif
/** @@ -191,19 +191,19 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA +//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN -#define AZALIA_SDIN_PIN_0 0x2 -#define AZALIA_SDIN_PIN_1 0x2 -#define AZALIA_SDIN_PIN_2 0x2 -#define AZALIA_SDIN_PIN_3 0x0 +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif
/** * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER -#define GPP_CONTROLLER 1 +#define GPP_CONTROLLER 1 #endif
/** @@ -216,7 +216,7 @@ * GPP_CFGMODE_X1111 */ #ifndef GPP_CFGMODE -#define GPP_CFGMODE GPP_CFGMODE_X1111 +#define GPP_CFGMODE GPP_CFGMODE_X1111 #endif
diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 93a38d6..155d80c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -10,84 +10,84 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end @@ -96,15 +96,15 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 19.0 on end device pci 19.0 on end device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end end device pci 19.1 on end device pci 19.2 on end diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..86469ba 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -77,7 +77,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 4692ea0..3b9005d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, // don't touch it, we need it for CAR with FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -210,23 +210,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -241,35 +241,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ed3df3f..1e75552 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -82,23 +82,23 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; - enable_smbus(); + uint32_t dword; + uint8_t byte; + enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
- byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); + dword |= (1<<0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
- dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); + dword |= (1<<16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); }
static const u8 spd_addr[] = { @@ -163,17 +163,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val, wants_reset; msr_t msr;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - } + }
post_code(0x30);
- if (bist == 0) + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
post_code(0x32); @@ -222,13 +222,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * of the BSP located right after sysinfo. */
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); + start_other_cores(); post_code(0x37); - wait_all_other_cores_started(bsp_apicid); + wait_all_other_cores_started(bsp_apicid); #endif
post_code(0x38); @@ -240,14 +240,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0 + if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } + }
post_code(0x3A);
@@ -263,9 +263,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); - soft_reset(); + soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); - } + }
if (wants_reset) printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); @@ -279,7 +279,7 @@ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D);
//printk(BIOS_DEBUG, "enable_smbus()\n"); -// enable_smbus(); /* enable in sio_setup */ +// enable_smbus(); /* enable in sio_setup */
post_code(0x40);
@@ -304,8 +304,8 @@ post_code(0x40); * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 97f59b3..05f2f69 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -138,11 +138,11 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -159,14 +159,14 @@ AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -289,12 +289,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -407,8 +407,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -441,7 +441,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); return Status; @@ -449,9 +449,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h index bf719bf..ec3ba32 100644 --- a/src/mainboard/supermicro/h8scm/OptionsIds.h +++ b/src/mainboard/supermicro/h8scm/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -53,15 +53,15 @@ #define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED TRUE #define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/supermicro/h8scm/acpi/ide.asl b/src/mainboard/supermicro/h8scm/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/supermicro/h8scm/acpi/ide.asl +++ b/src/mainboard/supermicro/h8scm/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 49abe25..7d6e7fe 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -41,38 +41,38 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); @@ -173,9 +173,9 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
UINT32 agesawrapper_amdinitmmio(VOID) { - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader;
/* * Set the MMIO Configuration Base Address and Bus Range onto @@ -431,9 +431,9 @@ UINT32 agesawrapper_amdinitlate(VOID) AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -461,8 +461,8 @@ UINT32 agesawrapper_amdinitlate(VOID) AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.h b/src/mainboard/supermicro/h8scm/agesawrapper.h index a553ea8..7fc25c5 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.h +++ b/src/mainboard/supermicro/h8scm/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,25 +31,25 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index 4cc4c0e..a4a6e4d 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -55,90 +55,90 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +//#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE
/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +//#define BLDOPT_REMOVE_HT_ASSIST TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
/* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY//1600 -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE//TRUE -#define BLDCFG_MEMORY_POWER_DOWN FALSE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY //DDR800_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY//1600 +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE//TRUE +#define BLDCFG_MEMORY_POWER_DOWN FALSE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY //DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/** * Enable Message Based C1e CPU feature in multi-socket systems. * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value, * else the feature cannot be enabled. */ -#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased -#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 - -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#define BLDCFG_1GB_ALIGN FALSE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define BLDCFG_1GB_ALIGN FALSE +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' //
// Select the platform control flow mode for performance tuning. @@ -151,8 +151,8 @@ * * This feature may interact with other performance features. * TRUE -Enable the feature (default) if supported by all processors, - * based on revision and presence of L3 cache. - * The feature is not enabled if there are no coherent HT links. + * based on revision and presence of L3 cache. + * The feature is not enabled if there are no coherent HT links. * FALSE -Do not enable the feature regardless of the configuration. */ //TODO enable it, @@ -339,22 +339,22 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
#include "SanMarinoInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -380,64 +380,64 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. //
/* Specifies the write leveling seed for a channel of a socket. * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, - * ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) */ WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, @@ -446,8 +446,8 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { F15_WL_SEED),
/* HW_RXEN_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) */ HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -487,8 +487,8 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -514,7 +514,7 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
diff --git a/src/mainboard/supermicro/h8scm/cmos.layout b/src/mainboard/supermicro/h8scm/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/supermicro/h8scm/cmos.layout +++ b/src/mainboard/supermicro/h8scm/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb index a4e6c97..067a26c 100644 --- a/src/mainboard/supermicro/h8scm/devicetree.cb +++ b/src/mainboard/supermicro/h8scm/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/agesa/family15/root_complex device domain 0 on subsystemid 0x15d9 0xab11 inherit #Supermicro chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl index 5e18375..a0492de 100644 --- a/src/mainboard/supermicro/h8scm/dsdt.asl +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) @@ -314,8 +314,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -455,7 +455,7 @@ DefinitionBlock ( if(CondRefOf(_OSI,Local1)) { Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } @@ -834,7 +834,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -989,17 +989,17 @@ DefinitionBlock ( Scope(_GPE) { /* Start Scope GPE */ /* General event 0 */ Method(_L00) { - //DBGO("\_GPE\_L00\n") + //DBGO("\_GPE\_L00\n") }
/* General event 1 */ Method(_L01) { - //DBGO("\_GPE\_L01\n") + //DBGO("\_GPE\_L01\n") }
/* General event 2 */ Method(_L02) { - //DBGO("\_GPE\_L02\n") + //DBGO("\_GPE\_L02\n") }
/* General event 3 */ @@ -1010,12 +1010,12 @@ DefinitionBlock (
/* General event 4 */ Method(_L04) { - //DBGO("\_GPE\_L04\n") + //DBGO("\_GPE\_L04\n") }
/* General event 5 */ Method(_L05) { - //DBGO("\_GPE\_L05\n") + //DBGO("\_GPE\_L05\n") }
/* _L06 General event 6 - Used for GPM6, moved to USB.asl */ @@ -1034,7 +1034,7 @@ DefinitionBlock (
/* Reserved */ Method(_L0A) { - //DBGO("\_GPE\_L0A\n") + //DBGO("\_GPE\_L0A\n") }
/* USB controller PME# */ @@ -1051,12 +1051,12 @@ DefinitionBlock (
/* AC97 controller PME# */ Method(_L0C) { - //DBGO("\_GPE\_L0C\n") + //DBGO("\_GPE\_L0C\n") }
/* OtherTherm PME# */ Method(_L0D) { - //DBGO("\_GPE\_L0D\n") + //DBGO("\_GPE\_L0D\n") }
/* _L0E GPM9 SCI event - Moved to USB.asl */ @@ -1079,7 +1079,7 @@ DefinitionBlock (
/* PCIe PME# event */ Method(_L12) { - //DBGO("\_GPE\_L12\n") + //DBGO("\_GPE\_L12\n") }
/* _L13 GPM0 SCI event - Moved to USB.asl */ @@ -1111,12 +1111,12 @@ DefinitionBlock (
/* GPM6 SCI event - Reassigned to _L06 */ Method(_L1C) { - //DBGO("\_GPE\_L1C\n") + //DBGO("\_GPE\_L1C\n") }
/* GPM7 SCI event - Reassigned to _L07 */ Method(_L1D) { - //DBGO("\_GPE\_L1D\n") + //DBGO("\_GPE\_L1D\n") }
/* GPIO2 or GPIO66 SCI event */ @@ -1434,7 +1434,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1508,60 +1508,60 @@ DefinitionBlock ( Name (CRS, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length ,,) IO (Decode16, - 0x0CF8, // Range Minimum - 0x0CF8, // Range Maximum - 0x01, // Alignment - 0x08, // Length + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length )
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x03AF, // Range Maximum - 0x0000, // Translation Offset - 0x03B0, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x03AF, // Range Maximum + 0x0000, // Translation Offset + 0x03B0, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03E0, // Range Minimum - 0x0CF7, // Range Maximum - 0x0000, // Translation Offset - 0x0918, // Length + 0x0000, // Granularity + 0x03E0, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0918, // Length ,, , TypeStatic)
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03B0, // Range Minimum - 0x03BB, // Range Maximum - 0x0000, // Translation Offset - 0x000C, // Length + 0x0000, // Granularity + 0x03B0, // Range Minimum + 0x03BB, // Range Maximum + 0x0000, // Translation Offset + 0x000C, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03C0, // Range Minimum - 0x03DF, // Range Maximum - 0x0000, // Translation Offset - 0x0020, // Length + 0x0000, // Granularity + 0x03C0, // Range Minimum + 0x03DF, // Range Maximum + 0x0000, // Translation Offset + 0x0020, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0D00, // Range Minimum - 0xFFFF, // Range Maximum - 0x0000, // Translation Offset - 0xF300, // Length + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
Memory32Fixed (ReadOnly, - 0xE0000000, // Address Base - 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) + 0xE0000000, // Address Base + 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) })
@@ -1570,18 +1570,18 @@ DefinitionBlock ( CreateDWordField (CRS, _SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, _SB.PCI0.MMIO._LEN, LEN1)
- /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1)
Return (CRS) @@ -1589,23 +1589,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1613,7 +1613,7 @@ DefinitionBlock ( CkOT() /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) *} */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c index ab50e0f..90c239a 100644 --- a/src/mainboard/supermicro/h8scm/fadt.c +++ b/src/mainboard/supermicro/h8scm/fadt.c @@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pstate_cnt = 0xe2;
/* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 4b2cb32..68de26d 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -135,7 +135,7 @@ void get_bus_conf(void) */
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10;
#if CONFIG_AMD_SB_CIMX diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index c10a219..fca029f 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
}
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/supermicro/h8scm/platform_oem.c b/src/mainboard/supermicro/h8scm/platform_oem.c index aeb91a7..924c692 100644 --- a/src/mainboard/supermicro/h8scm/platform_oem.c +++ b/src/mainboard/supermicro/h8scm/platform_oem.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index 07cd3d4..d1a23a6 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -104,8 +104,8 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); * - * @param[in] u32 func Northbridge CIMx CallBackId - * @param[in] u32 data Northbridge Input Data. + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. * */ diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h index 8547faa..0dc141c 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.h +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h @@ -66,7 +66,7 @@ /** * Bitmap of ports that have slot or onboard device connected. * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) - * #define DEFAULT_PORT_FORCE_GEN1 0x604 + * #define DEFAULT_PORT_FORCE_GEN1 0x604 */ #ifndef DEFAULT_PORT_FORCE_GEN1 #define DEFAULT_PORT_FORCE_GEN1 0x0 @@ -107,12 +107,12 @@
/** * Default GPP3a core configuraton on NB #0/1/2/3. - * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 - * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 - * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 - * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 - * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 - * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 */ #ifndef DEFAULT_GPP3A_CONFIG #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 @@ -153,17 +153,17 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. } NB_PLATFORM_CONFIG;
/** diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.c b/src/mainboard/supermicro/h8scm/sb700_cfg.c index c03a501..e520842 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.c +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.c @@ -19,7 +19,7 @@
#include <string.h> -#include <console/console.h> /* printk */ +#include <console/console.h> /* printk */ #include "Platform.h" #include "sb700_cfg.h"
@@ -96,7 +96,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER;
/* USB */ - sb_config->UsbIntClock = 0; // Use external clock + sb_config->UsbIntClock = 0; // Use external clock sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index 40c89fa..8bba30a 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -30,10 +30,10 @@ * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7
/* In SB700, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -57,7 +57,7 @@ * 0 - Disable Spread Spectrum function * 1 - Enable Spread Spectrum function */ -#define SPREAD_SPECTRUM 0 +#define SPREAD_SPECTRUM 0
/** * @def SB_HPET_TIMER @@ -65,7 +65,7 @@ * 0 - Disable hpet * 1 - Enable hpet */ -#define HPET_TIMER 1 +#define HPET_TIMER 1
/** * @def USB_CONFIG @@ -80,7 +80,7 @@ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 */ -#define USB_CINFIG 0x7F +#define USB_CINFIG 0x7F
/** * @def PCI_CLOCK_CTRL @@ -93,14 +93,14 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x1F
/** * @def SATA_CONTROLLER * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER -#define SATA_CONTROLLER 1 +#define SATA_CONTROLLER 1 #endif
/** @@ -109,14 +109,14 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE NATIVE_IDE_MODE #endif
/** * @brief INCHIP Sata IDE Controller Mode */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1
/** * @def SATA_IDE_MODE @@ -124,7 +124,7 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE -#define SATA_IDE_MODE IDE_LEGACY_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE #endif
/** @@ -136,37 +136,37 @@ * @brief 01/11: Reference clock from internal clock through * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01
-#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK
/** * @def SATA_PORT_MULT_CAP_RESERVED * @brief 1 ON, 0 0FF */ -#define SATA_PORT_MULT_CAP_RESERVED 1 +#define SATA_PORT_MULT_CAP_RESERVED 1
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2
/** * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER -#define AZALIA_CONTROLLER AZALIA_AUTO +#define AZALIA_CONTROLLER AZALIA_AUTO #endif
/** @@ -176,7 +176,7 @@ * 1 - enable */ #ifndef AZALIA_PIN_CONFIG -#define AZALIA_PIN_CONFIG 1 +#define AZALIA_PIN_CONFIG 1 #endif
/** @@ -191,19 +191,19 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -//#define AZALIA_SDIN_PIN 0xAA +//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN -#define AZALIA_SDIN_PIN_0 0x2 -#define AZALIA_SDIN_PIN_1 0x2 -#define AZALIA_SDIN_PIN_2 0x2 -#define AZALIA_SDIN_PIN_3 0x0 +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif
/** * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER -#define GPP_CONTROLLER 1 +#define GPP_CONTROLLER 1 #endif
/** @@ -216,7 +216,7 @@ * GPP_CFGMODE_X1111 */ #ifndef GPP_CFGMODE -#define GPP_CFGMODE GPP_CFGMODE_X1111 +#define GPP_CFGMODE GPP_CFGMODE_X1111 #endif
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl b/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl index 3283f6f..4b0f7f0 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl +++ b/src/mainboard/supermicro/h8scm_fam10/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index fece2b7..06f077c 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB700 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, gsi_base); + IO_APIC_ADDR, gsi_base); /* IOAPIC on rs5690 */ gsi_base += 24; /* SB700 has 24 IOAPIC entries. */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -81,7 +81,7 @@ unsigned long acpi_fill_madt(unsigned long current) pci_write_config32(dev, 0xF8, 0x1); dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2+1, - dword, gsi_base); + dword, gsi_base); }
diff --git a/src/mainboard/supermicro/h8scm_fam10/cmos.layout b/src/mainboard/supermicro/h8scm_fam10/cmos.layout index 53fdef5..d428dee 100644 --- a/src/mainboard/supermicro/h8scm_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8scm_fam10/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index ba7eb2a..3685b25 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -1,4 +1,4 @@ -# GPP1 (dev2,3) --> slot 7 +# GPP1 (dev2,3) --> slot 7 # GPP2 (dev12) --> slot 6 # GPP3A (dev9,A) --> Lan1, Lan2
@@ -50,43 +50,43 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627hf device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 off # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 off # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - device pnp 2e.7 off # GPIO_GAME_MIDI + device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 - end + end end #superio/winbond/w83627hf end #LPC device pci 14.4 on end # PCI 0x4384 diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index 13e5620..f4c5402 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) @@ -131,7 +131,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -152,13 +152,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -177,7 +177,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -302,8 +302,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -439,16 +439,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -819,7 +819,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1199,7 +1199,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1221,8 +1221,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1232,8 +1232,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1241,8 +1241,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1250,8 +1250,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1260,8 +1260,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1270,8 +1270,8 @@ DefinitionBlock ( Name(_ADR, 0x00090000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS9) } /* APIC mode */ - Return (PS9) /* PIC Mode */ + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ } /* end _PRT */ } /* end PBR9 */
@@ -1279,8 +1279,8 @@ DefinitionBlock ( Name(_ADR, 0x000A0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSa) } /* APIC mode */ - Return (PSa) /* PIC Mode */ + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ } /* end _PRT */ } /* end PBRa */
@@ -1288,8 +1288,8 @@ DefinitionBlock ( Name(_ADR, 0x000b0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSb) } /* APIC mode */ - Return (PSb) /* PIC Mode */ + If(PMOD){ Return(APSb) } /* APIC mode */ + Return (PSb) /* PIC Mode */ } /* end _PRT */ } /* end PBRb */
@@ -1297,8 +1297,8 @@ DefinitionBlock ( Name(_ADR, 0x000c0000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APSc) } /* APIC mode */ - Return (PSc) /* PIC Mode */ + If(PMOD){ Return(APSc) } /* APIC mode */ + Return (PSc) /* PIC Mode */ } /* end _PRT */ } /* end PBRc */
@@ -1490,7 +1490,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1690,23 +1690,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1715,7 +1715,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 142c9e6..a856728 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -126,7 +126,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 01a6980..80942b9 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) apicid_sr5650 = apicid_sp5100 + 1;
mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) } }
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -112,7 +112,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -168,7 +168,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c index b7a4b4f..0e9fd31 100644 --- a/src/mainboard/supermicro/h8scm_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8scm_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,27 +106,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -147,21 +147,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -178,23 +178,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -208,23 +208,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -238,35 +238,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0 PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 116ae0c..3548481 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -263,8 +263,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/supermicro/x6dai_g/cmos.layout b/src/mainboard/supermicro/x6dai_g/cmos.layout index 81f1a69..6742bd2 100644 --- a/src/mainboard/supermicro/x6dai_g/cmos.layout +++ b/src/mainboard/supermicro/x6dai_g/cmos.layout @@ -1,75 +1,75 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/supermicro/x6dai_g/irq_tables.c b/src/mainboard/supermicro/x6dai_g/irq_tables.c index 0574f05..4cedd15 100644 --- a/src/mainboard/supermicro/x6dai_g/irq_tables.c +++ b/src/mainboard/supermicro/x6dai_g/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x122e, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x78, /* u8 checksum - mod 256 checksum must give zero */ + 0x78, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, 0x00, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0x00}, {0x00, 0x10, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}, {0x63, 0xdef8}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index f57adaf..9096196 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -69,12 +69,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) - die("Missing 6300ESB?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) + die("Missing 6300ESB?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); diff --git a/src/mainboard/supermicro/x6dhe_g/cmos.layout b/src/mainboard/supermicro/x6dhe_g/cmos.layout index 81f1a69..6742bd2 100644 --- a/src/mainboard/supermicro/x6dhe_g/cmos.layout +++ b/src/mainboard/supermicro/x6dhe_g/cmos.layout @@ -1,75 +1,75 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/supermicro/x6dhe_g/irq_tables.c b/src/mainboard/supermicro/x6dhe_g/irq_tables.c index 594d948..38ade71 100644 --- a/src/mainboard/supermicro/x6dhe_g/irq_tables.c +++ b/src/mainboard/supermicro/x6dhe_g/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x25a1, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 071bb35..13bc550 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -72,12 +72,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) - die("Missing esb6300?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) + die("Missing esb6300?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); diff --git a/src/mainboard/supermicro/x6dhe_g2/cmos.layout b/src/mainboard/supermicro/x6dhe_g2/cmos.layout index 81f1a69..6742bd2 100644 --- a/src/mainboard/supermicro/x6dhe_g2/cmos.layout +++ b/src/mainboard/supermicro/x6dhe_g2/cmos.layout @@ -1,75 +1,75 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/supermicro/x6dhe_g2/irq_tables.c b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c index 594d948..38ade71 100644 --- a/src/mainboard/supermicro/x6dhe_g2/irq_tables.c +++ b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x25a1, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index c6350e8..6ae51aa 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -72,12 +72,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) - die("Missing ich5r?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); + if (dev == PCI_DEV_INVALID) + die("Missing ich5r?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); diff --git a/src/mainboard/supermicro/x6dhr_ig/cmos.layout b/src/mainboard/supermicro/x6dhr_ig/cmos.layout index 81f1a69..6742bd2 100644 --- a/src/mainboard/supermicro/x6dhr_ig/cmos.layout +++ b/src/mainboard/supermicro/x6dhr_ig/cmos.layout @@ -1,75 +1,75 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 3a037fb..26c4821 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -52,9 +52,9 @@ chip northbridge/intel/e7520 # mch device pci 0.2 on # On board gig e1000 chip drivers/generic/generic - device pci 02.0 on end - device pci 02.1 on end - end + device pci 02.0 on end + device pci 02.1 on end + end end device pci 0.3 on end end diff --git a/src/mainboard/supermicro/x6dhr_ig/irq_tables.c b/src/mainboard/supermicro/x6dhr_ig/irq_tables.c index 0988cb4..e98d68b 100644 --- a/src/mainboard/supermicro/x6dhr_ig/irq_tables.c +++ b/src/mainboard/supermicro/x6dhr_ig/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x24d0, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 9c61d60..b8ddc29 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -71,12 +71,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) - die("Missing ich5?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) + die("Missing ich5?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); diff --git a/src/mainboard/supermicro/x6dhr_ig2/cmos.layout b/src/mainboard/supermicro/x6dhr_ig2/cmos.layout index 81f1a69..6742bd2 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/cmos.layout +++ b/src/mainboard/supermicro/x6dhr_ig2/cmos.layout @@ -1,75 +1,75 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index 93199d7..34f4ed6 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -2,111 +2,111 @@
static void print_reg(unsigned char index) { - unsigned char data; + unsigned char data;
- outb(index, 0x2e); - data = inb(0x2f); + outb(index, 0x2e); + data = inb(0x2f); print_debug("0x"); print_debug_hex8(index); print_debug(": 0x"); print_debug_hex8(data); print_debug("\n"); - return; + return; }
static void xbus_en(void) { - /* select the XBUS function in the SIO */ - outb(0x07, 0x2e); - outb(0x0f, 0x2f); - outb(0x30, 0x2e); - outb(0x01, 0x2f); + /* select the XBUS function in the SIO */ + outb(0x07, 0x2e); + outb(0x0f, 0x2f); + outb(0x30, 0x2e); + outb(0x01, 0x2f); return; }
static void setup_func(unsigned char func) { - /* select the function in the SIO */ - outb(0x07, 0x2e); - outb(func, 0x2f); - /* print out the regs */ - print_reg(0x30); - print_reg(0x60); - print_reg(0x61); - print_reg(0x62); - print_reg(0x63); - print_reg(0x70); - print_reg(0x71); - print_reg(0x74); - print_reg(0x75); - return; + /* select the function in the SIO */ + outb(0x07, 0x2e); + outb(func, 0x2f); + /* print out the regs */ + print_reg(0x30); + print_reg(0x60); + print_reg(0x61); + print_reg(0x62); + print_reg(0x63); + print_reg(0x70); + print_reg(0x71); + print_reg(0x74); + print_reg(0x75); + return; }
static void siodump(void) { - int i; - unsigned char data; + int i; + unsigned char data;
print_debug("\n*** SERVER I/O REGISTERS ***\n"); - for (i=0x10; i<=0x2d; i++) { - print_reg((unsigned char)i); - } + for (i=0x10; i<=0x2d; i++) { + print_reg((unsigned char)i); + } #if 0 - print_debug("\n*** XBUS REGISTERS ***\n"); - setup_func(0x0f); - for (i=0xf0; i<=0xff; i++) { - print_reg((unsigned char)i); - } + print_debug("\n*** XBUS REGISTERS ***\n"); + setup_func(0x0f); + for (i=0xf0; i<=0xff; i++) { + print_reg((unsigned char)i); + }
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); - setup_func(0x03); - print_reg(0xf0); + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); + setup_func(0x03); + print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); - setup_func(0x02); - print_reg(0xf0); + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); + setup_func(0x02); + print_reg(0xf0);
#endif - print_debug("\n*** GPIO REGISTERS ***\n"); - setup_func(0x07); - for (i=0xf0; i<=0xf8; i++) { - print_reg((unsigned char)i); - } - print_debug("\n*** GPIO VALUES ***\n"); - data = inb(0x68a); + print_debug("\n*** GPIO REGISTERS ***\n"); + setup_func(0x07); + for (i=0xf0; i<=0xf8; i++) { + print_reg((unsigned char)i); + } + print_debug("\n*** GPIO VALUES ***\n"); + data = inb(0x68a); print_debug("\nGPDO 4: 0x"); print_debug_hex8(data); - data = inb(0x68b); + data = inb(0x68b); print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n");
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); - setup_func(0x0a); - print_reg(0xf0); + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); + setup_func(0x0a); + print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n"); - setup_func(0x09); - print_reg(0xf0); - print_reg(0xf1); + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); + setup_func(0x09); + print_reg(0xf0); + print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n"); - setup_func(0x10); - print_reg(0xf0); - print_reg(0xf1); - print_reg(0xf3); - print_reg(0xf6); - print_reg(0xf7); - print_reg(0xfe); - print_reg(0xff); + print_debug("\n*** RTC REGISTERS ***\n"); + setup_func(0x10); + print_reg(0xf0); + print_reg(0xf1); + print_reg(0xf3); + print_reg(0xf6); + print_reg(0xf7); + print_reg(0xfe); + print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); - setup_func(0x14); - print_reg(0xf0); + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); + setup_func(0x14); + print_reg(0xf0); #endif - return; + return; }
static void print_debug_pci_dev(unsigned dev) @@ -268,28 +268,28 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM7) { - int status = 0; - int i; - print_debug("\n"); - print_debug("dimm "); + unsigned device; + device = DIMM0; + while(device <= DIMM7) { + int status = 0; + int i; + print_debug("\n"); + print_debug("dimm "); print_debug_hex8(device);
- for(i = 0; (i < 256) ; i++) { - unsigned char byte; - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + unsigned char byte; + if ((i % 16) == 0) { print_debug("\n"); print_debug_hex8(i); print_debug(": "); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -301,23 +301,23 @@ void dump_spd_registers(void)
void dump_ipmi_registers(void) { - unsigned device; - device = 0x42; - while(device <= 0x42) { - int status = 0; - int i; - print_debug("\n"); - print_debug("ipmi "); + unsigned device; + device = 0x42; + while(device <= 0x42) { + int status = 0; + int i; + print_debug("\n"); + print_debug("ipmi "); print_debug_hex8(device);
- for(i = 0; (i < 8) ; i++) { - unsigned char byte; + for(i = 0; (i < 8) ; i++) { + unsigned char byte; status = smbus_read_byte(device, 2); - if (status < 0) { - print_debug("bad device: "); + if (status < 0) { + print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index ca8650b..2144135 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -51,9 +51,9 @@ chip northbridge/intel/e7520 # mch device pci 0.0 on # On board gig e1000 chip drivers/generic/generic - device pci 03.0 on end - device pci 03.1 on end - end + device pci 03.0 on end + device pci 03.1 on end + end end device pci 0.1 on end device pci 0.2 on end diff --git a/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c b/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c index 0988cb4..e98d68b 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c +++ b/src/mainboard/supermicro/x6dhr_ig2/irq_tables.c @@ -5,15 +5,15 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x52495024, /* u32 signature */ 0x0100, /* u16 version */ - 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - 0xf8, /* u8 Device 1, Function 0 */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ 0x0000, /* u16 reserve IRQ for PCI */ 0x8086, /* u16 Vendor */ 0x24d0, /* Device ID */ 0x00000000, /* u32 miniport_data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 7cfe818..a83c327 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -72,12 +72,12 @@ static void main(unsigned long bist)
/* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) - die("Missing ich5?"); - pci_write_config32(dev, 0xe8, 0x00000000); - pci_write_config8(dev, 0xf0, 0x00); + device_t dev; + dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + if (dev == PCI_DEV_INVALID) + die("Missing ich5?"); + pci_write_config32(dev, 0xe8, 0x00000000); + pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout index 29e78ad..cc81664 100644 --- a/src/mainboard/supermicro/x7db8/cmos.layout +++ b/src/mainboard/supermicro/x7db8/cmos.layout @@ -23,115 +23,115 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year # ----------------------------------------------------------------- # Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP # ----------------------------------------------------------------- # Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates # ----------------------------------------------------------------- # Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag # ----------------------------------------------------------------- # Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram # ----------------------------------------------------------------- # Diagnostic Status Register -#112 8 r 0 diag_rsvd1 +#112 8 r 0 diag_rsvd1
# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused +0 120 r 0 reserved_memory +#120 264 r 0 unused
# ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -385 1 e 4 last_boot -388 4 r 0 reboot_bits -#390 2 r 0 unused? +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused?
# ----------------------------------------------------------------- # coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused
# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused +400 1 e 2 hyper_threading +#401 7 r 0 unused
# coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail -#411 5 r 0 unused +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused
# coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt -#938 46 r 0 unused +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused
# coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes 9 0 Secondary 9 1 Primary # ----------------------------------------------------------------- diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb index e09619f..6914c62 100644 --- a/src/mainboard/supermicro/x7db8/devicetree.cb +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -41,10 +41,10 @@ chip northbridge/intel/i5000 device pci 00.0 on # PCI Express Upstream Port device pci 00.0 on # PCI Express Downstream Port E1 device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A - ioapic_irq 8 INTA 0x11 - ioapic_irq 8 INTB 0x10 - ioapic_irq 8 INTC 0x11 - ioapic_irq 8 INTD 0x10 + ioapic_irq 8 INTA 0x11 + ioapic_irq 8 INTB 0x10 + ioapic_irq 8 INTC 0x11 + ioapic_irq 8 INTD 0x10 # PCI slot device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B # PCI slot @@ -67,10 +67,10 @@ chip northbridge/intel/i5000 device pci 06.0 on end device pci 07.0 on end device pci 00.3 on # PCI Express to PCI-X Bridge - ioapic_irq 9 INTA 3 - ioapic_irq 9 INTB 0 - ioapic_irq 9 INTC 1 - ioapic_irq 9 INTD 2 + ioapic_irq 9 INTA 3 + ioapic_irq 9 INTB 0 + ioapic_irq 9 INTC 1 + ioapic_irq 9 INTD 2 # PCI-X Slot end end @@ -143,10 +143,10 @@ chip northbridge/intel/i5000
device pnp 2e.3 off end device pnp 2e.5 on # KBC - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end
device pnp 2e.6 off end # CIR diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c index 65c1822..8d99e9a 100644 --- a/src/mainboard/supermicro/x7db8/irq_tables.c +++ b/src/mainboard/supermicro/x7db8/irq_tables.c @@ -34,9 +34,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index bc54ed7..bf64966 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -41,7 +41,7 @@ #define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_HPTC 0x3404 /* 32 bit */ #define RCBA_GCS 0x3410 /* 32 bit */ -#define RCBA_FD 0x3418 /* 32 bit */ +#define RCBA_FD 0x3418 /* 32 bit */
static void early_config(void) { diff --git a/src/mainboard/technexion/tim5690/acpi/ide.asl b/src/mainboard/technexion/tim5690/acpi/ide.asl index 7cee00d..5e6d207 100644 --- a/src/mainboard/technexion/tim5690/acpi/ide.asl +++ b/src/mainboard/technexion/tim5690/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/technexion/tim5690/acpi_tables.c b/src/mainboard/technexion/tim5690/acpi_tables.c index 0465c1b..96429b5 100644 --- a/src/mainboard/technexion/tim5690/acpi_tables.c +++ b/src/mainboard/technexion/tim5690/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/technexion/tim5690/cmos.layout b/src/mainboard/technexion/tim5690/cmos.layout index 86aadf5..981f476 100644 --- a/src/mainboard/technexion/tim5690/cmos.layout +++ b/src/mainboard/technexion/tim5690/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index 23b9741..c5da037 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/amd/amdk8/root_complex device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 20fe2d7..0eaec18 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "TECHNEXION", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "TECHNEXION", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -380,16 +380,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -762,7 +762,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1142,7 +1142,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1164,8 +1164,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1175,8 +1175,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1184,8 +1184,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1193,8 +1193,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1396,7 +1396,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1411,7 +1411,7 @@ DefinitionBlock ( Offset (0xF0), APC0, 8, /* APC/PME Event Enable Register */ APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ + APC2, 8, /* APC/PME Control Register 1 */ APC3, 8, /* Environment Controller Special Configuration Register */ APC4, 8 /* APC/PME Control Register 2 */ } @@ -1435,7 +1435,7 @@ DefinitionBlock ( * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1577,23 +1577,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1602,7 +1602,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..3a79668 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -30,7 +30,7 @@ #include "vgabios.h"
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000
@@ -56,21 +56,21 @@ #define TV_MODE_NO 0xff /* No TV Support */
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA SIO_BASE+1
/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ -#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */ +#define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); @@ -86,29 +86,29 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); LDN the register belongs to, before you can access the register. */ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) { - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); }
static void it8712f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); + /* Enter the configuration state (MB PnP mode). */ + + /* Perform MB PnP setup to put the SIO chip at 0x2e. */ + /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ + /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ + outb(0x87, IT8712F_CONFIGURATION_PORT); + outb(0x01, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); + outb(0x55, IT8712F_CONFIGURATION_PORT); }
static void it8712f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); + /* Exit the configuration state (MB PnP mode). */ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); }
/* set thermal config @@ -177,15 +177,15 @@ static void set_thermal_config(void) /* Mainboard specific GPIO setup. */ static void mb_gpio_init(u16 *iobase) { - /* Init Super I/O GPIOs. */ - it8712f_enter_conf(); - outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); - outb(IT8712F_GPIO, SIO_DATA); - outb(0x62, SIO_INDEX); - outb((*iobase >> 8), SIO_DATA); - outb(0x63, SIO_INDEX); - outb((*iobase & 0xff), SIO_DATA); - it8712f_exit_conf(); + /* Init Super I/O GPIOs. */ + it8712f_enter_conf(); + outb(IT8712F_CONFIG_REG_LDN, SIO_INDEX); + outb(IT8712F_GPIO, SIO_DATA); + outb(0x62, SIO_INDEX); + outb((*iobase >> 8), SIO_DATA); + outb(0x63, SIO_INDEX); + outb((*iobase & 0xff), SIO_DATA); + it8712f_exit_conf(); }
#if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 6a94479..f0280de 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -147,7 +147,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/technexion/tim5690/tn_post_code.h b/src/mainboard/technexion/tim5690/tn_post_code.h index 46d7382..05c0588 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.h +++ b/src/mainboard/technexion/tim5690/tn_post_code.h @@ -18,9 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define LED_MESSAGE_START 0xFF -#define LED_MESSAGE_FINISH 0x99 -#define LED_MESSAGE_RAM 0x01 +#define LED_MESSAGE_START 0xFF +#define LED_MESSAGE_FINISH 0x99 +#define LED_MESSAGE_RAM 0x01
#ifdef __PRE_RAM__ diff --git a/src/mainboard/technexion/tim5690/vgabios.c b/src/mainboard/technexion/tim5690/vgabios.c index 3d09a86..1847956 100644 --- a/src/mainboard/technexion/tim5690/vgabios.c +++ b/src/mainboard/technexion/tim5690/vgabios.c @@ -34,39 +34,39 @@ static rs690_vbios_regs vbios_regs_local; /* Initialization interrupt function */ static void vbios_fun_init(rs690_vbios_regs *vbios_regs) { - vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; - vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; + vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; + vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; }
/* BIOS int15 function */ int tim5690_int15_handler(void) { - int res = 0; + int res = 0;
- printk(BIOS_DEBUG, "tim5690_int15_handler\n"); + printk(BIOS_DEBUG, "tim5690_int15_handler\n");
- switch (X86_EAX & 0xffff) { - case AMD_RS690_INT15: - switch (X86_EBX & 0xff) { - case 0x00: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; - res = 1; - break; - case 0x05: - X86_EAX &= ~(0xff); - X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; - res = 1; - break; - } - break; - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", - X86_EAX & 0xffff); + switch (X86_EAX & 0xffff) { + case AMD_RS690_INT15: + switch (X86_EBX & 0xff) { + case 0x00: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun00_panel_id; + res = 1; + break; + case 0x05: + X86_EAX &= ~(0xff); + X86_EBX = (X86_EBX & ~(0xff)) | vbios_regs_local.int15_regs.fun05_tv_standard; + res = 1; + break; + } break; - } + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + X86_EAX & 0xffff); + break; + }
- return res; + return res; }
/* Initialization VBIOS function */ diff --git a/src/mainboard/technexion/tim5690/vgabios.h b/src/mainboard/technexion/tim5690/vgabios.h index a353011..3cc977e 100644 --- a/src/mainboard/technexion/tim5690/vgabios.h +++ b/src/mainboard/technexion/tim5690/vgabios.h @@ -24,13 +24,13 @@
typedef struct __rs690_int15_regs__ { - u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID - u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard + u8 fun00_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID + u8 fun05_tv_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard }rs690_int15_regs;
typedef struct __rs690_vbios_regs__ { - rs690_int15_regs int15_regs; + rs690_int15_regs int15_regs; }rs690_vbios_regs;
/* Initialization VBIOS function */ diff --git a/src/mainboard/technexion/tim8690/acpi/ide.asl b/src/mainboard/technexion/tim8690/acpi/ide.asl index 7cee00d..5e6d207 100644 --- a/src/mainboard/technexion/tim8690/acpi/ide.asl +++ b/src/mainboard/technexion/tim8690/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/technexion/tim8690/acpi_tables.c b/src/mainboard/technexion/tim8690/acpi_tables.c index 0465c1b..96429b5 100644 --- a/src/mainboard/technexion/tim8690/acpi_tables.c +++ b/src/mainboard/technexion/tim8690/acpi_tables.c @@ -73,7 +73,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); diff --git a/src/mainboard/technexion/tim8690/cmos.layout b/src/mainboard/technexion/tim8690/cmos.layout index 86aadf5..981f476 100644 --- a/src/mainboard/technexion/tim8690/cmos.layout +++ b/src/mainboard/technexion/tim8690/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index ff14075..30f6c80 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -48,7 +48,7 @@ chip northbridge/amd/amdk8/root_complex device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index 53be887..89442cb 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -19,11 +19,11 @@
/* DefinitionBlock Statement */ DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "TECHNEXION", /* OEMID */ - "COREBOOT", /* TABLE ID */ + "TECHNEXION", /* OEMID */ + "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ @@ -71,7 +71,7 @@ DefinitionBlock ( PIND, 0x00000008, /* Index 3 */ AINT, 0x00000008, /* Index 4 */ SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ + , 0x00000008, /* Index 6 */ AAUD, 0x00000008, /* Index 7 */ AMOD, 0x00000008, /* Index 8 */ PINE, 0x00000008, /* Index 9 */ @@ -92,13 +92,13 @@ DefinitionBlock ( /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -117,7 +117,7 @@ DefinitionBlock ( /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -242,8 +242,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -380,16 +380,16 @@ DefinitionBlock (
if(CondRefOf(_OSI,Local1)) { - Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + Store(1, OSTP) /* Assume some form of XP */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } } else { If(WCMP(_OS,"Linux")) { - Store(3, OSTP) /* Linux */ + Store(3, OSTP) /* Linux */ } Else { - Store(4, OSTP) /* Gotta be WinCE */ + Store(4, OSTP) /* Gotta be WinCE */ } } Return(OSTP) @@ -762,7 +762,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -1142,7 +1142,7 @@ DefinitionBlock (
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Northbridge devices */ @@ -1164,8 +1164,8 @@ DefinitionBlock ( Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
@@ -1175,8 +1175,8 @@ DefinitionBlock ( Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */
@@ -1184,8 +1184,8 @@ DefinitionBlock ( Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */
@@ -1193,8 +1193,8 @@ DefinitionBlock ( Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */
@@ -1203,8 +1203,8 @@ DefinitionBlock ( Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */
@@ -1396,7 +1396,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1411,7 +1411,7 @@ DefinitionBlock ( Offset (0xF0), APC0, 8, /* APC/PME Event Enable Register */ APC1, 8, /* APC/PME Status Register */ - APC2, 8, /* APC/PME Control Register 1 */ + APC2, 8, /* APC/PME Control Register 1 */ APC3, 8, /* Environment Controller Special Configuration Register */ APC4, 8 /* APC/PME Control Register 2 */ } @@ -1435,7 +1435,7 @@ DefinitionBlock ( * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1577,23 +1577,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1602,7 +1602,7 @@ DefinitionBlock (
/* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 084e2b1..ea5487c 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -106,7 +106,7 @@ void get_bus_conf(void) } }
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 6010eb1..1eee3e6 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -27,12 +27,12 @@ #include <southbridge/amd/sb600/sb600.h>
#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ +#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); + u8 val); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 6a94479..f0280de 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ { device_t dev; u32 dword; @@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v) */ #if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else #define PCI_INT(bus, dev, fn, pin) #endif @@ -147,7 +147,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/technologic/ts5300/cmos.layout b/src/mainboard/technologic/ts5300/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/technologic/ts5300/cmos.layout +++ b/src/mainboard/technologic/ts5300/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/technologic/ts5300/irq_tables.c b/src/mainboard/technologic/ts5300/irq_tables.c index 15dcddd..d4f1fb0 100644 --- a/src/mainboard/technologic/ts5300/irq_tables.c +++ b/src/mainboard/technologic/ts5300/irq_tables.c @@ -9,23 +9,23 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x122e, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x50, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x12<<3)|0x0, {{0x30, 0x8000}, {0x00, 0x0}, {0x00, 0x0}, {0x00, 0x00}}, 0x0, 0x0}, {0x00,(0x14<<3)|0x0, {{0x30, 0x8000}, {0x31, 0x0}, {0x32, 0x0}, {0x33, 0x00}}, 0x0, 0x0}, } }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c index 7a0e2f3..f5c0b75 100644 --- a/src/mainboard/technologic/ts5300/mainboard.c +++ b/src/mainboard/technologic/ts5300/mainboard.c @@ -15,7 +15,7 @@ static void irqdump(void)
int i; int irqlist[] = {0xd00, 0xd02, 0xd03, 0xd04, 0xd08, 0xd0a, - 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, + 0xd14, 0xd18, 0xd1a, 0xd1b, 0xd1c, 0xd20, 0xd21, 0xd22, 0xd28, 0xd29, 0xd30, 0xd31, 0xd32, 0xd33, 0xd40, 0xd41, 0xd42, 0xd43,0xd44, 0xd45, 0xd46, diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 6806187..1519dfe 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -22,10 +22,10 @@ /* PAR register setup */ void setup_pars(void) { - volatile unsigned long *par; - par = (unsigned long *) 0xfffef088; + volatile unsigned long *par; + par = (unsigned long *) 0xfffef088;
- /* NOTE: Ron says, move this to mainboard.c */ + /* NOTE: Ron says, move this to mainboard.c */ *par++ = 0x00000000; *par++ = 0x340f0070; *par++ = 0x380701f0; @@ -147,8 +147,8 @@ static void main(unsigned long bist) for(i = 0; i < 100; i++) ;
- setupsc520(); - console_init(); + setupsc520(); + console_init();
print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/%5Cn"); diff --git a/src/mainboard/televideo/tc7020/devicetree.cb b/src/mainboard/televideo/tc7020/devicetree.cb index d1fa6bd..3602a7b 100644 --- a/src/mainboard/televideo/tc7020/devicetree.cb +++ b/src/mainboard/televideo/tc7020/devicetree.cb @@ -3,43 +3,43 @@ chip northbridge/amd/gx1 # Northbridge device pci 0.0 on end # Host bridge chip southbridge/amd/cs5530 # Southbridge device pci 12.0 on # ISA bridge - chip superio/nsc/pc97317 # Super I/O - device pnp 2e.0 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.1 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.2 on # RTC, Advanced power control (APC) - io 0x60 = 0x70 - irq 0x70 = 8 - end - device pnp 2e.3 off # Floppy (N/A on this board) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.4 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xe0 - end - device pnp 2e.8 on # Power management - io 0x60 = 0xe8 - end - end + chip superio/nsc/pc97317 # Super I/O + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC, Advanced power control (APC) + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy (N/A on this board) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe8 + end + end end device pci 12.1 off end # SMI device pci 12.2 on end # IDE diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index 167ada0..1e3a0d5 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -27,37 +27,37 @@ chip northbridge/intel/i82830 # Northbridge device pci 1d.7 on end # USB2 EHCI Controller device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA/LPC bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # Com2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard/mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.9 off end # Game port - device pnp 2e.a on # PME - io 0x60 = 0x800 - end - device pnp 2e.b off end # MPU-401 - end + chip superio/smsc/smscsuperio # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # Com2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard/mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # Keyboard interrupt + irq 0x72 = 12 # Mouse interrupt + end + device pnp 2e.9 off end # Game port + device pnp 2e.a on # PME + io 0x60 = 0x800 + end + device pnp 2e.b off end # MPU-401 + end end device pci 1f.1 on end # IDE device pci 1f.3 on end # SMBus diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index bcb02bc..9831f24 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -19,7 +19,7 @@ */
#define PME_DEV PNP_DEV(0x2e, 0x0a) -#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ +#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ #define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
/* Early mainboard specific GPIO setup. */ diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c index 767ab75..4641fdb 100644 --- a/src/mainboard/thomson/ip1000/irq_tables.c +++ b/src/mainboard/thomson/ip1000/irq_tables.c @@ -22,18 +22,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x24c0, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x02<<3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */ {0x00,(0x1d<<3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */ {0x00,(0x1f<<3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */ diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 90ba706..fcb7256 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -59,9 +59,9 @@ static void parport_gpios(void) (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on"); printk(BIOS_DEBUG, " orange led: %s\n", (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on"); - printk(BIOS_DEBUG, " red led: %s\n", + printk(BIOS_DEBUG, " red led: %s\n", (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on"); - printk(BIOS_DEBUG, " IR port: %s\n", + printk(BIOS_DEBUG, " IR port: %s\n", (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on"); }
diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h index a92a6cb..5abcaf8 100644 --- a/src/mainboard/thomson/ip1000/spd_table.h +++ b/src/mainboard/thomson/ip1000/spd_table.h @@ -40,11 +40,11 @@ struct spd_entry { * have to be set manually, the onboard memory is located in socket1 (0x51). */ const struct spd_entry spd_table [] = { - {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ - {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ - {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ - {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ + {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */ + {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */ + {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */ + {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */ {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */ - {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ + {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */ {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, DENSITY}, /* Density of each row on module */ }; diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 7029d1c..d7ffc3e 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -112,8 +112,8 @@ config CONSOLE_SERIAL_UART_ADDRESS Map the UART names to the respective MMIO address.
################################################################# -# stuff from smdk5250.h # -# FIXME: can we move some of these to exynos5250's Kconfig? # +# stuff from smdk5250.h # +# FIXME: can we move some of these to exynos5250's Kconfig? # ################################################################# config SYS_I2C_SPEED int diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig index 3139d7d..c8a2156 100644 --- a/src/mainboard/traverse/geos/Kconfig +++ b/src/mainboard/traverse/geos/Kconfig @@ -27,7 +27,7 @@ config IRQ_SLOT_COUNT default 6
config PLLMSRlo - hex - default 0x00de602e + hex + default 0x00de602e
endif # BOARD_TRAVERSE_GEOS diff --git a/src/mainboard/traverse/geos/cmos.layout b/src/mainboard/traverse/geos/cmos.layout index 864d89a..83122ad 100644 --- a/src/mainboard/traverse/geos/cmos.layout +++ b/src/mainboard/traverse/geos/cmos.layout @@ -1,70 +1,70 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 1 e 0 dcon_present +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c index 7431d24..d00e82d 100644 --- a/src/mainboard/traverse/geos/irq_tables.c +++ b/src/mainboard/traverse/geos/irq_tables.c @@ -43,7 +43,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -52,10 +52,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x002B, /* Device */ 0, /* Miniport data */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */ {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */ diff --git a/src/mainboard/tyan/Kconfig b/src/mainboard/tyan/Kconfig index 4a135bd..32306c8 100644 --- a/src/mainboard/tyan/Kconfig +++ b/src/mainboard/tyan/Kconfig @@ -52,7 +52,7 @@ config BOARD_TYAN_S4880 config BOARD_TYAN_S4882 bool "S4882 (Thunder K8QS Pro)" config BOARD_TYAN_S8226 - bool "S8226" + bool "S8226" endchoice
source "src/mainboard/tyan/s1846/Kconfig" diff --git a/src/mainboard/tyan/s1846/devicetree.cb b/src/mainboard/tyan/s1846/devicetree.cb index f774d4f..699de61 100644 --- a/src/mainboard/tyan/s1846/devicetree.cb +++ b/src/mainboard/tyan/s1846/devicetree.cb @@ -9,35 +9,35 @@ chip northbridge/intel/i440bx # Northbridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge - chip superio/nsc/pc87309 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 on # Power management - end - device pnp 2e.5 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.6 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - end + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Power management + end + device pnp 2e.5 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.6 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + end end device pci 7.1 on end # IDE device pci 7.2 on end # USB diff --git a/src/mainboard/tyan/s2735/cmos.layout b/src/mainboard/tyan/s2735/cmos.layout index 608f028..e9279f9 100644 --- a/src/mainboard/tyan/s2735/cmos.layout +++ b/src/mainboard/tyan/s2735/cmos.layout @@ -1,79 +1,79 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 2 hyper_threading -396 1 e 1 thermal_monitoring -397 1 e 1 remap_memory_high -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -#440 4 e 9 slow_cpu -444 1 e 1 nmi -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 2 hyper_threading +396 1 e 1 thermal_monitoring +397 1 e 1 remap_memory_high +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +#440 4 e 9 slow_cpu +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index d3b6b1e..2da3538 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -1,86 +1,86 @@ chip northbridge/intel/e7501 - device domain 0 on + device domain 0 on subsystemid 0x10f1 0x2735 inherit device pci 0.0 on end - device pci 0.1 on end - device pci 2.0 on - chip southbridge/intel/i82870 - device pci 1c.0 on end - device pci 1d.0 on - device pci 1.0 on end # intel lan - device pci 1.1 on end + device pci 0.1 on end + device pci 2.0 on + chip southbridge/intel/i82870 + device pci 1c.0 on end + device pci 1d.0 on + device pci 1.0 on end # intel lan + device pci 1.1 on end end - device pci 1e.0 on end - device pci 1f.0 on end - end + device pci 1e.0 on end + device pci 1f.0 on end + end end - device pci 6.0 on end - chip southbridge/intel/i82801ex - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.7 on end - device pci 1e.0 on - device pci 1.0 on end # intel lan 10/100 - device pci 2.0 on end # ati + device pci 6.0 on end + chip southbridge/intel/i82801ex + device pci 1d.0 on end + device pci 1d.1 on end + device pci 1d.2 on end + device pci 1d.3 on end + device pci 1d.7 on end + device pci 1e.0 on + device pci 1.0 on end # intel lan 10/100 + device pci 2.0 on end # ati end - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end - end - device pci 1f.1 off end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.5 off end - device pci 1f.6 off end + end + device pci 1f.1 off end + device pci 1f.2 on end + device pci 1f.3 on end + device pci 1f.5 off end + device pci 1f.6 off end end # SB - end # PCI domain - device cpu_cluster 0 on - chip cpu/intel/socket_mPGA604 - device lapic 0 on end - end - chip cpu/intel/socket_mPGA604 - device lapic 6 on end - end - end + end # PCI domain + device cpu_cluster 0 on + chip cpu/intel/socket_mPGA604 + device lapic 0 on end + end + chip cpu/intel/socket_mPGA604 + device lapic 6 on end + end + end end
diff --git a/src/mainboard/tyan/s2735/irq_tables.c b/src/mainboard/tyan/s2735/irq_tables.c index 3d69b49..6fd519b 100644 --- a/src/mainboard/tyan/s2735/irq_tables.c +++ b/src/mainboard/tyan/s2735/irq_tables.c @@ -9,18 +9,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x1f<<3)|0x0, /* Where the interrupt router lies (dev) */ 0, /* IRQs devoted exclusively to PCI usage */ 0x8086, /* Vendor */ 0x24d0, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x04,(0x08<<3)|0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x1f<<3)|0x0, {{0x62, 0xdcf8}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, {0x00,(0x1d<<3)|0x0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x6b, 0x0dcf8}}, 0x0, 0x0}, @@ -41,5 +41,5 @@ static const struct irq_routing_table intel_irq_routing_table = {
unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9073728..3f15027 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -7,33 +7,33 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int isa_bus; + struct mp_config_table *mc; + int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { - device_t dev; - struct resource *res; + device_t dev; + struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x09, 0x20, res->base); - } + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x09, 0x20, res->base); + } } dev = dev_find_slot(1, PCI_DEVFN(0x1c,0)); if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, 0x0a, 0x20, res->base); - } + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, 0x0a, 0x20, res->base); + } } } mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); @@ -48,32 +48,32 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x8, 0x17);
//onboard ati - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x8, 0x8, 0x12);
//onboard intel 82551 10/100 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x4, 0x8, 0x11);
// onboard Intel 82547 1000 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x4, 0xa, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x5, 0xa, 0x1);
//Slot 4 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|0, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|1, 0x8, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|2, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x3<<2)|3, 0x8, 0x11); //Slot 3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|0, 0x8, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|1, 0x8, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|2, 0x8, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x4<<2)|3, 0x8, 0x12); //Slot 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|0, 0x9, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|1, 0x9, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|2, 0x9, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x3<<2)|3, 0x9, 0x3); //Slot 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|0, 0x9, 0x4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|1, 0x9, 0x5); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|2, 0x9, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x6<<2)|3, 0x9, 0x7); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 4e71559..d6a9d73 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -19,9 +19,9 @@ // FIXME: There's another hard_reset() in reset.c. Why? static void hard_reset(void) { - /* full reset */ + /* full reset */ outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + outb(0x0e, 0x0cf9); }
static inline int spd_read_byte(unsigned device, unsigned address) @@ -36,19 +36,19 @@ static inline int spd_read_byte(unsigned device, unsigned address) void main(unsigned long bist) { static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, - .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, - }, + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, + .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, + }, };
if (bist == 0) enable_lapic();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist); @@ -69,6 +69,6 @@ void main(unsigned long bist) #endif
#if 1 - dump_pci_device(PCI_DEV(0, 0, 0)); + dump_pci_device(PCI_DEV(0, 0, 0)); #endif } diff --git a/src/mainboard/tyan/s2850/cmos.layout b/src/mainboard/tyan/s2850/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2850/cmos.layout +++ b/src/mainboard/tyan/s2850/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 85c6384..de59d27 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x10f1 0x2850 inherit chip northbridge/amd/amdk8 @@ -17,75 +17,75 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl - device pci b.0 on end + #chip drivers/ati/ragexl + device pci b.0 on end end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end end device pci 1.5 on end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end
device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c index 187981c..539b4d6 100644 --- a/src/mainboard/tyan/s2850/irq_tables.c +++ b/src/mainboard/tyan/s2850/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (2<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (2<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x9b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {1,(2<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, {0x2,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, @@ -36,5 +36,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..7b585cb 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -10,82 +10,82 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8111_1; - unsigned apicid_base; - unsigned apicid_8111; + unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8111_1 = 2; - } - } -/*Bus: Bus ID Type*/ + smp_write_processors(mc); + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8111_1 = 2; + } + } +/*Bus: Bus ID Type*/ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0;
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
@@ -96,59 +96,59 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13);
//On Board AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
//On Board ATI Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x12);
//Onboard Broadcom 5705 NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0d<<2)|0, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0e<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0d<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0e<<2)|0, apicid_8111, 0x10); //Onboard SI Serial ATA - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x11);
//PCI Slot 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|2, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|2, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|3, apicid_8111, 0x13);
//PCI Slot 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, apicid_8111, 0x10);
//PCI Slot 3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, apicid_8111, 0x11);
//PCI Slot 4 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, apicid_8111, 0x12);
//PCI Slot 5 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, apicid_8111, 0x13);
//PCI Slot 6 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, apicid_8111, 0x10);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); + mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
/* Compute the checksums */ diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 5e62f33..c9a5d72 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -26,18 +26,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -70,32 +70,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }, };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_default_resource_map(); + setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/tyan/s2875/cmos.layout b/src/mainboard/tyan/s2875/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2875/cmos.layout +++ b/src/mainboard/tyan/s2875/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index 39eb8b2..f0e5b48 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x10f1 0x2875 inherit chip northbridge/amd/amdk8 @@ -22,7 +22,7 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 5.0 on end + device pci 5.0 on end end device pci 1.0 on chip superio/winbond/w83627hf @@ -71,8 +71,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on end device pci 1.5 on end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
diff --git a/src/mainboard/tyan/s2875/irq_tables.c b/src/mainboard/tyan/s2875/irq_tables.c index af8c385..ce16a35 100644 --- a/src/mainboard/tyan/s2875/irq_tables.c +++ b/src/mainboard/tyan/s2875/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (5<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (5<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xcf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0xcf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {1,(5<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, {0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, @@ -37,5 +37,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..d2179f1 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -10,89 +10,89 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8111_1; + unsigned char bus_8111_1; unsigned char bus_8151_1; - unsigned apicid_base; - unsigned apicid_8111; + unsigned apicid_base; + unsigned apicid_8111;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
- { - device_t dev; + { + device_t dev;
- /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + }
- /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
- bus_8111_1 = 3; - } - /* 8151 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); + bus_8111_1 = 3; + } + /* 8151 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1);
- } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
- bus_8151_1 = 2; - } + bus_8151_1 = 2; + }
- } + }
/*Bus: Bus ID Type*/ mptable_write_buses(mc, NULL, &bus_isa); @@ -101,20 +101,20 @@ static void *smp_write_config_table(void *v) #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; + apicid_8111 = apicid_base+0; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio ??? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (5<<2)|1, apicid_8111, 0x11); // Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
// AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); @@ -122,45 +122,45 @@ static void *smp_write_config_table(void *v) // Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x13); //Onboard Firewire - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11); //Onboard Broadcom NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, apicid_8111, 0x12);
//Onboard VIA USB 1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|1, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|2, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|2, apicid_8111, 0x13);
//Slot 1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, apicid_8111, 0x10); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, apicid_8111, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, apicid_8111, 0x10); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, apicid_8111, 0x11); //
//Slot 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, apicid_8111, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, apicid_8111, 0x13); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, apicid_8111, 0x10); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, apicid_8111, 0x10); //
//Slot 3 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, apicid_8111, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, apicid_8111, 0x13); //
//Slot 4 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, apicid_8111, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, apicid_8111, 0x11); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, apicid_8111, 0x11); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, apicid_8111, 0x12); //
//Slot 5 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13); //
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index d35c65a..7170ebc 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -26,18 +26,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -81,30 +81,30 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_default_resource_map(); + setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/tyan/s2880/cmos.layout b/src/mainboard/tyan/s2880/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2880/cmos.layout +++ b/src/mainboard/tyan/s2880/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index f9f4856..fb889f9 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x10f1 0x2880 inherit chip northbridge/amd/amdk8 @@ -12,13 +12,13 @@ chip northbridge/amd/amdk8/root_complex chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - device pci 9.0 on end #broadcom + device pci 9.0 on end #broadcom device pci 9.1 on end -# chip drivers/lsi/53c1030 -# device pci a.0 on end -# device pci a.1 on end -# register "fw_address" = "0xfff8c000" -# end +# chip drivers/lsi/53c1030 +# device pci a.0 on end +# device pci a.1 on end +# register "fw_address" = "0xfff8c000" +# end end device pci 0.1 on end device pci 1.0 on end @@ -32,49 +32,49 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 5.0 on end #some sata - device pci 6.0 on end #adti + device pci 5.0 on end #some sata + device pci 6.0 on end #adti end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end @@ -82,13 +82,13 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
- device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end
device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c index d0c0d18..a9706c8 100644 --- a/src/mainboard/tyan/s2880/irq_tables.c +++ b/src/mainboard/tyan/s2880/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x59, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x59, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..b19b4fd 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -10,132 +10,132 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - unsigned apicid_base; - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - -/*Bus: Bus ID Type*/ + smp_write_processors(mc); + + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + + bus_8111_1 = 4; + } + /* 8131-1 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8131_1 = 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_8131_2 = 3; + } + } + +/*Bus: Bus ID Type*/ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); - { - - device_t dev; - struct resource *res; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } - } + { + + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + }
}
@@ -153,18 +153,18 @@ static void *smp_write_config_table(void *v)
//Slot 5 PCI 32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
//On Board Promise Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, apicid_8131_1, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, apicid_8131_1, 0x2);//
//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, apicid_8131_1, 0x2); @@ -179,16 +179,16 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|1, apicid_8131_1, 0x1);
//Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
//Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, apicid_8131_2, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, apicid_8131_2, 0x0);//
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 5f30796..adc69e4 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -26,18 +26,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -81,31 +81,31 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_default_resource_map(); + setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/tyan/s2881/cmos.layout b/src/mainboard/tyan/s2881/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2881/cmos.layout +++ b/src/mainboard/tyan/s2881/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index aab75a3..3e6bd90 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -10,116 +10,116 @@ chip northbridge/amd/amdk8/root_complex device pci 18.0 on end # link 0 device pci 18.0 on end # link 1 device pci 18.0 on # link 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - device pci a.0 on end # Adaptic - device pci a.1 on end - end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - device pci 5.0 on end # SiI - device pci 6.0 on end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - chip drivers/i2c/adt7463 # CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 - device i2c 2d on end - end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN - device i2c 2a on end - end - chip drivers/generic/generic # Winbond HWM 0x92 - device i2c 49 on end - end - chip drivers/generic/generic # Winbond HWM 0x94 - device i2c 4a on end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + device pci a.0 on end # Adaptic + device pci a.1 on end + end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + device pci 5.0 on end # SiI + device pci 6.0 on end + end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + chip drivers/i2c/adt7463 # CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3 + device i2c 2d on end + end + chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN + device i2c 2a on end + end + chip drivers/generic/generic # Winbond HWM 0x92 + device i2c 49 on end + end + chip drivers/generic/generic # Winbond HWM 0x94 + device i2c 4a on end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 332e578..e279f26 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -24,24 +24,24 @@ unsigned apicid_8131_2; unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -81,8 +81,8 @@ void get_bus_conf(void) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:03.0, using defaults\n", - bus_8111_0); + "ERROR - could not find PCI %02x:03.0, using defaults\n", + bus_8111_0); }
/* 8131-1 */ @@ -91,8 +91,8 @@ void get_bus_conf(void) bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); }
/* 8132-2 */ @@ -101,8 +101,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); }
/*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/tyan/s2881/irq_tables.c b/src/mainboard/tyan/s2881/irq_tables.c index b53a992..1de8fd8 100644 --- a/src/mainboard/tyan/s2881/irq_tables.c +++ b/src/mainboard/tyan/s2881/irq_tables.c @@ -16,18 +16,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; }
extern unsigned char bus_8131_0; @@ -48,17 +48,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -84,21 +84,21 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++;
- pirq_info++; slot_num++; + pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 7df5e87..5789782 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -19,14 +19,14 @@ extern unsigned sbdn3;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
@@ -34,23 +34,23 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } - } + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + }
}
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //8111 LPC ???? - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
//On Board AMD USB ??? smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); @@ -70,26 +70,26 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
//Slot 3 PCIX 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27 + }
//On Board NIC and adaptec scsi - for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24 - } + for(i=0;i<2;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24 + }
//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28 - } - - //Slot 1 PCI-X 133/100/66, Side 2 on raiser card - //Fix ME, IRQ Pins? - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28 + } + + //Slot 1 PCI-X 133/100/66, Side 2 on raiser card + //Fix ME, IRQ Pins? + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28 + }
diff --git a/src/mainboard/tyan/s2881/resourcemap.c b/src/mainboard/tyan/s2881/resourcemap.c index 23ab936..7212655 100644 --- a/src/mainboard/tyan/s2881/resourcemap.c +++ b/src/mainboard/tyan/s2881/resourcemap.c @@ -201,11 +201,11 @@ static void setup_s2881_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index 404c2df..7970f95 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -25,18 +25,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -66,41 +66,41 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8];
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx);
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_s2881_resource_map(); + setup_s2881_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); @@ -109,14 +109,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) dump_smbus_registers(); #endif
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
- memreset_setup(); - sdram_initialize(nodes, ctrl); + memreset_setup(); + sdram_initialize(nodes, ctrl);
#if 0 dump_pci_devices(); diff --git a/src/mainboard/tyan/s2882/cmos.layout b/src/mainboard/tyan/s2882/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2882/cmos.layout +++ b/src/mainboard/tyan/s2882/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index 4074695..96a5cca 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end
device domain 0 on subsystemid 0x10f1 0x2882 inherit @@ -13,10 +13,10 @@ chip northbridge/amd/amdk8/root_complex chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - device pci 6.0 on end # adaptec - device pci 6.1 on end - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end + device pci 6.0 on end # adaptec + device pci 6.1 on end + device pci 9.0 on end # broadcom 5704 + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -30,52 +30,52 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 5.0 on end - # chip drivers/ati/ragexl - device pci 6.0 on end - # end - device pci 8.0 on end #intel 10/100 + device pci 5.0 on end + # chip drivers/ati/ragexl + device pci 6.0 on end + # end + device pci 8.0 on end #intel 10/100 end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end @@ -106,7 +106,7 @@ chip northbridge/amd/amdk8/root_complex # chip drivers/generic/generic #dimm 1-1-1 # device i2c 57 on end # end - end # acpi + end # acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" @@ -114,8 +114,8 @@ chip northbridge/amd/amdk8/root_complex end end # device pci 18.0
- device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end
device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index 2e12291..0448465 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -11,87 +11,87 @@ #include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x746b, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xff, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu re (including checksum) */ - { - {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, - {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, - {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, - {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, - {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, - {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, - {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, - {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0}, - {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, - {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0}, - {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0}, - } + { + {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, + {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0}, + {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0}, + {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0}, + {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0}, + {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0}, + {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0}, + {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0}, + } };
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; }
unsigned long write_pirq_routing_table(unsigned long addr) @@ -102,63 +102,63 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; - - unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...\n", addr); + uint8_t sum=0; + int i; + + unsigned char bus_chain_0; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + + bus_8111_1 = 4; + } + /* 8131-1 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8131_1 = 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_8131_2 = 3; + } + } + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...\n", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -181,120 +181,120 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0;
- { - device_t dev; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ5 - PINTB = IRQ9 - PINTC = IRQ11 - PINTD = IRQ10 - */ - pci_write_config16(dev, 0x56, 0xab95); - } - } - - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); - write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + { + device_t dev; + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3)); + if (dev) { + /* initialize PCI interupts - these assignments depend + on the PCB routing of PINTA-D + + PINTA = IRQ5 + PINTB = IRQ9 + PINTC = IRQ11 + PINTD = IRQ10 + */ + pci_write_config16(dev, 0x56, 0xab95); + } + } + + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; + pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); + write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; - pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); - write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); + printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; + pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); + write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard ATI Display Adapter\n"); - static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6); - write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + printk(BIOS_DEBUG, "setting Onboard ATI Display Adapter\n"); + static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 }; + pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6); + write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 1\n"); - static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3); - write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0); + printk(BIOS_DEBUG, "setting Slot 1\n"); + static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 }; + pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3); + write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 2\n"); - static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 }; - pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1); - write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0); + printk(BIOS_DEBUG, "setting Slot 2\n"); + static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 }; + pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1); + write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 3\n"); - static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 }; - pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3); - write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0); + printk(BIOS_DEBUG, "setting Slot 3\n"); + static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 }; + pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3); + write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 4\n"); - static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 }; - pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2); - write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0); + printk(BIOS_DEBUG, "setting Slot 4\n"); + static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 }; + pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2); + write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Slot 5 \n"); - static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); - write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0); + printk(BIOS_DEBUG, "setting Slot 5 \n"); + static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; + pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); + write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard SI Serial ATA\n"); - static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5); - write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + printk(BIOS_DEBUG, "setting Onboard SI Serial ATA\n"); + static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 }; + pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5); + write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard Intel NIC\n"); - static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8); - write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); + printk(BIOS_DEBUG, "setting Onboard Intel NIC\n"); + static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 }; + pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8); + write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++;
- printk(BIOS_DEBUG, "setting Onboard Adaptec SCSI\n"); - static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6); - write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); + printk(BIOS_DEBUG, "setting Onboard Adaptec SCSI\n"); + static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 }; + pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6); + write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; #if 0 //?? - write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0); + write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0); pirq_info++; slot_num++; #endif
- printk(BIOS_DEBUG, "setting Onboard Broadcom NIC\n"); - static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9); - write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); + printk(BIOS_DEBUG, "setting Onboard Broadcom NIC\n"); + static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 }; + pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9); + write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); pirq_info++; slot_num++; #if 0 //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0); + write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0); pirq_info++; slot_num++; #endif
#if 0 //?? what's this? - write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); + write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0); pirq_info++; slot_num++; #endif
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..4d72301 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -11,129 +11,129 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - unsigned apicid_base; - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 0); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } + smp_write_processors(mc); + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + + bus_8111_1 = 4; + } + /* 8131-1 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8131_1 = 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_8131_2 = 3; + } + } mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2;
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } - } + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + }
}
@@ -144,66 +144,66 @@ static void *smp_write_config_table(void *v)
//On Board AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
//On Board ATI Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
#if 1 //Slot 5 PCI 32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
#endif //Onboard SI Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
//Onboard Intel 82551 10/100M NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
#if 1 //Slot 3 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
//Slot 4 PCIX 100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
#endif //Onboard adaptec scsi smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
//On Board NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
#if 1 //Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
//Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
#endif /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - mptable_lintsrc(mc, bus_isa); + mptable_lintsrc(mc, bus_isa); /* There is no extension information... */
/* Compute the checksums */ diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 5f30796..adc69e4 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -26,18 +26,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -81,31 +81,31 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_default_resource_map(); + setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif - // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + // automatically set that for you, but you might meet tight space + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/tyan/s2885/cmos.layout b/src/mainboard/tyan/s2885/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2885/cmos.layout +++ b/src/mainboard/tyan/s2885/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index acc5085..8b2a40f 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x10f1 0x2885 inherit chip northbridge/amd/amdk8 @@ -20,7 +20,7 @@ chip northbridge/amd/amdk8/root_complex chip southbridge/amd/amd8131 # the on/off keyword is mandatory device pci 0.0 on - device pci 9.0 on end # broadcom 5703 + device pci 9.0 on end # broadcom 5703 end device pci 0.1 on end device pci 1.0 on end @@ -34,82 +34,82 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci b.0 on end # SiI 3114 + device pci b.0 on end # SiI 3114 end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR + device pnp 2e.6 off # CIR io 0x60 = 0x100 end - device pnp 2e.7 off # GAME_MIDI_GIPO1 + device pnp 2e.7 off # GAME_MIDI_GIPO1 io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5 - end + end end end device pci 1.1 on end device pci 1.2 on end device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end end # acpi device pci 1.5 on end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
@@ -120,13 +120,13 @@ chip northbridge/amd/amdk8/root_complex
end #domain
-# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end +# chip drivers/generic/debug +# device pnp 0.0 off end +# device pnp 0.1 off end +# device pnp 0.2 off end +# device pnp 0.3 off end # device pnp 0.4 off end # device pnp 0.5 on end -# end +# end end
diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 88706c0..b3d4183 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -27,23 +27,23 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -85,8 +85,8 @@ void get_bus_conf(void) bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:03.0, using defaults\n", - bus_8111_0); + "ERROR - could not find PCI %02x:03.0, using defaults\n", + bus_8111_0); }
/* 8131-1 */ @@ -95,8 +95,8 @@ void get_bus_conf(void) bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0); }
/* 8132-2 */ @@ -105,8 +105,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0); }
/* HT chain 1 */ @@ -117,7 +117,7 @@ void get_bus_conf(void)
if (dev) { bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -// printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); +// printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1); }
/*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index b272fda..a199f2f 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -16,18 +16,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; }
extern unsigned char bus_8131_0; @@ -51,17 +51,17 @@ unsigned long write_pirq_routing_table(unsigned long addr) unsigned slot_num; uint8_t *v;
- uint8_t sum=0; - int i; + uint8_t sum=0; + int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
- /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -87,23 +87,23 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); -// pirq_info++; slot_num++; +// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// pirq_info++; slot_num++; //agp bridge - write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, bus_8151_0, (sbdn5<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++; + pirq_info++; slot_num++;
pirq->size = 32 + 16 * slot_num;
- for (i = 0; i < pirq->size; i++) - sum += v[i]; + for (i = 0; i < pirq->size; i++) + sum += v[i];
sum = pirq->checksum - sum;
- if (sum != pirq->checksum) { - pirq->checksum = sum; - } + if (sum != pirq->checksum) { + pirq->checksum = sum; + }
printk(BIOS_INFO, "done.\n");
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 26081c7..5a83c3c 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -22,14 +22,14 @@ extern unsigned sbdn5;
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; + struct mp_config_table *mc; int i, bus_isa;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); + smp_write_processors(mc);
get_bus_conf();
@@ -37,34 +37,34 @@ static void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 - { - device_t dev; + { + device_t dev; struct resource *res; - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); - if (dev) { + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } - } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); - if (dev) { + } + dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); } - } + } }
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //??? What - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|3, apicid_8111, 0x13); //Onboard AMD AC97 Audio - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|1, apicid_8111, 0x11); // Onboard AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
// AGP Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10); @@ -72,38 +72,38 @@ static void *smp_write_config_table(void *v) //Onboard Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, apicid_8111, 0x11); //Onboard Firewire - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, apicid_8111, 0x13); //Onboard Broadcom NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
//Slot 5 PCI 32 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|i, apicid_8111, 0x10 + (0+i)%4); //16 + }
//Slot 3 PCIX 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27 + }
//Slot 4 PCIX 100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|i, apicid_8131_1, (2+i)%4); //26 + }
//Slot 1 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28 + }
//Slot 2 PCI-X 133/100/66 - for(i=0;i<4;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29 - } + for(i=0;i<4;i++) { + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (1+i)%4); //29 + }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/tyan/s2885/resourcemap.c b/src/mainboard/tyan/s2885/resourcemap.c index af0ccab..394ba52 100644 --- a/src/mainboard/tyan/s2885/resourcemap.c +++ b/src/mainboard/tyan/s2885/resourcemap.c @@ -17,21 +17,21 @@ static void setup_s2885_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -51,25 +51,25 @@ static void setup_s2885_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -90,27 +90,27 @@ static void setup_s2885_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -131,21 +131,21 @@ static void setup_s2885_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -162,23 +162,23 @@ static void setup_s2885_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, @@ -192,23 +192,23 @@ static void setup_s2885_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -222,35 +222,35 @@ static void setup_s2885_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration regin i + * This field defines the highest bus number in configuration regin i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link2 of CPU 0 // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x08070003, // AMD 8151 on link0 of CPU 0 diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 00dff67..c9ee97b 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -25,18 +25,18 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
@@ -66,53 +66,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif };
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8];
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_s2885_resource_map(); + setup_s2885_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
- needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
- enable_smbus(); + enable_smbus();
- memreset_setup(); - sdram_initialize(nodes, ctrl); + memreset_setup(); + sdram_initialize(nodes, ctrl);
#if 0 dump_pci_devices(); diff --git a/src/mainboard/tyan/s2891/acpi_tables.c b/src/mainboard/tyan/s2891/acpi_tables.c index 42d9152..0776325 100644 --- a/src/mainboard/tyan/s2891/acpi_tables.c +++ b/src/mainboard/tyan/s2891/acpi_tables.c @@ -45,7 +45,7 @@ unsigned long acpi_fill_madt(unsigned long current) ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - res->base, 0); + res->base, 0); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) pci_write_config32(dev, 0x7c, 0x0120d218); @@ -58,14 +58,14 @@ unsigned long acpi_fill_madt(unsigned long current) if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); + apic_addr, 0x18); }
dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); + apic_addr, 0x1C); }
/* IRQ9 */ diff --git a/src/mainboard/tyan/s2891/cmos.layout b/src/mainboard/tyan/s2891/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2891/cmos.layout +++ b/src/mainboard/tyan/s2891/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2891/devicetree.cb b/src/mainboard/tyan/s2891/devicetree.cb index 3d8c65e..5348937 100644 --- a/src/mainboard/tyan/s2891/devicetree.cb +++ b/src/mainboard/tyan/s2891/devicetree.cb @@ -8,126 +8,126 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x10f1 0x2891 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # Consumer IR - io 0x60 = 0x100 - end - device pnp 2e.7 off # Game port, MIDI, GPIO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end - end - # device pci 1.1 on # SM 1 - # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - # device i2c 2d on end - # end - # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - # device i2c 2e on end - # end - # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - # device i2c 2a on end - # end - # chip drivers/generic/generic # Winbond HWM 0x92 - # device i2c 49 on end - # end - # chip drivers/generic/generic # Winbond HWM 0x94 - # device i2c 4a on end - # end - # end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 7.0 on end - end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 7.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end - device pci 9.1 on end - end - device pci 1.1 on end - end + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end + device pci 9.1 on end + end + device pci 1.1 on end + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index e94c608..82d7837 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -31,22 +31,22 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO 0x0000000, 0x0000200, 0x0000100, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -91,8 +91,8 @@ void get_bus_conf(void) bus_ck804_4++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_4 = 3; @@ -105,8 +105,8 @@ void get_bus_conf(void) bus_ck804_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0d); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4 + 1; } @@ -116,8 +116,8 @@ void get_bus_conf(void) bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0e); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; @@ -129,8 +129,8 @@ void get_bus_conf(void) bus_8131_2++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0);
bus_8131_1 = bus_8131_0 + 1; bus_8131_2 = bus_8131_0 + 2; @@ -141,8 +141,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0);
bus_8131_2 = bus_8131_1 + 1; } diff --git a/src/mainboard/tyan/s2891/resourcemap.c b/src/mainboard/tyan/s2891/resourcemap.c index d76f1d6..b40a938 100644 --- a/src/mainboard/tyan/s2891/resourcemap.c +++ b/src/mainboard/tyan/s2891/resourcemap.c @@ -17,21 +17,21 @@ static void setup_s2891_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -51,25 +51,25 @@ static void setup_s2891_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -90,27 +90,27 @@ static void setup_s2891_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -131,21 +131,21 @@ static void setup_s2891_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -162,23 +162,23 @@ static void setup_s2891_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -192,23 +192,23 @@ static void setup_s2891_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -222,35 +222,35 @@ static void setup_s2891_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ diff --git a/src/mainboard/tyan/s2892/acpi_tables.c b/src/mainboard/tyan/s2892/acpi_tables.c index 42d9152..0776325 100644 --- a/src/mainboard/tyan/s2892/acpi_tables.c +++ b/src/mainboard/tyan/s2892/acpi_tables.c @@ -45,7 +45,7 @@ unsigned long acpi_fill_madt(unsigned long current) ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - res->base, 0); + res->base, 0); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) pci_write_config32(dev, 0x7c, 0x0120d218); @@ -58,14 +58,14 @@ unsigned long acpi_fill_madt(unsigned long current) if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); + apic_addr, 0x18); }
dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); + apic_addr, 0x1C); }
/* IRQ9 */ diff --git a/src/mainboard/tyan/s2892/cmos.layout b/src/mainboard/tyan/s2892/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2892/cmos.layout +++ b/src/mainboard/tyan/s2892/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2892/devicetree.cb b/src/mainboard/tyan/s2892/devicetree.cb index af29be1..dbdd0ed 100644 --- a/src/mainboard/tyan/s2892/devicetree.cb +++ b/src/mainboard/tyan/s2892/devicetree.cb @@ -8,129 +8,129 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x10f1 0x2892 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # Consumer IR - io 0x60 = 0x100 - end - device pnp 2e.7 off # Game port, MIDI, GPIO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - device i2c 2d on end - end - chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - device i2c 2e on end - end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - device i2c 2a on end - end - chip drivers/generic/generic # Winbond HWM 0x92 - device i2c 49 on end - end - chip drivers/generic/generic # Winbond HWM 0x94 - device i2c 4a on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 6.0 on end - # end - device pci 8.0 on end - end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + device i2c 2d on end + end + chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + device i2c 2e on end + end + chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + device i2c 2a on end + end + chip drivers/generic/generic # Winbond HWM 0x92 + device i2c 49 on end + end + chip drivers/generic/generic # Winbond HWM 0x94 + device i2c 4a on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 6.0 on end + # end + device pci 8.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end # Broadcom 5704 - device pci 9.1 on end - end - device pci 1.1 on end - end + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + end + device pci 1.1 on end + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 0ead854..b08de4a 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -29,23 +29,23 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -89,8 +89,8 @@ void get_bus_conf(void) bus_ck804_4++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_4 = 3; @@ -103,8 +103,8 @@ void get_bus_conf(void) bus_ck804_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0d); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4 + 1; } @@ -114,8 +114,8 @@ void get_bus_conf(void) bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0e); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; @@ -127,8 +127,8 @@ void get_bus_conf(void) bus_8131_2++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0);
bus_8131_1 = bus_8131_0 + 1; bus_8131_2 = bus_8131_0 + 2; @@ -139,8 +139,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0);
bus_8131_2 = bus_8131_1 + 1; } diff --git a/src/mainboard/tyan/s2892/resourcemap.c b/src/mainboard/tyan/s2892/resourcemap.c index 61bead2..3580a73 100644 --- a/src/mainboard/tyan/s2892/resourcemap.c +++ b/src/mainboard/tyan/s2892/resourcemap.c @@ -201,11 +201,11 @@ static void setup_mb_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/tyan/s2895/acpi_tables.c b/src/mainboard/tyan/s2895/acpi_tables.c index 1974171..e4a5e76 100644 --- a/src/mainboard/tyan/s2895/acpi_tables.c +++ b/src/mainboard/tyan/s2895/acpi_tables.c @@ -45,7 +45,7 @@ unsigned long acpi_fill_madt(unsigned long current) ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - res->base, 0); + res->base, 0); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) pci_write_config32(dev, 0x7c, 0x0120d218); @@ -58,14 +58,14 @@ unsigned long acpi_fill_madt(unsigned long current) if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5, - apic_addr, 0x18); + apic_addr, 0x18); }
dev = dev_find_slot(0x40, PCI_DEVFN(0x1, 1)); if (dev) { apic_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6, - apic_addr, 0x1C); + apic_addr, 0x1C); }
/* Write second NVIDIA CK804 IOAPIC. */ @@ -76,7 +76,7 @@ unsigned long acpi_fill_madt(unsigned long current) ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 7, - res->base, 0x20); + res->base, 0x20); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) pci_write_config32(dev, 0x7c, 0x0000d218); // Why does the factory BIOS have 0? diff --git a/src/mainboard/tyan/s2895/cmos.layout b/src/mainboard/tyan/s2895/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s2895/cmos.layout +++ b/src/mainboard/tyan/s2895/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb index f830505..b0eb924 100644 --- a/src/mainboard/tyan/s2895/devicetree.cb +++ b/src/mainboard/tyan/s2895/devicetree.cb @@ -8,112 +8,112 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x10f1 0x2895 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47b397 # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.8 on # Hardware monitor - io 0x60 = 0x480 - chip drivers/generic/generic # LM95221 CPU temp - device i2c 2b on end - end - chip drivers/generic/generic # EMCT03 - device i2c 54 on end - end - end - device pnp 2e.a on # RT - io 0x60 = 0x400 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47b397 # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.8 on # Hardware monitor + io 0x60 = 0x480 + chip drivers/generic/generic # LM95221 CPU temp + device i2c 2b on end + end + chip drivers/generic/generic # EMCT03 + device i2c 54 on end + end + end + device pnp 2e.a on # RT + io 0x60 = 0x400 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/amd/amd8131 # Southbridge - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 6.0 on end # LSI SCSI - device pci 6.1 on end - end - device pci 1.1 on end - end + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 6.0 on end # LSI SCSI + device pci 6.1 on end + end + device pci 1.1 on end + end end device pci 18.1 on end device pci 18.2 on end @@ -121,27 +121,27 @@ chip northbridge/amd/amdk8/root_complex # Root complex end chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 19.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 19.0 on end device pci 19.0 on end diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 11b1bc2..d91f211 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -37,22 +37,22 @@ unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO 0x0000ff0, 0x0000ff0, 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0, -// 0x0000ff0 +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0, +// 0x0000ff0 };
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, -// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, +// 0x20202020, };
unsigned sbdn3; @@ -99,8 +99,8 @@ void get_bus_conf(void) bus_ck804_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_5 = 3; @@ -111,8 +111,8 @@ void get_bus_conf(void) bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0e); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; @@ -124,8 +124,8 @@ void get_bus_conf(void) bus_8131_2++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:01.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:01.0, using defaults\n", + bus_8131_0);
bus_8131_1 = bus_8131_0 + 1; bus_8131_2 = bus_8131_0 + 2; @@ -136,8 +136,8 @@ void get_bus_conf(void) bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:02.0, using defaults\n", - bus_8131_0); + "ERROR - could not find PCI %02x:02.0, using defaults\n", + bus_8131_0);
bus_8131_2 = bus_8131_1 + 1; } @@ -152,8 +152,8 @@ void get_bus_conf(void) bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI %02x:%02x.0, using defaults\n", - bus_ck804b_0, sbdnb + 0x0e); + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_ck804b_0, sbdnb + 0x0e); bus_ck804b_5 = bus_ck804b_4 + 1; } } diff --git a/src/mainboard/tyan/s2895/resourcemap.c b/src/mainboard/tyan/s2895/resourcemap.c index 8d20883..a3ababb 100644 --- a/src/mainboard/tyan/s2895/resourcemap.c +++ b/src/mainboard/tyan/s2895/resourcemap.c @@ -201,11 +201,11 @@ static void setup_mb_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 725dd3f..30ebe06 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -59,7 +59,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
diff --git a/src/mainboard/tyan/s2912/cmos.layout b/src/mainboard/tyan/s2912/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/tyan/s2912/cmos.layout +++ b/src/mainboard/tyan/s2912/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb index 57815de..803df0d 100644 --- a/src/mainboard/tyan/s2912/devicetree.cb +++ b/src/mainboard/tyan/s2912/devicetree.cb @@ -10,125 +10,125 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..f8ab32a 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 diff --git a/src/mainboard/tyan/s2912/resourcemap.c b/src/mainboard/tyan/s2912/resourcemap.c index b06aaf3..8bf2b58 100644 --- a/src/mainboard/tyan/s2912/resourcemap.c +++ b/src/mainboard/tyan/s2912/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index a8cec16..6cc4222 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,95 +22,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 200Mhz -8 1 166Mhz -8 2 133Mhz -8 3 100Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 0a5475f..168dee0 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -10,127 +10,127 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.0 on end device pci 18.0 on end device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 4.0 on end - end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 4.0 on end + end + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end end device pci 18.1 on end device pci 18.2 on end diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..8d0f8f8 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
- /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 diff --git a/src/mainboard/tyan/s2912_fam10/resourcemap.c b/src/mainboard/tyan/s2912_fam10/resourcemap.c index 044c674..7389246 100644 --- a/src/mainboard/tyan/s2912_fam10/resourcemap.c +++ b/src/mainboard/tyan/s2912_fam10/resourcemap.c @@ -33,21 +33,21 @@ static void setup_mb_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with interleave enable. + * specifies the values of A[14:12] to use with interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit address - * that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -68,25 +68,25 @@ static void setup_mb_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit address - * that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -107,27 +107,27 @@ static void setup_mb_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit address that - * defines the end of a memory-mapped I/O region n + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,21 +148,21 @@ static void setup_mb_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address - * that defines the start of memory-mapped I/O region i + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -179,23 +179,23 @@ static void setup_mb_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00007000, @@ -209,23 +209,23 @@ static void setup_mb_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -239,35 +239,35 @@ static void setup_mb_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in configuration region i + * This field defines the lowest bus number in configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in configuration region i + * This field defines the highest bus number in configuration region i */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 1e439d4..6ada583 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -253,8 +253,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain + * @param[in] u8 node = The node on which this chain is located + * @param[in] u8 link = The link on the host for this chain * @param[out] u8** list = supply a pointer to a list * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically diff --git a/src/mainboard/tyan/s4880/cmos.layout b/src/mainboard/tyan/s4880/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s4880/cmos.layout +++ b/src/mainboard/tyan/s4880/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index da59eb5..6e950b6 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end
device domain 0 on subsystemid 0x10f1 0x4880 inherit @@ -14,14 +14,14 @@ chip northbridge/amd/amdk8/root_complex # devices on link 2, link 2 == LDT 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on -# chip drivers/lsi/53c1030 -# device pci 4.0 on end -# device pci 4.1 on end -# register "fw_address" = "0xfff8c000" -# end - device pci 9.0 on end - device pci 9.1 on end + device pci 0.0 on +# chip drivers/lsi/53c1030 +# device pci 4.0 on end +# device pci 4.1 on end +# register "fw_address" = "0xfff8c000" +# end + device pci 9.0 on end + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -35,48 +35,48 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - device pci 6.0 on end + device pci 6.0 on end end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end @@ -84,8 +84,8 @@ chip northbridge/amd/amdk8/root_complex device pci 1.3 on end device pci 1.5 off end device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide0_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
diff --git a/src/mainboard/tyan/s4880/irq_tables.c b/src/mainboard/tyan/s4880/irq_tables.c index defe03b..49f8ba9 100644 --- a/src/mainboard/tyan/s4880/irq_tables.c +++ b/src/mainboard/tyan/s4880/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x7400, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x7400, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, {1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, @@ -46,5 +46,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..7cd11d9 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -10,132 +10,132 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - unsigned apicid_base; - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 2); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - -/*Bus: Bus ID Type*/ + smp_write_processors(mc); + + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 2); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + + bus_8111_1 = 4; + } + /* 8131-1 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8131_1 = 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_8131_2 = 3; + } + } + +/*Bus: Bus ID Type*/ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2;
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } - } + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + }
}
@@ -149,9 +149,9 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
//On Board Via USB 1.1 and 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2
//Slot 5 PCI 32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); @@ -163,14 +163,14 @@ static void *smp_write_config_table(void *v) //On Board SI Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13); //On Board ATI Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); @@ -179,22 +179,22 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
//On Board LSI scsi and NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
//Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
//Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/tyan/s4880/resourcemap.c b/src/mainboard/tyan/s4880/resourcemap.c index 5fa8578..91e23f3 100644 --- a/src/mainboard/tyan/s4880/resourcemap.c +++ b/src/mainboard/tyan/s4880/resourcemap.c @@ -201,11 +201,11 @@ static void setup_s4880_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 23efa10..f9c7a39 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -25,39 +25,39 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - unsigned device=(ctrl->channel0[0])>>8; - smbus_write_byte(SMBUS_HUB, 0x01, device); - smbus_write_byte(SMBUS_HUB, 0x03, 0); + unsigned device=(ctrl->channel0[0])>>8; + smbus_write_byte(SMBUS_HUB, 0x01, device); + smbus_write_byte(SMBUS_HUB, 0x03, 0); }
#if 0 static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 - int ret; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); + int ret; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif
@@ -83,76 +83,76 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const struct mem_controller cpu[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, - .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, - }, + { + .node_id = 0, + .f0 = PCI_DEV(0, 0x18, 0), + .f1 = PCI_DEV(0, 0x18, 1), + .f2 = PCI_DEV(0, 0x18, 2), + .f3 = PCI_DEV(0, 0x18, 3), + .channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 }, + .channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 }, + }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, - .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, - - }, + { + .node_id = 1, + .f0 = PCI_DEV(0, 0x19, 0), + .f1 = PCI_DEV(0, 0x19, 1), + .f2 = PCI_DEV(0, 0x19, 2), + .f3 = PCI_DEV(0, 0x19, 3), + .channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 }, + .channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 }, + + }, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - { - .node_id = 2, - .f0 = PCI_DEV(0, 0x1a, 0), - .f1 = PCI_DEV(0, 0x1a, 1), - .f2 = PCI_DEV(0, 0x1a, 2), - .f3 = PCI_DEV(0, 0x1a, 3), - .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, - .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, - - }, - { - .node_id = 3, - .f0 = PCI_DEV(0, 0x1b, 0), - .f1 = PCI_DEV(0, 0x1b, 1), - .f2 = PCI_DEV(0, 0x1b, 2), - .f3 = PCI_DEV(0, 0x1b, 3), - .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, - .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, - - }, + { + .node_id = 2, + .f0 = PCI_DEV(0, 0x1a, 0), + .f1 = PCI_DEV(0, 0x1a, 1), + .f2 = PCI_DEV(0, 0x1a, 2), + .f3 = PCI_DEV(0, 0x1a, 3), + .channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 }, + .channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 }, + + }, + { + .node_id = 3, + .f0 = PCI_DEV(0, 0x1b, 0), + .f1 = PCI_DEV(0, 0x1b, 1), + .f2 = PCI_DEV(0, 0x1b, 2), + .f3 = PCI_DEV(0, 0x1b, 3), + .channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 }, + .channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 }, + + }, #endif };
- int needs_reset; + int needs_reset;
- if (bist == 0) + if (bist == 0) init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_s4880_resource_map(); + setup_s4880_resource_map();
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); + // It is said that we should start core1 after all core0 launched + start_other_cores(); #endif // automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
enable_smbus(); diff --git a/src/mainboard/tyan/s4882/cmos.layout b/src/mainboard/tyan/s4882/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/tyan/s4882/cmos.layout +++ b/src/mainboard/tyan/s4882/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 151fbc4..64bc243 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x10f1 0x4882 inherit chip northbridge/amd/amdk8 @@ -18,8 +18,8 @@ chip northbridge/amd/amdk8/root_complex # device pci 4.1 on end # register "fw_address" = "0xfff8c000" # end - device pci 9.0 on end #Broadcom - device pci 9.1 on end + device pci 9.0 on end #Broadcom + device pci 9.1 on end end device pci 0.1 on end device pci 1.0 on end @@ -33,158 +33,158 @@ chip northbridge/amd/amdk8/root_complex device pci 0.1 on end device pci 0.2 off end device pci 1.0 off end - #chip drivers/ati/ragexl - device pci 6.0 on end - #end - device pci 5.0 on end #SiI + #chip drivers/ati/ragexl + device pci 6.0 on end + #end + device pci 5.0 on end #SiI end device pci 1.0 on chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end end device pci 1.1 on end device pci 1.2 on end - device pci 1.3 on -# chip drivers/i2c/i2cmux # pca9556 smbus mux -# device i2c 18 on #0 pca9516 2, 1 -# chip drivers/i2c/lm63 #cpu0 temp -# device i2c 4c on end -# end + device pci 1.3 on +# chip drivers/i2c/i2cmux # pca9556 smbus mux +# device i2c 18 on #0 pca9516 2, 1 +# chip drivers/i2c/lm63 #cpu0 temp +# device i2c 4c on end +# end # end -# device i2c 18 on #1 pca9516 1, 1 -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 53 on end +# device i2c 18 on #1 pca9516 1, 1 +# chip drivers/generic/generic #dimm 1-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 1-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 1-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 1-1-1 +# device i2c 53 on end # end -# end -# device i2c 18 on #2 pca9516 1, 2 -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end +# end +# device i2c 18 on #2 pca9516 1, 2 +# chip drivers/generic/generic #dimm 0-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 0-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 0-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 0-1-1 +# device i2c 53 on end # end -# end -# device i2c 18 on #3 pca9516 1, 3 -# chip drivers/generic/generic #dimm 3-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 3-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 3-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 3-1-1 -# device i2c 53 on end +# end +# device i2c 18 on #3 pca9516 1, 3 +# chip drivers/generic/generic #dimm 3-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 3-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 3-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 3-1-1 +# device i2c 53 on end # end -# end -# device i2c 18 on #4 pca9516 1, 4 -# chip drivers/generic/generic #dimm 2-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 2-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 2-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 2-1-1 -# device i2c 53 on end +# end +# device i2c 18 on #4 pca9516 1, 4 +# chip drivers/generic/generic #dimm 2-0-0 +# device i2c 50 on end +# end +# chip drivers/generic/generic #dimm 2-0-1 +# device i2c 51 on end +# end +# chip drivers/generic/generic #dimm 2-1-0 +# device i2c 52 on end +# end +# chip drivers/generic/generic #dimm 2-1-1 +# device i2c 53 on end # end -# end -# device i2c 18 on #5 pca9516 2, 2 -# chip drivers/i2c/lm63 #cpu1 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #6 pca9516 2, 3 -# chip drivers/i2c/lm63 #cpu2 temp -# device i2c 4c on end -# end -# end -# device i2c 18 on #7 pca9516 2, 4 -# chip drivers/i2c/lm63 #cpu3 temp -# device i2c 4c on end -# end -# end -# end # i2cmux -# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... -# device i2c 2e on end -# end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid -# device i2c 2a on end -# end -# chip drivers/generic/generic # Winbond HWM 0x92 -# device i2c 49 on end -# end -# chip drivers/generic/generic # Winbond HWM 0x94 -# device i2c 4a on end -# end -# chip drivers/generic/generic # ?? -# device i2c 69 on end -# end - end # acpi +# end +# device i2c 18 on #5 pca9516 2, 2 +# chip drivers/i2c/lm63 #cpu1 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #6 pca9516 2, 3 +# chip drivers/i2c/lm63 #cpu2 temp +# device i2c 4c on end +# end +# end +# device i2c 18 on #7 pca9516 2, 4 +# chip drivers/i2c/lm63 #cpu3 temp +# device i2c 4c on end +# end +# end +# end # i2cmux +# chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN... +# device i2c 2e on end +# end +# chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid +# device i2c 2a on end +# end +# chip drivers/generic/generic # Winbond HWM 0x92 +# device i2c 49 on end +# end +# chip drivers/generic/generic # Winbond HWM 0x94 +# device i2c 4a on end +# end +# chip drivers/generic/generic # ?? +# device i2c 69 on end +# end + end # acpi device pci 1.5 off end device pci 1.6 off end register "ide0_enable" = "1" - register "ide1_enable" = "1" + register "ide1_enable" = "1" end end # device pci 18.0
- device pci 18.0 on end + device pci 18.0 on end
device pci 18.1 on end device pci 18.2 on end @@ -192,15 +192,15 @@ chip northbridge/amd/amdk8/root_complex end
end -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 on end # cpuid -# device pnp 0.4 off end # smbus_regs_all +# chip drivers/generic/debug +# device pnp 0.0 off end # chip name +# device pnp 0.1 off end # pci_regs_all +# device pnp 0.2 off end # mem +# device pnp 0.3 on end # cpuid +# device pnp 0.4 off end # smbus_regs_all # device pnp 0.5 on end # dual core msr # device pnp 0.6 on end # cache size # device pnp 0.7 on end # tsc -# end +# end end
diff --git a/src/mainboard/tyan/s4882/irq_tables.c b/src/mainboard/tyan/s4882/irq_tables.c index d89c034..4ef4618 100644 --- a/src/mainboard/tyan/s4882/irq_tables.c +++ b/src/mainboard/tyan/s4882/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 1, /* Where the interrupt router lies (bus) */ - (4<<3)|3, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x1022, /* Vendor */ - 0x7400, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (4<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x7400, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { {0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, {1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0}, @@ -46,5 +46,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..fcb171d 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -10,131 +10,131 @@
static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; - unsigned reg; - - dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); - if (!dev) { - return 0; - } - for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; - unsigned dst_node; - unsigned dst_link; - unsigned bus_base; - config_map = pci_read_config32(dev, reg); - if ((config_map & 3) != 3) { - continue; - } - dst_node = (config_map >> 4) & 7; - dst_link = (config_map >> 8) & 3; - bus_base = (config_map >> 16) & 0xff; + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; #if 0 - printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", - dst_node, dst_link, bus_base, - reg, config_map); + printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); #endif - if ((dst_node == node) && (dst_link == link)) - { - return bus_base; - } - } - return 0; + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; }
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int bus_isa; + struct mp_config_table *mc; + int bus_isa; unsigned char bus_chain_0; - unsigned char bus_8131_1; - unsigned char bus_8131_2; - unsigned char bus_8111_1; - unsigned apicid_base; - unsigned apicid_8111; - unsigned apicid_8131_1; - unsigned apicid_8131_2; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_1; + unsigned apicid_base; + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - - { - device_t dev; - - /* HT chain 0 */ - bus_chain_0 = node_link_to_bus(0, 1); - if (bus_chain_0 == 0) { - printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); - bus_chain_0 = 1; - } - - /* 8111 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); - - bus_8111_1 = 4; - } - /* 8131-1 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); - if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); - - bus_8131_1 = 2; - } - /* 8131-2 */ - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - - bus_8131_2 = 3; - } - } - -/*Bus: Bus ID Type*/ + smp_write_processors(mc); + + { + device_t dev; + + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 1); + if (bus_chain_0 == 0) { + printk(BIOS_DEBUG, "ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + + /* 8111 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); + if (dev) { + bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + + bus_8111_1 = 4; + } + /* 8131-1 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); + if (dev) { + bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); + + bus_8131_1 = 2; + } + /* 8131-2 */ + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); + if (dev) { + bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + + } + else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); + + bus_8131_2 = 3; + } + } + +/*Bus: Bus ID Type*/ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(3); #else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + apicid_8111 = apicid_base+0; + apicid_8131_1 = apicid_base+1; + apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); - { - device_t dev; - struct resource *res; - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); - } - } - dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); - } - } + { + device_t dev; + struct resource *res; + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); + } + } + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); + if (dev) { + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); + } + }
}
@@ -148,9 +148,9 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
//On Board Via USB 1.1 and 2 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, apicid_8111, 0x11); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, apicid_8111, 0x10); //1.1 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, apicid_8111, 0x12); //2
//Slot 5 PCI 32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); @@ -162,14 +162,14 @@ static void *smp_write_config_table(void *v) //On Board SI Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13); //On Board ATI Display Adapter - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
//Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
//Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); @@ -178,22 +178,22 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
//On Board LSI scsi and NIC - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
//Slot 2 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
//Slot 1 PCI-X 133/100/66 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); diff --git a/src/mainboard/tyan/s4882/resourcemap.c b/src/mainboard/tyan/s4882/resourcemap.c index 2ee2749..95e918f 100644 --- a/src/mainboard/tyan/s4882/resourcemap.c +++ b/src/mainboard/tyan/s4882/resourcemap.c @@ -201,11 +201,11 @@ static void setup_s4882_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index e21cca3..387a8f9 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -24,48 +24,48 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) - outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 else - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { - udelay(800); - outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 - udelay(90); + udelay(800); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + udelay(90); } }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret,i; - unsigned device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); - - smbus_write_byte(SMBUS_HUB, 0x03, 0); + int ret,i; + unsigned device=(ctrl->channel0[0])>>8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret!=0) && (i-->0)); + + smbus_write_byte(SMBUS_HUB, 0x03, 0); }
#if 0 static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 - int ret, i; - print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); - } while ((ret!=0) && (i-->0)); - ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); - print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); + int ret, i; + print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); + i=2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); + } while ((ret!=0) && (i-->0)); + ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); + print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); } #endif
@@ -91,57 +91,57 @@ static inline int spd_read_byte(unsigned device, unsigned address) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - RC3|DIMM0, RC3|DIMM2, 0, 0, - RC3|DIMM1, RC3|DIMM3, 0, 0, + RC2|DIMM0, RC2|DIMM2, 0, 0, + RC2|DIMM1, RC2|DIMM3, 0, 0, + RC3|DIMM0, RC3|DIMM2, 0, 0, + RC3|DIMM1, RC3|DIMM3, 0, 0, #endif };
- int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset; + unsigned bsp_apicid = 0, nodes; + struct mem_controller ctrl[8];
- if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + console_init();
/* Halt if there was a built in self test failure */ report_bist_failure(bist);
- setup_s4882_resource_map(); + setup_s4882_resource_map();
needs_reset = setup_coherent_ht_domain();
- wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS - // It is said that we should start core1 after all core0 launched - start_other_cores(); - wait_all_other_cores_started(bsp_apicid); + // It is said that we should start core1 after all core0 launched + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); #endif
// automatically set that for you, but you might meet tight space - needs_reset |= ht_setup_chains_x(); + needs_reset |= ht_setup_chains_x();
if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); + print_info("ht reset -\n"); + soft_reset(); }
- allow_all_aps_stop(bsp_apicid); + allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes(); - //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + nodes = get_nodes(); + //It's the time to set ctrl now; + fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 0d6e175..25c544c 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -30,29 +30,29 @@ /* These defines are used to select the appropriate socket for the SPD read * because this is a multi-socket design. */ -#define PCI_REG_GPIO_48_47_46_37_CNTRL (0xA6) -#define PCI_REG_GPIO_52_to_49_CNTRL (0x50) -#define GPIO_OUT_BIT_GPIO48 (BIT3) -#define GPIO_OUT_BIT_GPIO49 (BIT0) -#define GPIO_OUT_ENABLE_BIT_GPIO48 (BIT7) -#define GPIO_OUT_ENABLE_BIT_GPIO49 (BIT4) +#define PCI_REG_GPIO_48_47_46_37_CNTRL (0xA6) +#define PCI_REG_GPIO_52_to_49_CNTRL (0x50) +#define GPIO_OUT_BIT_GPIO48 (BIT3) +#define GPIO_OUT_BIT_GPIO49 (BIT0) +#define GPIO_OUT_ENABLE_BIT_GPIO48 (BIT7) +#define GPIO_OUT_ENABLE_BIT_GPIO49 (BIT4)
static UINT8 select_socket(UINT8 socket_id) { device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - UINT8 value = 0; - UINT8 gpio52_to_49 = 0; + UINT8 value = 0; + UINT8 gpio52_to_49 = 0;
/* Configure GPIO49,48 to select the desired socket * GPIO49,48 control the IDTQS3253 S1,S0 * S1 S0 true table * 0 0 channel 0 * 0 1 channel 1 - * 1 0 channel 2 - Socket 0 - * 1 1 channel 3 - Socket 1 + * 1 0 channel 2 - Socket 0 + * 1 1 channel 3 - Socket 1 * Note: Above is abstracted from Schematic. But actually it seems to be other way. - * 1 0 channel 2 - Socket 1 - * 1 1 channel 3 - Socket 0 + * 1 0 channel 2 - Socket 1 + * 1 1 channel 3 - Socket 0 * Note: The DIMMs need to be plugged in from the farthest slot for each channel. */ gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL); @@ -192,11 +192,11 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -213,14 +213,14 @@ AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -343,12 +343,12 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -461,8 +461,8 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -495,7 +495,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); return Status; @@ -503,9 +503,9 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.h b/src/mainboard/tyan/s8226/BiosCallOuts.h index 53c23a9..b0da979 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.h +++ b/src/mainboard/tyan/s8226/BiosCallOuts.h @@ -65,13 +65,13 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 #endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/tyan/s8226/OptionsIds.h b/src/mainboard/tyan/s8226/OptionsIds.h index ceb336f..ca2bcd2 100644 --- a/src/mainboard/tyan/s8226/OptionsIds.h +++ b/src/mainboard/tyan/s8226/OptionsIds.h @@ -25,7 +25,7 @@ * This file is used to switch on/off IDS features. * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Core * @e $Revision: 12067 $ @e $Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ */ @@ -53,15 +53,15 @@ #define IDSOPT_IDS_ENABLED TRUE //#define IDSOPT_CONTROL_ENABLED TRUE //#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE #define IDSOPT_ASSERT_ENABLED TRUE //#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE //#undef IDSOPT_DEBUG_ENABLED //#define IDSOPT_DEBUG_ENABLED FALSE //#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE +//#define IDSOPT_HOST_SIMNOW FALSE //#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE +//#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80
#endif diff --git a/src/mainboard/tyan/s8226/acpi/ide.asl b/src/mainboard/tyan/s8226/acpi/ide.asl index b3aed9c..cb284ed 100644 --- a/src/mainboard/tyan/s8226/acpi/ide.asl +++ b/src/mainboard/tyan/s8226/acpi/ide.asl @@ -196,8 +196,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTM), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } @@ -232,8 +232,8 @@ Device(PRID) } Else { Store(Match - (MDTT, MLE, GTTM(PMTS), - MTR, 0, 0), Local0) + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) If(LLess(Local0, 3)) { Or(0x20, Local0, DMMD) } diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 7fba1b7..d773d9a 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -41,38 +41,38 @@ #define FILECODE UNASSIGNED_FILE_FILECODE
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; +VOID *DmiTable = NULL; VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL;
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); @@ -176,11 +176,11 @@ agesawrapper_amdinitmmio ( VOID ) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader;
/* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base @@ -441,9 +441,9 @@ UINT32 agesawrapper_amdinitlate(VOID) AMD_LATE_PARAMS *AmdLateParamsPtr;
LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -471,8 +471,8 @@ UINT32 agesawrapper_amdinitlate(VOID) AcpiAlib = AmdLateParamsPtr->AcpiAlib;
printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
diff --git a/src/mainboard/tyan/s8226/agesawrapper.h b/src/mainboard/tyan/s8226/agesawrapper.h index a553ea8..7fc25c5 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.h +++ b/src/mainboard/tyan/s8226/agesawrapper.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -31,25 +31,25 @@ #include "AGESA.h"
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */ #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ PICK_WHEA_MCE, /* WHEA MCE table */ PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ };
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
@@ -59,17 +59,17 @@ typedef struct { } BIOS_CALLOUT_STRUCT;
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index bb4dd2d..2549331 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -55,90 +55,90 @@ * Comment out the items wanted to be included in the build. * Uncomment those items you with to REMOVE from the build. */ -//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE -//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE -////#define BLDOPT_REMOVE_SRAT TRUE -////#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +////#define BLDOPT_REMOVE_SRAT TRUE +////#define BLDOPT_REMOVE_SLIT TRUE +//#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE
/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE -//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE +//#define BLDOPT_REMOVE_HT_ASSIST TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
/* Build configuration values here. */ -#define BLDCFG_VRM_CURRENT_LIMIT 120000 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 -#define BLDCFG_PLAT_NUM_IO_APICS 3 -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_MEM_INIT_PSTATE 0 -#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 - -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER - -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600 -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED -#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE -#define BLDCFG_MEMORY_POWER_DOWN FALSE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL -#define BLDCFG_ONLINE_SPARE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -#define BLDCFG_ENABLE_ECC_FEATURE TRUE -#define BLDCFG_ECC_REDIRECTION FALSE -#define BLDCFG_SCRUB_IC_RATE 0 -#define BLDCFG_ECC_SYNC_FLOOD TRUE -#define BLDCFG_ECC_SYMBOL_SIZE 4 - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600 +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_POWER_DOWN FALSE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/** * Enable Message Based C1e CPU feature in multi-socket systems. * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value, * else the feature cannot be enabled. */ -#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased -#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 - -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 -#define BLDCFG_1GB_ALIGN FALSE -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define BLDCFG_1GB_ALIGN FALSE +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' //
// Select the platform control flow mode for performance tuning. @@ -151,8 +151,8 @@ * * This feature may interact with other performance features. * TRUE -Enable the feature (default) if supported by all processors, - * based on revision and presence of L3 cache. - * The feature is not enabled if there are no coherent HT links. + * based on revision and presence of L3 cache. + * The feature is not enabled if there are no coherent HT links. * FALSE -Do not enable the feature regardless of the configuration. */ //TODO enable it, @@ -426,32 +426,32 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/* #if CONFIG_CPU_AMD_AGESA_FAMILY15 - #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif #if CONFIG_CPU_AMD_AGESA_FAMILY10 - #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */
-//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "SanMarinoInstall.h"
/*---------------------------------------------------------------------------------------- - * CUSTOMER OVERIDES MEMORY TABLE + * CUSTOMER OVERIDES MEMORY TABLE *---------------------------------------------------------------------------------------- */
@@ -476,64 +476,64 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // The following macros are supported (use comma to separate macros): // // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) - // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. - // AGESA will base on this value to disable unused MemClk to save power. - // Example: - // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - // Bit AM3/S1g3 pin name - // 0 M[B,A]_CLK_H/L[0] - // 1 M[B,A]_CLK_H/L[1] - // 2 M[B,A]_CLK_H/L[2] - // 3 M[B,A]_CLK_H/L[3] - // 4 M[B,A]_CLK_H/L[4] - // 5 M[B,A]_CLK_H/L[5] - // 6 M[B,A]_CLK_H/L[6] - // 7 M[B,A]_CLK_H/L[7] - // And platform has the following routing: - // CS0 M[B,A]_CLK_H/L[4] - // CS1 M[B,A]_CLK_H/L[2] - // CS2 M[B,A]_CLK_H/L[3] - // CS3 M[B,A]_CLK_H/L[5] - // Then platform can specify the following macro: - // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) // // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) - // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. - // AGESA will base on this value to tristate unused CKE to save power. + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. // // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) - // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. - // AGESA will base on this value to tristate unused ODT pins to save power. + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. // // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) - // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. - // AGESA will base on this value to tristate unused Chip select to save power. + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. // // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) - // Specifies the number of DIMM slots per channel. + // Specifies the number of DIMM slots per channel. // // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) - // Specifies the number of Chip selects per channel. + // Specifies the number of Chip selects per channel. // // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) - // Specifies the number of channels per socket. + // Specifies the number of channels per socket. // // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) - // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // Specifies DDR bus speed of channel ChannelID on socket SocketID. // // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE) - // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) // // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, - // Byte6Seed, Byte7Seed, ByteEccSeed) - // Specifies the write leveling seed for a channel of a socket. + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. //
/* Specifies the write leveling seed for a channel of a socket. * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, - * ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) */ WRITE_LEVELING_SEED( ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, @@ -542,8 +542,8 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { F15_WL_SEED),
/* HW_RXEN_SEED(SocketID, ChannelID, DimmID, - * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, - * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) */ HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, @@ -583,8 +583,8 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in // the table and replace the byte lane values with your own. // - // ------------------ BYTE LANES ---------------------- - // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC // Write Data Timing // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 @@ -610,7 +610,7 @@ UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 //-------------------------------------------------------------------------------------------------------------------------------------------------- // TABLE END - NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table }; UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
diff --git a/src/mainboard/tyan/s8226/cmos.layout b/src/mainboard/tyan/s8226/cmos.layout index 95ce3b5..1676c25 100644 --- a/src/mainboard/tyan/s8226/cmos.layout +++ b/src/mainboard/tyan/s8226/cmos.layout @@ -21,95 +21,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index f879ec5..6576e5e 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/agesa/family15/root_complex device domain 0 on subsystemid 0x15d9 0xab11 inherit #Tyan chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG diff --git a/src/mainboard/tyan/s8226/dsdt.asl b/src/mainboard/tyan/s8226/dsdt.asl index 79bc096..0f9508a 100644 --- a/src/mainboard/tyan/s8226/dsdt.asl +++ b/src/mainboard/tyan/s8226/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock ( "DSDT.AML", /* Output filename */ "DSDT", /* Signature */ 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ + "AMD ", /* OEMID */ "COREBOOT", /* TABLE ID */ 0x00010001 /* OEM Revision */ ) @@ -314,8 +314,8 @@ DefinitionBlock ( Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, @@ -455,7 +455,7 @@ DefinitionBlock ( if(CondRefOf(_OSI,Local1)) { Store(1, OSTP) /* Assume some form of XP */ - if (_OSI("Windows 2006")) /* Vista */ + if (_OSI("Windows 2006")) /* Vista */ { Store(2, OSTP) } @@ -834,7 +834,7 @@ DefinitionBlock ( } Store(Local0, PINH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
@@ -989,17 +989,17 @@ DefinitionBlock ( Scope(_GPE) { /* Start Scope GPE */ /* General event 0 */ Method(_L00) { - //DBGO("\_GPE\_L00\n") + //DBGO("\_GPE\_L00\n") }
/* General event 1 */ Method(_L01) { - //DBGO("\_GPE\_L01\n") + //DBGO("\_GPE\_L01\n") }
/* General event 2 */ Method(_L02) { - //DBGO("\_GPE\_L02\n") + //DBGO("\_GPE\_L02\n") }
/* General event 3 */ @@ -1010,12 +1010,12 @@ DefinitionBlock (
/* General event 4 */ Method(_L04) { - //DBGO("\_GPE\_L04\n") + //DBGO("\_GPE\_L04\n") }
/* General event 5 */ Method(_L05) { - //DBGO("\_GPE\_L05\n") + //DBGO("\_GPE\_L05\n") }
/* _L06 General event 6 - Used for GPM6, moved to USB.asl */ @@ -1034,7 +1034,7 @@ DefinitionBlock (
/* Reserved */ Method(_L0A) { - //DBGO("\_GPE\_L0A\n") + //DBGO("\_GPE\_L0A\n") }
/* USB controller PME# */ @@ -1051,12 +1051,12 @@ DefinitionBlock (
/* AC97 controller PME# */ Method(_L0C) { - //DBGO("\_GPE\_L0C\n") + //DBGO("\_GPE\_L0C\n") }
/* OtherTherm PME# */ Method(_L0D) { - //DBGO("\_GPE\_L0D\n") + //DBGO("\_GPE\_L0D\n") }
/* _L0E GPM9 SCI event - Moved to USB.asl */ @@ -1079,7 +1079,7 @@ DefinitionBlock (
/* PCIe PME# event */ Method(_L12) { - //DBGO("\_GPE\_L12\n") + //DBGO("\_GPE\_L12\n") }
/* _L13 GPM0 SCI event - Moved to USB.asl */ @@ -1111,12 +1111,12 @@ DefinitionBlock (
/* GPM6 SCI event - Reassigned to _L06 */ Method(_L1C) { - //DBGO("\_GPE\_L1C\n") + //DBGO("\_GPE\_L1C\n") }
/* GPM7 SCI event - Reassigned to _L07 */ Method(_L1D) { - //DBGO("\_GPE\_L1D\n") + //DBGO("\_GPE\_L1D\n") }
/* GPIO2 or GPIO66 SCI event */ @@ -1424,7 +1424,7 @@ DefinitionBlock ( OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ Field (IOID, ByteAcc, NoLock, Preserve) { - SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ }
IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) @@ -1498,60 +1498,60 @@ DefinitionBlock ( Name (CRS, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length ,,) IO (Decode16, - 0x0CF8, // Range Minimum - 0x0CF8, // Range Maximum - 0x01, // Alignment - 0x08, // Length + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length )
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x03AF, // Range Maximum - 0x0000, // Translation Offset - 0x03B0, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x03AF, // Range Maximum + 0x0000, // Translation Offset + 0x03B0, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03E0, // Range Minimum - 0x0CF7, // Range Maximum - 0x0000, // Translation Offset - 0x0918, // Length + 0x0000, // Granularity + 0x03E0, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0918, // Length ,, , TypeStatic)
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03B0, // Range Minimum - 0x03BB, // Range Maximum - 0x0000, // Translation Offset - 0x000C, // Length + 0x0000, // Granularity + 0x03B0, // Range Minimum + 0x03BB, // Range Maximum + 0x0000, // Translation Offset + 0x000C, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x03C0, // Range Minimum - 0x03DF, // Range Maximum - 0x0000, // Translation Offset - 0x0020, // Length + 0x0000, // Granularity + 0x03C0, // Range Minimum + 0x03DF, // Range Maximum + 0x0000, // Translation Offset + 0x0020, // Length ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, // Granularity - 0x0D00, // Range Minimum - 0xFFFF, // Range Maximum - 0x0000, // Translation Offset - 0xF300, // Length + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
Memory32Fixed (ReadOnly, - 0xE0000000, // Address Base - 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) + 0xE0000000, // Address Base + 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) })
@@ -1560,18 +1560,18 @@ DefinitionBlock ( CreateDWordField (CRS, _SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, _SB.PCI0.MMIO._LEN, LEN1)
- /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ Store(TOM1, BAS1) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, LEN1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) //DBGO(TOM1)
Return (CRS) @@ -1579,23 +1579,23 @@ DefinitionBlock (
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. + * value is based on user choice in BIOS setup. */ Method(_INI, 0) { /* DBGO("\_SB\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(" DSDT.ASL code from ") */ /* DBGO(__DATE__) */ /* DBGO(" ") */ /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n Sleep states supported: ") */ /* DBGO("\n") */ - /* DBGO(" \_OS=") */ + /* DBGO(" \_OS=") */ /* DBGO(_OS) */ - /* DBGO("\n \_REV=") */ + /* DBGO("\n \_REV=") */ /* DBGO(_REV) */ /* DBGO("\n") */
@@ -1603,7 +1603,7 @@ DefinitionBlock ( CkOT() /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) *} */ } /* End Method(_SB._INI) */ diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c index ab50e0f..90c239a 100644 --- a/src/mainboard/tyan/s8226/fadt.c +++ b/src/mainboard/tyan/s8226/fadt.c @@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pstate_cnt = 0xe2;
/* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index d45e1ad..e4fe048 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -134,7 +134,7 @@ void get_bus_conf(void) */
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10;
#if CONFIG_AMD_SB_CIMX diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index c10a219..fca029f 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -111,7 +111,7 @@ static void *smp_write_config_table(void *v)
}
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
@@ -179,7 +179,7 @@ static void *smp_write_config_table(void *v) PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ diff --git a/src/mainboard/tyan/s8226/platform_oem.c b/src/mainboard/tyan/s8226/platform_oem.c index aeb91a7..924c692 100644 --- a/src/mainboard/tyan/s8226/platform_oem.c +++ b/src/mainboard/tyan/s8226/platform_oem.c @@ -38,7 +38,7 @@ * @param[in] **PeiServices * @param[in] *InitEarly * - * @retval VOID + * @retval VOID * **/ /*---------------------------------------------------------------------------------------*/ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 07cd3d4..d1a23a6 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -104,8 +104,8 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); * - * @param[in] u32 func Northbridge CIMx CallBackId - * @param[in] u32 data Northbridge Input Data. + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. * */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 8547faa..0dc141c 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -66,7 +66,7 @@ /** * Bitmap of ports that have slot or onboard device connected. * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) - * #define DEFAULT_PORT_FORCE_GEN1 0x604 + * #define DEFAULT_PORT_FORCE_GEN1 0x604 */ #ifndef DEFAULT_PORT_FORCE_GEN1 #define DEFAULT_PORT_FORCE_GEN1 0x0 @@ -107,12 +107,12 @@
/** * Default GPP3a core configuraton on NB #0/1/2/3. - * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 - * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 - * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 - * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 - * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 - * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 */ #ifndef DEFAULT_GPP3A_CONFIG #define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 @@ -153,17 +153,17 @@ * Platform configuration */ typedef struct { - UINT16 PortEnableMap; ///< Bitmap of enabled ports - UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 - UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug - UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors - UINT32 TemporaryMmio; ///< Temporary MMIO - UINT32 Gpp1Config; ///< Default PCIe GFX core configuration - UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration - UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration - UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level - // HT_PATH NbHtPath; ///< HT path to NB - UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. } NB_PLATFORM_CONFIG;
/** diff --git a/src/mainboard/tyan/s8226/sb700_cfg.c b/src/mainboard/tyan/s8226/sb700_cfg.c index 54c139a..3dc5dc5 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.c +++ b/src/mainboard/tyan/s8226/sb700_cfg.c @@ -19,7 +19,7 @@
#include <string.h> -#include <console/console.h> /* printk */ +#include <console/console.h> /* printk */ #include "Platform.h" #include "sb700_cfg.h"
@@ -96,7 +96,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) sb_config->HpetTimer = HPET_TIMER;
/* USB */ - sb_config->UsbIntClock = 0; // Use external clock + sb_config->UsbIntClock = 0; // Use external clock sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h index c1ee84c..66615a2 100644 --- a/src/mainboard/tyan/s8226/sb700_cfg.h +++ b/src/mainboard/tyan/s8226/sb700_cfg.h @@ -30,10 +30,10 @@ * @def BIOS_SIZE_4M * @def BIOS_SIZE_8M */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7
/* In SB700, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -57,7 +57,7 @@ * 0 - Disable Spread Spectrum function * 1 - Enable Spread Spectrum function */ -#define SPREAD_SPECTRUM 0 +#define SPREAD_SPECTRUM 0
/** * @def SB_HPET_TIMER @@ -65,7 +65,7 @@ * 0 - Disable hpet * 1 - Enable hpet */ -#define HPET_TIMER 1 +#define HPET_TIMER 1
/** * @def USB_CONFIG @@ -80,7 +80,7 @@ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 */ -#define USB_CINFIG 0x7F +#define USB_CINFIG 0x7F
/** * @def PCI_CLOCK_CTRL @@ -93,14 +93,14 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x1F
/** * @def SATA_CONTROLLER * @brief INCHIP Sata Controller */ #ifndef SATA_CONTROLLER -#define SATA_CONTROLLER 1 +#define SATA_CONTROLLER 1 #endif
/** @@ -109,14 +109,14 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_MODE -#define SATA_MODE NATIVE_IDE_MODE +#define SATA_MODE NATIVE_IDE_MODE #endif
/** * @brief INCHIP Sata IDE Controller Mode */ -#define IDE_LEGACY_MODE 0 -#define IDE_NATIVE_MODE 1 +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1
/** * @def SATA_IDE_MODE @@ -124,7 +124,7 @@ * NOTE: DO NOT ALLOW SATA & IDE use same mode */ #ifndef SATA_IDE_MODE -#define SATA_IDE_MODE IDE_LEGACY_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE #endif
/** @@ -136,37 +136,37 @@ * @brief 01/11: Reference clock from internal clock through * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL */ -#define EXTERNAL_CLOCK 0x00 -#define INTERNAL_CLOCK 0x01 +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01
-#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK
/** * @def SATA_PORT_MULT_CAP_RESERVED * @brief 1 ON, 0 0FF */ -#define SATA_PORT_MULT_CAP_RESERVED 1 +#define SATA_PORT_MULT_CAP_RESERVED 1
/** - * @def AZALIA_AUTO + * @def AZALIA_AUTO * @brief Detect Azalia controller automatically. * - * @def AZALIA_DISABLE + * @def AZALIA_DISABLE * @brief Disable Azalia controller.
- * @def AZALIA_ENABLE + * @def AZALIA_ENABLE * @brief Enable Azalia controller. */ -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2
/** * @brief INCHIP HDA controller */ #ifndef AZALIA_CONTROLLER -#define AZALIA_CONTROLLER AZALIA_AUTO +#define AZALIA_CONTROLLER AZALIA_AUTO #endif
/** @@ -176,7 +176,7 @@ * 1 - enable */ #ifndef AZALIA_PIN_CONFIG -#define AZALIA_PIN_CONFIG 1 +#define AZALIA_PIN_CONFIG 1 #endif
/** @@ -191,14 +191,14 @@ * SDIN3 is define at BIT6 & BIT7 */ #ifndef AZALIA_SDIN_PIN -#define AZALIA_SDIN_PIN 0x02 +#define AZALIA_SDIN_PIN 0x02 #endif
/** * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER -#define GPP_CONTROLLER 1 +#define GPP_CONTROLLER 1 #endif
/** @@ -211,7 +211,7 @@ * GPP_CFGMODE_X1111 */ #ifndef GPP_CFGMODE -#define GPP_CFGMODE GPP_CFGMODE_X1111 +#define GPP_CFGMODE GPP_CFGMODE_X1111 #endif
diff --git a/src/mainboard/via/epia-cn/cmos.layout b/src/mainboard/via/epia-cn/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/via/epia-cn/cmos.layout +++ b/src/mainboard/via/epia-cn/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/epia-cn/devicetree.cb b/src/mainboard/via/epia-cn/devicetree.cb index 028cb88..db13dab 100644 --- a/src/mainboard/via/epia-cn/devicetree.cb +++ b/src/mainboard/via/epia-cn/devicetree.cb @@ -24,29 +24,29 @@ chip northbridge/via/cn700 # Northbridge device pci 10.4 on end # EHCI device pci 10.5 on end # UDCI device pci 11.0 on # Southbridge LPC - chip superio/via/vt1211 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.b on # HWM - io 0x60 = 0xec00 - end - end + chip superio/via/vt1211 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.b on # HWM + io 0x60 = 0xec00 + end + end end device pci 11.5 on end # AC'97 audio # device pci 11.6 off end # AC'97 Modem diff --git a/src/mainboard/via/epia-cn/irq_tables.c b/src/mainboard/via/epia-cn/irq_tables.c index 8b137ab..ac32c06 100644 --- a/src/mainboard/via/epia-cn/irq_tables.c +++ b/src/mainboard/via/epia-cn/irq_tables.c @@ -34,7 +34,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x66, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0}, diff --git a/src/mainboard/via/epia-m/acpi_tables.c b/src/mainboard/via/epia-m/acpi_tables.c index b174bae..d14a2c0 100644 --- a/src/mainboard/via/epia-m/acpi_tables.c +++ b/src/mainboard/via/epia-m/acpi_tables.c @@ -47,7 +47,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt;
/* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); + start = ALIGN(start, 16); current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); diff --git a/src/mainboard/via/epia-m/cmos.layout b/src/mainboard/via/epia-m/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/via/epia-m/cmos.layout +++ b/src/mainboard/via/epia-m/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/epia-m/devicetree.cb b/src/mainboard/via/epia-m/devicetree.cb index 98f6b4f..ad82414 100644 --- a/src/mainboard/via/epia-m/devicetree.cb +++ b/src/mainboard/via/epia-m/devicetree.cb @@ -18,7 +18,7 @@ chip northbridge/via/vt8623 device pci 10.2 on end # USB 1.1 device pci 10.3 on end # USB 2
- device pci 11.0 on # Southbridge + device pci 11.0 on # Southbridge chip superio/via/vt1211 device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 diff --git a/src/mainboard/via/epia-m/dsdt.asl b/src/mainboard/via/epia-m/dsdt.asl index edc38bf..de4222f 100644 --- a/src/mainboard/via/epia-m/dsdt.asl +++ b/src/mainboard/via/epia-m/dsdt.asl @@ -44,7 +44,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) IRQ (Level, ActiveLow, Shared) {5} }) Return (BUFF) - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -52,13 +52,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_PRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () - { + { IRQ (Level, ActiveLow, Shared) {5,9,10} - }) - Return (BUFF) - } + }) + Return (BUFF) + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -86,7 +86,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) IRQ (Level, ActiveLow, Shared) {9} }) Return (BUFF) - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -94,13 +94,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_PRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () - { + { IRQ (Level, ActiveLow, Shared) {5,9,10} - }) - Return (BUFF) - } + }) + Return (BUFF) + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -128,7 +128,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) IRQ (Level, ActiveLow, Shared) {9} }) Return (BUFF) - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -136,13 +136,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_PRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () - { + { IRQ (Level, ActiveLow, Shared) {5,9,10} - }) - Return (BUFF) - } + }) + Return (BUFF) + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -170,7 +170,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) IRQ (Level, ActiveLow, Shared) {5} }) Return (BUFF) - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -178,13 +178,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Method (_PRS, 0, NotSerialized) { Name (BUFF, ResourceTemplate () - { + { IRQ (Level, ActiveLow, Shared) {5,9,10} - }) - Return (BUFF) - } + }) + Return (BUFF) + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -246,7 +246,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) Package () {0x0001FFFF, 0x02, LNKC, 0x00}, // VGA Link C Package () {0x0001FFFF, 0x03, LNKD, 0x00} // VGA Link D
- }) + })
} // End of PCI0 diff --git a/src/mainboard/via/epia-m/irq_tables.c b/src/mainboard/via/epia-m/irq_tables.c index 1f2634e..dd9873c 100644 --- a/src/mainboard/via/epia-m/irq_tables.c +++ b/src/mainboard/via/epia-m/irq_tables.c @@ -9,18 +9,18 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x00<<3)|0x0, /* Where the interrupt router lies (dev) */ 0xc20, /* IRQs devoted exclusively to PCI usage */ 0, /* Vendor */ 0, /* Device */ 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x68, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x68, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0x0deb8}}, 0x3, 0x0}, @@ -30,5 +30,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index ebe6a50..c2f4a67 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -28,7 +28,7 @@ static void enable_mainboard_devices(void) device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8235), 0); + PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); @@ -39,14 +39,14 @@ static void enable_mainboard_devices(void) // This early setup switches IDE into compatibility mode before PCI gets // a chance to assign I/Os // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax - // // movb $0x09, %dl + // // movb $0x09, %dl // movb $0x00, %dl // PCI_WRITE_CONFIG_BYTE #endif /* we do this here as in V2, we can not yet do raw operations * to pci! */ - dev += 0x100; /* ICKY */ + dev += 0x100; /* ICKY */
pci_write_config8(dev, 0x04, 7); pci_write_config8(dev, 0x40, 3); diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c index fa8330f..17c581e 100644 --- a/src/mainboard/via/epia-m700/acpi_tables.c +++ b/src/mainboard/via/epia-m700/acpi_tables.c @@ -72,7 +72,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, if (!cpu->enabled) continue; current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, cpu_index, flags, lint); + current, cpu_index, flags, lint); cpu_index++; } return current; @@ -97,7 +97,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
return current; } @@ -114,8 +114,8 @@ unsigned long acpi_fill_srat(unsigned long current) return current; }
-#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) +#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) +#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
unsigned long write_acpi_tables(unsigned long start) { diff --git a/src/mainboard/via/epia-m700/cmos.layout b/src/mainboard/via/epia-m700/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/via/epia-m700/cmos.layout +++ b/src/mainboard/via/epia-m700/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/epia-m700/driving_clk_phase_data.c b/src/mainboard/via/epia-m700/driving_clk_phase_data.c index 6b0afa4..969fb06 100644 --- a/src/mainboard/via/epia-m700/driving_clk_phase_data.c +++ b/src/mainboard/via/epia-m700/driving_clk_phase_data.c @@ -23,7 +23,7 @@ // DQS Driving // Reg0xE0, 0xE1 // According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 +// #Bank 1 2 3 4 5 6 7 8 static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE }; static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE };
@@ -36,7 +36,7 @@ static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; // CS Driving // Reg0xE4, 0xE5 // According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 +// DDR1 #Bank 1 2 3 4 5 6 7 8 static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44 }; static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 }; @@ -45,23 +45,23 @@ static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 }; // MAA Driving // Reg0xE8, Reg0xE9 static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { - // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ + // Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 + {6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 + {18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 + {255, 0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~ };
static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - {6, 0x86}, // total MAB chips = 00 ~ 06 - {18, 0x86}, // total MAB chips = 06 ~ 18 - {255, 0xDB}, // total MAB chips = 18 ~ + // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 + {6, 0x86}, // total MAB chips = 00 ~ 06 + {18, 0x86}, // total MAB chips = 06 ~ 18 + {255, 0xDB}, // total MAB chips = 18 ~ };
// DCLK Driving // Reg0xE6, 0xE7 // For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M +// freq 400M, 533M, 667M, 800M static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
@@ -93,9 +93,9 @@ static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = * Processing: * 1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode. * 2. Program clock phase value with ChA/B DCLK enable, - * VIA_NB3DRAM_REG91[7:3]=00b + * VIA_NB3DRAM_REG91[7:3]=00b * 3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. + * ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b. */ static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { // (And NOT) DDR800 DDR667 DDR533 DDR400 @@ -116,7 +116,7 @@ static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { /* vt6413c */ #if 0 static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 + // (And NOT) DDR800 DDR667 DDR533 DDR400 //Reg Mask Value Value Value Value {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, @@ -126,7 +126,7 @@ static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
/* vt6413d */ static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 + // (And NOT) DDR800 DDR667 DDR533 DDR400 //Reg Mask Value Value Value Value {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02}, diff --git a/src/mainboard/via/epia-m700/irq_tables.c b/src/mainboard/via/epia-m700/irq_tables.c index 7cb4623..c93a371 100644 --- a/src/mainboard/via/epia-m700/irq_tables.c +++ b/src/mainboard/via/epia-m700/irq_tables.c @@ -22,7 +22,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ 0xdb, /* Checksum. 0xa0? */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0}, {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0}, {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0}, diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 1936052..1318790 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -59,7 +59,7 @@ static int acpi_is_wakeup_early_via_vx800(void) print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); + PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID) die("Power management controller not found\n"); @@ -72,7 +72,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
tmp = inw(VX800_ACPI_IO_BASE + 0x04); result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - print_debug(" boot_mode="); + print_debug(" boot_mode="); print_debug_hex16(result); print_debug("\n"); return result; @@ -89,7 +89,7 @@ static void enable_mainboard_devices(void) */ u8 regdata; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); + PCI_DEVICE_ID_VIA_VX855_LPC), 0);
/* Disable GP3. */ pci_write_config8(dev, 0x98, 0x00); @@ -254,7 +254,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table };
-#define USE_VCP 1 /* 0 means "use DVP". */ +#define USE_VCP 1 /* 0 means "use DVP". */ #define USE_COM1 1 #define USE_COM2 0
@@ -543,11 +543,11 @@ void main(unsigned long bist) * here, we must be careful: * * 1. during this MTRR code, must no function call (after - * this MTRR, I think it should be OK to use function). + * this MTRR, I think it should be OK to use function). * 2. Before stack switch, no use variable that have value - * set before this. + * set before this. * 3. Due to 2, take care of "cpu_reset", I directlly set it - * to ZERO. + * to ZERO. */ u32 memtop = *(u32 *) WAKE_MEM_INFO; u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; diff --git a/src/mainboard/via/epia-m700/wakeup.c b/src/mainboard/via/epia-m700/wakeup.c index 28b8911..df8e49c 100644 --- a/src/mainboard/via/epia-m700/wakeup.c +++ b/src/mainboard/via/epia-m700/wakeup.c @@ -88,7 +88,7 @@ no_idt = { 0, 0 }; * occurred; hopefully real BIOSs don't assume much. */
-// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */ +// 0x66, 0x0d, 0x00, 0x00, 0x00, 0x60, /* orl $0x60000000, %eax */
static unsigned char real_mode_switch[] = { 0x66, 0x0f, 0x20, 0xc0, /* movl %cr0,%eax */ @@ -115,9 +115,9 @@ void acpi_jump_wake(u32 vector) jump_to_wakeup[2], jump_to_wakeup[3], jump_to_wakeup[4]);
memcpy((void *)(WAKE_THUNK16_ADDR - sizeof(real_mode_switch) - 100), - real_mode_switch, sizeof(real_mode_switch)); + real_mode_switch, sizeof(real_mode_switch)); memcpy((void *)(WAKE_THUNK16_ADDR - 100), jump_to_wakeup, - sizeof(jump_to_wakeup)); + sizeof(jump_to_wakeup));
//jason_tsc_count(); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); @@ -153,7 +153,7 @@ void acpi_jump_wake(u32 vector) dest[i] = src[i];
__asm__ __volatile__("ljmp $0x0010,%0" /* 08 error */ - ::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20))); + ::"i"((void *)(WAKE_RECOVER1M_CODE + 0x20)));
/* Added 0x20 "nop" to make sure the ljmp will not jump then halt. */ asm volatile ("nop"); diff --git a/src/mainboard/via/epia-m850/irq_tables.c b/src/mainboard/via/epia-m850/irq_tables.c index 28fbb4f..40e4d22 100644 --- a/src/mainboard/via/epia-m850/irq_tables.c +++ b/src/mainboard/via/epia-m850/irq_tables.c @@ -52,7 +52,7 @@ const struct irq_routing_table intel_irq_routing_table = { * would give 0 after the sum of all bytes * for this structure (including checksum). */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {_OFF, ___OFF}, {_OFF, ___OFF}}, 0x0, 0x0}, {0x00, (0x03 << 3) | 0x0, {{LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}, {LNKH, BITMAP}}, 0x0, 0x0}, {0x00, (0x0a << 3) | 0x0, {{LNKA, BITMAP}, {LNKB, B_SATA}, {LNKC, BITMAP}, {LNKD, BITMAP}}, 0x0, 0x0}, diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index dbe682c..05d7147 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -81,7 +81,7 @@ static int vx900_int15_handler(void) #endif default: printk(BIOS_DEBUG, "Unsupported INT15 call %04x!\n", - X86_AX & 0xffff); + X86_AX & 0xffff); X86_AX = 0; res = -1; break; diff --git a/src/mainboard/via/epia-n/acpi/irq_links.asl b/src/mainboard/via/epia-n/acpi/irq_links.asl index 29b2a1b..cbd26b7 100644 --- a/src/mainboard/via/epia-n/acpi/irq_links.asl +++ b/src/mainboard/via/epia-n/acpi/irq_links.asl @@ -45,33 +45,33 @@ IRQ (Level, ActiveLow, Shared, _Y07) {} }) - /* Read the Binary Encoded Field and Map this */ + /* Read the Binary Encoded Field and Map this */ /* onto the bitwise _INT field in the IRQ descriptor */ - /* See ACPI Spec for detail of _IRQ Descriptor */ - CreateByteField (BUFA, _SB.PCI0.LNKA._CRS._Y07._INT, IRA1) - CreateByteField (BUFA, 0x02, IRA2) - Store (0x00, Local3) - Store (0x00, Local4) - And (PIRA, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNotEqual (Local1, 0x00)) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRA1) - Store (Local4, IRA2) - } + /* See ACPI Spec for detail of _IRQ Descriptor */ + CreateByteField (BUFA, _SB.PCI0.LNKA._CRS._Y07._INT, IRA1) + CreateByteField (BUFA, 0x02, IRA2) + Store (0x00, Local3) + Store (0x00, Local4) + And (PIRA, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNotEqual (Local1, 0x00)) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRA1) + Store (Local4, IRA2) + } Return (BUFA) }
@@ -123,32 +123,32 @@ IRQ (Level, ActiveLow, Shared, _Y08) {} }) - /* Read the Binary Encoded Field and Map this */ + /* Read the Binary Encoded Field and Map this */ /* onto the bitwise _INT field in the IRQ descriptor */ - /* See ACPI Spec for detail of _IRQ Descriptor */ - CreateByteField (BUFB, _SB.PCI0.LNKB._CRS._Y08._INT, IRB1) - CreateByteField (BUFB, 0x02, IRB2) - Store (0x00, Local3) - Store (0x00, Local4) - And (PIBC, 0x0F, Local1) - If (LNotEqual (Local1, 0x00)) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRB1) - Store (Local4, IRB2) - } + /* See ACPI Spec for detail of _IRQ Descriptor */ + CreateByteField (BUFB, _SB.PCI0.LNKB._CRS._Y08._INT, IRB1) + CreateByteField (BUFB, 0x02, IRB2) + Store (0x00, Local3) + Store (0x00, Local4) + And (PIBC, 0x0F, Local1) + If (LNotEqual (Local1, 0x00)) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRB1) + Store (Local4, IRB2) + } Return (BUFB) }
@@ -201,33 +201,33 @@ IRQ (Level, ActiveLow, Shared, _Y09) {} }) - /* Read the Binary Encoded Field and Map this */ + /* Read the Binary Encoded Field and Map this */ /* onto the bitwise _INT field in the IRQ descriptor */ - /* See ACPI Spec for detail of _IRQ Descriptor */ - CreateByteField (BUFC, _SB.PCI0.LNKC._CRS._Y09._INT, IRC1) - CreateByteField (BUFC, 0x02, IRC2) - Store (0x00, Local3) - Store (0x00, Local4) - And (PIBC, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNotEqual (Local1, 0x00)) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRC1) - Store (Local4, IRC2) - } + /* See ACPI Spec for detail of _IRQ Descriptor */ + CreateByteField (BUFC, _SB.PCI0.LNKC._CRS._Y09._INT, IRC1) + CreateByteField (BUFC, 0x02, IRC2) + Store (0x00, Local3) + Store (0x00, Local4) + And (PIBC, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNotEqual (Local1, 0x00)) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRC1) + Store (Local4, IRC2) + } Return (BUFC) }
@@ -280,33 +280,33 @@ Device (LNKD) IRQ (Level, ActiveLow, Shared, _Y0A) {} }) - /* Read the Binary Encoded Field and Map this */ + /* Read the Binary Encoded Field and Map this */ /* onto the bitwise _INT field in the IRQ descriptor */ - /* See ACPI Spec for detail of _IRQ Descriptor */ - CreateByteField (BUFD, _SB.PCI0.LNKD._CRS._Y0A._INT, IRD1) - CreateByteField (BUFD, 0x02, IRD2) - Store (0x00, Local3) - Store (0x00, Local4) - And (PIRD, 0xF0, Local1) - ShiftRight (Local1, 0x04, Local1) - If (LNotEqual (Local1, 0x00)) - { - If (LGreater (Local1, 0x07)) - { - Subtract (Local1, 0x08, Local2) - ShiftLeft (One, Local2, Local4) - } - Else - { - If (LGreater (Local1, 0x00)) - { - ShiftLeft (One, Local1, Local3) - } - } - - Store (Local3, IRD1) - Store (Local4, IRD2) - } + /* See ACPI Spec for detail of _IRQ Descriptor */ + CreateByteField (BUFD, _SB.PCI0.LNKD._CRS._Y0A._INT, IRD1) + CreateByteField (BUFD, 0x02, IRD2) + Store (0x00, Local3) + Store (0x00, Local4) + And (PIRD, 0xF0, Local1) + ShiftRight (Local1, 0x04, Local1) + If (LNotEqual (Local1, 0x00)) + { + If (LGreater (Local1, 0x07)) + { + Subtract (Local1, 0x08, Local2) + ShiftLeft (One, Local2, Local4) + } + Else + { + If (LGreater (Local1, 0x00)) + { + ShiftLeft (One, Local1, Local3) + } + } + + Store (Local3, IRD1) + Store (Local4, IRD2) + } Return (BUFD) }
@@ -338,54 +338,54 @@ Device (ATAI) { /* Double Check By Reading SATA VID */ /* Otherwise Compatibility Mode */ - If (LNotEqual (_SB.PCI0.SATA.VID, 0x1106)) - { - Return (0x09) - } - Else - { - Return (0x0B) - } + If (LNotEqual (_SB.PCI0.SATA.VID, 0x1106)) + { + Return (0x09) + } + Else + { + Return (0x0B) + } } Else { /* Serial ATA Enabled Check if PATA is in */ /* Compatibility Mode */ - If (LEqual (_SB.PCI0.PATA.ENAT, 0x0A)) - { - Return (0x09) - } - Else - { - Return (0x0B) - } + If (LEqual (_SB.PCI0.PATA.ENAT, 0x0A)) + { + Return (0x09) + } + Else + { + Return (0x0B) + } } }
Method (_PRS, 0, NotSerialized) { - Name (ATAN, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) - { - 0x00000014, - } - }) + Name (ATAN, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000014, + } + }) Return (ATAN) }
Method (_CRS, 0, NotSerialized) { Name (ATAB, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y10) - { - 0x00000000, - } - }) - CreateByteField (ATAB, _SB.PCI0.ATAI._CRS._Y10._INT, IRAI) - Store (0x14, IRAI) - Return (ATAB) + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y10) + { + 0x00000000, + } + }) + CreateByteField (ATAB, _SB.PCI0.ATAI._CRS._Y10._INT, IRAI) + Store (0x14, IRAI) + Return (ATAB)
}
@@ -408,43 +408,43 @@ Device (USBI) Method (_STA, 0, NotSerialized) { /* Check that at least one of the USB */ - /* functions is enabled */ - And (IDEB, 0x37, Local0) - If (LEqual (Local0, 0x37)) - { - Return (0x09) - } - Else - { - Return (0x0B) - } + /* functions is enabled */ + And (IDEB, 0x37, Local0) + If (LEqual (Local0, 0x37)) + { + Return (0x09) + } + Else + { + Return (0x0B) + } }
Method (_PRS, 0, NotSerialized) { - Name (USBB, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) - { - 0x00000015, - } - }) + Name (USBB, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000015, + } + })
Return(USBB) }
Method (_CRS, 0, NotSerialized) { - Name (USBB, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y12) - { - 0x00000000, - } - }) - CreateByteField (USBB, _SB.PCI0.USBI._CRS._Y12._INT, IRBI) - Store (0x15, IRBI) - Return (USBB) + Name (USBB, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y12) + { + 0x00000000, + } + }) + CreateByteField (USBB, _SB.PCI0.USBI._CRS._Y12._INT, IRBI) + Store (0x15, IRBI) + Return (USBB) }
@@ -465,40 +465,40 @@ Device (VT8I) Method (_STA, 0, NotSerialized) { /* Check Whether Sound and/or Modem are Activated */ - If (LEqual (EAMC, 0x03)) - { - Return (0x09) - } - Else - { - Return (0x0B) - } + If (LEqual (EAMC, 0x03)) + { + Return (0x09) + } + Else + { + Return (0x0B) + } }
Method (_PRS, 0, NotSerialized) { - Name (A97C, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) - { - 0x00000016, - } - }) - Return (A97C) + Name (A97C, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000016, + } + }) + Return (A97C) }
Method (_CRS, 0, NotSerialized) { - Name (A97B, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y14) - { - 0x00000000, - } - }) - CreateByteField (A97B, _SB.PCI0.VT8I._CRS._Y14._INT, IRCI) - Store (0x16, IRCI) - Return (A97B) + Name (A97B, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y14) + { + 0x00000000, + } + }) + CreateByteField (A97B, _SB.PCI0.VT8I._CRS._Y14._INT, IRCI) + Store (0x16, IRCI) + Return (A97B) }
/* Set Resources - dummy function to keep Linux ACPI happy @@ -519,9 +519,9 @@ Device (NICI) Name (_UID, 0x0C) Method (_STA, 0, NotSerialized) { - /* Check if LAN Function is Enabled */ + /* Check if LAN Function is Enabled */ /* Note that LAN Enable Polarity is different */ - /* from other functions in VT8237R !? */ + /* from other functions in VT8237R !? */ If (LEqual (ELAN, 0x00)) { Return (0x09) @@ -534,28 +534,28 @@ Device (NICI)
Method (_PRS, 0, NotSerialized) { - Name (NICB, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) - { - 0x00000017, - } - }) - Return (NICB) + Name (NICB, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) + { + 0x00000017, + } + }) + Return (NICB) }
Method (_CRS, 0, NotSerialized) { - Name (NICD, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y16) - { - 0x00000000, - } - }) - CreateByteField (NICD, _SB.PCI0.NICI._CRS._Y16._INT, IRDI) - Store (0x17, IRDI) - Return (NICD) + Name (NICD, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _Y16) + { + 0x00000000, + } + }) + CreateByteField (NICD, _SB.PCI0.NICI._CRS._Y16._INT, IRDI) + Store (0x17, IRDI) + Return (NICD) }
/* Set Resources - dummy function to keep Linux ACPI happy diff --git a/src/mainboard/via/epia-n/acpi/pata_methods.asl b/src/mainboard/via/epia-n/acpi/pata_methods.asl index 6106fc9..ae8ecd6 100644 --- a/src/mainboard/via/epia-n/acpi/pata_methods.asl +++ b/src/mainboard/via/epia-n/acpi/pata_methods.asl @@ -11,38 +11,38 @@ Name (TIM0, Package (0x07) { Package (0x05) { - 0x78, 0xB4, 0xF0, 0x017F, 0x0258 + 0x78, 0xB4, 0xF0, 0x017F, 0x0258 },
Package (0x05) { - 0x20, 0x22, 0x33, 0x47, 0x5D + 0x20, 0x22, 0x33, 0x47, 0x5D },
Package (0x05) { - 0x04, 0x03, 0x02, 0x01, 0x00 + 0x04, 0x03, 0x02, 0x01, 0x00 },
Package (0x04) { - 0x02, 0x01, 0x00, 0x00 + 0x02, 0x01, 0x00, 0x00 },
Package (0x07) { - 0x78, 0x50, 0x3C, 0x2D, 0x1E, 0x14, 0x0F + 0x78, 0x50, 0x3C, 0x2D, 0x1E, 0x14, 0x0F },
Package (0x0F) { - 0x06, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,0x00 + 0x06, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,0x00 },
Package (0x07) { - 0x0E, 0x08, 0x06, 0x04, 0x02, 0x01, 0x00 + 0x0E, 0x08, 0x06, 0x04, 0x02, 0x01, 0x00 } })
@@ -62,42 +62,42 @@ Method (PMEX, 0, Serialized) { /* Check if these regs are still at defaults */ /* Board specific timing improvement if not */ - /* Already changed */ - If (LEqual (PMPT, 0xA8)) - { - Store (0x5D, PMPT) - } - - If (LEqual (PSPT, 0xA8)) - { - Store (0x5D, PSPT) - } - - If (LEqual (SMPT, 0xA8)) - { - Store (0x5D, SMPT) - } - - If (LEqual (SSPT, 0xA8)) - { - Store (0x5D, SSPT) - } + /* Already changed */ + If (LEqual (PMPT, 0xA8)) + { + Store (0x5D, PMPT) + } + + If (LEqual (PSPT, 0xA8)) + { + Store (0x5D, PSPT) + } + + If (LEqual (SMPT, 0xA8)) + { + Store (0x5D, SMPT) + } + + If (LEqual (SSPT, 0xA8)) + { + Store (0x5D, SSPT) + }
} }
/* This Method Provides the method that is used to */ -/* Reset ATA Drives to POST reset condition */ +/* Reset ATA Drives to POST reset condition */ Method (GTF, 4, Serialized) { Store (Buffer (0x07) - { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF - }, Local1) + { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF + }, Local1) Store (Buffer (0x07) - { - 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF - }, Local2) + { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF + }, Local2) CreateByteField (Local1, 0x01, MODE) CreateByteField (Local2, 0x01, UMOD) CreateByteField (Local1, 0x05, PCHA) @@ -105,28 +105,28 @@ Method (GTF, 4, Serialized) And (Arg0, 0x03, Local3) If (LEqual (And (Local3, 0x01), 0x01)) { - Store (0xB0, PCHA) - Store (0xB0, UCHA) + Store (0xB0, PCHA) + Store (0xB0, UCHA) }
If (Arg1) { - Store (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Arg2)), - UMOD) - Or (UMOD, 0x40, UMOD) + Store (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Arg2)), + UMOD) + Or (UMOD, 0x40, UMOD) } Else { - Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR, - 0x00, 0x00), Local0) - Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0 - )), UMOD) + Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR, + 0x00, 0x00), Local0) + Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0 + )), UMOD) }
Store (Match (DerefOf (Index (TIM0, 0x01)), MEQ, Arg3, MTR, - 0x00, 0x00), Local0) + 0x00, 0x00), Local0) Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0 - )), MODE) + )), MODE) Concatenate (Local1, Local2, Local6) Return (Local6) } diff --git a/src/mainboard/via/epia-n/acpi/pci_init.asl b/src/mainboard/via/epia-n/acpi/pci_init.asl index 3169a03..be31270 100644 --- a/src/mainboard/via/epia-n/acpi/pci_init.asl +++ b/src/mainboard/via/epia-n/acpi/pci_init.asl @@ -23,7 +23,7 @@ Method (_SB.PCI0._INI, 0, NotSerialized) { If (LNotEqual (_SB.PCI0.PATA.VID, 0x1106)) { - Store (0x01, ATFL) + Store (0x01, ATFL) } }
diff --git a/src/mainboard/via/epia-n/acpi/sb_physical.asl b/src/mainboard/via/epia-n/acpi/sb_physical.asl index 7dd7b1d..4a490cb 100644 --- a/src/mainboard/via/epia-n/acpi/sb_physical.asl +++ b/src/mainboard/via/epia-n/acpi/sb_physical.asl @@ -84,34 +84,34 @@ Device (SATA) Name (_ADR, 0x000F0000) Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.SATA.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.SATA.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.SATA.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.SATA.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } }
OperationRegion (SAPR, PCI_Config, 0x00, 0xC2) Field (SAPR, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - IDEI, 8, - Offset (0x49), - , 6, - EPHY, 1 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + IDEI, 8, + Offset (0x49), + , 6, + EPHY, 1 } }
@@ -123,35 +123,35 @@ Device (PATA) Name (REGF, 0x01) Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.PATA.VID, 0x1106)) - { - Return (0x00) - } - Else - { - PMEX () + If (LNotEqual (_SB.PCI0.PATA.VID, 0x1106)) + { + Return (0x00) + } + Else + { + PMEX () /* Check if the Interface is Enabled */ - If (LEqual (_SB.PCI0.PATA.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LEqual (_SB.PCI0.PATA.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } }
/* ACPI Spec says to check that regions are accessible */ - /* before trying to access them */ + /* before trying to access them */ Method (_REG, 2, NotSerialized) { /* Arg0 = Operating Region (0x02 == PCI_Config) */ - If (LEqual (Arg0, 0x02)) - { + If (LEqual (Arg0, 0x02)) + { /* Arg1 = Handler Connection Mode (0x01 == Connect) */ - Store (Arg1, REGF) - } + Store (Arg1, REGF) + } }
#include "pata_methods.asl" @@ -160,175 +160,175 @@ Device (PATA) OperationRegion (PAPR, PCI_Config, 0x00, 0xC2) Field (PAPR, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x09), - ENAT, 4, - Offset (0x3C), - IDEI, 8, - Offset (0x40), - ESCH, 1, - EPCH, 1, - Offset (0x48), - SSPT, 8, - SMPT, 8, - PSPT, 8, - PMPT, 8, - Offset (0x50), - SSUT, 4, - SSCT, 1, - SSUE, 3, - SMUT, 4, - SMCT, 1, - SMUE, 3, - PSUT, 4, - PSCT, 1, - PSUE, 3, - PMUT, 4, - PMCT, 1, - PMUE, 3 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x09), + ENAT, 4, + Offset (0x3C), + IDEI, 8, + Offset (0x40), + ESCH, 1, + EPCH, 1, + Offset (0x48), + SSPT, 8, + SMPT, 8, + PSPT, 8, + PMPT, 8, + Offset (0x50), + SSUT, 4, + SSCT, 1, + SSUE, 3, + SMUT, 4, + SMCT, 1, + SMUE, 3, + PSUT, 4, + PSCT, 1, + PSUE, 3, + PMUT, 4, + PMCT, 1, + PMUE, 3 }
Device (CHN0) { - Name (_ADR, 0x00) - Method (_STA, 0, NotSerialized) - { - If (LNotEqual (_SB.PCI0.PATA.EPCH, 0x01)) - { - Return (0x00) - } - Else - { - Return (0x0F) - } - } - - Device (DRV0) - { - Name (_ADR, 0x00) - Method (_GTF, 0, NotSerialized) - { - Return (GTF (0x00, PMUE, PMUT, PMPT)) - } - } - - Device (DRV1) - { - Name (_ADR, 0x01) - Method (_GTF, 0, NotSerialized) - { - Return (GTF (0x01, PSUE, PSUT, PSPT)) - } - } + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) + { + If (LNotEqual (_SB.PCI0.PATA.EPCH, 0x01)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + + Device (DRV0) + { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) + { + Return (GTF (0x00, PMUE, PMUT, PMPT)) + } + } + + Device (DRV1) + { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) + { + Return (GTF (0x01, PSUE, PSUT, PSPT)) + } + } }
Device (CHN1) { - Name (_ADR, 0x01) - Method (_STA, 0, NotSerialized) - { - If (LNotEqual (ATFL, 0x02)) - { - If (LEqual (_SB.PCI0.SATA.EPHY, 0x01)) - { - Return (0x00) - } - Else - { - If (LNotEqual (_SB.PCI0.PATA.ESCH, 0x01)) - { - Return (0x00) - } - Else - { - Return (0x0F) - } - } - } + Name (_ADR, 0x01) + Method (_STA, 0, NotSerialized) + { + If (LNotEqual (ATFL, 0x02)) + { + If (LEqual (_SB.PCI0.SATA.EPHY, 0x01)) + { + Return (0x00) + } + Else + { + If (LNotEqual (_SB.PCI0.PATA.ESCH, 0x01)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } + } Else { - If (LEqual (ATFL, 0x02)) - { - If (LNotEqual (_SB.PCI0.PATA.ESCH, 0x01)) - { - Return (0x00) - } - Else - { - Return (0x0F) - } - } + If (LEqual (ATFL, 0x02)) + { + If (LNotEqual (_SB.PCI0.PATA.ESCH, 0x01)) + { + Return (0x00) + } + Else + { + Return (0x0F) + } + } Else { Return(0x00) } } - } - - Device (DRV0) - { - Name (_ADR, 0x00) - Method (_GTF, 0, NotSerialized) - { - Return (GTF (0x02, SMUE, SMUT, SMPT)) - } - } - - Device (DRV1) - { - Name (_ADR, 0x01) - Method (_GTF, 0, NotSerialized) - { - Return (GTF (0x03, SSUE, SSUT, SSPT)) - } - } + } + + Device (DRV0) + { + Name (_ADR, 0x00) + Method (_GTF, 0, NotSerialized) + { + Return (GTF (0x02, SMUE, SMUT, SMPT)) + } + } + + Device (DRV1) + { + Name (_ADR, 0x01) + Method (_GTF, 0, NotSerialized) + { + Return (GTF (0x03, SSUE, SSUT, SSPT)) + } + } } } // End of PATA Device
/* Implement Basic USB Presence detect and */ -/* Power Management Event mask */ +/* Power Management Event mask */ Device (USB0) { Name (_ADR, 0x00100000) Name (_PRW, Package (0x02) { - 0x0E, - 0x03 + 0x0E, + 0x03 })
OperationRegion (U2F0, PCI_Config, 0x00, 0xC2) Field (U2F0, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - U0IR, 4, - Offset (0x84), - ECDX, 2 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + U0IR, 4, + Offset (0x84), + ECDX, 2 }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.USB0.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.USB0.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.USB0.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.USB0.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -337,39 +337,39 @@ Device (USB1) Name (_ADR, 0x00100001) Name (_PRW, Package (0x02) { - 0x0E, - 0x03 + 0x0E, + 0x03 })
OperationRegion (U2F1, PCI_Config, 0x00, 0xC2) Field (U2F1, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - U1IR, 4, - Offset (0x84), - ECDX, 2 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + U1IR, 4, + Offset (0x84), + ECDX, 2 }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.USB1.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.USB1.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.USB1.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.USB1.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -378,39 +378,39 @@ Device (USB2) Name (_ADR, 0x00100002) Name (_PRW, Package (0x02) { - 0x0E, - 0x03 + 0x0E, + 0x03 })
OperationRegion (U2F2, PCI_Config, 0x00, 0xC2) Field (U2F2, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - U2IR, 4, - Offset (0x84), - ECDX, 2 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + U2IR, 4, + Offset (0x84), + ECDX, 2 }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.USB2.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.USB2.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.USB2.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.USB2.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -419,39 +419,39 @@ Device (USB3) Name (_ADR, 0x00100003) Name (_PRW, Package (0x02) { - 0x0E, - 0x03 + 0x0E, + 0x03 })
OperationRegion (U2F3, PCI_Config, 0x00, 0xC2) Field (U2F3, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - U3IR, 4, - Offset (0x84), - ECDX, 2 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + U3IR, 4, + Offset (0x84), + ECDX, 2 }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.USB3.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.USB3.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.USB3.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.USB3.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -460,39 +460,39 @@ Device (USB4) Name (_ADR, 0x00100004) Name (_PRW, Package (0x02) { - 0x0E, - 0x03 + 0x0E, + 0x03 })
OperationRegion (U2F4, PCI_Config, 0x00, 0xC2) Field (U2F4, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - U4IR, 4, - Offset (0x84), - ECDX, 2 + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + U4IR, 4, + Offset (0x84), + ECDX, 2 }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.USB4.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.USB4.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.USB4.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.USB4.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -502,37 +502,37 @@ Device (NIC0) Name (_ADR, 0x00120000) Name (_PRW, Package (0x02) { - 0x03, - 0x05 + 0x03, + 0x05 })
OperationRegion (NIC0, PCI_Config, 0x00, 0xC2) Field (NIC0, ByteAcc, NoLock, Preserve) { - VID, 16, - Offset (0x04), - CMDR, 3, - Offset (0x3C), - NIIR, 4, + VID, 16, + Offset (0x04), + CMDR, 3, + Offset (0x3C), + NIIR, 4, }
Method (_STA, 0, NotSerialized) { - If (LNotEqual (_SB.PCI0.NIC0.VID, 0x1106)) - { - Return (0x00) - } - Else - { - If (LEqual (_SB.PCI0.NIC0.CMDR, 0x00)) - { - Return (0x0D) - } - Else - { - Return (0x0F) - } - } + If (LNotEqual (_SB.PCI0.NIC0.VID, 0x1106)) + { + Return (0x00) + } + Else + { + If (LEqual (_SB.PCI0.NIC0.CMDR, 0x00)) + { + Return (0x0D) + } + Else + { + Return (0x0F) + } + } } }
@@ -542,7 +542,7 @@ Device (AC97) Name (_ADR, 0x00110005) Name (_PRW, Package (0x02) { - 0x0D, - 0x05 + 0x0D, + 0x05 }) } diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c index 5558dcb..209b404 100644 --- a/src/mainboard/via/epia-n/acpi_tables.c +++ b/src/mainboard/via/epia-n/acpi_tables.c @@ -48,11 +48,11 @@ extern const unsigned char AmlCode[]; #define MP_IRQ_POLARITY_DEFAULT 0x0 #define MP_IRQ_POLARITY_HIGH 0x1 #define MP_IRQ_POLARITY_LOW 0x3 -#define MP_IRQ_POLARITY_MASK 0x3 +#define MP_IRQ_POLARITY_MASK 0x3 #define MP_IRQ_TRIGGER_DEFAULT 0x0 #define MP_IRQ_TRIGGER_EDGE 0x4 #define MP_IRQ_TRIGGER_LEVEL 0xc -#define MP_IRQ_TRIGGER_MASK 0xc +#define MP_IRQ_TRIGGER_MASK 0xc
unsigned long acpi_fill_mcfg(unsigned long current) { @@ -80,7 +80,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, if (!cpu->enabled) continue; current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) - current, cpu_index, flags, lint); + current, cpu_index, flags, lint); cpu_index++; } return current; @@ -107,7 +107,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Create all subtables for processors. */ current = acpi_create_madt_lapic_nmis(current, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
return current; } @@ -129,7 +129,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_header_t *dsdt;
/* Align ACPI tables to 16byte */ - start = ALIGN(start, 16); + start = ALIGN(start, 16); current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); diff --git a/src/mainboard/via/epia-n/cmos.layout b/src/mainboard/via/epia-n/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/via/epia-n/cmos.layout +++ b/src/mainboard/via/epia-n/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/epia-n/devicetree.cb b/src/mainboard/via/epia-n/devicetree.cb index d17b96d..0f22b17 100644 --- a/src/mainboard/via/epia-n/devicetree.cb +++ b/src/mainboard/via/epia-n/devicetree.cb @@ -44,8 +44,8 @@ chip northbridge/via/cn400 # Northbridge register "ide1_80pin_cable" = "0" device pci f.0 on end # IDE/SATA device pci f.1 on end # IDE - register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97 - register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating + register "fn_ctrl_lo" = "0xC0" # Disable AC/MC97 + register "fn_ctrl_hi" = "0x9d" # Disable USB Direct & LAN Gating device pci 10.0 on end # OHCI device pci 10.1 on end # OHCI device pci 10.2 on end # OHCI @@ -53,45 +53,45 @@ chip northbridge/via/cn400 # Northbridge device pci 10.4 on end # EHCI device pci 10.5 off end # USB Direct device pci 11.0 on # Southbridge LPC - chip superio/winbond/w83697hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.6 off # IR Port - io 0x60 = 0x000 - end - device pnp 2e.7 off # GPIO 1 - io 0x60 = 0x201 # 0x201 - end - device pnp 2e.8 off # GPIO 5 - io 0x60 = 0x330 # 0x330 - end - device pnp 2e.9 off # GPIO 2, 3,and 4 - io 0x60 = 0x000 # - end - device pnp 2e.a off # ACPI - io 0x60 = 0x000 # - end - device pnp 2e.b on # HWM - io 0x60 = 0x290 + chip superio/winbond/w83697hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off # IR Port + io 0x60 = 0x000 + end + device pnp 2e.7 off # GPIO 1 + io 0x60 = 0x201 # 0x201 + end + device pnp 2e.8 off # GPIO 5 + io 0x60 = 0x330 # 0x330 + end + device pnp 2e.9 off # GPIO 2, 3,and 4 + io 0x60 = 0x000 # + end + device pnp 2e.a off # ACPI + io 0x60 = 0x000 # + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 irq 0x70 = 0 - end - end + end + end end device pci 11.5 off end # AC'97 audio device pci 11.6 off end # AC'97 Modem diff --git a/src/mainboard/via/epia-n/dsdt.asl b/src/mainboard/via/epia-n/dsdt.asl index e50ee6b..561f220 100644 --- a/src/mainboard/via/epia-n/dsdt.asl +++ b/src/mainboard/via/epia-n/dsdt.asl @@ -9,7 +9,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1) { Scope (_PR) { - Processor (_PR.CPU0, 0x00, 0x00000000, 0x00) {} + Processor (_PR.CPU0, 0x00, 0x00000000, 0x00) {} }
/* For now only define 2 power states: @@ -19,21 +19,21 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1) */ Name (_S0, Package (0x04) { - 0x00, - 0x00, - 0x00, - 0x00 + 0x00, + 0x00, + 0x00, + 0x00 }) Name (_S5, Package (0x04) { - 0x02, - 0x02, - 0x02, - 0x02 + 0x02, + 0x02, + 0x02, + 0x02 })
/* Global Flag Used to Indicate State of */ - /* ATA Interface */ + /* ATA Interface */ Name (ATFL, 0x00)
/* Root of the bus hierarchy */ @@ -42,50 +42,50 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1)
Device (PCI0) { - Name (_HID, EisaId ("PNP0A03")) - Name (_ADR, 0x00) - Name (_UID, 0x01) - Name (_BBN, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x01) + Name (_BBN, 0x00)
- /* PCI Routing Table */ - Name (_PRT, Package () { + /* PCI Routing Table */ + Name (_PRT, Package () {
- Package (0x04) {0x000FFFFF, 0x00, ATAI, 0x00}, // SATA Link A - Package (0x04) {0x000FFFFF, 0x01, ATAI, 0x00}, // SATA Link B - Package (0x04) {0x000FFFFF, 0x02, ATAI, 0x00}, // SATA Link C - Package (0x04) {0x000FFFFF, 0x03, ATAI, 0x00}, // SATA Link D + Package (0x04) {0x000FFFFF, 0x00, ATAI, 0x00}, // SATA Link A + Package (0x04) {0x000FFFFF, 0x01, ATAI, 0x00}, // SATA Link B + Package (0x04) {0x000FFFFF, 0x02, ATAI, 0x00}, // SATA Link C + Package (0x04) {0x000FFFFF, 0x03, ATAI, 0x00}, // SATA Link D
- Package (0x04) {0x0010FFFF, 0x00, USBI, 0x00}, // USB Link A - Package (0x04) {0x0010FFFF, 0x01, USBI, 0x00}, // USB Link B - Package (0x04) {0x0010FFFF, 0x02, USBI, 0x00}, // USB Link C - Package (0x04) {0x0010FFFF, 0x03, USBI, 0x00}, // USB Link D + Package (0x04) {0x0010FFFF, 0x00, USBI, 0x00}, // USB Link A + Package (0x04) {0x0010FFFF, 0x01, USBI, 0x00}, // USB Link B + Package (0x04) {0x0010FFFF, 0x02, USBI, 0x00}, // USB Link C + Package (0x04) {0x0010FFFF, 0x03, USBI, 0x00}, // USB Link D
- Package (0x04) {0x0011FFFF, 0x00, VT8I, 0x00}, // VT8237 Link A - Package (0x04) {0x0011FFFF, 0x01, VT8I, 0x00}, // VT8237 Link B - Package (0x04) {0x0011FFFF, 0x02, VT8I, 0x00}, // VT8237 Link C - Package (0x04) {0x0011FFFF, 0x03, VT8I, 0x00}, // VT8237 Link D + Package (0x04) {0x0011FFFF, 0x00, VT8I, 0x00}, // VT8237 Link A + Package (0x04) {0x0011FFFF, 0x01, VT8I, 0x00}, // VT8237 Link B + Package (0x04) {0x0011FFFF, 0x02, VT8I, 0x00}, // VT8237 Link C + Package (0x04) {0x0011FFFF, 0x03, VT8I, 0x00}, // VT8237 Link D
- Package (0x04) {0x0012FFFF, 0x00, NICI, 0x00}, // LAN Link A - Package (0x04) {0x0012FFFF, 0x01, NICI, 0x00}, // LAN Link B - Package (0x04) {0x0012FFFF, 0x02, NICI, 0x00}, // LAN Link C - Package (0x04) {0x0012FFFF, 0x03, NICI, 0x00}, // LAN Link D + Package (0x04) {0x0012FFFF, 0x00, NICI, 0x00}, // LAN Link A + Package (0x04) {0x0012FFFF, 0x01, NICI, 0x00}, // LAN Link B + Package (0x04) {0x0012FFFF, 0x02, NICI, 0x00}, // LAN Link C + Package (0x04) {0x0012FFFF, 0x03, NICI, 0x00}, // LAN Link D
- Package (0x04) {0x0001FFFF, 0x00, 0, 0x10}, // VGA Link A (GSI) - Package (0x04) {0x0001FFFF, 0x01, 0, 0x11}, // VGA Link B (GSI) - Package (0x04) {0x0001FFFF, 0x02, 0, 0x12}, // VGA Link C (GSI) - Package (0x04) {0x0001FFFF, 0x03, 0, 0x13}, // VGA Link D (GSI) + Package (0x04) {0x0001FFFF, 0x00, 0, 0x10}, // VGA Link A (GSI) + Package (0x04) {0x0001FFFF, 0x01, 0, 0x11}, // VGA Link B (GSI) + Package (0x04) {0x0001FFFF, 0x02, 0, 0x12}, // VGA Link C (GSI) + Package (0x04) {0x0001FFFF, 0x03, 0, 0x13}, // VGA Link D (GSI)
- Package (0x04) {0x0014FFFF, 0x00, 0, 0x12}, // Slot 1 Link C (GSI) - Package (0x04) {0x0014FFFF, 0x01, 0, 0x13}, // Slot 1 Link D (GSI) - Package (0x04) {0x0014FFFF, 0x02, 0, 0x10}, // Slot 1 Link A (GSI) - Package (0x04) {0x0014FFFF, 0x03, 0, 0x11}, // Slot 1 Link B (GSI) + Package (0x04) {0x0014FFFF, 0x00, 0, 0x12}, // Slot 1 Link C (GSI) + Package (0x04) {0x0014FFFF, 0x01, 0, 0x13}, // Slot 1 Link D (GSI) + Package (0x04) {0x0014FFFF, 0x02, 0, 0x10}, // Slot 1 Link A (GSI) + Package (0x04) {0x0014FFFF, 0x03, 0, 0x11}, // Slot 1 Link B (GSI)
- Package (0x04) {0x0013FFFF, 0x00, 0, 0x13}, // Riser Slot Link D (GSI) - Package (0x04) {0x0013FFFF, 0x01, 0, 0x12}, // Riser Slot Link C (GSI) - Package (0x04) {0x0013FFFF, 0x02, 0, 0x11}, // Riser Slot Link B (GSI) - Package (0x04) {0x0013FFFF, 0x03, 0, 0x10} // Riser Slot Link A (GSI) + Package (0x04) {0x0013FFFF, 0x00, 0, 0x13}, // Riser Slot Link D (GSI) + Package (0x04) {0x0013FFFF, 0x01, 0, 0x12}, // Riser Slot Link C (GSI) + Package (0x04) {0x0013FFFF, 0x02, 0, 0x11}, // Riser Slot Link B (GSI) + Package (0x04) {0x0013FFFF, 0x03, 0, 0x10} // Riser Slot Link A (GSI)
- }) + })
/* PCI Devices Included Here */ #include "acpi/sb_physical.asl" @@ -93,255 +93,255 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CBT-V2", "CBT-DSDT", 1) /* Legacy PNP Devices Defined Here */
/* Disable PS2 Mouse Support */ - Device (PS2M) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { Return (0x09) - } + }
- Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - IRQNoFlags () - {12} - }) - Return (BUF1) - } - } + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + IRQNoFlags () + {12} + }) + Return (BUF1) + } + }
/* Disable Legacy PS2 Keyboard Support */ - Device (PS2K) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, 0x0B03D041) - Method (_STA, 0, NotSerialized) - { - Return (0x09) - } + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, 0x0B03D041) + Method (_STA, 0, NotSerialized) + { + Return (0x09) + }
- Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0060, // Range Minimum - 0x0060, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IO (Decode16, - 0x0064, // Range Minimum - 0x0064, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - IRQNoFlags () - {1} - }) - } + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + }
/* Legacy PIC Description */ - Device (PIC) - { - Name (_HID, EisaId ("PNP0000")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0020, // Range Minimum - 0x0020, // Range Maximum - 0x01, // Alignment - 0x02, // Length - ) - IO (Decode16, - 0x00A0, // Range Minimum - 0x00A0, // Range Maximum - 0x01, // Alignment - 0x02, // Length - ) - IRQNoFlags () - {2} - }) - } + Device (PIC) + { + Name (_HID, EisaId ("PNP0000")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0020, // Range Minimum + 0x0020, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + IO (Decode16, + 0x00A0, // Range Minimum + 0x00A0, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + IRQNoFlags () + {2} + }) + }
/* Legacy DMA Description */ - Device (DMA1) - { - Name (_HID, EisaId ("PNP0200")) - Name (_CRS, ResourceTemplate () - { - DMA (Compatibility, BusMaster, Transfer8, ) - {4} - IO (Decode16, - 0x0000, // Range Minimum - 0x0000, // Range Maximum - 0x01, // Alignment - 0x10, // Length - ) - IO (Decode16, - 0x0080, // Range Minimum - 0x0080, // Range Maximum - 0x01, // Alignment - 0x11, // Length - ) - IO (Decode16, - 0x0094, // Range Minimum - 0x0094, // Range Maximum - 0x01, // Alignment - 0x0C, // Length - ) - IO (Decode16, - 0x00C0, // Range Minimum - 0x00C0, // Range Maximum - 0x01, // Alignment - 0x20, // Length - ) - }) - } + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200")) + Name (_CRS, ResourceTemplate () + { + DMA (Compatibility, BusMaster, Transfer8, ) + {4} + IO (Decode16, + 0x0000, // Range Minimum + 0x0000, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + IO (Decode16, + 0x0080, // Range Minimum + 0x0080, // Range Maximum + 0x01, // Alignment + 0x11, // Length + ) + IO (Decode16, + 0x0094, // Range Minimum + 0x0094, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + IO (Decode16, + 0x00C0, // Range Minimum + 0x00C0, // Range Maximum + 0x01, // Alignment + 0x20, // Length + ) + }) + }
/* Legacy Timer Description */ - Device (TMR) - { - Name (_HID, EisaId ("PNP0100")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0040, // Range Minimum - 0x0040, // Range Maximum - 0x01, // Alignment - 0x04, // Length - ) - IRQNoFlags () - {0} - }) - } + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0040, // Range Minimum + 0x0040, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + IRQNoFlags () + {0} + }) + }
/* Legacy RTC Description */ - Device (RTC) - { - Name (_HID, EisaId ("PNP0B00")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0070, // Range Minimum - 0x0070, // Range Maximum - 0x04, // Alignment - 0x04, // Length - ) - IRQNoFlags () - {8} - }) - } + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x04, // Alignment + 0x04, // Length + ) + IRQNoFlags () + {8} + }) + }
/* Legacy Speaker Description */ - Device (SPKR) - { - Name (_HID, EisaId ("PNP0800")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0061, // Range Minimum - 0x0061, // Range Maximum - 0x01, // Alignment - 0x01, // Length - ) - }) - } + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0061, // Range Minimum + 0x0061, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + }) + }
/* Legacy Math Co-Processor Description */ - Device (COPR) - { - Name (_HID, EisaId ("PNP0C04")) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x00F0, // Range Minimum - 0x00F0, // Range Maximum - 0x01, // Alignment - 0x10, // Length - ) - IRQNoFlags () - {13} - }) - } + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x00F0, // Range Minimum + 0x00F0, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + IRQNoFlags () + {13} + }) + }
- /* General Legacy IO Reservations */ + /* General Legacy IO Reservations */ /* Covering items that are not explicitly reserved */ - /* from coreboot. */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x01) - Name (_CRS, ResourceTemplate () - { - IO (Decode16, - 0x0010, // Range Minimum - 0x0010, // Range Maximum - 0x01, // Alignment - 0x10, // Length - ) - IO (Decode16, - 0x0022, // Range Minimum - 0x0022, // Range Maximum - 0x01, // Alignment - 0x1E, // Length - ) - IO (Decode16, - 0x0044, // Range Minimum - 0x0044, // Range Maximum - 0x01, // Alignment - 0x1C, // Length - ) - IO (Decode16, - 0x0062, // Range Minimum - 0x0062, // Range Maximum - 0x01, // Alignment - 0x02, // Length - ) - IO (Decode16, - 0x0065, // Range Minimum - 0x0065, // Range Maximum - 0x01, // Alignment - 0x0B, // Length - ) - IO (Decode16, - 0x0074, // Range Minimum - 0x0074, // Range Maximum - 0x01, // Alignment - 0x0C, // Length - ) - IO (Decode16, - 0x0091, // Range Minimum - 0x0091, // Range Maximum - 0x01, // Alignment - 0x03, // Length - ) - IO (Decode16, - 0x00A2, // Range Minimum - 0x00A2, // Range Maximum - 0x01, // Alignment - 0x1E, // Length - ) - IO (Decode16, - 0x00E0, // Range Minimum - 0x00E0, // Range Maximum - 0x01, // Alignment - 0x10, // Length - ) - IO (Decode16, - 0x04D0, // Range Minimum - 0x04D0, // Range Maximum - 0x01, // Alignment - 0x02, // Length - ) - IO (Decode16, - 0x0294, // Range Minimum - 0x0294, // Range Maximum - 0x01, // Alignment - 0x04, // Length - ) - }) - } + /* from coreboot. */ + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0010, // Range Minimum + 0x0010, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + IO (Decode16, + 0x0022, // Range Minimum + 0x0022, // Range Maximum + 0x01, // Alignment + 0x1E, // Length + ) + IO (Decode16, + 0x0044, // Range Minimum + 0x0044, // Range Maximum + 0x01, // Alignment + 0x1C, // Length + ) + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + IO (Decode16, + 0x0065, // Range Minimum + 0x0065, // Range Maximum + 0x01, // Alignment + 0x0B, // Length + ) + IO (Decode16, + 0x0074, // Range Minimum + 0x0074, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + IO (Decode16, + 0x0091, // Range Minimum + 0x0091, // Range Maximum + 0x01, // Alignment + 0x03, // Length + ) + IO (Decode16, + 0x00A2, // Range Minimum + 0x00A2, // Range Maximum + 0x01, // Alignment + 0x1E, // Length + ) + IO (Decode16, + 0x00E0, // Range Minimum + 0x00E0, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + IO (Decode16, + 0x04D0, // Range Minimum + 0x04D0, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + IO (Decode16, + 0x0294, // Range Minimum + 0x0294, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + }
#include "acpi/irq_links.asl" #include "acpi/pci_init.asl" diff --git a/src/mainboard/via/epia-n/irq_tables.c b/src/mainboard/via/epia-n/irq_tables.c index 9c1ee4e..21eb968 100644 --- a/src/mainboard/via/epia-n/irq_tables.c +++ b/src/mainboard/via/epia-n/irq_tables.c @@ -15,10 +15,10 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ - (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ + (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */ 0x1c00, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ 0x3227, /* Device */ @@ -28,7 +28,7 @@ static const struct irq_routing_table intel_irq_routing_table = { value that would give 0 after the sum of all bytes for this structure (including checksum) */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x14<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x1, 0x0}, {0x00,(0x13<<3)|0x0, {{0x05, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x01, 0xdeb8}}, 0x2, 0x0}, {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c index de25d0e..b16877e 100644 --- a/src/mainboard/via/epia-n/mptable.c +++ b/src/mainboard/via/epia-n/mptable.c @@ -9,15 +9,15 @@
static void *smp_write_config_table(void *v) { - struct mp_config_table *mc; - int isa_bus; + struct mp_config_table *mc; + int isa_bus;
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
- smp_write_processors(mc); - mptable_write_buses(mc, NULL, &isa_bus); + smp_write_processors(mc); + mptable_write_buses(mc, NULL, &isa_bus);
/*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); diff --git a/src/mainboard/via/epia/cmos.layout b/src/mainboard/via/epia/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/via/epia/cmos.layout +++ b/src/mainboard/via/epia/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/epia/devicetree.cb b/src/mainboard/via/epia/devicetree.cb index d5e16ac..82392b9 100644 --- a/src/mainboard/via/epia/devicetree.cb +++ b/src/mainboard/via/epia/devicetree.cb @@ -8,28 +8,28 @@ chip northbridge/via/vt8601 register "enable_native_ide" = "0" register "enable_com_ports" = "1" register "enable_keyboard" = "0" - device pci 11.0 on # Southbrdge + device pci 11.0 on # Southbrdge chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 + io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 + io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end @@ -49,13 +49,13 @@ chip northbridge/via/vt8601 device pci 11.4 off end # ACPI device pci 11.5 off end # AC97 Audio device pci 11.6 on end # AC97 Modem - device pci 12.0 on end # Ethernet - end + device pci 12.0 on end # Ethernet + end end
- device cpu_cluster 0 on - chip cpu/via/c3 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/via/c3 + device lapic 0 on end + end + end end diff --git a/src/mainboard/via/epia/irq_tables.c b/src/mainboard/via/epia/irq_tables.c index 94adba1..e7e4bd1 100644 --- a/src/mainboard/via/epia/irq_tables.c +++ b/src/mainboard/via/epia/irq_tables.c @@ -9,16 +9,16 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0, /* Where the interrupt router lies (bus) */ - 0x88, /* Where the interrupt router lies (dev) */ - 0x1c20, /* IRQs devoted exclusively to PCI usage */ - 0x1106, /* Vendor */ - 0x8231, /* Device */ - 0, /* Miniport data */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + 0x88, /* Where the interrupt router lies (dev) */ + 0x1c20, /* IRQs devoted exclusively to PCI usage */ + 0x1106, /* Vendor */ + 0x8231, /* Device */ + 0, /* Miniport data */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x5e, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* 8231 ethernet */ {0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0}, @@ -32,5 +32,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/via/pc2500e/cmos.layout b/src/mainboard/via/pc2500e/cmos.layout index fa5dc4c..5a01620 100644 --- a/src/mainboard/via/pc2500e/cmos.layout +++ b/src/mainboard/via/pc2500e/cmos.layout @@ -21,45 +21,45 @@ entries
#start-bit length config config-ID name -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy
checksums diff --git a/src/mainboard/via/pc2500e/devicetree.cb b/src/mainboard/via/pc2500e/devicetree.cb index 17bc35e..a246506 100644 --- a/src/mainboard/via/pc2500e/devicetree.cb +++ b/src/mainboard/via/pc2500e/devicetree.cb @@ -26,55 +26,55 @@ chip northbridge/via/cn700 # Northbridge device pci 10.4 on end # EHCI device pci 10.5 on end # UDCI device pci 11.0 on # Southbridge LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # COM2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 9 - end - device pnp 2e.5 off # PS/2 keyboard (not used) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # PS/2 mouse (not used) - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x0000 - io 0x62 = 0x0800 - io 0x64 = 0x0000 - end - device pnp 2e.8 off # MIDI port (N/A) - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # Game port (N/A) - io 0x60 = 0x201 - end - device pnp 2e.a on # Consumer IR - io 0x60 = 0x310 - irq 0x70 = 11 - end - end + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # COM2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x0000 + irq 0x70 = 9 + end + device pnp 2e.5 off # PS/2 keyboard (not used) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # PS/2 mouse (not used) + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x0000 + io 0x62 = 0x0800 + io 0x64 = 0x0000 + end + device pnp 2e.8 off # MIDI port (N/A) + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # Game port (N/A) + io 0x60 = 0x201 + end + device pnp 2e.a on # Consumer IR + io 0x60 = 0x310 + irq 0x70 = 11 + end + end end device pci 11.5 on end # AC'97 audio # device pci 11.6 off end # AC'97 modem (N/A) diff --git a/src/mainboard/via/pc2500e/irq_tables.c b/src/mainboard/via/pc2500e/irq_tables.c index b9818c0..ffa59bc 100644 --- a/src/mainboard/via/pc2500e/irq_tables.c +++ b/src/mainboard/via/pc2500e/irq_tables.c @@ -33,7 +33,7 @@ static const struct irq_routing_table intel_irq_routing_table = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x3e, /* Checksum */ { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x08<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0x0def8}}, 0x1, 0x0}, {0x00,(0x09<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0x0def8}}, 0x2, 0x0}, {0x00,(0x0a<<3)|0x0, {{0x03, 0xdef8}, {0x05, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x3, 0x0}, diff --git a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl index 1505683..640b5d1 100644 --- a/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl +++ b/src/mainboard/via/vt8454c/acpi/irq-p2p-bridge.asl @@ -20,7 +20,7 @@ */
Name (PICM, Package () { - // _ADR PIN SRC IDX + // _ADR PIN SRC IDX
Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }, Package () { 0x0003FFFF, 0x01, LNKB, 0x00 }, diff --git a/src/mainboard/via/vt8454c/acpi/irq.asl b/src/mainboard/via/vt8454c/acpi/irq.asl index a0bc380..28b4de7 100644 --- a/src/mainboard/via/vt8454c/acpi/irq.asl +++ b/src/mainboard/via/vt8454c/acpi/irq.asl @@ -20,7 +20,7 @@ */
Name (PICM, Package () { - // _ADR PIN SRC IDX + // _ADR PIN SRC IDX
Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, @@ -121,9 +121,9 @@ Name (APIC, Package () { Package () { 0x000FFFFF, 0x03, LNKA, 0x00 },
/* USB controller. Hardwired in internal - APIC mode, see PM pg. 137, - "miscellaneous controls", footnote to - "IDE interrupt select" */ + APIC mode, see PM pg. 137, + "miscellaneous controls", footnote to + "IDE interrupt select" */ Package () { 0x0010FFFF, 0x00, 0x00, 0x14 }, Package () { 0x0010FFFF, 0x01, 0x00, 0x16 }, Package () { 0x0010FFFF, 0x02, 0x00, 0x15 }, diff --git a/src/mainboard/via/vt8454c/cmos.layout b/src/mainboard/via/vt8454c/cmos.layout index e80bb94..7fe0b9c 100644 --- a/src/mainboard/via/vt8454c/cmos.layout +++ b/src/mainboard/via/vt8454c/cmos.layout @@ -21,42 +21,42 @@ entries
#start-bit length config config-ID name -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -1008 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb index 87d2ed1..f400c3f 100644 --- a/src/mainboard/via/vt8454c/devicetree.cb +++ b/src/mainboard/via/vt8454c/devicetree.cb @@ -11,7 +11,7 @@ chip northbridge/via/cx700 device pci 0.3 on end # Memory Controller device pci 0.4 on end # Power Management device pci 0.7 on end # V-Link Controller - device pci 1.0 on # PCI Bridge + device pci 1.0 on # PCI Bridge device pci 0.0 on end # Onboard Video end # PCI Bridge device pci f.0 on end # IDE/SATA @@ -20,7 +20,7 @@ chip northbridge/via/cx700 device pci 10.1 on end # USB 1.1 device pci 10.2 on end # USB 1.1 device pci 10.4 on end # USB 2.0 - device pci 11.0 on # Southbridge LPC + device pci 11.0 on # Southbridge LPC chip superio/via/vt1211 device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 diff --git a/src/mainboard/via/vt8454c/dsdt.asl b/src/mainboard/via/vt8454c/dsdt.asl index d0ec7db..b881549 100644 --- a/src/mainboard/via/vt8454c/dsdt.asl +++ b/src/mainboard/via/vt8454c/dsdt.asl @@ -76,7 +76,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -85,10 +85,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + })
If (LNot (PICF)) { Return (PRSP) @@ -96,9 +96,9 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) }
- } + } /* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -135,7 +135,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -144,10 +144,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + })
If (LNot (PICF)) { Return (PRSP) @@ -155,10 +155,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) }
- } + }
/* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -195,7 +195,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -204,10 +204,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + })
If (LNot (PICF)) { Return (PRSP) @@ -215,10 +215,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) }
- } + }
/* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -255,7 +255,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) } Else { Return (CRSA) } - } + } /* Possible Resources - return the range of irqs * we are using for PCI - only here to keep Linux ACPI * happy @@ -264,10 +264,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) { Name (PRSP, ResourceTemplate () { IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12} - }) + }) Name (PRSA, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23} - }) + })
If (LNot (PICF)) { Return (PRSP) @@ -275,10 +275,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) Return (PRSA) }
- } + }
/* Set Resources - dummy function to keep Linux ACPI happy - * Linux is more than happy not to tinker with irq + * Linux is more than happy not to tinker with irq * assignments as long as the CRS and STA functions * return good values */ @@ -301,17 +301,17 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001) #include "acpi/irq.asl"
/* PCI Routing Table */ - Method (_PRT, 0, NotSerialized) - { - If (LNot (PICF)) - { - Return (PICM) - } - Else - { - Return (APIC) - } - } + Method (_PRT, 0, NotSerialized) + { + If (LNot (PICF)) + { + Return (PICM) + } + Else + { + Return (APIC) + } + }
Device (P2PB) /* PCI to PCI bridge */ { diff --git a/src/mainboard/via/vt8454c/irq_tables.c b/src/mainboard/via/vt8454c/irq_tables.c index a4cb0b1..f86b677 100644 --- a/src/mainboard/via/vt8454c/irq_tables.c +++ b/src/mainboard/via/vt8454c/irq_tables.c @@ -23,7 +23,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c index fc9cb99..9ebf72a 100644 --- a/src/mainboard/via/vt8454c/mptable.c +++ b/src/mainboard/via/vt8454c/mptable.c @@ -40,12 +40,12 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus);
- /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, 2, 17, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x40, 0x2, 0x14); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x41, 0x2, 0x16); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x42, 0x2, 0x15); @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x2, 0x10, 0x2, 0x11);
- /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, 0x0);
/* Compute the checksums */ diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 1b59fbb..1615e74 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -44,7 +44,7 @@ unsigned long acpi_fill_madt(unsigned long current) ASSERT(res != NULL);
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4, - res->base, 0); + res->base, 0); /* Initialize interrupt mapping if mptable.c didn't. */ #if (!CONFIG_GENERATE_MP_TABLE) pci_write_config32(dev, 0x7c, 0x0120d218); diff --git a/src/mainboard/winent/mb6047/cmos.layout b/src/mainboard/winent/mb6047/cmos.layout index 924934c..bedb2da 100644 --- a/src/mainboard/winent/mb6047/cmos.layout +++ b/src/mainboard/winent/mb6047/cmos.layout @@ -1,95 +1,95 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM -8 0 DDR400 -8 1 DDR333 -8 2 DDR266 -8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5%
checksums
diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 09a062e..77a199b 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -8,107 +8,107 @@ chip northbridge/amd/amdk8/root_complex # Root complex subsystemid 0x10de 0xcb84 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, MIDI, GPIO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end - end - # device pci 1.1 on # SM 1 - # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - # device i2c 2d on end - # end - # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - # device i2c 2e on end - # end - # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - # device i2c 2a on end - # end - # chip drivers/generic/generic # Winbond HWM 0x92 - # device i2c 49 on end - # end - # chip drivers/generic/generic # Winbond HWM 0x94 - # device i2c 4a on end - # end - # end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # device pci 6.0 on end - end - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "0" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # device pci 6.0 on end + end + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "0" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end end device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 2 == LDT 2 diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 5b96b05..159360f 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -64,8 +64,8 @@ void get_bus_conf(void) bus_ck804_4++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x09); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_4 = 3; @@ -78,8 +78,8 @@ void get_bus_conf(void) bus_ck804_5++; } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0d); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4 + 1; } @@ -89,8 +89,8 @@ void get_bus_conf(void) bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { printk(BIOS_DEBUG, - "ERROR - could not find PCI 1:%02x.0, using defaults\n", - sbdn + 0x0e); + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x0e); }
/*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/winent/pl6064/cmos.layout b/src/mainboard/winent/pl6064/cmos.layout index c1354a2..3bb338e 100644 --- a/src/mainboard/winent/pl6064/cmos.layout +++ b/src/mainboard/winent/pl6064/cmos.layout @@ -1,69 +1,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/winent/pl6064/irq_tables.c b/src/mainboard/winent/pl6064/irq_tables.c index db9dfdc..eee872a 100644 --- a/src/mainboard/winent/pl6064/irq_tables.c +++ b/src/mainboard/winent/pl6064/irq_tables.c @@ -44,7 +44,7 @@
static const struct irq_routing_table intel_irq_routing_table = { PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ + PIRQ_VERSION, /* u16 version */ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ @@ -53,10 +53,10 @@ static const struct irq_routing_table intel_irq_routing_table = { 0x002B, /* Device */ 0, /* Miniport data */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ { /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ {0x00, (0x09 << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet 0*/ diff --git a/src/mainboard/wyse/s50/cmos.layout b/src/mainboard/wyse/s50/cmos.layout index e561358..7298f2d 100644 --- a/src/mainboard/wyse/s50/cmos.layout +++ b/src/mainboard/wyse/s50/cmos.layout @@ -24,69 +24,69 @@ entries
#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory -388 4 r 0 reboot_bits -392 3 e 5 baud_rate -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -1008 16 h 0 check_sum +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum
enumerations
#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD 7 10 Fallback_Floppy #7 3 ROM
diff --git a/src/mainboard/wyse/s50/irq_tables.c b/src/mainboard/wyse/s50/irq_tables.c index bf4ac7a..0c640ba 100644 --- a/src/mainboard/wyse/s50/irq_tables.c +++ b/src/mainboard/wyse/s50/irq_tables.c @@ -52,9 +52,9 @@ static const struct irq_routing_table intel_irq_routing_table = { 0xdc, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). - */ + */ { - /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0}, {0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0}, {0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0}, diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index d5c039f..bd1d673 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -18,8 +18,8 @@ #
config NORTHBRIDGE_AMD_AGESA - bool - default CPU_AMD_AGESA + bool + default CPU_AMD_AGESA
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/agesa/family10/amdfam10.h b/src/northbridge/amd/agesa/family10/amdfam10.h index 0026803..b1316c1 100644 --- a/src/northbridge/amd/agesa/family10/amdfam10.h +++ b/src/northbridge/amd/agesa/family10/amdfam10.h @@ -22,13 +22,13 @@
#include <cpu/x86/msr.h>
-#define HWCR_MSR 0xC0010015 -#define NB_CFG_MSR 0xC001001f -#define LS_CFG_MSR 0xC0011020 -#define IC_CFG_MSR 0xC0011021 -#define DC_CFG_MSR 0xC0011022 -#define BU_CFG_MSR 0xC0011023 -#define BU_CFG2_MSR 0xC001102A +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define BU_CFG_MSR 0xC0011023 +#define BU_CFG2_MSR 0xC001102A
#define CPU_ID_FEATURES_MSR 0xC0011004 #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 @@ -50,10 +50,10 @@ #define HTTC_RSP_PASS_PW (1 << 11) #define HTTC_BUF_REL_PRI_SHIFT 13 #define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 #define HTTC_LIMIT_CLDT_CFG (1 << 15) #define HTTC_LINT_EN (1 << 16) #define HTTC_APIC_EXT_BRD_CST (1 << 17) @@ -62,10 +62,10 @@ #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 #define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3
/* Function 1 */
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1c7e547..868c17b 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -46,8 +46,8 @@ extern uint32_t agesawrapper_amdinitmid(void);
typedef struct amdfam10_sysconf_t sys_info_conf_t; typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 } dram_base_mask_t;
@@ -263,7 +263,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, for (i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -373,9 +373,9 @@ static device_t get_node_pci(u32 nodeid, u32 fn)
static unsigned int read_nb_cfg_54(void) { - msr_t msr; - msr = rdmsr(NB_CFG_MSR); - return (( msr.hi >> (54-32)) & 1); + msr_t msr; + msr = rdmsr(NB_CFG_MSR); + return (( msr.hi >> (54-32)) & 1); }
static void get_fx_devs(void) @@ -1054,7 +1054,7 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); + i, mmio_basek, basek, limitk); if (!ramtop) ramtop = limitk * 1024; } diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index eb539d6..6fc4d05 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -126,7 +126,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -234,7 +234,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index e6be598..09ab50b 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -61,15 +61,15 @@ static void get_fx_devs(void) { int i; for(i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; } if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); + die("Cannot find 0:0x18.[0|1]\n"); } }
@@ -77,7 +77,7 @@ static void get_fx_devs(void) static u32 f1_read_config32(unsigned reg) { if (fx_devs == 0) - get_fx_devs(); + get_fx_devs(); return pci_read_config32(__f1_dev[0], reg); }
@@ -86,13 +86,13 @@ static void f1_write_config32(unsigned reg, u32 value) { int i; if (fx_devs == 0) - get_fx_devs(); + get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } } }
@@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, - unsigned goal_link) + unsigned goal_link) { struct resource *res; unsigned nodeid, link = 0; @@ -136,22 +136,22 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for(link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for(link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } } result = 2; if (res) { - result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); return result; @@ -163,20 +163,20 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi u32 result, reg; resource = 0; reg = 0; - result = reg_useable(0xc0, dev, nodeid, link); - if (result >= 1) { - /* I have been allocated this one */ - reg = 0xc0; + result = reg_useable(0xc0, dev, nodeid, link); + if (result >= 1) { + /* I have been allocated this one */ + reg = 0xc0; }
//Ext conf space if(!reg) { - //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range - u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range + u32 index = get_io_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 }
- resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
return resource; } @@ -188,28 +188,28 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link resource = 0; free_reg = 0; for(reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } } if (reg > 0xb8) { - reg = free_reg; + reg = free_reg; }
//Ext conf space if(!reg) { - //because of Extend conf space, we will never run out of reg, - // but we need one index to differ them. so same node and - // same link can have multi range - u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + //because of Extend conf space, we will never run out of reg, + // but we need one index to differ them. so same node and + // same link can have multi range + u32 index = get_mmio_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
} resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); @@ -225,37 +225,37 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) /* Initialize the io space constraints on the current bus */ resource = amdfam12_find_iopair(dev, nodeid, link); if (resource) { - u32 align; + u32 align; #if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - align = 8; - } - else + if((resource->index & 0x1fff) == 0x1110) { // ext + align = 8; + } + else #endif - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; }
/* Initialize the prefetchable memory constraints on the current bus */ resource = amdfam12_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE;
#if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } + if((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } #endif
} @@ -263,16 +263,16 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) /* Initialize the memory constraints on the current bus */ resource = amdfam12_find_mempair(dev, nodeid, link); if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; #if CONFIG_EXT_CONF_SUPPORT - if((resource->index & 0x1fff) == 0x1110) { // ext - normalize_resource(resource); - } + if((resource->index & 0x1fff) == 0x1110) { // ext + normalize_resource(resource); + } #endif } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -284,7 +284,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) min = 0; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); if (min && tolm > min->base) { - tolm = min->base; + tolm = min->base; } return tolm; } @@ -298,46 +298,46 @@ struct hw_mem_hole_info {
static struct hw_mem_hole_info get_hw_mem_hole_info(void) { - struct hw_mem_hole_info mem_hole; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - struct dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(0); - if(d.mask & 1) { - hole = pci_read_config32(__f1_dev[0], 0xf0); - if(hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = 0; // record the node No with hole - } - } + struct hw_mem_hole_info mem_hole; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + struct dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(0); + if(d.mask & 1) { + hole = pci_read_config32(__f1_dev[0], 0xf0); + if(hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = 0; // record the node No with hole + } + }
#if 0 - // We need to double check if there is speical set on base reg and limit reg - // are not continous instead of hole, it will find out it's hole_startk - if(mem_hole.node_id==-1) { - resource_t limitk_pri = 0; - struct dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(0); - if(d.base & 1) { - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if(base_k <= 4 *1024 * 1024) { - if(limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G - mem_hole.node_id = 0; - } - } - - limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } + // We need to double check if there is speical set on base reg and limit reg + // are not continous instead of hole, it will find out it's hole_startk + if(mem_hole.node_id==-1) { + resource_t limitk_pri = 0; + struct dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(0); + if(d.base & 1) { + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if(base_k <= 4 *1024 * 1024) { + if(limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G + mem_hole.node_id = 0; + } + } + + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } #endif
- return mem_hole; + return mem_hole; } #endif
@@ -350,16 +350,16 @@ static void read_resources(device_t dev)
nodeid = amdfam12_nodeid(dev); for(link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam12_link_read_bases(dev, nodeid, link->link_num); - } + if (link->children) { + amdfam12_link_read_bases(dev, nodeid, link->link_num); + } } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }
static void set_resource(device_t dev, struct resource *resource, - u32 nodeid) + u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -369,21 +369,21 @@ static void set_resource(device_t dev, struct resource *resource,
/* Make certain the resource has actually been set */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; + return; }
/* If I have already stored this resource don't worry about it */ if (resource->flags & IORESOURCE_STORED) { - return; + return; }
/* Only handle PCI memory and IO resources */ if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; + return;
/* Ensure I am actually looking at a resource of function 1 */ if ((resource->index & 0xffff) < 0x1000) { - return; + return; } /* Get the base address */ rbase = resource->base; @@ -396,14 +396,14 @@ static void set_resource(device_t dev, struct resource *resource, link_num = IOINDEX_LINK(resource->index);
if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); } else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] } resource->flags |= IORESOURCE_STORED; sprintf(buf, " <node %x link %x>", - nodeid, link_num); + nodeid, link_num); report_resource_stored(dev, resource, buf); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -422,22 +422,22 @@ static void create_vga_resource(device_t dev, unsigned nodeid) /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) #endif - break; - } + break; + } }
/* no VGA card installed */ if (link == NULL) - return; + return;
printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); set_vga_enable_reg(nodeid, link->link_num); @@ -460,13 +460,13 @@ static void set_resources(device_t dev)
/* Set each resource we have found */ for(res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); + set_resource(dev, res, nodeid); }
for(bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } + if (bus->children) { + assign_resources(bus); + } } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -480,10 +480,10 @@ static void setup_uma_memory(void) /* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M */ sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { @@ -495,7 +495,7 @@ static void setup_uma_memory(void) } uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); + __func__, uma_memory_size, uma_memory_base); #endif }
@@ -510,29 +510,29 @@ static void domain_read_resources(device_t dev) /* Find the already assigned resource pairs */ get_fx_devs(); for(reg = 0x80; reg <= 0xc0; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned nodeid, reg_link; - device_t reg_dev; - if(reg<0xc0) { // mmio - nodeid = (limit & 0xf) + (base&0x30); - } else { // io - nodeid = (limit & 0xf) + ((base>>4)&0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if(reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } } /* FIXME: do we need to check extend conf space? I don't believe that much preset value */ @@ -558,21 +558,21 @@ static void domain_read_resources(device_t dev) struct bus *link; struct resource *resource; for(link=dev->link_list; link; link = link->next) { - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0|(link->link_num<<2)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2|(link->link_num<<2)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; } #endif printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -602,57 +602,57 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); for(link = dev->link_list; link; link = link->next) { - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1|(link->link_num<<2)); - mem2 = find_resource(dev, 2|(link->link_num<<2)); - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); }
for(res = &dev->resource_list; res; res = res->next) { - res->flags |= IORESOURCE_ASSIGNED; - res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, ""); + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); } #endif
pci_tolm = 0xffffffffUL; for(link = dev->link_list; link; link = link->next) { - pci_tolm = my_find_pci_tolm(link, pci_tolm); + pci_tolm = my_find_pci_tolm(link, pci_tolm); }
// FIXME handle interleaved nodes. If you fix this here, please fix @@ -677,8 +677,8 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
// Use hole_basek as mmio_basek, and we don't need to reset hole anymore if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; } #endif
@@ -690,59 +690,59 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); d = get_dram_base_mask(0);
if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + basek = ((resource_t)(d.base)) << 8; + limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
- /* Convert these values to multiples of 1K for ease of math. */ - basek >>= 10; - limitk >>= 10; - sizek = limitk - basek + 1; + /* Convert these values to multiples of 1K for ease of math. */ + basek >>= 10; + limitk >>= 10; + sizek = limitk - basek + 1;
printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
- /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < 640) && (sizek > 768)) { + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < 640) && (sizek > 768)) { printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); - ram_resource(dev, (idx | 0), basek, 640 - basek); - idx += 0x10; - basek = 768; - sizek = limitk - 768; - } + ram_resource(dev, (idx | 0), basek, 640 - basek); + idx += 0x10; + basek = 768; + sizek = limitk - 768; + }
printk(BIOS_DEBUG, "adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", mmio_basek, basek, limitk);
- /* split the region to accomodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { - if (basek <= mmio_basek) { - unsigned pre_sizek; - pre_sizek = mmio_basek - basek; - if(pre_sizek>0) { - ram_resource(dev, idx, basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - if (!ramtop) - ramtop = mmio_basek * 1024; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - - ram_resource(dev, (idx | 0), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - 0, mmio_basek, basek, limitk); - if (!ramtop) - ramtop = limitk * 1024; + /* split the region to accomodate pci memory space */ + if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if(pre_sizek>0) { + ram_resource(dev, idx, basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + if (!ramtop) + ramtop = mmio_basek * 1024; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + + ram_resource(dev, (idx | 0), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + 0, mmio_basek, basek, limitk); + if (!ramtop) + ramtop = limitk * 1024; } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
@@ -754,9 +754,9 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); #endif
for(link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } + if (link->children) { + assign_resources(link); + } } printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -790,7 +790,7 @@ static void cpu_bus_read_resources(device_t dev) resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; #endif printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -801,7 +801,7 @@ static void cpu_bus_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); + report_resource_stored(dev, resource, " <mmconfig>"); } pci_dev_set_resources(dev); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -832,7 +832,7 @@ static void cpu_bus_init(device_t dev) printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - agesawrapper_amdinitmid - Start.\n",__func__); val = agesawrapper_amdinitmid (); if(val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - agesawrapper_amdinitmid - End.\n",__func__); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); @@ -845,9 +845,9 @@ static struct device_operations northbridge_operations = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
@@ -871,8 +871,8 @@ static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .init = NULL, + .scan_bus = pci_domain_scan_bus, };
@@ -880,8 +880,8 @@ static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_read_resources, .set_resources = cpu_bus_set_resources, .enable_resources = NULL, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
@@ -900,10 +900,10 @@ static void root_complex_enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; + dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; + dev->ops = &cpu_bus_ops; } printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index d302db3..737f5cc 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -126,7 +126,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -234,7 +234,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index a3f5bb3..f630a95 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -37,7 +37,7 @@ * address and offset. Following bytes auto increment. */ static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, - int offset, int initial_offset) + int offset, int initial_offset) { unsigned int status = -1; UINT64 time_limit; diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.h b/src/northbridge/amd/agesa/family14/dimmSpd.h index 57512c7..1a9b90f 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.h +++ b/src/northbridge/amd/agesa/family14/dimmSpd.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -26,7 +26,7 @@ #define _DIMMSPD_H_
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
@@ -58,17 +58,17 @@
#define SMBUS_FREQUENCY_CONST 66000000 / 4 /*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -76,7 +76,7 @@ AGESA_STATUS agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData);
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 7cc812b..3625efe 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -118,7 +118,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) }
static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, - unsigned goal_link) + unsigned goal_link) { struct resource *res; unsigned nodeid, link = 0; @@ -145,7 +145,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, }
static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, - unsigned link) + unsigned link) { struct resource *resource; u32 result, reg; @@ -172,7 +172,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, }
static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, - u32 link) + u32 link) { struct resource *resource; u32 free_reg, reg; @@ -269,7 +269,7 @@ static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) struct resource *min; min = 0; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, - &min); + &min); if (min && tolm > min->base) { tolm = min->base; } @@ -502,7 +502,7 @@ static void domain_read_resources(device_t dev) /* Reserve the resource */ struct resource *res; res = - new_resource(reg_dev, + new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); if (res) { @@ -714,7 +714,7 @@ static void domain_set_resources(device_t dev) pre_sizek = mmio_basek - basek; if (pre_sizek > 0) { ram_resource(dev, idx, basek, - pre_sizek); + pre_sizek); idx += 0x10; sizek -= pre_sizek; if (!ramtop) diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c index 294454c..f08e70b 100644 --- a/src/northbridge/amd/agesa/family15/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15/dimmSpd.c @@ -36,7 +36,7 @@ * address and offset. Following bytes auto increment. */ static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, - int offset, int initial_offset) + int offset, int initial_offset) { unsigned int status = -1; UINT64 time_limit; @@ -110,10 +110,10 @@ UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer,
static void setupFch(UINT16 ioBase) { - AMD_CONFIG_PARAMS StdHeader; - UINT32 PciData32; - UINT8 PciData8; - PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress;
/* Set SMBus MMIO. */ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.h b/src/northbridge/amd/agesa/family15/dimmSpd.h index 167b4a1..8e8cc23 100644 --- a/src/northbridge/amd/agesa/family15/dimmSpd.h +++ b/src/northbridge/amd/agesa/family15/dimmSpd.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -26,7 +26,7 @@ #define _DIMMSPD_H_
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
@@ -60,17 +60,17 @@
#define SMBUS_FREQUENCY_CONST 66000000 / 4 /*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -90,7 +90,7 @@ agesa_ReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT void *SpdData); UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset);
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index a8cc1cc..81aa0c9 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -89,7 +89,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for (i=0; i<node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -656,10 +656,10 @@ static void setup_uma_memory(void) /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M */ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { @@ -1057,7 +1057,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ #define CFG_PLAT_NUM_IO_APICS 3 #endif diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index 28c0002..bc001fe 100755 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -55,7 +55,7 @@ Device(PBR2) { Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { If(PMOD){ Return(APS2) } /* APIC mode */ - Return (PS2) /* PIC Mode */ + Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */
diff --git a/src/northbridge/amd/agesa/family15tn/amdfam15_conf.c b/src/northbridge/amd/agesa/family15tn/amdfam15_conf.c index 291b7f9..32947ef 100644 --- a/src/northbridge/amd/agesa/family15tn/amdfam15_conf.c +++ b/src/northbridge/amd/agesa/family15tn/amdfam15_conf.c @@ -126,7 +126,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -232,7 +232,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 5b8a9b5..a440860 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -42,11 +42,11 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
address |= 1; // set read bit
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command
// time limit to avoid hanging for unexpected error status (should never happen) limit = __rdtsc () + 2000000000 / 10; @@ -54,20 +54,20 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) { status = __inbyte (iobase); if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting break; }
buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + if (status == 2) status = 0; // check for done with no errors return status; }
/*----------------------------------------------------------------------------- * * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData + * this function is faster function readSmbusByteData */
static int readSmbusByte (int iobase, int address, char *buffer) @@ -75,8 +75,8 @@ static int readSmbusByte (int iobase, int address, char *buffer) unsigned int status; UINT64 limit;
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status limit = __rdtsc () + 2000000000 / 10; @@ -84,23 +84,23 @@ static int readSmbusByte (int iobase, int address, char *buffer) { status = __inbyte (iobase); if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting break; }
buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + if (status == 2) status = 0; // check for done with no errors return status; }
/*--------------------------------------------------------------------------- * * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. */
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) @@ -143,11 +143,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA if ((dev == 0) || (config == 0)) return AGESA_ERROR;
- if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) return AGESA_ERROR;
spdAddress = config->spdAddrLookup diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.h b/src/northbridge/amd/agesa/family15tn/dimmSpd.h index e50d53e..cb093ec 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.h +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -26,22 +26,22 @@ #define _DIMMSPD_H_
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -49,7 +49,7 @@ AGESA_STATUS AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 38bf975..e3f225c 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -52,14 +52,14 @@ static AGESA_STATUS alloc_cbmem(AGESA_BUFFER_PARAMS *AllocParams) {
AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -185,12 +185,12 @@ AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS fam15tn_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -303,8 +303,8 @@ AGESA_STATUS fam15tn_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr
AGESA_STATUS fam15tn_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -343,11 +343,11 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS fam15tn_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -363,9 +363,9 @@ AGESA_STATUS fam15tn_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS fam15tn_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -399,7 +399,7 @@ AGESA_STATUS fam15tn_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS fam15tn_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index b55d52b..5d09597 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -88,7 +88,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for (i=0; i<node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -642,10 +642,10 @@ static void setup_uma_memory(void) /* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M */ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { @@ -1044,7 +1044,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ #define CFG_PLAT_NUM_IO_APICS 3 #endif diff --git a/src/northbridge/amd/agesa/family16kb/amdfam16_conf.c b/src/northbridge/amd/agesa/family16kb/amdfam16_conf.c index 291b7f9..32947ef 100644 --- a/src/northbridge/amd/agesa/family16kb/amdfam16_conf.c +++ b/src/northbridge/amd/agesa/family16kb/amdfam16_conf.c @@ -126,7 +126,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ dev = NODE_PCI(i, 1); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); @@ -232,7 +232,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit pci_write_config32(__f1_dev[0], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 1d9363c..43cb4fa 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -42,11 +42,11 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
address |= 1; // set read bit
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command
// time limit to avoid hanging for unexpected error status (should never happen) limit = __rdtsc () + 2000000000 / 10; @@ -54,20 +54,20 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset) { status = __inbyte (iobase); if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting break; }
buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + if (status == 2) status = 0; // check for done with no errors return status; }
/*----------------------------------------------------------------------------- * * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData + * this function is faster function readSmbusByteData */
static int readSmbusByte (int iobase, int address, char *buffer) @@ -75,8 +75,8 @@ static int readSmbusByte (int iobase, int address, char *buffer) unsigned int status; UINT64 limit;
- __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status limit = __rdtsc () + 2000000000 / 10; @@ -84,23 +84,23 @@ static int readSmbusByte (int iobase, int address, char *buffer) { status = __inbyte (iobase); if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting break; }
buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors + if (status == 2) status = 0; // check for done with no errors return status; }
/*--------------------------------------------------------------------------- * * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. */
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) @@ -143,11 +143,11 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA if ((dev == 0) || (config == 0)) return AGESA_ERROR;
- if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) return AGESA_ERROR;
spdAddress = config->spdAddrLookup diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.h b/src/northbridge/amd/agesa/family16kb/dimmSpd.h index e50d53e..cb093ec 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.h +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.h @@ -18,7 +18,7 @@ */
/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D + * M O D U L E S U S E D *---------------------------------------------------------------------------------------- */
@@ -26,22 +26,22 @@ #define _DIMMSPD_H_
/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S + * D E F I N I T I O N S A N D M A C R O S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S + * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S + * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -49,7 +49,7 @@ AGESA_STATUS AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S + * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */
diff --git a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c index eed8d40..762a4df 100644 --- a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c +++ b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c @@ -29,14 +29,14 @@
AGESA_STATUS fam16kb_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -158,12 +158,12 @@ AGESA_STATUS fam16kb_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS fam16kb_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) {
- UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -276,8 +276,8 @@ AGESA_STATUS fam16kb_DeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr
AGESA_STATUS fam16kb_LocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AllocNodeOffset; - UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; @@ -316,11 +316,11 @@ CONST IDS_NV_ITEM IdsData[] = } };
-#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
AGESA_STATUS fam16kb_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINTN i; + UINTN i; IDS_NV_ITEM *IdsPtr;
IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; @@ -336,9 +336,9 @@ AGESA_STATUS fam16kb_GetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS fam16kb_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINT8 Value; - UINTN ResetType; + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader;
ResetType = Data; @@ -372,7 +372,7 @@ AGESA_STATUS fam16kb_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS fam16kb_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; + AGESA_STATUS Status;
Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); return Status; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b8bba50..286e8d5 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -88,7 +88,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit for (i=0; i<node_nums; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { @@ -646,10 +646,10 @@ static void setup_uma_memory(void) /* refer to UMA Size Consideration in Family16h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M */ sys_mem = topmem + (16 << ONE_MB_SHIFT); // Ignore 16MB allocated for C6 when finding UMA size if ((bsp_topmem2()>>32) || (sys_mem >= 2048 << ONE_MB_SHIFT)) { @@ -1050,7 +1050,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * * This is needed because many IO-APIC devices only have 4 bits * for their APIC id and therefore must reside at 0..15 - */ + */ #ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ #define CFG_PLAT_NUM_IO_APICS 3 #endif diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 73da579..d49afdb 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -59,8 +59,8 @@ config MMCONF_BUS_NUMBER default 256
config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" + string + default "northbridge/amd/amdfam10/bootblock.c"
config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool @@ -113,8 +113,8 @@ endif config SVI_HIGH_FREQ bool default n - help - Select this for boards with a Voltage Regulator able to operate - at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. + help + Select this for boards with a Voltage Regulator able to operate + at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
endif # NORTHBRIDGE_AMD_AMDFAM10 diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index eded515..1882669 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -37,10 +37,10 @@ #define HTTC_RSP_PASS_PW (1 << 11) #define HTTC_BUF_REL_PRI_SHIFT 13 #define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 #define HTTC_LIMIT_CLDT_CFG (1 << 15) #define HTTC_LINT_EN (1 << 16) #define HTTC_APIC_EXT_BRD_CST (1 << 17) @@ -49,10 +49,10 @@ #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 #define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3
/* Function 1 */ @@ -124,147 +124,147 @@ #define DM_MprEn (1<<26) /* DDR3 */
#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 0xf -#define DTL_TCL_BASE 1 /* DDR3 =4 */ -#define DTL_TCL_MIN 3 /* DDR3 =4 */ -#define DTL_TCL_MAX 6 /* DDR3 =12 */ +#define DTL_TCL_SHIFT 0 +#define DTL_TCL_MASK 0xf +#define DTL_TCL_BASE 1 /* DDR3 =4 */ +#define DTL_TCL_MIN 3 /* DDR3 =4 */ +#define DTL_TCL_MAX 6 /* DDR3 =12 */ #define DTL_TRCD_SHIFT 4 -#define DTL_TRCD_MASK 3 /* DDR3 =7 */ +#define DTL_TRCD_MASK 3 /* DDR3 =7 */ #define DTL_TRCD_BASE 3 /* DDR3 =5 */ -#define DTL_TRCD_MIN 3 /* DDR3 =5 */ -#define DTL_TRCD_MAX 6 /* DDR3 =12 */ -#define DTL_TRP_SHIFT 8 /* DDR3 =7 */ -#define DTL_TRP_MASK 3 /* DDR3 =7 */ -#define DTL_TRP_BASE 3 /* DDR3 =5 */ -#define DTL_TRP_MIN 3 /* DDR3 =5 */ -#define DTL_TRP_MAX 6 /* DDR3 =12 */ +#define DTL_TRCD_MIN 3 /* DDR3 =5 */ +#define DTL_TRCD_MAX 6 /* DDR3 =12 */ +#define DTL_TRP_SHIFT 8 /* DDR3 =7 */ +#define DTL_TRP_MASK 3 /* DDR3 =7 */ +#define DTL_TRP_BASE 3 /* DDR3 =5 */ +#define DTL_TRP_MIN 3 /* DDR3 =5 */ +#define DTL_TRP_MAX 6 /* DDR3 =12 */ #define DTL_TRTP_SHIFT 11 /*DDR3 =10 */ -#define DTL_TRTP_MASK 1 /*DDR3 =3 */ +#define DTL_TRTP_MASK 1 /*DDR3 =3 */ #define DTL_TRTP_BASE 2 /* DDR3 =4 */ -#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */ -#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */ +#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ /* DDR3 =4 for 32bytes or 64bytes */ +#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ /* DDR3 =7 for 32Bytes or 64bytes */ #define DTL_TRAS_SHIFT 12 -#define DTL_TRAS_MASK 0xf +#define DTL_TRAS_MASK 0xf #define DTL_TRAS_BASE 3 /* DDR3 =15 */ -#define DTL_TRAS_MIN 5 /* DDR3 =15 */ -#define DTL_TRAS_MAX 18 /*DDR3 =30 */ -#define DTL_TRC_SHIFT 16 -#define DTL_TRC_MASK 0xf /* DDR3 =0x1f */ -#define DTL_TRC_BASE 11 -#define DTL_TRC_MIN 11 -#define DTL_TRC_MAX 26 /* DDR3 =43 */ -#define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */ -#define DTL_TWR_MASK 3 -#define DTL_TWR_BASE 3 -#define DTL_TWR_MIN 3 -#define DTL_TWR_MAX 6 -#define DTL_TRRD_SHIFT 22 -#define DTL_TRRD_MASK 3 -#define DTL_TRRD_BASE 2 /* DDR3 =4 */ -#define DTL_TRRD_MIN 2 /* DDR3 =4 */ -#define DTL_TRRD_MAX 5 /* DDR3 =7 */ -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ -#define DTL_MemClkDis3 (1 << 26) -#define DTL_MemClkDis2 (1 << 27) -#define DTL_MemClkDis1 (1 << 28) -#define DTL_MemClkDis0 (1 << 29) +#define DTL_TRAS_MIN 5 /* DDR3 =15 */ +#define DTL_TRAS_MAX 18 /*DDR3 =30 */ +#define DTL_TRC_SHIFT 16 +#define DTL_TRC_MASK 0xf /* DDR3 =0x1f */ +#define DTL_TRC_BASE 11 +#define DTL_TRC_MIN 11 +#define DTL_TRC_MAX 26 /* DDR3 =43 */ +#define DTL_TWR_SHIFT 20 /* only for DDR2, DDR3's is on DC */ +#define DTL_TWR_MASK 3 +#define DTL_TWR_BASE 3 +#define DTL_TWR_MIN 3 +#define DTL_TWR_MAX 6 +#define DTL_TRRD_SHIFT 22 +#define DTL_TRRD_MASK 3 +#define DTL_TRRD_BASE 2 /* DDR3 =4 */ +#define DTL_TRRD_MIN 2 /* DDR3 =4 */ +#define DTL_TRRD_MAX 5 /* DDR3 =7 */ +#define DTL_MemClkDis_SHIFT 24 /* Channel A */ +#define DTL_MemClkDis3 (1 << 26) +#define DTL_MemClkDis2 (1 << 27) +#define DTL_MemClkDis1 (1 << 28) +#define DTL_MemClkDis0 (1 << 29) /* DTL_MemClkDis for m2 and s1g1 is different */
#define DRAM_TIMING_HIGH 0x8c #define DTH_TRWTWB_SHIFT 0 #define DTH_TRWTWB_MASK 3 -#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */ -#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */ -#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */ +#define DTH_TRWTWB_BASE 3 /* DDR3 =4 */ +#define DTH_TRWTWB_MIN 3 /* DDR3 =5 */ +#define DTH_TRWTWB_MAX 10 /* DDR3 =11 */ #define DTH_TRWTTO_SHIFT 4 #define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */ -#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */ +#define DTH_TRWTTO_BASE 2 /* DDR3 =3 */ +#define DTH_TRWTTO_MIN 2 /* DDR3 =3 */ +#define DTH_TRWTTO_MAX 9 /* DDR3 =10 */ #define DTH_TWTR_SHIFT 8 -#define DTH_TWTR_MASK 3 +#define DTH_TWTR_MASK 3 #define DTH_TWTR_BASE 0 /* DDR3 =4 */ -#define DTH_TWTR_MIN 1 /* DDR3 =4 */ -#define DTH_TWTR_MAX 3 /* DDR3 =7 */ +#define DTH_TWTR_MIN 1 /* DDR3 =4 */ +#define DTH_TWTR_MAX 3 /* DDR3 =7 */ #define DTH_TWRRD_SHIFT 10 #define DTH_TWRRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ #define DTH_TWRRD_BASE 0 /* DDR3 =0 */ #define DTH_TWRRD_MIN 0 /* DDR3 =2 */ #define DTH_TWRRD_MAX 3 /* DDR3 =12 */ #define DTH_TWRWR_SHIFT 12 -#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TWRWR_BASE 1 -#define DTH_TWRWR_MIN 1 /* DDR3 =3 */ -#define DTH_TWRWR_MAX 3 /* DDR3 =12 */ +#define DTH_TWRWR_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ +#define DTH_TWRWR_BASE 1 +#define DTH_TWRWR_MIN 1 /* DDR3 =3 */ +#define DTH_TWRWR_MAX 3 /* DDR3 =12 */ #define DTH_TRDRD_SHIFT 14 -#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ -#define DTH_TRDRD_BASE 2 -#define DTH_TRDRD_MIN 2 -#define DTH_TRDRD_MAX 5 /* DDR3 =10 */ +#define DTH_TRDRD_MASK 3 /* For DDR3 3_2 is at 0x78 DC */ +#define DTH_TRDRD_BASE 2 +#define DTH_TRDRD_MIN 2 +#define DTH_TRDRD_MAX 5 /* DDR3 =10 */ #define DTH_TREF_SHIFT 16 -#define DTH_TREF_MASK 3 +#define DTH_TREF_MASK 3 #define DTH_TREF_7_8_US 2 #define DTH_TREF_3_9_US 3 #define DTH_DisAutoRefresh (1<<18) #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 +#define DTH_TRFC_MASK 7 #define DTH_TRFC_75_256M 0 #define DTH_TRFC_105_512M 1 -#define DTH_TRFC_127_5_1G 2 -#define DTH_TRFC_195_2G 3 -#define DTH_TRFC_327_5_4G 4 +#define DTH_TRFC_127_5_1G 2 +#define DTH_TRFC_195_2G 3 +#define DTH_TRFC_327_5_4G 4 #if 0 //DDR3 -#define DTH_TRFC_90_512M 1 -#define DTH_TRFC_110_5_1G 2 -#define DTH_TRFC_160_2G 3 -#define DTH_TRFC_300_4G 4 -#define DTH_TRFC_UNDEFINED_8G 5 +#define DTH_TRFC_90_512M 1 +#define DTH_TRFC_110_5_1G 2 +#define DTH_TRFC_160_2G 3 +#define DTH_TRFC_300_4G 4 +#define DTH_TRFC_UNDEFINED_8G 5 #endif #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
#define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) +#define DCL_InitDram (1<<0) #define DCL_ExitSelfRef (1<<1) #define DCL_PllLockTime_SHIFT 2 #define DCL_PllLockTime_MASK 3 -#define DCL_PllLockTime_15US 0 -#define DCL_PllLockTime_6US 1 +#define DCL_PllLockTime_15US 0 +#define DCL_PllLockTime_6US 1 #define DCL_DramTerm_SHIFT 4 #define DCL_DramTerm_MASK 3 -#define DCL_DramTerm_No 0 -#define DCL_DramTerm_75_OH 1 -#define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 -#define DCL_DisDqsBar (1<<6) /* only for DDR2 */ +#define DCL_DramTerm_No 0 +#define DCL_DramTerm_75_OH 1 +#define DCL_DramTerm_150_OH 2 +#define DCL_DramTerm_50_OH 3 +#define DCL_DisDqsBar (1<<6) /* only for DDR2 */ #define DCL_DramDrvWeak (1<<7) /* only for DDR2 */ #define DCL_ParEn (1<<8) #define DCL_SelfRefRateEn (1<<9) /* only for DDR2 */ #define DCL_BurstLength32 (1<<10) /* only for DDR3 */ -#define DCL_Width128 (1<<11) +#define DCL_Width128 (1<<11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) +#define DCL_UnBuffDimm (1<<16) #define DCL_EnPhyDqsRcvEnTr (1<<18) -#define DCL_DimmEccEn (1<<19) +#define DCL_DimmEccEn (1<<19) #define DCL_DynPageCloseEn (1<<20) #define DCL_IdleCycInit_SHIFT 21 #define DCL_IdleCycInit_MASK 3 -#define DCL_IdleCycInit_16CLK 0 -#define DCL_IdleCycInit_32CLK 1 -#define DCL_IdleCycInit_64CLK 2 -#define DCL_IdleCycInit_96CLK 3 +#define DCL_IdleCycInit_16CLK 0 +#define DCL_IdleCycInit_32CLK 1 +#define DCL_IdleCycInit_64CLK 2 +#define DCL_IdleCycInit_96CLK 3 #define DCL_ForceAutoPchg (1<<23)
#define DRAM_CONFIG_HIGH 0x94 #define DCH_MemClkFreq_SHIFT 0 #define DCH_MemClkFreq_MASK 7 -#define DCH_MemClkFreq_200MHz 0 /* DDR2 */ -#define DCH_MemClkFreq_266MHz 1 /* DDR2 */ -#define DCH_MemClkFreq_333MHz 2 /* DDR2 */ +#define DCH_MemClkFreq_200MHz 0 /* DDR2 */ +#define DCH_MemClkFreq_266MHz 1 /* DDR2 */ +#define DCH_MemClkFreq_333MHz 2 /* DDR2 */ #define DCH_MemClkFreq_400MHz 3 /* DDR2 and DDR 3*/ #define DCH_MemClkFreq_533MHz 4 /* DDR 3 */ #define DCH_MemClkFreq_667MHz 5 /* DDR 3 */ @@ -278,28 +278,28 @@ #define DCH_ZqcsInterval_64MS 1 #define DCH_ZqcsInterval_128MS 2 #define DCH_ZqcsInterval_256MS 3 -#define DCH_RDqsEn (1<<12) /* only for DDR2 */ +#define DCH_RDqsEn (1<<12) /* only for DDR2 */ #define DCH_DisSimulRdWr (1<<13) #define DCH_DisDramInterface (1<<14) #define DCH_PowerDownEn (1<<15) #define DCH_PowerDownMode_SHIFT 16 #define DCH_PowerDownMode_MASK 1 -#define DCH_PowerDownMode_Channel_CKE 0 -#define DCH_PowerDownMode_ChipSelect_CKE 1 +#define DCH_PowerDownMode_Channel_CKE 0 +#define DCH_PowerDownMode_ChipSelect_CKE 1 #define DCH_FourRankSODimm (1<<17) #define DCH_FourRankRDimm (1<<18) #define DCH_SlowAccessMode (1<<20) #define DCH_BankSwizzleMode (1<<22) #define DCH_DcqBypassMax_SHIFT 24 #define DCH_DcqBypassMax_MASK 0xf -#define DCH_DcqBypassMax_BASE 0 -#define DCH_DcqBypassMax_MIN 0 -#define DCH_DcqBypassMax_MAX 15 +#define DCH_DcqBypassMax_BASE 0 +#define DCH_DcqBypassMax_MIN 0 +#define DCH_DcqBypassMax_MAX 15 #define DCH_FourActWindow_SHIFT 28 #define DCH_FourActWindow_MASK 0xf -#define DCH_FourActWindow_BASE 7 /* DDR3 15 */ -#define DCH_FourActWindow_MIN 8 /* DDR3 16 */ -#define DCH_FourActWindow_MAX 20 /* DDR3 30 */ +#define DCH_FourActWindow_BASE 7 /* DDR3 15 */ +#define DCH_FourActWindow_MIN 8 /* DDR3 16 */ +#define DCH_FourActWindow_MAX 20 /* DDR3 30 */
// for 0x98 index and 0x9c data for DCT0 @@ -317,56 +317,56 @@ #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 #define DODCC_CkeDrvStren_SHIFT 0 #define DODCC_CkeDrvStren_MASK 3 -#define DODCC_CkeDrvStren_1_0X 0 -#define DODCC_CkeDrvStren_1_25X 1 -#define DODCC_CkeDrvStren_1_5X 2 -#define DODCC_CkeDrvStren_2_0X 3 +#define DODCC_CkeDrvStren_1_0X 0 +#define DODCC_CkeDrvStren_1_25X 1 +#define DODCC_CkeDrvStren_1_5X 2 +#define DODCC_CkeDrvStren_2_0X 3 #define DODCC_CsOdtDrvStren_SHIFT 4 #define DODCC_CsOdtDrvStren_MASK 3 -#define DODCC_CsOdtDrvStren_1_0X 0 -#define DODCC_CsOdtDrvStren_1_25X 1 -#define DODCC_CsOdtDrvStren_1_5X 2 -#define DODCC_CsOdtDrvStren_2_0X 3 +#define DODCC_CsOdtDrvStren_1_0X 0 +#define DODCC_CsOdtDrvStren_1_25X 1 +#define DODCC_CsOdtDrvStren_1_5X 2 +#define DODCC_CsOdtDrvStren_2_0X 3 #define DODCC_AddrCmdDrvStren_SHIFT 8 #define DODCC_AddrCmdDrvStren_MASK 3 -#define DODCC_AddrCmdDrvStren_1_0X 0 -#define DODCC_AddrCmdDrvStren_1_25X 1 -#define DODCC_AddrCmdDrvStren_1_5X 2 -#define DODCC_AddrCmdDrvStren_2_0X 3 +#define DODCC_AddrCmdDrvStren_1_0X 0 +#define DODCC_AddrCmdDrvStren_1_25X 1 +#define DODCC_AddrCmdDrvStren_1_5X 2 +#define DODCC_AddrCmdDrvStren_2_0X 3 #define DODCC_ClkDrvStren_SHIFT 12 #define DODCC_ClkDrvStren_MASK 3 -#define DODCC_ClkDrvStren_0_75X 0 -#define DODCC_ClkDrvStren_1_0X 1 -#define DODCC_ClkDrvStren_1_25X 2 -#define DODCC_ClkDrvStren_1_5X 3 +#define DODCC_ClkDrvStren_0_75X 0 +#define DODCC_ClkDrvStren_1_0X 1 +#define DODCC_ClkDrvStren_1_25X 2 +#define DODCC_ClkDrvStren_1_5X 3 #define DODCC_DataDrvStren_SHIFT 16 #define DODCC_DataDrvStren_MASK 3 -#define DODCC_DataDrvStren_0_75X 0 -#define DODCC_DataDrvStren_1_0X 1 -#define DODCC_DataDrvStren_1_25X 2 -#define DODCC_DataDrvStren_1_5X 3 +#define DODCC_DataDrvStren_0_75X 0 +#define DODCC_DataDrvStren_1_0X 1 +#define DODCC_DataDrvStren_1_25X 2 +#define DODCC_DataDrvStren_1_5X 3 #define DODCC_DqsDrvStren_SHIFT 20 #define DODCC_DqsDrvStren_MASK 3 -#define DODCC_DqsDrvStren_0_75X 0 -#define DODCC_DqsDrvStren_1_0X 1 -#define DODCC_DqsDrvStren_1_25X 2 -#define DODCC_DqsDrvStren_1_5X 3 +#define DODCC_DqsDrvStren_0_75X 0 +#define DODCC_DqsDrvStren_1_0X 1 +#define DODCC_DqsDrvStren_1_25X 2 +#define DODCC_DqsDrvStren_1_5X 3 #define DODCC_ProcOdt_SHIFT 28 #define DODCC_ProcOdt_MASK 3 -#define DODCC_ProcOdt_300_OHMS 0 -#define DODCC_ProcOdt_150_OHMS 1 -#define DODCC_ProcOdt_75_OHMS 2 +#define DODCC_ProcOdt_300_OHMS 0 +#define DODCC_ProcOdt_150_OHMS 1 +#define DODCC_ProcOdt_75_OHMS 2 #if 0 //DDR3 -#define DODCC_ProcOdt_240_OHMS 0 -#define DODCC_ProcOdt_120_OHMS 1 -#define DODCC_ProcOdt_60_OHMS 2 +#define DODCC_ProcOdt_240_OHMS 0 +#define DODCC_ProcOdt_120_OHMS 1 +#define DODCC_ProcOdt_60_OHMS 2 #endif
/* for DDR2 400, 533, 667, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of all DIMMs for DDR2 800, DDR3 800, 1067, 1333, 1600, F2x[1,0]9C_x[02:01], [03], [06:05], [07] controll timing of DIMM0 - F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 + F2x[1,0]9C_x[102:101], [103], [106:105], [107] controll timing of DIMM1 So Socket F with Four Logical DIMM will only support DDR2 800 ? */ /* there are index +100 ===> for DIMM1 @@ -376,14 +376,14 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 #define DWDTC_WrDatFineDlyByte0_SHIFT 0 #define DWDTC_WrDatFineDlyByte_MASK 0x1f -#define DWDTC_WrDatFineDlyByte_BASE 0 -#define DWDTC_WrDatFineDlyByte_MIN 0 -#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK +#define DWDTC_WrDatFineDlyByte_BASE 0 +#define DWDTC_WrDatFineDlyByte_MIN 0 +#define DWDTC_WrDatFineDlyByte_MAX 31 // 1/64 MEMCLK #define DWDTC_WrDatGrossDlyByte0_SHIFT 5 #define DWDTC_WrDatGrossDlyByte_MASK 0x3 -#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0 -#define DWDTC_WrDatGrossDlyByte_0_5_ 1 -#define DWDTC_WrDatGrossDlyByte_1 2 +#define DWDTC_WrDatGrossDlyByte_NO_DELAY 0 +#define DWDTC_WrDatGrossDlyByte_0_5_ 1 +#define DWDTC_WrDatGrossDlyByte_1 2 #define DWDTC_WrDatFineDlyByte1_SHIFT 8 #define DWDTC_WrDatGrossDlyByte1_SHIFT 13 #define DWDTC_WrDatFineDlyByte2_SHIFT 16 @@ -408,29 +408,29 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DRAM_ADDR_CMD_TIMING_CTRL 0x04 #define DACTC_CkeFineDelay_SHIFT 0 #define DACTC_CkeFineDelay_MASK 0x1f -#define DACTC_CkeFineDelay_BASE 0 -#define DACTC_CkeFineDelay_MIN 0 -#define DACTC_CkeFineDelay_MAX 31 +#define DACTC_CkeFineDelay_BASE 0 +#define DACTC_CkeFineDelay_MIN 0 +#define DACTC_CkeFineDelay_MAX 31 #define DACTC_CkeSetup (1<<5) #define DACTC_CsOdtFineDelay_SHIFT 8 #define DACTC_CsOdtFineDelay_MASK 0x1f -#define DACTC_CsOdtFineDelay_BASE 0 -#define DACTC_CsOdtFineDelay_MIN 0 -#define DACTC_CsOdtFineDelay_MAX 31 +#define DACTC_CsOdtFineDelay_BASE 0 +#define DACTC_CsOdtFineDelay_MIN 0 +#define DACTC_CsOdtFineDelay_MAX 31 #define DACTC_CsOdtSetup (1<<13) #define DACTC_AddrCmdFineDelay_SHIFT 16 #define DACTC_AddrCmdFineDelay_MASK 0x1f -#define DACTC_AddrCmdFineDelay_BASE 0 -#define DACTC_AddrCmdFineDelay_MIN 0 -#define DACTC_AddrCmdFineDelay_MAX 31 +#define DACTC_AddrCmdFineDelay_BASE 0 +#define DACTC_AddrCmdFineDelay_MIN 0 +#define DACTC_AddrCmdFineDelay_MAX 31 #define DACTC_AddrCmdSetup (1<<21)
#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 #define DRDTC_RdDqsTimeByte0_SHIFT 0 #define DRDTC_RdDqsTimeByte_MASK 0x3f -#define DRDTC_RdDqsTimeByte_BASE 0 -#define DRDTC_RdDqsTimeByte_MIN 0 -#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK +#define DRDTC_RdDqsTimeByte_BASE 0 +#define DRDTC_RdDqsTimeByte_MIN 0 +#define DRDTC_RdDqsTimeByte_MAX 63 // 1/128 MEMCLK #define DRDTC_RdDqsTimeByte1_SHIFT 8 #define DRDTC_RdDqsTimeByte2_SHIFT 16 #define DRDTC_RdDqsTimeByte3_SHIFT 24 @@ -449,9 +449,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DPC_WrtLvTrMode (1<<1) #define DPC_TrNibbleSel (1<<2) #define DPC_TrDimmSel_SHIFT 4 -#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ +#define DPC_TrDimmSel_MASK 3 /* 0-->dimm0, 1-->dimm1, 2--->dimm2, 3--->dimm3 */ #define DPC_WrLvOdt_SHIFT 8 -#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ +#define DPC_WrLvOdt_MASK 0xf /* bit 0-->odt 0, ...*/ #define DPC_WrLvODtEn (1<<12) #define DPC_DqsRcvTrEn (1<<13) #define DPC_DisAutoComp (1<<30) @@ -459,9 +459,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_0 0x10 //DIMM0 Channel A #define DDRETC_DqsRcvEnFineDelayByte0_SHIFT 0 -#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f +#define DDRETC_DqsRcvEnFineDelayByte0_MASK 0x1f #define DDRETC_DqsRcvEnGrossDelayByte0_SHIFT 5 -#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3 +#define DDRETC_DqsRcvEnGrossDelayByte0_MASK 0x3 #define DDRETC_DqsRcvEnFineDelayByte1_SHIFT 8 #define DDRETC_DqsRcvEnGrossDelayByte1_SHIFT 13 #define DDRETC_DqsRcvEnFineDelayByte2_SHIFT 16 @@ -483,7 +483,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DDRETCE_WrChkFineDlyByte0_SHIFT 0 #define DDRETCE_WrChkGrossDlyByte0_SHIFT 5
-#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B +#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_0_2 0x20 //DIMM0 channel B #define DDRETC_DqsRcvEnFineDelayByte8_SHIFT 0 #define DDRETC_DqsRcvEnGrossDelayByte8_SHIFT 5 #define DDRETC_DqsRcvEnFineDelayByte9_SHIFT 8 @@ -514,14 +514,14 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_1_3 0x24 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_1_1 0x25
-#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2 +#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_0 0x16 // DIMM2 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_1 0x17 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_0 0x18 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_2 0x26 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_2_3 0x27 #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_2_1 0x28
-#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3 +#define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_0 0x19 // DIMM3 #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_1 0x1a #define DRAM_DQS_RECV_ENABLE_TIMING_CTRL_ECC_3_0 0x1b #define DRAM_DQS_RECV_ENABLE_TIME_CTRL_3_2 0x29 @@ -534,9 +534,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 //DDR3 #define DRAM_DQS_WRITE_TIME_CTRL_0_0 0x30 //DIMM0 Channel A #define DDWTC_WrDqsFineDlyByte0_SHIFT 0 -#define DDWTC_WrDqsFineDlyByte0_MASK 0x1f +#define DDWTC_WrDqsFineDlyByte0_MASK 0x1f #define DDWTC_WrDqsGrossDlyByte0_SHIFT 5 -#define DDWTC_WrDqsGrossDlyByte0_MASK 0x3 +#define DDWTC_WrDqsGrossDlyByte0_MASK 0x3 #define DDWTC_WrDqsFineDlyByte1_SHIFT 8 #define DDWTC_WrDqsGrossDlyByte1_SHIFT 13 #define DDWTC_WrDqsFineDlyByte2_SHIFT 16 @@ -592,9 +592,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define DRAM_PHASE_RECOVERY_CTRL_0 0x50 #define DPRC_PhRecFineDlyByte0_SHIFT 0 -#define DDWTC_PhRecFineDlyByte0_MASK 0x1f +#define DDWTC_PhRecFineDlyByte0_MASK 0x1f #define DDWTC_PhRecGrossDlyByte0_SHIFT 5 -#define DDWTC_PhRecGrossDlyByte0_MASK 0x3 +#define DDWTC_PhRecGrossDlyByte0_MASK 0x3 #define DDWTC_PhRecFineDlyByte1_SHIFT 8 #define DDWTC_PhRecGrossDlyByte1_SHIFT 13 #define DDWTC_PhRecFineDlyByte2_SHIFT 16 @@ -618,7 +618,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define DRAM_WRITE_LEVEL_ERROR 0x53 /* read only */ #define DWLE_WrLvErr_SHIFT 0 -#define DWLE_WrLvErr_MASK 0xff +#define DWLE_WrLvErr_MASK 0xff
#define DRAM_CTRL_MISC 0xa0 #define DCM_MemCleared (1<<0) /* RD == F2x110 [MemCleared] */ @@ -634,11 +634,11 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define DCT_DEBUG_CTRL 0xf0 /* 0xf0 for DCT0, 0x1f0 is for DCT1*/ #define DDC_DllAdjust_SHIFT 0 -#define DDC_DllAdjust_MASK 0xff +#define DDC_DllAdjust_MASK 0xff #define DDC_DllSlower (1<<8) #define DDC_DllFaster (1<<9) #define DDC_WrtDqsAdjust_SHIFT 16 -#define DDC_WrtDqsAdjust_MASK 0x7 +#define DDC_WrtDqsAdjust_MASK 0x7 #define DDC_WrtDqsAdjustEn (1<<19)
#define DRAM_CTRL_SEL_LOW 0x110 @@ -649,62 +649,62 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DCSL_DctGangEn (1<<4) #define DCSL_DctDataIntLv (1<<5) #define DCSL_DctSelIntLvAddr_SHIFT -#define DCSL_DctSelIntLvAddr_MASK 3 +#define DCSL_DctSelIntLvAddr_MASK 3 #define DCSL_DramEnable (1<<8) /* RD only */ #define DCSL_MemClrBusy (1<<9) /* RD only */ #define DCSL_MemCleared (1<<10) /* RD only */ #define DCSL_DctSelBaseAddr_47_27_SHIFT 11 -#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff +#define DCSL_DctSelBaseAddr_47_27_MASK 0x1fffff
#define DRAM_CTRL_SEL_HIGH 0x114 #define DCSH_DctSelBaseOffset_47_26_SHIFT 10 -#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff +#define DCSH_DctSelBaseOffset_47_26_MASK 0x3fffff
#define MEM_CTRL_CONF_LOW 0x118 #define MCCL_MctPriCpuRd (1<<0) #define MCCL_MctPriCpuWr (1<<1) #define MCCL_MctPriIsocRd_SHIFT 4 -#define MCCL_MctPriIsoc_MASK 0x3 +#define MCCL_MctPriIsoc_MASK 0x3 #define MCCL_MctPriIsocWr_SHIFT 6 -#define MCCL_MctPriIsocWe_MASK 0x3 +#define MCCL_MctPriIsocWe_MASK 0x3 #define MCCL_MctPriDefault_SHIFT 8 -#define MCCL_MctPriDefault_MASK 0x3 +#define MCCL_MctPriDefault_MASK 0x3 #define MCCL_MctPriWr_SHIFT 10 -#define MCCL_MctPriWr_MASK 0x3 +#define MCCL_MctPriWr_MASK 0x3 #define MCCL_MctPriIsoc_SHIFT 12 -#define MCCL_MctPriIsoc_MASK 0x3 +#define MCCL_MctPriIsoc_MASK 0x3 #define MCCL_MctPriTrace_SHIFT 14 -#define MCCL_MctPriTrace_MASK 0x3 +#define MCCL_MctPriTrace_MASK 0x3 #define MCCL_MctPriScrub_SHIFT 16 -#define MCCL_MctPriScrub_MASK 0x3 +#define MCCL_MctPriScrub_MASK 0x3 #define MCCL_McqMedPriByPassMax_SHIFT 20 -#define MCCL_McqMedPriByPassMax_MASK 0x7 +#define MCCL_McqMedPriByPassMax_MASK 0x7 #define MCCL_McqHiPriByPassMax_SHIFT 24 -#define MCCL_McqHiPriByPassMax_MASK 0x7 +#define MCCL_McqHiPriByPassMax_MASK 0x7 #define MCCL_MctVarPriCntLmt_SHIFT 28 -#define MCCL_MctVarPriCntLmt_MASK 0x7 +#define MCCL_MctVarPriCntLmt_MASK 0x7
#define MEM_CTRL_CONF_HIGH 0x11c #define MCCH_DctWrLimit_SHIFT 0 -#define MCCH_DctWrLimit_MASK 0x3 +#define MCCH_DctWrLimit_MASK 0x3 #define MCCH_MctWrLimit_SHIFT 2 -#define MCCH_MctWrLimit_MASK 0x1f +#define MCCH_MctWrLimit_MASK 0x1f #define MCCH_MctPrefReqLimit_SHIFT 7 -#define MCCH_MctPrefReqLimit_MASK 0x1f +#define MCCH_MctPrefReqLimit_MASK 0x1f #define MCCH_PrefCpuDis (1<<12) #define MCCH_PrefIoDis (1<<13) #define MCCH_PrefIoFixStrideEn (1<<14) #define MCCH_PrefFixStrideEn (1<<15) #define MCCH_PrefFixDist_SHIFT 16 -#define MCCH_PrefFixDist_MASK 0x3 +#define MCCH_PrefFixDist_MASK 0x3 #define MCCH_PrefConfSat_SHIFT 18 -#define MCCH_PrefConfSat_MASK 0x3 +#define MCCH_PrefConfSat_MASK 0x3 #define MCCH_PrefOneConf_SHIFT 20 -#define MCCH_PrefOneConf_MASK 0x3 +#define MCCH_PrefOneConf_MASK 0x3 #define MCCH_PrefTwoConf_SHIFT 22 -#define MCCH_PrefTwoConf_MASK 0x7 +#define MCCH_PrefTwoConf_MASK 0x7 #define MCCH_PrefThreeConf_SHIFT 25 -#define MCCH_prefThreeConf_MASK 0x7 +#define MCCH_prefThreeConf_MASK 0x7 #define MCCH_PrefDramTrainMode (1<<28) #define MCCH_FlushWrOnStpGnt (1<<29) #define MCCH_FlushWr (1<<30) @@ -746,60 +746,60 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
-#define MCA_NB_CONFIG 0x44 -#define MNC_CpuRdDatErrEn (1<<1) -#define MNC_SyncOnUcEccEn (1<<2) -#define MNC_SynvPktGenDis (1<<3) -#define MNC_SyncPktPropDis (1<<4) -#define MNC_IoMstAbortDis (1<<5) -#define MNC_CpuErrDis (1<<6) -#define MNC_IoErrDis (1<<7) -#define MNC_WdogTmrDis (1<<8) -#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ -#define MNC_WdogTmrCntSel_2_0_MASK 0x3 -#define MNC_WdogTmrBaseSel_SHIFT 12 -#define MNC_WdogTmrBaseSel_MASK 0x3 -#define MNC_LdtLinkSel_SHIFT 14 -#define MNC_LdtLinkSel_MASK 0x3 -#define MNC_GenCrcErrByte0 (1<<16) -#define MNC_GenCrcErrByte1 (1<<17) -#define MNC_SubLinkSel_SHIFT 18 -#define MNC_SubLinkSel_MASK 0x3 -#define MNC_SyncOnWdogEn (1<<20) -#define MNC_SyncOnAnyErrEn (1<<21) -#define MNC_DramEccEn (1<<22) -#define MNC_ChipKillEccEn (1<<23) -#define MNC_IoRdDatErrEn (1<<24) -#define MNC_DisPciCfgCpuErrRsp (1<<25) -#define MNC_CorrMcaExcEn (1<<26) -#define MNC_NbMcaToMstCpuEn (1<<27) -#define MNC_DisTgtAbtCpuErrRsp (1<<28) -#define MNC_DisMstAbtCpuErrRsp (1<<29) -#define MNC_SyncOnDramAdrParErrEn (1<<30) -#define MNC_NbMcaLogEn (1<<31) +#define MCA_NB_CONFIG 0x44 +#define MNC_CpuRdDatErrEn (1<<1) +#define MNC_SyncOnUcEccEn (1<<2) +#define MNC_SynvPktGenDis (1<<3) +#define MNC_SyncPktPropDis (1<<4) +#define MNC_IoMstAbortDis (1<<5) +#define MNC_CpuErrDis (1<<6) +#define MNC_IoErrDis (1<<7) +#define MNC_WdogTmrDis (1<<8) +#define MNC_WdogTmrCntSel_2_0_SHIFT 9 /* 3 is ar f3x180 */ +#define MNC_WdogTmrCntSel_2_0_MASK 0x3 +#define MNC_WdogTmrBaseSel_SHIFT 12 +#define MNC_WdogTmrBaseSel_MASK 0x3 +#define MNC_LdtLinkSel_SHIFT 14 +#define MNC_LdtLinkSel_MASK 0x3 +#define MNC_GenCrcErrByte0 (1<<16) +#define MNC_GenCrcErrByte1 (1<<17) +#define MNC_SubLinkSel_SHIFT 18 +#define MNC_SubLinkSel_MASK 0x3 +#define MNC_SyncOnWdogEn (1<<20) +#define MNC_SyncOnAnyErrEn (1<<21) +#define MNC_DramEccEn (1<<22) +#define MNC_ChipKillEccEn (1<<23) +#define MNC_IoRdDatErrEn (1<<24) +#define MNC_DisPciCfgCpuErrRsp (1<<25) +#define MNC_CorrMcaExcEn (1<<26) +#define MNC_NbMcaToMstCpuEn (1<<27) +#define MNC_DisTgtAbtCpuErrRsp (1<<28) +#define MNC_DisMstAbtCpuErrRsp (1<<29) +#define MNC_SyncOnDramAdrParErrEn (1<<30) +#define MNC_NbMcaLogEn (1<<31)
#define MCA_NB_STATUS_LOW 0x48 #define MNSL_ErrorCode_SHIFT 0 -#define MNSL_ErrorCode_MASK 0xffff +#define MNSL_ErrorCode_MASK 0xffff #define MNSL_ErrorCodeExt_SHIFT 16 -#define MNSL_ErrorCodeExt_MASK 0x1f +#define MNSL_ErrorCodeExt_MASK 0x1f #define MNSL_Syndrome_15_8_SHIFT 24 -#define MNSL_Syndrome_15_8_MASK 0xff +#define MNSL_Syndrome_15_8_MASK 0xff
#define MCA_NB_STATUS_HIGH 0x4c #define MNSH_ErrCPU_SHIFT 0 -#define MNSH_ErrCPU_MASK 0xf +#define MNSH_ErrCPU_MASK 0xf #define MNSH_LDTLink_SHIFT 4 -#define MNSH_LDTLink_MASK 0xf +#define MNSH_LDTLink_MASK 0xf #define MNSH_ErrScrub (1<<8) #define MNSH_SubLink (1<<9) #define MNSH_McaStatusSubCache_SHIFT 10 -#define MNSH_McaStatusSubCache_MASK 0x3 +#define MNSH_McaStatusSubCache_MASK 0x3 #define MNSH_Deffered (1<<12) #define MNSH_UnCorrECC (1<<13) #define MNSH_CorrECC (1<<14) #define MNSH_Syndrome_7_0_SHIFT 15 -#define MNSH_Syndrome_7_0_MASK 0xff +#define MNSH_Syndrome_7_0_MASK 0xff #define MNSH_PCC (1<<25) #define MNSH_ErrAddrVal (1<<26) #define MNSH_ErrMiscVal (1<<27) @@ -810,36 +810,36 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define MCA_NB_ADDR_LOW 0x50 #define MNAL_ErrAddr_31_1_SHIFT 1 -#define MNAL_ErrAddr_31_1_MASK 0x7fffffff +#define MNAL_ErrAddr_31_1_MASK 0x7fffffff
#define MCA_NB_ADDR_HIGH 0x54 #define MNAL_ErrAddr_47_32_SHIFT 0 -#define MNAL_ErrAddr_47_32_MASK 0xffff - -#define DRAM_SCRUB_RATE_CTRL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 0xa -#define SCRUB_41_0us 0xb -#define SCRUB_81_9us 0xc +#define MNAL_ErrAddr_47_32_MASK 0xffff + +#define DRAM_SCRUB_RATE_CTRL 0x58 +#define SCRUB_NONE 0 +#define SCRUB_40ns 1 +#define SCRUB_80ns 2 +#define SCRUB_160ns 3 +#define SCRUB_320ns 4 +#define SCRUB_640ns 5 +#define SCRUB_1_28us 6 +#define SCRUB_2_56us 7 +#define SCRUB_5_12us 8 +#define SCRUB_10_2us 9 +#define SCRUB_20_5us 0xa +#define SCRUB_41_0us 0xb +#define SCRUB_81_9us 0xc #define SCRUB_163_8us 0xd #define SCRUB_327_7us 0xe #define SCRUB_655_4us 0xf -#define SCRUB_1_31ms 0x10 -#define SCRUB_2_62ms 0x11 -#define SCRUB_5_24ms 0x12 +#define SCRUB_1_31ms 0x10 +#define SCRUB_2_62ms 0x11 +#define SCRUB_5_24ms 0x12 #define SCRUB_10_49ms 0x13 #define SCRUB_20_97ms 0x14 -#define SCRUB_42ms 0x15 -#define SCRUB_84ms 0x16 +#define SCRUB_42ms 0x15 +#define SCRUB_84ms 0x16 #define DSRC_DramScrub_SHFIT 0 #define DSRC_DramScrub_MASK 0x1f #define DSRC_L2Scrub_SHIFT 8 @@ -852,11 +852,11 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define DRAM_SCRUB_ADDR_LOW 0x5C #define DSAL_ScrubReDirEn (1<<0) #define DSAL_ScrubAddrLo_SHIFT 6 -#define DSAL_ScrubAddrLo_MASK 0x3ffffff +#define DSAL_ScrubAddrLo_MASK 0x3ffffff
-#define DRAM_SCRUB_ADDR_HIGH 0x60 +#define DRAM_SCRUB_ADDR_HIGH 0x60 #define DSAH_ScrubAddrHi_SHIFT 0 -#define DSAH_ScrubAddrHi_MASK 0xffff +#define DSAH_ScrubAddrHi_MASK 0xffff
#define HW_THERMAL_CTRL 0x64
@@ -899,10 +899,10 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_TwoChanDRAMcap (1 << 0) -#define NBCAP_DualNodeMPcap (1 << 1) -#define NBCAP_EightNodeMPcap (1 << 2) -#define NBCAP_ECCcap (1 << 3) +#define NBCAP_TwoChanDRAMcap (1 << 0) +#define NBCAP_DualNodeMPcap (1 << 1) +#define NBCAP_EightNodeMPcap (1 << 2) +#define NBCAP_ECCcap (1 << 3) #define NBCAP_ChipkillECCcap (1 << 4) #define NBCAP_DdrMaxRate_SHIFT 5 #define NBCAP_DdrMaxRate_MASK 7 @@ -919,20 +919,20 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #define NBCAP_DdrMaxRate_6_4G 3 #define NBCAP_DdrMaxRate_8_0G 2 #define NBCAP_DdrMaxRate_9_6G 1 -#define NBCAP_Mem_ctrl_cap (1 << 8) -#define MBCAP_SVMCap (1<<9) +#define NBCAP_Mem_ctrl_cap (1 << 8) +#define MBCAP_SVMCap (1<<9) #define NBCAP_HtcCap (1<<10) #define NBCAP_CmpCap_SHIFT 12 #define NBCAP_CmpCap_MASK 3 #define NBCAP_MpCap_SHIFT 16 #define NBCAP_MpCap_MASK 7 -#define NBCAP_MpCap_1N 7 -#define NBCAP_MpCap_2N 6 -#define NBCAP_MpCap_4N 5 -#define NBCAP_MpCap_8N 4 -#define NBCAP_MpCap_32N 0 +#define NBCAP_MpCap_1N 7 +#define NBCAP_MpCap_2N 6 +#define NBCAP_MpCap_4N 5 +#define NBCAP_MpCap_8N 4 +#define NBCAP_MpCap_32N 0 #define NBCAP_UnGangEn_SHIFT 20 -#define NBCAP_UnGangEn_MASK 0xf +#define NBCAP_UnGangEn_MASK 0xf #define NBCAP_L3Cap (1<<25) #define NBCAP_HtAcCap (1<<26)
@@ -948,16 +948,16 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 /* Function 5 for FBDIMM */ #define FBD_DRAM_TIMING_LOW
-#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) #define NonCoherent (1 << 2) #define ConnectionPending (1 << 4)
// Use the LAPIC timer count register to hold each core's init status // Format: byte 0 - state -// byte 1 - fid_max -// byte 2 - nb_cof_vid_update -// byte 3 - apic id +// byte 1 - fid_max +// byte 2 - nb_cof_vid_update +// byte 3 - apic id
#define LAPIC_MSG_REG 0x380 #define F10_APSTATE_STARTED 0x13 // start of AP execution diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c index cfb914a..7a0e5c4 100644 --- a/src/northbridge/amd/amdfam10/conf.c +++ b/src/northbridge/amd/amdfam10/conf.c @@ -506,7 +506,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); } - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? for(i=0; i<nodes; i++){ #if defined(__PRE_RAM__) dev = NODE_PCI(i, 1); @@ -781,7 +781,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, for(i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg+4, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? #if 0 // FIXME: can we use VGA reg instead? if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 244dc3c..43ead35 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -140,15 +140,15 @@ static void misc_control_init(struct device *dev)
static struct device_operations mcf3_ops = { .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources, + .set_resources = mcf3_set_resources, .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, + .init = misc_control_init, + .scan_bus = 0, + .ops_pci = 0, };
static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1203, }; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6bcab41..f0475c7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -207,7 +207,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. + // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. else { min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same } @@ -1066,7 +1066,7 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); + i, mmio_basek, basek, limitk); if (!ramtop) ramtop = limitk * 1024; } diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index 8ecdac3..66748df 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -45,8 +45,8 @@ struct mem_controller { //#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F - * 2 for socket M2/M3 - * 1 for socket s1g1 + * 2 for socket M2/M3 + * 1 for socket s1g1 */ #define DIMM_SOCKETS 4 struct mem_controller { diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 50d30a2..39c19a8 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -32,22 +32,22 @@ static void setup_default_resource_map(void) * F1:0x74 i = 6 * F1:0x7C i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 3] Reserved * [10: 8] Interleave select - * specifies the values of A[14:12] to use with - * interleave enable. + * specifies the values of A[14:12] to use with + * interleave enable. * [15:11] Reserved * [31:16] DRAM Limit Address i Bits 39-24 - * This field defines the upper address bits of a 40 bit - * address that define the end of the DRAM region. + * This field defines the upper address bits of a 40 bit + * address that define the end of the DRAM region. */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, @@ -67,25 +67,25 @@ static void setup_default_resource_map(void) * F1:0x70 i = 6 * F1:0x78 i = 7 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 7: 2] Reserved * [10: 8] Interleave Enable - * 000 = No interleave - * 001 = Interleave on A[12] (2 nodes) - * 010 = reserved - * 011 = Interleave on A[12] and A[14] (4 nodes) - * 100 = reserved - * 101 = reserved - * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 - * This field defines the upper address bits of a 40-bit - * address that define the start of the DRAM region. + * This field defines the upper address bits of a 40-bit + * address that define the start of the DRAM region. */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, @@ -106,28 +106,28 @@ static void setup_default_resource_map(void) * F1:0xB4 i = 6 * F1:0xBC i = 7 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved * [ 6: 6] Reserved * [ 7: 7] Non-Posted - * 0 = CPU writes may be posted - * 1 = CPU writes must be non-posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted * [31: 8] Memory-Mapped I/O Limit Address i (39-16) - * This field defines the upp adddress bits of a 40-bit - * address that defines the end of a memory-mapped - * I/O region n + * This field defines the upp adddress bits of a 40-bit + * address that defines the end of a memory-mapped + * I/O region n */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, @@ -148,22 +148,22 @@ static void setup_default_resource_map(void) * F1:0xB0 i = 6 * F1:0xB8 i = 7 * [ 0: 0] Read Enable - * 0 = Reads disabled - * 1 = Reads Enabled + * 0 = Reads disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes disabled - * 1 = Writes Enabled + * 0 = Writes disabled + * 1 = Writes Enabled * [ 2: 2] Cpu Disable - * 0 = Cpu can use this I/O range - * 1 = Cpu requests do not use this I/O range + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range * [ 3: 3] Lock - * 0 = base/limit registers i are read/write - * 1 = base/limit registers i are read-only + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit - * address that defines the start of memory-mapped - * I/O region i + * This field defines the upper address bits of a 40bit + * address that defines the start of memory-mapped + * I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, @@ -180,23 +180,23 @@ static void setup_default_resource_map(void) * F1:0xD4 i = 2 * F1:0xDC i = 3 * [ 2: 0] Destination Node ID - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 3: 3] Reserved * [ 5: 4] Destination Link ID - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 = reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved * [11: 6] Reserved * [24:12] PCI I/O Limit Address i - * This field defines the end of PCI I/O region n + * This field defines the end of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, @@ -210,25 +210,25 @@ static void setup_default_resource_map(void) * F1:0xD0 i = 2 * F1:0xD8 i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 3: 2] Reserved * [ 4: 4] VGA Enable - * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in - * the range 3B0-3BB or 3C0-3DF independent of the - * base & limit registers + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in + * the range 3B0-3BB or 3C0-3DF independent of the + * base & limit registers * [ 5: 5] ISA Enable - * 0 = ISA matches Disabled - * 1 = Blocks address < 64K and in the last 768 bytes of - * eack 1K block from matching agains this base/limit - * pair + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of + * eack 1K block from matching agains this base/limit + * pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, @@ -242,37 +242,37 @@ static void setup_default_resource_map(void) * F1:0xE8 i = 2 * F1:0xEC i = 3 * [ 0: 0] Read Enable - * 0 = Reads Disabled - * 1 = Reads Enabled + * 0 = Reads Disabled + * 1 = Reads Enabled * [ 1: 1] Write Enable - * 0 = Writes Disabled - * 1 = Writes Enabled + * 0 = Writes Disabled + * 1 = Writes Enabled * [ 2: 2] Device Number Compare Enable - * 0 = The ranges are based on bus number - * 1 = The ranges are ranges of devices on bus 0 + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 * [ 3: 3] Reserved * [ 6: 4] Destination Node - * 000 = Node 0 - * 001 = Node 1 - * 010 = Node 2 - * 011 = Node 3 - * 100 = Node 4 - * 101 = Node 5 - * 110 = Node 6 - * 111 = Node 7 + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 * [ 7: 7] Reserved * [ 9: 8] Destination Link - * 00 = Link 0 - * 01 = Link 1 - * 10 = Link 2 - * 11 - Reserved + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved * [15:10] Reserved * [23:16] Bus Number Base i - * This field defines the lowest bus number in - * configuration region i + * This field defines the lowest bus number in + * configuration region i * [31:24] Bus Number Limit i - * This field defines the highest bus number in - * configuration regin i + * This field defines the highest bus number in + * configuration regin i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c index ae0f55c..76ad89e 100644 --- a/src/northbridge/amd/amdfam10/util.c +++ b/src/northbridge/amd/amdfam10/util.c @@ -121,9 +121,9 @@ static int r_link(u32 reg) static void showdram(int level, u8 which, u32 base, u32 lim) { printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", - which, (((u64) base & 0xffff0000) << 8), - (((u64) lim & 0xffff0000) << 8) + 0xffffff, - r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); + which, (((u64) base & 0xffff0000) << 8), + (((u64) lim & 0xffff0000) << 8) + 0xffffff, + r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); }
/** @@ -140,10 +140,10 @@ static void showconfig(int level, u8 which, u32 reg) { /* Don't use r_node() and r_link() here. */ printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", - which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), - BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), - re(reg), we(reg), - BITS(reg, 2, 0x1)?"dev":"bus"); + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), + BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); }
/** @@ -160,9 +160,9 @@ static void showconfig(int level, u8 which, u32 reg) static void showpciio(int level, u8 which, u32 base, u32 lim) { printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", - which, BITS(base, 12, 0x3fff) << 12, - (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), - re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); + which, BITS(base, 12, 0x3fff) << 12, + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), + re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); }
/** @@ -179,11 +179,11 @@ static void showpciio(int level, u8 which, u32 base, u32 lim) static void showmmio(int level, u8 which, u32 base, u32 lim) { printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " - "CPU disable %d, Lock %d, Non posted %d\n", - which, ((u64) BITS(base, 0, 0xffffff00)) << 8, - (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), - r_link(lim), re(base), we(base), BITS(base, 4, 0x1), - BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); + "CPU disable %d, Lock %d, Non posted %d\n", + which, ((u64) BITS(base, 0, 0xffffff00)) << 8, + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), + r_link(lim), re(base), we(base), BITS(base, 4, 0x1), + BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); }
/** @@ -191,7 +191,7 @@ static void showmmio(int level, u8 which, u32 base, u32 lim) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showalldram(int level, device_t dev) { @@ -209,7 +209,7 @@ static void showalldram(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallmmio(int level, device_t dev) { @@ -227,7 +227,7 @@ static void showallmmio(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallpciio(int level, device_t dev) { @@ -245,7 +245,7 @@ static void showallpciio(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallconfig(int level, device_t dev) { @@ -262,7 +262,7 @@ static void showallconfig(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ void showallroutes(int level, device_t dev) { diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index cf449f7..2b7c57d 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -44,9 +44,9 @@ #define PS_REG3 3 /* offset for P3 */ #define PS_REG4 4 /* offset for P4 */
-#define PS_IDD_VALUE_SHFT 0 /* IddValue: current value +#define PS_IDD_VALUE_SHFT 0 /* IddValue: current value field offset for msr.hi */ -#define PS_IDD_VALUE_MASK 0xFF /* IddValue: current value +#define PS_IDD_VALUE_MASK 0xFF /* IddValue: current value field mask for msr.hi */ #define PS_PSDIS_MASK 0x7fffffff /* disable P-state register */ #define PS_EN_MASK 0x80000000 /* P-state register enable mask */ @@ -60,8 +60,8 @@ #define PS_CPU_NB_VID_SHFT 16 /* P-state bit shift from CpuVid to NbVid */ #define PS_DIS 0x7fffffff /* disable P-state reg */ #define PS_EN 0x80000000 /* enable P-state reg */ -#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] - Core Frequency Id */ +#define PS_CPU_FID_MASK 0x03f /* MSRC001_00[68:64][CpuFid] + Core Frequency Id */ #define PS_CURDIV_SHFT 8 /* P-state Current Divisor shift position */ #define PS_CPUDID_SHIFT 6 /* P-state CPU DID shift position */
@@ -116,7 +116,7 @@ #define NB_FID_EN 0x20 /* NbFidEn bit ON */ #define NB_CLKDID_ALL 0x80000000 /* NbClkDidApplyAll bit ON */ #define NB_CLKDID 0x40000000 /* NbClkDid value set by BIOS */ -#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */ +#define NB_CLKDID_SHIFT 28 /* NbClkDid bit shift */ #define PW_STP_UP50 0x08000000 /* PowerStepUp 50nS(1000b) */ #define PW_STP_DN50 0x00800000 /* PowerStepDown 50nS (1000b)*/ #define PW_STP_UP100 0x03000000 /* PowerStepUp 100nS(0011b) */ @@ -126,10 +126,10 @@ #define PW_STP_UP400 0x00000000 /* PowerStepUp 400nS(0000b) */ #define PW_STP_DN400 0x00000000 /* PowerStepDown 400nS (0000b)*/ #define CLK_RAMP_HYST_SEL_VAL 0x00000f00 /* value mask for clock ramp - hysteresis select. BIOS - should program - F3xC4[ClkRampHystSel] to - 1111b */ + hysteresis select. BIOS + should program + F3xC4[ClkRampHystSel] to + 1111b */
#define LNK_PLL_LOCK 0x00010000 /* LnkPllLock value set (01b) by BIOS */ @@ -188,7 +188,7 @@ #define CPTC2 0xdc /* Clock Power/Timing Control2 Register*/ #define PS_MAX_VAL_POS 8 /* PstateMaxValue bit shift */ #define PS_MAX_VAL_MASK 0xfffff8ff /* PstateMaxValue Mask off */ -#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */ +#define NB_SYN_PTR_ADJ_POS 12 /* NbsynPtrAdj bit shift */ #define NB_SYN_PTR_ADJ_MASK (0x7 << NB_SYN_PTR_ADJ_POS) /* NbsynPtrAdj bit mask */
#define PRCT_INFO 0x1fc /* Product Info Register */ @@ -201,10 +201,10 @@ #define NB_VID_UPDATE_ALL 0x02 /* F3x1FC[NbVidUpdatedAll] bit mask */ #define C_FID_DID_M_OFF 0xfffffe00 /* mask off Core FID & DID */
-#define CPB_MASK 0x00000020 /* core performance - boost. CPUID Fn8000 0007 edx */ -#define NC_MASK 0x000000FF /* number of cores - 1. CPUID - Fn8000 0008 ecx */ +#define CPB_MASK 0x00000020 /* core performance + boost. CPUID Fn8000 0007 edx */ +#define NC_MASK 0x000000FF /* number of cores - 1. CPUID + Fn8000 0008 ecx */ #define PW_CTL_MISC 0x0a0 /* Power Control Miscellaneous Register */ #define COF_VID_PROG_BIT 0x80000000 /* CofVidProg bit. 0= unfused part */ #define DUAL_VDD_BIT 0x40000000 /* DualVdd bit. */ @@ -221,8 +221,8 @@ #define PLLLOCK_DFT 0x00001800 /* PllLockTime default value = 011b */ #define PLLLOCK_DFT_L 0x00002800 /* PllLockTime long value = 101b */
-#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for - 3.4 MHz SVI in rev. C3 */ +#define SVI_HIGH_FREQ_ON 0x00000200 /* F3xA0[SviHighFreqSel] for + 3.4 MHz SVI in rev. C3 */
/* P-state Specification register base in PCI space */ #define PS_SPEC_REG 0x1e0 /* PS Spec register base address */ @@ -259,7 +259,7 @@ /* sFidVidInit.outFlags defines */ #define PWR_CK_OK 0 /* System board check OK */ #define PWR_CK_NO_PS 1 /* All P-state registers are over - the limit */ + the limit */
/* bit mask */ #define BIT_MASK_1 0x1 diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index c5a27a2..f6b8685 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -253,38 +253,38 @@ void ErrorStop(u32 value) ; ; For use with SimNow the unrotated error code is also written to port 84h ErrorStop PROC FAR PASCAL PUBLIC Value:DWORD - pushad - mov eax, Value - mov bx, 0DEADh - out 84h, eax + pushad + mov eax, Value + mov bx, 0DEADh + out 84h, eax
ErrorStopTop: - out 80h, eax + out 80h, eax
- mov cx, 4 ; Rotate the display by one nibble + mov cx, 4 ; Rotate the display by one nibble @@: - bt bx, 15 - rcl eax, 1 - rcl bx, 1 - loop @B + bt bx, 15 + rcl eax, 1 + rcl bx, 1 + loop @B
- push eax ; Delay a few hundred milliseconds - push ebx - mov ecx, 10h ; TSC - db 00Fh, 032h ; RDMSR - mov ebx, eax + push eax ; Delay a few hundred milliseconds + push ebx + mov ecx, 10h ; TSC + db 00Fh, 032h ; RDMSR + mov ebx, eax @@: - db 00Fh, 032h ; RDMSR - sub eax, ebx - cmp eax, 500000000 - jb @B - pop ebx - pop eax + db 00Fh, 032h ; RDMSR + sub eax, ebx + cmp eax, 500000000 + jb @B + pop ebx + pop eax
- jmp ErrorStopTop + jmp ErrorStopTop
- popad - ret + popad + ret ErrorStop ENDP */ diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index eb4d6a2..15cc723 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -98,7 +98,7 @@ #define HTUNIT_ENABLE_REG 8
/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS + * TYPEDEFS, STRUCTURES, ENUMS * *---------------------------------------------------------------------------- */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 55da604..eb4787f 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -138,10 +138,10 @@ static u8 graphHowManyNodes(u8 *graph) * Relies on rule that directly connected nodes always route requests directly. * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] BOOL results = true if nodeA connects to nodeB false if not + * @param[in] u8 graph = the graph to examine + * @param[in] u8 nodeA = the node number of the first node + * @param[in] u8 nodeB = the node number of the second node + * @param[out] BOOL results = true if nodeA connects to nodeB false if not * --------------------------------------------------------------------------------------- */ static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) @@ -164,10 +164,10 @@ static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) * it is the responsibility of the caller to apply any permutation needed. * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] u8 results = The response route node + * @param[in] u8 graph = the graph to examine + * @param[in] u8 nodeA = the node number of the first node + * @param[in] u8 nodeB = the node number of the second node + * @param[out] u8 results = The response route node * --------------------------------------------------------------------------------------- */ static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) @@ -190,10 +190,10 @@ static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) * it is the responsibility of the caller to apply any permutation needed. * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * @param[out] u8 results = The request route node + * @param[in] u8 graph = the graph to examine + * @param[in] u8 nodeA = the node number of the first node + * @param[in] u8 nodeB = the node number of the second node + * @param[out] u8 results = The request route node * --------------------------------------------------------------------------------------- */ static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) @@ -213,10 +213,10 @@ static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) * nodeB towards * * Parameters: - * @param[in] u8 graph = the graph to examine - * @param[in] u8 nodeA = the node number of the first node - * @param[in] u8 nodeB = the node number of the second node - * OU u8 results = the broadcast routes for nodeA from nodeB + * @param[in] u8 graph = the graph to examine + * @param[in] u8 nodeA = the node number of the first node + * @param[in] u8 nodeB = the node number of the second node + * OU u8 results = the broadcast routes for nodeA from nodeB * --------------------------------------------------------------------------------------- */ static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) @@ -243,9 +243,9 @@ static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) * for config access during discovery, but NOT for coherency. * * Parameters: - * @param[in] u8 targetNode = the path to actual target goes through target - * @param[in] u8 actualTarget = the ultimate target being routed to - * @param[in] sMainData* pDat = our global state, port config info + * @param[in] u8 targetNode = the path to actual target goes through target + * @param[in] u8 actualTarget = the ultimate target being routed to + * @param[in] sMainData* pDat = our global state, port config info * --------------------------------------------------------------------------------------- */ static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) @@ -281,10 +281,10 @@ static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) * Return the link on source node which connects to target node * * Parameters: - * @param[in] u8 srcNode = the source node - * @param[in] u8 targetNode = the target node to find the link to - * @param[in] sMainData* pDat = our global state - * @param[out] u8 results = the link on source which connects to target + * @param[in] u8 srcNode = the source node + * @param[in] u8 targetNode = the target node to find the link to + * @param[in] sMainData* pDat = our global state + * @param[out] u8 results = the link on source which connects to target * --------------------------------------------------------------------------------------- */ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) @@ -323,7 +323,7 @@ static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) * was discovered on (no coherency is active yet). * * Parameters: - * @param[in] sMainData* pDat = our global state + * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ static void htDiscoveryFloodFill(sMainData *pDat) @@ -589,7 +589,7 @@ static void htDiscoveryFloodFill(sMainData *pDat) * * Parameters: * @param[in] u8 i = the discovered node which we are trying to match - * with a permutation the topology + * with a permutation the topology * @param[in]/@param[out] sMainData* pDat = our global state, degree and adjacency matrix, * output a permutation if successful * @param[out] BOOL results = the graphs are (or are not) isomorphic @@ -665,7 +665,7 @@ static BOOL isoMorph(u8 i, sMainData *pDat) * node discovered to the BSP, writing the routing tables as we go. * * Parameters: - * @param[in] sMainData* pDat = our global state, the discovered fabric, + * @param[in] sMainData* pDat = our global state, the discovered fabric, * @param[out] degree matrix, permutation * --------------------------------------------------------------------------------------- */ @@ -874,7 +874,7 @@ static void coherentInit(sMainData *pDat) }
/*************************************************************************** - *** Non-coherent init code *** + *** Non-coherent init code *** *** Algorithms *** ***************************************************************************/ /*---------------------------------------------------------------------------------------- @@ -1197,7 +1197,7 @@ static void ncInit(sMainData *pDat) for (link = 0; link < pDat->nb->maxLinks; link++) { if (pDat->HtBlock->AMD_CB_IgnoreLink && pDat->HtBlock->AMD_CB_IgnoreLink(node, link)) - continue; /* Skip the link */ + continue; /* Skip the link */
if (node == 0 && link == compatLink) continue; @@ -1248,22 +1248,22 @@ static void regangLinks(sMainData *pDat) for (j = i+2; j < pDat->TotalLinks*2; j += 2) { if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) - continue; /* Only process cpu to cpu links */ + continue; /* Only process cpu to cpu links */
if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) - continue; /* Links must be from the same source */ + continue; /* Links must be from the same source */
if (pDat->PortList[i+1].NodeID != pDat->PortList[j+1].NodeID) - continue; /* Link must be to the same target */ + continue; /* Link must be to the same target */
if ((pDat->PortList[i].Link & 3) != (pDat->PortList[j].Link & 3)) - continue; /* Ensure same source base port */ + continue; /* Ensure same source base port */
if ((pDat->PortList[i+1].Link & 3) != (pDat->PortList[j+1].Link & 3)) - continue; /* Ensure same destination base port */ + continue; /* Ensure same destination base port */
if ((pDat->PortList[i].Link & 4) != (pDat->PortList[i+1].Link & 4)) - continue; /* Ensure sublink0 routes to sublink0 */ + continue; /* Ensure sublink0 routes to sublink0 */
ASSERT((pDat->PortList[j].Link & 4) == (pDat->PortList[j+1].Link & 4)); /* (therefore sublink1 routes to sublink1) */
@@ -1273,7 +1273,7 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i+1].NodeID, pDat->PortList[i+1].Link & 0x03)) { - continue; /* Skip regang */ + continue; /* Skip regang */ }
@@ -1309,7 +1309,7 @@ static void regangLinks(sMainData *pDat) * For all links: * Examine both sides of a link and determine the optimal frequency and width, * taking into account externally provided limits and enforcing any other limit - * or matching rules as applicable except sublink balancing. Update the port + * or matching rules as applicable except sublink balancing. Update the port * list date with the optimal settings. * Note no hardware state changes in this routine. * @@ -1506,36 +1506,36 @@ static void hammerSublinkFixup(sMainData *pDat) { if ((loFreq != 7) && /* {13, 7} 2400MHz / 1200MHz 2:1 */ (loFreq != 4) && /* {13, 4} 2400MHz / 600MHz 4:1 */ - (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */ + (loFreq != 2) ) /* {13, 2} 2400MHz / 400MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 11) { - if ((loFreq != 6)) /* {11, 6} 2000MHz / 1000MHz 2:1 */ + if ((loFreq != 6)) /* {11, 6} 2000MHz / 1000MHz 2:1 */ downgrade = TRUE; } else if (hiFreq == 9) { if ((loFreq != 5) && /* { 9, 5} 1600MHz / 800MHz 2:1 */ (loFreq != 2) && /* { 9, 2} 1600MHz / 400MHz 4:1 */ - (loFreq != 0) ) /* { 9, 0} 1600MHz / 200Mhz 8:1 */ + (loFreq != 0) ) /* { 9, 0} 1600MHz / 200Mhz 8:1 */ downgrade = TRUE; } else if (hiFreq == 7) { if ((loFreq != 4) && /* { 7, 4} 1200MHz / 600MHz 2:1 */ - (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */ + (loFreq != 0) ) /* { 7, 0} 1200MHz / 200MHz 6:1 */ downgrade = TRUE; } else if (hiFreq == 5) { if ((loFreq != 2) && /* { 5, 2} 800MHz / 400MHz 2:1 */ - (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */ + (loFreq != 0) ) /* { 5, 0} 800MHz / 200MHz 4:1 */ downgrade = TRUE; } else if (hiFreq == 2) { - if ((loFreq != 0)) /* { 2, 0} 400MHz / 200MHz 2:1 */ + if ((loFreq != 0)) /* { 2, 0} 400MHz / 200MHz 2:1 */ downgrade = TRUE; } else diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index e169456..9c8c7bf 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -139,10 +139,10 @@ typedef struct { * (Note: not called for IO device to IO Device links.) * * Parameters: - * @param[in] u8 node = The node on which this link is located - * @param[in] u8 link = The link about to be initialized + * @param[in] u8 node = The node on which this link is located + * @param[in] u8 link = The link about to be initialized * @param[out] BOOL result = true to ignore this link and skip it - * false to initialize the link normally + * false to initialize the link normally * * --------------------------------------------------------------------------------------- */ @@ -217,8 +217,8 @@ typedef struct { * @param[in] u8 hostLink = The link on the host for this chain * @param[in] u8 Depth = The depth in the I/O chain from the Host * @param[in] u8 Segment = The Device's PCI Bus Segment number - * @param[in] u8 Bus = The Device's PCI Bus number - * @param[in] u8 Dev = The Device's PCI device Number + * @param[in] u8 Bus = The Device's PCI Bus number + * @param[in] u8 Dev = The Device's PCI device Number * @param[in] u32 DevVenID = The Device's PCI Vendor + Device ID (offset 0x00) * @param[in] u8 Link = The Device's link number (0 or 1) * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In @@ -279,7 +279,7 @@ typedef struct { * * void * AMD_CB_IOPCBLimits(u8 HostNode, u8 HostLink, u8 Depth, u8 *DownstreamLinkWidthLimit, - * u8 *UpstreamLinkWidthLimit, u16 *PCBFreqCap) + * u8 *UpstreamLinkWidthLimit, u16 *PCBFreqCap) * * Description: * For each non-coherent connection this routine is called once. @@ -349,7 +349,7 @@ typedef struct { * * Parameters: * @param[out] BOOL result = true skip traffic distribution - * false do normal traffic distribution + * false do normal traffic distribution * * --------------------------------------------------------------------------------------- */ @@ -370,7 +370,7 @@ typedef struct { * Parameters: * @param[in] u8 node = buffer allocation may apply to this node * @param[out] BOOL result = true skip buffer allocation on this node - * false tune buffers normally + * false tune buffers normally * * --------------------------------------------------------------------------------------- */ @@ -380,7 +380,7 @@ typedef struct { * * void * AMD_CB_OverrideDevicePort(u8 HostNode, u8 HostLink, u8 Depth, u8 *LinkWidthIn, - * u8 *LinkWidthOut, u16 *LinkFrequency) + * u8 *LinkWidthOut, u16 *LinkFrequency) * * Description: * Called once for each active link on each IO device. @@ -393,8 +393,8 @@ typedef struct { * @param[in] u8 hostLink = The link about to be initialized * @param[in] u8 Depth = The depth in the I/O chain from the Host * @param[in] u8 Link = the link on the device (0 or 1) - * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In - * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out + * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In + * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out * @param[in,out] u16* LinkFrequency = modify to change the link's frequency capability * * --------------------------------------------------------------------------------------- @@ -544,7 +544,7 @@ typedef struct } sHtEventNcohAutoDepth;
/* For event HT_EVENT_OPT_REQUIRED_CAP_RETRY, - * HT_EVENT_OPT_REQUIRED_CAP_GEN3 + * HT_EVENT_OPT_REQUIRED_CAP_GEN3 */ typedef struct { diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h index bcd3a41..fee7fee 100644 --- a/src/northbridge/amd/amdht/h3gtopo.h +++ b/src/northbridge/amd/amdht/h3gtopo.h @@ -84,7 +84,7 @@ static u8 const amdHtTopologyTriangle[] = { };
/* - * 2 3 + * 2 3 * |\ | * | | * 0---1 @@ -128,9 +128,9 @@ static u8 const amdHtTopologyFourKite[] = {
/* - * 2 3 - * | | - * | | + * 2 3 + * | | + * | | * 0---1 */ static u8 const amdHtTopologyFourLine[] = { @@ -144,8 +144,8 @@ static u8 const amdHtTopologyFourLine[] = {
/* * 2---3 - * | | - * | | + * | | + * | | * 0---1 */ static u8 const amdHtTopologyFourSquare[] = { @@ -161,7 +161,7 @@ static u8 const amdHtTopologyFourSquare[] = { * 2---3 * |\ * | \ - * 0 1 + * 0 1 */ static u8 const amdHtTopologyFourStar[] = { 0x04, @@ -187,8 +187,8 @@ static u8 const amdHtTopologyFiveFully[] = { * 4 * |\ * | \ - * 2 3 - * | | + * 2 3 + * | | * 0---1 */ static u8 const amdHtTopologyFiveTwistedLadder[] = { @@ -213,11 +213,11 @@ static u8 const amdHtTopologySixFully[] = {
/* * - * 4 5 + * 4 5 * |\ /| * |/ | - * 2 3 - * | | + * 2 3 + * | | * 0---1 */ static u8 const amdHtTopologySixTwistedLadder[] = { @@ -245,11 +245,11 @@ static u8 const amdHtTopologySevenFully[] = {
/* 6 * | - * 4 5 + * 4 5 * |\ /| * |/ | - * 2 3 - * | | + * 2 3 + * | | * 0---1 */ static u8 const amdHtTopologySevenTwistedLadder[] = { @@ -287,11 +287,11 @@ static u8 const amdHtTopologyEightFully [] = {
/* 6---7 - * | | + * | | * 4---5 - * | | + * | | * 2---3 - * | | + * | | * 0---1 */ static u8 const amdHtTopologyEightStraightLadder[] = { @@ -308,12 +308,12 @@ static u8 const amdHtTopologyEightStraightLadder[] = {
/* 6---7 - * | | - * 4 5 + * | | + * 4 5 * |\ /| * |/ | - * 2 3 - * | | + * 2 3 + * | | * 0---1 */ static u8 const amdHtTopologyEightTwistedLadder[] = { diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index cba21b3..98d79af 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -99,8 +99,8 @@ * PCI config address for a link. * * Parameters: - * @param[in] u8 node = the node this link is on - * @param[in] u8 link = the link + * @param[in] u8 node = the node this link is on + * @param[in] u8 link = the link * @param[out] SBDFO result = the pci config address * * --------------------------------------------------------------------------------------- @@ -180,10 +180,10 @@ static void setHtControlRegisterBits(SBDFO reg, u8 hiBit, u8 loBit, u32 *pValue) * response paths. * * Parameters: - * @param[in] u8 node = the node that will have it's routing tables modified. + * @param[in] u8 node = the node that will have it's routing tables modified. * @param[in] u8 target = For routing to node target - * @param[in] u8 Link = Link from node to target - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] u8 Link = Link from node to target + * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -213,7 +213,7 @@ static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) * Modifies the NodeID register on the target node * * Parameters: - * @param[in] u8 node = the node that will have its NodeID altered. + * @param[in] u8 node = the node that will have its NodeID altered. * @param[in] u8 nodeID = the new value for NodeID * @param[in] cNorthBridge *nb = this northbridge * @@ -308,15 +308,15 @@ static void enableRoutingTables(u8 node, cNorthBridge *nb) * Verify that the link is coherent, connected, and ready * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the link on that Node to examine - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] u8 node = the node that will be examined + * @param[in] u8 link = the link on that Node to examine + * @param[in] cNorthBridge *nb = this northbridge * @param[out] u8 result = true - The link has the following status - * linkCon=1, Link is connected - * InitComplete=1, Link initialization is complete - * NC=0, Link is coherent - * UniP-cLDT=0, Link is not Uniprocessor cLDT - * LinkConPend=0 Link connection is not pending + * linkCon=1, Link is connected + * InitComplete=1, Link initialization is complete + * NC=0, Link is coherent + * UniP-cLDT=0, Link is not Uniprocessor cLDT + * LinkConPend=0 Link connection is not pending * false- The link has some other status * * --------------------------------------------------------------------------------------- @@ -353,20 +353,20 @@ static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) * Also, call event notify if a Hardware Fault caused a synch flood on a previous boot. * * The table below summarizes correct responses of this routine. - * Family before after unconnected Notify? return - * 0F 0 0 0 No 0 - * 0F 1 0 0 Yes 0 - * 0F 1 1 X No 1 - * 10 0 0 0 No 0 - * 10 1 0 0 Yes 0 - * 10 1 0 3 No 1 + * Family before after unconnected Notify? return + * 0F 0 0 0 No 0 + * 0F 1 0 0 Yes 0 + * 0F 1 1 X No 1 + * 10 0 0 0 No 0 + * 10 1 0 0 Yes 0 + * 10 1 0 3 No 1 * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the link on that node to examine - * @param[in] u8 sMainData = access to call back routine - * @param[in] cNorthBridge *nb = this northbridge - * @param[out] u8 result = true - the link is not connected or has hard error + * @param[in] u8 node = the node that will be examined + * @param[in] u8 link = the link on that node to examine + * @param[in] u8 sMainData = access to call back routine + * @param[in] cNorthBridge *nb = this northbridge + * @param[out] u8 result = true - the link is not connected or has hard error * false- if the link is connected * * --------------------------------------------------------------------------------------- @@ -446,7 +446,7 @@ static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBrid * using it will have no ill-effects during HyperTransport initialization. * * Parameters: - * @param[in] u8 node = the node that will be examined + * @param[in] u8 node = the node that will be examined * @param[in] cNorthBridge *nb = this northbridge * @param[out] u8 result = the Token read from the node * @@ -511,7 +511,7 @@ static void writeToken(u8 node, u8 value, cNorthBridge *nb) * Return the number of cores (1 based count) on node. * * Parameters: - * @param[in] u8 node = the node that will be examined + * @param[in] u8 node = the node that will be examined * @param[in] cNorthBridge *nb = this northbridge * @param[out] u8 result = the number of cores * @@ -543,7 +543,7 @@ static u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) * Return the number of cores (1 based count) on node. * * Parameters: - * @param[in] u8 node = the node that will be examined + * @param[in] u8 node = the node that will be examined * @param[in] cNorthBridge *nb = this northbridge * @param[out] u8 result = the number of cores * @@ -592,10 +592,10 @@ static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) * Write the total number of cores and nodes to the node * * Parameters: - * @param[in] u8 node = the node that will be examined + * @param[in] u8 node = the node that will be examined * @param[in] u8 totalNodes = the total number of nodes * @param[in] u8 totalCores = the total number of cores - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -657,7 +657,7 @@ static void limitNodes(u8 node, cNorthBridge *nb) * link, and broadcast links provided. * * Parameters: - * @param[in] u8 node = the node that will be examined + * @param[in] u8 node = the node that will be examined * @param[in] u8 target = the target node for these routes * @param[in] u8 reqLink = the link for requests to target * @param[in] u8 rspLink = the link for responses to target @@ -743,7 +743,7 @@ static u32 makeKey(u8 node) * same as the BSP's. * * Parameters: - * @param[in] u8 node = the node + * @param[in] u8 node = the node * @param[in] cNorthBridge *nb = this northbridge * @param[out] BOOL result = true: the new is compatible, false: it is not * @@ -764,11 +764,11 @@ static BOOL isCompatible(u8 node, cNorthBridge *nb) * Return whether the current configuration exceeds the capability. * * Parameters: - * @param[in] u8 node = the node + * @param[in] u8 node = the node * @param[in,out] sMainData *pDat = sysMpCap (updated) and NodesDiscovered * @param[in] cNorthBridge *nb = this northbridge * @param[out] BOOL result = true: system is capable of current config. - * false: system is not capable of current config. + * false: system is not capable of current config. * * --------------------------------------------------------------------------------------- */ @@ -818,11 +818,11 @@ static BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * Return whether the current configuration exceeds the capability. * * Parameters: - * @param[in] u8 node = the node + * @param[in] u8 node = the node * @param[in,out] sMainData *pDat = sysMpCap (updated) and NodesDiscovered - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] cNorthBridge *nb = this northbridge * @param[out] BOOL result = true: system is capable of current config. - * false: system is not capable of current config. + * false: system is not capable of current config. * * --------------------------------------------------------------------------------------- */ @@ -870,8 +870,8 @@ static BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * Disable a cHT link on node by setting F0x[E4, C4, A4, 84][TransOff, EndOfChain]=1 * * Parameters: - * @param[in] u8 node = the node this link is on - * @param[in] u8 link = the link to stop + * @param[in] u8 node = the node this link is on + * @param[in] u8 link = the link to stop * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- @@ -918,7 +918,7 @@ static void commonVoid(void) * Return False. * * Parameters: - * @param[out] BOOL result = false + * @param[out] BOOL result = false * --------------------------------------------------------------------------------------- */ static BOOL commonReturnFalse(void) @@ -966,13 +966,13 @@ static u8 readSbLink(cNorthBridge *nb) * Verify that the link is non-coherent, connected, and ready * * Parameters: - * @param[in] u8 node = the node that will be examined - * @param[in] u8 link = the Link on that node to examine + * @param[in] u8 node = the node that will be examined + * @param[in] u8 link = the Link on that node to examine * @param[in] cNorthBridge *nb = this northbridge * @param[out] u8 results = true - The link has the following status * LinkCon=1, Link is connected * InitComplete=1,Link initilization is complete - * NC=1, Link is coherent + * NC=1, Link is coherent * UniP-cLDT=0, Link is not Uniprocessor cLDT * LinkConPend=0 Link connection is not pending * false- The link has some other status @@ -1005,11 +1005,11 @@ static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) * * Parameters: * @param[in] u8 cfgRouteIndex = the map entry to set - * @param[in] u8 secBus = The secondary bus number to use - * @param[in] u8 subBus = The subordinate bus number to use + * @param[in] u8 secBus = The secondary bus number to use + * @param[in] u8 subBus = The subordinate bus number to use * @param[in] u8 targetNode = The node that shall be the recipient of the traffic * @param[in] u8 targetLink = The link that shall be the recipient of the traffic - * @param[in] sMainData* pDat = our global state + * @param[in] sMainData* pDat = our global state * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- @@ -1055,8 +1055,8 @@ static void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNod * @param[in] u8 subBus = The subordinate bus number to use * @param[in] u8 targetNode = The node that shall be the recipient of the traffic * @param[in] u8 targetLink = The link that shall be the recipient of the traffic - * @param[in] sMainData* pDat = our global state - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] sMainData* pDat = our global state + * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -1158,7 +1158,7 @@ static u8 convertWidthToBits(u8 value, cNorthBridge *nb) * northbridge frequency. * * Parameters: - * @param[in] u8 node = Result could (later) be for a specific node + * @param[in] u8 node = Result could (later) be for a specific node * @param[in] cNorthBridge *nb = this northbridge * @param[out] u16 results = Frequency mask * @@ -1236,7 +1236,7 @@ static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) * * Parameters: * @param[in,out] sMainData* pDat = our global state, port list - * @param[in] cNorthBridge *nb = this northbridge + * @param[in] cNorthBridge *nb = this northbridge * * --------------------------------------------------------------------------------------- */ @@ -1723,7 +1723,7 @@ static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * /* Convert the request routes to a link number. Note "0xE" is ht1 nb specific. * Find the response link numbers. */ - ASSERT((route01 & 0xE) && (route10 & 0xE)); /* no route! error! */ + ASSERT((route01 & 0xE) && (route10 & 0xE)); /* no route! error! */ req0 = (u8)AmdBitScanReverse((route01 & 0xE)) - 1; req1 = (u8)AmdBitScanReverse((route10 & 0xE)) - 1; /* Now, find the other link for the responses */ @@ -1795,7 +1795,7 @@ static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge * * which require adjustments and apply any standard workarounds to this node. * * Parameters: - * @param[in] u8 node = the node to + * @param[in] u8 node = the node to * @param[in] sMainData *pDat = coherent links from node 0 to 1 * @param[in] cNorthBridge* nb = this northbridge * @@ -1992,7 +1992,7 @@ static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * which require adjustments and apply any standard workarounds to this node. * * Parameters: - * @param[in] u8 node = the node to tune + * @param[in] u8 node = the node to tune * @param[in] sMainData *pDat = global state * @param[in] cNorthBridge* nb = this northbridge * diff --git a/src/northbridge/amd/amdht/h3ncmn.h b/src/northbridge/amd/amdht/h3ncmn.h index 0e5dba1..ba28b3f 100644 --- a/src/northbridge/amd/amdht/h3ncmn.h +++ b/src/northbridge/amd/amdht/h3ncmn.h @@ -69,7 +69,7 @@ #endif
/*---------------------------------------------------------------------------- - * TYPEDEFS, STRUCTURES, ENUMS + * TYPEDEFS, STRUCTURES, ENUMS * *---------------------------------------------------------------------------- */ diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 2f3660b..29a3c20 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -56,8 +56,8 @@ config HW_MEM_HOLE_SIZE_AUTO_INC default n
config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" + string + default "northbridge/amd/amdk8/bootblock.c"
config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 2eb39c0..99de1e8 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -142,14 +142,14 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */
/* because We has assume that we know the topology of the HT connection, So we can have set if we know the node_num */ - static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, - 1, 0, 2, 1, 3, 2, 4, 3, - 1, 2, 0, 1, 1, 2, 2, 3, - 2, 1, 1, 0, 2, 1, 3, 2, - 2, 3, 1, 2, 0, 1, 1, 2, - 3, 2, 2, 1, 1, 0, 2, 1, - 3, 4, 2, 3, 1, 2, 0, 1, - 4, 4, 3, 2, 2, 1, 1, 0 }; + static u8 hops_8[] = { 0, 1, 1, 2, 2, 3, 3, 4, + 1, 0, 2, 1, 3, 2, 4, 3, + 1, 2, 0, 1, 1, 2, 2, 3, + 2, 1, 1, 0, 2, 1, 3, 2, + 2, 3, 1, 2, 0, 1, 1, 2, + 3, 2, 2, 1, 1, 0, 2, 1, + 3, 4, 2, 3, 1, 2, 0, 1, + 4, 4, 3, 2, 2, 1, 1, 0 };
// u8 outer_node[8];
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index e001706..1fa604d 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -3,9 +3,9 @@ #define AMDK8_H
#if CONFIG_K8_REV_F_SUPPORT - #include "f.h" + #include "f.h" #else - #include "pre_f.h" + #include "pre_f.h" #endif
#ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 22d74c2..24ef3ea 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -5,7 +5,7 @@ * * (c) 2004 Tyan Computer * 2004.12 yhlu added support to create routing table dynamically. - * it also support 8 ways too. (8 ways ladder or 8 ways crossbar) + * it also support 8 ways too. (8 ways ladder or 8 ways crossbar) * * This code is licensed under GPL. */ @@ -13,53 +13,53 @@ /* * This algorithm assumes a grid configuration as follows: * - * nodes : 1 2 4 6 8 + * nodes : 1 2 4 6 8 * org. : 1x1 2x1 2x2 2x3 2x4 Ladder: CPU7-------------CPU6 - | | - | | - | | - | | - | | - | | + | | + | | + | | + | | + | | + | | CPU5-------------CPU4 - | | - | | - | | - | | - | | - | | + | | + | | + | | + | | + | | + | | CPU3-------------CPU2 - | | - | | - | | - | | - | | - | | + | | + | | + | | + | | + | | + | | CPU1-------------CPU0 CROSS_BAR_47_56: CPU7-------------CPU6 | ____ ___/ | - | \ / | - | / | - | /\ | - | / \ | + | \ / | + | / | + | /\ | + | / \ | | ____/ ___ | - CPU5 CPU4 - | | - | | - | | - | | - | | - | | + CPU5 CPU4 + | | + | | + | | + | | + | | + | | CPU3-------------CPU2 - | | - | | - | | - | | - | | - | | + | | + | | + | | + | | + | | + | | CPU1-------------CPU0 */
@@ -127,20 +127,20 @@ static void disable_probes(void) /* Hypetransport Transaction Control Register * F0:0x68 * [ 0: 0] Disable read byte probe - * 0 = Probes issues - * 1 = Probes not issued + * 0 = Probes issues + * 1 = Probes not issued * [ 1: 1] Disable Read Doubleword probe - * 0 = Probes issued - * 1 = Probes not issued + * 0 = Probes issued + * 1 = Probes not issued * [ 2: 2] Disable write byte probes - * 0 = Probes issued - * 1 = Probes not issued + * 0 = Probes issued + * 1 = Probes not issued * [ 3: 3] Disable Write Doubleword Probes - * 0 = Probes issued - * 1 = Probes not issued. + * 0 = Probes issued + * 1 = Probes not issued. * [10:10] Disable Fill Probe - * 0 = Probes issued for cache fills - * 1 = Probes not issued for cache fills. + * 0 = Probes issued for cache fills + * 1 = Probes not issued for cache fills. */
u32 val; @@ -179,22 +179,22 @@ static void enable_routing(u8 node) /* HT Initialization Control Register * F0:0x6C * [ 0: 0] Routing Table Disable - * 0 = Packets are routed according to routing tables - * 1 = Packets are routed according to the default link field + * 0 = Packets are routed according to routing tables + * 1 = Packets are routed according to the default link field * [ 1: 1] Request Disable (BSP should clear this) - * 0 = Request packets may be generated - * 1 = Request packets may not be generated. + * 0 = Request packets may be generated + * 1 = Request packets may not be generated. * [ 3: 2] Default Link (Read-only) - * 00 = LDT0 - * 01 = LDT1 - * 10 = LDT2 - * 11 = CPU on same node + * 00 = LDT0 + * 01 = LDT1 + * 10 = LDT2 + * 11 = CPU on same node * [ 4: 4] Cold Reset - * - Scratch bit cleared by a cold reset + * - Scratch bit cleared by a cold reset * [ 5: 5] BIOS Reset Detect - * - Scratch bit cleared by a cold reset + * - Scratch bit cleared by a cold reset * [ 6: 6] INIT Detect - * - Scratch bit cleared by a warm or cold reset not by an INIT + * - Scratch bit cleared by a warm or cold reset not by an INIT * */
@@ -219,10 +219,10 @@ static u8 link_to_register(int ldt) { /* * [ 0: 3] Request Route - * [0] Route to this node - * [1] Route to Link 0 - * [2] Route to Link 1 - * [3] Route to Link 2 + * [0] Route to this node + * [1] Route to Link 0 + * [2] Route to Link 1 + * [3] Route to Link 2 */
if (ldt&0x08) return 0x40; @@ -253,7 +253,7 @@ static void rename_temp_node(u8 node)
val=pci_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ - val |= node; /* new node */ + val |= node; /* new node */ pci_write_config32(NODE_HT(7), 0x60, val);
print_spew(" done.\n"); @@ -433,7 +433,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) if(((source &1)!=(dest &1)) #if CROSS_BAR_47_56 && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here - //(6,5) (7,4) should be here + //(6,5) (7,4) should be here #endif ){ val |= (1<<16); @@ -750,8 +750,8 @@ static unsigned setup_smp2(void) #endif
setup_remote_node(1); /* Setup the regs on the remote node */ - rename_temp_node(1); /* Rename Node 7 to Node 1 */ - enable_routing(1); /* Enable routing on Node 1 */ + rename_temp_node(1); /* Rename Node 7 to Node 1 */ + enable_routing(1); /* Enable routing on Node 1 */ #if 0 /*don't need and it is done by clear_dead_links */ clear_temp_row(0); @@ -822,8 +822,8 @@ static unsigned setup_smp4(void) setup_remote_row_direct(2, 0, byte); /* node 2 to node 0 direct link done */ setup_remote_node(2); /* Setup the regs on the remote node */
- rename_temp_node(2); /* Rename Node 7 to Node 2 */ - enable_routing(2); /* Enable routing on Node 2 */ + rename_temp_node(2); /* Rename Node 7 to Node 2 */ + enable_routing(2); /* Enable routing on Node 2 */
setup_temp_row(0,1); setup_temp_row(1,3); @@ -905,7 +905,7 @@ static unsigned setup_smp4(void)
/* ready to enable RT for Node 3 */ rename_temp_node(3); - enable_routing(3); /* enable routing on node 3 (temp.) */ + enable_routing(3); /* enable routing on node 3 (temp.) */
// beside 2, 0 is set, We need to make sure 2, 4 link is set already in case has three link in 2 #if !CROSS_BAR_47_56 @@ -1096,7 +1096,7 @@ static unsigned setup_smp6(void)
/* ready to enable RT for 5 */ rename_temp_node(5); - enable_routing(5); /* enable routing on node 5 (temp.) */ + enable_routing(5); /* enable routing on node 5 (temp.) */
static const u8 conn6_4[] = { #if !CROSS_BAR_47_56 @@ -1223,7 +1223,7 @@ static unsigned setup_smp8(void) setup_row_local(7,6); setup_remote_row_direct(6, 4, byte); setup_remote_node(6); /* Setup the regs on the remote node */ - /* Set indirect connection to 0, to 3 */ + /* Set indirect connection to 0, to 3 */ #warning "FIXME we need to find out the correct gateway for 8p" static const u8 conn8_2[] = { #if !CROSS_BAR_47_56 @@ -1261,19 +1261,19 @@ static unsigned setup_smp8(void) if( (val>>16) == 1) { // it is real node 7 so swap it /* We need to recompute link to 6 */ val = get_row(5,5); - byte = ((val>>16) & 0xfe) - link_connection(5,3); + byte = ((val>>16) & 0xfe) - link_connection(5,3); #if TRY_HIGH_FIRST == 1 byte = get_linkn_first(byte); #else byte = get_linkn_last(byte); #endif - print_linkn("\t-->(5,6) link=", byte); + print_linkn("\t-->(5,6) link=", byte); setup_row_direct(5, 6, byte); #if 0 - setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ + setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */ for(byte=0; byte<4; byte+=2) { setup_temp_row(byte+1,byte+3); - } + } #endif setup_temp_row(5,6);
@@ -1426,7 +1426,7 @@ static unsigned setup_smp8(void)
#if CROSS_BAR_47_56 /* for 47, 56, 57, 75, 46, 64 we need to substract another link to - 6, 7, 6, 6, 7, 7 */ + 6, 7, 6, 6, 7, 7 */ static const u8 conn8_4[] = { //direct 4, 7, 6, @@ -1477,7 +1477,7 @@ static unsigned setup_smp8(void)
/* ready to enable RT for Node 7 */ - enable_routing(7); /* enable routing on node 7 (temp.) */ + enable_routing(7); /* enable routing on node 7 (temp.) */
return nodes; } @@ -1526,7 +1526,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
switch(mask) { #if CONFIG_MAX_PHYSICAL_CPUS > 2 - case 0x02: /* MPCap */ + case 0x02: /* MPCap */ if(nodes > 2) { print_err("Going back to DP\n"); return 2; @@ -1807,15 +1807,15 @@ static int optimize_link_coherent_ht(void)
#if CONFIG_MAX_PHYSICAL_CPUS > 6 if(nodes>6) { - static const uint8_t opt_conn8[] ={ - 4, 6, + static const uint8_t opt_conn8[] ={ + 4, 6, #if CROSS_BAR_47_56 - 4, 7, - 5, 6, + 4, 7, + 5, 6, #endif - 5, 7, - 6, 7, - }; + 5, 7, + 6, 7, + }; needs_reset |= optimize_connection_group(opt_conn8, ARRAY_SIZE(opt_conn8)); } #endif diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 2ecc0d0..9f8348d 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -99,7 +99,7 @@ static void enumerate_ht_chain(void) }
if (ctrl & ((1 << 4) | (1 << 8))) { - /* + /* * Either the link has failed, or we have * a CRC error. * Sometimes this can happen due to link @@ -131,8 +131,8 @@ out: uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); - flags &= ~0x1f; - flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; + flags &= ~0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index 6aeff1b..fb5f8f6 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -55,7 +55,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, }
printk(BIOS_DEBUG, "before resume errata #%d\n", - (is_post_rev_g) ? 270 : 125); + (is_post_rev_g) ? 270 : 125); /* 1. Restore memory controller registers as normal. 2. Set the DisAutoRefresh bit (Dev:2x8C[18]). (270 only) @@ -77,10 +77,10 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, if (is_post_rev_g) { dcl = pci_read_config32(ctrl[i].f2, - DRAM_TIMING_HIGH); + DRAM_TIMING_HIGH); dcl |= (1 << 18); pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH, - dcl); + dcl); }
dcl = DI_EnDramInit; @@ -97,10 +97,10 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, if (is_post_rev_g) { dcl = pci_read_config32(ctrl[i].f2, - DRAM_TIMING_HIGH); + DRAM_TIMING_HIGH); dcl &= ~(1 << 18); pci_write_config32(ctrl[i].f2, DRAM_TIMING_HIGH, - dcl); + dcl); }
dcl = pci_read_config32(ctrl[i].f2, DRAM_BANK_ADDR_MAP); @@ -113,18 +113,18 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk(BIOS_DEBUG, "pcidev is %x\n", pcidev); bitmask = 2; __asm__ __volatile__("pushl %0\n\t" - "movw $0xcf8, %%dx\n\t" - "out %%eax, (%%dx)\n\t" - "movw $0xcfc, %%dx\n\t" - "inl %%dx, %%eax\n\t" - "orb %1, %%al\n\t" - "not %1\n\t" - ".align 64\n\t" - "outl %%eax, (%%dx) \n\t" - "andb %1, %%al\n\t" - "outl %%eax, (%%dx)\n\t" - "popl %0\n\t"::"a"(pcidev), - "q"(bitmask):"edx"); + "movw $0xcf8, %%dx\n\t" + "out %%eax, (%%dx)\n\t" + "movw $0xcfc, %%dx\n\t" + "inl %%dx, %%eax\n\t" + "orb %1, %%al\n\t" + "not %1\n\t" + ".align 64\n\t" + "outl %%eax, (%%dx) \n\t" + "andb %1, %%al\n\t" + "outl %%eax, (%%dx)\n\t" + "popl %0\n\t"::"a"(pcidev), + "q"(bitmask):"edx"); }
printk(BIOS_DEBUG, "after exit errata\n"); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index bfeee0e..325ad07 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -4,37 +4,37 @@ /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_CHG_ISOC_TO_ORD (1 << 12) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_CHG_ISOC_TO_ORD (1 << 12) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 #define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 #define HTTC_MED_PRI_BYP_CNT_SHIFT 24 #define HTTC_MED_PRI_BYP_CNT_MASK 3 #define HTTC_HI_PRI_BYP_CNT_SHIFT 26 @@ -42,10 +42,10 @@
/* Function 1 */ -#define PCI_IO_BASE0 0xc0 -#define PCI_IO_BASE1 0xc8 -#define PCI_IO_BASE2 0xd0 -#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 #define PCI_IO_BASE_VGA_EN (1 << 4) #define PCI_IO_BASE_NO_ISA (1 << 5)
@@ -60,16 +60,16 @@ #define DC_RdPrtInit_MASK 0xf #define DC_RdPadRcvFifoDly_SHIFT 4 #define DC_RdPadRcvFifoDly_MASK 7 -#define DC_RdPadRcvFiloDly_1_5_CLK 2 -#define DC_RdPadRcvFiloDly_2_CLK 3 -#define DC_RdPadRcvFiloDly_2_5_CLK 4 -#define DC_RdPadRcvFiloDly_3_CLK 5 -#define DC_RdPadRcvFiloDly_3_5_CLK 6 +#define DC_RdPadRcvFiloDly_1_5_CLK 2 +#define DC_RdPadRcvFiloDly_2_CLK 3 +#define DC_RdPadRcvFiloDly_2_5_CLK 4 +#define DC_RdPadRcvFiloDly_3_CLK 5 +#define DC_RdPadRcvFiloDly_3_5_CLK 6 #define DC_AltVidC3MemClkTriEn (1<<16) #define DC_DllTempAdjTime_SHIFT 17 #define DC_DllTempAdjTime_MASK 1 -#define DC_DllTempAdjTime_5_MS 0 -#define DC_DllTempAdjTime_1_MS 1 +#define DC_DllTempAdjTime_5_MS 0 +#define DC_DllTempAdjTime_1_MS 1 #define DC_DqsRcvEnTrain (1<<18)
#define DRAM_INIT 0x7c @@ -79,157 +79,157 @@ #define DI_MrsBank_MASK 7 #define DI_SendRchgAll (1<<24) #define DI_SendAutoRefresh (1<<25) -#define DI_SendMrsCmd (1<<26) +#define DI_SendMrsCmd (1<<26) #define DI_DeassertMemRstX (1<<27) -#define DI_AssertCke (1<<28) +#define DI_AssertCke (1<<28) #define DI_EnDramInit (1<<31)
#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 7 +#define DTL_TCL_SHIFT 0 +#define DTL_TCL_MASK 7 #define DTL_TCL_BASE 1 -#define DTL_TCL_MIN 3 -#define DTL_TCL_MAX 6 +#define DTL_TCL_MIN 3 +#define DTL_TCL_MAX 6 #define DTL_TRCD_SHIFT 4 -#define DTL_TRCD_MASK 3 +#define DTL_TRCD_MASK 3 #define DTL_TRCD_BASE 3 -#define DTL_TRCD_MIN 3 -#define DTL_TRCD_MAX 6 -#define DTL_TRP_SHIFT 8 -#define DTL_TRP_MASK 3 -#define DTL_TRP_BASE 3 -#define DTL_TRP_MIN 3 -#define DTL_TRP_MAX 6 +#define DTL_TRCD_MIN 3 +#define DTL_TRCD_MAX 6 +#define DTL_TRP_SHIFT 8 +#define DTL_TRP_MASK 3 +#define DTL_TRP_BASE 3 +#define DTL_TRP_MIN 3 +#define DTL_TRP_MAX 6 #define DTL_TRTP_SHIFT 11 -#define DTL_TRTP_MASK 1 +#define DTL_TRTP_MASK 1 #define DTL_TRTP_BASE 2 -#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ -#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ +#define DTL_TRTP_MIN 2 /* 4 for 64 bytes*/ +#define DTL_TRTP_MAX 3 /* 5 for 64 bytes */ #define DTL_TRAS_SHIFT 12 -#define DTL_TRAS_MASK 0xf +#define DTL_TRAS_MASK 0xf #define DTL_TRAS_BASE 3 -#define DTL_TRAS_MIN 5 -#define DTL_TRAS_MAX 18 -#define DTL_TRC_SHIFT 16 -#define DTL_TRC_MASK 0xf -#define DTL_TRC_BASE 11 -#define DTL_TRC_MIN 11 -#define DTL_TRC_MAX 26 -#define DTL_TWR_SHIFT 20 -#define DTL_TWR_MASK 3 -#define DTL_TWR_BASE 3 -#define DTL_TWR_MIN 3 -#define DTL_TWR_MAX 6 -#define DTL_TRRD_SHIFT 22 -#define DTL_TRRD_MASK 3 -#define DTL_TRRD_BASE 2 -#define DTL_TRRD_MIN 2 -#define DTL_TRRD_MAX 5 -#define DTL_MemClkDis_SHIFT 24 /* Channel A */ -#define DTL_MemClkDis3 (1 << 26) -#define DTL_MemClkDis2 (1 << 27) -#define DTL_MemClkDis1 (1 << 28) -#define DTL_MemClkDis0 (1 << 29) -#define DTL_MemClkDis1_AM2 (0x51 << 24) -#define DTL_MemClkDis0_AM2 (0xa2 << 24) -#define DTL_MemClkDis0_S1g1 (0xa2 << 24) +#define DTL_TRAS_MIN 5 +#define DTL_TRAS_MAX 18 +#define DTL_TRC_SHIFT 16 +#define DTL_TRC_MASK 0xf +#define DTL_TRC_BASE 11 +#define DTL_TRC_MIN 11 +#define DTL_TRC_MAX 26 +#define DTL_TWR_SHIFT 20 +#define DTL_TWR_MASK 3 +#define DTL_TWR_BASE 3 +#define DTL_TWR_MIN 3 +#define DTL_TWR_MAX 6 +#define DTL_TRRD_SHIFT 22 +#define DTL_TRRD_MASK 3 +#define DTL_TRRD_BASE 2 +#define DTL_TRRD_MIN 2 +#define DTL_TRRD_MAX 5 +#define DTL_MemClkDis_SHIFT 24 /* Channel A */ +#define DTL_MemClkDis3 (1 << 26) +#define DTL_MemClkDis2 (1 << 27) +#define DTL_MemClkDis1 (1 << 28) +#define DTL_MemClkDis0 (1 << 29) +#define DTL_MemClkDis1_AM2 (0x51 << 24) +#define DTL_MemClkDis0_AM2 (0xa2 << 24) +#define DTL_MemClkDis0_S1g1 (0xa2 << 24)
/* DTL_MemClkDis for m2 and s1g1 is different */
#define DRAM_TIMING_HIGH 0x8c #define DTH_TRWTTO_SHIFT 4 #define DTH_TRWTTO_MASK 7 -#define DTH_TRWTTO_BASE 2 -#define DTH_TRWTTO_MIN 2 -#define DTH_TRWTTO_MAX 9 +#define DTH_TRWTTO_BASE 2 +#define DTH_TRWTTO_MIN 2 +#define DTH_TRWTTO_MAX 9 #define DTH_TWTR_SHIFT 8 -#define DTH_TWTR_MASK 3 +#define DTH_TWTR_MASK 3 #define DTH_TWTR_BASE 0 -#define DTH_TWTR_MIN 1 -#define DTH_TWTR_MAX 3 +#define DTH_TWTR_MIN 1 +#define DTH_TWTR_MAX 3 #define DTH_TWRRD_SHIFT 10 #define DTH_TWRRD_MASK 3 #define DTH_TWRRD_BASE 0 #define DTH_TWRRD_MIN 0 #define DTH_TWRRD_MAX 3 #define DTH_TWRWR_SHIFT 12 -#define DTH_TWRWR_MASK 3 -#define DTH_TWRWR_BASE 1 -#define DTH_TWRWR_MIN 1 -#define DTH_TWRWR_MAX 3 +#define DTH_TWRWR_MASK 3 +#define DTH_TWRWR_BASE 1 +#define DTH_TWRWR_MIN 1 +#define DTH_TWRWR_MAX 3 #define DTH_TRDRD_SHIFT 14 -#define DTH_TRDRD_MASK 3 -#define DTH_TRDRD_BASE 2 -#define DTH_TRDRD_MIN 2 -#define DTH_TRDRD_MAX 5 +#define DTH_TRDRD_MASK 3 +#define DTH_TRDRD_BASE 2 +#define DTH_TRDRD_MIN 2 +#define DTH_TRDRD_MAX 5 #define DTH_TREF_SHIFT 16 -#define DTH_TREF_MASK 3 +#define DTH_TREF_MASK 3 #define DTH_TREF_7_8_US 2 #define DTH_TREF_3_9_US 3 #define DTH_TRFC0_SHIFT 20 /* for Logical DIMM0 */ -#define DTH_TRFC_MASK 7 +#define DTH_TRFC_MASK 7 #define DTH_TRFC_75_256M 0 #define DTH_TRFC_105_512M 1 -#define DTH_TRFC_127_5_1G 2 -#define DTH_TRFC_195_2G 3 -#define DTH_TRFC_327_5_4G 4 +#define DTH_TRFC_127_5_1G 2 +#define DTH_TRFC_195_2G 3 +#define DTH_TRFC_327_5_4G 4 #define DTH_TRFC1_SHIFT 23 /*for Logical DIMM1 */ #define DTH_TRFC2_SHIFT 26 /*for Logical DIMM2 */ #define DTH_TRFC3_SHIFT 29 /*for Logical DIMM3 */
#define DRAM_CONFIG_LOW 0x90 -#define DCL_InitDram (1<<0) +#define DCL_InitDram (1<<0) #define DCL_ExitSelfRef (1<<1) #define DCL_DramTerm_SHIFT 4 #define DCL_DramTerm_MASK 3 -#define DCL_DramTerm_No 0 -#define DCL_DramTerm_75_OH 1 -#define DCL_DramTerm_150_OH 2 -#define DCL_DramTerm_50_OH 3 -#define DCL_DrvWeak (1<<7) +#define DCL_DramTerm_No 0 +#define DCL_DramTerm_75_OH 1 +#define DCL_DramTerm_150_OH 2 +#define DCL_DramTerm_50_OH 3 +#define DCL_DrvWeak (1<<7) #define DCL_ParEn (1<<8) #define DCL_SelfRefRateEn (1<<9) #define DCL_BurstLength32 (1<<10) -#define DCL_Width128 (1<<11) +#define DCL_Width128 (1<<11) #define DCL_X4Dimm_SHIFT 12 #define DCL_X4Dimm_MASK 0xf -#define DCL_UnBuffDimm (1<<16) -#define DCL_DimmEccEn (1<<19) +#define DCL_UnBuffDimm (1<<16) +#define DCL_DimmEccEn (1<<19)
#define DRAM_CONFIG_HIGH 0x94 #define DCH_MemClkFreq_SHIFT 0 #define DCH_MemClkFreq_MASK 7 -#define DCH_MemClkFreq_200MHz 0 -#define DCH_MemClkFreq_266MHz 1 -#define DCH_MemClkFreq_333MHz 2 +#define DCH_MemClkFreq_200MHz 0 +#define DCH_MemClkFreq_266MHz 1 +#define DCH_MemClkFreq_333MHz 2 #define DCH_MemClkFreq_400MHz 3 #define DCH_MemClkFreqVal (1<<3) #define DCH_MaxAsyncLat_SHIFT 4 -#define DCH_MaxAsyncLat_MASK 0xf +#define DCH_MaxAsyncLat_MASK 0xf #define DCH_MaxAsyncLat_BASE 0 -#define DCH_MaxAsyncLat_MIN 0 -#define DCH_MaxAsyncLat_MAX 15 -#define DCH_RDqsEn (1<<12) +#define DCH_MaxAsyncLat_MIN 0 +#define DCH_MaxAsyncLat_MAX 15 +#define DCH_RDqsEn (1<<12) #define DCH_DisDramInterface (1<<14) #define DCH_PowerDownEn (1<<15) #define DCH_PowerDownMode_SHIFT 16 #define DCH_PowerDownMode_MASK 1 -#define DCH_PowerDownMode_Channel_CKE 0 -#define DCH_PowerDownMode_ChipSelect_CKE 1 +#define DCH_PowerDownMode_Channel_CKE 0 +#define DCH_PowerDownMode_ChipSelect_CKE 1 #define DCH_FourRankSODimm (1<<17) #define DCH_FourRankRDimm (1<<18) #define DCH_SlowAccessMode (1<<19) -#define DCH_BankSwizzleMode (1<<22) +#define DCH_BankSwizzleMode (1<<22) #define DCH_DcqBypassMax_SHIFT 24 #define DCH_DcqBypassMax_MASK 0xf -#define DCH_DcqBypassMax_BASE 0 -#define DCH_DcqBypassMax_MIN 0 -#define DCH_DcqBypassMax_MAX 15 +#define DCH_DcqBypassMax_BASE 0 +#define DCH_DcqBypassMax_MIN 0 +#define DCH_DcqBypassMax_MAX 15 #define DCH_FourActWindow_SHIFT 28 #define DCH_FourActWindow_MASK 0xf -#define DCH_FourActWindow_BASE 7 -#define DCH_FourActWindow_MIN 8 -#define DCH_FourActWindow_MAX 20 +#define DCH_FourActWindow_BASE 7 +#define DCH_FourActWindow_MIN 8 +#define DCH_FourActWindow_MAX 20
// for 0x98 index and 0x9c data @@ -244,52 +244,52 @@ #define DRAM_OUTPUT_DRV_COMP_CTRL 0x00 #define DODCC_CkeDrvStren_SHIFT 0 #define DODCC_CkeDrvStren_MASK 3 -#define DODCC_CkeDrvStren_1_0X 0 -#define DODCC_CkeDrvStren_1_25X 1 -#define DODCC_CkeDrvStren_1_5X 2 -#define DODCC_CkeDrvStren_2_0X 3 +#define DODCC_CkeDrvStren_1_0X 0 +#define DODCC_CkeDrvStren_1_25X 1 +#define DODCC_CkeDrvStren_1_5X 2 +#define DODCC_CkeDrvStren_2_0X 3 #define DODCC_CsOdtDrvStren_SHIFT 4 #define DODCC_CsOdtDrvStren_MASK 3 -#define DODCC_CsOdtDrvStren_1_0X 0 -#define DODCC_CsOdtDrvStren_1_25X 1 -#define DODCC_CsOdtDrvStren_1_5X 2 -#define DODCC_CsOdtDrvStren_2_0X 3 +#define DODCC_CsOdtDrvStren_1_0X 0 +#define DODCC_CsOdtDrvStren_1_25X 1 +#define DODCC_CsOdtDrvStren_1_5X 2 +#define DODCC_CsOdtDrvStren_2_0X 3 #define DODCC_AddrCmdDrvStren_SHIFT 8 #define DODCC_AddrCmdDrvStren_MASK 3 -#define DODCC_AddrCmdDrvStren_1_0X 0 -#define DODCC_AddrCmdDrvStren_1_25X 1 -#define DODCC_AddrCmdDrvStren_1_5X 2 -#define DODCC_AddrCmdDrvStren_2_0X 3 +#define DODCC_AddrCmdDrvStren_1_0X 0 +#define DODCC_AddrCmdDrvStren_1_25X 1 +#define DODCC_AddrCmdDrvStren_1_5X 2 +#define DODCC_AddrCmdDrvStren_2_0X 3 #define DODCC_ClkDrvStren_SHIFT 12 #define DODCC_ClkDrvStren_MASK 3 -#define DODCC_ClkDrvStren_0_75X 0 -#define DODCC_ClkDrvStren_1_0X 1 -#define DODCC_ClkDrvStren_1_25X 2 -#define DODCC_ClkDrvStren_1_5X 3 +#define DODCC_ClkDrvStren_0_75X 0 +#define DODCC_ClkDrvStren_1_0X 1 +#define DODCC_ClkDrvStren_1_25X 2 +#define DODCC_ClkDrvStren_1_5X 3 #define DODCC_DataDrvStren_SHIFT 16 #define DODCC_DataDrvStren_MASK 3 -#define DODCC_DataDrvStren_0_75X 0 -#define DODCC_DataDrvStren_1_0X 1 -#define DODCC_DataDrvStren_1_25X 2 -#define DODCC_DataDrvStren_1_5X 3 +#define DODCC_DataDrvStren_0_75X 0 +#define DODCC_DataDrvStren_1_0X 1 +#define DODCC_DataDrvStren_1_25X 2 +#define DODCC_DataDrvStren_1_5X 3 #define DODCC_DqsDrvStren_SHIFT 20 #define DODCC_DqsDrvStren_MASK 3 -#define DODCC_DqsDrvStren_0_75X 0 -#define DODCC_DqsDrvStren_1_0X 1 -#define DODCC_DqsDrvStren_1_25X 2 -#define DODCC_DqsDrvStren_1_5X 3 +#define DODCC_DqsDrvStren_0_75X 0 +#define DODCC_DqsDrvStren_1_0X 1 +#define DODCC_DqsDrvStren_1_25X 2 +#define DODCC_DqsDrvStren_1_5X 3 #define DODCC_ProcOdt_SHIFT 28 #define DODCC_ProcOdt_MASK 3 -#define DODCC_ProcOdt_300_OHMS 0 -#define DODCC_ProcOdt_150_OHMS 1 -#define DODCC_ProcOdt_75_OHMS 2 +#define DODCC_ProcOdt_300_OHMS 0 +#define DODCC_ProcOdt_150_OHMS 1 +#define DODCC_ProcOdt_75_OHMS 2
#define DRAM_WRITE_DATA_TIMING_CTRL_LOW 0x01 #define DWDTCL_WrDatTimeByte0_SHIFT 0 #define DWDTC_WrDatTimeByte_MASK 0x3f -#define DWDTC_WrDatTimeByte_BASE 0 -#define DWDTC_WrDatTimeByte_MIN 0 -#define DWDTC_WrDatTimeByte_MAX 47 +#define DWDTC_WrDatTimeByte_BASE 0 +#define DWDTC_WrDatTimeByte_MIN 0 +#define DWDTC_WrDatTimeByte_MAX 47 #define DWDTCL_WrDatTimeByte1_SHIFT 8 #define DWDTCL_WrDatTimeByte2_SHIFT 16 #define DWDTCL_WrDatTimeByte3_SHIFT 24 @@ -303,36 +303,36 @@ #define DRAM_WRITE_DATA_ECC_TIMING_CTRL 0x03 #define DWDETC_WrChkTime_SHIFT 0 #define DWDETC_WrChkTime_MASK 0x3f -#define DWDETC_WrChkTime_BASE 0 -#define DWDETC_WrChkTime_MIN 0 -#define DWDETC_WrChkTime_MAX 47 +#define DWDETC_WrChkTime_BASE 0 +#define DWDETC_WrChkTime_MIN 0 +#define DWDETC_WrChkTime_MAX 47
#define DRAM_ADDR_TIMING_CTRL 0x04 #define DATC_CkeFineDelay_SHIFT 0 #define DATC_CkeFineDelay_MASK 0x1f -#define DATC_CkeFineDelay_BASE 0 -#define DATC_CkeFineDelay_MIN 0 -#define DATC_CkeFineDelay_MAX 31 +#define DATC_CkeFineDelay_BASE 0 +#define DATC_CkeFineDelay_MIN 0 +#define DATC_CkeFineDelay_MAX 31 #define DATC_CkeSetup (1<<5) #define DATC_CsOdtFineDelay_SHIFT 8 #define DATC_CsOdtFineDelay_MASK 0x1f -#define DATC_CsOdtFineDelay_BASE 0 -#define DATC_CsOdtFineDelay_MIN 0 -#define DATC_CsOdtFineDelay_MAX 31 +#define DATC_CsOdtFineDelay_BASE 0 +#define DATC_CsOdtFineDelay_MIN 0 +#define DATC_CsOdtFineDelay_MAX 31 #define DATC_CsOdtSetup (1<<13) #define DATC_AddrCmdFineDelay_SHIFT 16 #define DATC_AddrCmdFineDelay_MASK 0x1f -#define DATC_AddrCmdFineDelay_BASE 0 -#define DATC_AddrCmdFineDelay_MIN 0 -#define DATC_AddrCmdFineDelay_MAX 31 +#define DATC_AddrCmdFineDelay_BASE 0 +#define DATC_AddrCmdFineDelay_MIN 0 +#define DATC_AddrCmdFineDelay_MAX 31 #define DATC_AddrCmdSetup (1<<21)
#define DRAM_READ_DQS_TIMING_CTRL_LOW 0x05 #define DRDTCL_RdDqsTimeByte0_SHIFT 0 #define DRDTC_RdDqsTimeByte_MASK 0x3f -#define DRDTC_RdDqsTimeByte_BASE 0 -#define DRDTC_RdDqsTimeByte_MIN 0 -#define DRDTC_RdDqsTimeByte_MAX 47 +#define DRDTC_RdDqsTimeByte_BASE 0 +#define DRDTC_RdDqsTimeByte_MIN 0 +#define DRDTC_RdDqsTimeByte_MAX 47 #define DRDTCL_RdDqsTimeByte1_SHIFT 8 #define DRDTCL_RdDqsTimeByte2_SHIFT 16 #define DRDTCL_RdDqsTimeByte3_SHIFT 24 @@ -346,22 +346,22 @@ #define DRAM_READ_DQS_ECC_TIMING_CTRL 0x07 #define DRDETC_RdDqsTimeCheck_SHIFT 0 #define DRDETC_RdDqsTimeCheck_MASK 0x3f -#define DRDETC_RdDqsTimeCheck_BASE 0 -#define DRDETC_RdDqsTimeCheck_MIN 0 -#define DRDETC_RdDqsTimeCheck_MAX 47 +#define DRDETC_RdDqsTimeCheck_BASE 0 +#define DRDETC_RdDqsTimeCheck_MIN 0 +#define DRDETC_RdDqsTimeCheck_MAX 47
#define DRAM_DQS_RECV_ENABLE_TIME0 0x10 #define DDRET_DqsRcvEnDelay_SHIFT 0 #define DDRET_DqsRcvEnDelay_MASK 0xff -#define DDRET_DqsRcvEnDelay_BASE 0 -#define DDRET_DqsRcvEnDelay_MIN 0 -#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */ +#define DDRET_DqsRcvEnDelay_BASE 0 +#define DDRET_DqsRcvEnDelay_MIN 0 +#define DDRET_DqsRcvEnDelay_MAX 0xae /* unit is 50ps */
#define DRAM_DQS_RECV_ENABLE_TIME1 0x13 #define DRAM_DQS_RECV_ENABLE_TIME2 0x16 #define DRAM_DQS_RECV_ENABLE_TIME3 0x19
-/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 +/* there are index 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x30, 0x33, 0x36, 0x39 that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, 0x13, 0x16, 0x19 */ #define DRAM_CTRL_MISC 0xa0 @@ -369,75 +369,75 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, #define DCM_DisableJitter (1<<1) #define DCM_RdWrQByp_SHIFT 2 #define DCM_RdWrQByp_MASK 3 -#define DCM_RdWrQByp_2 0 -#define DCM_RdWrQByp_4 1 -#define DCM_RdWrQByp_8 2 -#define DCM_RdWrQByp_16 3 +#define DCM_RdWrQByp_2 0 +#define DCM_RdWrQByp_4 1 +#define DCM_RdWrQByp_8 2 +#define DCM_RdWrQByp_16 3 #define DCM_Mode64BitMux (1<<4) #define DCM_DCC_EN (1<<5) #define DCM_ILD_lmt_SHIFT 6 #define DCM_ILD_lmt_MASK 7 -#define DCM_ILD_lmt_0 0 -#define DCM_ILD_lmt_4 1 -#define DCM_ILD_lmt_8 2 -#define DCM_ILD_lmt_16 3 -#define DCM_ILD_lmt_32 4 -#define DCM_ILD_lmt_64 5 -#define DCM_ILD_lmt_128 6 -#define DCM_ILD_lmt_256 7 +#define DCM_ILD_lmt_0 0 +#define DCM_ILD_lmt_4 1 +#define DCM_ILD_lmt_8 2 +#define DCM_ILD_lmt_16 3 +#define DCM_ILD_lmt_32 4 +#define DCM_ILD_lmt_64 5 +#define DCM_ILD_lmt_128 6 +#define DCM_ILD_lmt_256 7 #define DCM_DramEnabled (1<<9) -#define DCM_MemClkDis_SHIFT 24 /* Channel B */ -#define DCM_MemClkDis3 (1 << 26) -#define DCM_MemClkDis2 (1 << 27) -#define DCM_MemClkDis1 (1 << 28) -#define DCM_MemClkDis0 (1 << 29) +#define DCM_MemClkDis_SHIFT 24 /* Channel B */ +#define DCM_MemClkDis3 (1 << 26) +#define DCM_MemClkDis2 (1 << 27) +#define DCM_MemClkDis1 (1 << 28) +#define DCM_MemClkDis0 (1 << 29)
/* Function 3 */ -#define MCA_NB_CONFIG 0x44 -#define MNC_ECC_EN (1 << 22) -#define MNC_CHIPKILL_EN (1 << 23) - -#define SCRUB_CONTROL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 10 -#define SCRUB_41_0us 11 -#define SCRUB_81_9us 12 +#define MCA_NB_CONFIG 0x44 +#define MNC_ECC_EN (1 << 22) +#define MNC_CHIPKILL_EN (1 << 23) + +#define SCRUB_CONTROL 0x58 +#define SCRUB_NONE 0 +#define SCRUB_40ns 1 +#define SCRUB_80ns 2 +#define SCRUB_160ns 3 +#define SCRUB_320ns 4 +#define SCRUB_640ns 5 +#define SCRUB_1_28us 6 +#define SCRUB_2_56us 7 +#define SCRUB_5_12us 8 +#define SCRUB_10_2us 9 +#define SCRUB_20_5us 10 +#define SCRUB_41_0us 11 +#define SCRUB_81_9us 12 #define SCRUB_163_8us 13 #define SCRUB_327_7us 14 #define SCRUB_655_4us 15 -#define SCRUB_1_31ms 16 -#define SCRUB_2_62ms 17 -#define SCRUB_5_24ms 18 +#define SCRUB_1_31ms 16 +#define SCRUB_2_62ms 17 +#define SCRUB_5_24ms 18 #define SCRUB_10_49ms 19 #define SCRUB_20_97ms 20 -#define SCRUB_42ms 21 -#define SCRUB_84ms 22 +#define SCRUB_42ms 21 +#define SCRUB_84ms 22 #define SC_DRAM_SCRUB_RATE_SHFIT 0 #define SC_DRAM_SCRUB_RATE_MASK 0x1f #define SC_L2_SCRUB_RATE_SHIFT 8 -#define SC_L2_SCRUB_RATE_MASK 0x1f +#define SC_L2_SCRUB_RATE_MASK 0x1f #define SC_L1D_SCRUB_RATE_SHIFT 16 #define SC_L1D_SCRUB_RATE_MASK 0x1f
-#define SCRUB_ADDR_LOW 0x5C +#define SCRUB_ADDR_LOW 0x5C
#define SCRUB_ADDR_HIGH 0x60
#define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_128Bit (1 << 0) -#define NBCAP_MP (1 << 1) -#define NBCAP_BIG_MP (1 << 2) -#define NBCAP_ECC (1 << 3) +#define NBCAP_128Bit (1 << 0) +#define NBCAP_MP (1 << 1) +#define NBCAP_BIG_MP (1 << 2) +#define NBCAP_ECC (1 << 3) #define NBCAP_CHIPKILL_ECC (1 << 4) #define NBCAP_MEMCLK_SHIFT 5 #define NBCAP_MEMCLK_MASK 3 @@ -445,15 +445,15 @@ that are corresponding to 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x10, #define NBCAP_MEMCLK_266MHZ 2 #define NBCAP_MEMCLK_333MHZ 1 #define NBCAP_MEMCLK_NOLIMIT 0 -#define NBCAP_MEMCTRL (1 << 8) +#define NBCAP_MEMCTRL (1 << 8) #define NBCAP_HtcCap (1<<10) #define NBCAP_CmpCap_SHIFT 12 #define NBCAP_CmpCap_MASK 3
-#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) #define ConnectionPending (1 << 4)
#include "raminit.h" diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index e5bcdcb..b0bca2a 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -19,8 +19,8 @@ */
-// 2005.9 yhlu serengeti support -// 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB +// 2005.9 yhlu serengeti support +// 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB // 2007.9 stepan improve code documentation
#include <console/console.h> @@ -100,22 +100,22 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * For this example you need to set * * unsigned pci1234[] = { - * 0x0000ff0, - * 0x0000f10, // HT IO 1 card always on node 1 - * 0x0000f20, // HT IO 2 card always on node 2 - * 0x0000f30 // HT IO 3 card always on node 3 + * 0x0000ff0, + * 0x0000f10, // HT IO 1 card always on node 1 + * 0x0000f20, // HT IO 2 card always on node 2 + * 0x0000f30 // HT IO 3 card always on node 3 * }; * * For 2P + htio(n1) + htio(n0_1) + htio(n1_1), 2P + htio(n1) + 2P + htio(n2) + htio(n3): * You need an array pci1234[6]: * * unsigned pci1234[] = { - * 0x0000ff0, - * 0x0000010, // HT IO 1 card always on node 1 - * 0x0000f00, // HT IO 2 card always on node 0 - * 0x0000110, // HT IO 3 card always on node 1 - * 0x0000f20, // HT IO 4 card always on node 2 - * 0x0000f30 // HT IO 5 card always on node 3 + * 0x0000ff0, + * 0x0000010, // HT IO 1 card always on node 1 + * 0x0000f00, // HT IO 2 card always on node 0 + * 0x0000110, // HT IO 3 card always on node 1 + * 0x0000f20, // HT IO 4 card always on node 2 + * 0x0000f30 // HT IO 5 card always on node 3 * }; * * @@ -123,12 +123,12 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * You need an array pci1234[6]: * * unsigned pci1234[] = { - * 0x0000ff0, - * 0x0000f10, // HT IO 1 card always on node 1 - * 0x0000f20, // HT IO 2 card always on node 2 - * 0x0000f30, // HT IO 3 card always on node 3 - * 0x0000f60, // HT IO 4 card always on node 6 - * 0x0000f70 // HT IO 5 card always on node 7 + * 0x0000ff0, + * 0x0000f10, // HT IO 1 card always on node 1 + * 0x0000f20, // HT IO 2 card always on node 2 + * 0x0000f30, // HT IO 3 card always on node 3 + * 0x0000f60, // HT IO 4 card always on node 6 + * 0x0000f70 // HT IO 5 card always on node 7 * }; * * @@ -137,14 +137,14 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * you need an array pci1234[8]: * * unsigned pci1234[] = { - * 0x0000ff0, - * 0x0000010, // HT IO 1 card always on node 1 - * 0x0000f00, // HT IO 2 card always on node 0 - * 0x0000110, // HT IO 3 card always on node 1 - * 0x0000f20, // HT IO 4 card always on node 2 - * 0x0000f30 // HT IO 5 card always on node 3 - * 0x0000f40, // HT IO 6 card always on node 4 - * 0x0000f50 // HT IO 7 card always on node 5 + * 0x0000ff0, + * 0x0000010, // HT IO 1 card always on node 1 + * 0x0000f00, // HT IO 2 card always on node 0 + * 0x0000110, // HT IO 3 card always on node 1 + * 0x0000f20, // HT IO 4 card always on node 2 + * 0x0000f30 // HT IO 5 card always on node 3 + * 0x0000f40, // HT IO 6 card always on node 4 + * 0x0000f50 // HT IO 7 card always on node 5 * }; * * @@ -153,25 +153,25 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * you need an array pci1234[8]: * * unsigned pci1234[] = { - * 0x0000ff0, - * 0x0000f10, // HT IO 1 card always on node 1 - * 0x0000f20, // HT IO 2 card always on node 2 - * 0x0000f30, // HT IO 3 card always on node 3 - * 0x0000f40, // HT IO 4 card always on node 4 - * 0x0000f50 // HT IO 5 card always on node 5 - * 0x0000f60, // HT IO 6 card always on node 6 - * 0x0000f70 // HT IO 7 card always on node 7 + * 0x0000ff0, + * 0x0000f10, // HT IO 1 card always on node 1 + * 0x0000f20, // HT IO 2 card always on node 2 + * 0x0000f30, // HT IO 3 card always on node 3 + * 0x0000f40, // HT IO 4 card always on node 4 + * 0x0000f50 // HT IO 5 card always on node 5 + * 0x0000f60, // HT IO 6 card always on node 6 + * 0x0000f70 // HT IO 7 card always on node 7 * }; * * * So the maximum posible value of HC_POSSIBLE_NUM is 8. (FIXME Why?) * - * 1n: 3 + * 1n: 3 * 2n: 2x2 - 1 * 4n: 1x4 - 2 - * 6n: 2 - * 8n: 2 - * Total: 12 + * 6n: 2 + * 8n: 2 + * Total: 12 * * Just put all the possible HT Node/link to the list tp pci1234[] in * src/mainboard/<vendor>/<mainboard>get_bus_conf.c diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 6cbe7dc..34aaee9 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -79,7 +79,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000))) { + (id == 0x0000ffff) || (id == 0xffff0000))) { return; } } @@ -178,9 +178,9 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \ (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
-#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF) +#define LINK_CTRL(OFFS) ((OFFS >> 24) & 0xFF) #define LINK_WIDTH(OFFS) ((OFFS >> 16) & 0xFF) -#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF) +#define LINK_FREQ(OFFS) ((OFFS >> 8) & 0xFF) #define LINK_FREQ_CAP(OFFS) ((OFFS) & 0xFF)
#define PCI_HT_HOST_OFFS LINK_OFFS( \ diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 030c992..8914750 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -221,15 +221,15 @@ static void misc_control_init(struct device *dev)
static struct device_operations mcf3_ops = { .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources, + .set_resources = mcf3_set_resources, .enable_resources = pci_dev_enable_resources, - .init = misc_control_init, - .scan_bus = 0, - .ops_pci = 0, + .init = misc_control_init, + .scan_bus = 0, + .ops_pci = 0, };
static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1103, }; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8f0a11b..bb7587f 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -296,7 +296,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, }
static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, - unsigned min, unsigned max) + unsigned min, unsigned max) { unsigned resource; unsigned free_reg, reg; @@ -454,7 +454,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n", - __func__, dev_path(dev), link_num); + __func__, dev_path(dev), link_num); base |= PCI_IO_BASE_VGA_EN; } if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { @@ -547,7 +547,7 @@ static void amdk8_set_resources(device_t dev) IOINDEX_LINK(res->index)); else index = amdk8_find_mempair(dev, nodeid, - IOINDEX_LINK(res->index)); + IOINDEX_LINK(res->index));
old = probe_resource(dev, index); if (old) { @@ -971,8 +971,8 @@ static void amdk8_domain_set_resources(device_t dev)
if(reset_memhole) { if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! - // We need to reset our Mem Hole, because We want more big HOLE than we already set - //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead + // We need to reset our Mem Hole, because We want more big HOLE than we already set + //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); }
@@ -1051,7 +1051,7 @@ static void amdk8_domain_set_resources(device_t dev) #if !CONFIG_K8_REV_F_SUPPORT if(!is_cpu_pre_e0() ) #endif - sizek += hoist_memory(mmio_basek,i); + sizek += hoist_memory(mmio_basek,i); #endif
basek = mmio_basek; @@ -1068,7 +1068,7 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", - i, mmio_basek, basek, limitk); + i, mmio_basek, basek, limitk); if (!ramtop) ramtop = limitk * 1024; } @@ -1256,14 +1256,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) // That is the typical case
if(j == 0 ){ - #if !CONFIG_K8_REV_F_SUPPORT - e0_later_single_core = is_e0_later_in_bsp(i); // single core - #else - e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 - #endif + #if !CONFIG_K8_REV_F_SUPPORT + e0_later_single_core = is_e0_later_in_bsp(i); // single core + #else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 + #endif } else { - e0_later_single_core = 0; - } + e0_later_single_core = 0; + } if(e0_later_single_core) { printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 0e0f9f4..6d16291 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -4,37 +4,37 @@ /* Definitions of various K8 registers */ /* Function 0 */ #define HT_TRANSACTION_CONTROL 0x68 -#define HTTC_DIS_RD_B_P (1 << 0) -#define HTTC_DIS_RD_DW_P (1 << 1) -#define HTTC_DIS_WR_B_P (1 << 2) -#define HTTC_DIS_WR_DW_P (1 << 3) -#define HTTC_DIS_MTS (1 << 4) -#define HTTC_CPU1_EN (1 << 5) -#define HTTC_CPU_REQ_PASS_PW (1 << 6) +#define HTTC_DIS_RD_B_P (1 << 0) +#define HTTC_DIS_RD_DW_P (1 << 1) +#define HTTC_DIS_WR_B_P (1 << 2) +#define HTTC_DIS_WR_DW_P (1 << 3) +#define HTTC_DIS_MTS (1 << 4) +#define HTTC_CPU1_EN (1 << 5) +#define HTTC_CPU_REQ_PASS_PW (1 << 6) #define HTTC_CPU_RD_RSP_PASS_PW (1 << 7) -#define HTTC_DIS_P_MEM_C (1 << 8) -#define HTTC_DIS_RMT_MEM_C (1 << 9) -#define HTTC_DIS_FILL_P (1 << 10) -#define HTTC_RSP_PASS_PW (1 << 11) -#define HTTC_CHG_ISOC_TO_ORD (1 << 12) -#define HTTC_BUF_REL_PRI_SHIFT 13 -#define HTTC_BUF_REL_PRI_MASK 3 -#define HTTC_BUF_REL_PRI_64 0 -#define HTTC_BUF_REL_PRI_16 1 -#define HTTC_BUF_REL_PRI_8 2 -#define HTTC_BUF_REL_PRI_2 3 -#define HTTC_LIMIT_CLDT_CFG (1 << 15) -#define HTTC_LINT_EN (1 << 16) -#define HTTC_APIC_EXT_BRD_CST (1 << 17) -#define HTTC_APIC_EXT_ID (1 << 18) -#define HTTC_APIC_EXT_SPUR (1 << 19) +#define HTTC_DIS_P_MEM_C (1 << 8) +#define HTTC_DIS_RMT_MEM_C (1 << 9) +#define HTTC_DIS_FILL_P (1 << 10) +#define HTTC_RSP_PASS_PW (1 << 11) +#define HTTC_CHG_ISOC_TO_ORD (1 << 12) +#define HTTC_BUF_REL_PRI_SHIFT 13 +#define HTTC_BUF_REL_PRI_MASK 3 +#define HTTC_BUF_REL_PRI_64 0 +#define HTTC_BUF_REL_PRI_16 1 +#define HTTC_BUF_REL_PRI_8 2 +#define HTTC_BUF_REL_PRI_2 3 +#define HTTC_LIMIT_CLDT_CFG (1 << 15) +#define HTTC_LINT_EN (1 << 16) +#define HTTC_APIC_EXT_BRD_CST (1 << 17) +#define HTTC_APIC_EXT_ID (1 << 18) +#define HTTC_APIC_EXT_SPUR (1 << 19) #define HTTC_SEQ_ID_SRC_NODE_EN (1 << 20) #define HTTC_DS_NP_REQ_LIMIT_SHIFT 21 #define HTTC_DS_NP_REQ_LIMIT_MASK 3 -#define HTTC_DS_NP_REQ_LIMIT_NONE 0 -#define HTTC_DS_NP_REQ_LIMIT_1 1 -#define HTTC_DS_NP_REQ_LIMIT_4 2 -#define HTTC_DS_NP_REQ_LIMIT_8 3 +#define HTTC_DS_NP_REQ_LIMIT_NONE 0 +#define HTTC_DS_NP_REQ_LIMIT_1 1 +#define HTTC_DS_NP_REQ_LIMIT_4 2 +#define HTTC_DS_NP_REQ_LIMIT_8 3 #define HTTC_MED_PRI_BYP_CNT_SHIFT 24 #define HTTC_MED_PRI_BYP_CNT_MASK 3 #define HTTC_HI_PRI_BYP_CNT_SHIFT 26 @@ -42,10 +42,10 @@
/* Function 1 */ -#define PCI_IO_BASE0 0xc0 -#define PCI_IO_BASE1 0xc8 -#define PCI_IO_BASE2 0xd0 -#define PCI_IO_BASE3 0xd8 +#define PCI_IO_BASE0 0xc0 +#define PCI_IO_BASE1 0xc8 +#define PCI_IO_BASE2 0xd0 +#define PCI_IO_BASE3 0xd8 #define PCI_IO_BASE_VGA_EN (1 << 4) #define PCI_IO_BASE_NO_ISA (1 << 5)
@@ -56,60 +56,60 @@ #define DRAM_BANK_ADDR_MAP 0x80
#define DRAM_TIMING_LOW 0x88 -#define DTL_TCL_SHIFT 0 -#define DTL_TCL_MASK 0x7 +#define DTL_TCL_SHIFT 0 +#define DTL_TCL_MASK 0x7 #define DTL_CL_2 1 #define DTL_CL_3 2 -#define DTL_CL_2_5 5 -#define DTL_TRC_SHIFT 4 -#define DTL_TRC_MASK 0xf -#define DTL_TRC_BASE 7 -#define DTL_TRC_MIN 7 -#define DTL_TRC_MAX 22 +#define DTL_CL_2_5 5 +#define DTL_TRC_SHIFT 4 +#define DTL_TRC_MASK 0xf +#define DTL_TRC_BASE 7 +#define DTL_TRC_MIN 7 +#define DTL_TRC_MAX 22 #define DTL_TRFC_SHIFT 8 -#define DTL_TRFC_MASK 0xf +#define DTL_TRFC_MASK 0xf #define DTL_TRFC_BASE 9 -#define DTL_TRFC_MIN 9 -#define DTL_TRFC_MAX 24 +#define DTL_TRFC_MIN 9 +#define DTL_TRFC_MAX 24 #define DTL_TRCD_SHIFT 12 -#define DTL_TRCD_MASK 0x7 +#define DTL_TRCD_MASK 0x7 #define DTL_TRCD_BASE 0 -#define DTL_TRCD_MIN 2 -#define DTL_TRCD_MAX 6 +#define DTL_TRCD_MIN 2 +#define DTL_TRCD_MAX 6 #define DTL_TRRD_SHIFT 16 -#define DTL_TRRD_MASK 0x7 +#define DTL_TRRD_MASK 0x7 #define DTL_TRRD_BASE 0 -#define DTL_TRRD_MIN 2 -#define DTL_TRRD_MAX 4 +#define DTL_TRRD_MIN 2 +#define DTL_TRRD_MAX 4 #define DTL_TRAS_SHIFT 20 -#define DTL_TRAS_MASK 0xf +#define DTL_TRAS_MASK 0xf #define DTL_TRAS_BASE 0 -#define DTL_TRAS_MIN 5 -#define DTL_TRAS_MAX 15 -#define DTL_TRP_SHIFT 24 -#define DTL_TRP_MASK 0x7 -#define DTL_TRP_BASE 0 -#define DTL_TRP_MIN 2 -#define DTL_TRP_MAX 6 -#define DTL_TWR_SHIFT 28 -#define DTL_TWR_MASK 0x1 -#define DTL_TWR_BASE 2 -#define DTL_TWR_MIN 2 -#define DTL_TWR_MAX 3 +#define DTL_TRAS_MIN 5 +#define DTL_TRAS_MAX 15 +#define DTL_TRP_SHIFT 24 +#define DTL_TRP_MASK 0x7 +#define DTL_TRP_BASE 0 +#define DTL_TRP_MIN 2 +#define DTL_TRP_MAX 6 +#define DTL_TWR_SHIFT 28 +#define DTL_TWR_MASK 0x1 +#define DTL_TWR_BASE 2 +#define DTL_TWR_MIN 2 +#define DTL_TWR_MAX 3
#define DRAM_TIMING_HIGH 0x8c #define DTH_TWTR_SHIFT 0 -#define DTH_TWTR_MASK 0x1 +#define DTH_TWTR_MASK 0x1 #define DTH_TWTR_BASE 1 -#define DTH_TWTR_MIN 1 -#define DTH_TWTR_MAX 2 +#define DTH_TWTR_MIN 1 +#define DTH_TWTR_MAX 2 #define DTH_TRWT_SHIFT 4 -#define DTH_TRWT_MASK 0x7 +#define DTH_TRWT_MASK 0x7 #define DTH_TRWT_BASE 1 -#define DTH_TRWT_MIN 1 -#define DTH_TRWT_MAX 6 +#define DTH_TRWT_MIN 1 +#define DTH_TRWT_MAX 6 #define DTH_TREF_SHIFT 8 -#define DTH_TREF_MASK 0x1f +#define DTH_TREF_MASK 0x1f #define DTH_TREF_100MHZ_4K 0x00 #define DTH_TREF_133MHZ_4K 0x01 #define DTH_TREF_166MHZ_4K 0x02 @@ -119,32 +119,32 @@ #define DTH_TREF_166MHZ_8K 0x0A #define DTH_TREF_200MHZ_8K 0x0B #define DTH_TWCL_SHIFT 20 -#define DTH_TWCL_MASK 0x7 +#define DTH_TWCL_MASK 0x7 #define DTH_TWCL_BASE 1 -#define DTH_TWCL_MIN 1 -#define DTH_TWCL_MAX 2 +#define DTH_TWCL_MIN 1 +#define DTH_TWCL_MAX 2
#define DRAM_CONFIG_LOW 0x90 #define DCL_DLL_Disable (1<<0) #define DCL_D_DRV (1<<1) #define DCL_QFC_EN (1<<2) -#define DCL_DisDqsHys (1<<3) -#define DCL_Burst2Opt (1<<5) -#define DCL_DramInit (1<<8) -#define DCL_DualDIMMen (1<<9) +#define DCL_DisDqsHys (1<<3) +#define DCL_Burst2Opt (1<<5) +#define DCL_DramInit (1<<8) +#define DCL_DualDIMMen (1<<9) #define DCL_DramEnable (1<<10) #define DCL_MemClrStatus (1<<11) #define DCL_ESR (1<<12) #define DCL_SRS (1<<13) -#define DCL_128BitEn (1<<16) -#define DCL_DimmEccEn (1<<17) +#define DCL_128BitEn (1<<16) +#define DCL_DimmEccEn (1<<17) #define DCL_UnBuffDimm (1<<18) -#define DCL_32ByteEn (1<<19) +#define DCL_32ByteEn (1<<19) #define DCL_x4DIMM_SHIFT 20 -#define DCL_DisInRcvrs (1<<24) +#define DCL_DisInRcvrs (1<<24) #define DCL_BypMax_SHIFT 25 -#define DCL_En2T (1<<28) -#define DCL_UpperCSMap (1<<29) +#define DCL_En2T (1<<28) +#define DCL_UpperCSMap (1<<29)
#define DRAM_CONFIG_HIGH 0x94 #define DCH_ASYNC_LAT_SHIFT 0 @@ -181,46 +181,46 @@ #define DCH_MEMCLK_EN3 (1 << 29)
/* Function 3 */ -#define MCA_NB_CONFIG 0x44 -#define MNC_ECC_EN (1 << 22) -#define MNC_CHIPKILL_EN (1 << 23) -#define SCRUB_CONTROL 0x58 -#define SCRUB_NONE 0 -#define SCRUB_40ns 1 -#define SCRUB_80ns 2 -#define SCRUB_160ns 3 -#define SCRUB_320ns 4 -#define SCRUB_640ns 5 -#define SCRUB_1_28us 6 -#define SCRUB_2_56us 7 -#define SCRUB_5_12us 8 -#define SCRUB_10_2us 9 -#define SCRUB_20_5us 10 -#define SCRUB_41_0us 11 -#define SCRUB_81_9us 12 +#define MCA_NB_CONFIG 0x44 +#define MNC_ECC_EN (1 << 22) +#define MNC_CHIPKILL_EN (1 << 23) +#define SCRUB_CONTROL 0x58 +#define SCRUB_NONE 0 +#define SCRUB_40ns 1 +#define SCRUB_80ns 2 +#define SCRUB_160ns 3 +#define SCRUB_320ns 4 +#define SCRUB_640ns 5 +#define SCRUB_1_28us 6 +#define SCRUB_2_56us 7 +#define SCRUB_5_12us 8 +#define SCRUB_10_2us 9 +#define SCRUB_20_5us 10 +#define SCRUB_41_0us 11 +#define SCRUB_81_9us 12 #define SCRUB_163_8us 13 #define SCRUB_327_7us 14 #define SCRUB_655_4us 15 -#define SCRUB_1_31ms 16 -#define SCRUB_2_62ms 17 -#define SCRUB_5_24ms 18 +#define SCRUB_1_31ms 16 +#define SCRUB_2_62ms 17 +#define SCRUB_5_24ms 18 #define SCRUB_10_49ms 19 #define SCRUB_20_97ms 20 -#define SCRUB_42ms 21 -#define SCRUB_84ms 22 +#define SCRUB_42ms 21 +#define SCRUB_84ms 22 #define SC_DRAM_SCRUB_RATE_SHFIT 0 #define SC_DRAM_SCRUB_RATE_MASK 0x1f #define SC_L2_SCRUB_RATE_SHIFT 8 -#define SC_L2_SCRUB_RATE_MASK 0x1f +#define SC_L2_SCRUB_RATE_MASK 0x1f #define SC_L1D_SCRUB_RATE_SHIFT 16 #define SC_L1D_SCRUB_RATE_MASK 0x1f -#define SCRUB_ADDR_LOW 0x5C +#define SCRUB_ADDR_LOW 0x5C #define SCRUB_ADDR_HIGH 0x60 #define NORTHBRIDGE_CAP 0xE8 -#define NBCAP_128Bit (1 << 0) -#define NBCAP_MP (1 << 1) -#define NBCAP_BIG_MP (1 << 2) -#define NBCAP_ECC (1 << 3) +#define NBCAP_128Bit (1 << 0) +#define NBCAP_MP (1 << 1) +#define NBCAP_BIG_MP (1 << 2) +#define NBCAP_ECC (1 << 3) #define NBCAP_CHIPKILL_ECC (1 << 4) #define NBCAP_MEMCLK_SHIFT 5 #define NBCAP_MEMCLK_MASK 3 @@ -228,12 +228,12 @@ #define NBCAP_MEMCLK_133MHZ 2 #define NBCAP_MEMCLK_166MHZ 1 #define NBCAP_MEMCLK_200MHZ 0 -#define NBCAP_MEMCTRL (1 << 8) +#define NBCAP_MEMCTRL (1 << 8)
-#define LinkConnected (1 << 0) -#define InitComplete (1 << 1) -#define NonCoherent (1 << 2) +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) #define ConnectionPending (1 << 4)
#include "raminit.h" diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4aaa1bb..b092d90 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -484,18 +484,18 @@ static void sdram_set_registers(const struct mem_controller *ctrl) * 00011 = 160.00 ns * 00100 = 320.00 ns * 00101 = 640.00 ns - * 00110 = 1.28 us - * 00111 = 2.56 us - * 01000 = 5.12 us + * 00110 = 1.28 us + * 00111 = 2.56 us + * 01000 = 5.12 us * 01001 = 10.20 us * 01011 = 41.00 us * 01100 = 81.90 us * 01101 = 163.80 us * 01110 = 327.70 us * 01111 = 655.40 us - * 10000 = 1.31 ms - * 10001 = 2.62 ms - * 10010 = 5.24 ms + * 10000 = 1.31 ms + * 10001 = 2.62 ms + * 10010 = 5.24 ms * 10011 = 10.49 ms * 10100 = 20.97 ms * 10101 = 42.00 ms @@ -894,17 +894,17 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) };
static const uint8_t csbase_low_d0_shift[] = { - /* 32MB */ (13 - 4), - /* 64MB */ (14 - 4), - /* 128MB */ (14 - 4), - /* 128MB */ (15 - 4), - /* 256MB */ (15 - 4), - /* 512MB */ (15 - 4), - /* 256MB */ (16 - 4), - /* 512MB */ (16 - 4), - /* 1GB */ (16 - 4), - /* 1GB */ (17 - 4), - /* 2GB */ (17 - 4), + /* 32MB */ (13 - 4), + /* 64MB */ (14 - 4), + /* 128MB */ (14 - 4), + /* 128MB */ (15 - 4), + /* 256MB */ (15 - 4), + /* 512MB */ (15 - 4), + /* 256MB */ (16 - 4), + /* 512MB */ (16 - 4), + /* 1GB */ (16 - 4), + /* 1GB */ (17 - 4), + /* 2GB */ (17 - 4), };
/* cs_base_high is not changed */ @@ -2214,7 +2214,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) if (dimm_mask < 0) goto hw_spd_err; result = spd_set_memclk(ctrl, dimm_mask); - param = result.param; + param = result.param; dimm_mask = result.dimm_mask; if (dimm_mask < 0) goto hw_spd_err; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 64271b5..0ce7ea0 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -302,18 +302,18 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [15:12] CS7/6 * [31:16] row col bank - 0: 13 9 2 :128M - 1: 13 10 2 :256M - 2: 14 10 2 :512M - 3: 13 11 2 :512M - 4: 13 10 3 :512M - 5: 14 10 3 :1G - 6: 14 11 2 :1G - 7: 15 10 3 :2G - 8: 14 11 3 :2G - 9: 15 11 3 :4G - 10: 16 10 3 :4G - 11: 16 11 3 :8G + 0: 13 9 2 :128M + 1: 13 10 2 :256M + 2: 14 10 2 :512M + 3: 13 11 2 :512M + 4: 13 10 3 :512M + 5: 14 10 3 :1G + 6: 14 11 2 :1G + 7: 15 10 3 :2G + 8: 14 11 3 :2G + 9: 15 11 3 :4G + 10: 16 10 3 :4G + 11: 16 11 3 :8G */ PCI_ADDR(0, 0x18, 2, 0x80), 0xffff0000, 0x00000000, /* DRAM Timing Low Register @@ -342,9 +342,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [10:10] Reserved * [11:11] Trtp (Read to Precharge Time, read Cas# to precharge time) * 0 = 2 clocks for Burst Length of 32 Bytes - * 4 clocks for Burst Length of 64 Bytes + * 4 clocks for Burst Length of 64 Bytes * 1 = 3 clocks for Burst Length of 32 Bytes - * 5 clocks for Burst Length of 64 Bytes + * 5 clocks for Burst Length of 64 Bytes * [15:12] Tras (Minimum Ras# Active Time) * 0000 = reserved * 0001 = reserved @@ -372,14 +372,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, * BIOS should set it to reduce the power consumption) * Bit F(1207) M2 Package S1g1 Package - * 0 N/A MA1_CLK1 N/A - * 1 N/A MA0_CLK1 MA0_CLK1 - * 2 MA3_CLK N/A N/A - * 3 MA2_CLK N/A N/A - * 4 MA1_CLK MA1_CLK0 N/A - * 5 MA0_CLK MA0_CLK0 MA0_CLK0 - * 6 N/A MA1_CLK2 N/A - * 7 N/A MA0_CLK2 MA0_CLK2 + * 0 N/A MA1_CLK1 N/A + * 1 N/A MA0_CLK1 MA0_CLK1 + * 2 MA3_CLK N/A N/A + * 3 MA2_CLK N/A N/A + * 4 MA1_CLK MA1_CLK0 N/A + * 5 MA0_CLK MA0_CLK0 MA0_CLK0 + * 6 N/A MA1_CLK2 N/A + * 7 N/A MA0_CLK2 MA0_CLK2 */ PCI_ADDR(0, 0x18, 2, 0x88), 0x000004c8, 0xff000002 /* 0x03623125 */ , /* DRAM Timing High Register @@ -445,10 +445,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * F2:0x90 * [ 0: 0] InitDram (Initialize DRAM) * 1 = write 1 cause DRAM controller to execute the DRAM - * initialization, when done it read to 0 + * initialization, when done it read to 0 * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command ) * 1 = write 1 causes the DRAM controller to bring the DRAMs out - * for self refresh mode + * for self refresh mode * [ 3: 2] Reserved * [ 5: 4] DramTerm (DRAM Termination) * 00 = On die termination disabled @@ -461,10 +461,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1 = Weak drive strength mode * [ 8: 8] ParEn (Parity Enable) * 1 = Enable address parity computation output, PAR, - * and enables the parity error input, ERR + * and enables the parity error input, ERR * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable) * 1 = Enable high temperature ( two times normal ) - * self refresh rate + * self refresh rate * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes) * 0 = 64-byte mode * 1 = 32-byte mode @@ -475,15 +475,15 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [13:13] X4Dimm (DIMM 1 is x4) * [14:14] X4Dimm (DIMM 2 is x4) * [15:15] X4Dimm (DIMM 3 is x4) - * 0 = DIMM is not x4 - * 1 = x4 DIMM present + * 0 = DIMM is not x4 + * 1 = x4 DIMM present * [16:16] UnBuffDimm ( Unbuffered DIMMs) * 0 = Buffered DIMMs * 1 = Unbuffered DIMMs * [18:17] Reserved * [19:19] DimmEccEn ( DIMM ECC Enable ) * 1 = ECC checking is being enabled for all DIMMs on the DRAM - * controller ( Through F3 0x44[EccEn]) + * controller ( Through F3 0x44[EccEn]) * [31:20] Reserved */ PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010, @@ -497,11 +497,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1xx = reserved * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid) * 1 = BIOS need to set the bit when setting up MemClkFreq to - * the proper value + * the proper value * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) - * 0000 = 0 ns - * ... - * 1111 = 15 ns + * 0000 = 0 ns + * ... + * 1111 = 15 ns * [11: 8] Reserved * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 * registered DIMMs are present in the system @@ -521,29 +521,29 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1 = Chip Select CKE Control * [17:17] FourRankSODimm (Four Rank SO-DIMM) * 1 = this bit is set by BIOS to indicate that a four rank - * SO-DIMM is present + * SO-DIMM is present * [18:18] FourRankRDimm (Four Rank Registered DIMM) - * 1 = this bit is set by BIOS to indicate that a four rank - * registered DIMM is present + * 1 = this bit is set by BIOS to indicate that a four rank + * registered DIMM is present * [19:19] Reserved * [20:20] SlowAccessMode (Slow Access Mode (2T Mode)) * 0 = DRAM address and control signals are driven for one - * MEMCLK cycle + * MEMCLK cycle * 1 = One additional MEMCLK of setup time is provided on all - * DRAM address and control signals except CS, CKE, and ODT; - * i.e., these signals are drivern for two MEMCLK cycles - * rather than one + * DRAM address and control signals except CS, CKE, and ODT; + * i.e., these signals are drivern for two MEMCLK cycles + * rather than one * [21:21] Reserved * [22:22] BankSwizzleMode ( Bank Swizzle Mode), - * 0 = Disabled (default) - * 1 = Enabled + * 0 = Disabled (default) + * 1 = Enabled * [23:23] Reserved * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum) * 0000 = No bypass; the oldest request is never bypassed * 0001 = The oldest request may be bypassed no more than 1 time * ... * 1111 = The oldest request may be bypassed no more than 15\ - * times + * times * [31:28] FourActWindow ( Four Bank Activate Window) , not more than * 4 banks in a 8 bank device are activated * 0000 = No tFAW window restriction @@ -576,7 +576,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable) * When set to 1, indicates that each entry in the page tables * dynamically adjusts the idle cycle limit based on page - * Conflict/Page Miss (PC/PM) traffic + * Conflict/Page Miss (PC/PM) traffic * [ 8: 6] ILD_lmt ( Idle Cycle Limit) * 000 = 0 cycles * 001 = 4 cycles @@ -597,15 +597,15 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [23:10] Reserved * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, * BIOS should set it to reduce the power consumption) - * Bit F(1207) M2 Package S1g1 Package - * 0 N/A MA1_CLK1 N/A - * 1 N/A MA0_CLK1 MA0_CLK1 - * 2 MA3_CLK N/A N/A - * 3 MA2_CLK N/A N/A - * 4 MA1_CLK MA1_CLK0 N/A - * 5 MA0_CLK MA0_CLK0 MA0_CLK0 - * 6 N/A MA1_CLK2 N/A - * 7 N/A MA0_CLK2 MA0_CLK2 + * Bit F(1207) M2 Package S1g1 Package + * 0 N/A MA1_CLK1 N/A + * 1 N/A MA0_CLK1 MA0_CLK1 + * 2 MA3_CLK N/A N/A + * 3 MA2_CLK N/A N/A + * 4 MA1_CLK MA1_CLK0 N/A + * 5 MA0_CLK MA0_CLK0 MA0_CLK0 + * 6 N/A MA1_CLK2 N/A + * 7 N/A MA0_CLK2 MA0_CLK2 */ PCI_ADDR(0, 0x18, 2, 0xa0), 0x00fffc00, 0xff000000,
@@ -624,18 +624,18 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 00011 = 160.00 ns * 00100 = 320.00 ns * 00101 = 640.00 ns - * 00110 = 1.28 us - * 00111 = 2.56 us - * 01000 = 5.12 us + * 00110 = 1.28 us + * 00111 = 2.56 us + * 01000 = 5.12 us * 01001 = 10.20 us * 01011 = 41.00 us * 01100 = 81.90 us * 01101 = 163.80 us * 01110 = 327.70 us * 01111 = 655.40 us - * 10000 = 1.31 ms - * 10001 = 2.62 ms - * 10010 = 5.24 ms + * 10000 = 1.31 ms + * 10001 = 2.62 ms + * 10010 = 5.24 ms * 10011 = 10.49 ms * 10100 = 20.97 ms * 10101 = 42.00 ms @@ -920,24 +920,24 @@ static void set_dimm_size(const struct mem_controller *ctrl, }
/* row col bank for 64 bit - 0: 13 9 2 :128M - 1: 13 10 2 :256M - 2: 14 10 2 :512M - 3: 13 11 2 :512M - 4: 13 10 3 :512M - 5: 14 10 3 :1G - 6: 14 11 2 :1G - 7: 15 10 3 :2G - 8: 14 11 3 :2G - 9: 15 11 3 :4G - 10: 16 10 3 :4G - 11: 16 11 3 :8G + 0: 13 9 2 :128M + 1: 13 10 2 :256M + 2: 14 10 2 :512M + 3: 13 11 2 :512M + 4: 13 10 3 :512M + 5: 14 10 3 :1G + 6: 14 11 2 :1G + 7: 15 10 3 :2G + 8: 14 11 3 :2G + 9: 15 11 3 :4G + 10: 16 10 3 :4G + 11: 16 11 3 :8G */
static void set_dimm_cs_map(const struct mem_controller *ctrl, - struct dimm_size *sz, unsigned index, - struct mem_info *meminfo) + struct dimm_size *sz, unsigned index, + struct mem_info *meminfo) { static const uint8_t cs_map_aaa[24] = { /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ @@ -984,7 +984,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
static long spd_set_ram_size(const struct mem_controller *ctrl, - struct mem_info *meminfo) + struct mem_info *meminfo) { int i;
@@ -1084,18 +1084,18 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, /* 35 - 27 */
static const uint8_t csbase_low_f0_shift[] = { - /* 128MB */ (14 - (13-5)), - /* 256MB */ (15 - (13-5)), - /* 512MB */ (15 - (13-5)), - /* 512MB */ (16 - (13-5)), - /* 512MB */ (16 - (13-5)), - /* 1GB */ (16 - (13-5)), - /* 1GB */ (16 - (13-5)), - /* 2GB */ (16 - (13-5)), - /* 2GB */ (17 - (13-5)), - /* 4GB */ (17 - (13-5)), - /* 4GB */ (16 - (13-5)), - /* 8GB */ (17 - (13-5)), + /* 128MB */ (14 - (13-5)), + /* 256MB */ (15 - (13-5)), + /* 512MB */ (15 - (13-5)), + /* 512MB */ (16 - (13-5)), + /* 512MB */ (16 - (13-5)), + /* 1GB */ (16 - (13-5)), + /* 1GB */ (16 - (13-5)), + /* 2GB */ (16 - (13-5)), + /* 2GB */ (17 - (13-5)), + /* 4GB */ (17 - (13-5)), + /* 4GB */ (16 - (13-5)), + /* 8GB */ (17 - (13-5)), };
/* cs_base_high is not changed */ @@ -1629,7 +1629,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor) { //input divisor could be 200(200), 150(266), 120(333), 100 (400) static const uint8_t dv_a[] = { - /* 200 266 333 400 */ + /* 200 266 333 400 */ /*4 */ 250, 250, 250, 250, /*5 */ 200, 200, 200, 100, /*6 */ 200, 166, 166, 100, @@ -2096,7 +2096,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me }
static int update_dimm_Trcd(const struct mem_controller *ctrl, - const struct mem_param *param, int i, long dimm_mask) + const struct mem_param *param, int i, long dimm_mask) { return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX); } @@ -2174,7 +2174,7 @@ static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_p
static int update_dimm_Tref(const struct mem_controller *ctrl, - const struct mem_param *param, int i, long dimm_mask) + const struct mem_param *param, int i, long dimm_mask) { uint32_t dth, dth_old; int value; @@ -2238,7 +2238,7 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, }
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, - struct mem_info *meminfo) + struct mem_info *meminfo) { int i;
@@ -2420,7 +2420,7 @@ static void set_ecc(const struct mem_controller *ctrl,
static int update_dimm_Twtr(const struct mem_controller *ctrl, - const struct mem_param *param, int i, long dimm_mask) + const struct mem_param *param, int i, long dimm_mask) { return update_dimm_TT_1_4(ctrl, param, i, dimm_mask, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX); } @@ -2534,7 +2534,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * unsigned SlowAccessMode = 0; #endif
-#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; @@ -2832,7 +2832,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, }
static void sdram_set_spd_registers(const struct mem_controller *ctrl, - struct sys_info *sysinfo) + struct sys_info *sysinfo) { struct spd_set_memclk_result result; const struct mem_param *param; @@ -2873,7 +2873,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, goto hw_spd_err;
result = spd_set_memclk(ctrl, meminfo); - param = result.param; + param = result.param; meminfo->dimm_mask = result.dimm_mask; printk_raminit("spd_set_memclk: dimm_mask=0x%x\n", meminfo->dimm_mask); if (meminfo->dimm_mask == -1) diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 4438340..58b611f 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -397,11 +397,11 @@ static void ResetDCTWrPtr(const struct mem_controller *ctrl)
static uint16_t get_exact_T1000(unsigned i) { - // 200 266, 333, 400 + // 200 266, 333, 400 static const uint16_t T1000_a[]= { 5000, 3759, 3003, 2500 };
static const uint16_t TT_a[] = { - /*200 266 333 400 */ + /*200 266 333 400 */ /*4 */ 6250, 6250, 6250, 6250, /*5 */ 5000, 5000, 5000, 2500, /*6 */ 5000, 4166, 4166, 2500, @@ -665,9 +665,9 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
if(RcvrEnDly & 1) { /* Odd steps get another pattern such that even - and odd steps alternate. - The pointers to the patterns will be swapped - at the end of the loop so they are correspond + and odd steps alternate. + The pointers to the patterns will be swapped + at the end of the loop so they are correspond */ PatternA = 1; PatternB = 0; @@ -707,7 +707,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st if(Test0 == DQS_PASS) {
Read1LTestPattern(TestAddr0B); - Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr0B);
ResetDCTWrPtr(ctrl); @@ -977,7 +977,7 @@ static void ReadL9TestPattern(unsigned addr_lo) "movl %%fs:(%%edx), %%eax\n\t" //+6 "movl %%fs:64(%%edx), %%eax\n\t" //+7
- "movl %%fs:-128(%%ebx), %%eax\n\t" //+8 + "movl %%fs:-128(%%ebx), %%eax\n\t" //+8
:: "a"(0), "b" (addr_lo+128+8*64), "c"(addr_lo+128), "d"(addr_lo+128+4*64) ); @@ -1304,12 +1304,12 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW5,CHA-B, DQ0-ODD 0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe,0xFeFeFeFe, // QW6,CHA-B, DQ0-ODD 0x01010101,0x01010101,0x01010101,0x01010101, // QW7,CHA-B, DQ0-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW0,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW1,CHA-B, DQ1-ODD 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW2,CHA-B, DQ1-ODD 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW3,CHA-B, DQ1-ODD - 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD - 0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD + 0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd,0xFdFdFdFd, // QW4,CHA-B, DQ1-ODD + 0x02020202,0x02020202,0x02020202,0x02020202, // QW5,CHA-B, DQ1-ODD 0x02020202,0x02020202,0x02020202,0x02020202, // QW6,CHA-B, DQ1-ODD 0x02020202,0x02020202,0x02020202,0x02020202, // QW7,CHA-B, DQ1-ODD 0x04040404,0x04040404,0x04040404,0x04040404, // QW0,CHA-B, DQ2-ODD @@ -2064,7 +2064,7 @@ out:
if(v) { for(ii=0;ii<4;ii++) { - print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); + print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo); } }
@@ -2079,8 +2079,8 @@ out: static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy -// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); -// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); +// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8); +// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9); sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
} diff --git a/src/northbridge/amd/amdk8/resourcemap.c b/src/northbridge/amd/amdk8/resourcemap.c index ccb3674..23746c4 100644 --- a/src/northbridge/amd/amdk8/resourcemap.c +++ b/src/northbridge/amd/amdk8/resourcemap.c @@ -196,11 +196,11 @@ static void setup_default_resource_map(void) * [ 4: 4] VGA Enable * 0 = VGA matches Disabled * 1 = matches all address < 64K and where A[9:0] is in the - * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block - * from matching agains this base/limit pair + * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i * This field defines the start of PCI I/O region n diff --git a/src/northbridge/amd/amdk8/util.c b/src/northbridge/amd/amdk8/util.c index 2e81d87..706dd18 100644 --- a/src/northbridge/amd/amdk8/util.c +++ b/src/northbridge/amd/amdk8/util.c @@ -121,9 +121,9 @@ static int r_link(u32 reg) static void showdram(int level, u8 which, u32 base, u32 lim) { printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n", - which, (((u64) base & 0xffff0000) << 8), - (((u64) lim & 0xffff0000) << 8) + 0xffffff, - r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); + which, (((u64) base & 0xffff0000) << 8), + (((u64) lim & 0xffff0000) << 8) + 0xffffff, + r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3); }
/** @@ -140,10 +140,10 @@ static void showconfig(int level, u8 which, u32 reg) { /* Don't use r_node() and r_link() here. */ printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", - which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), - BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), - re(reg), we(reg), - BITS(reg, 2, 0x1)?"dev":"bus"); + which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), + BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), + re(reg), we(reg), + BITS(reg, 2, 0x1)?"dev":"bus"); }
/** @@ -160,9 +160,9 @@ static void showconfig(int level, u8 which, u32 reg) static void showpciio(int level, u8 which, u32 base, u32 lim) { printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n", - which, BITS(base, 12, 0x3fff) << 12, - (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), - re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); + which, BITS(base, 12, 0x3fff) << 12, + (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim), + re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1)); }
/** @@ -179,11 +179,11 @@ static void showpciio(int level, u8 which, u32 base, u32 lim) static void showmmio(int level, u8 which, u32 base, u32 lim) { printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, " - "CPU disable %d, Lock %d, Non posted %d\n", - which, ((u64) BITS(base, 0, 0xffffff00)) << 8, - (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), - r_link(lim), re(base), we(base), BITS(base, 4, 0x1), - BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); + "CPU disable %d, Lock %d, Non posted %d\n", + which, ((u64) BITS(base, 0, 0xffffff00)) << 8, + (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim), + r_link(lim), re(base), we(base), BITS(base, 4, 0x1), + BITS(base, 7, 0x1), BITS(lim, 7, 0x1)); }
/** @@ -191,7 +191,7 @@ static void showmmio(int level, u8 which, u32 base, u32 lim) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showalldram(int level, device_t dev) { @@ -209,7 +209,7 @@ static void showalldram(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallmmio(int level, device_t dev) { @@ -227,7 +227,7 @@ static void showallmmio(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallpciio(int level, device_t dev) { @@ -245,7 +245,7 @@ static void showallpciio(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ static void showallconfig(int level, device_t dev) { @@ -262,7 +262,7 @@ static void showallconfig(int level, device_t dev) * * @param level The debug level. * @param dev A 32-bit number in the standard bus/dev/fn format which is used - * raw config space. + * raw config space. */ void showallroutes(int level, device_t dev) { diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 9efc1db..1ea0886 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -68,9 +68,9 @@ #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0) #define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0)) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) -#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) +#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3) +#define AMD_DR_Cx (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx) +#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3) #define AMD_DR_Dx (AMD_HY_D0 | AMD_HY_D1) #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 ) #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 ) diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h index a8f7d70..25b02e2 100644 --- a/src/northbridge/amd/amdmct/mct/mct.h +++ b/src/northbridge/amd/amdmct/mct/mct.h @@ -236,16 +236,16 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DATAload[2]; /* Number of ranks loading CH A DATA*/ /* Number of ranks loading CH B DATA*/ u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs - 1=200Mhz - 2=266Mhz - 3=333Mhz - 4=400Mhz */ + 1=200Mhz + 2=266Mhz + 3=333Mhz + 4=400Mhz */ u8 DIMMCASL; /* Min valid Mfg. CL bitfield - 0=2.0 - 1=3.0 - 2=4.0 - 3=5.0 - 4=6.0 */ + 0=2.0 + 1=3.0 + 2=4.0 + 3=5.0 + 4=6.0 */ u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/ u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/ u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/ @@ -402,81 +402,81 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /* Platform Configuration */ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0=NPT L1 + 1=NPT M2 + 2=NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200Mhz (DDR400) - 266=266Mhz (DDR533) - 333=333Mhz (DDR667) - 400=400Mhz (DDR800)*/ + 200=200Mhz (DDR400) + 266=266Mhz (DDR533) + 333=333Mhz (DDR667) + 400=400Mhz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0=Platform not capable + 1=Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0=Normal + 1=R4 (4-Rank Registered DIMMs in AMD server configuration) + 2=S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4=4 times bypass (normal for non-UMA systems) + 7=7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2=8 times (normal for non-UMA systems) + 3=16 times (normal for UMA systems)*/
/* Dram Timing */ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0=Auto, no user limit + 1=Auto, user limit provided in NV_MemCkVal + 2=Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200Mhz - 1=266Mhz - 2=333Mhz - 3=400Mhz*/ + 0=200Mhz + 1=266Mhz + 2=333Mhz + 3=400Mhz*/
/* Dram Configuration */ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0=normal + 1=enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0=Exit current node init if any DIMM has SPD checksum error + 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0=skip DQS training + 1=perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0=disable (normal) + 1=enable (4 beat burst when width is 64-bits)*/
/* Dram Power */ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0=per Channel control + 1=per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/
/* Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ + NV_BottomIO[7:0]=Addr[31:24]*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ + NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0=disable + 1=enable */
/* ECC */ #define NV_ECC 50 /* Dram ECC enable*/ @@ -487,14 +487,14 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0=disable Spare + 1=enable Spare */ /*Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ + Reserved, must be zero*/ #define NV_Parity 60 /* Parity Enable*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0=disable + 1=enable*/
/* global function */ diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 47b89b4..b12d486 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -200,23 +200,23 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * 3. Checksummed or Valid NVRAM bits * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to - * entry + * entry * 6. All var MTRRs reset to zero * 7. State of NB_CFG.DisDatMsk set properly on all CPUs * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed). * 9. All cHT links at max Speed/Width (unless DQS training is not - * installed). + * installed). * * * Global relationship between index values and item values: - * j CL(j) k F(k) + * j CL(j) k F(k) * -------------------------- - * 0 2.0 - - - * 1 3.0 1 200 Mhz - * 2 4.0 2 266 Mhz - * 3 5.0 3 333 Mhz - * 4 6.0 4 400 Mhz - * 5 7.0 5 533 Mhz + * 0 2.0 - - + * 1 3.0 1 200 Mhz + * 2 4.0 2 266 Mhz + * 3 5.0 3 333 Mhz + * 4 6.0 4 400 Mhz + * 5 7.0 5 533 Mhz */ u8 Node, NodesWmem; u32 node_sys_base; @@ -438,9 +438,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * and set conf for dimm0, hw will copy to dimm1/2/3 * set for dimm1, hw will copy to dimm3 * Rev A/B only support DIMM0/1 when 800Mhz and above - * + 0x100 to next dimm + * + 0x100 to next dimm * Rev C support DIMM0/1/2/3 when 800Mhz and above - * + 0x100 to next dimm + * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 2; DIMM++) { if (DIMM==0) { @@ -810,7 +810,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst stopDCTflag = 0; if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { print_t("\t\tDCTInit_D: StartupDCT_D\n"); - StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ + StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ } } } @@ -1055,7 +1055,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, val = ((byte >> 5) | (byte << 3)) & 0xFF; val <<= 2;
- byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ + byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */ if (byte == 4) { val >>= 4; } else if (byte == 8) { @@ -1471,7 +1471,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */ val = Get_NB32(dev, reg); - val |= 1 << 20; /* 2T CMD mode */ + val |= 1 << 20; /* 2T CMD mode */ Set_NB32(dev, reg, val); }
@@ -3745,13 +3745,13 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * subsequent update to be invalid during any MemClk frequency change: * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the - * following sequence : + * following sequence : * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change * d) Enable Compensation (F2[1, 0]9C_x08[30] ) * 2. A software-initiated Disable Compensation should always be - * followed by step b) of the above steps. + * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 * * Errata#177: DRAM Phy Automatic Compensation Updates May Be Invalid @@ -3759,7 +3759,7 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * to initiating a memory clock frequency change as follows: * 1. Disable PhyAutoComp by writing 1'b1 to F2x[1, 0]9C_x08[30] * 2. Reset the Begin Compensation bits by writing 32'h0 to - * F2x[1, 0]9C_x4D004F00 + * F2x[1, 0]9C_x4D004F00 * 3. Perform frequency change * 4. Enable PhyAutoComp by writing 1'b0 to F2x[1, 0]9C_08[30] * In addition, any time software disables the automatic phy @@ -3802,9 +3802,9 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, /* Errata 178 * * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations - * In TX FIFO + * In TX FIFO * Solution: BIOS should program DRAM Control Register[RdPtrInit] = - * 5h, (F2x[1, 0]78[3:0] = 5h). + * 5h, (F2x[1, 0]78[3:0] = 5h). * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 4370b8d..1dc200d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -257,7 +257,7 @@ struct MCTStatStruc { u32 GStatus; /* Global Status bitfield*/ u32 HoleBase; /* If not zero, BASE[39:8] (system address) - of sub 4GB dram hole for HW remapping.*/ + of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ }; @@ -568,81 +568,81 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0=NPT L1 + 1=NPT M2 + 2=NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200Mhz (DDR400) - 266=266Mhz (DDR533) - 333=333Mhz (DDR667) - 400=400Mhz (DDR800)*/ + 200=200Mhz (DDR400) + 266=266Mhz (DDR533) + 333=333Mhz (DDR667) + 400=400Mhz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0=Platform not capable + 1=Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0=Normal + 1=R4 (4-Rank Registered DIMMs in AMD server configuration) + 2=S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4=4 times bypass (normal for non-UMA systems) + 7=7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2=8 times (normal for non-UMA systems) + 3=16 times (normal for UMA systems)*/
/*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0=Auto, no user limit + 1=Auto, user limit provided in NV_MemCkVal + 2=Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200Mhz - 1=266Mhz - 2=333Mhz - 3=400Mhz*/ + 0=200Mhz + 1=266Mhz + 2=333Mhz + 3=400Mhz*/
/*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0=normal + 1=enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0=Exit current node init if any DIMM has SPD checksum error + 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0=skip DQS training + 1=perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0=disable (normal) + 1=enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0=per Channel control + 1=per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/
/*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ + NV_BottomIO[7:0]=Addr[31:24]*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ + NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0=disable + 1=enable */
/*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -653,13 +653,13 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0=disable Spare + 1=enable Spare */ /* Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ + Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c index 9bc30fe..e08c24d 100644 --- a/src/northbridge/amd/amdmct/mct/mctardk3.c +++ b/src/northbridge/amd/amdmct/mct/mctardk3.c @@ -127,8 +127,8 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, *=============================================================================== * #1, BYTE, Speed (DCTStatstruc.Speed) (Secondary Key) * #2, BYTE, number of Address bus loads on the Channel. (Tershery Key) - * These must be listed in ascending order. - * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. + * These must be listed in ascending order. + * FFh (0xFE) has special meaning of 'any', and must be listed first for each speed grade. * #3, DWORD, Address Timing Control Register Value * #4, DWORD, Output Driver Compensation Control Register Value * #5, BYTE, Number of DIMMs (Primary Key) diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c index feb4170..433c575 100644 --- a/src/northbridge/amd/amdmct/mct/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct/mctsrc.c @@ -74,7 +74,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, { /* * 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary + * aligning on 16 byte boundary * 2. Set the ptr to DCTStatstruc.PtrPatternBufA for Alpha * 3. Set the ptr to DCTStatstruc.PtrPatternBufB for Beta */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7db13d2..b45d2f6 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -187,25 +187,25 @@ static const u8 Table_DQSRcvEn_Offset[] = {0x00,0x01,0x10,0x11,0x2};
Example: BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: - Bit AM3/S1g3 pin name - 0 M[B,A]_CLK_H/L[0] - 1 M[B,A]_CLK_H/L[1] - 2 M[B,A]_CLK_H/L[2] - 3 M[B,A]_CLK_H/L[3] - 4 M[B,A]_CLK_H/L[4] - 5 M[B,A]_CLK_H/L[5] - 6 M[B,A]_CLK_H/L[6] - 7 M[B,A]_CLK_H/L[7] + Bit AM3/S1g3 pin name + 0 M[B,A]_CLK_H/L[0] + 1 M[B,A]_CLK_H/L[1] + 2 M[B,A]_CLK_H/L[2] + 3 M[B,A]_CLK_H/L[3] + 4 M[B,A]_CLK_H/L[4] + 5 M[B,A]_CLK_H/L[5] + 6 M[B,A]_CLK_H/L[6] + 7 M[B,A]_CLK_H/L[7]
And platform has the following routing: - CS0 M[B,A]_CLK_H/L[4] - CS1 M[B,A]_CLK_H/L[2] - CS2 M[B,A]_CLK_H/L[3] - CS3 M[B,A]_CLK_H/L[5] + CS0 M[B,A]_CLK_H/L[4] + CS1 M[B,A]_CLK_H/L[2] + CS2 M[B,A]_CLK_H/L[3] + CS3 M[B,A]_CLK_H/L[5]
Then: - ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 - MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b + ; CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 + MEMCLK_MAPPING EQU 00010000b, 00000100b, 00001000b, 00100000b, 00000000b, 00000000b, 00000000b, 00000000b */
/* Note: If you are not sure about the pin mappings at initial stage, we dont have to disable MemClk. @@ -255,16 +255,16 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, * Global relationship between index values and item values: * * pDCTstat.CASL pDCTstat.Speed - * j CL(j) k F(k) + * j CL(j) k F(k) * -------------------------- - * 0 2.0 - - - * 1 3.0 1 200 Mhz - * 2 4.0 2 266 Mhz - * 3 5.0 3 333 Mhz - * 4 6.0 4 400 Mhz - * 5 7.0 5 533 Mhz - * 6 8.0 6 667 Mhz - * 7 9.0 7 800 Mhz + * 0 2.0 - - + * 1 3.0 1 200 Mhz + * 2 4.0 2 266 Mhz + * 3 5.0 3 333 Mhz + * 4 6.0 4 400 Mhz + * 5 7.0 5 533 Mhz + * 6 8.0 6 667 Mhz + * 7 9.0 7 800 Mhz */ u8 Node, NodesWmem; u32 node_sys_base; @@ -488,9 +488,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, * and set conf for dimm0, hw will copy to dimm1/2/3 * set for dimm1, hw will copy to dimm3 * Rev A/B only support DIMM0/1 when 800Mhz and above - * + 0x100 to next dimm + * + 0x100 to next dimm * Rev C support DIMM0/1/2/3 when 800Mhz and above - * + 0x100 to next dimm + * + 0x100 to next dimm */ for (DIMM = 0; DIMM < 4; DIMM++) { if (DIMM == 0) { @@ -810,7 +810,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst stopDCTflag = 0; if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { printk(BIOS_DEBUG, "\t\tDCTInit_D: StartupDCT_D\n"); - StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ + StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ } } } @@ -1507,7 +1507,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */ val = Get_NB32(dev, reg); - val |= 1 << 20; /* 2T CMD mode */ + val |= 1 << 20; /* 2T CMD mode */ Set_NB32(dev, reg, val); }
@@ -2145,7 +2145,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, /* byte = mctRead_SPD(smbaddr, SPD_RefRawCard); */ /* Get Byte65/66 for register manufacture ID code */ if ((0x97 == mctRead_SPD(smbaddr, SPD_RegManufactureID_H)) && - (0x80 == mctRead_SPD(smbaddr, SPD_RegManufactureID_L))) { + (0x80 == mctRead_SPD(smbaddr, SPD_RegManufactureID_L))) { if (0x16 == mctRead_SPD(smbaddr, SPD_RegManRevID)) pDCTstat->RegMan2Present |= 1 << i; else @@ -2906,7 +2906,7 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat, }
static void mct_PhyController_Config(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 dct) + struct DCTStatStruc *pDCTstat, u8 dct) { u32 index_reg = 0x98 + 0x100 * dct; u32 dev = pDCTstat->dev_dct; @@ -3566,13 +3566,13 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * subsequent update to be invalid during any MemClk frequency change: * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the - * following sequence : + * following sequence : * - a) Disable Compensation (F2[1, 0]9C_x08[30] ) * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines * c) Do frequency change * d) Enable Compensation (F2[1, 0]9C_x08[30] ) * 2. A software-initiated Disable Compensation should always be - * followed by step b) of the above steps. + * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 * * Errata#177: DRAM Phy Automatic Compensation Updates May Be Invalid @@ -3580,7 +3580,7 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct, * to initiating a memory clock frequency change as follows: * 1. Disable PhyAutoComp by writing 1'b1 to F2x[1, 0]9C_x08[30] * 2. Reset the Begin Compensation bits by writing 32'h0 to - * F2x[1, 0]9C_x4D004F00 + * F2x[1, 0]9C_x4D004F00 * 3. Perform frequency change * 4. Enable PhyAutoComp by writing 1'b0 to F2x[1, 0]9C_08[30] * In addition, any time software disables the automatic phy @@ -3613,9 +3613,9 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat, /* Errata 178 * * Bug#15115: Uncertainty In The Sync Chain Leads To Setup Violations - * In TX FIFO + * In TX FIFO * Solution: BIOS should program DRAM Control Register[RdPtrInit] = - * 5h, (F2x[1, 0]78[3:0] = 5h). + * 5h, (F2x[1, 0]78[3:0] = 5h). * Silicon Status: Fixed In Rev B0 * * Bug#15880: Determine validity of reset settings for DDR PHY timing. diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index d2872e4..e72e5e2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -118,7 +118,7 @@ #define TestFail 2 /* func 2, offset 40h-5C, bit 2*/ #define DqsRcvEnTrain 18 /* func 2, offset 78h, bit 18*/ #define EnDramInit 31 /* func 2, offset 7Ch, bit 31*/ -#define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */ +#define PchgPDModeSel 23 /* func 2, offset 84h, bit 23 */ #define DisAutoRefresh 18 /* func 2, offset 8Ch, bit 18*/ #define InitDram 0 /* func 2, offset 90h, bit 0*/ #define BurstLength32 10 /* func 2, offset 90h, bit 10*/ @@ -129,7 +129,7 @@ #define MemClkFreqVal 3 /* func 2, offset 94h, bit 3*/ #define RDqsEn 12 /* func 2, offset 94h, bit 12*/ #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/ -#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ +#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/ #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/ #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/ #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/ @@ -177,7 +177,7 @@ #define Ddr3FourSocketCh 2 /* func 2, offset A8h, bit 2 */ #define SendControlWord 30 /* func 2, offset 7Ch, bit 30 */
-#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */ +#define NB_GfxNbPstateDis 62 /* MSRC001_001F Northbridge Configuration Register (NB_CFG) bit 62 GfxNbPstateDis disable northbridge p-state transitions */ /*============================================================================= SW Initialization ============================================================================*/ @@ -284,7 +284,7 @@ struct MCTStatStruc { u32 GStatus; /* Global Status bitfield*/ u32 HoleBase; /* If not zero, BASE[39:8] (system address) - of sub 4GB dram hole for HW remapping.*/ + of sub 4GB dram hole for HW remapping.*/ u32 Sub4GCacheTop; /* If not zero, the 32-bit top of cacheable memory.*/ u32 SysLimit; /* LIMIT[39:8] (system address)*/ }; @@ -629,81 +629,81 @@ struct DCTStatStruc { /* A per Node structure*/ ===============================================================================*/ /*Platform Configuration*/ #define NV_PACK_TYPE 0 /* CPU Package Type (2-bits) - 0=NPT L1 - 1=NPT M2 - 2=NPT S1*/ + 0=NPT L1 + 1=NPT M2 + 2=NPT S1*/ #define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/ #define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/ #define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits) - 200=200Mhz (DDR400) - 266=266Mhz (DDR533) - 333=333Mhz (DDR667) - 400=400Mhz (DDR800)*/ + 200=200Mhz (DDR400) + 266=266Mhz (DDR533) + 333=333Mhz (DDR667) + 400=400Mhz (DDR800)*/ #define NV_ECC_CAP 4 /* Bus ECC capable (1-bits) - 0=Platform not capable - 1=Platform is capable*/ + 0=Platform not capable + 1=Platform is capable*/ #define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits) - 0=Normal - 1=R4 (4-Rank Registered DIMMs in AMD server configuration) - 2=S4 (Unbuffered SO-DIMMs)*/ + 0=Normal + 1=R4 (4-Rank Registered DIMMs in AMD server configuration) + 2=S4 (Unbuffered SO-DIMMs)*/ #define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition). - 4=4 times bypass (normal for non-UMA systems) - 7=7 times bypass (normal for UMA systems)*/ + 4=4 times bypass (normal for non-UMA systems) + 7=7 times bypass (normal for UMA systems)*/ #define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition). - 2=8 times (normal for non-UMA systems) - 3=16 times (normal for UMA systems)*/ + 2=8 times (normal for non-UMA systems) + 3=16 times (normal for UMA systems)*/
/*Dram Timing*/ #define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits) - 0=Auto, no user limit - 1=Auto, user limit provided in NV_MemCkVal - 2=Manual, user value provided in NV_MemCkVal*/ + 0=Auto, no user limit + 1=Auto, user limit provided in NV_MemCkVal + 2=Manual, user value provided in NV_MemCkVal*/ #define NV_MemCkVal 11 /* Memory Clock Value (2-bits) - 0=200Mhz - 1=266Mhz - 2=333Mhz - 3=400Mhz*/ + 0=200Mhz + 1=266Mhz + 2=333Mhz + 3=400Mhz*/
/*Dram Configuration*/ #define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits) - 0=normal - 1=enable all memclocks*/ + 0=normal + 1=enable all memclocks*/ #define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits) - 0=Exit current node init if any DIMM has SPD checksum error - 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ + 0=Exit current node init if any DIMM has SPD checksum error + 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/ #define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control - 0=skip DQS training - 1=perform DQS training*/ + 0=skip DQS training + 1=perform DQS training*/ #define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits) - 0=disable (normal) - 1=enable (4 beat burst when width is 64-bits)*/ + 0=disable (normal) + 1=enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/ #define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_CKE_CTL 31 /* CKE based power down control (1-bits) - 0=per Channel control - 1=per Chip select control*/ + 0=per Channel control + 1=per Chip select control*/ #define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits) - 0=disable - 1=enable*/ + 0=disable + 1=enable*/
/*Memory Map/Mgt.*/ #define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits) - NV_BottomIO[7:0]=Addr[31:24]*/ + NV_BottomIO[7:0]=Addr[31:24]*/ #define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits) - NV_BottomUMA[7:0]=Addr[31:24]*/ + NV_BottomUMA[7:0]=Addr[31:24]*/ #define NV_MemHole 42 /* Memory Hole Remapping (1-bits) - 0=disable - 1=enable */ + 0=disable + 1=enable */
/*ECC*/ #define NV_ECC 50 /* Dram ECC enable*/ @@ -714,13 +714,13 @@ struct DCTStatStruc { /* A per Node structure*/ #define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/ #define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/ #define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0: - 0=disable Spare - 1=enable Spare */ + 0=disable Spare + 1=enable Spare */ /* Chip Select Spare Control bit 1-4: - Reserved, must be zero*/ + Reserved, must be zero*/ #define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control - 0=disable - 1=enable*/ + 0=disable + 1=enable*/ #define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c index 7a56e91..65f1c9e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c @@ -39,11 +39,11 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
/* * In: MAAdimms - number of DIMMs on the channel - * : Speed - Speed (see DCTStatstruc.Speed for definition) - * : MAAload - number of address bus loads on the channel + * : Speed - Speed (see DCTStatstruc.Speed for definition) + * : MAAload - number of address bus loads on the channel * Out: AddrTmgCTL - Address Timing Control Register Value - * : ODC_CTL - Output Driver Compensation Control Register Value - * : CMDmode - CMD mode + * : ODC_CTL - Output Driver Compensation Control Register Value + * : CMDmode - CMD mode */ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c index 4dbec26..3bc691f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c @@ -35,9 +35,9 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
if (pDCTstat->GangedMode == 1 && dct == 0) Get_ChannelPS_Cfg0_D(pDCTstat->MAdimms[1], pDCTstat->Speed, - pDCTstat->MAload[1], pDCTstat->DATAload[1], - &(pDCTstat->CH_ADDR_TMG[1]), &(pDCTstat->CH_ODC_CTL[1]), - &pDCTstat->_2Tmode); + pDCTstat->MAload[1], pDCTstat->DATAload[1], + &(pDCTstat->CH_ADDR_TMG[1]), &(pDCTstat->CH_ODC_CTL[1]), + &pDCTstat->_2Tmode);
pDCTstat->CH_EccDQSLike[0] = 0x0302; pDCTstat->CH_EccDQSLike[1] = 0x0302; @@ -46,12 +46,12 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
/* * In: MAAdimms - number of DIMMs on the channel - * : Speed - Speed (see DCTStatstruc.Speed for definition) - * : MAAload - number of address bus loads on the channel + * : Speed - Speed (see DCTStatstruc.Speed for definition) + * : MAAload - number of address bus loads on the channel * : DATAAload - number of ranks on the channel * Out: AddrTmgCTL - Address Timing Control Register Value - * : ODC_CTL - Output Driver Compensation Control Register Value - * : CMDmode - CMD mode + * : ODC_CTL - Output Driver Compensation Control Register Value + * : CMDmode - CMD mode */ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 76d01da..6439ff7 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -67,7 +67,7 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
static void StoreWrRdDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel, - u8 RnkDlyFilterMin, u8 RnkDlyFilterMax); + u8 RnkDlyFilterMin, u8 RnkDlyFilterMax);
static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 6189608..7852747 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -73,7 +73,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat, { /* * 1. Copy the alpha and Beta patterns from ROM to Cache, - * aligning on 16 byte boundary + * aligning on 16 byte boundary * 2. Set the ptr to DCTStatstruc.PtrPatternBufA for Alpha * 3. Set the ptr to DCTStatstruc.PtrPatternBufB for Beta */ @@ -432,7 +432,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n"); for(Channel = 0; Channel<2; Channel++) { printk(BIOS_DEBUG, "Channel:%x: %x\n", - Channel, pDCTstat->CH_MaxRdLat[Channel]); + Channel, pDCTstat->CH_MaxRdLat[Channel]); } } #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index aba558f..0211443 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -45,20 +45,20 @@ void getWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm);
/*----------------------------------------------------------------------------- * void AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, - * u8 Dimm, u8 Pass) + * u8 Dimm, u8 Pass) * * Description: - * This function initialized Hardware based write levelization phase 1 + * This function initialized Hardware based write levelization phase 1 * * Parameters: - * IN OUT *SPDData - Pointer to buffer with information about each DIMMs - * SPD information - * *MCTData - Pointer to buffer with runtime parameters, - * *DCTData - Pointer to buffer with information about each DCT + * IN OUT *SPDData - Pointer to buffer with information about each DIMMs + * SPD information + * *MCTData - Pointer to buffer with runtime parameters, + * *DCTData - Pointer to buffer with information about each DCT * - * IN DIMM - Logical DIMM number - * Pass - First or Second Pass - * OUT + * IN DIMM - Logical DIMM number + * Pass - First or Second Pass + * OUT *----------------------------------------------------------------------------- */ void AgesaHwWlPhase1(sMCTStruct *pMCTData, sDCTStruct *pDCTData, @@ -203,12 +203,12 @@ u32 swapAddrBits_wl(sDCTStruct *pDCTData, u32 MRSValue) * u32 swapBankBits(sDCTStruct *pDCTData, u32 MRSValue) * * Description: - * This function swaps the bits in MSR register value + * This function swaps the bits in MSR register value * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN u32: MRS value - * OUT u32: Swapped BANK BITS + * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN u32: MRS value + * OUT u32: Swapped BANK BITS * * ---------------------------------------------------------------------------- */ @@ -239,18 +239,18 @@ u32 swapBankBits(sDCTStruct *pDCTData, u32 MRSValue) * void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *DCTData, u8 Dimm, BOOL WL) * * Description: - * This function prepares DIMMS for training + * This function prepares DIMMS for training * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN OUT *DCTData - Pointer to buffer with information about each DCT * *SPDData - Pointer to buffer with information about each DIMMs - * SPD information + * SPD information * *MCTData - Pointer to buffer with runtime parameters, - * IN Dimm - Logical DIMM number + * IN Dimm - Logical DIMM number * WL - indicates if the routine is used for Write levelization - * training + * training * - * OUT + * OUT * * ---------------------------------------------------------------------------- */ @@ -581,7 +581,7 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl) set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, MrsAddressStart, MrsAddressEnd, tempW); /* Program F2x[1, 0]7C[SendMrsCmd]=1 to initiate the command to - the specified DIMM.*/ + the specified DIMM.*/ set_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, FUN_DCT, DRAM_INIT, SendMrsCmd, SendMrsCmd, 1); /* Wait for F2x[1, 0]7C[SendMrsCmd] to be cleared by hardware. */ @@ -601,12 +601,12 @@ void prepareDimms(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl) * void programODT(sMCTStruct *pMCTData, DCTStruct *DCTData, u8 dimm) * * Description: - * This function programs the ODT values for the NB + * This function programs the ODT values for the NB * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN - * OUT + * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN + * OUT * ---------------------------------------------------------------------------- */ void programODT(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) @@ -634,14 +634,14 @@ void programODT(sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) * void procConifg(MCTStruct *MCTData,DCTStruct *DCTData, u8 Dimm, u8 Pass) * * Description: - * This function programs the ODT values for the NB + * This function programs the ODT values for the NB * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN OUT *DCTData - Pointer to buffer with information about each DCT * *MCTData - Pointer to buffer with runtime parameters, - * IN Dimm - Logical DIMM + * IN Dimm - Logical DIMM * Pass - First of Second Pass - * OUT + * OUT * ---------------------------------------------------------------------------- */ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass) @@ -732,7 +732,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass) while(ByteLane < MAX_BYTE_LANES) { MemClkFreq = get_Bits(pDCTData, pDCTData->CurrDct, pDCTData->NodeId, - FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); + FUN_DCT, DRAM_CONFIG_HIGH, 0, 2); if (pDCTData->Status[DCT_STATUS_REGISTERED]) RegisterDelay = 0x20; /* TODO: ((RCW2 & BIT0) == 0) ? 0x20 : 0x30; */ else @@ -743,7 +743,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass) training) - RegisterDelay. */ /* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz; 6: 800Mhz */ SeedTotal = (u16) (RegisterDelay + ((((u32) SeedTotal - RegisterDelay) * - freq_tab[MemClkFreq-3]) / 400)); + freq_tab[MemClkFreq-3]) / 400)); Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2; Seed_Fine = SeedTotal & 0x1F; pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; @@ -759,12 +759,12 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass) * void setWLByteDelay(DCTStruct *DCTData, u8 ByteLane, u8 Dimm){ * * Description: - * This function writes the write levelization byte delay for the Phase - * Recovery control registers + * This function writes the write levelization byte delay for the Phase + * Recovery control registers * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN Dimm - Dimm Number + * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN Dimm - Dimm Number * DCTData->WLGrossDelay[index+ByteLane] - gross write delay for each * logical DIMM * DCTData->WLFineDelay[index+ByteLane] - fine write delay for each @@ -772,7 +772,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass) * ByteLane - target byte lane to write * targetAddr - 0: write to DRAM phase recovery control register * 1: write to DQS write register - * OUT + * OUT * *----------------------------------------------------------------------------- */ @@ -800,8 +800,8 @@ void setWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm, u8 targetAddr) } grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; /* Adjust seed gross delay overflow (greater than 3): - * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). - * - Keep original seed gross delay for later reference. + * - Program seed gross delay as 2 (gross is 4 or 6) or 1 (gross is 5). + * - Keep original seed gross delay for later reference. */ if(grossDelayValue >= 3) { @@ -875,14 +875,14 @@ void setWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm, u8 targetAddr) * void getWLByteDelay(DCTStruct *DCTData, u8 ByteLane, u8 Dimm) * * Description: - * This function reads the write levelization byte delay from the Phase - * Recovery control registers + * This function reads the write levelization byte delay from the Phase + * Recovery control registers * * Parameters: - * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN Dimm - Dimm Number + * IN OUT *DCTData - Pointer to buffer with information about each DCT + * IN Dimm - Dimm Number * ByteLane - target byte lane to read - * OUT + * OUT * DCTData->WLGrossDelay[index+ByteLane] - gross write delay for current * byte for logical DIMM * DCTData->WLFineDelay[index+ByteLane] - fine write delay for current diff --git a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c index 42696f6..ed541a5 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c @@ -21,19 +21,19 @@
/* *----------------------------------------------------------------------------- - * MODULES USED + * MODULES USED * *----------------------------------------------------------------------------- */ /*---------------------------------------------------------------------------- - * PROTOTYPES OF LOCAL FUNCTIONS + * PROTOTYPES OF LOCAL FUNCTIONS * *---------------------------------------------------------------------------- */
/* *----------------------------------------------------------------------------- - * EXPORTED FUNCTIONS + * EXPORTED FUNCTIONS * *----------------------------------------------------------------------------- */ @@ -44,11 +44,11 @@ * This function set Rtt_Nom for registered DDR3 dimms on targeted dimm. * * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * dimm - targeted dimm + * wl - current mode, either write levelization mode or normal mode + * MemClkFreq - current frequency * - * @return tempW1 - Rtt_Nom + * @return tempW1 - Rtt_Nom */ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { @@ -155,11 +155,11 @@ static u32 RttNomTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 d * This function set Rtt_Nom for registered DDR3 dimms on non-targeted dimm. * * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - non-targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * dimm - non-targeted dimm + * wl - current mode, either write levelization mode or normal mode + * MemClkFreq - current frequency * - * @return tempW1 - Rtt_Nom + * @return tempW1 - Rtt_Nom */ static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { @@ -177,11 +177,11 @@ static u32 RttNomNonTargetRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u * This function set Rtt_Wr for registered DDR3 dimms. * * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm - * wl - current mode, either write levelization mode or normal mode - * MemClkFreq - current frequency + * dimm - targeted dimm + * wl - current mode, either write levelization mode or normal mode + * MemClkFreq - current frequency * - * @return tempW1 - Rtt_Wr + * @return tempW1 - Rtt_Wr */ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BOOL wl, u8 MemClkFreq, u8 rank) { @@ -239,9 +239,9 @@ static u32 RttWrRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm, BO * This function set WrLvOdt for registered DDR3 dimms. * * @param[in] *pDCTData - Pointer to buffer with information about each DCT - * dimm - targeted dimm + * dimm - targeted dimm * - * @return WrLvOdt + * @return WrLvOdt */ static u8 WrLvOdtRegDimm (sMCTStruct *pMCTData, sDCTStruct *pDCTData, u8 dimm) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c index d2c118c..fe5f8b8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c @@ -70,9 +70,9 @@ static void AmdMemPCIWriteBits(SBDFO loc, u8 highbit, u8 lowbit, u32 *pValue) * This routine sets a bit in a u32 * * Parameters: - * IN csMask = Target value in which the bit will be set - * IN tempD = Bit that will be set - * OUT value = Target value with the bit set + * IN csMask = Target value in which the bit will be set + * IN tempD = Bit that will be set + * OUT value = Target value with the bit set *----------------------------------------------------------------------------- */ static u32 bitTestSet(u32 csMask,u32 tempD) @@ -91,9 +91,9 @@ static u32 bitTestSet(u32 csMask,u32 tempD) * This routine re-sets a bit in a u32 * * Parameters: - * IN csMask = Target value in which the bit will be re-set - * IN tempD = Bit that will be re-set - * OUT value = Target value with the bit re-set + * IN csMask = Target value in which the bit will be re-set + * IN tempD = Bit that will be re-set + * OUT value = Target value with the bit re-set *----------------------------------------------------------------------------- */ static u32 bitTestReset(u32 csMask,u32 tempD) @@ -109,24 +109,24 @@ static u32 bitTestReset(u32 csMask,u32 tempD)
/*----------------------------------------------------------------------------- * u32 get_Bits(DCTStruct *DCTData, u8 DCT, u8 Node, u8 func, u16 offset, - * u8 low, u8 high) + * u8 low, u8 high) * * Description: * This routine Gets the PCT bits from the specified Node, DCT and PCI address * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field + * IN DCT - DCT number + * - 1 indicates DCT 1 + * - 0 indicates DCT 0 + * - 2 both DCTs + * Node - Node number + * Func - PCI Function number + * Offset - PCI register number + * Low - Low bit of the bit field + * High - High bit of the bit field * - * OUT value = Value read from PCI space + * OUT value = Value read from PCI space *----------------------------------------------------------------------------- */ static u32 get_Bits(sDCTStruct *pDCTData, @@ -159,22 +159,22 @@ static u32 get_Bits(sDCTStruct *pDCTData,
/*----------------------------------------------------------------------------- * void set_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, u16 offset, - * u8 low, u8 high, u32 value) + * u8 low, u8 high, u32 value) * * Description: * This routine Sets the PCT bits from the specified Node, DCT and PCI address * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field + * IN DCT - DCT number + * - 1 indicates DCT 1 + * - 0 indicates DCT 0 + * - 2 both DCTs + * Node - Node number + * Func - PCI Function number + * Offset - PCI register number + * Low - Low bit of the bit field + * High - High bit of the bit field * * OUT *----------------------------------------------------------------------------- @@ -209,7 +209,7 @@ static void set_Bits(sDCTStruct *pDCTData,
/*------------------------------------------------- * u32 get_ADD_DCT_Bits(DCTStruct *DCTData,u8 DCT,u8 Node,u8 func, - * u16 offset,u8 low, u8 high) + * u16 offset,u8 low, u8 high) * * Description: * This routine gets the Additional PCT register from Function 2 by specified @@ -217,15 +217,15 @@ static void set_Bits(sDCTStruct *pDCTData, * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - Additional PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field + * IN DCT - DCT number + * - 1 indicates DCT 1 + * - 0 indicates DCT 0 + * - 2 both DCTs + * Node - Node number + * Func - PCI Function number + * Offset - Additional PCI register number + * Low - Low bit of the bit field + * High - High bit of the bit field * * OUT *------------------------------------------------- @@ -247,7 +247,7 @@ static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData,
/*------------------------------------------------- * void set_DCT_ADDR_Bits(DCTStruct *DCTData, u8 DCT,u8 Node,u8 func, - * u16 offset,u8 low, u8 high, u32 value) + * u16 offset,u8 low, u8 high, u32 value) * * Description: * This routine sets the Additional PCT register from Function 2 by specified @@ -255,15 +255,15 @@ static u32 get_ADD_DCT_Bits(sDCTStruct *pDCTData, * * Parameters: * IN OUT *DCTData - Pointer to buffer with information about each DCT - * IN DCT - DCT number - * - 1 indicates DCT 1 - * - 0 indicates DCT 0 - * - 2 both DCTs - * Node - Node number - * Func - PCI Function number - * Offset - Additional PCI register number - * Low - Low bit of the bit field - * High - High bit of the bit field + * IN DCT - DCT number + * - 1 indicates DCT 1 + * - 0 indicates DCT 0 + * - 2 both DCTs + * Node - Node number + * Func - PCI Function number + * Offset - Additional PCI register number + * Low - Low bit of the bit field + * High - High bit of the bit field * * OUT *------------------------------------------------- @@ -297,10 +297,10 @@ static void set_DCT_ADDR_Bits(sDCTStruct *pDCTData, * This routine tests the value to determine if the bitLoc is set * * Parameters: - * IN Value - value to be tested - * bitLoc - bit location to be tested + * IN Value - value to be tested + * bitLoc - bit location to be tested * OUT TRUE - bit is set - * FALSE - bit is clear + * FALSE - bit is clear *------------------------------------------------- */ static BOOL bitTest(u32 value, u8 bitLoc) diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 100f932..630c35f 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -37,7 +37,7 @@ COMMENT OUT ALL BUT 1 COMMENT OUT ALL BUT 1 ----------------------------------------------------------------------------*/ #ifndef SYSTEM_TYPE -#define SYSTEM_TYPE SERVER +#define SYSTEM_TYPE SERVER //#define SYSTEM_TYPE DESKTOP //#define SYSTEM_TYPE MOBILE #endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2..5ea2d4b 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -216,12 +216,12 @@ static u16 mctGet_NVbits(u8 index) break; case NV_ChannelIntlv: val = 5; /* Not currently checked in mctchi_d.c */ - /* Bit 0 = 0 - Disable - * 1 - Enable + /* Bit 0 = 0 - Disable + * 1 - Enable * Bits[2:1] = 00b - Address bits 6 - * 01b - Address bits 1 - * 10b - Hash*, XOR of address bits [20:16, 6] - * 11b - Hash*, XOR of address bits [20:16, 9] + * 01b - Address bits 1 + * 10b - Hash*, XOR of address bits [20:16, 6] + * 11b - Hash*, XOR of address bits [20:16, 9] */ break; } @@ -352,25 +352,25 @@ static void coreDelay(u32 microseconds)
cycles = (microseconds * 100) << 3; /* x8 (number of 1.25ns ticks) */
- if (!(rdmsr(HWCR).lo & TSC_FREQ_SEL_MASK)) { - msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); - if (!(rdmsr(0xC0010064+pstate_msr.lo).lo & NB_DID_M_ON)) { + if (!(rdmsr(HWCR).lo & TSC_FREQ_SEL_MASK)) { + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + if (!(rdmsr(0xC0010064+pstate_msr.lo).lo & NB_DID_M_ON)) { cycles = cycles <<1; // half freq, double cycles } } // else should we keep p0 freq at the time of setting TSC_FREQ_SEL_MASK somewhere and check it here ?
now = rdmsr(TSC_MSR); - // avoid overflow when called near 2^32 ticks ~ 5.3 s boundaries + // avoid overflow when called near 2^32 ticks ~ 5.3 s boundaries if (0xffffffff - cycles >= now.lo ) { end.hi = now.hi; - end.lo = now.lo + cycles; + end.lo = now.lo + cycles; } else { - end.hi = now.hi +1; // - end.lo = cycles - (1+(0xffffffff - now.lo)); + end.hi = now.hi +1; // + end.lo = cycles - (1+(0xffffffff - now.lo)); } do { - now = rdmsr(TSC_MSR); - } while ((now.hi < end.hi) || ((now.hi == end.hi) && (now.lo < end.lo))); + now = rdmsr(TSC_MSR); + } while ((now.hi < end.hi) || ((now.hi == end.hi) && (now.lo < end.lo))); }
/* Erratum 350 */ @@ -404,16 +404,16 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */ u32DctDev = pDCTstat->dev_dct; Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000); - /* ^--- value - ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG. - ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ + /* ^--- value + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG. + ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
if(!pDCTstat->GangedMode) { print_t("vErrata350: step 2b\n"); Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000); - /* ^--- value - ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG - ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ + /* ^--- value + ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG + ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ }
print_t("vErrata350: step 3\n"); @@ -437,17 +437,17 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs
static void vErratum372(struct DCTStatStruc *pDCTstat) { - msr_t msr = rdmsr(NB_CFG_MSR); + msr_t msr = rdmsr(NB_CFG_MSR);
- int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ; + int nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ;
- // is this the right way to check for NB pstate 1 or DDR3-1333 ? - if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) - &&(!pDCTstat->GangedMode)) { - /* DisableCf8ExtCfg */ - msr.hi &= ~(3 << (51 - 32)); - wrmsr(NB_CFG_MSR, msr); - } + // is this the right way to check for NB pstate 1 or DDR3-1333 ? + if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported)) + &&(!pDCTstat->GangedMode)) { + /* DisableCf8ExtCfg */ + msr.hi &= ~(3 << (51 - 32)); + wrmsr(NB_CFG_MSR, msr); + } }
static void vErratum414(struct DCTStatStruc *pDCTstat) @@ -455,11 +455,11 @@ static void vErratum414(struct DCTStatStruc *pDCTstat) int dct=0; for(; dct < 2 ; dct++) { - int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); - int powerDown = dRAMConfigHi && (1 << PowerDownEn ) ; - int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ; - int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); - int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ; + int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); + int powerDown = dRAMConfigHi && (1 << PowerDownEn ) ; + int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ; + int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct)); + int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ; if (powerDown && ddr3 && pchgPDModeSel ) { Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) ); diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig index 9642416..04e9950 100644 --- a/src/northbridge/amd/cimx/rd890/Kconfig +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -31,6 +31,6 @@ config REDIRECT_NBCIMX_TRACE_TO_SERIAL This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console.
- Warning: Only enable this option when debuging or tracing AMD CIMX code. + Warning: Only enable this option when debuging or tracing AMD CIMX code.
endif # NORTHBRIDGE_AMD_CIMX_RD890 diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h index 29b5d64..fd259f1 100644 --- a/src/northbridge/amd/cimx/rd890/NbPlatform.h +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -63,7 +63,7 @@ #endif
/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S + * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- */
@@ -79,16 +79,16 @@
// CIMX configuration parameters -//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 /** * PCIEX_BASE_ADDRESS - Define PCIE base address * * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 */ #ifdef MOVE_PCIEBAR_TO_F0000000 -#define PCIEX_BASE_ADDRESS 0xF7000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 #else -#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #endif
@@ -136,11 +136,11 @@
#define AmdNbDispatcher NULL
-#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_TRACE_ALL 0xFFFFFFFF #define CIMX_NBPOR_TRACE 0xFFFFFFFF -#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF #define CIMX_NBPCIE_TRACE 0xFFFFFFFF -#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF #define CIMX_NBPCIE_MISC 0xFFFFFFFF
#endif diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index e7a9ca9..05eaae0 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -25,7 +25,7 @@ #define VOLATILE volatile #define CALLCONV #define ROMDATA -#define CIMXAPI EFIAPI +#define CIMXAPI EFIAPI
// // @@ -44,13 +44,13 @@ typedef UINTN AGESA_STATUS;
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) #define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); @@ -58,85 +58,85 @@ typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. } ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits.
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH;
// AGESA Structures /// The standard header AMD NB UEFI drivers typedef struct _AMD_CONFIG_PARAMS { - VOID **PeiServices; ///< Pointer to PEI service table - VOID *StallPpi; ///< Pointer to Stall PPI -// UINT32 Func; - VOID *PcieBasePtr; ///< TBD - CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function - CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function + CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function } AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure typedef struct _AMD_IMAGE_HEADER { - IN UINT32 Signature; ///< Binary Signature - IN CHAR8 CreatorID[8]; ///< 8 characters ID - IN CHAR8 Version[12]; ///< 12 characters version - IN UINT32 ModuleInfoOffset; ///< Offset of module - IN UINT32 EntryPointAddress; ///< Entry address - IN UINT32 ImageBase; ///< Image base - IN UINT32 RelocTableOffset; ///< Relocate Table offset - IN UINT32 ImageSize; ///< Size - IN UINT16 Checksum; ///< Checksum - IN UINT8 ImageType; ///< Type - IN UINT8 V_Reserved; ///< Reserved + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved } AMD_IMAGE_HEADER;
/// AGESA Binary module header structure typedef struct _AMD_MODULE_HEADER { - IN UINT32 ModuleHeaderSignature; ///< Module signature - IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID - IN CHAR8 ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER;
/// Extended PCI address format typedef struct { - IN OUT UINT32 Register:12; ///< Register offset - IN OUT UINT32 Function:3; ///< Function number - IN OUT UINT32 Device:5; ///< Device number - IN OUT UINT32 Bus:8; ///< Bus number - IN OUT UINT32 Segment:4; ///< Segment + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment } EXT_PCI_ADDR;
/// Union type for PCI address typedef union _PCI_ADDR { - IN UINT32 AddressValue; ///< Formal address - IN EXT_PCI_ADDR Address; ///< Extended address + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address } PCI_ADDR;
-#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7
// SBDFO - Segment Bus Device Function Offset // 31:28 Segment (4-bits) @@ -146,15 +146,15 @@ typedef union _PCI_ADDR { // 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ - (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) #define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format typedef struct _CPUID_DATA { - IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX - IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX - IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX - IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX } CPUID_DATA;
#define WARM_RESET 1 @@ -162,215 +162,215 @@ typedef struct _CPUID_DATA {
/// HT frequency for external callbacks typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks } HT_FREQUENCIES;
#ifndef BIT0 - #define BIT0 0x0000000000000001ull + #define BIT0 0x0000000000000001ull #endif #ifndef BIT1 - #define BIT1 0x0000000000000002ull + #define BIT1 0x0000000000000002ull #endif #ifndef BIT2 - #define BIT2 0x0000000000000004ull + #define BIT2 0x0000000000000004ull #endif #ifndef BIT3 - #define BIT3 0x0000000000000008ull + #define BIT3 0x0000000000000008ull #endif #ifndef BIT4 - #define BIT4 0x0000000000000010ull + #define BIT4 0x0000000000000010ull #endif #ifndef BIT5 - #define BIT5 0x0000000000000020ull + #define BIT5 0x0000000000000020ull #endif #ifndef BIT6 - #define BIT6 0x0000000000000040ull + #define BIT6 0x0000000000000040ull #endif #ifndef BIT7 - #define BIT7 0x0000000000000080ull + #define BIT7 0x0000000000000080ull #endif #ifndef BIT8 - #define BIT8 0x0000000000000100ull + #define BIT8 0x0000000000000100ull #endif #ifndef BIT9 - #define BIT9 0x0000000000000200ull + #define BIT9 0x0000000000000200ull #endif #ifndef BIT10 - #define BIT10 0x0000000000000400ull + #define BIT10 0x0000000000000400ull #endif #ifndef BIT11 - #define BIT11 0x0000000000000800ull + #define BIT11 0x0000000000000800ull #endif #ifndef BIT12 - #define BIT12 0x0000000000001000ull + #define BIT12 0x0000000000001000ull #endif #ifndef BIT13 - #define BIT13 0x0000000000002000ull + #define BIT13 0x0000000000002000ull #endif #ifndef BIT14 - #define BIT14 0x0000000000004000ull + #define BIT14 0x0000000000004000ull #endif #ifndef BIT15 - #define BIT15 0x0000000000008000ull + #define BIT15 0x0000000000008000ull #endif #ifndef BIT16 - #define BIT16 0x0000000000010000ull + #define BIT16 0x0000000000010000ull #endif #ifndef BIT17 - #define BIT17 0x0000000000020000ull + #define BIT17 0x0000000000020000ull #endif #ifndef BIT18 - #define BIT18 0x0000000000040000ull + #define BIT18 0x0000000000040000ull #endif #ifndef BIT19 - #define BIT19 0x0000000000080000ull + #define BIT19 0x0000000000080000ull #endif #ifndef BIT20 - #define BIT20 0x0000000000100000ull + #define BIT20 0x0000000000100000ull #endif #ifndef BIT21 - #define BIT21 0x0000000000200000ull + #define BIT21 0x0000000000200000ull #endif #ifndef BIT22 - #define BIT22 0x0000000000400000ull + #define BIT22 0x0000000000400000ull #endif #ifndef BIT23 - #define BIT23 0x0000000000800000ull + #define BIT23 0x0000000000800000ull #endif #ifndef BIT24 - #define BIT24 0x0000000001000000ull + #define BIT24 0x0000000001000000ull #endif #ifndef BIT25 - #define BIT25 0x0000000002000000ull + #define BIT25 0x0000000002000000ull #endif #ifndef BIT26 - #define BIT26 0x0000000004000000ull + #define BIT26 0x0000000004000000ull #endif #ifndef BIT27 - #define BIT27 0x0000000008000000ull + #define BIT27 0x0000000008000000ull #endif #ifndef BIT28 - #define BIT28 0x0000000010000000ull + #define BIT28 0x0000000010000000ull #endif #ifndef BIT29 - #define BIT29 0x0000000020000000ull + #define BIT29 0x0000000020000000ull #endif #ifndef BIT30 - #define BIT30 0x0000000040000000ull + #define BIT30 0x0000000040000000ull #endif #ifndef BIT31 - #define BIT31 0x0000000080000000ull + #define BIT31 0x0000000080000000ull #endif #ifndef BIT32 - #define BIT32 0x0000000100000000ull + #define BIT32 0x0000000100000000ull #endif #ifndef BIT33 - #define BIT33 0x0000000200000000ull + #define BIT33 0x0000000200000000ull #endif #ifndef BIT34 - #define BIT34 0x0000000400000000ull + #define BIT34 0x0000000400000000ull #endif #ifndef BIT35 - #define BIT35 0x0000000800000000ull + #define BIT35 0x0000000800000000ull #endif #ifndef BIT36 - #define BIT36 0x0000001000000000ull + #define BIT36 0x0000001000000000ull #endif #ifndef BIT37 - #define BIT37 0x0000002000000000ull + #define BIT37 0x0000002000000000ull #endif #ifndef BIT38 - #define BIT38 0x0000004000000000ull + #define BIT38 0x0000004000000000ull #endif #ifndef BIT39 - #define BIT39 0x0000008000000000ull + #define BIT39 0x0000008000000000ull #endif #ifndef BIT40 - #define BIT40 0x0000010000000000ull + #define BIT40 0x0000010000000000ull #endif #ifndef BIT41 - #define BIT41 0x0000020000000000ull + #define BIT41 0x0000020000000000ull #endif #ifndef BIT42 - #define BIT42 0x0000040000000000ull + #define BIT42 0x0000040000000000ull #endif #ifndef BIT43 - #define BIT43 0x0000080000000000ull + #define BIT43 0x0000080000000000ull #endif #ifndef BIT44 - #define BIT44 0x0000100000000000ull + #define BIT44 0x0000100000000000ull #endif #ifndef BIT45 - #define BIT45 0x0000200000000000ull + #define BIT45 0x0000200000000000ull #endif #ifndef BIT46 - #define BIT46 0x0000400000000000ull + #define BIT46 0x0000400000000000ull #endif #ifndef BIT47 - #define BIT47 0x0000800000000000ull + #define BIT47 0x0000800000000000ull #endif #ifndef BIT48 - #define BIT48 0x0001000000000000ull + #define BIT48 0x0001000000000000ull #endif #ifndef BIT49 - #define BIT49 0x0002000000000000ull + #define BIT49 0x0002000000000000ull #endif #ifndef BIT50 - #define BIT50 0x0004000000000000ull + #define BIT50 0x0004000000000000ull #endif #ifndef BIT51 - #define BIT51 0x0008000000000000ull + #define BIT51 0x0008000000000000ull #endif #ifndef BIT52 - #define BIT52 0x0010000000000000ull + #define BIT52 0x0010000000000000ull #endif #ifndef BIT53 - #define BIT53 0x0020000000000000ull + #define BIT53 0x0020000000000000ull #endif #ifndef BIT54 - #define BIT54 0x0040000000000000ull + #define BIT54 0x0040000000000000ull #endif #ifndef BIT55 - #define BIT55 0x0080000000000000ull + #define BIT55 0x0080000000000000ull #endif #ifndef BIT56 - #define BIT56 0x0100000000000000ull + #define BIT56 0x0100000000000000ull #endif #ifndef BIT57 - #define BIT57 0x0200000000000000ull + #define BIT57 0x0200000000000000ull #endif #ifndef BIT58 - #define BIT58 0x0400000000000000ull + #define BIT58 0x0400000000000000ull #endif #ifndef BIT59 - #define BIT59 0x0800000000000000ull + #define BIT59 0x0800000000000000ull #endif #ifndef BIT60 - #define BIT60 0x1000000000000000ull + #define BIT60 0x1000000000000000ull #endif #ifndef BIT61 - #define BIT61 0x2000000000000000ull + #define BIT61 0x2000000000000000ull #endif #ifndef BIT62 - #define BIT62 0x4000000000000000ull + #define BIT62 0x4000000000000000ull #endif #ifndef BIT63 - #define BIT63 0x8000000000000000ull + #define BIT63 0x8000000000000000ull #endif
#ifdef ASSERT diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index eab798d..60bf350 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -38,7 +38,7 @@ void sr56x0_rd890_disable_pcie_bridge(void) AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]);
- nb_cfg->ConfigPtr = &cfg_ptr; + nb_cfg->ConfigPtr = &cfg_ptr; nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); val = (1 << 2) | (1 << 3); /*GPP1*/ val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index c8f7f94..8fb0318 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -28,7 +28,7 @@ static void optimize_xbus(device_t dev) * So this region is read/write and cache able * * FIXME: What about PCI master access into - * this region? + * this region? **/
static void enable_shadow(device_t dev) @@ -50,11 +50,11 @@ static void northbridge_init(device_t dev)
static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -68,9 +68,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned int tomk, tolmk; @@ -118,12 +118,12 @@ static void pci_domain_set_resources(device_t dev) }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) @@ -137,26 +137,26 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - printk(BIOS_SPEW, "DEVICE_PATH_DOMAIN\n"); - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - printk(BIOS_SPEW, "DEVICE_PATH_CPU_CLUSTER\n"); - dev->ops = &cpu_bus_ops; - } else { - printk(BIOS_SPEW, "device path type %d\n",dev->path.type); + printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + printk(BIOS_SPEW, "DEVICE_PATH_DOMAIN\n"); + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + printk(BIOS_SPEW, "DEVICE_PATH_CPU_CLUSTER\n"); + dev->ops = &cpu_bus_ops; + } else { + printk(BIOS_SPEW, "device path type %d\n",dev->path.type); } }
diff --git a/src/northbridge/amd/gx1/raminit.c b/src/northbridge/amd/gx1/raminit.c index aa07f49..bc5e959 100644 --- a/src/northbridge/amd/gx1/raminit.c +++ b/src/northbridge/amd/gx1/raminit.c @@ -2,7 +2,7 @@
/* This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described +called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has been authored by an employee or employees of the University of @@ -150,7 +150,7 @@ int comp_banks; page_size <<= (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
#if 0 - print_debug(" page_size = "); + print_debug(" page_size = "); print_debug_hex32(page_size); print_debug("\n"); #endif @@ -187,7 +187,7 @@ int page_size = 0x800; /* Smallest page = 1K * 2 banks */ page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
#if 0 - print_debug(" page_size = "); + print_debug(" page_size = "); print_debug_hex32(page_size); print_debug("\n"); #endif @@ -267,7 +267,7 @@ unsigned int test; if (test != TEST_DATA1) return 0;
- print_debug(" Found DIMM"); + print_debug(" Found DIMM"); print_debug_char((dimm_shift >> 4) + 0x30); print_debug("\n");
@@ -283,7 +283,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) mem_config &= (~(DIMM_PG_SZ << dimm_shift)); mem_config |= (page_size(dimm_shift));
- print_debug(" Page Size: "); + print_debug(" Page Size: "); print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4))); print_debug("\n");
@@ -292,7 +292,7 @@ static int size_memory(int dimm_shift, unsigned int mem_config) mem_config &= (~(DIMM_COMP_BNK << dimm_shift)); mem_config |= (component_banks(dimm_shift));
- print_debug(" Component Banks: "); + print_debug(" Component Banks: "); print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30); print_debug("\n");
@@ -301,14 +301,14 @@ static int size_memory(int dimm_shift, unsigned int mem_config) mem_config &= (~(DIMM_MOD_BNK << dimm_shift)); mem_config |= (module_banks(dimm_shift));
- print_debug(" Module Banks: "); + print_debug(" Module Banks: "); print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30); print_debug("\n");
mem_config &= (~(DIMM_SZ << dimm_shift)); mem_config |= (size_dimm(dimm_shift));
- print_debug(" DIMM size: "); + print_debug(" DIMM size: "); print_debug_hex32(1 << ((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22); print_debug("\n"); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index e2f4d11..d3c40df 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -97,7 +97,7 @@ void print_conf(void) for (i = 0; cpu_msr_defs[i] != GL_END; i++) { msr = rdmsr(cpu_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - cpu_msr_defs[i], msr.hi, msr.lo); + cpu_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); @@ -105,7 +105,7 @@ void print_conf(void) for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu0_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - gliu0_msr_defs[i], msr.hi, msr.lo); + gliu0_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); @@ -113,7 +113,7 @@ void print_conf(void) for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu1_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - gliu1_msr_defs[i], msr.hi, msr.lo); + gliu1_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- RCONF ------------\n"); @@ -121,7 +121,7 @@ void print_conf(void) for (i = 0; rconf_msr[i] != GL_END; i++) { msr = rdmsr(rconf_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- VARIA ------------\n"); @@ -142,7 +142,7 @@ void print_conf(void) for (i = 0; pci_msr[i] != GL_END; i++) { msr = rdmsr(pci_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); @@ -150,7 +150,7 @@ void print_conf(void) for (i = 0; dma_msr[i] != GL_END; i++) { msr = rdmsr(dma_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n"); @@ -158,7 +158,7 @@ void print_conf(void) for (i = 0; irq_msr[i] != GL_END; i++) { msr = rdmsr(irq_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n"); @@ -166,7 +166,7 @@ void print_conf(void) for (i = 0; lbar_msr[i] != GL_END; i++) { msr = rdmsr(lbar_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); @@ -234,7 +234,7 @@ static void northbridge_set_resources(struct device *dev) for(bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", - bus->secondary); + bus->secondary); assign_resources(bus); } } diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c index cb8b4f0..0da4e69 100644 --- a/src/northbridge/amd/gx2/pll_reset.c +++ b/src/northbridge/amd/gx2/pll_reset.c @@ -25,8 +25,8 @@ #define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
/* spll_raw_clk = SYSREF * FbDIV, - * GLIU Clock = spll_raw_clk / MDIV - * CPU Clock = spll_raw_clk / VDIV + * GLIU Clock = spll_raw_clk / MDIV + * CPU Clock = spll_raw_clk / VDIV */
/* table for Feedback divisor to FbDiv register value */ diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index 71d0a16..9be9200 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -113,7 +113,7 @@ static void auto_size_dimm(unsigned int dimm) * Field: PAGE size * EEPROM byte usage: (4) Number of Column Addresses * PageSize = 2^# Column Addresses * Data width in bytes - * (should be 8bytes for a normal DIMM) + * (should be 8bytes for a normal DIMM) * * But this really works by magic. * If ma[11:0] is the memory address pins, and pa[13:0] is the physical column @@ -122,10 +122,10 @@ static void auto_size_dimm(unsigned int dimm) * * ma 11 10 09 08 07 06 05 04 03 02 01 00 * --------------------------------------- - * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) - * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) - * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) - * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) + * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) + * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) + * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) + * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) * pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) * * (AP = autoprecharge bit) diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index 4537881..22b40a6 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -80,13 +80,13 @@ void graphics_init(void) wClassIndex = (VRC_VG << 8) + VG_CONFIG;
/* - * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) - * External Monochrome Card Support(12) 0, NO - * Controller Priority Select(11) 1, Primary - * Display Select(10:8) 0x0, CRT - * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, - * defined in devicetree.cb - * PLL Reference Clock Bypass(0) 0, Default + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in devicetree.cb + * PLL Reference Clock Bypass(0) 0, Default */
/* Video RAM has to be given in 2MB chunks diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index df69b51..8be5605 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -171,7 +171,7 @@ void print_conf(void) for (i = 0; cpu_msr_defs[i] != GL_END; i++) { msr = rdmsr(cpu_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - cpu_msr_defs[i], msr.hi, msr.lo); + cpu_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n"); @@ -179,7 +179,7 @@ void print_conf(void) for (i = 0; gliu0_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu0_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - gliu0_msr_defs[i], msr.hi, msr.lo); + gliu0_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n"); @@ -187,7 +187,7 @@ void print_conf(void) for (i = 0; gliu1_msr_defs[i] != GL_END; i++) { msr = rdmsr(gliu1_msr_defs[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", - gliu1_msr_defs[i], msr.hi, msr.lo); + gliu1_msr_defs[i], msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- RCONF ------------\n"); @@ -195,7 +195,7 @@ void print_conf(void) for (i = 0; rconf_msr[i] != GL_END; i++) { msr = rdmsr(rconf_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- VARIA ------------\n"); @@ -226,7 +226,7 @@ void print_conf(void) for (i = 0; pci_msr[i] != GL_END; i++) { msr = rdmsr(pci_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n"); @@ -234,7 +234,7 @@ void print_conf(void) for (i = 0; dma_msr[i] != GL_END; i++) { msr = rdmsr(dma_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
printk(BIOS_DEBUG, "---------- CS5536 ------------\n"); @@ -242,7 +242,7 @@ void print_conf(void) for (i = 0; cs5536_msr[i] != GL_END; i++) { msr = rdmsr(cs5536_msr[i]); printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i], - msr.hi, msr.lo); + msr.hi, msr.lo); }
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE); @@ -332,7 +332,7 @@ static void northbridge_set_resources(struct device *dev) for (bus = dev->link_list; bus; bus = bus->next) { if (bus->children) { printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n", - bus->secondary); + bus->secondary); assign_resources(bus); } } diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 42b91d6..478de61 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -53,8 +53,8 @@ struct gliutable gliu1table[] = { {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = 0x0FFF80}, /* 0-7FFFF to MC */ {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0,.lo = (0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW,.hi = MSR_GL0 + 0x0,.lo = 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ - {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ + {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM,.hi = MSR_GL0,.lo = 0x0}, /* Catch and fix dynamicly. */ {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER,.hi = 0x0,.lo = GL1_GLIU0}, {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO,.hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, /* FooGlue FPU 0xF0 */ @@ -224,18 +224,18 @@ static void GLIUInit(struct gliutable *gl)
/* ************************************************************************** */ /* * */ - /* * GLPCIInit */ + /* * GLPCIInit */ /* * */ - /* * Set up GLPCI settings for reads/write into memory */ - /* * R0: 0-640KB, */ - /* * R1: 1MB - Top of System Memory */ - /* * R2: SMM Memory */ - /* * R3: Framebuffer? - not set up yet */ - /* * R4: ?? */ + /* * Set up GLPCI settings for reads/write into memory */ + /* * R0: 0-640KB, */ + /* * R1: 1MB - Top of System Memory */ + /* * R2: SMM Memory */ + /* * R3: Framebuffer? - not set up yet */ + /* * R4: ?? */ /* * */ - /* * Entry: */ - /* * Exit: */ - /* * Modified: */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ /* * */ /* ************************************************************************** */ static void GLPCIInit(void) @@ -290,13 +290,13 @@ static void GLPCIInit(void) GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET; printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", - msr.lo, msr.hi); + msr.lo, msr.hi); msrnum = GLPCI_RC1; wrmsr(msrnum, msr); }
/* */ - /* R2 - GLPCI settings for SMM space */ + /* R2 - GLPCI settings for SMM space */ /* */ msr.hi = ((SMM_OFFSET + @@ -415,13 +415,13 @@ static void GLPCIInit(void)
/* ************************************************************************** */ /* * */ - /* * ClockGatingInit */ + /* * ClockGatingInit */ /* * */ - /* * Enable Clock Gating. */ + /* * Enable Clock Gating. */ /* * */ - /* * Entry: */ - /* * Exit: */ - /* * Modified: */ + /* * Entry: */ + /* * Exit: */ + /* * Modified: */ /* * */ /* ************************************************************************** */ static void ClockGatingInit(void) @@ -570,8 +570,8 @@ static void setShadow(uint64_t shadowSettings) msr.lo = (uint32_t) shadowSettings; msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX msr.hi |= - ((uint32_t) (shadowSettings >> 32)) & - 0x0000FFFF; + ((uint32_t) (shadowSettings >> 32)) & + 0x0000FFFF; wrmsr(pTable->desc_name, msr); // MSR - See the table above } } diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 5cae84f..071e8bb 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -49,7 +49,7 @@ static void pll_reset(void) (0xDE << RSTPPL_LOWER_HOLD_COUNT_SHIFT); msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_COREBYPASS_SET | - RSTPPL_LOWER_MBBYPASS_SET); + RSTPPL_LOWER_MBBYPASS_SET); msrGlcpSysRstpll.lo |= RSTPPL_LOWER_COREPD_SET | RSTPPL_LOWER_CLPD_SET; } diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 6dfb073..e2889b1 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -87,9 +87,9 @@ static void auto_size_dimm(unsigned int dimm)
/*; Field: DIMM size *; EEPROM byte usage: (3) Number of Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density + *; (4) Number of Column Addresses + *; (5) Number of DIMM Banks + *; (31) Module Bank Density *; Size = Module Density * Module Banks */ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) @@ -105,7 +105,7 @@ static void auto_size_dimm(unsigned int dimm) dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
- /* Module Density * Module Banks */ + /* Module Density * Module Banks */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ banner("BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); @@ -131,7 +131,7 @@ static void auto_size_dimm(unsigned int dimm) *;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) *;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) *;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) -*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) +*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) *;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) *;pa 14 13 AP 12 11 10 09 08 07 06 05 04 03 (12 col addr bits = 32K page size) *; *AP=autoprecharge bit @@ -638,7 +638,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) hcf(); }
- /* Set CKEs */ + /* Set CKEs */ msrnum = MC_CFCLK_DBUG; msr = rdmsr(msrnum); msr.lo &= ~(CFCLK_LOWER_MASK_CKE_SET0 | CFCLK_LOWER_MASK_CKE_SET1); @@ -763,11 +763,11 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl) if ((msr.lo & 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */ - /* (depending on where it counts from etc). */ + /* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */ - /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ - /* it would do a normal boot */ + /* 5536 so will need to store the S3 resume flag in NVRAM otherwise */ + /* it would do a normal boot */
/* Reset the system */ msrnum = MDD_SOFT_RESET; diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..b51c7e7 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -42,9 +42,9 @@ static void northbridge_init(device_t dev) }
static struct device_operations northbridge_operations = { - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init + .init = northbridge_init };
static const struct pci_driver northbridge_driver_6025 __pci_driver = { @@ -114,11 +114,11 @@ static void pci_domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void enable_dev(struct device *dev) diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c index 2382fe2..db01ba9 100644 --- a/src/northbridge/dmp/vortex86ex/raminit.c +++ b/src/northbridge/dmp/vortex86ex/raminit.c @@ -58,20 +58,20 @@ static u8 check_dram_side(int addr_bit) }
// DDRIII memory bank register control: -// bit : +// bit : // 2 - 0 : DRAMC_COLSIZE : DDRIII Column Address Type : 0 0 0 = 10bit -// : 0 0 1 = 11bit +// : 0 0 1 = 11bit // 7 - 5 : DRAMC_ROWSIZE : DDRIII Row Address Type : 0 0 0 = 13bit -// : 0 0 1 = 14bit -// : 0 1 0 = 15bit -// : 0 1 1 = 16bit -// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M -// : 0 1 1 0 = 128M -// : 0 1 1 1 = 256M -// : 1 0 0 0 = 512M -// : 1 0 0 1 = 1GB -// : 1 0 1 0 = 2GB -// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable +// : 0 0 1 = 14bit +// : 0 1 0 = 15bit +// : 0 1 1 = 16bit +// 11 - 8 : DRAM_SIZE : DDRIII Size : 0 1 0 1 = 64M +// : 0 1 1 0 = 128M +// : 0 1 1 1 = 256M +// : 1 0 0 0 = 512M +// : 1 0 0 1 = 1GB +// : 1 0 1 0 = 2GB +// 13 : DRAMC_CSMASK : DDRIII CS#[1] Mask : 1 = Mask CS1 enable
#define DDR3_COL_10BIT 0 #define DDR3_COL_11BIT 1 @@ -79,14 +79,14 @@ static u8 check_dram_side(int addr_bit) #define DDR3_ROW_14BIT 1 #define DDR3_ROW_15BIT 2 #define DDR3_ROW_16BIT 3 -#define DDR3_SIZE_64M 5 +#define DDR3_SIZE_64M 5 #define DDR3_SIZE_128M 6 #define DDR3_SIZE_256M 7 #define DDR3_SIZE_512M 8 -#define DDR3_SIZE_1GB 9 -#define DDR3_SIZE_2GB 10 +#define DDR3_SIZE_1GB 9 +#define DDR3_SIZE_2GB 10 #define DDR3_C1M_ACTIVE 0 -#define DDR3_C1M_MASK 1 +#define DDR3_C1M_MASK 1
static u16 set_ddr3_mem_reg_col(u16 reg, u16 col) { diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 07f1596..86fcd80 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -40,7 +40,7 @@ static void dump_pci_device(unsigned dev) unsigned char val; if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); #else print_debug("\n"); print_debug_hex8(i); @@ -77,19 +77,19 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; - for(dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } + device_t dev; + for(dev = PCI_DEV(busn, 0, 0); + dev <= PCI_DEV(busn, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } }
static inline void dump_spd_registers(const struct mem_controller *ctrl) @@ -139,7 +139,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) if (device) { int j; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); + printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); print_debug_hex8(i); @@ -151,7 +151,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) unsigned char byte; if ((j & 0xf) == 0) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); print_debug_hex8(j); @@ -164,7 +164,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) } byte = status & 0xff; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); print_debug_char(' '); @@ -177,41 +177,41 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) static inline void dump_smbus_registers(void) { unsigned device; - print_debug("\n"); - for(device = 1; device < 0x80; device++) { - int j; + print_debug("\n"); + for(device = 1; device < 0x80; device++) { + int j; if( smbus_read_byte(device, 0) < 0 ) continue; #if !defined(__ROMCC__) printk(BIOS_DEBUG, "smbus: %02x", device); #else - print_debug("smbus: "); - print_debug_hex8(device); + print_debug("smbus: "); + print_debug_hex8(device); #endif - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = smbus_read_byte(device, j); - if (status < 0) { + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + status = smbus_read_byte(device, j); + if (status < 0) { break; - } - if ((j & 0xf) == 0) { + } + if ((j & 0xf) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ",j); #else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); #endif - } - byte = status & 0xff; + } + byte = status & 0xff; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); #else - print_debug_hex8(byte); - print_debug_char(' '); + print_debug_hex8(byte); + print_debug_char(' '); #endif - } - print_debug("\n"); + } + print_debug("\n"); } }
@@ -222,38 +222,38 @@ static inline void dump_io_resources(unsigned port) #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%04x:\n", port); #else - print_debug_hex16(port); - print_debug(":\n"); + print_debug_hex16(port); + print_debug(":\n"); #endif - for(i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) { + for(i=0;i<256;i++) { + uint8_t val; + if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); #else - print_debug_hex8(i); - print_debug_char(':'); + print_debug_hex8(i); + print_debug_char(':'); #endif - } - val = inb(port); + } + val = inb(port); #if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x",val); #else - print_debug_char(' '); - print_debug_hex8(val); + print_debug_char(' '); + print_debug_hex8(val); #endif - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } port++; - } + } }
static inline void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; print_debug("dump_mem:"); - for(i=start;i<end;i++) { + for(i=start;i<end;i++) { if((i & 0xf)==0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%08x:", i); @@ -267,9 +267,9 @@ static inline void dump_mem(unsigned start, unsigned end) printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); - print_debug_hex8((unsigned char)*((unsigned char *)i)); + print_debug_hex8((unsigned char)*((unsigned char *)i)); #endif - } - print_debug("\n"); + } + print_debug("\n"); } #endif diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index b0b150d..9d4d139 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -11,9 +11,9 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -40,7 +40,7 @@ static void pci_domain_set_resources(device_t dev) * we won't use the remap window. */ tolmk = tomk; - remapbasek = 0x3ff << 16; + remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; } else { @@ -90,17 +90,17 @@ static void pci_domain_set_resources(device_t dev) }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -108,22 +108,22 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } }
struct chip_operations northbridge_intel_e7501_ops = { diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index f42bef2..5e1df3c 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -42,8 +42,8 @@ Definitions: #define SPD_ERROR "Error reading SPD info\n"
// NOTE: This used to be 0x100000. -// That doesn't work on systems where A20M# is asserted, because -// attempts to access 0x1000NN end up accessing 0x0000NN. +// That doesn't work on systems where A20M# is asserted, because +// attempts to access 0x1000NN end up accessing 0x0000NN. #define RCOMP_MMIO 0x200000
struct dimm_size { @@ -78,7 +78,7 @@ static const uint32_t refresh_rate_map[] = { * [2] == 7.8 us -> 7.8 us * [3] == 31.3 us -> 15.6 us * [4] == 62.5 us -> 15.6 us - * [5] == 125 us -> 64 us + * [5] == 125 us -> 64 us */ 1, 7, 2, 1, 1, 3 }; @@ -97,7 +97,7 @@ static const uint8_t dual_channel_parameters[] = { };
/* - * Table: constant_register_values + * Table: constant_register_values */ static const long constant_register_values[] = { /* SVID - Subsystem Vendor Identification Register @@ -130,14 +130,14 @@ static const long constant_register_values[] = { * Steven James 02/06/2003 */ /* NOTE: values now configured in configure_e7501_cas_latency() based - * on SPD info and total number of DIMMs (per Intel) + * on SPD info and total number of DIMMs (per Intel) */
/* FDHC - Fixed DRAM Hole Control * 0x58 * [7:7] Hole_Enable - * 0 == No memory Hole - * 1 == Memory Hole from 15MB to 16MB + * 0 == No memory Hole + * 1 == Memory Hole from 15MB to 16MB * [6:0] Reserved * * PAM - Programmable Attribute Map @@ -155,10 +155,10 @@ static const long constant_register_values[] = { * 0x5E [5:4] 0xE4000 - 0xE7FFF * 0x5F [1:0] 0xE8000 - 0xEBFFF * 0x5F [5:4] 0xEC000 - 0xEFFFF - * 00 == DRAM Disabled (All Access go to memory mapped I/O space) - * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) - * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) - * 11 == Normal (All Access go to DRAM) + * 00 == DRAM Disabled (All Access go to memory mapped I/O space) + * 01 == Read Only (Reads to DRAM, Writes to memory mapped I/O space) + * 10 == Write Only (Writes to DRAM, Reads to memory mapped I/O space) + * 11 == Normal (All Access go to DRAM) */
// Map all legacy ranges to DRAM @@ -167,14 +167,14 @@ static const long constant_register_values[] = {
/* DRB - DRAM Row Boundary Registers * 0x60 - 0x6F - * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. + * An array of 8 byte registers, which hold the ending + * memory address assigned to each pair of DIMMS, in 64MB + * granularity. */ // Conservatively say each row has 64MB of ram, we will fix this up later // NOTE: These defaults allow us to prime all of the DIMMs on the board - // without jumping through 36-bit adddressing hoops, even if the - // total memory is > 4 GB. Changing these values may break do_ram_command()! + // without jumping through 36-bit adddressing hoops, even if the + // total memory is > 4 GB. Changing these values may break do_ram_command()! 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24),
@@ -184,23 +184,23 @@ static const long constant_register_values[] = { * 0x72 Row 4,5 * 0x73 Row 6,7 * [7:7] Device width for Odd numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 + * 0 == 8 bits wide x8 + * 1 == 4 bits wide x4 * [6:4] Row Attributes for Odd numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (for dual-channel) - * Others == Reserved + * 010 == 8KB (for dual-channel) + * 011 == 16KB (for dual-channel) + * 100 == 32KB (for dual-channel) + * 101 == 64KB (for dual-channel) + * Others == Reserved * [3:3] Device width for Even numbered rows - * 0 == 8 bits wide x8 - * 1 == 4 bits wide x4 + * 0 == 8 bits wide x8 + * 1 == 4 bits wide x4 * [2:0] Row Attributes for Even numbered rows - * 010 == 8KB (for dual-channel) - * 011 == 16KB (for dual-channel) - * 100 == 32KB (for dual-channel) - * 101 == 64KB (This page size appears broken) - * Others == Reserved + * 010 == 8KB (for dual-channel) + * 011 == 16KB (for dual-channel) + * 100 == 32KB (for dual-channel) + * 101 == 64KB (This page size appears broken) + * Others == Reserved */ // NOTE: overridden by configure_e7501_row_attributes(), later 0x70, 0x00000000, 0, @@ -209,54 +209,54 @@ static const long constant_register_values[] = { * 0x78 * [31:30] Reserved * [29:29] Back to Back Write-Read Turn Around - * 0 == 3 clocks between WR-RD commands - * 1 == 2 clocks between WR-RD commands + * 0 == 3 clocks between WR-RD commands + * 1 == 2 clocks between WR-RD commands * [28:28] Back to Back Read-Write Turn Around - * 0 == 5 clocks between RD-WR commands - * 1 == 4 clocks between RD-WR commands + * 0 == 5 clocks between RD-WR commands + * 1 == 4 clocks between RD-WR commands * [27:27] Back to Back Read Turn Around - * 0 == 4 clocks between RD commands - * 1 == 3 clocks between RD commands + * 0 == 4 clocks between RD commands + * 1 == 3 clocks between RD commands * [26:24] Read Delay (tRD) - * 000 == 7 clocks - * 001 == 6 clocks - * 010 == 5 clocks - * Others == Reserved + * 000 == 7 clocks + * 001 == 6 clocks + * 010 == 5 clocks + * Others == Reserved * [23:19] Reserved * [18:16] DRAM idle timer - * 000 == infinite - * 011 == 16 dram clocks - * 001 == 0 clocks + * 000 == infinite + * 011 == 16 dram clocks + * 001 == 0 clocks * [15:11] Reserved * [10:09] Active to Precharge (tRAS) - * 00 == 7 clocks - * 01 == 6 clocks - * 10 == 5 clocks - * 11 == Reserved + * 00 == 7 clocks + * 01 == 6 clocks + * 10 == 5 clocks + * 11 == Reserved * [08:06] Reserved * [05:04] Cas Latency (tCL) - * 00 == 2.5 Clocks - * 01 == 2.0 Clocks - * 10 == Reserved (was 1.5 Clocks for E7500) - * 11 == Reserved + * 00 == 2.5 Clocks + * 01 == 2.0 Clocks + * 10 == Reserved (was 1.5 Clocks for E7500) + * 11 == Reserved * [03:03] Write Ras# to Cas# Delay (tRCD) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks + * 0 == 3 DRAM Clocks + * 1 == 2 DRAM Clocks * [02:01] Read RAS# to CAS# Delay (tRCD) - * 00 == reserved - * 01 == reserved - * 10 == 3 DRAM Clocks - * 11 == 2 DRAM Clocks + * 00 == reserved + * 01 == reserved + * 10 == 3 DRAM Clocks + * 11 == 2 DRAM Clocks * [00:00] DRAM RAS# to Precharge (tRP) - * 0 == 3 DRAM Clocks - * 1 == 2 DRAM Clocks + * 0 == 3 DRAM Clocks + * 1 == 2 DRAM Clocks */
// Some earlier settings: /* Most aggressive settings possible */ -// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), -// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), -// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), +// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), +// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), +// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0),
// The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. @@ -269,48 +269,48 @@ static const long constant_register_values[] = { * 0x7c * [31:30] Reserved * [29:29] Initialization Complete - * 0 == Not Complete - * 1 == Complete + * 0 == Not Complete + * 1 == Complete * [28:23] Reserved - * [22:22] Channels - * 0 == Single channel - * 1 == Dual Channel + * [22:22] Channels + * 0 == Single channel + * 1 == Dual Channel * [21:20] DRAM Data Integrity Mode - * 00 == Disabled, no ECC - * 01 == Reserved - * 10 == Error checking, using chip-kill, with correction - * 11 == Reserved + * 00 == Disabled, no ECC + * 01 == Reserved + * 10 == Error checking, using chip-kill, with correction + * 11 == Reserved * [19:18] DRB Granularity (Read-Only) - * 00 == 32 MB quantities (single channel mode) - * 01 == 64 MB quantities (dual-channel mode) - * 10 == Reserved - * 11 == Reserved - * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) + * 00 == 32 MB quantities (single channel mode) + * 01 == 64 MB quantities (dual-channel mode) + * 10 == Reserved + * 11 == Reserved + * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) - * 0 == 2n Rule - * 1 == 1n rule + * 0 == 2n Rule + * 1 == 1n rule * [15:11] Reserved * [10:08] Refresh mode select - * 000 == Refresh disabled - * 001 == Refresh interval 15.6 usec - * 010 == Refresh interval 7.8 usec - * 011 == Refresh interval 64 usec - * 111 == Refresh every 64 clocks (fast refresh) + * 000 == Refresh disabled + * 001 == Refresh interval 15.6 usec + * 010 == Refresh interval 7.8 usec + * 011 == Refresh interval 64 usec + * 111 == Refresh every 64 clocks (fast refresh) * [07:07] Reserved * [06:04] Mode Select (SMS) - * 000 == Reserved (was Self Refresh Mode in E7500) - * 001 == NOP Command - * 010 == All Banks Precharge - * 011 == Mode Register Set - * 100 == Extended Mode Register Set - * 101 == Reserved - * 110 == CBR Refresh - * 111 == Normal Operation + * 000 == Reserved (was Self Refresh Mode in E7500) + * 001 == NOP Command + * 010 == All Banks Precharge + * 011 == Mode Register Set + * 100 == Extended Mode Register Set + * 101 == Reserved + * 110 == CBR Refresh + * 111 == Normal Operation * [03:00] Reserved */ -// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8),
// Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further @@ -318,56 +318,56 @@ static const long constant_register_values[] = {
/* Another Intel undocumented register * 0x88 - 0x8B - * [31:31] Purpose unknown - * [26:26] Master DLL Reset? - * 0 == Normal operation? - * 1 == Reset? - * [07:07] Periodic memory recalibration? - * 0 == Disabled? - * 1 == Enabled? - * [04:04] Receive FIFO RE-Sync? - * 0 == Normal operation? - * 1 == Reset? + * [31:31] Purpose unknown + * [26:26] Master DLL Reset? + * 0 == Normal operation? + * 1 == Reset? + * [07:07] Periodic memory recalibration? + * 0 == Disabled? + * 1 == Enabled? + * [04:04] Receive FIFO RE-Sync? + * 0 == Normal operation? + * 1 == Reset? */ // NOTE: Some factory BIOSs don't do this. - // Doesn't seem to matter either way. + // Doesn't seem to matter either way. 0x88, 0xffffff00, 0x80,
/* CLOCK_DIS - CK/CK# Disable Register * 0x8C * [7:7] DDR Frequency - * 0 == 100 MHz (200 MHz data rate) - * 1 == 133 MHz (266 MHz data rate) + * 0 == 100 MHz (200 MHz data rate) + * 1 == 133 MHz (266 MHz data rate) * [6:4] Reserved * [3:3] CK3 - * 0 == Enable - * 1 == Disable + * 0 == Enable + * 1 == Disable * [2:2] CK2 - * 0 == Enable - * 1 == Disable + * 0 == Enable + * 1 == Disable * [1:1] CK1 - * 0 == Enable - * 1 == Disable + * 0 == Enable + * 1 == Disable * [0:0] CK0 - * 0 == Enable - * 1 == Disable + * 0 == Enable + * 1 == Disable */ // NOTE: Disable all clocks initially; turn ones we need back on - // in enable_e7501_clocks() + // in enable_e7501_clocks() 0x8C, 0xfffffff0, 0xf,
/* TOLM - Top of Low Memory Register * 0xC4 - 0xC5 * [15:11] Top of low memory (TOLM) - * The address below 4GB that should be treated as RAM, - * on a 128MB granularity. + * The address below 4GB that should be treated as RAM, + * on a 128MB granularity. * [10:00] Reserved */ /* REMAPBASE - Remap Base Address Regsiter * 0xC6 - 0xC7 * [15:10] Reserved * [09:00] Remap Base Address [35:26] 64M aligned - * Bits [25:0] are assumed to be 0. + * Bits [25:0] are assumed to be 0. */
// NOTE: TOLM overridden by configure_e7501_ram_addresses() @@ -385,18 +385,18 @@ static const long constant_register_values[] = { * 0xE0 - 0xE1 * [15:05] Reserved * [04:04] Device 4 Function 1 Present - * 0 == Present - * 1 == Absent + * 0 == Present + * 1 == Absent * [03:03] Device 3 Function 1 Present - * 0 == Present - * 1 == Absent + * 0 == Present + * 1 == Absent * [02:02] Device 2 Function 1 Present - * 0 == Present - * 1 == Absent + * 0 == Present + * 1 == Absent * [01:01] Reserved * [00:00] Device 0 Function 1 Present - * 0 == Present - * 1 == Absent + * 0 == Present + * 1 == Absent */
// Enable D0:D1, disable D2:F1, D3:F1, D4:F1 @@ -412,13 +412,13 @@ static const long constant_register_values[] = { * [30:30] Purpose unknown * [29:23] Unknown - not used? * [22:22] System Memory MMR Enable - * 0 == Disable: mem space and BAR at 0x14 are not accessible - * 1 == Enable: mem space and BAR at 0x14 are accessible + * 0 == Disable: mem space and BAR at 0x14 are not accessible + * 1 == Enable: mem space and BAR at 0x14 are accessible * [21:20] Purpose unknown * [19:02] Unknown - not used? * [01:01] D6EN (Device #6 enable) - * 0 == Disable - * 1 == Enable + * 0 == Disable + * 1 == Enable * [00:00] Unknown - not used? */
@@ -426,7 +426,7 @@ static const long constant_register_values[] = {
#ifdef SUSPICIOUS_LOOKING_CODE // SJM: Undocumented. - // This will access D2:F0:0x50, is this correct?? + // This will access D2:F0:0x50, is this correct?? 0x1050, 0xffffffcf, 0x00000030, #endif }; @@ -604,7 +604,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) * Calculate the log base 2 size in bits of both DIMM sides. * * log2(# bits) = (# columns) + log2(data width) + - * (# rows) + log2(banks per SDRAM) + * (# rows) + log2(banks per SDRAM) * * Note that it might be easier to use SPD byte 31 here, it has the DIMM size * as a multiple of 4MB. The way we do it now we can size both sides of an @@ -659,11 +659,11 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. * @return 1 if both DIMM sockets report the same value for the specified - * SPD parameter, 0 if the values differed or an error occurred. + * SPD parameter, 0 if the values differed or an error occurred. */ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) + uint16_t dimm0_address, + uint16_t dimm1_address) { uint8_t bEqual = 0; int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); @@ -684,16 +684,16 @@ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, * that compatible DIMMs are paired. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @return A bitmask indicating which of the possible sockets for each channel - * was found to contain a compatible DIMM. - * Bit 0 corresponds to the closest socket for channel 0 - * Bit 1 to the next socket for channel 0 - * ... - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 - * ... - * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 + * was found to contain a compatible DIMM. + * Bit 0 corresponds to the closest socket for channel 0 + * Bit 1 to the next socket for channel 0 + * ... + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 + * ... + * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 */ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) { @@ -750,7 +750,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) // Validate DIMM page size // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel // NOTE: 4 KB = 32 Kb = 2^15 - // 32 KB = 262 Kb = 2^18 + // 32 KB = 262 Kb = 2^18
if ((page_size.side1 < 15) || (page_size.side1 > 18)) continue; @@ -798,7 +798,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) for (j = 0; j < sizeof(dual_channel_parameters); ++j) { if (!are_spd_values_equal (dual_channel_parameters[j], channel0_dimm, - channel1_dimm)) { + channel1_dimm)) {
bDualChannel = 0; break; @@ -839,7 +839,7 @@ SDRAM configuration functions: * * @param command Specifies the command to be sent to the DIMMs. * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. + * register value in JEDEC format. */ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { @@ -894,9 +894,9 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // NOTE: 2^26 == 64 MB
uint32_t dimm_start_address = - dimm_start_64M_multiple << 26; + dimm_start_64M_multiple << 26;
- RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); + RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); RAM_DEBUG_MESSAGE("\n");
@@ -904,7 +904,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// Set the start of the next DIMM dimm_start_64M_multiple = - dimm_end_64M_multiple; + dimm_end_64M_multiple; } } } @@ -917,7 +917,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) * by the caller. * * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. + * register value in JEDEC format. */ static void set_ram_mode(uint16_t jedec_mode_bits) { @@ -952,11 +952,11 @@ DIMM-independant configuration functions: * present in the specified DIMM. * * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of - * the DIMM. + * the DIMM. * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of - * 64 MB) for DIMMs < dimm_index. + * 64 MB) for DIMMs < dimm_index. * @param dimm_index Which DIMM pair is being processed - * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). + * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) @@ -968,7 +968,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits // DIMM sides must be at least 32 MB ASSERT(dimm_log2_num_bits.side1 >= 28); ASSERT((dimm_log2_num_bits.side2 == 0) - || (dimm_log2_num_bits.side2 >= 28)); + || (dimm_log2_num_bits.side2 >= 28));
// In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. @@ -1019,7 +1019,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits * would lie behind addresses reserved for memory-mapped I/O. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_ram_addresses(const struct mem_controller @@ -1059,7 +1059,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Configure the Top Of Low Memory (TOLM) in the E7501 // This address must be a multiple of 128 MB that is less than 4 GB. // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address - // in the highest 5 bits. + // in the highest 5 bits.
// We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes @@ -1107,7 +1107,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Define a remap window to make the RAM that would appear from 3 GB - 4 GB // visible just beyond 4 GB or the end of physical memory, whichever is larger // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, - // (i.e. a multiple of 64 MB) in the lowest 10 bits. + // (i.e. a multiple of 64 MB) in the lowest 10 bits. // NOTE: 0x100000000 / (64 MB) == 0x40
if (total_dram_64M_multiple < 0x40) { @@ -1173,7 +1173,7 @@ static void initialize_ecc(void) * parameters of the various installed DIMMs. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, @@ -1190,7 +1190,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
// CAS# latency must be programmed beforehand ASSERT((current_cas_latency == DRT_CAS_2_0) - || (current_cas_latency == DRT_CAS_2_5)); + || (current_cas_latency == DRT_CAS_2_5));
// Each timing parameter is determined by the slowest DIMM
@@ -1232,7 +1232,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, }
// NOTE for timing parameters: - // At 133 MHz, 1 clock == 7.52 ns + // At 133 MHz, 1 clock == 7.52 ns
/* Read the initial state */ dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); @@ -1266,13 +1266,13 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, dram_timing &= ~(3 << 9);
if (slowest_active_to_precharge_delay > 52) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else - dram_timing |= (2 << 9); // < 38 ns: 5 clocks + dram_timing |= (2 << 9); // < 38 ns: 5 clocks
/* Trd */
@@ -1307,7 +1307,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, * common, and program the E7501 to use it. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, @@ -1373,7 +1373,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, goto hw_err; if (value > 0x75) dimm_compatible_cas_latencies &= - ~current_cas_latency; + ~current_cas_latency; } // Can we support the next-highest CAS# latency (max - 1.0)? current_cas_latency >>= 1; @@ -1385,7 +1385,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, goto hw_err; if (value > 0x75) dimm_compatible_cas_latencies &= - ~current_cas_latency; + ~current_cas_latency; } // Restrict the system to CAS# latencies compatible with this DIMM system_compatible_cas_latencies &= @@ -1463,7 +1463,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, * don't support it. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_dram_controller_mode(const struct @@ -1480,8 +1480,8 @@ static void configure_e7501_dram_controller_mode(const struct // Code below assumes that most aggressive settings are in // force when we are called, either via E7501 reset defaults // or by sdram_set_registers(): - // - ECC enabled - // - No refresh + // - ECC enabled + // - No refresh
ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC ASSERT(!(controller_mode & (7 << 8))); // Refresh @@ -1506,7 +1506,7 @@ static void configure_e7501_dram_controller_mode(const struct else dimm_socket_address = ctrl->channel1[i - - MAX_DIMM_SOCKETS_PER_CHANNEL]; + MAX_DIMM_SOCKETS_PER_CHANNEL];
// Disable ECC mode if any one of the DIMMs does not support ECC // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. @@ -1540,8 +1540,8 @@ static void configure_e7501_dram_controller_mode(const struct
#ifdef SUSPICIOUS_LOOKING_CODE // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. +// than the clock period of the memory controller. Also, no other northbridge +// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
// Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns @@ -1570,11 +1570,11 @@ static void configure_e7501_dram_controller_mode(const struct * (4, 8, 16, or 32 KB). * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, uint8_t dimm_mask) { int i; uint32_t row_attributes = 0; @@ -1797,7 +1797,7 @@ static void ram_set_rcomp_regs(void) dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
// NOTE: Some factory BIOS don't do this. - // Doesn't seem to matter either way. + // Doesn't seem to matter either way. dword &= ~2;
dword |= 1; @@ -1838,7 +1838,7 @@ Public interface: * * @param controllers Not used. * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_enable(int controllers, const struct mem_controller *ctrl) @@ -1870,8 +1870,8 @@ static void sdram_enable(int controllers, /* 5. Issue EMRS to enable DLL */ RAM_DEBUG_MESSAGE("Ram Enable 5\n"); do_ram_command(RAM_COMMAND_EMRS, - SDRAM_EXTMODE_DLL_ENABLE | - SDRAM_EXTMODE_DRIVE_NORMAL); + SDRAM_EXTMODE_DLL_ENABLE | + SDRAM_EXTMODE_DRIVE_NORMAL); EXTRA_DELAY;
/* 6. Reset DLL */ @@ -1950,7 +1950,7 @@ static void sdram_enable(int controllers, * DIMMs via the standard Serial Presence Detect (SPD) interface. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { @@ -1995,7 +1995,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) * information (i.e. independent of DIMM specifics). * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_set_registers(const struct mem_controller *ctrl) { diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 3d6ca2a..4a385f1 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -50,7 +50,7 @@ void dump_pci_device(unsigned dev) unsigned char val; if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x:",i); + printk(BIOS_DEBUG, "\n%02x:",i); #else print_debug("\n"); print_debug_hex8(i); @@ -87,19 +87,19 @@ void dump_pci_devices(void)
void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; - for(dev = PCI_DEV(busn, 0, 0); - dev <= PCI_DEV(busn, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } + device_t dev; + for(dev = PCI_DEV(busn, 0, 0); + dev <= PCI_DEV(busn, 0x1f, 0x7); + dev += PCI_DEV(0,0,1)) { + uint32_t id; + id = pci_read_config32(dev, PCI_VENDOR_ID); + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0xffff) || + (((id >> 16) & 0xffff) == 0x0000)) { + continue; + } + dump_pci_device(dev); + } }
void dump_spd_registers(const struct mem_controller *ctrl) @@ -149,7 +149,7 @@ void dump_spd_registers(const struct mem_controller *ctrl) if (device) { int j; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); + printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else print_debug("dimm: "); print_debug_hex8(i); @@ -161,7 +161,7 @@ void dump_spd_registers(const struct mem_controller *ctrl) unsigned char byte; if ((j & 0xf) == 0) { #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "\n%02x: ", j); + printk(BIOS_DEBUG, "\n%02x: ", j); #else print_debug("\n"); print_debug_hex8(j); @@ -174,7 +174,7 @@ void dump_spd_registers(const struct mem_controller *ctrl) } byte = status & 0xff; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); #else print_debug_hex8(byte); print_debug_char(' '); @@ -187,41 +187,41 @@ void dump_spd_registers(const struct mem_controller *ctrl) void dump_smbus_registers(void) { unsigned device; - print_debug("\n"); - for(device = 1; device < 0x80; device++) { - int j; + print_debug("\n"); + for(device = 1; device < 0x80; device++) { + int j; if( spd_read_byte(device, 0) < 0 ) continue; #if !defined(__ROMCC__) printk(BIOS_DEBUG, "smbus: %02x", device); #else - print_debug("smbus: "); - print_debug_hex8(device); + print_debug("smbus: "); + print_debug_hex8(device); #endif - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - status = spd_read_byte(device, j); - if (status < 0) { + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + status = spd_read_byte(device, j); + if (status < 0) { break; - } - if ((j & 0xf) == 0) { + } + if ((j & 0xf) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%02x: ",j); #else - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); #endif - } - byte = status & 0xff; + } + byte = status & 0xff; #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "%02x ", byte); + printk(BIOS_DEBUG, "%02x ", byte); #else - print_debug_hex8(byte); - print_debug_char(' '); + print_debug_hex8(byte); + print_debug_char(' '); #endif - } - print_debug("\n"); + } + print_debug("\n"); } }
@@ -232,38 +232,38 @@ void dump_io_resources(unsigned port) #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%04x:\n", port); #else - print_debug_hex16(port); - print_debug(":\n"); + print_debug_hex16(port); + print_debug(":\n"); #endif - for(i=0;i<256;i++) { - uint8_t val; - if ((i & 0x0f) == 0) { + for(i=0;i<256;i++) { + uint8_t val; + if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); #else - print_debug_hex8(i); - print_debug_char(':'); + print_debug_hex8(i); + print_debug_char(':'); #endif - } - val = inb(port); + } + val = inb(port); #if !defined(__ROMCC__) printk(BIOS_DEBUG, " %02x",val); #else - print_debug_char(' '); - print_debug_hex8(val); + print_debug_char(' '); + print_debug_hex8(val); #endif - if ((i & 0x0f) == 0x0f) { - print_debug("\n"); - } + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } port++; - } + } }
void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; print_debug("dump_mem:"); - for(i=start;i<end;i++) { + for(i=start;i<end;i++) { if((i & 0xf)==0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "\n%08x:", i); @@ -277,8 +277,8 @@ void dump_mem(unsigned start, unsigned end) printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); - print_debug_hex8((unsigned char)*((unsigned char *)i)); + print_debug_hex8((unsigned char)*((unsigned char *)i)); #endif - } - print_debug("\n"); + } + print_debug("\n"); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index a63029b..1c2b293 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -12,9 +12,9 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. @@ -41,7 +41,7 @@ static void pci_domain_set_resources(device_t dev) * we won't use the remap window. */ tolmk = tomk; - remapbasek = 0x3ff << 16; + remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; } else { @@ -101,18 +101,18 @@ static struct pci_operations intel_pci_ops = { };
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci = &intel_pci_ops, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci = &intel_pci_ops, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -120,22 +120,22 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } }
struct chip_operations northbridge_intel_e7505_ops = { diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 3d4dfe2..f36817b 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -60,8 +60,8 @@ Definitions: #define D060DEV PCI_DEV(0,6,0)
// NOTE: This used to be 0x100000. -// That doesn't work on systems where A20M# is asserted, because -// attempts to access 0x1000NN end up accessing 0x0000NN. +// That doesn't work on systems where A20M# is asserted, because +// attempts to access 0x1000NN end up accessing 0x0000NN. #define RCOMP_MMIO 0x200000
struct dimm_size { @@ -96,7 +96,7 @@ static const uint32_t refresh_rate_map[] = { * [2] == 7.8 us -> 7.8 us * [3] == 31.3 us -> 15.6 us * [4] == 62.5 us -> 15.6 us - * [5] == 125 us -> 64 us + * [5] == 125 us -> 64 us */ 1, 7, 2, 1, 1, 3 }; @@ -119,7 +119,7 @@ static const uint8_t dual_channel_parameters[] = { */
/* (DRAM Read Timing Control, if similar to 855PM?) - * 0x80 - 0x81 documented differently for e7505 + * 0x80 - 0x81 documented differently for e7505 * This register has something to do with CAS latencies, * possibily this is the real chipset control. * At 0x00 CAS latency 1.5 works. @@ -135,29 +135,29 @@ static const uint8_t dual_channel_parameters[] = { * Steven James 02/06/2003 * * NOTE: values now configured in configure_e7501_cas_latency() based - * on SPD info and total number of DIMMs (per Intel) + * on SPD info and total number of DIMMs (per Intel) */
/* FDHC - Fixed DRAM Hole Control ??? * 0x58 undocumented for e7505, memory hole in southbridge configuration? * [7:7] Hole_Enable - * 0 == No memory Hole - * 1 == Memory Hole from 15MB to 16MB + * 0 == No memory Hole + * 1 == Memory Hole from 15MB to 16MB * [6:0] Reserved */
/* Another Intel undocumented register * 0x88 - 0x8B - * [31:31] Purpose unknown - * [26:26] Master DLL Reset? - * 0 == Normal operation? - * 1 == Reset? - * [07:07] Periodic memory recalibration? - * 0 == Disabled? - * 1 == Enabled? - * [04:04] Receive FIFO RE-Sync? - * 0 == Normal operation? - * 1 == Reset? + * [31:31] Purpose unknown + * [26:26] Master DLL Reset? + * 0 == Normal operation? + * 1 == Reset? + * [07:07] Periodic memory recalibration? + * 0 == Disabled? + * 1 == Enabled? + * [04:04] Receive FIFO RE-Sync? + * 0 == Normal operation? + * 1 == Reset? */
/* DDR RECOMP tables */ @@ -214,19 +214,19 @@ typedef enum { } rcomp_smr_cc;
/** - * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM + * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM * * [31:31] Purpose unknown * [30:30] Purpose unknown * [29:23] Unknown - not used? * [22:22] System Memory MMR Enable - * 0 == Disable: mem space and BAR at 0x14 are not accessible - * 1 == Enable: mem space and BAR at 0x14 are accessible + * 0 == Disable: mem space and BAR at 0x14 are not accessible + * 1 == Enable: mem space and BAR at 0x14 are accessible * [21:20] Purpose unknown * [19:02] Unknown - not used? * [01:01] D6EN (Device #6 enable) - * 0 == Disable - * 1 == Enable + * 0 == Disable + * 1 == Enable * [00:00] Unknown - not used? */ static void mchtest_control(mchtst_cc cmd) @@ -422,7 +422,7 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) * Calculate the log base 2 size in bits of both DIMM sides. * * log2(# bits) = (# columns) + log2(data width) + - * (# rows) + log2(banks per SDRAM) + * (# rows) + log2(banks per SDRAM) * * Note that it might be easier to use SPD byte 31 here, it has the DIMM size * as a multiple of 4MB. The way we do it now we can size both sides of an @@ -477,11 +477,11 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. * @return 1 if both DIMM sockets report the same value for the specified - * SPD parameter, 0 if the values differed or an error occurred. + * SPD parameter, 0 if the values differed or an error occurred. */ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) + uint16_t dimm0_address, + uint16_t dimm1_address) { uint8_t bEqual = 0; int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); @@ -502,16 +502,16 @@ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, * that compatible DIMMs are paired. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @return A bitmask indicating which of the possible sockets for each channel - * was found to contain a compatible DIMM. - * Bit 0 corresponds to the closest socket for channel 0 - * Bit 1 to the next socket for channel 0 - * ... - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 - * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 - * ... - * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 + * was found to contain a compatible DIMM. + * Bit 0 corresponds to the closest socket for channel 0 + * Bit 1 to the next socket for channel 0 + * ... + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 + * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 + * ... + * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 */ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) { @@ -568,7 +568,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) // Validate DIMM page size // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel // NOTE: 4 KB = 32 Kb = 2^15 - // 32 KB = 262 Kb = 2^18 + // 32 KB = 262 Kb = 2^18
if ((page_size.side1 < 15) || (page_size.side1 > 18)) continue; @@ -616,7 +616,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) for (j = 0; j < sizeof(dual_channel_parameters); ++j) { if (!are_spd_values_equal (dual_channel_parameters[j], channel0_dimm, - channel1_dimm)) { + channel1_dimm)) {
bDualChannel = 0; break; @@ -657,7 +657,7 @@ SDRAM configuration functions: * * @param command Specifies the command to be sent to the DIMMs. * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. + * register value in JEDEC format. */ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { @@ -725,7 +725,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) * by the caller. * * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the - * register value in JEDEC format. + * register value in JEDEC format. */ static void set_ram_mode(uint16_t jedec_mode_bits) { @@ -760,11 +760,11 @@ DIMM-independant configuration functions: * present in the specified DIMM. * * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of - * the DIMM. + * the DIMM. * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of - * 64 MB) for DIMMs < dimm_index. + * 64 MB) for DIMMs < dimm_index. * @param dimm_index Which DIMM pair is being processed - * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). + * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) @@ -776,7 +776,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits // DIMM sides must be at least 32 MB ASSERT(dimm_log2_num_bits.side1 >= 28); ASSERT((dimm_log2_num_bits.side2 == 0) - || (dimm_log2_num_bits.side2 >= 28)); + || (dimm_log2_num_bits.side2 >= 28));
// In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. @@ -827,7 +827,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits * would lie behind addresses reserved for memory-mapped I/O. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_ram_addresses(const struct mem_controller @@ -867,7 +867,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Configure the Top Of Low Memory (TOLM) in the E7501 // This address must be a multiple of 128 MB that is less than 4 GB. // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address - // in the highest 5 bits. + // in the highest 5 bits.
// We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes @@ -915,7 +915,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Define a remap window to make the RAM that would appear from 3 GB - 4 GB // visible just beyond 4 GB or the end of physical memory, whichever is larger // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, - // (i.e. a multiple of 64 MB) in the lowest 10 bits. + // (i.e. a multiple of 64 MB) in the lowest 10 bits. // NOTE: 0x100000000 / (64 MB) == 0x40
if (total_dram_64M_multiple < 0x40) { @@ -1026,7 +1026,7 @@ static inline void __attribute__((always_inline)) * parameters of the various installed DIMMs. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, @@ -1043,7 +1043,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
// CAS# latency must be programmed beforehand ASSERT((current_cas_latency == DRT_CAS_2_0) - || (current_cas_latency == DRT_CAS_2_5)); + || (current_cas_latency == DRT_CAS_2_5));
// Each timing parameter is determined by the slowest DIMM
@@ -1085,7 +1085,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, }
// NOTE for timing parameters: - // At 133 MHz, 1 clock == 7.52 ns + // At 133 MHz, 1 clock == 7.52 ns
/* Read the initial state */ dram_timing = pci_read_config32(MCHDEV, DRT); @@ -1119,13 +1119,13 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, dram_timing &= ~(3 << 9);
if (slowest_active_to_precharge_delay > 52) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else - dram_timing |= (2 << 9); // < 38 ns: 5 clocks + dram_timing |= (2 << 9); // < 38 ns: 5 clocks
/* Trd */
@@ -1160,7 +1160,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, * common, and program the E7501 to use it. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, @@ -1226,7 +1226,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, goto hw_err; if (value > 0x75) dimm_compatible_cas_latencies &= - ~current_cas_latency; + ~current_cas_latency; } // Can we support the next-highest CAS# latency (max - 1.0)? current_cas_latency >>= 1; @@ -1238,7 +1238,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, goto hw_err; if (value > 0x75) dimm_compatible_cas_latencies &= - ~current_cas_latency; + ~current_cas_latency; } // Restrict the system to CAS# latencies compatible with this DIMM system_compatible_cas_latencies &= @@ -1316,7 +1316,7 @@ hw_err: * don't support it. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_dram_controller_mode(const struct @@ -1333,8 +1333,8 @@ static void configure_e7501_dram_controller_mode(const struct // Code below assumes that most aggressive settings are in // force when we are called, either via E7501 reset defaults // or by sdram_set_registers(): - // - ECC enabled - // - No refresh + // - ECC enabled + // - No refresh
ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC ASSERT(!(controller_mode & (7 << 8))); // Refresh @@ -1359,7 +1359,7 @@ static void configure_e7501_dram_controller_mode(const struct else dimm_socket_address = ctrl->channel1[i - - MAX_DIMM_SOCKETS_PER_CHANNEL]; + MAX_DIMM_SOCKETS_PER_CHANNEL];
// Disable ECC mode if any one of the DIMMs does not support ECC // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. @@ -1393,8 +1393,8 @@ static void configure_e7501_dram_controller_mode(const struct
#ifdef SUSPICIOUS_LOOKING_CODE // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. +// than the clock period of the memory controller. Also, no other northbridge +// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
// Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns @@ -1423,11 +1423,11 @@ static void configure_e7501_dram_controller_mode(const struct * (4, 8, 16, or 32 KB). * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, uint8_t dimm_mask) { int i; uint32_t row_attributes = 0; @@ -1657,7 +1657,7 @@ Public interface: * and running. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_enable(const struct mem_controller *ctrl) { @@ -1686,8 +1686,8 @@ static void sdram_enable(const struct mem_controller *ctrl) /* 5. Issue EMRS to enable DLL */ RAM_DEBUG_MESSAGE("Ram Enable 5\n"); do_ram_command(RAM_COMMAND_EMRS, - SDRAM_EXTMODE_DLL_ENABLE | - SDRAM_EXTMODE_DRIVE_NORMAL); + SDRAM_EXTMODE_DLL_ENABLE | + SDRAM_EXTMODE_DRIVE_NORMAL);
/* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); @@ -1736,7 +1736,7 @@ static void sdram_enable(const struct mem_controller *ctrl)
/** * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_post_ecc(const struct mem_controller *ctrl) { @@ -1753,7 +1753,7 @@ static void sdram_post_ecc(const struct mem_controller *ctrl) * DIMMs via the standard Serial Presence Detect (SPD) interface. * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { @@ -1798,7 +1798,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) * information (i.e. independent of DIMM specifics). * * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. + * addresses of DIMM slots on the mainboard. */ static void sdram_set_registers(const struct mem_controller *ctrl) { diff --git a/src/northbridge/intel/e7520/chip.h b/src/northbridge/intel/e7520/chip.h index 99833bd..56b34a0 100644 --- a/src/northbridge/intel/e7520/chip.h +++ b/src/northbridge/intel/e7520/chip.h @@ -1,6 +1,6 @@ struct northbridge_intel_e7520_config { - /* Interrupt line connect */ - unsigned int intrline; + /* Interrupt line connect */ + unsigned int intrline; };
diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c index d7a8048..76f5370 100644 --- a/src/northbridge/intel/e7520/memory_initialized.c +++ b/src/northbridge/intel/e7520/memory_initialized.c @@ -4,10 +4,10 @@ static inline int memory_initialized(void) { uint32_t drc; - drc = pci_read_config32(NB_DEV, DRC); - //print_debug("memory_initialized: DRC: "); - //print_debug_hex32(drc); - //print_debug("\n"); + drc = pci_read_config32(NB_DEV, DRC); + //print_debug("memory_initialized: DRC: "); + //print_debug_hex32(drc); + //print_debug("\n");
return (drc & (1<<29)); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index c632b2d..56b88eb 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -20,7 +20,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list);
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
@@ -52,7 +52,7 @@ static void pci_domain_set_resources(device_t dev) * we won't use the remap window. */ tolmk = tomk; - remapbasek = 0x3ff << 16; + remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; remapoffsetk = 0 << 16; } @@ -115,11 +115,11 @@ static u32 e7520_domain_scan_bus(device_t dev, u32 max)
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = e7520_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = e7520_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void mc_read_resources(device_t dev) @@ -157,11 +157,11 @@ static struct pci_operations intel_pci_ops = {
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .init = 0, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver __pci_driver = { @@ -172,7 +172,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -180,11 +180,11 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c index ab73a71..a79504a 100644 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ b/src/northbridge/intel/e7520/pciexp_porta.c @@ -12,14 +12,14 @@ typedef struct northbridge_intel_e7520_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
@@ -44,19 +44,19 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) }
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PA, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PA, };
diff --git a/src/northbridge/intel/e7520/pciexp_porta1.c b/src/northbridge/intel/e7520/pciexp_porta1.c index c79535f..9da5dfe 100644 --- a/src/northbridge/intel/e7520/pciexp_porta1.c +++ b/src/northbridge/intel/e7520/pciexp_porta1.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7520_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, };
diff --git a/src/northbridge/intel/e7520/pciexp_portb.c b/src/northbridge/intel/e7520/pciexp_portb.c index b20abde..2bfc4bd 100644 --- a/src/northbridge/intel/e7520/pciexp_portb.c +++ b/src/northbridge/intel/e7520/pciexp_portb.c @@ -12,31 +12,31 @@ typedef struct northbridge_intel_e7520_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PB, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PB, };
diff --git a/src/northbridge/intel/e7520/pciexp_portc.c b/src/northbridge/intel/e7520/pciexp_portc.c index d2706d1..f95b108 100644 --- a/src/northbridge/intel/e7520/pciexp_portc.c +++ b/src/northbridge/intel/e7520/pciexp_portc.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7520_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PC, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PC, };
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 55be449..da15b7e 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -95,8 +95,8 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
/* test for ddr2 */ ddr2=0; - value = spd_read_byte(device, 2); /* type */ - if (value < 0) goto hw_err; + value = spd_read_byte(device, 2); /* type */ + if (value < 0) goto hw_err; if (value == 8) ddr2 = 1;
/* Note it might be easier to use byte 31 here, it has the DIMM size as @@ -338,7 +338,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, continue; } value = spd_read_byte(ctrl->channel0[cnt], - latency_indicies[index]); + latency_indicies[index]);
if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { @@ -355,8 +355,8 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
for(cnt=0;cnt<4;cnt++) { if (!(dimm_mask & (1 << cnt))) { - continue; - } + continue; + } reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff; if(((index>>8)&0x0ff)<reg) { index &= ~(0x0ff << 8); @@ -690,7 +690,7 @@ static void pll_setup(uint32_t drc) if((drc&0x0c) == 0x0c) { /* FSB 200 */ pins = 2 | 1; } - else if((drc&0x0c) == 0x08) { /* FSB 167 */ + else if((drc&0x0c) == 0x08) { /* FSB 167 */ pins = 0 | 1; } else if(drc&1){ /* FSB 133 DDR 333 */ @@ -721,8 +721,8 @@ static void pll_setup(uint32_t drc) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { unsigned char c1,c2; - unsigned int dimm,i; - unsigned int data32; + unsigned int dimm,i; + unsigned int data32; unsigned int t4;
/* Set up northbridge values */ @@ -935,7 +935,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) recen+=2; recen >>= 1; recen += (cnt*8); - recen+=2; /* this is not in the spec, but matches + recen+=2; /* this is not in the spec, but matches the factory output, and has less failure */ recen <<= (dimm/2) * 8; if(!(dimm&1)) { @@ -1105,7 +1105,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); - data16 |= (3 << 12); /* use dual channel lock step */ + data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16);
/* program row size DRB */ @@ -1146,9 +1146,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ - write32(BAR+DCALADDR, 0x04000000); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000000); + write32(BAR+DCALADDR, 0x04000000); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1159,9 +1159,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ - write32(BAR+DCALADDR, 0x0b940001); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000001); + write32(BAR+DCALADDR, 0x0b940001); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1169,17 +1169,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* MRS reset dll's */ do_delay(); if ((drc & 3) == 2) { /* DDR2 */ - if(cas_latency == 30) - mode_reg = 0x053a0000; - else - mode_reg = 0x054a0000; - } - else { /* DDR1 */ - if(cas_latency == 20) - mode_reg = 0x012a0000; - else /* CAS Latency 2.5 */ - mode_reg = 0x016a0000; - } + if(cas_latency == 30) + mode_reg = 0x053a0000; + else + mode_reg = 0x054a0000; + } + else { /* DDR1 */ + if(cas_latency == 20) + mode_reg = 0x012a0000; + else /* CAS Latency 2.5 */ + mode_reg = 0x016a0000; + } for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); @@ -1193,9 +1193,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ - write32(BAR+DCALADDR, 0x04000000); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000000); + write32(BAR+DCALADDR, 0x04000000); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1250,15 +1250,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) }
/* Do only if DDR2 EMRS dll's enabled */ - if ((drc & 3) == 2) { /* DDR2 */ - do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR+DCALADDR, (0x0b940001)); - write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); + if ((drc & 3) == 2) { /* DDR2 */ + do_delay(); + for(cs=0;cs<8;cs++) { + write32(BAR+DCALADDR, (0x0b940001)); + write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); - } - } + } + }
do_delay(); /* No command */ @@ -1268,13 +1268,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR, 0x00100000);
- if ((drc & 3) == 2) { /* DDR2 */ + if ((drc & 3) == 2) { /* DDR2 */ /* enable on dimm termination */ set_on_dimm_termination_enable(ctrl); } else { /* ddr */ - pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 ); - } + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 ); + }
/* receive enable calibration */ set_receive_enable(ctrl); diff --git a/src/northbridge/intel/e7525/chip.h b/src/northbridge/intel/e7525/chip.h index c7783d4..4e163a0 100644 --- a/src/northbridge/intel/e7525/chip.h +++ b/src/northbridge/intel/e7525/chip.h @@ -1,6 +1,6 @@ struct northbridge_intel_e7525_config { - /* Interrupt line connect */ - unsigned int intrline; + /* Interrupt line connect */ + unsigned int intrline; };
diff --git a/src/northbridge/intel/e7525/memory_initialized.c b/src/northbridge/intel/e7525/memory_initialized.c index 69bfdf3..d758f70 100644 --- a/src/northbridge/intel/e7525/memory_initialized.c +++ b/src/northbridge/intel/e7525/memory_initialized.c @@ -4,6 +4,6 @@ static inline int memory_initialized(void) { uint32_t drc; - drc = pci_read_config32(NB_DEV, DRC); + drc = pci_read_config32(NB_DEV, DRC); return (drc & (1<<29)); } diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 7625596..34c9809 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -20,7 +20,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list);
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); /* FIXME Me temporary hack */ @@ -51,7 +51,7 @@ static void pci_domain_set_resources(device_t dev) * we won't use the remap window. */ tolmk = tomk; - remapbasek = 0x3ff << 16; + remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; remapoffsetk = 0 << 16; } @@ -114,11 +114,11 @@ static u32 e7525_domain_scan_bus(device_t dev, u32 max)
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = e7525_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = e7525_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void mc_read_resources(device_t dev) @@ -156,11 +156,11 @@ static struct pci_operations intel_pci_ops = {
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .init = 0, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver __pci_driver = { @@ -171,7 +171,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -179,11 +179,11 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
diff --git a/src/northbridge/intel/e7525/pciexp_porta.c b/src/northbridge/intel/e7525/pciexp_porta.c index 4bae287..7c0f671 100644 --- a/src/northbridge/intel/e7525/pciexp_porta.c +++ b/src/northbridge/intel/e7525/pciexp_porta.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7525_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PA, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PA, };
diff --git a/src/northbridge/intel/e7525/pciexp_porta1.c b/src/northbridge/intel/e7525/pciexp_porta1.c index b54ee8a..f1fffe1 100644 --- a/src/northbridge/intel/e7525/pciexp_porta1.c +++ b/src/northbridge/intel/e7525/pciexp_porta1.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7525_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, };
diff --git a/src/northbridge/intel/e7525/pciexp_portb.c b/src/northbridge/intel/e7525/pciexp_portb.c index 7b78b42..f2c3ee8 100644 --- a/src/northbridge/intel/e7525/pciexp_portb.c +++ b/src/northbridge/intel/e7525/pciexp_portb.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7525_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PB, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PB, };
diff --git a/src/northbridge/intel/e7525/pciexp_portc.c b/src/northbridge/intel/e7525/pciexp_portc.c index da6eaf7..e192e6f 100644 --- a/src/northbridge/intel/e7525/pciexp_portc.c +++ b/src/northbridge/intel/e7525/pciexp_portc.c @@ -11,31 +11,31 @@ typedef struct northbridge_intel_e7525_config config_t;
static void pcie_init(struct device *dev) { - config_t *config; + config_t *config;
- /* Get the chip configuration */ - config = dev->chip_info; + /* Get the chip configuration */ + config = dev->chip_info;
- if(config->intrline) { - pci_write_config32(dev, 0x3c, config->intrline); - } + if(config->intrline) { + pci_write_config32(dev, 0x3c, config->intrline); + }
}
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pciexp_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_PCIE_PC, + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_PCIE_PC, };
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 11f26ee..40adf9f 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -98,8 +98,8 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
/* test for ddr2 */ ddr2=0; - value = spd_read_byte(device, 2); /* type */ - if (value < 0) goto hw_err; + value = spd_read_byte(device, 2); /* type */ + if (value < 0) goto hw_err; if (value == 8) ddr2 = 1;
/* Note it might be easier to use byte 31 here, it has the DIMM size as @@ -344,7 +344,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, continue; } value = spd_read_byte(ctrl->channel0[cnt], - latency_indicies[index]); + latency_indicies[index]);
if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { @@ -361,8 +361,8 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
for(cnt=0;cnt<4;cnt++) { if (!(dimm_mask & (1 << cnt))) { - continue; - } + continue; + } reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff; if(((index>>8)&0x0ff)<reg) { index &= ~(0x0ff << 8); @@ -698,8 +698,8 @@ static void do_delay(void) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { unsigned char c1,c2; - unsigned int dimm,i; - unsigned int data32; + unsigned int dimm,i; + unsigned int data32; unsigned int t4;
/* Set up northbridge values */ @@ -1081,7 +1081,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(ctrl->f0, DDRCSR); data16 &= ~(7 << 12); - data16 |= (3 << 12); /* use dual channel lock step */ + data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(ctrl->f0, DDRCSR, data16);
/* program row size DRB */ @@ -1122,9 +1122,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ - write32(BAR+DCALADDR, 0x04000000); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000000); + write32(BAR+DCALADDR, 0x04000000); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1135,9 +1135,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ - write32(BAR+DCALADDR, 0x0b940001); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000001); + write32(BAR+DCALADDR, 0x0b940001); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1145,17 +1145,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* MRS reset dll's */ do_delay(); if ((drc & 3) == 2) { /* DDR2 */ - if(cas_latency == 30) - mode_reg = 0x053a0000; - else - mode_reg = 0x054a0000; - } - else { /* DDR1 */ - if(cas_latency == 20) - mode_reg = 0x012a0000; - else /* CAS Latency 2.5 */ - mode_reg = 0x016a0000; - } + if(cas_latency == 30) + mode_reg = 0x053a0000; + else + mode_reg = 0x054a0000; + } + else { /* DDR1 */ + if(cas_latency == 20) + mode_reg = 0x012a0000; + else /* CAS Latency 2.5 */ + mode_reg = 0x016a0000; + } for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); @@ -1169,9 +1169,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ - write32(BAR+DCALADDR, 0x04000000); - else /* DDR1 */ - write32(BAR+DCALADDR, 0x00000000); + write32(BAR+DCALADDR, 0x04000000); + else /* DDR1 */ + write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); @@ -1226,15 +1226,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) }
/* Do only if DDR2 EMRS dll's enabled */ - if ((drc & 3) == 2) { /* DDR2 */ - do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR+DCALADDR, (0x0b940001)); - write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); + if ((drc & 3) == 2) { /* DDR2 */ + do_delay(); + for(cs=0;cs<8;cs++) { + write32(BAR+DCALADDR, (0x0b940001)); + write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); do data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000); - } - } + } + }
do_delay(); /* No command */ @@ -1244,7 +1244,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR, 0x00100000);
- if ((drc & 3) == 2) { /* DDR2 */ + if ((drc & 3) == 2) { /* DDR2 */ /* enable on dimm termination */ set_on_dimm_termination_enable(ctrl); } diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h index 60eed4d..6919fc4 100644 --- a/src/northbridge/intel/gm45/chip.h +++ b/src/northbridge/intel/gm45/chip.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 227baef..27b1e33 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -116,7 +116,7 @@ typedef struct {
typedef struct { unsigned int card_type; /* 0x0: unpopulated, - 0xa - 0xf: raw card type A - F */ + 0xa - 0xf: raw card type A - F */ chip_width_t chip_width; chip_capacity_t chip_capacity; unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 0a8f21e..ec2b20f 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -48,9 +48,9 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) MCHBAR8(0xbd0 + 4) = 0x5a;
static const u16 display_clock_from_f0_and_vco[][4] = { - /* VCO 2666 VCO 3200 VCO 4000 VCO 5333 */ - { 222, 228, 222, 222, }, - { 333, 320, 333, 333, }, + /* VCO 2666 VCO 3200 VCO 4000 VCO 5333 */ + { 222, 228, 222, 222, }, + { 333, 320, 333, 333, }, }; const int f0_12 = (pci_read_config16(igd_dev, 0xf0) >> 12) & 1; const int vco = raminit_read_vco_index(); @@ -60,7 +60,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) pci_write_config16(igd_dev, 0xcc, reg16);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled, - 2MB GTT + 2MB shadow GTT (0x0b00) else. */ + 2MB GTT + 2MB shadow GTT (0x0b00) else. */ /* Graphics Mode Select: 32MB framebuffer (0x0050) */ /* TODO: We could switch to 64MB (0x0070), config flag? */ const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); @@ -99,7 +99,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) if (!(deven & 2) || no_peg) { /* Disable PEG finally. */ printk(BIOS_DEBUG, "Finally disabling " - "PEG in favor of IGD.\n"); + "PEG in favor of IGD.\n"); MCHBAR8(0xc14) |= (1 << 5) | (1 << 0);
reg32 = pci_read_config32(peg_dev, 0x200); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index afd270f..5482544 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -83,20 +83,20 @@ static void mch_domain_read_resources(device_t dev) /* Total Memory 2GB example: * * 00000000 0000MB-2014MB 2014MB RAM (writeback) - * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) - * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) - * 80000000 2048MB TOLUD - * 80000000 2048MB TOM + * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) + * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) + * 80000000 2048MB TOLUD + * 80000000 2048MB TOM * * Total Memory 4GB example: * * 00000000 0000MB-3038MB 3038MB RAM (writeback) - * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) - * be000000 3040MB-3072MB 32MB GFX UMA (uncached) - * be000000 3072MB TOLUD - * 100000000 4096MB TOM + * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) + * be000000 3040MB-3072MB 32MB GFX UMA (uncached) + * be000000 3072MB TOLUD + * 100000000 4096MB TOM * 100000000 4096MB-5120MB 1024MB RAM (writeback) - * 140000000 5120MB TOUUD + * 140000000 5120MB TOUUD */
pci_domain_read_resources(dev); @@ -114,7 +114,7 @@ static void mch_domain_read_resources(device_t dev) tom <<= 27;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); + touud, tolud, tom);
tomk = tolud >> 10;
@@ -151,17 +151,17 @@ static void mch_domain_read_resources(device_t dev) if (touud > 4096 * 1024) { ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud >> 10) - 4096); }
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " - "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); + "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); /* Don't use uma_resource() as our UMA touches the PCI hole. */ fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE);
if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + "size=0x%x\n", pcie_config_base, pcie_config_size); fixed_mem_resource(dev, 7, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } @@ -196,10 +196,10 @@ static void mch_domain_init(device_t dev)
static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, - .set_resources = mch_domain_set_resources, + .set_resources = mch_domain_set_resources, .enable_resources = NULL, - .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, };
@@ -215,10 +215,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
@@ -260,7 +260,7 @@ static void gm45_init(void *const chip_info) if (!d || d->enabled) continue; const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); + deven & ~(1 << (bit_base + fn))); } }
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 39791a6..4fd0608 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -111,8 +111,8 @@ static void init_dmi(int b2step) }
static void init_pcie(const int peg_enabled, - const int sdvo_enabled, - const int peg_x16) + const int sdvo_enabled, + const int peg_x16) { u8 tmp8; u16 tmp16; diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index d607f84..0f9d9e1 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -31,15 +31,15 @@ #include "gm45.h"
static const gmch_gfx_t gmch_gfx_types[][5] = { -/* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ +/* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, - { GMCH_GM47, GMCH_GM45, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_GM49 }, - { GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45 }, - { GMCH_UNKNOWN, GMCH_GL43, GMCH_GL40, GMCH_UNKNOWN, GMCH_UNKNOWN }, - { GMCH_UNKNOWN, GMCH_GS45, GMCH_GS40, GMCH_UNKNOWN, GMCH_UNKNOWN }, + { GMCH_GM47, GMCH_GM45, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_GM49 }, + { GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45 }, + { GMCH_UNKNOWN, GMCH_GL43, GMCH_GL40, GMCH_UNKNOWN, GMCH_UNKNOWN }, + { GMCH_UNKNOWN, GMCH_GS45, GMCH_GS40, GMCH_UNKNOWN, GMCH_UNKNOWN }, { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, - { GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45 }, + { GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45 }, };
void get_gmch_info(sysinfo_t *sysinfo) @@ -47,7 +47,7 @@ void get_gmch_info(sysinfo_t *sysinfo) sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); if ((sysinfo->stepping > STEPPING_B3) && (sysinfo->stepping != STEPPING_CONVERSION_A1)) - die("Unknown stepping.\n"); + die("Unknown stepping.\n"); if (sysinfo->stepping <= STEPPING_B3) printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); else @@ -335,7 +335,7 @@ static void collect_ddr3(spdinfo_t *const config) config->channel[cur].chip_capacity = smbus_read_byte(smb_addr, 4) & 0xf;
config->channel[cur].banks = 8; /* GM45 only accepts this for DDR3. - verify_ddr3() fails for other values. */ + verify_ddr3() fails for other values. */ config->channel[cur].ranks = ((smbus_read_byte(smb_addr, 7) >> 3) & 7) + 1;
config->channel[cur].cas_latencies = @@ -472,8 +472,8 @@ static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, }
static void calculate_derived_timings(sysinfo_t *const sysinfo, - const unsigned int tCLK, - const spdinfo_t *const spdinfo) + const unsigned int tCLK, + const spdinfo_t *const spdinfo) { int i;
@@ -496,10 +496,10 @@ static void calculate_derived_timings(sysinfo_t *const sysinfo,
/* Lookup tRFC and calculate common tRFCmin. */ const unsigned int tRFC_from_clock_and_cap[][4] = { - /* CAP_256M CAP_512M CAP_1G CAP_2G */ - /* 533MHz */ { 40, 56, 68, 104 }, - /* 400MHz */ { 30, 42, 51, 78 }, - /* 333MHz */ { 25, 35, 43, 65 }, + /* CAP_256M CAP_512M CAP_1G CAP_2G */ + /* 533MHz */ { 40, 56, 68, 104 }, + /* 400MHz */ { 30, 42, 51, 78 }, + /* 333MHz */ { 25, 35, 43, 65 }, }; unsigned int tRFCmin = 0; FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { @@ -624,14 +624,14 @@ static void collect_dimm_config(sysinfo_t *const sysinfo) " Raw card type: %4c\n" " Row addr bits: %4u\n" " Col addr bits: %4u\n" - " byte width: %4u\n" - " page size: %4u\n" - " banks: %4u\n" - " ranks: %4u\n" + " byte width: %4u\n" + " page size: %4u\n" + " banks: %4u\n" + " ranks: %4u\n" " tAAmin: %3u\n" " tCKmin: %3u\n" " Max clock: %3u MHz\n" - " CAS: 0x%04x\n", + " CAS: 0x%04x\n", i, spdinfo.channel[i].raw_card + 'A', spdinfo.channel[i].rows, spdinfo.channel[i].cols, spdinfo.channel[i].width, spdinfo.channel[i].page_size, @@ -770,14 +770,14 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo)
/* Render and sampler frequency values seem to be some kind of factor. */ const u16 render_freq_from_vco_and_gfxtype[][10] = { - /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ + /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ /* VCO 2666 */ { 0xd, 0xd, 0xe, 0xd, 0xb, 0xd, 0xb, 0xa, 0xd }, /* VCO 3200 */ { 0xd, 0xe, 0xf, 0xd, 0xb, 0xd, 0xb, 0x9, 0xd }, /* VCO 4000 */ { 0xc, 0xd, 0xf, 0xc, 0xa, 0xc, 0xa, 0x9, 0xc }, /* VCO 5333 */ { 0xb, 0xc, 0xe, 0xb, 0x9, 0xb, 0x9, 0x8, 0xb }, }; const u16 sampler_freq_from_vco_and_gfxtype[][10] = { - /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ + /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ /* VCO 2666 */ { 0xc, 0xc, 0xd, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, /* VCO 3200 */ { 0xc, 0xd, 0xe, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, /* VCO 4000 */ { 0xa, 0xc, 0xd, 0xa, 0x8, 0xa, 0x8, 0x8, 0xa }, @@ -785,7 +785,7 @@ static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) }; const u16 display_clock_select_from_gfxtype[] = { /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ - 1, 1, 1, 1, 1, 1, 1, 0, 1 + 1, 1, 1, 1, 1, 1, 1, 0, 1 };
if (pci_read_config16(GCFGC_PCIDEV, 0) != 0x8086) { @@ -984,12 +984,12 @@ static void dram_program_timings(const timings_t *const timings)
reg = MCHBAR32(CxDRT4_MCHBAR(i)); static const u8 timings_by_clock[4][3] = { - /* 333MHz 400MHz 533MHz - 667MT 800MT 1067MT */ - { 0x07, 0x0a, 0x0d }, - { 0x3a, 0x46, 0x5d }, - { 0x0c, 0x0e, 0x18 }, - { 0x21, 0x28, 0x35 }, + /* 333MHz 400MHz 533MHz + 667MT 800MT 1067MT */ + { 0x07, 0x0a, 0x0d }, + { 0x3a, 0x46, 0x5d }, + { 0x0c, 0x0e, 0x18 }, + { 0x21, 0x28, 0x35 }, }; const int clk_idx = 2 - timings->mem_clock; reg = (reg & ~(0x01f << 27)) | (timings_by_clock[0][clk_idx] << 27); @@ -1091,7 +1091,7 @@ static void misc_settings(const timings_t *const timings, MCHBAR8(0x13a0) = (MCHBAR8(0x13a0) & ~(0xf)) | 0xa;
MCHBAR32(0x218) = (MCHBAR32(0x218) & ~((7 << 29) | (7 << 25) | (3 << 22) | (3 << 10))) | - (4 << 29) | (3 << 25) | (0 << 22) | (1 << 10); + (4 << 29) | (3 << 25) | (0 << 22) | (1 << 10); MCHBAR32(0x220) = (MCHBAR32(0x220) & ~(7 << 16)) | (1 << 21) | (1 << 16); MCHBAR32(0x224) = (MCHBAR32(0x224) & ~(7 << 8)) | (3 << 8); if (stepping >= STEPPING_B1) @@ -1129,7 +1129,7 @@ static void clock_crossing_setup(const fsb_clock_t fsb, MCHBAR32(0x0210) = data[1];
static const u32 from_fsb_and_mem[][3] = { - /* DDR3-1067 DDR3-800 DDR3-667 */ + /* DDR3-1067 DDR3-800 DDR3-667 */ /* FSB 1067MHz */{ 0x40100401, 0x10040220, 0x08040110, }, /* FSB 800MHz */{ 0x00000000, 0x40100401, 0x00080201, }, /* FSB 667MHz */{ 0x00000000, 0x00000000, 0x40100401, }, @@ -1293,16 +1293,16 @@ static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, mixed = 4 << 11; const unsigned int b = 0x14b0 + (ch * 0x0100); MCHBAR32(b+0x1c) = (MCHBAR32(b+0x1c) & ~(7 << 11)) | - ((( cardF[ch])?1:0) << 11) | mixed; - MCHBAR32(b+0x18) = (MCHBAR32(b+0x18) & ~(7 << 11)) | mixed; + ((( cardF[ch])?1:0) << 11) | mixed; + MCHBAR32(b+0x18) = (MCHBAR32(b+0x18) & ~(7 << 11)) | mixed; MCHBAR32(b+0x14) = (MCHBAR32(b+0x14) & ~(7 << 11)) | (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed; MCHBAR32(b+0x10) = (MCHBAR32(b+0x10) & ~(7 << 11)) | ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed; MCHBAR32(b+0x0c) = (MCHBAR32(b+0x0c) & ~(7 << 11)) | - ((( cardF[ch])?3:2) << 11) | mixed; + ((( cardF[ch])?3:2) << 11) | mixed; MCHBAR32(b+0x08) = (MCHBAR32(b+0x08) & ~(7 << 11)) | - (2 << 11) | mixed; + (2 << 11) | mixed; MCHBAR32(b+0x04) = (MCHBAR32(b+0x04) & ~(7 << 11)) | (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed; MCHBAR32(b+0x00) = (MCHBAR32(b+0x00) & ~(7 << 11)) | @@ -1310,9 +1310,9 @@ static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, } } static void ddr3_write_io_init(const mem_clock_t ddr3clock, - const dimminfo_t *const dimms, - const stepping_t stepping, - const int sff) + const dimminfo_t *const dimms, + const stepping_t stepping, + const int sff) { const int a1step = stepping >= STEPPING_CONVERSION_A1; const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; @@ -1376,8 +1376,8 @@ static void ddr3_write_io_init(const mem_clock_t ddr3clock, MCHBAR32(0x1594) = 0x000d8000; } static void ddr3_read_io_init(const mem_clock_t ddr3clock, - const dimminfo_t *const dimms, - const int sff) + const dimminfo_t *const dimms, + const int sff) { int ch;
@@ -1509,7 +1509,7 @@ static void memory_io_init(const mem_clock_t ddr3clock, }
static void jedec_init(const timings_t *const timings, - const dimminfo_t *const dimms) + const dimminfo_t *const dimms) { if ((timings->tWR < 5) || (timings->tWR > 12)) die("tWR value unsupported in Jedec initialization.\n"); @@ -1558,7 +1558,7 @@ static void jedec_init(const timings_t *const timings, MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; - read32(rankaddr | WR | CAS | INTERLEAVED); + read32(rankaddr | WR | CAS | INTERLEAVED); } }
@@ -1614,7 +1614,7 @@ static void post_jedec_sequence(const int cores) { }
static void dram_optimizations(const timings_t *const timings, - const dimminfo_t *const dimms) + const dimminfo_t *const dimms) { int ch;
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c index 4327045..a11ce56 100644 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c @@ -164,8 +164,8 @@ static const u8 ddr3_lut[2][64][8] = { } }; static void lookup_and_write(const int a1step, - const int row, const int col, - unsigned int mchbar) + const int row, const int col, + unsigned int mchbar) { int i;
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c index 5149c2b..01f3dc5 100644 --- a/src/northbridge/intel/gm45/raminit_read_write_training.c +++ b/src/northbridge/intel/gm45/raminit_read_write_training.c @@ -57,11 +57,11 @@ typedef struct { int p; } read_timing_t; static void print_read_timing(const int msg_lvl, const char *const msg, - const int lane, const int channel, - const read_timing_t *const timing) + const int lane, const int channel, + const read_timing_t *const timing) { printk(msg_lvl, "%s for byte lane %d on channel %d: %d.%d\n", - msg, lane, channel, timing->t, timing->p); + msg, lane, channel, timing->t, timing->p); }
static int normalize_read_timing(read_timing_t *const timing) @@ -76,13 +76,13 @@ static int normalize_read_timing(read_timing_t *const timing) } if (timing->t < 0) { printk(BIOS_WARNING, - "Timing underflow during read training.\n"); + "Timing underflow during read training.\n"); timing->t = 0; timing->p = 0; return -1; } else if (timing->t >= READ_TIMING_T_BOUND) { printk(BIOS_WARNING, - "Timing overflow during read training.\n"); + "Timing overflow during read training.\n"); timing->t = READ_TIMING_T_BOUND - 1; timing->p = READ_TIMING_P_BOUND - 1; return -1; @@ -90,7 +90,7 @@ static int normalize_read_timing(read_timing_t *const timing) return 0; } static int program_read_timing(const int ch, const int lane, - read_timing_t *const timing) + read_timing_t *const timing) { if (normalize_read_timing(timing) < 0) return -1; @@ -104,7 +104,7 @@ static int program_read_timing(const int ch, const int lane, } /* Returns 1 on success, 0 on failure. */ static int read_training_test(const int channel, const int lane, - const address_bunch_t *const addresses) + const address_bunch_t *const addresses) { int i;
@@ -123,8 +123,8 @@ static int read_training_test(const int channel, const int lane, return 1; } static int read_training_find_lower(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const lower) + const address_bunch_t *const addresses, + read_timing_t *const lower) { /* Coarse search for good t. */ program_read_timing(channel, lane, lower); @@ -150,14 +150,14 @@ static int read_training_find_lower(const int channel, const int lane, return 0; } static int read_training_find_upper(const int channel, const int lane, - const address_bunch_t *const addresses, - read_timing_t *const upper) + const address_bunch_t *const addresses, + read_timing_t *const upper) { if (program_read_timing(channel, lane, upper) < 0) return -1; if (!read_training_test(channel, lane, addresses)) { printk(BIOS_WARNING, - "Read training failure: limits too narrow.\n"); + "Read training failure: limits too narrow.\n"); return -1; } /* Coarse search for bad t. */ @@ -275,7 +275,7 @@ static void read_training_restore_results(void) bl_reg |= (3 << 25) | CxRDTy_T(t) | CxRDTy_P(p); MCHBAR32(CxRDTy_MCHBAR(ch, i)) = bl_reg; printk(BIOS_DEBUG, "Restored timings for byte lane " - "%d on channel %d: %d.%d\n", i, ch, t, p); + "%d on channel %d: %d.%d\n", i, ch, t, p); } } } @@ -352,11 +352,11 @@ typedef struct { int p; } write_timing_t; static void print_write_timing(const int msg_lvl, const char *const msg, - const int group, const int channel, - const write_timing_t *const timing) + const int group, const int channel, + const write_timing_t *const timing) { printk(msg_lvl, "%s for group %d on channel %d: %d.%d.%d\n", - msg, group, channel, timing->f, timing->t, timing->p); + msg, group, channel, timing->f, timing->t, timing->p); }
static int normalize_write_timing(write_timing_t *const timing) @@ -379,14 +379,14 @@ static int normalize_write_timing(write_timing_t *const timing) } if (timing->f < 0) { printk(BIOS_WARNING, - "Timing underflow during write training.\n"); + "Timing underflow during write training.\n"); timing->f = 0; timing->t = 0; timing->p = 0; return -1; } else if (timing->f >= WRITE_TIMING_F_BOUND) { printk(BIOS_WARNING, - "Timing overflow during write training.\n"); + "Timing overflow during write training.\n"); timing->f = WRITE_TIMING_F_BOUND - 1; timing->t = timing->t_bound - 1; timing->p = WRITE_TIMING_P_BOUND - 1; @@ -406,7 +406,7 @@ static int program_write_timing(const int ch, const int group, const int f = timing->f; const int t = timing->t; const int p = (memclk1067 && (((t == 9) && (timing->p >= 4)) || - ((t == 10) && (timing->p < 4)))) + ((t == 10) && (timing->p < 4)))) ? 4 : timing->p; const int d = (t <= d_bounds[memclk1067][0]) ? CxWRTy_BELOW_D : @@ -422,7 +422,7 @@ static int program_write_timing(const int ch, const int group, } /* Returns 1 on success, 0 on failure. */ static int write_training_test(const address_bunch_t *const addresses, - const u32 *const masks) + const u32 *const masks) { int i, ret = 0;
@@ -461,9 +461,9 @@ _bad_timing_out: return ret; } static int write_training_find_lower(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const lower) + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const lower) { program_write_timing(ch, group, lower, memclk1067); /* Coarse search for good t. */ @@ -488,15 +488,15 @@ static int write_training_find_lower(const int ch, const int group, return 0; } static int write_training_find_upper(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067, - write_timing_t *const upper) + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067, + write_timing_t *const upper) { if (program_write_timing(ch, group, upper, memclk1067) < 0) return -1; if (!write_training_test(addresses, masks[group])) { printk(BIOS_WARNING, - "Write training failure; limits too narrow.\n"); + "Write training failure; limits too narrow.\n"); return -1; } /* Coarse search for bad t. */ @@ -517,12 +517,12 @@ static int write_training_find_upper(const int ch, const int group, return 0; } static void write_training_per_group(const int ch, const int group, - const address_bunch_t *const addresses, - const u32 masks[][2], const int memclk1067) + const address_bunch_t *const addresses, + const u32 masks[][2], const int memclk1067) { const int t_bound = memclk1067 ? 12 : 11; write_timing_t lower = { 0, 0, t_bound, 0 }, - upper = { 0, 0, t_bound, 0 }; + upper = { 0, 0, t_bound, 0 };
/*** Search lower bound. ***/
@@ -533,7 +533,7 @@ static void write_training_per_group(const int ch, const int group, lower.f = ((reg >> 2) & 0x3) - 1;
if (write_training_find_lower(ch, group, addresses, - masks, memclk1067, &lower) < 0) + masks, memclk1067, &lower) < 0) die("Write training failure: lower bound.\n"); print_write_timing(BIOS_SPEW, "Lower bound", group, ch, &lower);
@@ -545,7 +545,7 @@ static void write_training_per_group(const int ch, const int group, upper.f = lower.f;
if (write_training_find_upper(ch, group, addresses, - masks, memclk1067, &upper) < 0) + masks, memclk1067, &upper) < 0) printk(BIOS_WARNING, "Write training failure: upper bound.\n"); print_write_timing(BIOS_SPEW, "Upper bound", group, ch, &upper);
@@ -567,7 +567,7 @@ static void perform_write_training(const int memclk1067, const dimminfo_t *const dimms) { const int cardF[] = { dimms[0].card_type == 0xf, - dimms[1].card_type == 0xf }; + dimms[1].card_type == 0xf }; int ch, r, group;
address_bunch_t addr[2] = { { { 0, }, 0 }, { { 0, }, 0 }, }; @@ -642,8 +642,8 @@ static void write_training_restore_results(const int memclk1067) timing.p = bytes[(ch * 8) + (i * 2)] & 7; program_write_timing(ch, i, &timing, memclk1067); printk(BIOS_DEBUG, "Restored timings for group %d " - "on channel %d: %d.%d.%d\n", - i, ch, timing.f, timing.t, timing.p); + "on channel %d: %d.%d.%d\n", + i, ch, timing.f, timing.t, timing.p); } } } diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c index 5130b59..72d57e1 100644 --- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c +++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c @@ -205,12 +205,12 @@ static void find_preamble(const int channel, const int group, }
static void receive_enable_calibration(const timings_t *const timings, - const dimminfo_t *const dimms) + const dimminfo_t *const dimms) { /* Override group to byte-lane mapping for raw card type F DIMMS. */ static const char over_bytelane_map[2][4][2] = { /* A,B,C */{ { 0, 1 }, { 2, 3 }, { 4, 5 }, { 6, 7 } }, - /* F */{ { 0, 0 }, { 3, 3 }, { 6, 6 }, { 5, 5 } }, + /* F */{ { 0, 0 }, { 3, 3 }, { 6, 6 }, { 5, 5 } }, };
const int cardF[] = @@ -265,12 +265,12 @@ static void receive_enable_calibration(const timings_t *const timings, program_timing(ch, group, rec_timings); printk(BIOS_SPEW, "Final timings for group %d " "on channel %d: %d.%d.%d.%d.%d\n", - group, ch, - rec_timings[ch][group].c, - rec_timings[ch][group].pre, - rec_timings[ch][group].ph, - rec_timings[ch][group].t, - rec_timings[ch][group].p); + group, ch, + rec_timings[ch][group].c, + rec_timings[ch][group].pre, + rec_timings[ch][group].ph, + rec_timings[ch][group].t, + rec_timings[ch][group].p); } } } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 681f6dc..3c2e750 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -144,7 +144,7 @@ Device (MCHC) * * Format of _PSS: * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } + * Package (6) { freq, power, tlat, blat, control, status } * } */ External (_PR.CPU0._PSS) @@ -156,7 +156,7 @@ Device (MCHC) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index d60504c..e03e0a5 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -30,9 +30,9 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 467ed93..8930917 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -270,7 +270,7 @@ static void gma_read_resources(struct device *dev) }
static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = gma_set_subsystem, };
static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 96438ad..c607aa9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -224,8 +224,8 @@ void report_platform_info(void); #endif /* !__SMM__ */
-#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
struct mrc_data_container { u32 mrc_signature; // "MRCD" diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index f60d0f7..d95d8e7 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -116,7 +116,7 @@ static struct mrc_data_container *find_current_mrc_cache_local }
printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); + entry_id - 1);
return mrc_cache; } @@ -144,11 +144,11 @@ static struct mrc_data_container *find_next_mrc_cache /* Crossed the boundary */ mrc_cache = NULL; printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); + __func__); } else { printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); + "%s: picked next entry from cache block at %p\n", + __func__, mrc_cache); }
return mrc_cache; @@ -173,7 +173,7 @@ static void update_mrc_cache(void *unused) cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); + __func__); return; }
@@ -209,8 +209,8 @@ static void update_mrc_cache(void *unused) */ if (!cache) { printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); + "Need to erase the MRC cache region of %d bytes at %p\n", + cache_size, cache_base);
flash->erase(flash, to_flash_offset(cache_base), cache_size);
@@ -219,14 +219,14 @@ static void update_mrc_cache(void *unused) } // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); + cache); flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); }
BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), + update_mrc_cache, NULL), }; #endif
@@ -238,7 +238,7 @@ struct mrc_data_container *find_current_mrc_cache(void) cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); + __func__); return NULL; }
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ac61ca4..9b6e7fb 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -94,10 +94,10 @@ static void pci_domain_set_resources(device_t dev) */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, };
@@ -121,7 +121,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) * Intel special features, but they do consume resources that need to be * accounted for. */ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, - u32 *len) + u32 *len) { u32 bar;
@@ -141,16 +141,16 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; int (*get_resource)(device_t dev, unsigned int index, - u32 *base, u32 *size); + u32 *base, u32 *size); const char *description; };
#define SIZE_KB(x) ((x)*1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, - { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, - { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, + { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, + { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, + { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, + { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, }; @@ -173,35 +173,35 @@ static void mc_add_fixed_mmio_resources(device_t dev) size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + &base, &size)) continue;
resource = new_resource(dev, mc_fixed_resources[i].index); resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); + __func__, mc_fixed_resources[i].description, index, + (unsigned long)base, (unsigned long)(base + size - 1)); } }
/* Host Memory Map: * * +--------------------------+ TOUUD - * | | + * | | * +--------------------------+ 4GiB - * | PCI Address Space | + * | PCI Address Space | * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | + * | iGD | * +--------------------------+ BDSM - * | GTT | + * | GTT | * +--------------------------+ BGSM - * | TSEG | + * | TSEG | * +--------------------------+ TSEGMB - * | Usage DRAM | + * | Usage DRAM | * +--------------------------+ 0 * * Some of the base registers above can be equal making the size of those @@ -218,7 +218,7 @@ struct map_entry { };
static void read_map_entry(device_t dev, struct map_entry *entry, - uint64_t *result) + uint64_t *result) { uint64_t value; uint64_t mask; @@ -245,8 +245,8 @@ static void read_map_entry(device_t dev, struct map_entry *entry,
#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ + .reg = reg_, \ + .is_64_bit = is_64_, \ .is_limit = is_limit_, \ .description = desc_, \ } @@ -299,7 +299,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); + memory_map[i].description, values[i]); } /* One can validate the BDSM and BGSM against the GGC. */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); @@ -321,7 +321,7 @@ static void mc_add_dram_resources(device_t dev) * These are the host memory ranges that should be added: * - 0 -> SMM_DEFAULT_BASE : cacheable * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : - * cacheable and reserved + * cacheable and reserved * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> BGSM: cacheable with standard MTRRs and reserved @@ -362,8 +362,8 @@ static void mc_add_dram_resources(device_t dev) resource->base = SMM_DEFAULT_BASE; resource->size = SMM_DEFAULT_SIZE; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_CACHEABLE | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + IORESOURCE_CACHEABLE | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
/* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; @@ -380,16 +380,16 @@ static void mc_add_dram_resources(device_t dev) resource->base = mc_values[TSEG_REG]; resource->size = mc_values[BGSM_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
/* BGSM -> TOLUD */ resource = new_resource(dev, index++); resource->base = mc_values[BGSM_REG]; resource->size = mc_values[TOLUD_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED;
/* 4GiB -> TOUUD */ base_k = 4096 * 1024; /* 4GiB */ @@ -405,7 +405,7 @@ static void mc_add_dram_resources(device_t dev) */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10); #if CONFIG_CHROMEOS_RAMOOPS reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, @@ -566,27 +566,27 @@ static void northbridge_enable(device_t dev) }
static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = intel_set_subsystem, };
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = northbridge_enable, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .init = northbridge_init, + .enable = northbridge_enable, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_HSW_MOBILE, };
static const struct pci_driver mc_driver_hsw_ult __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_HSW_ULT, }; @@ -602,10 +602,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(device_t dev) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 7311829..5856a94 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -7,13 +7,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index a90b360..cb49881 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -48,21 +48,21 @@ void save_mrc_data(struct pei_data *pei_data) output_len + sizeof(struct mrc_data_container));
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - pei_data->mrc_output, mrcdata, output_len); + pei_data->mrc_output, mrcdata, output_len);
mrcdata->mrc_signature = MRC_DATA_SIGNATURE; mrcdata->mrc_data_size = output_len; mrcdata->reserved = 0; memcpy(mrcdata->mrc_data, pei_data->mrc_output, - pei_data->mrc_output_len); + pei_data->mrc_output_len);
/* Zero the unused space in aligned buffer. */ if (output_len > pei_data->mrc_output_len) memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, - output_len - pei_data->mrc_output_len); + output_len - pei_data->mrc_output_len);
mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); + mrcdata->mrc_data_size); }
static void prepare_mrc_cache(struct pei_data *pei_data) @@ -82,8 +82,8 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input_len = mrc_cache->mrc_data_size;
printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", - __func__, pei_data->mrc_input, - pei_data->mrc_input_len, mrc_cache->mrc_checksum); + __func__, pei_data->mrc_input, + pei_data->mrc_input_len, mrc_cache->mrc_checksum); }
static const char* ecc_decoder[] = { @@ -107,32 +107,32 @@ static void report_memory_config(void) addr_decode_ch[1] = MCHBAR32(0x5008);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3);
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); + i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", + ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); } }
@@ -172,8 +172,8 @@ void sdram_initialize(struct pei_data *pei_data) if (entry) { int rv; asm volatile ( - "call *%%ecx\n\t" - :"=a" (rv) : "c" (entry), "a" (pei_data)); + "call *%%ecx\n\t" + :"=a" (rv) : "c" (entry), "a" (pei_data)); if (rv) { switch (rv) { case -1: diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8bb4a05..33773c2 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -62,7 +62,7 @@ static void report_cpu_info(void) txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); + mode[aes], mode[txt], mode[vt]); }
/* The PCI id name match comes from Intel document 472178 */ diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h index e9dee4d..6538589 100644 --- a/src/northbridge/intel/i3100/ep80579.h +++ b/src/northbridge/intel/i3100/ep80579.h @@ -20,44 +20,44 @@ #ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H #define NORTHBRIDGE_INTEL_I3100_EP80579_H
-#define SMRBASE 0x14 +#define SMRBASE 0x14 #define MCHCFG0 0x50 -#define FDHC 0x58 -#define PAM 0x59 -#define DRB 0x60 -#define DRT1 0x64 -#define DRA 0x70 -#define DRT0 0x78 -#define DRC 0x7c -#define ECCDIAG 0x84 -#define SDRC 0x88 -#define CKDIS 0x8c -#define CKEDIS 0x8d -#define DEVPRES 0x9c +#define FDHC 0x58 +#define PAM 0x59 +#define DRB 0x60 +#define DRT1 0x64 +#define DRA 0x70 +#define DRT0 0x78 +#define DRC 0x7c +#define ECCDIAG 0x84 +#define SDRC 0x88 +#define CKDIS 0x8c +#define CKEDIS 0x8d +#define DEVPRES 0x9c #define DEVPRES_D0F0 (1 << 0) #define DEVPRES_D1F0 (1 << 1) #define DEVPRES_D2F0 (1 << 2) #define DEVPRES_D3F0 (1 << 3) #define DEVPRES_D4F0 (1 << 4) #define DEVPRES_D10F0 (1 << 5) -#define EXSMRC 0x9d -#define SMRAM 0x9e +#define EXSMRC 0x9d +#define SMRAM 0x9e #define EXSMRAMC 0x9f #define DDR2ODTC 0xb0 -#define TOLM 0xc4 +#define TOLM 0xc4 #define REMAPBASE 0xc6 #define REMAPLIMIT 0xc8 #define REMAPOFFSET 0xca -#define TOM 0xcc -#define HECBASE 0xce +#define TOM 0xcc +#define HECBASE 0xce #define DEVPRES1 0xf4
-#define DCALCSR 0x040 +#define DCALCSR 0x040 #define DCALADDR 0x044 #define DCALDATA 0x048 -#define MBCSR 0x140 -#define MBADDR 0x144 -#define MBDATA 0x148 +#define MBCSR 0x140 +#define MBADDR 0x144 +#define MBDATA 0x148 #define DDRIOMC2 0x268
#endif diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h index 2d036bd..54e8d67 100644 --- a/src/northbridge/intel/i3100/i3100.h +++ b/src/northbridge/intel/i3100/i3100.h @@ -61,8 +61,8 @@ #define MSCFG 0XF6
/* DRC */ -#define DRC_NOECC_MODE (0 << 20) -#define DRC_72BIT_ECC (1 << 20) +#define DRC_NOECC_MODE (0 << 20) +#define DRC_72BIT_ECC (1 << 20)
#define RCBA 0xF0 #define DEFAULT_RCBA 0xFEA00000 diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index dcce48d..6180c5e 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -43,7 +43,7 @@ static void pci_domain_set_resources(device_t dev) device_t mc_dev; u32 pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list);
#if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); @@ -76,7 +76,7 @@ static void pci_domain_set_resources(device_t dev) * we won't use the remap window. */ tolmk = tomk; - remapbasek = 0x3ff << 16; + remapbasek = 0x3ff << 16; remaplimitk = 0 << 16; remapoffsetk = 0 << 16; } @@ -139,11 +139,11 @@ static u32 i3100_domain_scan_bus(device_t dev, u32 max)
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = i3100_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = i3100_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void mc_read_resources(device_t dev) @@ -181,11 +181,11 @@ static struct pci_operations intel_pci_ops = {
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .init = 0, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver __pci_driver = { @@ -196,7 +196,7 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -204,11 +204,11 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index 2fa162f..e40fc3b 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -67,22 +67,22 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA0, };
static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1, }; diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index c0a4d3d..75e0681 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -89,22 +89,22 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pcie_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA0, };
static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_PCIE_PA1, }; diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 0292496..b0639f0 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -844,7 +844,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) recen+=2; recen >>= 1; recen += (cnt*8); - recen+=2; /* this is not in the spec, but matches + recen+=2; /* this is not in the spec, but matches the factory output, and has less failure */ recen <<= (dimm/2) * 8; if(!(dimm&1)) { diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 682b1fc..ab69d06 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -383,14 +383,14 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, print_debug("\n");
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9) - | ((cl - 3) << 6) | ((cl - 3) << 3)); + | ((cl - 3) << 6) | ((cl - 3) << 3)); print_debug("drt0 = "); print_debug_hex32(val); print_debug("\n"); pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25) - | (twtr << 15)); + | (twtr << 15)); print_debug("drt1 = "); print_debug_hex32(val); print_debug("\n"); @@ -503,8 +503,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; - u32 dimm,i; - u32 data32; + u32 dimm,i; + u32 data32; u32 t4;
/* Set up northbridge values */ @@ -700,7 +700,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); do data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000); - } + }
udelay(16); /* No command */ diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 581c6b5..6b0cc5d 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -38,11 +38,11 @@ Method(TOM1, 0) { Method(_CRS, 0) { Name(TMP, ResourceTemplate() { WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length ,, ) IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 2d0ebcc..46f1e14 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -34,35 +34,35 @@ */
#define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ -#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ -#define DRAMT 0x58 /* DRAM Timing (0x03). */ -#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ -#define PAM0 0x59 -#define PAM1 0x5a -#define PAM2 0x5b -#define PAM3 0x5c -#define PAM4 0x5d -#define PAM5 0x5e -#define PAM6 0x5f -#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ -#define DRB0 0x60 -#define DRB1 0x61 -#define DRB2 0x62 -#define DRB3 0x63 -#define DRB4 0x64 -#define DRB5 0x65 -#define DRB6 0x66 -#define DRB7 0x67 -#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ -#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ -#define SMRAM 0x72 /* System Management RAM Control (0x02). */ +#define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ +#define DRAMT 0x58 /* DRAM Timing (0x03). */ +#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ +#define PAM0 0x59 +#define PAM1 0x5a +#define PAM2 0x5b +#define PAM3 0x5c +#define PAM4 0x5d +#define PAM5 0x5e +#define PAM6 0x5f +#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ +#define DRB0 0x60 +#define DRB1 0x61 +#define DRB2 0x62 +#define DRB3 0x63 +#define DRB4 0x64 +#define DRB5 0x65 +#define DRB6 0x66 +#define DRB7 0x67 +#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ +#define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ +#define SMRAM 0x72 /* System Management RAM Control (0x02). */ #define ESMRAMC 0x73 /* Extended System Management RAM Control (0x38). */ -#define RPS 0x74 /* SDRAM Row Page Size (0x0000). */ +#define RPS 0x74 /* SDRAM Row Page Size (0x0000). */ #define SDRAMC 0x76 /* SDRAM Control Register (0x0000). */ -#define PGPOL 0x78 /* Paging Policy Register (0x00). */ -#define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */ -#define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */ -#define EAP 0x80 /* Error Address Pointer Register (0x00000000). */ +#define PGPOL 0x78 /* Paging Policy Register (0x00). */ +#define PMCR 0x7a /* Power Management Control Register (0000_S0S0b). */ +#define SCRR 0x7b /* Suspend CBR Refresh Rate Register (0x0038). */ +#define EAP 0x80 /* Error Address Pointer Register (0x00000000). */ #define ERRCMD 0x90 /* Error Command Register (0x80). */ #define ERRSTS 0x91 /* Error Status (0x0000). */ // TODO: AGP stuff. @@ -73,8 +73,8 @@ #define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */
-#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ -#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ +#define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ +#define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ #define BSPAD0 0xd0 /* These are free for our use. */ #define BSPAD1 0xd1 #define BSPAD2 0xd2 @@ -83,7 +83,7 @@ #define BSPAD5 0xd5 #define BSPAD6 0xd6 #define BSPAD7 0xd7 -#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ -#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ -#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ +#define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ +#define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ +#define BUFFC 0xf0 /* Buffer Control Register (0x0000). */
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 1e6b58e..122050b 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -19,11 +19,11 @@ static void northbridge_init(device_t dev)
static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -92,10 +92,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e3cfbdf..97bd94d 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -54,12 +54,12 @@ Macros and definitions. /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as * defined in DRAMC[2:0]. * - * [0] == Normal 15.625 us -> 15.6 us - * [1] == Reduced(.25X) 3.9 us -> 7.8 ns - * [2] == Reduced(.5X) 7.8 us -> 7.8 us - * [3] == Extended(2x) 31.3 us -> 31.2 us - * [4] == Extended(4x) 62.5 us -> 62.4 us - * [5] == Extended(8x) 125 us -> 124.8 us + * [0] == Normal 15.625 us -> 15.6 us + * [1] == Reduced(.25X) 3.9 us -> 7.8 ns + * [2] == Reduced(.5X) 7.8 us -> 7.8 us + * [3] == Extended(2x) 31.3 us -> 31.2 us + * [4] == Extended(4x) 62.5 us -> 62.4 us + * [5] == Extended(8x) 125 us -> 124.8 us */ static const uint32_t refresh_rate_map[] = { 1, 5, 5, 2, 3, 4 @@ -71,60 +71,60 @@ static const u8 register_values[] = { * 0x50 - 0x53 * * [31:24] SDRAM Row Without ECC - * 0 = ECC components are populated in this row - * 1 = ECC components are not populated in this row + * 0 = ECC components are populated in this row + * 1 = ECC components are not populated in this row * [23:19] Reserved * [18:18] Host Bus Fast Data Ready Enable (HBFDRE) - * Assertion of DRAM data on host bus occurs... - * 0 = ...one clock after sampling snoop results (default) - * 1 = ...on the same clock the snoop result is being sampled - * (this mode is faster by one clock cycle) + * Assertion of DRAM data on host bus occurs... + * 0 = ...one clock after sampling snoop results (default) + * 1 = ...on the same clock the snoop result is being sampled + * (this mode is faster by one clock cycle) * [17:17] ECC - EDO static Drive mode - * 0 = Normal mode (default) - * 1 = ECC signals are always driven + * 0 = Normal mode (default) + * 1 = ECC signals are always driven * [16:16] IDSEL_REDIRECT - * 0 = IDSEL1 is allocated to this bridge (default) - * 1 = IDSEL7 is allocated to this bridge + * 0 = IDSEL1 is allocated to this bridge (default) + * 1 = IDSEL7 is allocated to this bridge * [15:15] WSC# Handshake Disable - * 1 = Uni-processor mode - * 0 = Dual-processor mode with external IOAPIC (default) + * 1 = Uni-processor mode + * 0 = Dual-processor mode with external IOAPIC (default) * [14:14] Intel Reserved * [13:12] Host/DRAM Frequency - * 00 = 100 MHz - * 01 = Reserved - * 10 = 66 MHz - * 11 = Reserved + * 00 = 100 MHz + * 01 = Reserved + * 10 = 66 MHz + * 11 = Reserved * [11:11] AGP to PCI Access Enable - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [10:10] PCI Agent to Aperture Access Disable - * 1 = Disable - * 0 = Enable (default) + * 1 = Disable + * 0 = Enable (default) * [09:09] Aperture Access Global Enable - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [08:07] DRAM Data Integrity Mode (DDIM) - * 00 = Non-ECC - * 01 = EC-only - * 10 = ECC Mode - * 11 = ECC Mode with hardware scrubbing enabled + * 00 = Non-ECC + * 01 = EC-only + * 10 = ECC Mode + * 11 = ECC Mode with hardware scrubbing enabled * [06:06] ECC Diagnostic Mode Enable (EDME) - * 1 = Enable - * 0 = Normal operation mode (default) + * 1 = Enable + * 0 = Normal operation mode (default) * [05:05] MDA Present (MDAP) - * Works in conjunction with the VGA_EN bit. - * VGA_EN MDAP - * 0 x All VGA cycles are sent to PCI - * 1 0 All VGA cycles are sent to AGP - * 1 1 All VGA cycles are sent to AGP, except for - * cycles in the MDA range. + * Works in conjunction with the VGA_EN bit. + * VGA_EN MDAP + * 0 x All VGA cycles are sent to PCI + * 1 0 All VGA cycles are sent to AGP + * 1 1 All VGA cycles are sent to AGP, except for + * cycles in the MDA range. * [04:04] Reserved * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO) - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [02:02] In-Order Queue Depth (IOQD) - * 1 = In-order queue = maximum - * 0 = A7# is sampled asserted (i.e., 0) + * 1 = In-order queue = maximum + * 0 = A7# is sampled asserted (i.e., 0) * [01:00] Reserved */ NBXCFG + 0, 0x00, 0x0c, @@ -138,27 +138,27 @@ static const u8 register_values[] = { * * [7:6] Reserved * [5:5] Module Mode Configuration (MMCONFIG) - * The combination of SDRAMPWR and this bit (which is set by an - * external strapping option) determine how CKE works. - * SDRAMPWR MMCONFIG - * 0 0 = 3 DIMM, CKE0[5:0] driven - * X 1 = 3 DIMM, CKE0 only - * 1 0 = 4 DIMM, GCKE only + * The combination of SDRAMPWR and this bit (which is set by an + * external strapping option) determine how CKE works. + * SDRAMPWR MMCONFIG + * 0 0 = 3 DIMM, CKE0[5:0] driven + * X 1 = 3 DIMM, CKE0 only + * 1 0 = 4 DIMM, GCKE only * [4:3] DRAM Type (DT) - * 00 = EDO - * 01 = SDRAM - * 10 = Registered SDRAM - * 11 = Reserved - * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. + * 00 = EDO + * 01 = SDRAM + * 10 = Registered SDRAM + * 11 = Reserved + * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. * [2:0] DRAM Refresh Rate (DRR) - * 000 = Refresh disabled - * 001 = 15.6 us - * 010 = 31.2 us - * 011 = 62.4 us - * 100 = 124.8 us - * 101 = 249.6 us - * 110 = Reserved - * 111 = Reserved + * 000 = Refresh disabled + * 001 = 15.6 us + * 010 = 31.2 us + * 011 = 62.4 us + * 100 = 124.8 us + * 101 = 249.6 us + * 110 = Reserved + * 111 = Reserved */ /* Choose SDRAM (not registered), and disable refresh for now. */ DRAMC, 0x00, 0x08, @@ -237,10 +237,10 @@ static const u8 register_values[] = { * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB. * * [7:6] Hole Enable (HEN) - * 00 = None - * 01 = 512 KB - 640 KB (128 KB) - * 10 = 15 MB - 16 MB (1 MB) - * 11 = Reserved + * 00 = None + * 01 = 512 KB - 640 KB (128 KB) + * 10 = 15 MB - 16 MB (1 MB) + * 11 = Reserved * [5:0] Reserved */ /* No memory holes. */ @@ -253,10 +253,10 @@ static const u8 register_values[] = { * size is fixed at 2 KB. * * Bits[1:0] Page Size - * 00 2 KB - * 01 4 KB - * 10 8 KB - * 11 Reserved + * 00 2 KB + * 01 4 KB + * 10 8 KB + * 11 Reserved * * RPS bits Corresponding DRB register * [01:00] DRB[0], row 0 @@ -277,33 +277,33 @@ static const u8 register_values[] = { * * [15:10] Reserved * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT) - * 00 = Illegal - * 01 = Add a clock delay to the lead-off clock count - * 1x = Illegal + * 00 = Illegal + * 01 = Add a clock delay to the lead-off clock count + * 1x = Illegal * [07:05] SDRAM Mode Select (SMS) - * 000 = Normal SDRAM Operation (default) - * 001 = NOP Command Enable - * 010 = All Banks Precharge Enable - * 011 = Mode Register Set Enable - * 100 = CBR Enable - * 101 = Reserved - * 110 = Reserved - * 111 = Reserved + * 000 = Normal SDRAM Operation (default) + * 001 = NOP Command Enable + * 010 = All Banks Precharge Enable + * 011 = Mode Register Set Enable + * 100 = CBR Enable + * 101 = Reserved + * 110 = Reserved + * 111 = Reserved * [04:04] SDRAMPWR - * 0 = 3 DIMM configuration - * 1 = 4 DIMM configuration + * 0 = 3 DIMM configuration + * 1 = 4 DIMM configuration * [03:03] Leadoff Command Timing (LCT) - * 0 = 4 CS# Clock - * 1 = 3 CS# Clock + * 0 = 4 CS# Clock + * 1 = 3 CS# Clock * [02:02] CAS# Latency (CL) - * 0 = 3 DCLK CAS# latency - * 1 = 2 DCLK CAS# latency + * 0 = 3 DCLK CAS# latency + * 1 = 2 DCLK CAS# latency * [01:01] SDRAM RAS# to CAS# Delay (SRCD) - * 0 = 3 clocks between a row activate and a read or write cmd. - * 1 = 2 clocks between a row activate and a read or write cmd. + * 0 = 3 clocks between a row activate and a read or write cmd. + * 1 = 2 clocks between a row activate and a read or write cmd. * [00:00] SDRAM RAS# Precharge (SRP) - * 0 = 3 clocks of RAS# precharge - * 1 = 2 clocks of RAS# precharge + * 0 = 3 clocks of RAS# precharge + * 1 = 2 clocks of RAS# precharge */ #if CONFIG_SDRAMPWR_4DIMM SDRAMC + 0, 0x00, 0x10, /* The board has 4 DIMM slots. */ @@ -316,23 +316,23 @@ static const u8 register_values[] = { * 0x78 - 0x79 * * [15:08] Banks per Row (BPR) - * Each bit in this field corresponds to one row of the memory - * array. Bit 15 corresponds to row 7 while bit 8 corresponds - * to row 0. Bits for empty rows are "don't care". - * 0 = 2 banks - * 1 = 4 banks + * Each bit in this field corresponds to one row of the memory + * array. Bit 15 corresponds to row 7 while bit 8 corresponds + * to row 0. Bits for empty rows are "don't care". + * 0 = 2 banks + * 1 = 4 banks * [07:05] Reserved * [04:04] Intel Reserved * [03:00] DRAM Idle Timer (DIT) - * 0000 = 0 clocks - * 0001 = 2 clocks - * 0010 = 4 clocks - * 0011 = 8 clocks - * 0100 = 10 clocks - * 0101 = 12 clocks - * 0110 = 16 clocks - * 0111 = 32 clocks - * 1xxx = Infinite (pages are not closed for idle condition) + * 0000 = 0 clocks + * 0001 = 2 clocks + * 0010 = 4 clocks + * 0011 = 8 clocks + * 0100 = 10 clocks + * 0101 = 12 clocks + * 0110 = 16 clocks + * 0111 = 32 clocks + * 1xxx = Infinite (pages are not closed for idle condition) */ PGPOL + 0, 0x00, 0x00, PGPOL + 1, 0x00, 0xff, @@ -341,28 +341,28 @@ static const u8 register_values[] = { * 0x7a * * [07:07] Power Down SDRAM Enable (PDSE) - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [06:06] ACPI Control Register Enable (SCRE) - * 1 = Enable - * 0 = Disable (default) + * 1 = Enable + * 0 = Disable (default) * [05:05] Suspend Refresh Type (SRT) - * 1 = Self refresh mode - * 0 = CBR fresh mode + * 1 = Self refresh mode + * 0 = CBR fresh mode * [04:04] Normal Refresh Enable (NREF_EN) - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [03:03] Quick Start Mode (QSTART) - * 1 = Quick start mode for the processor is enabled + * 1 = Quick start mode for the processor is enabled * [02:02] Gated Clock Enable (GCLKEN) - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable * [01:01] AGP Disable (AGP_DIS) - * 1 = Disable - * 0 = Enable + * 1 = Disable + * 0 = Enable * [00:00] CPU reset without PCIRST enable (CRst_En) - * 1 = Enable - * 0 = Disable + * 1 = Enable + * 0 = Disable */ /* Enable normal refresh and the gated clock. */ // TODO: Only do this later? @@ -500,8 +500,8 @@ static void set_dram_buffer_strength(void) * MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+||||||||||||||||||||| * MAA[13:0],WEA#,SRASA#,SCASA# -----------------+|||||||||||||||||||||| * Reserved ------------------------------------+||||||||||||||||||||||| - * |||||||||||||||||||||||| - * 3 32 21 10 0 * 2 21 10 0 + * |||||||||||||||||||||||| + * 3 32 21 10 0 * 2 21 10 0 * 9876543210987654321098765432109876543210 * 321098765432109876543210 * a 10------------------------1010---------- * -1---------------11----- a *!a 11------------------------1111---------- * -0---------------00----- !a @@ -611,7 +611,7 @@ static void spd_enable_refresh(void) continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)];
- PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); + PRINT_DEBUG(" Enabling refresh (DRAMC = 0x%02x) for DIMM %02x\n", reg, i); }
pci_write_config8(NB, DRAMC, reg); @@ -638,7 +638,7 @@ void sdram_set_registers(void) reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); #if 0 - PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n", + PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n", register_values[i], reg); #endif } diff --git a/src/northbridge/intel/i440lx/i440lx.h b/src/northbridge/intel/i440lx/i440lx.h index 5e49b81..1572466 100644 --- a/src/northbridge/intel/i440lx/i440lx.h +++ b/src/northbridge/intel/i440lx/i440lx.h @@ -40,34 +40,34 @@ #define DBC 0x53 /* DRAM Row Type Register (0x83) */ #define DRT 0x55 /* DRAM Row Type Register (0x0000) */ #define DRAMC 0x57 /* DRAM Control (0x01) */ -#define DRAMT 0x58 /* DRAM Timing (0x00) */ -#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ -#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ -#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ +#define DRAMT 0x58 /* DRAM Timing (0x00) */ +#define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ +#define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ +#define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ #define DRAMXC 0x6A /* Dram Extended Control Register (0x0000) */ #define MBSC 0x6C /* Memory Buffer Strength Control: (0x55555555) */
-#define SMRAM 0x72 /* System Management RAM Control (0x02). */ +#define SMRAM 0x72 /* System Management RAM Control (0x02). */ #define ERRCMD 0x90 /* Error Command Register (0x80). */ #define ERRSTS0 0x91 /* Error Status (0x0000). */ #define ERRSTS1 0x92 /* Error Status (0x0000). */ // TODO: AGP stuff.
/* For convenience: */ -#define DRB0 0x60 -#define DRB1 0x61 -#define DRB2 0x62 -#define DRB3 0x63 -#define DRB4 0x64 -#define DRB5 0x65 -#define DRB6 0x66 -#define DRB7 0x67 +#define DRB0 0x60 +#define DRB1 0x61 +#define DRB2 0x62 +#define DRB3 0x63 +#define DRB4 0x64 +#define DRB5 0x65 +#define DRB6 0x66 +#define DRB7 0x67
-#define PAM0 0x59 -#define PAM1 0x5a -#define PAM2 0x5b -#define PAM3 0x5c -#define PAM4 0x5d -#define PAM5 0x5e -#define PAM6 0x5f +#define PAM0 0x59 +#define PAM1 0x5a +#define PAM2 0x5b +#define PAM3 0x5c +#define PAM4 0x5d +#define PAM5 0x5e +#define PAM6 0x5f
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index ca4ec6e..54bbd19 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -45,11 +45,11 @@ static void northbridge_init(device_t dev)
static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -118,10 +118,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index d96e4eb..ed2390f 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -64,7 +64,7 @@ static const long register_values[] = {
DBC, 0x00, 0xC3,
- DRT, 0x00, 0xFF, + DRT, 0x00, 0xFF, DRT+1, 0x00, 0xFF,
DRAMC, 0x00, 0x00, /* disable refresh for now. */ @@ -124,29 +124,29 @@ static void do_ram_command(u32 command) /* Send the RAM command to each row of memory. */ dimm_start = 0; for (i = 0; i < (DIMM_SOCKETS * 2); i++) { - addr_offset = 0; - caslatency = 3; /* TODO: Dynamically get CAS latency later. */ + addr_offset = 0; + caslatency = 3; /* TODO: Dynamically get CAS latency later. */
/* before translation it is * * M[02:00] Burst Length * M[03:03] Burst Type * M[06:04] Cas Latency - * 000 - Reserved - * 001 - Reserved - * 010 - CAS 2 - * 011 - CAS 3 - * 100 - Reserved - * 101 - Reserved - * 110 - Reserved - * 111 - Reserved + * 000 - Reserved + * 001 - Reserved + * 010 - CAS 2 + * 011 - CAS 3 + * 100 - Reserved + * 101 - Reserved + * 110 - Reserved + * 111 - Reserved * M[08:07] Op Mode - * Must Be 00b (Defined mode) + * Must Be 00b (Defined mode) * M[09:09] Write Burst Mode - * 0 - Programmed burst length - * 1 - Single location access + * 0 - Programmed burst length + * 1 - Single location access * M[11:10] Reserved - * write 0 to ensure compatibility with.... + * write 0 to ensure compatibility with.... */
/* seems constructed value will be right shifted by 3 bit, thus constructed value @@ -266,7 +266,7 @@ static void sdram_set_registers(void) * for me to confirm what got written */ #if CONFIG_DEBUG_RAM_SETUP - PRINT_DEBUG(" Set register 0x"); + PRINT_DEBUG(" Set register 0x"); PRINT_DEBUG_HEX8(register_values[i]); PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX8(reg); diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 041807e..87b82bb 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -46,11 +46,11 @@ loop: hlt jmp loop
1: /* set magic value for soft reset detection */ - movl $0x800080d0, %eax - movw $0xcf8, %dx - outl %eax, %dx + movl $0x800080d0, %eax + movw $0xcf8, %dx + outl %eax, %dx
- addw $4, %dx + addw $4, %dx movl $0x12345678, %eax outl %eax, %dx
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index c28b0c1..5b39076 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -69,7 +69,7 @@ static void mc_read_resources(device_t dev) ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3, - pci_read_config16(dev16_1, 0x84) & ~3); + pci_read_config16(dev16_1, 0x84) & ~3); memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
memsize <<= 24; @@ -115,15 +115,15 @@ static void mc_read_resources(device_t dev) }
static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = intel_set_subsystem, };
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const unsigned short nb_ids[] = { @@ -134,7 +134,7 @@ static const unsigned short nb_ids[] = { 0};
static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = nb_ids, }; @@ -149,10 +149,10 @@ static void cpu_bus_noop(device_t dev) } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, }; static void pci_domain_set_resources(device_t dev) { @@ -161,10 +161,10 @@ static void pci_domain_set_resources(device_t dev)
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, };
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a..24b3c80 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -59,7 +59,7 @@ static int i5000_for_each_branch(struct i5000_fbd_setup *setup, }
static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, - int (*cb)(struct i5000_fbdimm *)) + int (*cb)(struct i5000_fbdimm *)) { struct i5000_fbdimm *d; int ret, i; @@ -74,7 +74,7 @@ static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, }
static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, - int (*cb)(struct i5000_fbdimm *)) + int (*cb)(struct i5000_fbdimm *)) { struct i5000_fbdimm *d; int ret, i; @@ -171,7 +171,7 @@ static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
default: printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", - d->setup->ddr_speed); + d->setup->ddr_speed);
case DDR_667MHZ: div = 300; @@ -191,7 +191,7 @@ static int mtb2clks(struct i5000_fbdimm *d, int del) break; default: printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", - d->setup->ddr_speed); + d->setup->ddr_speed);
case DDR_667MHZ: div = 300; @@ -214,7 +214,7 @@ static int i5000_read_spd_data(struct i5000_fbdimm *d)
if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) { printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", - d->branch->num, d->channel->num, d->num); + d->branch->num, d->channel->num, d->num); return 0; // No FBDIMM present }
@@ -300,7 +300,7 @@ static int i5000_read_spd_data(struct i5000_fbdimm *d) }
s->t_rc = MAX(s->t_rc, mtb2clks(d, - t_rc | ((t_ras_rc_h & 0xf0) << 4))); + t_rc | ((t_ras_rc_h & 0xf0) << 4))); s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd)); s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc)); s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd)); @@ -327,9 +327,9 @@ static int i5000_read_spd_data(struct i5000_fbdimm *d) d->channel->width = d->sdram_width;
printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, " - "%d columns, %d rows, %d ranks\n", - d->branch->num, d->channel->num, d->num, dimmsize, - d->banks, d->columns, d->rows, d->ranks); + "%d columns, %d rows, %d ranks\n", + d->branch->num, d->channel->num, d->num, dimmsize, + d->banks, d->columns, d->rows, d->ranks);
d->present = 1; d->branch->used |= 1; @@ -356,7 +356,7 @@ static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) return 0;
printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", - d->branch->num, d->channel->num, d->num, byte1, byte2, status); + d->branch->num, d->channel->num, d->num, byte1, byte2, status); for(;;); return -1; } @@ -380,7 +380,7 @@ static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
if (status & I5000_SPD_SBE || !timeout) { printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n", - d->branch->num, d->channel->num, d->num, byte1, status); + d->branch->num, d->channel->num, d->num, byte1, status); return -1; } return 0; @@ -455,19 +455,19 @@ static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d, }
static void i5000_amb_write_config8(struct i5000_fbdimm *d, - int fn, int reg, u32 val) + int fn, int reg, u32 val) { write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); }
static void i5000_amb_write_config16(struct i5000_fbdimm *d, - int fn, int reg, u32 val) + int fn, int reg, u32 val) { write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); }
static void i5000_amb_write_config32(struct i5000_fbdimm *d, - int fn, int reg, u32 val) + int fn, int reg, u32 val) { write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); } @@ -483,7 +483,7 @@ static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command) u32 drc, status;
printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...", - d->branch->num, d->channel->num, d->num, rank, command, addr); + d->branch->num, d->channel->num, d->num, rank, command, addr);
drc = i5000_amb_read_config32(d, 3, AMB_DRC); drc &= ~((3 << 9) | (1 << 12)); @@ -536,7 +536,7 @@ static int i5000_ddr_init(struct i5000_fbdimm *d)
for(rank = 0; rank < d->ranks; rank++) { printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__, - d->branch->num, d->channel->num, d->num, rank); + d->branch->num, d->channel->num, d->num, rank);
if (ddr_command(d, 1 << rank, 0, AMB_DCALCSR_OPCODE_NOP)) @@ -603,7 +603,7 @@ static int i5000_ddr_init(struct i5000_fbdimm *d)
val = (d->setup->t_al << 19) | ((odt & 1) << 18) | - ((odt & 2) << 21) | 1; + ((odt & 2) << 21) | 1;
printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
@@ -621,14 +621,14 @@ static int i5000_amb_preinit(struct i5000_fbdimm *d) u32 id, drc, fbdsbcfg = 0x0909;
printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__, - d->branch->num, d->channel->num, d->num); + d->branch->num, d->channel->num, d->num);
i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]); i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
drc = (d->setup->t_al << 4) | (d->setup->t_cl); printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, - d->cmd2datanxt[d->setup->ddr_speed]); + d->cmd2datanxt[d->setup->ddr_speed]);
switch(d->setup->ddr_speed) { case DDR_533MHZ: @@ -655,7 +655,7 @@ static int i5000_amb_preinit(struct i5000_fbdimm *d) }
pci_write_config8(d->branch->branchdev, - d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); + d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); return 0; }
@@ -679,7 +679,7 @@ static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) }
printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n", - state, b->num); + state, b->num); }
static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) @@ -688,13 +688,13 @@ static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
- printk(BIOS_DEBUG, " waiting for pattern recognition..."); + printk(BIOS_DEBUG, " waiting for pattern recognition..."); while(pci_read_config16(dev, 0) != 0x1fff && --i > 0) udelay(5000);
printk(BIOS_DEBUG, i ? "done\n" : "failed\n"); printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num, - pci_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); + pci_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); return !i; }
@@ -710,9 +710,9 @@ static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wai device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
- printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", - c->branch->num, c->num, - pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); + printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", + c->branch->num, c->num, + pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); pci_write_config8(dev, 0, pattern);
if (!wait) @@ -809,7 +809,7 @@ static int i5000_train_channel_idle(struct i5000_fbd_channel *c) }
pci_write_config8(c->branch->branchdev, - c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05); + c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
for(i = 0; i < 4; i++) { if (c->dimm[i].present) @@ -900,8 +900,8 @@ static int i5000_amb_check(struct i5000_fbdimm *d) u32 id = i5000_amb_read_config32(d, 0, 0);
printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n", - d->branch->num, d->channel->num, d->num, - id & 0xffff, id >> 16); + d->branch->num, d->channel->num, d->num, + id & 0xffff, id >> 16);
if ((id & 0xffff) != d->vendor || id >> 16 != d->device) { printk(BIOS_ERR, "AMB mapping failed\n"); @@ -930,7 +930,7 @@ static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) s = d->setup;
printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n", - d->branch->num, d->channel->num, d->num); + d->branch->num, d->channel->num, d->num);
val = 0x44; printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val); @@ -989,7 +989,7 @@ static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) break; default: printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n", - d->t_refi & 0x0f); + d->t_refi & 0x0f); refi = 7800; break; } @@ -1028,7 +1028,7 @@ static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern) { printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n", - d->branch->num, d->channel->num, d->num, rank, pattern); + d->branch->num, d->channel->num, d->num, rank, pattern);
i5000_amb_write_config32(d, 3, AMB_DAREFTC, i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000); @@ -1051,7 +1051,7 @@ static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank) return 0;
printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n", - d->branch->num, d->channel->num, d->num, rank); + d->branch->num, d->channel->num, d->num, rank); return -1; }
@@ -1130,24 +1130,24 @@ static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
if (c->dimm[0].present || c->dimm[1].present) { val = (((c->columns - 10) & 3) | - (((c->rows - 13) & 3) << 2) | - (((c->ranks == 2) ? 1 : 0) << 4) | - (((c->banks == 8) ? 1 : 0) << 5) | - ((c->width ? 1 : 0) << 6) | - (1 << 7) | /* Electrical Throttling enabled */ - (1 << 8)); /* DIMM present and compatible */ + (((c->rows - 13) & 3) << 2) | + (((c->ranks == 2) ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ printk(BIOS_DEBUG, "MTR0: %04x\n", val); pci_write_config16(c->branch->branchdev, mtr, val); }
if (c->dimm[2].present || c->dimm[3].present) { val = (((c->columns - 10) & 3) | - (((c->rows - 13) & 3) << 4) | - ((c->ranks ? 1 : 0) << 4) | - (((c->banks == 8) ? 1 : 0) << 5) | - ((c->width ? 1 : 0) << 6) | - (1 << 7) | /* Electrical Throttling enabled */ - (1 << 8)); /* DIMM present and compatible */ + (((c->rows - 13) & 3) << 4) | + ((c->ranks ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ printk(BIOS_DEBUG, "MTR1: %04x\n", val); pci_write_config16(c->branch->branchdev, mtr+2, val); } @@ -1239,14 +1239,14 @@ static int i5000_setup_dmir(struct i5000_fbd_branch *b) rankoffset += (set * ranksize);
printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, - dmirval); + dmirval); pci_write_config32(dev, dmir, dmirval); dmir += 4; }
for(; dmir <= I5000_DMIR4; dmir += 4) { printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, - dmirval); + dmirval); pci_write_config32(dev, dmir, dmirval); } return rankoffset; @@ -1272,7 +1272,7 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) mir0 = (size0 << 1) | 3; mir1 = (size0 << 1); mir2 = (size0 << 1); - } else if (!size0) { + } else if (!size0) { mir0 = size1 | 1; mir1 = size1; mir2 = size1; @@ -1460,60 +1460,60 @@ static void i5000_dump_error_registers(void) device_t dev = PCI_ADDR(0, 16, 1, 0);
printk(BIOS_ERR, "Dump of FBD error registers:\n" - "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" - "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" - "EMASK_FBD: 0x%08x\n" - "ERR0_FBD: 0x%08x\n" - "ERR1_FBD: 0x%08x\n" - "ERR2_FBD: 0x%08x\n" - "MC_ERR_FBD: 0x%08x\n", - pci_read_config32(dev, I5000_FERR_FAT_FBD), - pci_read_config32(dev, I5000_NERR_FAT_FBD), - pci_read_config32(dev, I5000_FERR_NF_FBD), - pci_read_config32(dev, I5000_NERR_NF_FBD), - pci_read_config32(dev, I5000_EMASK_FBD), - pci_read_config32(dev, I5000_ERR0_FBD), - pci_read_config32(dev, I5000_ERR1_FBD), - pci_read_config32(dev, I5000_ERR2_FBD), - pci_read_config32(dev, I5000_MCERR_FBD)); + "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" + "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" + "EMASK_FBD: 0x%08x\n" + "ERR0_FBD: 0x%08x\n" + "ERR1_FBD: 0x%08x\n" + "ERR2_FBD: 0x%08x\n" + "MC_ERR_FBD: 0x%08x\n", + pci_read_config32(dev, I5000_FERR_FAT_FBD), + pci_read_config32(dev, I5000_NERR_FAT_FBD), + pci_read_config32(dev, I5000_FERR_NF_FBD), + pci_read_config32(dev, I5000_NERR_NF_FBD), + pci_read_config32(dev, I5000_EMASK_FBD), + pci_read_config32(dev, I5000_ERR0_FBD), + pci_read_config32(dev, I5000_ERR1_FBD), + pci_read_config32(dev, I5000_ERR2_FBD), + pci_read_config32(dev, I5000_MCERR_FBD));
printk(BIOS_ERR, "Non recoverable error registers:\n" - "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" - "NRECFGLOG: 0x%08x\n", - pci_read_config32(dev, I5000_NRECMEMA), - pci_read_config32(dev, I5000_NRECMEMB), - pci_read_config32(dev, I5000_NRECFGLOG)); + "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" + "NRECFGLOG: 0x%08x\n", + pci_read_config32(dev, I5000_NRECMEMA), + pci_read_config32(dev, I5000_NRECMEMB), + pci_read_config32(dev, I5000_NRECFGLOG));
printk(BIOS_ERR, "Packet data:\n" - "NRECFBDA: 0x%08x\n" - "NRECFBDB: 0x%08x\n" - "NRECFBDC: 0x%08x\n" - "NRECFBDD: 0x%08x\n" - "NRECFBDE: 0x%08x\n", - pci_read_config32(dev, I5000_NRECFBDA), - pci_read_config32(dev, I5000_NRECFBDB), - pci_read_config32(dev, I5000_NRECFBDC), - pci_read_config32(dev, I5000_NRECFBDD), - pci_read_config32(dev, I5000_NRECFBDE)); + "NRECFBDA: 0x%08x\n" + "NRECFBDB: 0x%08x\n" + "NRECFBDC: 0x%08x\n" + "NRECFBDD: 0x%08x\n" + "NRECFBDE: 0x%08x\n", + pci_read_config32(dev, I5000_NRECFBDA), + pci_read_config32(dev, I5000_NRECFBDB), + pci_read_config32(dev, I5000_NRECFBDC), + pci_read_config32(dev, I5000_NRECFBDD), + pci_read_config32(dev, I5000_NRECFBDE));
printk(BIOS_ERR, "recoverable error registers:\n" - "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" - "RECFGLOG: 0x%08x\n", - pci_read_config32(dev, I5000_RECMEMA), - pci_read_config32(dev, I5000_RECMEMB), - pci_read_config32(dev, I5000_RECFGLOG)); + "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" + "RECFGLOG: 0x%08x\n", + pci_read_config32(dev, I5000_RECMEMA), + pci_read_config32(dev, I5000_RECMEMB), + pci_read_config32(dev, I5000_RECFGLOG));
printk(BIOS_ERR, "Packet data:\n" - "RECFBDA: 0x%08x\n" - "RECFBDB: 0x%08x\n" - "RECFBDC: 0x%08x\n" - "RECFBDD: 0x%08x\n" - "RECFBDE: 0x%08x\n", - pci_read_config32(dev, I5000_RECFBDA), - pci_read_config32(dev, I5000_RECFBDB), - pci_read_config32(dev, I5000_RECFBDC), - pci_read_config32(dev, I5000_RECFBDD), - pci_read_config32(dev, I5000_RECFBDE)); + "RECFBDA: 0x%08x\n" + "RECFBDB: 0x%08x\n" + "RECFBDC: 0x%08x\n" + "RECFBDD: 0x%08x\n" + "RECFBDE: 0x%08x\n", + pci_read_config32(dev, I5000_RECFBDA), + pci_read_config32(dev, I5000_RECFBDB), + pci_read_config32(dev, I5000_RECFBDC), + pci_read_config32(dev, I5000_RECFBDD), + pci_read_config32(dev, I5000_RECFBDE));
}
@@ -1620,7 +1620,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
if (ddrfrq != ddrfrqnow) { printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n", - ddrfrqnow, ddrfrq); + ddrfrqnow, ddrfrq); pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); /* FSB:FBD mapping changed, needs hard reset */ outb(0x06, 0xcf9); @@ -1660,12 +1660,12 @@ void i5000_fbdimm_init(void) setup.t_al = setup.t_rcd - 1;
printk(BIOS_DEBUG, "global timing parameters:\n" - "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" - "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", - setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, - setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, - setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, - setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al); + "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" + "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", + setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, + setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, + setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, + setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
setup.single_channel = (!(setup.branch[0].channel[1].used || setup.branch[1].channel[0].used || diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h index aa14092..113a0fe 100644 --- a/src/northbridge/intel/i5000/raminit.h +++ b/src/northbridge/intel/i5000/raminit.h @@ -176,10 +176,10 @@ #define AMB_DCALADDR 0x44 #define AMB_DCALCSR_START (1 << 31)
-#define AMB_DCALCSR_OPCODE_NOP 0x00 -#define AMB_DCALCSR_OPCODE_REFRESH 0x01 -#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 -#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 +#define AMB_DCALCSR_OPCODE_NOP 0x00 +#define AMB_DCALCSR_OPCODE_REFRESH 0x01 +#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 +#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 #define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 #define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c #define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h index 8a29ea3..4cf2361 100644 --- a/src/northbridge/intel/i82810/i82810.h +++ b/src/northbridge/intel/i82810/i82810.h @@ -24,7 +24,7 @@ /* * Datasheet: * - Name: Intel 810 Chipset: - * 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) + * 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH) * - URL: http://www.intel.com/design/chipsets/datashts/290656.htm * - PDF: ftp://download.intel.com/design/chipsets/datashts/29065602.pdf * - Order Number: 290656-002 diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 2e07db8..3734c3f 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -55,7 +55,7 @@ static const struct pci_driver i810_northbridge_driver __pci_driver = {
/* Intel 82810E */ static const struct pci_driver i810e_northbridge_driver __pci_driver = { - .ops = &northbridge_operations, + .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x7124, }; @@ -65,7 +65,7 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = { * Some size values appear twice, due to single-sided vs dual-sided banks. */ static int translate_i82810_to_mb[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, };
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 2c379e7..a10df03 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -111,13 +111,13 @@ static const u8 translate_spd_to_i82810[] = { * Some size values appear twice, due to single-sided vs dual-sided banks. */ static const u16 translate_i82810_to_mb[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, };
/* Size of bank#0 for dual-sided DIMMs */ static const u8 translate_i82810_to_bank[] = { -/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ +/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */ /* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128, };
@@ -171,11 +171,11 @@ static void do_ram_command(u8 command) * * (1) Some hardcoded values specified in the datasheet. * (2) Which CAS latency we will use/set. This is the SMAA[4] - * bit, which is 1 for CL3, and 0 for CL2. The bitstring - * so far has the form '00000001X1010', X being SMAA[4]. + * bit, which is 1 for CL3, and 0 for CL2. The bitstring + * so far has the form '00000001X1010', X being SMAA[4]. * (3) The DIMM to which we want to send the command. For - * DIMM0 no special handling is needed, but for DIMM1 we - * must invert the four bits SMAA[7:4] (see datasheet). + * DIMM0 no special handling is needed, but for DIMM1 we + * must invert the four bits SMAA[7:4] (see datasheet). * * Finally, the bitstring has to be shifted 3 bits to the left. * See i810 datasheet pages 43, 85, and 86 for details. @@ -247,7 +247,7 @@ static void spd_set_dram_size(void) printk(BIOS_ERR, "DIMM row sizes larger than 128MB not" "supported on i810\n"); printk - (BIOS_ERR, "Attempting to treat as 128MB DIMM\n"); + (BIOS_ERR, "Attempting to treat as 128MB DIMM\n"); dimm_size = 32; }
@@ -297,23 +297,23 @@ static void set_dram_timing(void) * * (DRP: c = 128MB dual sided, d = 128MB single sided, f = 256MB dual sided) * - * BUFF_SC TOM DRP DIMM0 DIMM1 + * BUFF_SC TOM DRP DIMM0 DIMM1 * ---------------------------------------------------------------------------- - * 0x3356 128MB 0x0c 128MB dual-sided - - * 0xcc56 128MB 0xc0 - 128MB dual-sided - * 0x77da 128MB 0x0d 128MB single-sided - - * 0xddda 128MB 0xd0 - 128MB single-sided - * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided - * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided - * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided - * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided - * 0x3356 256MB 0x0f 256MB dual-sided - - * 0xcc56 256MB 0xf0 - 256MB dual-sided - * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided - * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided - * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided - * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided - * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided + * 0x3356 128MB 0x0c 128MB dual-sided - + * 0xcc56 128MB 0xc0 - 128MB dual-sided + * 0x77da 128MB 0x0d 128MB single-sided - + * 0xddda 128MB 0xd0 - 128MB single-sided + * 0x0001 256MB 0xcc 128MB dual-sided 128MB dual-sided + * 0x55c6 256MB 0xdd 128MB single-sided 128MB single-sided + * 0x4445 256MB 0xcd 128MB single-sided 128MB dual-sided + * 0x1145 256MB 0xdc 128MB dual-sided 128MB single-sided + * 0x3356 256MB 0x0f 256MB dual-sided - + * 0xcc56 256MB 0xf0 - 256MB dual-sided + * 0x0001 384MB 0xcf 256MB dual-sided 128MB dual-sided + * 0x0001 384MB 0xfc 128MB dual-sided 256MB dual-sided + * 0x1145 384MB 0xdf 256MB dual-sided 128MB single-sided + * 0x4445 384MB 0xfd 128MB single-sided 256MB dual-sided + * 0x0001 512MB 0xff 256MB dual-sided 256MB dual-sided * * See also: * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html @@ -402,7 +402,7 @@ void sdram_set_registers(void) reg8 &= 0x3f; /* Disable graphics (for now). */ #if CONFIG_VIDEO_MB if (CONFIG_VIDEO_MB == 512) - reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */ + reg8 |= (1 << 7); /* Enable graphics (512KB RAM). */ else if (CONFIG_VIDEO_MB == 1) reg8 |= (1 << 7) | (1 << 6); /* Enable graphics (1MB RAM). */ #endif diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index 40c32c9..e9f5415 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -18,30 +18,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ -#define GCC0 0x50 /* GMCH Control #0 (0xa072) */ -#define GCC1 0x52 /* GMCH Control #1 (0x0000) */ -#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */ -#define PAM0 0x59 /* Programable Attribute Map #0 (0x00) */ -#define PAM1 0x5a /* Programable Attribute Map #1 (0x00) */ -#define PAM2 0x5b /* Programable Attribute Map #2 (0x00) */ -#define PAM3 0x5c /* Programable Attribute Map #3 (0x00) */ -#define PAM4 0x5d /* Programable Attribute Map #4 (0x00) */ -#define PAM5 0x5e /* Programable Attribute Map #5 (0x00) */ -#define PAM6 0x5f /* Programable Attribute Map #6 (0x00) */ -#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */ -#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */ -#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */ -#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */ -#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */ -#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */ -#define DRT 0x78 /* DRAM Timing (0x00000010) */ -#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */ -#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */ -#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */ -#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */ -#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */ -#define SMRAM 0x90 /* System Management RAM Control (0x02) */ +#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ +#define GCC0 0x50 /* GMCH Control #0 (0xa072) */ +#define GCC1 0x52 /* GMCH Control #1 (0x0000) */ +#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */ +#define PAM0 0x59 /* Programable Attribute Map #0 (0x00) */ +#define PAM1 0x5a /* Programable Attribute Map #1 (0x00) */ +#define PAM2 0x5b /* Programable Attribute Map #2 (0x00) */ +#define PAM3 0x5c /* Programable Attribute Map #3 (0x00) */ +#define PAM4 0x5d /* Programable Attribute Map #4 (0x00) */ +#define PAM5 0x5e /* Programable Attribute Map #5 (0x00) */ +#define PAM6 0x5f /* Programable Attribute Map #6 (0x00) */ +#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */ +#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */ +#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */ +#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */ +#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */ +#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */ +#define DRT 0x78 /* DRAM Timing (0x00000010) */ +#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */ +#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */ +#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */ +#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */ +#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */ +#define SMRAM 0x90 /* System Management RAM Control (0x02) */ #define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */ #define ERRSTS 0x92 /* Error Status (0x0000) */ #define ERRCMD 0x94 /* Error Command (0x0000) */ diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c index e4d93cf..e6ca6b4 100644 --- a/src/northbridge/intel/i82830/smihandler.c +++ b/src/northbridge/intel/i82830/smihandler.c @@ -44,11 +44,11 @@ extern u32 mbi_len;
/* I830M */ #define SMRAM 0x90 -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
typedef struct { @@ -285,8 +285,8 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) }
#define SMI_IFC_SUCCESS 1 -#define SMI_IFC_FAILURE_GENERIC 0 -#define SMI_IFC_FAILURE_INVALID 2 +#define SMI_IFC_FAILURE_GENERIC 0 +#define SMI_IFC_FAILURE_INVALID 2 #define SMI_IFC_FAILURE_CRITICAL 4 #define SMI_IFC_FAILURE_NONCRITICAL 6
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 49bfa34..410ab42 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -39,7 +39,7 @@ static void vga_init(device_t dev) if (file) { if (ntohl(file->type) != CBFS_TYPE_MBI) { printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of" - "type %x\n", file->type, CBFS_TYPE_MBI); + "type %x\n", file->type, CBFS_TYPE_MBI); } else { mbi = (void *) CBFS_SUBHEADER(file); mbi_len = ntohl(file->len); @@ -91,16 +91,16 @@ static void vga_init(device_t dev)
static const struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .scan_bus = 0, - .enable = 0, - .ops_pci = 0, + .init = vga_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, + .ops = &vga_operations, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x3577, }; diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index f5c2890..1bd48c7 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,33 +1,33 @@ config NORTHBRIDGE_INTEL_I855 bool - select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_RAM_SETUP
choice - prompt "Onboard graphics" - default I855_VIDEO_MB_8MB - depends on NORTHBRIDGE_INTEL_I855 + prompt "Onboard graphics" + default I855_VIDEO_MB_8MB + depends on NORTHBRIDGE_INTEL_I855
config I855_VIDEO_MB_OFF - bool "Disabled, 0KB" + bool "Disabled, 0KB" config I855_VIDEO_MB_1MB - bool "Enabled, 1MB" + bool "Enabled, 1MB" config I855_VIDEO_MB_4MB - bool "Enabled, 4MB" + bool "Enabled, 4MB" config I855_VIDEO_MB_8MB - bool "Enabled, 8MB" + bool "Enabled, 8MB" config I855_VIDEO_MB_16MB - bool "Enabled, 16MB" + bool "Enabled, 16MB" config I855_VIDEO_MB_32MB - bool "Enabled, 32MB" + bool "Enabled, 32MB"
endchoice
config VIDEO_MB - int - default 0 if I855_VIDEO_MB_OFF - default 1 if I855_VIDEO_MB_1MB - default 4 if I855_VIDEO_MB_4MB - default 8 if I855_VIDEO_MB_8MB - default 16 if I855_VIDEO_MB_16MB - default 32 if I855_VIDEO_MB_32MB - depends on NORTHBRIDGE_INTEL_I855 + int + default 0 if I855_VIDEO_MB_OFF + default 1 if I855_VIDEO_MB_1MB + default 4 if I855_VIDEO_MB_4MB + default 8 if I855_VIDEO_MB_8MB + default 16 if I855_VIDEO_MB_16MB + default 32 if I855_VIDEO_MB_32MB + depends on NORTHBRIDGE_INTEL_I855 diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index 327f47d..c01eac4 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -123,31 +123,31 @@ static inline void dump_spd_registers(void)
static inline void dump_smbus_registers(void) { - int i; - print_debug("\n"); - for(i = 1; i < 0x80; i++) { - unsigned device; - device = i; - int j; - print_debug("smbus: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\n"); + int i; + print_debug("\n"); + for(i = 1; i < 0x80; i++) { + unsigned device; + device = i; + int j; + print_debug("smbus: "); + print_debug_hex8(device); + for(j = 0; j < 256; j++) { + int status; + unsigned char byte; + if ((j & 0xf) == 0) { + print_debug("\n"); + print_debug_hex8(j); + print_debug(": "); + } + status = smbus_read_byte(device, j); + if (status < 0) { + print_debug("bad device\n"); + break; + } + byte = status & 0xff; + print_debug_hex8(byte); + print_debug_char(' '); + } + print_debug("\n"); } } diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 8786fd7..5a7eefd 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -19,58 +19,58 @@ */
/* Host-Hub Interface Bridge */ -#define GMC 0x50 /* GMCH Misc. Control (0x0000) */ -#define GGC 0x52 /* GMCH Graphics Control (0x0030) */ -#define DAFC 0x54 /* Device and Function Control (0x0000) */ -#define FDHC 0x58 /* Fixed Dram Hole Control */ -#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */ -#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */ -#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */ -#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */ -#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */ -#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */ -#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */ -#define SMRAM 0x60 /* System Management RAM Control (0x02) */ +#define GMC 0x50 /* GMCH Misc. Control (0x0000) */ +#define GGC 0x52 /* GMCH Graphics Control (0x0030) */ +#define DAFC 0x54 /* Device and Function Control (0x0000) */ +#define FDHC 0x58 /* Fixed Dram Hole Control */ +#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */ +#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */ +#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */ +#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */ +#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */ +#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */ +#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */ +#define SMRAM 0x60 /* System Management RAM Control (0x02) */ #define ESMRAMC 0x61 /* Extended System Management RAM Control (0x38) */ -#define ERRSTS 0x62 /* Error Status (0x0000) */ -#define ERRCMD 0x64 /* Error Command (0x0000) */ -#define SMICMD 0x66 /* SMI Command (0x00) */ -#define SCICMD 0x67 /* SCI Command (0x00) */ -#define SHIC 0x74 /* Secondary Host Interface Control Register (0x00006010) */ -#define ACAPID 0xA0 /* AGP Capability Identifier (0x00200002) */ +#define ERRSTS 0x62 /* Error Status (0x0000) */ +#define ERRCMD 0x64 /* Error Command (0x0000) */ +#define SMICMD 0x66 /* SMI Command (0x00) */ +#define SCICMD 0x67 /* SCI Command (0x00) */ +#define SHIC 0x74 /* Secondary Host Interface Control Register (0x00006010) */ +#define ACAPID 0xA0 /* AGP Capability Identifier (0x00200002) */ #define AGPSTAT 0xA4 /* AGP Status Register (0x1f000217) */ -#define AGPCMD 0xA8 /* AGP Command (0x0000) */ +#define AGPCMD 0xA8 /* AGP Command (0x0000) */ #define AGPCTRL 0xB0 /* AGP Control (0x0000) */ -#define AFT 0xB2 /* AGP Functional Test (0xe9f0) */ +#define AFT 0xB2 /* AGP Functional Test (0xe9f0) */ #define ATTBASE 0xB8 /* Aperture Translation Table Base (0x00000000) */ -#define AMTT 0xBC /* AGP Interface Multi Transaction Timer (0x00) */ -#define LPTT 0xBD /* Low Priority Transaction Timer (0x00) */ -#define HEM 0xF0 /* Host Error Control/Status/Obs (0x00000000) */ +#define AMTT 0xBC /* AGP Interface Multi Transaction Timer (0x00) */ +#define LPTT 0xBD /* Low Priority Transaction Timer (0x00) */ +#define HEM 0xF0 /* Host Error Control/Status/Obs (0x00000000) */
/* Main Memory Control */ -#define DRB 0x40 /* DRAM Row 0-3 Boundary (0x00000000) */ -#define DRA 0x50 /* DRAM Row 0-3 Attribute (0x7777) */ -#define DRT 0x60 /* DRAM Timing (0x18004425) */ -#define PWRMG 0x68 /* DRAM Controller Power Management Control (0x00000000) */ -#define DRC 0x70 /* DRAM Controller Mode (0x00000081) */ -#define DTC 0xA0 /* DRAM Throttling Control (0x00000000) */ +#define DRB 0x40 /* DRAM Row 0-3 Boundary (0x00000000) */ +#define DRA 0x50 /* DRAM Row 0-3 Attribute (0x7777) */ +#define DRT 0x60 /* DRAM Timing (0x18004425) */ +#define PWRMG 0x68 /* DRAM Controller Power Management Control (0x00000000) */ +#define DRC 0x70 /* DRAM Controller Mode (0x00000081) */ +#define DTC 0xA0 /* DRAM Throttling Control (0x00000000) */
-#define DRT_CAS_MASK (3 << 5) -#define DRT_CAS_2_0 (1 << 5) -#define DRT_CAS_2_5 (0 << 5) +#define DRT_CAS_MASK (3 << 5) +#define DRT_CAS_2_0 (1 << 5) +#define DRT_CAS_2_5 (0 << 5)
-#define DRT_TRP_MASK 3 -#define DRT_TRP_4 0 -#define DRT_TRP_3 1 -#define DRT_TRP_2 2 +#define DRT_TRP_MASK 3 +#define DRT_TRP_4 0 +#define DRT_TRP_3 1 +#define DRT_TRP_2 2
-#define DRT_RCD_MASK (3 << 2) -#define DRT_RCD_4 (0 << 2) -#define DRT_RCD_3 (1 << 2) -#define DRT_RCD_2 (2 << 2) +#define DRT_RCD_MASK (3 << 2) +#define DRT_RCD_4 (0 << 2) +#define DRT_RCD_3 (1 << 2) +#define DRT_RCD_2 (2 << 2)
#define DRT_TRAS_MIN_MASK (3 << 9) -#define DRT_TRAS_MIN_8 (0 << 9) -#define DRT_TRAS_MIN_7 (1 << 9) -#define DRT_TRAS_MIN_6 (2 << 9) -#define DRT_TRAS_MIN_5 (3 << 9) +#define DRT_TRAS_MIN_8 (0 << 9) +#define DRT_TRAS_MIN_7 (1 << 9) +#define DRT_TRAS_MIN_6 (2 << 9) +#define DRT_TRAS_MIN_5 (3 << 9) diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 5c0379c..957b726 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -34,33 +34,33 @@
static void northbridge_init(device_t dev) { - printk(BIOS_SPEW, "Northbridge init\n"); + printk(BIOS_SPEW, "Northbridge init\n"); }
static struct device_operations northbridge_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x3580, + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x3580, };
static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
- printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); @@ -111,17 +111,17 @@ static void pci_domain_set_resources(device_t dev) }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -129,25 +129,25 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } }
struct chip_operations northbridge_intel_i855_ops = { - CHIP_NAME("Intel 855 Northbridge") + CHIP_NAME("Intel 855 Northbridge") .enable_dev = enable_dev, }; diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 919c653..7582b9d 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -33,8 +33,8 @@ Macros and definitions:
/* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP -#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) -#define DUMPNORTH() dump_pci_device(NORTHBRIDGE_MMC) +#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) +#define DUMPNORTH() dump_pci_device(NORTHBRIDGE_MMC) #else #define PRINTK_DEBUG(x...) #define DUMPNORTH() @@ -96,7 +96,7 @@ static const uint32_t refresh_rate_map[] = { * [2] == 7.8 us -> 7.8 us * [3] == 31.3 us -> 15.6 us * [4] == 62.5 us -> 15.6 us - * [5] == 125 us -> 15.6 us + * [5] == 125 us -> 15.6 us */ 1, 7, 2, 1, 1, 1 }; @@ -229,7 +229,7 @@ static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address) * Calculate the log base 2 size in bits of both DIMM sides. * * log2(# bits) = (# columns) + log2(data width) + - * (# rows) + log2(banks per SDRAM) + * (# rows) + log2(banks per SDRAM) * * Note that it might be easier to use SPD byte 31 here, it has the DIMM size * as a multiple of 4MB. The way we do it now we can size both sides of an @@ -317,7 +317,7 @@ static uint8_t spd_get_supported_dimms(void) // Validate DIMM page size // The i855 only supports page sizes of 4, 8, 16 KB per channel // NOTE: 4 KB = 32 Kb = 2^15 - // 16 KB = 128 Kb = 2^17 + // 16 KB = 128 Kb = 2^17
if ((page_size.side1 < 15) || (page_size.side1 > 17)) { PRINTK_DEBUG("Skipping DIMM with unsupported page size: %d\n", page_size.side1); @@ -372,32 +372,32 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32); pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
- // RAM_COMMAND_NORMAL is an exception. - // It affects only the memory controller and does not need to be "sent" to the DIMMs. + // RAM_COMMAND_NORMAL is an exception. + // It affects only the memory controller and does not need to be "sent" to the DIMMs.
- if (command != RAM_COMMAND_NORMAL) { + if (command != RAM_COMMAND_NORMAL) {
- // Send the command to all DIMMs by accessing a memory location within each - // NOTE: for mode select commands, some of the location address bits - // are part of the command + // Send the command to all DIMMs by accessing a memory location within each + // NOTE: for mode select commands, some of the location address bits + // are part of the command
- // Map JEDEC mode bits to i855 - if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { + // Map JEDEC mode bits to i855 + if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) { /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9)); - } + }
- for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { - uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); - if (dimm_end_32M_multiple > dimm_start_32M_multiple) { + for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { + uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); + if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
- uint32_t dimm_start_address = dimm_start_32M_multiple << 25; + uint32_t dimm_start_address = dimm_start_32M_multiple << 25; PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits); - read32(dimm_start_address + i855_mode_bits); + read32(dimm_start_address + i855_mode_bits);
- // Set the start of the next DIMM - dimm_start_32M_multiple = dimm_end_32M_multiple; - } + // Set the start of the next DIMM + dimm_start_32M_multiple = dimm_end_32M_multiple; + } } } } @@ -737,15 +737,15 @@ static void spd_set_dram_timing(uint8_t dimm_mask) // i855 supports only 5, 6, 7 or 8 clocks for tRAS // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns, 8 clocks ~= 60.1 ns if (slowest_active_to_precharge_delay > 60) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 52) - dram_timing |= DRT_TRAS_MIN_8; // 46-52 ns: 7 clocks + dram_timing |= DRT_TRAS_MIN_8; // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 45) - dram_timing |= DRT_TRAS_MIN_7; // 46-52 ns: 7 clocks + dram_timing |= DRT_TRAS_MIN_7; // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) - dram_timing |= DRT_TRAS_MIN_6; // 38-45 ns: 6 clocks + dram_timing |= DRT_TRAS_MIN_6; // 38-45 ns: 6 clocks else - dram_timing |= DRT_TRAS_MIN_5; // < 38 ns: 5 clocks + dram_timing |= DRT_TRAS_MIN_5; // < 38 ns: 5 clocks
/* FIXME: guess work starts here... * @@ -827,7 +827,7 @@ static void spd_set_dram_throttle_control(void)
/* DDR SDRAM Throttle Mode (TMODE): * 0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO- - * DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT + * DIMM Thermal Sensor is Tripped DDR SDRAM Throttling begins based on the setting in RTT */ dtc_reg |= (3 << 28);
diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h index 3d5176b..a37892c 100644 --- a/src/northbridge/intel/i855/raminit.h +++ b/src/northbridge/intel/i855/raminit.h @@ -22,8 +22,8 @@ #define NORTHBRIDGE_INTEL_I855_RAMINIT_H
/* i855 Northbridge PCI devices */ -#define NORTHBRIDGE PCI_DEV(0, 0, 0) -#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1) +#define NORTHBRIDGE PCI_DEV(0, 0, 0) +#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1)
/* The i855 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index e47f762..80f79d9 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -83,21 +83,21 @@ void dump_pci_devices(void)
void dump_spd_registers(void) { - unsigned device; - device = DIMM0; - while(device <= DIMM3) { - int status = 0; - int i; - printk(BIOS_DEBUG, "\ndimm %02x", device); + unsigned device; + device = DIMM0; + while(device <= DIMM3) { + int status = 0; + int i; + printk(BIOS_DEBUG, "\ndimm %02x", device);
- for(i = 0; (i < 256) ; i++) { - if ((i % 16) == 0) { + for(i = 0; (i < 256) ; i++) { + if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); - } + } status = smbus_read_byte(device, i); - if (status < 0) { - printk(BIOS_DEBUG, "bad device: %02x\n", -status); - break; + if (status < 0) { + printk(BIOS_DEBUG, "bad device: %02x\n", -status); + break; } printk(BIOS_DEBUG, "%02x ", status); } @@ -108,13 +108,13 @@ void dump_spd_registers(void)
void dump_mem(unsigned start, unsigned end) { - unsigned i; + unsigned i; print_debug("dump_mem:"); - for(i=start;i<end;i++) { + for(i=start;i<end;i++) { if((i & 0xf)==0) { printk(BIOS_DEBUG, "\n%08x:", i); } printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); - } - print_debug("\n"); + } + print_debug("\n"); } diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index deda2fa..5fd8cfc 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -112,7 +112,7 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = gma_set_subsystem, };
static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 922a819..7100537 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -179,10 +179,10 @@ static void pci_domain_set_resources(device_t dev) */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, };
@@ -254,22 +254,22 @@ static void northbridge_init(struct device *dev) #endif
static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = intel_set_subsystem, };
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, + .init = northbridge_init, #endif - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27a0, }; @@ -285,10 +285,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 512d8e9..03ecf3e 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -75,7 +75,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command) if (command == RAM_COMMAND_NORMAL) reg32 |= RAM_INITIALIZATION_COMPLETE;
- PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); + PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);
MCHBAR32(DCC) = reg32; /* This is the actual magic */
@@ -86,7 +86,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command)
static void ram_read32(u32 offset) { - PRINTK_DEBUG(" ram read: %08x\n", offset); + PRINTK_DEBUG(" ram read: %08x\n", offset);
read32(offset); } @@ -574,7 +574,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { - PRINTK_DEBUG(": OK\n"); + PRINTK_DEBUG(": OK\n"); break; }
@@ -869,7 +869,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) continue;
if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -988,63 +988,63 @@ enum { static const u8 dual_channel_slew_group_lookup[] = { DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, - DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, - DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, + DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
- DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, - DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, + DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, - DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, - DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, + DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC,
- NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, - NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, - NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, - NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710 + NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710 };
static const u8 single_channel_slew_group_lookup[] = { DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
- DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, + DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC,
DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, - DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, + DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC,
- DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, - DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, - DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, - DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 + DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, + DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, + DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 };
static const u32 *slew_group_lookup(int dual_channel, int index) @@ -1912,7 +1912,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo) if (sdram_capabilities_interleave() && ( ( sysinfo->banksize[0] + sysinfo->banksize[1] + sysinfo->banksize[2] + sysinfo->banksize[3] ) == - ( sysinfo->banksize[4] + sysinfo->banksize[5] + + ( sysinfo->banksize[4] + sysinfo->banksize[5] + sysinfo->banksize[6] + sysinfo->banksize[7] ) ) ) { /* Both channels equipped with DIMMs of the same size */ sysinfo->interleaved = 1; diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c index 15829c5..5b9cd9c 100644 --- a/src/northbridge/intel/i945/rcven.c +++ b/src/northbridge/intel/i945/rcven.c @@ -67,7 +67,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse) { u32 reg32;
- printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse); + printk(BIOS_SPEW, " set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
reg32 = MCHBAR32(C0DRT1 + channel_offset); reg32 &= 0xf0ffffff; @@ -216,7 +216,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine, }
static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine, - struct sys_info *sysinfo) + struct sys_info *sysinfo) {
int counter; @@ -253,7 +253,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine, *mediumcoarse += 2; if (*mediumcoarse <= 0x40) { set_receive_enable(channel_offset, *mediumcoarse & 3, - *mediumcoarse >> 2); + *mediumcoarse >> 2); continue; }
@@ -281,7 +281,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine, */
static int receive_enable_autoconfig(int channel_offset, - struct sys_info *sysinfo) + struct sys_info *sysinfo) { u8 mediumcoarse; u8 fine; diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index df6cc1a..874b23d 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -41,7 +41,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) /* Quickpath bus is not in standard coreboot device tree, so read register directly. */ pciexbar_reg = read32(DEFAULT_PCIEXBAR - | (QUICKPATH_BUS << 20) | 0x1050); + | (QUICKPATH_BUS << 20) | 0x1050);
// MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) @@ -51,19 +51,19 @@ unsigned long acpi_fill_mcfg(unsigned long current) case 0: // 256MB pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); + (1 << 28)); max_buses = 256; break; case 1: // 128M pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); + (1 << 28) | (1 << 27)); max_buses = 128; break; case 2: // 64M pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); + (1 << 28) | (1 << 27) | (1 << 26)); max_buses = 64; break; default: // RSVD @@ -74,7 +74,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + pciexbar, 0x0, 0x0, max_buses - 1);
return current; } @@ -89,11 +89,11 @@ static void *get_intel_vbios(void)
optionrom_header_t *oprom = (optionrom_header_t *) vbios; optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios + - oprom->pcir_offset); + oprom->pcir_offset);
printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n", - oprom->signature, pcir->vendor, pcir->classcode[0], - pcir->classcode[1], pcir->classcode[2]); + oprom->signature, pcir->vendor, pcir->classcode[0], + pcir->classcode[1], pcir->classcode[2]);
if ((oprom->signature == OPROM_SIGNATURE) && (pcir->vendor == PCI_VENDOR_ID_INTEL) && @@ -124,7 +124,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ? - vbt->hdr_vbt_size : 7168); + vbt->hdr_vbt_size : 7168);
return 0; } @@ -140,7 +140,7 @@ int init_igd_opregion(igd_opregion_t * opregion) // FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(IGD_OPREGION_SIGNATURE)); + sizeof(IGD_OPREGION_SIGNATURE));
/* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024; diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index d85dbe8..0e634e6 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -106,7 +106,7 @@ Device (MCHC) * * Format of _PSS: * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } + * Package (6) { freq, power, tlat, blat, control, status } * } */ External (_PR.CPU0._PSS) @@ -118,7 +118,7 @@ Device (MCHC) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/nehalem/acpi/igd.asl b/src/northbridge/intel/nehalem/acpi/igd.asl index 7d3d4db..f3cb1bc 100644 --- a/src/northbridge/intel/nehalem/acpi/igd.asl +++ b/src/northbridge/intel/nehalem/acpi/igd.asl @@ -24,21 +24,21 @@ Device (GFX0) Name (_ADR, 0x00020000)
OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) - Field (GFXC, DWordAcc, NoLock, Preserve) - { - Offset (0x10), + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), BAR0, 64 - } + }
- OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) Field (GFRG, DWordAcc, NoLock, Preserve) - { + { Offset (0x48254), BCLV, 16, - Offset (0xc8250), - CR1, 32, + Offset (0xc8250), + CR1, 32, CR2, 32 - } + }
/* Display Output Switching */ Method (_DOS, 1) diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index 3164035..718793d 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -30,9 +30,9 @@ struct northbridge_intel_nehalem_config { u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 31068d1..7fdee1e 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -415,17 +415,17 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (tdp <= 17) { /* <=17W ULV */ printk(BIOS_DEBUG, "IVB GT2 17W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ printk(BIOS_DEBUG, "IVB GT2 25W-35W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { /* All others */ printk(BIOS_DEBUG, "IVB GT2 35W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index e81ac3f..f04cc8e 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -117,7 +117,7 @@ typedef struct {
typedef struct { unsigned int card_type; /* 0x0: unpopulated, - 0xa - 0xf: raw card type A - F */ + 0xa - 0xf: raw card type A - F */ chip_width_t chip_width; chip_capacity_t chip_capacity; unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ @@ -607,8 +607,8 @@ void report_platform_info(void); #endif /* !__SMM__ */
-#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
struct mrc_data_container { u32 mrc_signature; // "MRCD" diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..59c0176 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -46,7 +46,7 @@ int bridge_silicon_revision(void) uint8_t stepping = cpuid_eax(1) & 0xf; uint8_t bridge_id = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), - PCI_DEVICE_ID) & 0xf0; + PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } return bridge_revision_id; @@ -86,14 +86,14 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); + (0xc0000 >> 10) - legacy_hole_base_k); reserved_ram_resource(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); + CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif }
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 19af3bb..93546bf 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -67,13 +67,13 @@ typedef u32 device_t; #define HECIBAR 0x10
#define FOR_ALL_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ + for (channel = 0; channel < NUM_CHANNELS; channel++) \ + for (slot = 0; slot < NUM_SLOTS; slot++) \ for (rank = 0; rank < NUM_RANKS; rank++)
-#define FOR_POPULATED_RANKS \ - for (channel = 0; channel < NUM_CHANNELS; channel++) \ - for (slot = 0; slot < NUM_SLOTS; slot++) \ +#define FOR_POPULATED_RANKS \ + for (channel = 0; channel < NUM_CHANNELS; channel++) \ + for (slot = 0; slot < NUM_SLOTS; slot++) \ for (rank = 0; rank < NUM_RANKS; rank++) \ if (info->populated_ranks[channel][slot][rank])
@@ -161,9 +161,9 @@ static void read128(u32 addr, u64 * out) u128 ret; u128 stor; asm volatile ("movdqu %%xmm0, %0\n" - "movdqa (%2), %%xmm0\n" - "movdqu %%xmm0, %1\n" - "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr)); + "movdqa (%2), %%xmm0\n" + "movdqu %%xmm0, %1\n" + "movdqu %0, %%xmm0":"+m" (stor), "=m"(ret):"r"(addr)); out[0] = ret.lo; out[1] = ret.hi; } @@ -176,7 +176,7 @@ static void write_1d0(u32 val, u16 addr, int bits, int flag) write_mchbar32(0x1d0, 0); while (read_mchbar32(0x1d0) & 0x800000) ; write_mchbar32(0x1d4, - (val & ((1 << bits) - 1)) | (2 << bits) | (flag << + (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x1d0, 0x40000000 | addr); while (read_mchbar32(0x1d0) & 0x800000) ; @@ -189,8 +189,8 @@ static u16 read_1d0(u16 addr, int split) write_mchbar32(0x1d0, 0); while (read_mchbar32(0x1d0) & 0x800000) ; write_mchbar32(0x1d0, - 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) + - 0x361 - addr)); + 0x80000000 | (((read_mchbar8(0x246) >> 2) & 3) + + 0x361 - addr)); while (read_mchbar32(0x1d0) & 0x800000) ; val = read_mchbar32(0x1d8); write_1d0(0, 0x33d, 0, 0); @@ -284,8 +284,8 @@ read_500(struct raminfo *info, int channel, u16 addr, int split) write_mchbar32(0x500 + (channel << 10), 0); while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; write_mchbar32(0x500 + (channel << 10), - 0x80000000 | - (((read_mchbar8(0x246 + (channel << 10)) >> 2) & + 0x80000000 | + (((read_mchbar8(0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; val = read_mchbar32(0x508 + (channel << 10)); @@ -304,7 +304,7 @@ write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, write_mchbar32(0x500 + (channel << 10), 0); while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; write_mchbar32(0x504 + (channel << 10), - (val & ((1 << bits) - 1)) | (2 << bits) | (flag << + (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); write_mchbar32(0x500 + (channel << 10), 0x40000000 | addr); while (read_mchbar32(0x500 + (channel << 10)) & 0x800000) ; @@ -383,10 +383,10 @@ static u32 get_580(int channel, u8 addr) write_mchbar8(0x5ff, 0x80); /* OK */ write_mchbar32(0x580 + (channel << 10), 0x8493c012 | addr); write_mchbar8(0x580 + (channel << 10), - read_mchbar8(0x580 + (channel << 10)) | 1); + read_mchbar8(0x580 + (channel << 10)) | 1); while (!((ret = read_mchbar32(0x580 + (channel << 10))) & 0x10000)) ; write_mchbar8(0x580 + (channel << 10), - read_mchbar8(0x580 + (channel << 10)) & ~1); + read_mchbar8(0x580 + (channel << 10)) & ~1); return ret; }
@@ -408,7 +408,7 @@ static void seq9(struct raminfo *info, int channel, int slot, int rank) for (lane = 0; lane < 8; lane++) write_500(info, channel, info->training.lane_timings[i + - 1][channel][slot] + 1][channel][slot] [rank][lane], get_timing_register_addr(lane, i + 1, slot, @@ -426,7 +426,7 @@ static void seq9(struct raminfo *info, int channel, int slot, int rank) for (lane = 0; lane < 8; lane++) write_500(info, channel, info->training.lane_timings[i + - 1][channel][slot] + 1][channel][slot] [rank][lane], get_timing_register_addr(lane, i + 1, slot, @@ -440,10 +440,10 @@ static void seq9(struct raminfo *info, int channel, int slot, int rank) write_mchbar8(0x5ff, 0x80); /* OK */ write_1d0(0x2, 0x142, 3, 1); for (lane = 0; lane < 8; lane++) { - // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); + // printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[2][channel][slot][rank][lane] = read_500(info, channel, - get_timing_register_addr(lane, 2, slot, rank), 9); + get_timing_register_addr(lane, 2, slot, rank), 9); //printk (BIOS_ERR, "after: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]); info->training.lane_timings[3][channel][slot][rank][lane] = info->training.lane_timings[2][channel][slot][rank][lane] + @@ -521,22 +521,22 @@ static void set_334(int zero)
for (k = 0; k < 2; k++) { write_mchbar32(0x138 + 8 * k, - (channel << 26) | (j << 24)); + (channel << 26) | (j << 24)); gav(vd8[1][(channel << 3) | (j << 1) | k] = - read_mchbar32(0x138 + 8 * k)); + read_mchbar32(0x138 + 8 * k)); gav(vd8[0][(channel << 3) | (j << 1) | k] = - read_mchbar32(0x13c + 8 * k)); + read_mchbar32(0x13c + 8 * k)); }
write_mchbar32(0x334 + (channel << 10) + (j * 0x44), - zero ? 0 : val3[j]); + zero ? 0 : val3[j]); write_mchbar32(0x32c + (channel << 10) + (j * 0x44), - zero ? 0 : (0x18191819 & lmask)); + zero ? 0 : (0x18191819 & lmask)); write_mchbar16(0x34a + (channel << 10) + (j * 0x44), c); write_mchbar32(0x33c + (channel << 10) + (j * 0x44), - zero ? 0 : (a & lmask)); + zero ? 0 : (a & lmask)); write_mchbar32(0x344 + (channel << 10) + (j * 0x44), - zero ? 0 : (a & lmask)); + zero ? 0 : (a & lmask)); } }
@@ -607,12 +607,12 @@ static void calculate_timings(struct raminfo *info) for (slot = 0; slot < NUM_SLOTS; slot++) if (info->populated_ranks[channel][slot][0]) supported_cas_latencies &= - 2 * - (info-> - spd[channel][slot][CAS_LATENCIES_LSB] | - (info-> - spd[channel][slot][CAS_LATENCIES_MSB] << - 8)); + 2 * + (info-> + spd[channel][slot][CAS_LATENCIES_LSB] | + (info-> + spd[channel][slot][CAS_LATENCIES_MSB] << + 8));
max_clock_index = min(3, info->max_supported_clock_speed_index);
@@ -624,16 +624,16 @@ static void calculate_timings(struct raminfo *info) if (info->populated_ranks[channel][slot][0]) { unsigned timebase; timebase = - 1000 * - info-> - spd[channel][slot][TIMEBASE_DIVIDEND] / - info->spd[channel][slot][TIMEBASE_DIVISOR]; + 1000 * + info-> + spd[channel][slot][TIMEBASE_DIVIDEND] / + info->spd[channel][slot][TIMEBASE_DIVISOR]; cycletime = - max(cycletime, + max(cycletime, timebase * info->spd[channel][slot][CYCLETIME]); cas_latency_time = - max(cas_latency_time, + max(cas_latency_time, timebase * info-> spd[channel][slot][CAS_LATENCY_TIME]); @@ -678,8 +678,8 @@ static void program_base_timings(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) for (slot = 0; slot < NUM_SLOTS; slot++) if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) extended_silicon_revision = 4;
for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -695,54 +695,54 @@ static void program_base_timings(struct raminfo *info)
card_timing = 0; if ((info-> - spd[channel][slot][MODULE_TYPE] & - 0xF) == 3) { + spd[channel][slot][MODULE_TYPE] & + 0xF) == 3) { int reference_card; reference_card = - info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1f; + info-> + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1f; if (reference_card == 3) card_timing = - u16_ffd1188[0][lane] - [info-> - clock_speed_index]; + u16_ffd1188[0][lane] + [info-> + clock_speed_index]; if (reference_card == 5) card_timing = - u16_ffd1188[1][lane] - [info-> - clock_speed_index]; + u16_ffd1188[1][lane] + [info-> + clock_speed_index]; }
info->training. - lane_timings[0][channel][slot][rank] - [lane] = - u8_FFFD1218[info-> + lane_timings[0][channel][slot][rank] + [lane] = + u8_FFFD1218[info-> clock_speed_index]; info->training. - lane_timings[1][channel][slot][rank] - [lane] = 256; + lane_timings[1][channel][slot][rank] + [lane] = 256;
for (tm_reg = 2; tm_reg < 4; tm_reg++) info->training. - lane_timings[tm_reg] - [channel][slot][rank][lane] - = - u8_FFFD1240[channel] - [extended_silicon_revision] - [lane][2 * slot + - rank][info-> + lane_timings[tm_reg] + [channel][slot][rank][lane] + = + u8_FFFD1240[channel] + [extended_silicon_revision] + [lane][2 * slot + + rank][info-> clock_speed_index] - + info->max4048[channel] - + - u8_FFFD0C78[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][slot] - [rank][info-> - clock_speed_index] - + card_timing; + + info->max4048[channel] + + + u8_FFFD0C78[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][slot] + [rank][info-> + clock_speed_index] + + card_timing; for (tm_reg = 0; tm_reg < 4; tm_reg++) write_500(info, channel, info->training. @@ -751,49 +751,49 @@ static void program_base_timings(struct raminfo *info) [lane], get_timing_register_addr (lane, tm_reg, slot, - rank), 9, 0); + rank), 9, 0); }
card_timing_2 = 0; if (!(extended_silicon_revision != 4 - || (info-> + || (info-> populated_ranks_mask[channel] & 5) == - 5)) { + 5)) { if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 3) + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 3) card_timing_2 = - u16_FFFE0EB8[0][info-> + u16_FFFE0EB8[0][info-> clock_speed_index]; if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & 0x1F) - == 5) + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & 0x1F) + == 5) card_timing_2 = - u16_FFFE0EB8[1][info-> + u16_FFFE0EB8[1][info-> clock_speed_index]; }
for (i = 0; i < 3; i++) write_500(info, channel, (card_timing_2 + - info->max4048[channel] - + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> + info->max4048[channel] + + + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> clock_speed_index]), u16_fffd0c50[i][slot][rank], 8, 1); write_500(info, channel, (info->max4048[channel] + - u8_FFFD0C78[channel] - [extended_silicon_revision][info-> + u8_FFFD0C78[channel] + [extended_silicon_revision][info-> mode4030 [channel]] - [slot][rank][info-> + [slot][rank][info-> clock_speed_index]), u16_fffd0c70[slot][rank], 7, 1); } @@ -806,8 +806,8 @@ static void program_base_timings(struct raminfo *info) + u8_FFFD17E0[channel] [extended_silicon_revision][info-> - mode4030 - [channel]][info-> + mode4030 + [channel]][info-> clock_speed_index]), u16_fffd0c68[i], 8, 1); } @@ -873,8 +873,8 @@ static void compute_derived_timings(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) for (slot = 0; slot < NUM_SLOTS; slot++) if ((info-> - spd[channel][slot][MODULE_TYPE] & 0xF) == - 3) + spd[channel][slot][MODULE_TYPE] & 0xF) == + 3) extended_silicon_revision = 4; if (info->board_lane_delay[7] < 5) info->board_lane_delay[7] = 5; @@ -887,13 +887,13 @@ static void compute_derived_timings(struct raminfo *info) if (info->revision < 8) info->revision_flag_1 = 0; if (info->revision >= 8 && (info->silicon_revision == 0 - || info->silicon_revision == 1)) + || info->silicon_revision == 1)) some_delay_2_ps = 735; else some_delay_2_ps = 750;
if (info->revision >= 0x10 && (info->silicon_revision == 0 - || info->silicon_revision == 1)) + || info->silicon_revision == 1)) some_delay_1_ps = 3929; else some_delay_1_ps = 3490; @@ -943,9 +943,9 @@ static void compute_derived_timings(struct raminfo *info) info->max_slots_used_in_channel = 1; for (channel = 0; channel < 2; channel++) write_mchbar32(0x244 + (channel << 10), - ((info->revision < 8) ? 1 : 0x200) - | ((2 - info->max_slots_used_in_channel) << 17) | - (channel << 21) | (info-> + ((info->revision < 8) ? 1 : 0x200) + | ((2 - info->max_slots_used_in_channel) << 17) | + (channel << 21) | (info-> some_delay_1_cycle_floor << 18) | 0x9510); if (info->max_slots_used_in_channel == 1) { @@ -954,7 +954,7 @@ static void compute_derived_timings(struct raminfo *info) } else { info->mode4030[0] = ((count_ranks_in_channel(info, 0) == 1) || (count_ranks_in_channel(info, 0) == 2)) ? 2 : 3; /* 2 if 1 or 2 ranks */ info->mode4030[1] = ((count_ranks_in_channel(info, 1) == 1) - || (count_ranks_in_channel(info, 1) == + || (count_ranks_in_channel(info, 1) == 2)) ? 2 : 3; } for (channel = 0; channel < NUM_CHANNELS; channel++) { @@ -976,16 +976,16 @@ static void compute_derived_timings(struct raminfo *info) int unk1; if (info->revision < 8) unk1 = - u8_FFFD1891[0][channel][info-> - clock_speed_index] - [i]; + u8_FFFD1891[0][channel][info-> + clock_speed_index] + [i]; else if (! (info->revision >= 0x10 || info->revision_flag_1)) unk1 = - u8_FFFD1891[1][channel][info-> - clock_speed_index] - [i]; + u8_FFFD1891[1][channel][info-> + clock_speed_index] + [i]; else unk1 = 0; for (slot = 0; slot < NUM_SLOTS; slot++) @@ -994,30 +994,30 @@ static void compute_derived_timings(struct raminfo *info) int b = 0;
if (!info-> - populated_ranks[channel][slot] - [rank]) + populated_ranks[channel][slot] + [rank]) continue; if (extended_silicon_revision == 4 - && (info-> + && (info-> populated_ranks_mask[channel] & 5) != 5) { if ((info-> - spd[channel][slot] - [REFERENCE_RAW_CARD_USED] & - 0x1F) == 3) { + spd[channel][slot] + [REFERENCE_RAW_CARD_USED] & + 0x1F) == 3) { a = u16_ffd1178[0] - [info-> - clock_speed_index]; + [info-> + clock_speed_index]; b = u16_fe0eb8[0][info-> clock_speed_index]; } else - if ((info-> + if ((info-> spd[channel][slot] [REFERENCE_RAW_CARD_USED] & 0x1F) == 5) { a = u16_ffd1178[1] - [info-> - clock_speed_index]; + [info-> + clock_speed_index]; b = u16_fe0eb8[1][info-> clock_speed_index]; } @@ -1031,24 +1031,24 @@ static void compute_derived_timings(struct raminfo *info) { int t; t = b + - u8_FFFD0EF8[channel] - [extended_silicon_revision] - [info-> - mode4030[channel]][info-> + u8_FFFD0EF8[channel] + [extended_silicon_revision] + [info-> + mode4030[channel]][info-> clock_speed_index]; if (unk1 >= t) max_of_unk = - max(max_of_unk, + max(max_of_unk, unk1 - t); } } { int t = - u8_FFFD17E0[channel] - [extended_silicon_revision][info-> + u8_FFFD17E0[channel] + [extended_silicon_revision][info-> mode4030 [channel]] - [info->clock_speed_index] + min_of_unk_2; + [info->clock_speed_index] + min_of_unk_2; if (unk1 >= t) max_of_unk = max(max_of_unk, unk1 - t); } @@ -1060,14 +1060,14 @@ static void compute_derived_timings(struct raminfo *info) }
static void jedec_read(struct raminfo *info, - int channel, int slot, int rank, - int total_rank, u8 addr3, unsigned int value) + int channel, int slot, int rank, + int total_rank, u8 addr3, unsigned int value) { /* Handle mirrored mapping. */ if ((rank & 1) && (info->spd[channel][slot][RANK1_ADDRESS_MAPPING] & 1)) addr3 = (addr3 & 0xCF) | ((addr3 & 0x10) << 1) | ((addr3 >> 1) & - 0x10); + 0x10); write_mchbar8(0x271, addr3 | (read_mchbar8(0x271) & 0xC1)); write_mchbar8(0x671, addr3 | (read_mchbar8(0x671) & 0xC1));
@@ -1132,9 +1132,9 @@ static void jedec_init(struct raminfo *info)
dll_on = ((info->silicon_revision != 2 && info->silicon_revision != 3) || (info->populated_ranks[0][0][0] - && info->populated_ranks[0][1][0]) + && info->populated_ranks[0][1][0]) || (info->populated_ranks[1][0][0] - && info->populated_ranks[1][1][0])); + && info->populated_ranks[1][1][0]));
total_rank = 0;
@@ -1171,25 +1171,25 @@ static void jedec_init(struct raminfo *info) for (rank = 0; rank < NUM_RANKS; rank++) if (info->populated_ranks[channel][slot][rank]) { jedec_read(info, channel, slot, rank, - total_rank, 0x28, - rtt_wr | (info-> - clock_speed_index - << 3) - | (auto_self_refresh << 6) | - (self_refresh_temperature << - 7)); + total_rank, 0x28, + rtt_wr | (info-> + clock_speed_index + << 3) + | (auto_self_refresh << 6) | + (self_refresh_temperature << + 7)); jedec_read(info, channel, slot, rank, - total_rank, 0x38, 0); + total_rank, 0x38, 0); jedec_read(info, channel, slot, rank, - total_rank, 0x18, - rtt | MR1_ODS34OHM); + total_rank, 0x18, + rtt | MR1_ODS34OHM); jedec_read(info, channel, slot, rank, - total_rank, 6, - (dll_on << 12) | - (write_recovery << 9) - | ((info->cas_latency - 4) << - 4) | MR0_BT_INTERLEAVED | - MR0_DLL_RESET_ON); + total_rank, 6, + (dll_on << 12) | + (write_recovery << 9) + | ((info->cas_latency - 4) << + 4) | MR0_BT_INTERLEAVED | + MR0_DLL_RESET_ON); total_rank++; } } @@ -1205,17 +1205,17 @@ static void program_modules_memory_map(struct raminfo *info, int pre_jedec) if (info->populated_ranks[channel][slot][rank]) { total_mb[channel] += pre_jedec ? 256 : (256 << info-> - density[channel][slot] >> info-> - is_x16_module[channel][slot]); + density[channel][slot] >> info-> + is_x16_module[channel][slot]); write_mchbar8(0x208 + rank + 2 * slot + (channel << 10), - (pre_jedec ? (1 | ((1 + 1) << 1)) - : (info-> + (pre_jedec ? (1 | ((1 + 1) << 1)) + : (info-> is_x16_module[channel][slot] | ((info->density[channel][slot] + - 1) << 1))) | 0x80); + 1) << 1))) | 0x80); } write_mchbar16(0x200 + (channel << 10) + 4 * slot + 2 * rank, - total_mb[channel] >> 6); + total_mb[channel] >> 6); }
info->total_memory_mb = total_mb[0] + total_mb[1]; @@ -1226,9 +1226,9 @@ static void program_modules_memory_map(struct raminfo *info, int pre_jedec) total_mb[0] + total_mb[1] - info->interleaved_part_mb; channel_0_non_interleaved = total_mb[0] - info->interleaved_part_mb / 2; write_mchbar32(0x100, - channel_0_non_interleaved | (info-> - non_interleaved_part_mb << - 16)); + channel_0_non_interleaved | (info-> + non_interleaved_part_mb << + 16)); if (!pre_jedec) write_mchbar16(0x104, info->interleaved_part_mb); } @@ -1257,9 +1257,9 @@ static void program_board_delay(struct raminfo *info) int speed_bit; speed_bit = ((info->clock_speed_index > 1 - || (info->silicon_revision != 2 + || (info->silicon_revision != 2 && info->silicon_revision != 3))) ^ (info->revision >= - 0x10); + 0x10); write_500(info, 0, speed_bit | ((!info->use_ecc) << 1), 0x60e, 3, 1); write_500(info, 1, speed_bit | ((!info->use_ecc) << 1), 0x60e, @@ -1270,34 +1270,34 @@ static void program_board_delay(struct raminfo *info) rmw_1d0(0x116, 5, 2, 4, 1); } write_mchbar32(0x120, - (1 << (info->max_slots_used_in_channel + 28)) | - 0x188e7f9f); + (1 << (info->max_slots_used_in_channel + 28)) | + 0x188e7f9f);
write_mchbar8(0x124, - info->board_lane_delay[4] + - ((frequency_01(info) + 999) / 1000)); + info->board_lane_delay[4] + + ((frequency_01(info) + 999) / 1000)); write_mchbar16(0x125, 0x1360); write_mchbar8(0x127, 0x40); if (info->fsb_frequency < frequency_11(info) / 2) { unsigned some_delay_2_half_cycles; high_multiplier = 1; some_delay_2_half_cycles = ps_to_halfcycles(info, - ((3 * - fsbcycle_ps(info)) - >> 1) + - (halfcycle_ps(info) - * - reg178_min[info-> + ((3 * + fsbcycle_ps(info)) + >> 1) + + (halfcycle_ps(info) + * + reg178_min[info-> clock_speed_index] - >> 6) - + - 4 * - halfcycle_ps(info) - + 2230); + >> 6) + + + 4 * + halfcycle_ps(info) + + 2230); some_delay_3_half_cycles = min((some_delay_2_half_cycles + (frequency_11(info) * 2) * (28 - - some_delay_2_half_cycles) / + some_delay_2_half_cycles) / (frequency_11(info) * 2 - 4 * (info->fsb_frequency))) >> 3, 7); } @@ -1305,46 +1305,46 @@ static void program_board_delay(struct raminfo *info) some_delay_3_half_cycles = 3; for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32(0x220 + (channel << 10), - read_mchbar32(0x220 + - (channel << 10)) | 0x18001117); + read_mchbar32(0x220 + + (channel << 10)) | 0x18001117); write_mchbar32(0x224 + (channel << 10), - (info->max_slots_used_in_channel - 1) - | - ((info->cas_latency - 5 - + (info->max_slots_used_in_channel - 1) + | + ((info->cas_latency - 5 - info->clock_speed_index) << 21) - | - ((info->max_slots_used_in_channel + + | + ((info->max_slots_used_in_channel + info->cas_latency - cas_latency_shift - 4) << 16) - | ((info->cas_latency - cas_latency_shift - 4) << + | ((info->cas_latency - cas_latency_shift - 4) << 26) - | - ((info->cas_latency - info->clock_speed_index + + | + ((info->cas_latency - info->clock_speed_index + info->max_slots_used_in_channel - 6) << 8)); write_mchbar32(0x228 + (channel << 10), - info->max_slots_used_in_channel); + info->max_slots_used_in_channel); write_mchbar8(0x239 + (channel << 10), 32); write_mchbar32(0x248 + (channel << 10), - (high_multiplier << 24) | - (some_delay_3_half_cycles << 25) | 0x840000); + (high_multiplier << 24) | + (some_delay_3_half_cycles << 25) | 0x840000); write_mchbar32(0x278 + (channel << 10), 0xc362042); write_mchbar32(0x27c + (channel << 10), 0x8b000062); write_mchbar32(0x24c + (channel << 10), - ((! !info-> + ((! !info-> clock_speed_index) << 17) | (((2 + info-> clock_speed_index - (! !info-> clock_speed_index))) - << 12) | 0x10200); + << 12) | 0x10200);
write_mchbar8(0x267 + (channel << 10), 0x4); write_mchbar16(0x272 + (channel << 10), 0x155); write_mchbar32(0x2bc + (channel << 10), - (read_mchbar32(0x2bc + (channel << 10)) & + (read_mchbar32(0x2bc + (channel << 10)) & 0xFF000000) - | 0x707070); + | 0x707070);
write_500(info, channel, ((!info->populated_ranks[channel][1][1]) @@ -1379,11 +1379,11 @@ static void program_board_delay(struct raminfo *info) cas_latency_derived++; for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32(0x240 + (channel << 10), - ((info->clock_speed_index == + ((info->clock_speed_index == 0) * 0x11000) | 0x1002100 | ((2 + - info-> - clock_speed_index) - << 4) | (info-> + info-> + clock_speed_index) + << 4) | (info-> cas_latency - 3)); write_500(info, channel, (info->clock_speed_index << 1) | 1, @@ -1393,57 +1393,57 @@ static void program_board_delay(struct raminfo *info) 0x601, 6, 1);
write_mchbar32(0x250 + (channel << 10), - ((lane_3_delay + info->clock_speed_index + + ((lane_3_delay + info->clock_speed_index + 9) << 6) - | (info->board_lane_delay[7] << 2) | (info-> + | (info->board_lane_delay[7] << 2) | (info-> board_lane_delay [4] << 16) - | (info->board_lane_delay[1] << 25) | (info-> + | (info->board_lane_delay[1] << 25) | (info-> board_lane_delay [1] << 29) - | 1); + | 1); write_mchbar32(0x254 + (channel << 10), - (info-> + (info-> board_lane_delay[1] >> 3) | ((info-> - board_lane_delay - [8] + - 4 * - info-> - use_ecc) << 6) | - 0x80 | (info->board_lane_delay[6] << 1) | (info-> + board_lane_delay + [8] + + 4 * + info-> + use_ecc) << 6) | + 0x80 | (info->board_lane_delay[6] << 1) | (info-> board_lane_delay [2] << 28) | - (cas_latency_derived << 16) | 0x4700000); + (cas_latency_derived << 16) | 0x4700000); write_mchbar32(0x258 + (channel << 10), - ((info->board_lane_delay[5] + + ((info->board_lane_delay[5] + info->clock_speed_index + 9) << 12) | ((info->clock_speed_index - - info->cas_latency + 12) << 8) - | (info->board_lane_delay[2] << 17) | (info-> + info->cas_latency + 12) << 8) + | (info->board_lane_delay[2] << 17) | (info-> board_lane_delay [4] << 24) - | 0x47); + | 0x47); write_mchbar32(0x25c + (channel << 10), - (info->board_lane_delay[1] << 1) | (info-> + (info->board_lane_delay[1] << 1) | (info-> board_lane_delay [0] << 8) | - 0x1da50000); + 0x1da50000); write_mchbar8(0x264 + (channel << 10), 0xff); write_mchbar8(0x5f8 + (channel << 10), - (cas_latency_shift << 3) | info->use_ecc); + (cas_latency_shift << 3) | info->use_ecc); }
program_modules_memory_map(info, 1);
write_mchbar16(0x610, - (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) - | (read_mchbar16(0x610) & 0x1C3) | 0x3C); + (min(ns_to_cycles(info, some_delay_ns) / 2, 127) << 9) + | (read_mchbar16(0x610) & 0x1C3) | 0x3C); write_mchbar16(0x612, read_mchbar16(0x612) | 0x100); write_mchbar16(0x214, read_mchbar16(0x214) | 0x3E00); for (i = 0; i < 8; i++) { pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0x80 + 4 * i, - (info->total_memory_mb - 64) | !i | 2); + (info->total_memory_mb - 64) | !i | 2); pcie_write_config32(PCI_DEV (QUICKPATH_BUS, 0, 1), 0xc0 + 4 * i, 0); } } @@ -1488,7 +1488,7 @@ static void program_total_memory_map(struct raminfo *info) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); TOLUD = ALIGN_DOWN(min(3072 + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) - , TOUUD), 64); + , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { memory_remap = 1; @@ -1554,7 +1554,7 @@ static void program_total_memory_map(struct raminfo *info) for (i = 0; i < ARRAY_SIZE(memory_map); i++) { current_limit = max(current_limit, memory_map[i] & ~1); pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0x80, - (memory_map[i] & 1) | ALIGN_DOWN(current_limit - + (memory_map[i] & 1) | ALIGN_DOWN(current_limit - 1, 64) | 2); pcie_write_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 4 * i + 0xc0, 0); } @@ -1645,7 +1645,7 @@ static void write_training_data(struct raminfo *info) [lane], get_timing_register_addr (lane, tm, slot, - rank), 9, 0); + rank), 9, 0); write_1d0(info->cached_training->reg_178, 0x178, 7, 1); write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1); } @@ -1657,26 +1657,26 @@ static void dump_timings(struct raminfo *info) printk(BIOS_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, - slot, rank); + slot, rank); for (lane = 0; lane < 9; lane++) { printk(BIOS_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { printk(BIOS_DEBUG, "%x (%x) ", - read_500(info, channel, + read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), 9), - info->training. - lane_timings[i][channel][slot][rank] - [lane]); + info->training. + lane_timings[i][channel][slot][rank] + [lane]); } printk(BIOS_DEBUG, "\n"); } } printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), - info->training.reg_178); + info->training.reg_178); printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), - info->training.reg_10b); + info->training.reg_10b); #endif }
@@ -1693,8 +1693,8 @@ static void save_timings(struct raminfo *info) for (i = 0; i < 4; i++) train.lane_timings[i][channel][slot][rank][lane] = read_500(info, channel, - get_timing_register_addr(lane, i, slot, - rank), 9); + get_timing_register_addr(lane, i, slot, + rank), 9); train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6);
@@ -1704,7 +1704,7 @@ static void save_timings(struct raminfo *info) (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container));
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - &train, mrcdata, output_len); + &train, mrcdata, output_len);
mrcdata->mrc_signature = MRC_DATA_SIGNATURE; mrcdata->mrc_data_size = output_len; @@ -1714,10 +1714,10 @@ static void save_timings(struct raminfo *info) /* Zero the unused space in aligned buffer. */ if (output_len > sizeof(train)) memset(mrcdata->mrc_data + sizeof(train), 0, - output_len - sizeof(train)); + output_len - sizeof(train));
mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); + mrcdata->mrc_data_size); #endif }
@@ -1753,8 +1753,8 @@ static void wait_heci_cb_avail(int len) do csr.raw = read32(DEFAULT_HECIBAR | 0x4); while (len > - csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - - csr.csr.buffer_read_ptr)); + csr.csr.buffer_depth - (csr.csr.buffer_write_ptr - + csr.csr.buffer_read_ptr)); }
static void send_heci_packet(struct mei_header *head, u32 * payload) @@ -1835,7 +1835,7 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet, do csr.raw = read32(DEFAULT_HECIBAR | 0xc); while ((head->length + 3) >> 2 > - csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr); + csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
for (i = 0; i < (head->length + 3) >> 2; i++) packet[i++] = read32(DEFAULT_HECIBAR | 0x8); @@ -1950,7 +1950,7 @@ static void setup_heci_uma(struct raminfo *info) write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK while (read16(DEFAULT_RCBA | 0x46) & 2 - && read16(DEFAULT_DMIBAR | 0x3e) & 2) ; + && read16(DEFAULT_DMIBAR | 0x3e) & 2) ; }
write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb); @@ -2000,8 +2000,8 @@ static void read_4090(struct raminfo *info) for (rank = 0; rank < NUM_RANKS; rank++) for (lane = 0; lane < 9; lane++) info->training. - lane_timings[0][i][slot][rank][lane] - = 32; + lane_timings[0][i][slot][rank][lane] + = 32;
for (i = 1; i < 4; i++) for (channel = 0; channel < NUM_CHANNELS; channel++) @@ -2009,13 +2009,13 @@ static void read_4090(struct raminfo *info) for (rank = 0; rank < NUM_RANKS; rank++) for (lane = 0; lane < 9; lane++) { info->training. - lane_timings[i][channel] - [slot][rank][lane] = - read_500(info, channel, - get_timing_register_addr - (lane, i, slot, - rank), 9) - + (i == 1) * 11; // !!!! + lane_timings[i][channel] + [slot][rank][lane] = + read_500(info, channel, + get_timing_register_addr + (lane, i, slot, + rank), 9) + + (i == 1) * 11; // !!!! }
} @@ -2113,17 +2113,17 @@ static u8 check_testing(struct raminfo *info, u8 total_rank, int flip) for (comp2 = 0; comp2 < 60; comp2++) { u32 re[4]; u32 curroffset = - comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; + comp3 * 8 * 60 + 2 * comp1 + 8 * comp2; read128((total_rank << 28) | (curroffset << 3), (u64 *) re); failxor[0] |= - get_etalon2(flip, curroffset) ^ re[0]; + get_etalon2(flip, curroffset) ^ re[0]; failxor[1] |= - get_etalon2(flip, curroffset) ^ re[1]; + get_etalon2(flip, curroffset) ^ re[1]; failxor[0] |= - get_etalon2(flip, curroffset | 1) ^ re[2]; + get_etalon2(flip, curroffset | 1) ^ re[2]; failxor[1] |= - get_etalon2(flip, curroffset | 1) ^ re[3]; + get_etalon2(flip, curroffset | 1) ^ re[3]; } for (i = 0; i < 8; i++) if ((0xff << (8 * (i % 4))) & failxor[i / 4]) @@ -2194,7 +2194,7 @@ static u32 get_etalon(int flip, u32 addr) mask_byte |= 0xff << (8 * byte);
return (mask_bit & mask_byte) | (part1 << comp3) | (part2 << - (comp3 + 16)); + (comp3 + 16)); }
static void @@ -2224,12 +2224,12 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block, for (comp1 = 0; comp1 < 16; comp1++) for (comp2 = 0; comp2 < 64; comp2++) { u32 addr = - (totalrank << 28) | (region << 25) | (block + (totalrank << 28) | (region << 25) | (block << 16) - | (comp3 << 12) | (comp2 << 6) | (comp1 << + | (comp3 << 12) | (comp2 << 6) | (comp1 << 2); failxor[comp1 & 1] |= - read32(addr) ^ get_etalon(flip, addr); + read32(addr) ^ get_etalon(flip, addr); } for (i = 0; i < 8; i++) if ((0xff << (8 * (i % 4))) & failxor[i / 4]) @@ -2355,9 +2355,9 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, timings[reg_178][channel][slot][rank][lane]. largest) { timings[reg_178][channel][slot][rank][lane]. - smallest = 0; + smallest = 0; timings[reg_178][channel][slot][rank][lane]. - largest = 0; + largest = 0; is_all_ok = 0; } if (is_all_ok) { @@ -2374,7 +2374,7 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, failmask = check_testing(info, total_rank, 0); write_mchbar32(0xfb0, read_mchbar32(0xfb0) | 0x00030000); do_fsm(state, count, failmask, 5, 47, lower_usable, - upper_usable, reg1b3); + upper_usable, reg1b3); }
if (reg1b3) { @@ -2383,17 +2383,17 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, for (lane = 0; lane < 8; lane++) { if (state[lane] == COMPLETE) { timings[reg_178][channel][slot][rank][lane]. - smallest = - lower_usable[lane] + - (info->training. - lane_timings[0][channel][slot][rank][lane] - & 0x3F) - 32; + smallest = + lower_usable[lane] + + (info->training. + lane_timings[0][channel][slot][rank][lane] + & 0x3F) - 32; timings[reg_178][channel][slot][rank][lane]. - largest = - upper_usable[lane] + - (info->training. - lane_timings[0][channel][slot][rank][lane] - & 0x3F) - 32; + largest = + upper_usable[lane] + + (info->training. + lane_timings[0][channel][slot][rank][lane] + & 0x3F) - 32; } } } @@ -2432,31 +2432,31 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, if (failmask == 0xFF) break; failmask |= - check_testing_type2(info, total_rank, 2, i, + check_testing_type2(info, total_rank, 2, i, 0); failmask |= - check_testing_type2(info, total_rank, 3, i, + check_testing_type2(info, total_rank, 3, i, 1); } write_mchbar32(0xfb0, - read_mchbar32(0xfb0) | 0x00030000); + read_mchbar32(0xfb0) | 0x00030000); for (lane = 0; lane < 8; lane++) if (num_sucessfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] - [slot][rank][lane]. - largest <= - timings[reg_178][channel] - [slot][rank][lane].smallest) + [slot][rank][lane]. + largest <= + timings[reg_178][channel] + [slot][rank][lane].smallest) num_sucessfully_checked - [lane] = -1; + [lane] = -1; else { num_sucessfully_checked - [lane] = 0; + [lane] = 0; timings[reg_178] - [channel][slot] - [rank][lane]. - smallest++; + [channel][slot] + [rank][lane]. + smallest++; write_500(info, channel, timings [reg_178] @@ -2532,33 +2532,33 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, if (failmask == 0xFF) break; failmask |= - check_testing_type2(info, total_rank, 2, i, + check_testing_type2(info, total_rank, 2, i, 0); failmask |= - check_testing_type2(info, total_rank, 3, i, + check_testing_type2(info, total_rank, 3, i, 1); }
write_mchbar32(0xfb0, - read_mchbar32(0xfb0) | 0x00030000); + read_mchbar32(0xfb0) | 0x00030000); for (lane = 0; lane < 8; lane++) { if (num_sucessfully_checked[lane] != 0xffff) { if ((1 << lane) & failmask) { if (timings[reg_178][channel] - [slot][rank][lane]. - largest <= - timings[reg_178][channel] - [slot][rank][lane]. - smallest) { + [slot][rank][lane]. + largest <= + timings[reg_178][channel] + [slot][rank][lane]. + smallest) { num_sucessfully_checked - [lane] = -1; + [lane] = -1; } else { num_sucessfully_checked - [lane] = 0; + [lane] = 0; timings[reg_178] - [channel][slot] - [rank][lane]. - largest--; + [channel][slot] + [rank][lane]. + largest--; write_500(info, channel, timings [reg_178] @@ -2618,9 +2618,9 @@ train_ram_at_178(struct raminfo *info, u8 channel, int slot, int rank, timings[reg_178][channel][slot][rank][lane]. smallest) { timings[reg_178][channel][slot][rank][lane]. - largest = 0; + largest = 0; timings[reg_178][channel][slot][rank][lane]. - smallest = 0; + smallest = 0; } } } @@ -2641,7 +2641,7 @@ static void set_10b(struct raminfo *info, u8 val) u16 reg_500; reg_500 = read_500(info, channel, get_timing_register_addr(lane, 0, slot, - rank), 9); + rank), 9); if (val == 1) { if (lut16[info->clock_speed_index] <= reg_500) reg_500 -= lut16[info->clock_speed_index]; @@ -2681,7 +2681,7 @@ static void set_178(u8 val)
static void write_500_timings_type(struct raminfo *info, int channel, int slot, int rank, - int type) + int type) { int lane;
@@ -2727,7 +2727,7 @@ try_timing_offsets(struct raminfo *info, int channel, failmask |= check_testing(info, totalrank, flip); } do_fsm(state, count, failmask, 10, 63, lower_usable, - upper_usable, timing_offset); + upper_usable, timing_offset); } write_1d0(0, 0x1bb, 6, 1); dump_timings(info); @@ -2887,16 +2887,16 @@ static u8 choose_reg178(struct raminfo *info, timing_bounds_t * timings) reg178 += reg178_step[info->clock_speed_index]) if (margin[reg178] >= threshold) { usable_length += - reg178_step[info->clock_speed_index]; + reg178_step[info->clock_speed_index]; info->training.reg178_largest = - reg178 - - 2 * reg178_step[info->clock_speed_index]; + reg178 - + 2 * reg178_step[info->clock_speed_index];
if (!smallest_fount) { smallest_fount = 1; info->training.reg178_smallest = - reg178 + - reg178_step[info-> + reg178 + + reg178_step[info-> clock_speed_index]; } } @@ -2922,20 +2922,20 @@ static int check_cached_sanity(struct raminfo *info) for (lane = 0; lane < 8 + info->use_ecc; lane++) { u16 cached_value, estimation_value; cached_value = - info->cached_training-> - lane_timings[1][channel][slot][rank] - [lane]; + info->cached_training-> + lane_timings[1][channel][slot][rank] + [lane]; if (cached_value >= 0x18 - && cached_value <= 0x1E7) { + && cached_value <= 0x1E7) { estimation_value = - info->training. - lane_timings[1][channel] - [slot][rank][lane]; + info->training. + lane_timings[1][channel] + [slot][rank][lane]; if (estimation_value < - cached_value - 24) + cached_value - 24) return 0; if (estimation_value > - cached_value + 24) + cached_value + 24) return 0; } } @@ -2958,11 +2958,11 @@ static int try_cached_training(struct raminfo *info) info->training.reg178_smallest = info->cached_training->reg178_smallest; info->training.reg178_largest = info->cached_training->reg178_largest; memcpy(&info->training.timing_bounds, - &info->cached_training->timing_bounds, - sizeof(info->training.timing_bounds)); + &info->cached_training->timing_bounds, + sizeof(info->training.timing_bounds)); memcpy(&info->training.timing_offset, - &info->cached_training->timing_offset, - sizeof(info->training.timing_offset)); + &info->cached_training->timing_offset, + sizeof(info->training.timing_offset));
write_1d0(2, 0x142, 3, 1); saved_243[0] = read_mchbar8(0x243); @@ -3026,13 +3026,13 @@ static int try_cached_training(struct raminfo *info) timing_offset[channel][slot] [rank][lane] + (i ? info->cached_training-> - timing_bounds[tm][channel] - [slot][rank][lane]. - largest : info-> - cached_training-> - timing_bounds[tm][channel] - [slot][rank][lane]. - smallest) - 64, + timing_bounds[tm][channel] + [slot][rank][lane]. + largest : info-> + cached_training-> + timing_bounds[tm][channel] + [slot][rank][lane]. + smallest) - 64, get_timing_register_addr(lane, 1, slot, @@ -3046,7 +3046,7 @@ static int try_cached_training(struct raminfo *info)
reg1b3 = (j == 1) + 4; reg1b3 = - j == i ? reg1b3 : (-reg1b3) & 0x3f; + j == i ? reg1b3 : (-reg1b3) & 0x3f; write_1d0(reg1b3, 0x1bb, 6, 1); write_1d0(reg1b3, 0x1b3, 6, 1); write_1d0(reg1b3, 0x1a3, 6, 1); @@ -3054,10 +3054,10 @@ static int try_cached_training(struct raminfo *info) flip = !flip; write_testing(info, totalrank, flip); failmask = - check_testing(info, totalrank, + check_testing(info, totalrank, flip); expected_failmask = - j == 0 ? 0x00 : 0xff; + j == 0 ? 0x00 : 0xff; if (failmask != expected_failmask) goto fail; } @@ -3143,8 +3143,8 @@ static void do_ram_training(struct raminfo *info) if (reg178_min[info->clock_speed_index] < reg178_max[info->clock_speed_index]) memset(timings[reg178_min[info->clock_speed_index]], 0, - sizeof(timings[0]) * - (reg178_max[info->clock_speed_index] - + sizeof(timings[0]) * + (reg178_max[info->clock_speed_index] - reg178_min[info->clock_speed_index])); for (reg_178 = reg178_min[info->clock_speed_index]; reg_178 < reg178_max[info->clock_speed_index]; @@ -3155,10 +3155,10 @@ static void do_ram_training(struct raminfo *info) for (slot = 0; slot < NUM_SLOTS; slot++) for (rank = 0; rank < NUM_RANKS; rank++) { memset(&timings[reg_178][channel][slot] - [rank][0].smallest, 0, 16); + [rank][0].smallest, 0, 16); if (info-> - populated_ranks[channel][slot] - [rank]) { + populated_ranks[channel][slot] + [rank]) { train_ram_at_178(info, channel, slot, rank, totalrank, @@ -3200,7 +3200,7 @@ static void do_ram_training(struct raminfo *info) if (info->silicon_revision == 1 && (info-> populated_ranks_mask[1] ^ (info-> - populated_ranks_mask[1] >> 2)) & 1) { + populated_ranks_mask[1] >> 2)) & 1) { int ranks_after_channel1;
totalrank = 0; @@ -3211,7 +3211,7 @@ static void do_ram_training(struct raminfo *info) for (slot = 0; slot < NUM_SLOTS; slot++) for (rank = 0; rank < NUM_RANKS; rank++) { if (info-> - populated_ranks[1][slot][rank]) { + populated_ranks[1][slot][rank]) { train_ram_at_178(info, 1, slot, rank, totalrank, @@ -3231,7 +3231,7 @@ static void do_ram_training(struct raminfo *info) for (slot = 0; slot < NUM_SLOTS; slot++) for (rank = 0; rank < NUM_RANKS; rank++) if (info-> - populated_ranks[0][slot][rank]) { + populated_ranks[0][slot][rank]) { train_ram_at_178(info, 0, slot, rank, totalrank, @@ -3262,7 +3262,7 @@ static void do_ram_training(struct raminfo *info)
tm0 = choose_training(info, channel, slot, rank, lane, timings, - reg178_center); + reg178_center); write_500(info, channel, tm0, get_timing_register_addr(lane, 0, slot, rank), 9, 1); write_500(info, channel, @@ -3387,35 +3387,35 @@ compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2, result->divisor_f3_to_f1 = freq3 / freq1_reduced; result->divisor_f4_to_f2 = (freq4 - - (freq1_reduced - freq2_reduced)) / freq2_reduced; + (freq1_reduced - freq2_reduced)) / freq2_reduced; result->freq4_to_2_remainder = -(char)((freq1_reduced - freq2_reduced) + - ((u8) freq4 - - (freq1_reduced - - freq2_reduced)) % (u8) freq2_reduced); + ((u8) freq4 - + (freq1_reduced - + freq2_reduced)) % (u8) freq2_reduced); } else { if (freq2_reduced > freq1_reduced) { result->freq4_to_max_remainder = - (freq4 % freq2_reduced) - freq2_reduced + 1; + (freq4 % freq2_reduced) - freq2_reduced + 1; result->freq4_to_2_remainder = - freq4 % freq_max_reduced - - freq_max_reduced + 1; + freq4 % freq_max_reduced - + freq_max_reduced + 1; } else { result->freq4_to_max_remainder = - -(freq4 % freq2_reduced); + -(freq4 % freq2_reduced); result->freq4_to_2_remainder = - -(char)(freq4 % freq_max_reduced); + -(char)(freq4 % freq_max_reduced); } result->divisor_f4_to_f2 = freq4 / freq2_reduced; result->divisor_f3_to_f1 = (freq3 - - (freq2_reduced - freq1_reduced)) / freq1_reduced; + (freq2_reduced - freq1_reduced)) / freq1_reduced; result->freq3_to_2_remainder = -(freq3 % freq2_reduced); result->freq3_to_2_remaindera = -(char)((freq_max_reduced - freq_min_reduced) + - (freq3 - - (freq_max_reduced - - freq_min_reduced)) % freq1_reduced); + (freq3 - + (freq_max_reduced - + freq_min_reduced)) % freq1_reduced); } } result->divisor_f3_to_fmax = freq3 / freq_max_reduced; @@ -3453,7 +3453,7 @@ set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, (div_roundup(num_cycles_2, vv.common_time_unit_ps) + div_roundup(num_cycles_3, vv.common_time_unit_ps), div_roundup(num_cycles_1, - vv.common_time_unit_ps) + + vv.common_time_unit_ps) + div_roundup(num_cycles_4, vv.common_time_unit_ps)) + vv.freq_min_reduced - 1, vv.freq_max_reduced) - 1;
@@ -3461,8 +3461,8 @@ set_2d5x_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, (u8) ((vv.freq_max_reduced - vv.freq_min_reduced) + vv.freq_max_reduced * multiplier) | (vv. - freqs_reversed << 8) | ((u8) (vv.freq_min_reduced * - multiplier) << 16) | ((u8) (vv. + freqs_reversed << 8) | ((u8) (vv.freq_min_reduced * + multiplier) << 16) | ((u8) (vv. freq_min_reduced * multiplier) @@ -3494,12 +3494,12 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); write_mchbar32(reg, - ratios1.freq4_to_max_remainder | (ratios2. + ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder << 8) - | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. - divisor_f4_to_fmax - << 20)); + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); }
static void @@ -3513,42 +3513,42 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, switch (mode) { case 0: write_mchbar32(reg + 4, - ratios.freq_diff_reduced | (ratios. - freqs_reversed << - 8)); + ratios.freq_diff_reduced | (ratios. + freqs_reversed << + 8)); write_mchbar32(reg, - ratios.freq3_to_2_remainder | (ratios. - freq4_to_max_remainder - << 8) - | (ratios.divisor_f3_to_fmax << 16) | (ratios. + ratios.freq3_to_2_remainder | (ratios. + freq4_to_max_remainder + << 8) + | (ratios.divisor_f3_to_fmax << 16) | (ratios. divisor_f4_to_fmax << 20) | - (ratios.freq_min_reduced << 24)); + (ratios.freq_min_reduced << 24)); break;
case 1: write_mchbar32(reg, - ratios.freq3_to_2_remainder | (ratios. - divisor_f3_to_fmax - << 16)); + ratios.freq3_to_2_remainder | (ratios. + divisor_f3_to_fmax + << 16)); break;
case 2: write_mchbar32(reg, - ratios.freq3_to_2_remainder | (ratios. - freq4_to_max_remainder - << 8) | (ratios. + ratios.freq3_to_2_remainder | (ratios. + freq4_to_max_remainder + << 8) | (ratios. divisor_f3_to_fmax << 16) | - (ratios.divisor_f4_to_fmax << 20)); + (ratios.divisor_f4_to_fmax << 20)); break;
case 4: write_mchbar32(reg, (ratios.divisor_f3_to_fmax << 4) - | (ratios.divisor_f4_to_fmax << 8) | (ratios. + | (ratios.divisor_f4_to_fmax << 8) | (ratios. freqs_reversed << 12) | - (ratios.freq_min_reduced << 16) | (ratios. + (ratios.freq_min_reduced << 16) | (ratios. freq_diff_reduced << 24)); break; @@ -3650,7 +3650,7 @@ static void set_274265(struct raminfo *info) - info->some_delay_3_ps_rounded + 200; if (! ((info->silicon_revision == 0 - || info->silicon_revision == 1) + || info->silicon_revision == 1) && (info->revision >= 8))) delay_d_ps += halfcycle_ps(info) * 2; delay_d_ps += @@ -3662,9 +3662,9 @@ static void set_274265(struct raminfo *info) delay_d_ps += info->revision >= 8 ? 2758 : 4428;
write_mchbar32(0x140, - (read_mchbar32(0x140) & 0xfaffffff) | 0x2000000); + (read_mchbar32(0x140) & 0xfaffffff) | 0x2000000); write_mchbar32(0x138, - (read_mchbar32(0x138) & 0xfaffffff) | 0x2000000); + (read_mchbar32(0x138) & 0xfaffffff) | 0x2000000); if ((read_mchbar8(0x144) & 0x1f) > 0x13) delay_d_ps += 650; delay_c_ps = delay_d_ps + 1800; @@ -3673,7 +3673,7 @@ static void set_274265(struct raminfo *info) else delay_e_ps = cycletime_ps * div_roundup(delay_c_ps - delay_a_ps, - cycletime_ps); + cycletime_ps);
delay_e_over_cycle_ps = delay_e_ps % (2 * halfcycle_ps(info)); delay_e_cycles = delay_e_ps / (2 * halfcycle_ps(info)); @@ -3701,7 +3701,7 @@ static void set_274265(struct raminfo *info) delay_b_ps -= delay_a_ps; info->delay54_ps[channel] = cycletime_ps * div_roundup(delay_b_ps, - cycletime_ps) - + cycletime_ps) - 2 * halfcycle_ps(info) * delay_e_cycles; if (info->delay54_ps[channel] < 2500) info->delay54_ps[channel] = 2500; @@ -3714,14 +3714,14 @@ static void set_274265(struct raminfo *info) div_roundup(delay_d_ps + 7 * halfcycle_ps(info), 4 * halfcycle_ps(info)) - 6; write_mchbar32((channel << 10) + 0x274, - info->reg274265[channel][1] | (info-> - reg274265[channel] - [0] << 16)); + info->reg274265[channel][1] | (info-> + reg274265[channel] + [0] << 16)); info->reg274265[channel][2] = div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info)) + 1; write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->reg274265[channel][2] << 8); } if (info->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); @@ -3735,10 +3735,10 @@ static void restore_274265(struct raminfo *info)
for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32((channel << 10) + 0x274, - (info->reg274265[channel][0] << 16) | info-> - reg274265[channel][1]); + (info->reg274265[channel][0] << 16) | info-> + reg274265[channel][1]); write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->reg274265[channel][2] << 8); } if (info->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); @@ -3930,63 +3930,63 @@ void raminit(int s3resume) CAS_LATENCY_TIME, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, - 0x1c, 0x1d, + 0x1c, 0x1d, THERMAL_AND_REFRESH, 0x20, REFERENCE_RAW_CARD_USED, RANK1_ADDRESS_MAPPING, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, - 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, - 0x85, 0x86, 0x87, 0x88, + 0x7f, 0x80, 0x81, 0x82, 0x83, 0x84, + 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, - 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, - 0x95 + 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, + 0x95 }; if (slot) continue; for (try = 0; try < 5; try++) { v = smbus_read_byte(0x50 + channel, - DEVICE_TYPE); + DEVICE_TYPE); if (v >= 0) break; } if (v < 0) continue; for (addr = 0; - addr < - sizeof(useful_addresses) / - sizeof(useful_addresses[0]); addr++) + addr < + sizeof(useful_addresses) / + sizeof(useful_addresses[0]); addr++) gav(info. - spd[channel][0][useful_addresses - [addr]] = - smbus_read_byte(0x50 + channel, - useful_addresses - [addr])); + spd[channel][0][useful_addresses + [addr]] = + smbus_read_byte(0x50 + channel, + useful_addresses + [addr])); if (info.spd[channel][0][DEVICE_TYPE] != 11) die("Only DDR3 is supported");
v = info.spd[channel][0][RANKS_AND_DQ]; info.populated_ranks[channel][0][0] = 1; info.populated_ranks[channel][0][1] = - ((v >> 3) & 7); + ((v >> 3) & 7); if (((v >> 3) & 7) > 1) die("At most 2 ranks are supported"); if ((v & 7) == 0 || (v & 7) > 2) die("Only x8 and x16 modules are supported"); if ((info. - spd[channel][slot][MODULE_TYPE] & 0xF) != 2 - && (info. + spd[channel][slot][MODULE_TYPE] & 0xF) != 2 + && (info. spd[channel][slot][MODULE_TYPE] & 0xF) - != 3) + != 3) die("Registered memory is not supported"); info.is_x16_module[channel][0] = (v & 7) - 1; info.density[channel][slot] = - info.spd[channel][slot][DENSITY] & 0xF; + info.spd[channel][slot][DENSITY] & 0xF; if (! - (info. - spd[channel][slot][MEMORY_BUS_WIDTH] & - 0x18)) + (info. + spd[channel][slot][MEMORY_BUS_WIDTH] & + 0x18)) info.use_ecc = 0; }
@@ -3997,8 +3997,8 @@ void raminit(int s3resume) for (slot = 0; slot < NUM_SLOTS; slot++) for (rank = 0; rank < NUM_RANKS; rank++) v |= info. - populated_ranks[channel][slot][rank] - << (2 * slot + rank); + populated_ranks[channel][slot][rank] + << (2 * slot + rank); info.populated_ranks_mask[channel] = v; }
@@ -4036,7 +4036,7 @@ void raminit(int s3resume) (reg8 & ~(1 << 7)));
printk(BIOS_INFO, - "Interrupted RAM init, reset required.\n"); + "Interrupted RAM init, reset required.\n"); outb(0x6, 0xcf9); #if REAL while (1) { @@ -4051,7 +4051,7 @@ void raminit(int s3resume)
if (!s3resume && x2ca8 == 0) pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80); + pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) | 0x80);
compute_derived_timings(&info);
@@ -4075,7 +4075,7 @@ void raminit(int s3resume)
gav(read_mchbar8(0x2ca8)); // !!!! write_mchbar32(0x1804, - (read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080); + (read_mchbar32(0x1804) & 0xfffffffc) | 0x8400080);
pcie_read_config32(PCI_DEV(0xff, 2, 1), 0x6c); // !!!! pcie_write_config32(PCI_DEV(0xff, 2, 1), 0x6c, 0x40a0a0); @@ -4195,13 +4195,13 @@ void raminit(int s3resume) for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", - i, j, info.reg274265[i][j]); + i, j, info.reg274265[i][j]); for (i = 0; i < 2; i++) printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, - info.delay46_ps[i]); + info.delay46_ps[i]); for (i = 0; i < 2; i++) printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, - info.delay54_ps[i]); + info.delay54_ps[i]);
set_2dxx_series(&info);
@@ -4450,7 +4450,7 @@ void raminit(int s3resume) write_mchbar32(0x1a30, 0x0); write_mchbar32(0x1a34, 0x0); write_mchbar16(0x614, - 0xb5b | (info.populated_ranks[1][0][0] * + 0xb5b | (info.populated_ranks[1][0][0] * 0x404) | (info.populated_ranks[0][0][0] * 0xa0)); write_mchbar16(0x616, 0x26a); @@ -4462,8 +4462,8 @@ void raminit(int s3resume) write_mchbar32(0x118, 0x4); for (channel = 0; channel < NUM_CHANNELS; channel++) write_mchbar32(0x260 + (channel << 10), - 0x30809ff | - ((info. + 0x30809ff | + ((info. populated_ranks_mask[channel] & 3) << 20)); for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar16(0x31c + (channel << 10), 0x101); @@ -4490,8 +4490,8 @@ void raminit(int s3resume) rmw_1d0(0x21c, 0x38, 0, 6, 1);
write_1d0(((!info.populated_ranks[1][0][0]) << 1) | ((!info. - populated_ranks[0] - [0][0]) << 0), + populated_ranks[0] + [0][0]) << 0), 0x1d1, 3, 1); for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar16(0x38e + (channel << 10), 0x5f5f); @@ -4525,7 +4525,7 @@ void raminit(int s3resume) if (info.cached_training == NULL) { u32 reg32; printk(BIOS_ERR, - "Couldn't find training data. Rebooting\n"); + "Couldn't find training data. Rebooting\n"); reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outb(0xe, 0xcf9); @@ -4638,8 +4638,8 @@ void raminit(int s3resume) info.populated_ranks[channel][0][0] ? 9 : 0);
write_mchbar32(0x130, - 0x11111301 | (info. - populated_ranks[1][0][0] << 30) | (info. + 0x11111301 | (info. + populated_ranks[1][0][0] << 30) | (info. populated_ranks [0][0] [0] << @@ -4682,15 +4682,15 @@ void raminit(int s3resume) write_mchbar8(0x1e8, 0x4); /* OK */ for (channel = 0; channel < NUM_CHANNELS; channel++) write_mchbar32(0x294 + (channel << 10), - (info.populated_ranks_mask[channel] & 3) << 16); + (info.populated_ranks_mask[channel] & 3) << 16); write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc01ffff) | 0x10000); /* OK */ write_mchbar32(0x134, (read_mchbar32(0x134) & 0xfc85ffff) | 0x850000); /* OK */ for (channel = 0; channel < NUM_CHANNELS; channel++) write_mchbar32(0x260 + (channel << 10), - (read_mchbar32(0x260 + (channel << 10)) & + (read_mchbar32(0x260 + (channel << 10)) & ~0xf00000) | 0x8000000 | ((info. - populated_ranks_mask - [channel] & 3) << + populated_ranks_mask + [channel] & 3) << 20));
if (!s3resume) @@ -4702,7 +4702,7 @@ void raminit(int s3resume) for (rank = 0; rank < NUM_RANKS; rank++) if (info.populated_ranks[channel][slot][rank]) { jedec_read(&info, channel, slot, rank, - totalrank, 0xa, 0x400); + totalrank, 0xa, 0x400); totalrank++; }
@@ -4716,11 +4716,11 @@ void raminit(int s3resume) if (!s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32(0x294 + (channel << 10), - (info. + (info. populated_ranks_mask[channel] & 3) << - 16); + 16); write_mchbar16(0x298 + (channel << 10), - (info. + (info. populated_ranks[channel][0][0]) | (info. populated_ranks [channel] @@ -4754,11 +4754,11 @@ void raminit(int s3resume) for (slot = 0; slot < NUM_SLOTS; slot++) for (rank = 0; rank < NUM_RANKS; rank++) if (info. - populated_ranks[channel][slot] - [rank]) + populated_ranks[channel][slot] + [rank]) config_rank(&info, s3resume, - channel, slot, - rank); + channel, slot, + rank);
write_mchbar8(0x243, 0x1); write_mchbar8(0x643, 0x1); @@ -4774,11 +4774,11 @@ void raminit(int s3resume) if (s3resume) { for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32(0x294 + (channel << 10), - (info. + (info. populated_ranks_mask[channel] & 3) << - 16); + 16); write_mchbar16(0x298 + (channel << 10), - (info. + (info. populated_ranks[channel][0][0]) | (info. populated_ranks [channel] @@ -4989,7 +4989,7 @@ void raminit(int s3resume) }
pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2, - pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); + pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); udelay(10000); write_mchbar16(0x2ca8, 0x0);
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 93db98d..e6a58ff 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -144,7 +144,7 @@ Device (MCHC) * * Format of _PSS: * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } + * Package (6) { freq, power, tlat, blat, control, status } * } */ External (_PR.CPU0._PSS) @@ -156,7 +156,7 @@ Device (MCHC) While (LLess (Local0, Local1)) { /* Store _PSS entry Control value to Local2 */ ShiftRight (DeRefOf (Index (DeRefOf (Index - (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) + (_PR.CPU0._PSS, Local0)), 4)), 8, Local2) If (LEqual (Local2, Arg0)) { Return (Subtract (Local0, 1)) } diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 16df91b..5596863 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -30,9 +30,9 @@ struct northbridge_intel_sandybridge_config { u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ - u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ - u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ - u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 853139e..de87dd4 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -321,8 +321,8 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860116: /* GT2 Mobile */ case 0x80860122: /* GT2 Desktop >=1.3GHz */ case 0x80860126: /* GT2 Mobile >=1.3GHz */ - case 0x80860156: /* IVB */ - case 0x80860166: /* IVB */ + case 0x80860156: /* IVB */ + case 0x80860166: /* IVB */ new_vendev=0x80860106; /* GT1 Mobile */ break; } @@ -424,17 +424,17 @@ static void gma_pm_init_pre_vbios(struct device *dev) if (tdp <= 17) { /* <=17W ULV */ printk(BIOS_DEBUG, "IVB GT2 17W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_17w); } else if ((tdp >= 25) && (tdp <= 35)) { /* 25W-35W */ printk(BIOS_DEBUG, "IVB GT2 25W-35W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } else { /* All others */ printk(BIOS_DEBUG, "IVB GT2 35W " - "Power Meter Weights\n"); + "Power Meter Weights\n"); gtt_write_powermeter(ivb_pm_gt2_35w); } } @@ -682,7 +682,7 @@ static void gma_read_resources(struct device *dev) }
static struct pci_operations gma_pci_ops = { - .set_subsystem = gma_set_subsystem, + .set_subsystem = gma_set_subsystem, };
static struct device_operations gma_func0_ops = { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index e19d2c5..b38d7e3 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -116,7 +116,7 @@ static struct mrc_data_container *find_current_mrc_cache_local }
printk(BIOS_DEBUG, "%s: picked entry %u from cache block\n", __func__, - entry_id - 1); + entry_id - 1);
return mrc_cache; } @@ -144,11 +144,11 @@ static struct mrc_data_container *find_next_mrc_cache /* Crossed the boundary */ mrc_cache = NULL; printk(BIOS_DEBUG, "%s: no available entries found\n", - __func__); + __func__); } else { printk(BIOS_DEBUG, - "%s: picked next entry from cache block at %p\n", - __func__, mrc_cache); + "%s: picked next entry from cache block at %p\n", + __func__, mrc_cache); }
return mrc_cache; @@ -173,7 +173,7 @@ static void update_mrc_cache(void *unused) cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); + __func__); return; }
@@ -209,8 +209,8 @@ static void update_mrc_cache(void *unused) */ if (!cache) { printk(BIOS_DEBUG, - "Need to erase the MRC cache region of %d bytes at %p\n", - cache_size, cache_base); + "Need to erase the MRC cache region of %d bytes at %p\n", + cache_size, cache_base);
flash->erase(flash, to_flash_offset(cache_base), cache_size);
@@ -219,14 +219,14 @@ static void update_mrc_cache(void *unused) } // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", - cache); + cache); flash->write(flash, to_flash_offset(cache), current->mrc_data_size + sizeof(*current), current); }
BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - update_mrc_cache, NULL), + update_mrc_cache, NULL), }; #endif
@@ -238,7 +238,7 @@ struct mrc_data_container *find_current_mrc_cache(void) cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find MRC cache area\n", - __func__); + __func__); return NULL; }
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a03b8a6..c853bdb 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -122,7 +122,7 @@ static void add_fixed_resources(struct device *dev, int index)
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + "size=0x%x\n", pcie_config_base, pcie_config_size); resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; @@ -156,27 +156,27 @@ static void pci_domain_set_resources(device_t dev) /* Total Memory 2GB example: * * 00000000 0000MB-1992MB 1992MB RAM (writeback) - * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) - * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) - * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) - * 7f200000 2034MB TOLUD - * 7f800000 2040MB MEBASE - * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) - * 80000000 2048MB TOM - * 100000000 4096MB-4102MB 6MB RAM (writeback) + * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) + * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) + * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) + * 7f200000 2034MB TOLUD + * 7f800000 2040MB MEBASE + * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) + * 80000000 2048MB TOM + * 100000000 4096MB-4102MB 6MB RAM (writeback) * * Total Memory 4GB example: * * 00000000 0000MB-2768MB 2768MB RAM (writeback) - * ad000000 2768MB-2776MB 8MB TSEG (SMRR) - * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) - * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) - * afa00000 2810MB TOLUD - * ff800000 4088MB MEBASE - * ff800000 4088MB-4096MB 8MB ME UMA (uncached) - * 100000000 4096MB TOM + * ad000000 2768MB-2776MB 8MB TSEG (SMRR) + * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) + * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) + * afa00000 2810MB TOLUD + * ff800000 4088MB MEBASE + * ff800000 4088MB-4096MB 8MB ME UMA (uncached) + * 100000000 4096MB TOM * 100000000 4096MB-5374MB 1278MB RAM (writeback) - * 14fe00000 5368MB TOUUD + * 14fe00000 5368MB TOUUD */
/* Top of Upper Usable DRAM, including remap */ @@ -193,7 +193,7 @@ static void pci_domain_set_resources(device_t dev) tom |= pci_read_config32(dev, 0xa0);
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); + touud, tolud, tom);
/* ME UMA needs excluding if total memory <4GB */ me_base = pci_read_config32(dev, 0x74); @@ -212,7 +212,7 @@ static void pci_domain_set_resources(device_t dev) uma_memory_base = tomk * 1024ULL; uma_memory_size = uma_size * 1024ULL; printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", - me_base, uma_size >> 10); + me_base, uma_size >> 10); }
/* Graphics memory comes next */ @@ -242,7 +242,7 @@ static void pci_domain_set_resources(device_t dev) uma_memory_base = tomk * 1024ULL; uma_memory_size += uma_size * 1024ULL; printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", - tseg_base, uma_size >> 10); + tseg_base, uma_size >> 10);
printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
@@ -259,7 +259,7 @@ static void pci_domain_set_resources(device_t dev) if (touud > 4096 * 1024) { ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud >> 10) - 4096); }
add_fixed_resources(dev, 6); @@ -275,10 +275,10 @@ static void pci_domain_set_resources(device_t dev) */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .init = NULL, + .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, };
@@ -449,33 +449,33 @@ static void northbridge_enable(device_t dev) }
static struct pci_operations intel_pci_ops = { - .set_subsystem = intel_set_subsystem, + .set_subsystem = intel_set_subsystem, };
static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = northbridge_enable, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .init = northbridge_init, + .enable = northbridge_enable, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, };
static const struct pci_driver mc_driver_0100 __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0100, };
static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0104, /* Sandy bridge */ };
static const struct pci_driver mc_driver_1 __pci_driver = { - .ops = &mc_ops, + .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0154, /* Ivy bridge */ }; @@ -493,10 +493,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(device_t dev) diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index d317515..45c9b16 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -7,13 +7,13 @@ * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -31,10 +31,10 @@ #define PEI_DATA_H
typedef struct { - uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto + uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable uint16_t preboot_support; // 0: No xHCI preOS driver, 1: xHCI preOS driver - uint16_t xhci_streams; // 0: Disable, 1: Enable + uint16_t xhci_streams; // 0: Disable, 1: Enable } pch_usb3_controller_settings;
typedef void (*tx_byte_func)(unsigned char byte); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3b321d7..8ff2a6e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -45,11 +45,11 @@ */ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" -#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) +#define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) #else -#define CMOS_OFFSET_MRC_SEED 152 +#define CMOS_OFFSET_MRC_SEED 152 #define CMOS_OFFSET_MRC_SEED_S3 156 #define CMOS_OFFSET_MRC_SEED_CHK 160 #endif @@ -69,31 +69,31 @@ static void save_mrc_data(struct pei_data *pei_data) output_len + sizeof(struct mrc_data_container));
printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - pei_data->mrc_output, mrcdata, output_len); + pei_data->mrc_output, mrcdata, output_len);
mrcdata->mrc_signature = MRC_DATA_SIGNATURE; mrcdata->mrc_data_size = output_len; mrcdata->reserved = 0; memcpy(mrcdata->mrc_data, pei_data->mrc_output, - pei_data->mrc_output_len); + pei_data->mrc_output_len);
/* Zero the unused space in aligned buffer. */ if (output_len > pei_data->mrc_output_len) memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, - output_len - pei_data->mrc_output_len); + output_len - pei_data->mrc_output_len);
mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); + mrcdata->mrc_data_size); #endif
/* Save the MRC seed values to CMOS */ cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", - pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3); printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", - pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Save a simple checksum of the seed values */ c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, @@ -118,11 +118,11 @@ static void prepare_mrc_cache(struct pei_data *pei_data) /* Read scrambler seeds from CMOS */ pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", - pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); + pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", - pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); + pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
/* Compute seed checksum and compare */ c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed, @@ -150,8 +150,8 @@ static void prepare_mrc_cache(struct pei_data *pei_data) pei_data->mrc_input_len = mrc_cache->mrc_data_size;
printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", - __func__, pei_data->mrc_input, - pei_data->mrc_input_len, mrc_cache->mrc_checksum); + __func__, pei_data->mrc_input, + pei_data->mrc_input_len, mrc_cache->mrc_checksum); }
static const char* ecc_decoder[] = { @@ -175,32 +175,32 @@ static void report_memory_config(void) addr_decode_ch[1] = MCHBAR32(0x5008);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); + addr_decoder_common & 3, + (addr_decoder_common >> 2) & 3, + (addr_decoder_common >> 4) & 3);
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { u32 ch_conf = addr_decode_ch[i]; printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? 16 : 8, - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? 16 : 8, - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); + i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", + ecc_decoder[(ch_conf >> 24) & 3]); + printk(BIOS_DEBUG, " enhanced interleave mode %s\n", + ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", + ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", + ((ch_conf >> 0) & 0xff) * 256, + ((ch_conf >> 19) & 1) ? 16 : 8, + ((ch_conf >> 17) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", + ((ch_conf >> 8) & 0xff) * 256, + ((ch_conf >> 20) & 1) ? 16 : 8, + ((ch_conf >> 18) & 1) ? "dual" : "single", + ((ch_conf >> 16) & 1) ? ", selected" : ""); } }
@@ -257,8 +257,8 @@ void sdram_initialize(struct pei_data *pei_data) if (entry) { int rv; asm volatile ( - "call *%%ecx\n\t" - :"=a" (rv) : "c" (entry), "a" (pei_data)); + "call *%%ecx\n\t" + :"=a" (rv) : "c" (entry), "a" (pei_data)); if (rv) { switch (rv) { case -1: diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index cc74841..95a04b9 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -56,7 +56,7 @@ static void report_cpu_info(void) txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0; printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n", - mode[aes], mode[txt], mode[vt]); + mode[aes], mode[txt], mode[vt]); }
/* The PCI id name match comes from Intel document 472178 */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 291ea46..704afc4 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -220,8 +220,8 @@ void report_platform_info(void); #endif /* !__SMM__ */
-#define MRC_DATA_ALIGN 0x1000 -#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
struct mrc_data_container { u32 mrc_signature; // "MRCD" diff --git a/src/northbridge/intel/sch/acpi.c b/src/northbridge/intel/sch/acpi.c index 6dd495f..e010279 100644 --- a/src/northbridge/intel/sch/acpi.c +++ b/src/northbridge/intel/sch/acpi.c @@ -46,17 +46,17 @@ unsigned long acpi_fill_mcfg(unsigned long current) switch ((pciexbar_reg >> 1) & 3) { case 0: /* 256MB */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); + (1 << 28)); max_buses = 256; break; case 1: /* 128M */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27)); + (1 << 28) | (1 << 27)); max_buses = 128; break; case 2: /* 64M */ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28) | (1 << 27) | (1 << 26)); + (1 << 28) | (1 << 27) | (1 << 26)); max_buses = 64; break; default: /* RSVD */ @@ -68,7 +68,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
#if CONFIG_GENERATE_ACPI_TABLES current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + pciexbar, 0x0, 0x0, max_buses - 1); #endif return current; } diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 9dc33f5..455d32c 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -105,7 +105,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = find_pci_tolm(dev->link_list); printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm); printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n", - pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c)); + pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
tolud = sch_port_access_read(2, 8, 4); printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud); @@ -220,9 +220,9 @@ static void mc_read_resources(device_t dev) IORESOURCE_STORED | IORESOURCE_ASSIGNED; get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size); printk(BIOS_DEBUG, - "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), - (unsigned long)(resource->base + resource->size)); + "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), + (unsigned long)(resource->base + resource->size)); }
static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index a33a564..6d9cb10 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -31,19 +31,19 @@ * Restricted Access Regions: * * MCR - Message Control Register - * 31 24 16 8 4 0 + * 31 24 16 8 4 0 * ---------------------------------------------------------------------------- - * | | | Target | Write | | - * | Opcode | Port | register | byte | Reserved | - * | | | Address | Enables | | + * | | | Target | Write | | + * | Opcode | Port | register | byte | Reserved | + * | | | Address | Enables | | * ---------------------------------------------------------------------------- * * MDR - Message Data Register - * 31 0 + * 31 0 * ---------------------------------------------------------------------------- - * | | - * | Data | - * | | + * | | + * | Data | + * | | * ---------------------------------------------------------------------------- */
diff --git a/src/northbridge/intel/sch/raminit.c b/src/northbridge/intel/sch/raminit.c index 8689c6f..a105882 100644 --- a/src/northbridge/intel/sch/raminit.c +++ b/src/northbridge/intel/sch/raminit.c @@ -134,7 +134,7 @@ static void program_sch_dram_data(struct sys_info *sysinfo) reg32 |= (sysinfo->data_width << 4) | ((sysinfo->device_density) << 5) | (1 << 7); sch_port_access_write(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4, reg32); + SCH_MSG_DUNIT_REG_DRP, 4, reg32);
/* * Program DTR DRAM Timing Register as per data in sysinfo SCH port 1 @@ -152,7 +152,7 @@ static void program_sch_dram_data(struct sys_info *sysinfo) reg32 |= (sysinfo->cl) << 4; reg32 |= 0X4000; /* tRD_dly = 2 (15:13 = 010b) */ sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4, - reg32); + reg32);
/* * DCO DRAM Controller Operation Register as per data in sysinfo @@ -169,7 +169,7 @@ static void program_sch_dram_data(struct sys_info *sysinfo) reg32 = 0x006911c; // FIXME ?
sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, - reg32); + reg32); }
static void program_dll_config(struct sys_info *sysinfo) @@ -198,7 +198,7 @@ static void do_jedec_init(struct sys_info *sysinfo) sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); reg32 |= DRP_CKE_DIS; sch_port_access_write(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4, reg32); + SCH_MSG_DUNIT_REG_DRP, 4, reg32); reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4); rank = 0; @@ -207,12 +207,12 @@ static void do_jedec_init(struct sys_info *sysinfo) do { /* Start clocks */ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4); + SCH_MSG_DUNIT_REG_DRP, 4); reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */ sch_port_access_write(1, SCH_MSG_DUNIT_REG_DRP, 4, reg32); /* Program misc. SCH registers on rank 0 initialization. */ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4); + SCH_MSG_DUNIT_REG_DRP, 4); if (rank == 0) program_dll_config(sysinfo);
@@ -233,23 +233,23 @@ static void do_jedec_init(struct sys_info *sysinfo) cmd = rank; cmd |= SCH_DRAMINIT_CMD_NOP; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd); /* Set CKE=high. */ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4); + SCH_MSG_DUNIT_REG_DRP, 4); reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables. */ sch_port_access_write(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4, reg32); + SCH_MSG_DUNIT_REG_DRP, 4, reg32); /* * Wait 400ns (not needed when executing from flash). * Precharge all. */ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DRP, 4); + SCH_MSG_DUNIT_REG_DRP, 4); cmd = rank; cmd |= SCH_DRAMINIT_CMD_PALL; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* * EMRS(2); High temp self refresh=disabled, @@ -258,40 +258,40 @@ static void do_jedec_init(struct sys_info *sysinfo) cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS2; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* EMRS(3) (no command). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS3; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* EMRS(1); Enable DLL (Leave all bits in the command at 0). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS1; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* MRS; Reset DLL (Set memory address bit 8). */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_MRS; cmd |= (SCH_JEDEC_DLLRESET << SCH_DRAMINIT_ADDR_OFFSET); sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* Precharge all. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_PALL; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* Issue 2 auto-refresh commands. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_AREF; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd); sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* MRS command including tCL, tWR, burst length (always 4). */ cmd = rank; @@ -299,10 +299,10 @@ static void do_jedec_init(struct sys_info *sysinfo) temp = sysinfo->cl; temp += TCL_LOW; /* Adjust for the TCL base. */ temp = temp << ((SCH_JEDEC_CL_OFFSET - + SCH_DRAMINIT_ADDR_OFFSET)); /* Ready the CAS latency */ + + SCH_DRAMINIT_ADDR_OFFSET)); /* Ready the CAS latency */ cmd |= temp; sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* * Wait 200 clocks (max of 1us, so no need to delay). @@ -312,14 +312,14 @@ static void do_jedec_init(struct sys_info *sysinfo) cmd |= SCH_DRAMINIT_CMD_EMRS1; cmd |= (SCH_JEDEC_OCD_DEFAULT << SCH_DRAMINIT_ADDR_OFFSET); sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd);
/* Issue EMRS(1): OCD cal. mode exit. */ cmd = rank; cmd |= SCH_DRAMINIT_CMD_EMRS1; cmd |= (SCH_JEDEC_DQS_DIS << SCH_DRAMINIT_ADDR_OFFSET); sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, - SCH_MSG_DUNIT_PORT, 0, cmd); + SCH_MSG_DUNIT_PORT, 0, cmd); rank += SCH_DRAMINIT_RANK_MASK; num_ranks--; } while (num_ranks); @@ -355,7 +355,7 @@ void sdram_initialize(int boot_mode) reg32 |= ((sysinfo.refresh) << 2); reg32 = 0x006919c; sch_port_access_write(SCH_MSG_DUNIT_PORT, - SCH_MSG_DUNIT_REG_DCO, 4, reg32); + SCH_MSG_DUNIT_REG_DCO, 4, reg32);
/* Setting up TOM. */ reg32 = 0x10000000; @@ -368,7 +368,7 @@ void sdram_initialize(int boot_mode) /* Resume mode. */ if (boot_mode == BOOT_MODE_RESUME) sch_port_access_write_ram_cmd(SCH_OPCODE_WAKEFULLON, - SCH_MSG_DUNIT_PORT, 0, 0); + SCH_MSG_DUNIT_PORT, 0, 0);
sch_port_access_write(2, 0, 4, 0x98); sch_port_access_write(2, 3, 4, 0x7); diff --git a/src/northbridge/intel/sch/raminit.h b/src/northbridge/intel/sch/raminit.h index 179b87d..60abd64 100644 --- a/src/northbridge/intel/sch/raminit.h +++ b/src/northbridge/intel/sch/raminit.h @@ -23,128 +23,128 @@ /** * Bit Equates **/ -#define BIT(x) (1<<x) - -#define EBP_TRP_MASK (BIT(1) | BIT(0)) -#define TRP_LOW 3h -#define TRP_HIGH 5h -#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/ -#define EBP_TRCD_MASK (BIT(3) | BIT(2)) -#define TRCD_LOW 3h -#define TRCD_HIGH 5h -#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/ -#define EBP_TCL_MASK (BIT(5) | BIT(4)) -#define TCL_LOW 3 /* Minimum supported CL*/ -#define TCL_HIGH 5 /* Maximum supported CL*/ -#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/ -#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/ -#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/ -#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/ -#define EBP_FREQ_MASK (BIT(10)| BIT(9)) -#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/ -#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/ -#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/ -#define EBP_REFRESH_MASK (BIT(12)| BIT(11)) -#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/ -#define EBP_REF_DIS 00h /* Mask for refresh disabled*/ -#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/ -#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/ -#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/ -#define EBP_WIDTH_MASK BIT(15) -#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/ -#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/ -#define EBP_DENSITY_MASK (BIT(17)| BIT(16)) -#define EBP_DENSITY_OFFSET 16 -#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/ -#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/ -#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/ -#define EBP_RANKS_MASK BIT(18) -#define EBP_RANKS_OFFSET 18 -#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/ -#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/ -#define EBP_2X_MASK BIT(20) -#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/ -#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/ -#define EBP_DRAM_PARM_MASK BIT(21) -#define EBP_DRAM_PARM_OFFSET 21 -#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/ -#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/ -#define EBP_BOOT_PATH BIT(31) - - - - -#define HB_REG_MCR 0xD0 /* Message Control Register */ -#define HB_REG_MCR_OP_OFFSET 24 /* Offset of the opcode field in MCR */ -#define HB_REG_MCR_PORT_OFFSET 16 /* Offset of the port field in MCR */ -#define HB_REG_MCR_REG_OFFSET 8 /* Offset of the register field in MCR */ -#define HB_REG_MDR 0xD4 /* Message Data Register */ +#define BIT(x) (1<<x) + +#define EBP_TRP_MASK (BIT(1) | BIT(0)) +#define TRP_LOW 3h +#define TRP_HIGH 5h +#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/ +#define EBP_TRCD_MASK (BIT(3) | BIT(2)) +#define TRCD_LOW 3h +#define TRCD_HIGH 5h +#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/ +#define EBP_TCL_MASK (BIT(5) | BIT(4)) +#define TCL_LOW 3 /* Minimum supported CL*/ +#define TCL_HIGH 5 /* Maximum supported CL*/ +#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/ +#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/ +#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/ +#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/ +#define EBP_FREQ_MASK (BIT(10)| BIT(9)) +#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/ +#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/ +#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/ +#define EBP_REFRESH_MASK (BIT(12)| BIT(11)) +#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/ +#define EBP_REF_DIS 00h /* Mask for refresh disabled*/ +#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/ +#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/ +#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/ +#define EBP_WIDTH_MASK BIT(15) +#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/ +#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/ +#define EBP_DENSITY_MASK (BIT(17)| BIT(16)) +#define EBP_DENSITY_OFFSET 16 +#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/ +#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/ +#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/ +#define EBP_RANKS_MASK BIT(18) +#define EBP_RANKS_OFFSET 18 +#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/ +#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/ +#define EBP_2X_MASK BIT(20) +#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/ +#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/ +#define EBP_DRAM_PARM_MASK BIT(21) +#define EBP_DRAM_PARM_OFFSET 21 +#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/ +#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/ +#define EBP_BOOT_PATH BIT(31) + + + + +#define HB_REG_MCR 0xD0 /* Message Control Register */ +#define HB_REG_MCR_OP_OFFSET 24 /* Offset of the opcode field in MCR */ +#define HB_REG_MCR_PORT_OFFSET 16 /* Offset of the port field in MCR */ +#define HB_REG_MCR_REG_OFFSET 8 /* Offset of the register field in MCR */ +#define HB_REG_MDR 0xD4 /* Message Data Register */
/* SCH Message OpCodes and Attributes*/ -#define SCH_OPCODE_WAKEFULLON 0x2 /* SCH message bus "Wake Full On" opcode*/ -#define SCH_OPCODE_DRAMINIT 0xA0 /* SCH message bus "DRAM Init" opcode */ -#define SCH_DRAMINIT_CMD_MRS 0x4000 /* MRS command */ -#define SCH_DRAMINIT_CMD_EMRS1 0x8 /* EMRS 1 command */ -#define SCH_DRAMINIT_CMD_EMRS2 0x10 /* EMRS 2 command */ -#define SCH_DRAMINIT_CMD_EMRS3 0x18 /* EMRS 3 command */ -#define SCH_DRAMINIT_CMD_CBR 0x1 /* CBR command */ -#define SCH_DRAMINIT_CMD_AREF 0x10001 /* Refresh command, MA10=0->All */ -#define SCH_DRAMINIT_CMD_PALL 0x10002 /* Precharge command, MA10=1->All */ -#define SCH_DRAMINIT_CMD_BACT 0x3 /* Bank activate command */ -#define SCH_DRAMINIT_CMD_NOP 0x7 /* NOP command */ -#define SCH_DRAMINIT_RANK_OFFSET 21 /* Offset of the rank selection bit */ -#define SCH_DRAMINIT_RANK_MASK BIT(21) -#define SCH_DRAMINIT_ADDR_OFFSET 6 /* Offset of the address field in MDR */ -#define SCH_DRAMINIT_INTLV BIT(3) /* Interleave burst type */ -#define SCH_DRAMINIT_BL4 2 /* Burst Length = 4 */ -#define SCH_DRAMINIT_CL_OFFSET 4 /* CAS Latency bit offset */ -#define SCH_DRAMINIT_OCD_DEFAULT 0xE000 /* OCD Default command */ -#define SCH_DRAMINIT_DQS_DIS BIT(16) /* DQS Disable command */ -#define SCH_OPCODE_READ 0xD0 /* SCH message bus "read" opcode */ -#define SCH_OPCODE_WRITE 0xE0 /* SCH message bus "write" opcode */ +#define SCH_OPCODE_WAKEFULLON 0x2 /* SCH message bus "Wake Full On" opcode*/ +#define SCH_OPCODE_DRAMINIT 0xA0 /* SCH message bus "DRAM Init" opcode */ +#define SCH_DRAMINIT_CMD_MRS 0x4000 /* MRS command */ +#define SCH_DRAMINIT_CMD_EMRS1 0x8 /* EMRS 1 command */ +#define SCH_DRAMINIT_CMD_EMRS2 0x10 /* EMRS 2 command */ +#define SCH_DRAMINIT_CMD_EMRS3 0x18 /* EMRS 3 command */ +#define SCH_DRAMINIT_CMD_CBR 0x1 /* CBR command */ +#define SCH_DRAMINIT_CMD_AREF 0x10001 /* Refresh command, MA10=0->All */ +#define SCH_DRAMINIT_CMD_PALL 0x10002 /* Precharge command, MA10=1->All */ +#define SCH_DRAMINIT_CMD_BACT 0x3 /* Bank activate command */ +#define SCH_DRAMINIT_CMD_NOP 0x7 /* NOP command */ +#define SCH_DRAMINIT_RANK_OFFSET 21 /* Offset of the rank selection bit */ +#define SCH_DRAMINIT_RANK_MASK BIT(21) +#define SCH_DRAMINIT_ADDR_OFFSET 6 /* Offset of the address field in MDR */ +#define SCH_DRAMINIT_INTLV BIT(3) /* Interleave burst type */ +#define SCH_DRAMINIT_BL4 2 /* Burst Length = 4 */ +#define SCH_DRAMINIT_CL_OFFSET 4 /* CAS Latency bit offset */ +#define SCH_DRAMINIT_OCD_DEFAULT 0xE000 /* OCD Default command */ +#define SCH_DRAMINIT_DQS_DIS BIT(16) /* DQS Disable command */ +#define SCH_OPCODE_READ 0xD0 /* SCH message bus "read" opcode */ +#define SCH_OPCODE_WRITE 0xE0 /* SCH message bus "write" opcode */
/* SCH Message Ports and Registers*/
-#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */ -#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */ -#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */ -#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */ -#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */ -#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */ -#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */ -#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */ -#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */ -#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */ -#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */ -#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */ -#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */ -#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */ -#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */ -#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */ -#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */ -#define DTR_TCL_OFFSET 4 /* CAS latency offset */ -#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */ -#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */ -#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */ -#define DCO_FIELDS 0xF /* Pertinent fields in DCO */ -#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */ -#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */ -#define DCO_IC BIT(7) /* Initialization complete bit */ -#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */ -#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */ -#define SCH_MSG_TEST_PORT 05h /* Test port */ -#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */ +#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */ +#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */ +#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */ +#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */ +#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */ +#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */ +#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */ +#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */ +#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */ +#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */ +#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */ +#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */ +#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */ +#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */ +#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */ +#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */ +#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */ +#define DTR_TCL_OFFSET 4 /* CAS latency offset */ +#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */ +#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */ +#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */ +#define DCO_FIELDS 0xF /* Pertinent fields in DCO */ +#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */ +#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */ +#define DCO_IC BIT(7) /* Initialization complete bit */ +#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */ +#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */ +#define SCH_MSG_TEST_PORT 05h /* Test port */ +#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */
/* Jedec initialization mapping into the MDR address field for DRAM init messages*/
-#define SCH_JEDEC_DLLRESET BIT(8) /* DLL Reset bit( ) */ -#define SCH_JEDEC_INTLV BIT(3) /* Interleave/NOT(Sequential) bit( ) */ -#define SCH_JEDEC_CL_OFFSET 4 /* Offset of the CAS latency field */ -#define SCH_JEDEC_OCD_DEFAULT (BIT(7)| BIT(8)| BIT(9)) /* OCD default value */ -#define SCH_JEDEC_DQS_DIS BIT(10) /* DQS disable bit */ -#define SCH_JEDEC_BL4 BIT(1) /* Burst length 4 value */ +#define SCH_JEDEC_DLLRESET BIT(8) /* DLL Reset bit( ) */ +#define SCH_JEDEC_INTLV BIT(3) /* Interleave/NOT(Sequential) bit( ) */ +#define SCH_JEDEC_CL_OFFSET 4 /* Offset of the CAS latency field */ +#define SCH_JEDEC_OCD_DEFAULT (BIT(7)| BIT(8)| BIT(9)) /* OCD default value */ +#define SCH_JEDEC_DQS_DIS BIT(10) /* DQS disable bit */ +#define SCH_JEDEC_BL4 BIT(1) /* Burst length 4 value */ /*static values used during JEDEC iniatialization. These values are not dependent on memory or chipset configuration.*/ #define JEDEC_STATIC_PARAM ((SCH_JEDEC_INTLV << SCH_DRAMINIT_ADDR_OFFSET) + (SCH_JEDEC_BL4 << SCH_DRAMINIT_ADDR_OFFSET)) @@ -157,22 +157,22 @@ dependent on memory or chipset configuration.*/ /* Burst length is always 8 */ #define BURSTLENGTH 8 #define RAM_PARAM_SOURCE_SOFTSTRAP 1 -#define RAM_PARAM_SOURCE_SPD 0 +#define RAM_PARAM_SOURCE_SPD 0 struct sys_info {
u16 memory_frequency; /* 400 or 533*/ - u16 fsb_frequency; /* 400 or 533*/ + u16 fsb_frequency; /* 400 or 533*/
- u8 trp; /*3,4,5 DRAM clocks */ - u8 trcd; /*3,4,5 DRAM clocks */ - u8 cl; /*CAS Latency 3,4,5*/ + u8 trp; /*3,4,5 DRAM clocks */ + u8 trcd; /*3,4,5 DRAM clocks */ + u8 cl; /*CAS Latency 3,4,5*/
- u8 refresh; /*Refresh rate disabled,128 DRAM clocks,3.9us,7.8us */ + u8 refresh; /*Refresh rate disabled,128 DRAM clocks,3.9us,7.8us */
- u8 data_width; /*x8/x16 data width */ - u8 device_density; /*SDRAM Device Density 512/1024/2048Mbit */ - u8 ranks; /*Single/Double */ - u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */ + u8 data_width; /*x8/x16 data width */ + u8 device_density; /*SDRAM Device Density 512/1024/2048Mbit */ + u8 ranks; /*Single/Double */ + u8 ram_param_source; /*DRAM Parameter Source SPD/SoftStraps(R) Block (down memory) */ u8 boot_path;
} __attribute__ ((packed)); diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 5700842..0b4edc0 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -28,15 +28,15 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
/* Southbridge IO BARs */ /* TODO Make sure these don't get changed by stage2 */ -#define SCH_ENABLE_BIT (1<<31) -#define DEFAULT_ACPIPBLKBASE 0x510 +#define SCH_ENABLE_BIT (1<<31) +#define DEFAULT_ACPIPBLKBASE 0x510
-#define DEFAULT_SMBUSBASE 0x540 -#define DEFAULT_GPIOBASE 0x588 -#define DEFAULT_GPE0BASE 0x5C0 -#define DEFAULT_SMMCNTRLBASE 0x3F703F76 +#define DEFAULT_SMBUSBASE 0x540 +#define DEFAULT_GPIOBASE 0x588 +#define DEFAULT_GPE0BASE 0x5C0 +#define DEFAULT_SMMCNTRLBASE 0x3F703F76
-#define DEFAULT_RCBABASE 0xfed1c000 +#define DEFAULT_RCBABASE 0xfed1c000
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..e1af71d 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -50,7 +50,7 @@ static void cpu_pci_domain_set_resources(device_t dev)
tomk = get_memory_size(); printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", - tomk, tomk / 1024); + tomk, tomk / 1024);
/* Compute the top of Low memory */ tolmk = pci_tolm >> 10; diff --git a/src/northbridge/via/cn400/agp.c b/src/northbridge/via/cn400/agp.c index ce814c5..1f8c84a 100644 --- a/src/northbridge/via/cn400/agp.c +++ b/src/northbridge/via/cn400/agp.c @@ -129,14 +129,14 @@ static void agp_init(device_t dev)
static const struct device_operations agp_operations = { .read_resources = cn400_noop, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = agp_init, - .ops_pci = 0, + .init = agp_init, + .ops_pci = 0, };
static const struct pci_driver agp_driver __pci_driver = { - .ops = &agp_operations, + .ops = &agp_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_AGP, }; @@ -224,15 +224,15 @@ static void agp_bridge_init(device_t dev)
static const struct device_operations agp_bridge_operations = { .read_resources = agp_bridge_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = agp_bridge_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = agp_bridge_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver agp_bridge_driver __pci_driver = { - .ops = &agp_bridge_operations, + .ops = &agp_bridge_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_BRIDGE, }; diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 149eab3..c43ef34 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -44,10 +44,10 @@ static void memctrl_init(device_t dev) printk(BIOS_SPEW, "Entering cn400 memctrl_init.\n"); /* vlink mirror */ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_CN400_VLINK, 0); + PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
/* Setup Low Memory Top */ - /* 0x47 == HA(32:25) */ + /* 0x47 == HA(32:25) */ /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */ ranks = pci_read_config8(dev, 0x47); reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0; @@ -128,14 +128,14 @@ static void memctrl_init(device_t dev)
static const struct device_operations memctrl_operations = { .read_resources = cn400_noop, - .set_resources = cn400_noop, + .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = memctrl_init, - .ops_pci = 0, + .init = memctrl_init, + .ops_pci = 0, };
static const struct pci_driver memctrl_driver __pci_driver = { - .ops = &memctrl_operations, + .ops = &memctrl_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, }; @@ -212,7 +212,7 @@ static void cn400_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); /* First 640k */ /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ ram_resource(dev, idx++, 768, - (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); + (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } assign_resources(dev->link_list);
@@ -229,11 +229,11 @@ static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
static struct device_operations pci_domain_ops = { .read_resources = cn400_domain_read_resources, - .set_resources = cn400_domain_set_resources, + .set_resources = cn400_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = cn400_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = cn400_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) @@ -247,10 +247,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c index 23a6209..400aa58 100644 --- a/src/northbridge/via/cn400/raminit.c +++ b/src/northbridge/via/cn400/raminit.c @@ -195,16 +195,16 @@ static void ddr_ram_setup(void) /* Read SPD byte 13, Primary DRAM width. */ b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH); //print_val("\nPrimary DRAM width", b); - if( b != 4 ) // not 64/128Mb (x4) + if( b != 4 ) // not 64/128Mb (x4) c = 0x81; // 256Mb }
/* Read SPD byte 4, Number of column addresses. */ b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS); //print_val("\nNo Columns ",b); - if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr - if( b == 9 ) c |= 0x40; // 9 bit col addr - if( b == 8 ) c |= 0x20; // 8 bit col addr + if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr + if( b == 9 ) c |= 0x40; // 9 bit col addr + if( b == 8 ) c |= 0x20; // 8 bit col addr
//print_val("\nMA type ", c); pci_write_config8(ctrl.d0f3, 0x50, c); @@ -235,7 +235,7 @@ static void ddr_ram_setup(void) b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if( b & 0x02 ) { - c = 0x40; // 2GB + c = 0x40; // 2GB bank |= 0x02; } else if( b & 0x01) @@ -265,8 +265,8 @@ static void ddr_ram_setup(void) c = 0x02; // 64MB bank |= 0x01; } - else if( b & 0x08) c = 0x01; // 32MB - else c = 0x01; // Error, use default + else if( b & 0x08) c = 0x01; // 32MB + else c = 0x01; // Error, use default
// set bank zero size pci_write_config8(ctrl.d0f3, 0x40, c); @@ -318,11 +318,11 @@ static void ddr_ram_setup(void) print_val("\nCycle time at CL X-1 (nS)", c); */ /* Scaling of Cycle Time SPD data */ - /* 7 4 3 0 */ - /* ns x0.1ns */ + /* 7 4 3 0 */ + /* ns x0.1ns */ bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if( b & 0x10 ){ // DDR offering optional CAS 3 + if( b & 0x10 ){ // DDR offering optional CAS 3 //print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ @@ -338,9 +338,9 @@ static void ddr_ram_setup(void) c = 0x10; } } - }else{ // no optional CAS values just 2 & 2.5 + }else{ // no optional CAS values just 2 & 2.5 //print_debug("\nStarting at CAS 2.5"); - c = 0x20; // assume CAS 2.5 + c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 //print_debug("\nWe can do CAS 2"); @@ -350,8 +350,8 @@ static void ddr_ram_setup(void) }
/* Scale DRAM Cycle Time to tRP/tRCD */ - /* 7 2 1 0 */ - /* ns x0.25ns */ + /* 7 2 1 0 */ + /* ns x0.25ns */ if ( bank <= 0x50 ) bank = 0x14; else if (bank <= 0x60) bank = 0x18; else bank = 0x1E; @@ -360,10 +360,10 @@ static void ddr_ram_setup(void) DRAM Timing Device 0 Fn 3 Offset 56
RAS Pulse width 56[7,6] - CAS Latency 56[5,4] + CAS Latency 56[5,4] Row pre-charge 56[1,0]
- SDR DDR + SDR DDR 00 1T - 01 2T 2T 10 3T 2.5T @@ -535,7 +535,7 @@ static void ddr_ram_setup(void) CPU Frequency Device 0 Function 2 Offset 54
CPU FSB Operating Frequency (bits 7:5) - 000 : 100MHz 001 : 133MHz + 000 : 100MHz 001 : 133MHz 010 : 200MHz 011->111 : Reserved
@@ -623,14 +623,14 @@ static void ddr_ram_setup(void) MR[0-2] dont care
CAS Latency - 000 reserved - 001 reserved - 010 2 - 011 3 - 100 reserved - 101 1.5 - 110 2.5 - 111 reserved + 000 reserved + 001 reserved + 010 2 + 011 3 + 100 reserved + 101 1.5 + 110 2.5 + 111 reserved
CAS 2 0101011000 = 0x158 CAS 2.5 1101011000 = 0x358 diff --git a/src/northbridge/via/cn400/vga.c b/src/northbridge/via/cn400/vga.c index a2afdce..81da39a 100644 --- a/src/northbridge/via/cn400/vga.c +++ b/src/northbridge/via/cn400/vga.c @@ -68,7 +68,7 @@ static int via_cn400_int15_handler(void) case 0x5f0f: X86_EAX=0x860f; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; @@ -140,14 +140,14 @@ static void vga_init(device_t dev)
static const struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .ops_pci = 0, + .init = vga_init, + .ops_pci = 0, };
static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, + .ops = &vga_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_VGA, }; diff --git a/src/northbridge/via/cn400/vlink.c b/src/northbridge/via/cn400/vlink.c index c98982e..7aae641 100644 --- a/src/northbridge/via/cn400/vlink.c +++ b/src/northbridge/via/cn400/vlink.c @@ -123,14 +123,14 @@ static void vlink_init(device_t dev)
static const struct device_operations vlink_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vlink_init, - .ops_pci = 0, + .init = vlink_init, + .ops_pci = 0, };
static const struct pci_driver vlink_driver __pci_driver = { - .ops = &vlink_operations, + .ops = &vlink_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_VLINK, }; @@ -159,14 +159,14 @@ static void c3_host_init(device_t dev)
static const struct device_operations c3_host_operations = { .read_resources = cn400_noop, - .set_resources = cn400_noop, + .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = c3_host_init, - .ops_pci = 0, + .init = c3_host_init, + .ops_pci = 0, };
static const struct pci_driver c3_host_driver __pci_driver = { - .ops = &c3_host_operations, + .ops = &c3_host_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_HOST, }; @@ -196,14 +196,14 @@ static void c3_err_init(device_t dev)
static const struct device_operations c3_err_operations = { .read_resources = cn400_noop, - .set_resources = cn400_noop, + .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = c3_err_init, - .ops_pci = 0, + .init = c3_err_init, + .ops_pci = 0, };
static const struct pci_driver c3_err_driver __pci_driver = { - .ops = &c3_err_operations, + .ops = &c3_err_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_ERR, }; @@ -232,14 +232,14 @@ static void cn400_pm_init(device_t dev)
static const struct device_operations cn400_pm_operations = { .read_resources = cn400_noop, - .set_resources = cn400_noop, + .set_resources = cn400_noop, .enable_resources = cn400_noop, - .init = cn400_pm_init, - .ops_pci = 0, + .init = cn400_pm_init, + .ops_pci = 0, };
static const struct pci_driver cn400_pm_driver __pci_driver = { - .ops = &c3_err_operations, + .ops = &c3_err_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN400_PM, }; diff --git a/src/northbridge/via/cn700/agp.c b/src/northbridge/via/cn700/agp.c index e5a0fd0..10a51e1 100644 --- a/src/northbridge/via/cn700/agp.c +++ b/src/northbridge/via/cn700/agp.c @@ -105,14 +105,14 @@ static void agp_init(device_t dev)
static const struct device_operations agp_operations = { .read_resources = cn700_noop, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = agp_init, - .ops_pci = 0, + .init = agp_init, + .ops_pci = 0, };
static const struct pci_driver agp_driver __pci_driver = { - .ops = &agp_operations, + .ops = &agp_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_AGP, }; @@ -158,15 +158,15 @@ static void agp_bridge_init(device_t dev)
static const struct device_operations agp_bridge_operations = { .read_resources = cn700_noop, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = agp_bridge_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = agp_bridge_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver agp_bridge_driver __pci_driver = { - .ops = &agp_bridge_operations, + .ops = &agp_bridge_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_BRIDGE, }; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index a326baf..4893002 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -74,7 +74,7 @@ static void memctrl_init(device_t dev) pci_write_config8(dev, 0x83, shadowreg); /* vlink mirror */ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_CN700_VLINK, 0); + PCI_DEVICE_ID_VIA_CN700_VLINK, 0); if (vlink_dev) { pci_write_config8(vlink_dev, 0x61, pagec); pci_write_config8(vlink_dev, 0x62, paged); @@ -88,11 +88,11 @@ static void memctrl_init(device_t dev)
static const struct device_operations memctrl_operations = { .read_resources = cn700_noop, - .init = memctrl_init, + .init = memctrl_init, };
static const struct pci_driver memctrl_driver __pci_driver = { - .ops = &memctrl_operations, + .ops = &memctrl_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; @@ -142,18 +142,18 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); /* First 640k */ /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ ram_resource(dev, idx++, 768, - (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); + (tolmk - 768 - CONFIG_VIDEO_MB * 1024)); } assign_resources(dev->link_list); }
static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) @@ -167,10 +167,10 @@ static void cpu_bus_noop(device_t dev)
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 0103c4f..b515309 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -80,10 +80,10 @@ static void c7_cpu_setup(device_t dev) /* Miscellaneous Control */ /* * DRAM Operating Frequency (bits 7:5) - * 000 : 100MHz 001 : 133MHz - * 010 : 166MHz 011 : 200MHz - * 100 : 266MHz 101 : 333MHz - * 110/111 : Reserved + * 000 : 100MHz 001 : 133MHz + * 010 : 166MHz 011 : 200MHz + * 100 : 266MHz 101 : 333MHz + * 110/111 : Reserved */ /* CPU Miscellaneous Control */ pci_write_config8(dev, 0x59, 0x44); @@ -461,6 +461,6 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) reg = pci_read_config8(ctrl->d0f3, 0x41); if (reg != 0) sdram_enable(ctrl->d0f3, - pci_read_config8(ctrl->d0f3, 0x40) << 26); + pci_read_config8(ctrl->d0f3, 0x40) << 26); sdram_set_post(ctrl); } diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 4434e57..bdadb2f 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -68,7 +68,7 @@ static int via_cn700_int15_handler(void) case 0x5f0f: X86_EAX=0x860f; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; @@ -137,14 +137,14 @@ static void vga_init(device_t dev)
static const struct device_operations vga_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .ops_pci = 0, + .init = vga_init, + .ops_pci = 0, };
static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, + .ops = &vga_operations, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_CN700_VGA, }; diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c index 7c77bff..9d12159 100644 --- a/src/northbridge/via/cx700/early_smbus.c +++ b/src/northbridge/via/cx700/early_smbus.c @@ -158,7 +158,7 @@ static void set_ics_data(unsigned char dev, int data, char len) }
//for (i=0; i < len; i++) - // outb(data[i],SMBBLKDAT); + // outb(data[i],SMBBLKDAT);
outb(dev, SMBXMITADD); outb(0, SMBHSTCMD); diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 22e8743..a5660fe 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -173,7 +173,7 @@ static void cx700_set_lpc_registers(struct device *dev) pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); +// pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index a2e6dad..49eb394 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -25,7 +25,7 @@
/* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP -#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) +#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #else #define PRINTK_DEBUG(x...) #endif @@ -215,13 +215,13 @@ static const u8 Dram_Driving_ODT_CTRL[] = {
static const u8 ODT_TBL[] = { /* RankMap, ODT Control Bits, DRAM & NB ODT setting */ - 0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), - 0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), - 0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), 0x0f, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), };
@@ -239,7 +239,7 @@ static const u8 Duty_Control_DDR2[] = { /* RxEC, RxED, RxEE, RXEF */ /* DDRII533 1~2 rank, DDRII400 */ 0x84, 0x10, 0x00, 0x10, - /* DDRII533 3~4 rank */ + /* DDRII533 3~4 rank */ 0x44, 0x10, 0x00, 0x10, };
@@ -308,7 +308,7 @@ static const u8 Init_Rank_Reg_Table[] = { };
static const u16 DDR2_MRS_table[] = { -/* CL: 2, 3, 4, 5 */ +/* CL: 2, 3, 4, 5 */ 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ }; @@ -351,7 +351,7 @@ static void do_ram_command(const struct mem_controller *ctrl, u8 command) reg |= command; pci_write_config8(MEMCTRL, 0x6b, reg);
- PRINTK_DEBUG(" Sending RAM command 0x%02x\n", reg); + PRINTK_DEBUG(" Sending RAM command 0x%02x\n", reg); }
// TODO factor out to another file @@ -422,7 +422,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x6d, 0xc0);
/**********************************************/ - /* Set DRAM Freq (DDR2 533) */ + /* Set DRAM Freq (DDR2 533) */ /**********************************************/ /* SPD 9 SDRAM Cycle Time */ GET_SPD(dimm, spds, regs, 9); @@ -480,7 +480,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x6f, regs);
/**********************************************/ - /* Set DRAM Timing Setting (DDR2 533) */ + /* Set DRAM Timing Setting (DDR2 533) */ /**********************************************/ /* SPD 9 18 23 25 CAS Latency NB3DRAM_REG62[2:0] */ /* Read SPD byte 18 CAS Latency */ @@ -663,7 +663,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x63, regs);
/**********************************************/ - /* Set DRAM DRDY Setting */ + /* Set DRAM DRDY Setting */ /**********************************************/ /* Write slowest value to register */ tmp = sizeof(Host_Reg_Val) / sizeof(Host_Reg_Val[0]); @@ -676,7 +676,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(HOSTCTRL, 0x51, regs);
/**********************************************/ - /* Set DRAM BurstLength */ + /* Set DRAM BurstLength */ /**********************************************/ regs = pci_read_config8(MEMCTRL, 0x6c); for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { @@ -696,7 +696,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(HOSTCTRL, 0x54, val);
/**********************************************/ - /* Set DRAM Driving Setting */ + /* Set DRAM Driving Setting */ /**********************************************/ /* DRAM Timing ODT */ tmp = sizeof(Dram_Driving_ODT_CTRL) / sizeof(Dram_Driving_ODT_CTRL[0]); @@ -774,7 +774,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0xe6, 0xaa);
/**********************************************/ - /* Set DRAM Duty Control */ + /* Set DRAM Duty Control */ /**********************************************/ regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_RANK_NUM); switch (regs) { @@ -799,7 +799,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) }
/**********************************************/ - /* Set DRAM Clock Control */ + /* Set DRAM Clock Control */ /**********************************************/ /* Write Data Phase */ val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -821,7 +821,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl)
/* Clock Phase Control for FeedBack Mode */ regs = pci_read_config8(MEMCTRL, 0x90); -// regs |= 0x80; +// regs |= 0x80; pci_write_config8(MEMCTRL, 0x90, regs);
regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -918,7 +918,7 @@ static void sdram_set_safe_values(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x6f, regs);
/***************************************************/ - /* Find suitable DQS value for ChA and ChB */ + /* Find suitable DQS value for ChA and ChB */ /***************************************************/ // Set DQS output delay for Channel A regs = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_FREQ); @@ -1258,7 +1258,7 @@ static void sdram_enable(const struct mem_controller *ctrl)
#ifdef MEM_WIDTH_32BIT_MODE /****************************************************************/ - /* Set Dram 32bit Mode */ + /* Set Dram 32bit Mode */ /****************************************************************/ reg8 = pci_read_config8(MEMCTRL, 0x6c); reg8 |= 0x20; @@ -1347,7 +1347,7 @@ static void sdram_enable(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x77, reg8);
/****************************************************************/ - /* Find out the lowest Bank Interleave and Set Register */ + /* Find out the lowest Bank Interleave and Set Register */ /****************************************************************/ #if 0 //TODO @@ -1388,7 +1388,7 @@ static void sdram_enable(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x69, reg8);
/****************************************************************/ - /* DRAM Sizing and Fill MA type */ + /* DRAM Sizing and Fill MA type */ /****************************************************************/ for (i = 0; i < 4; i++) { val = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i)); @@ -1450,7 +1450,7 @@ static void sdram_enable(const struct mem_controller *ctrl) pci_write_config8(MEMCTRL, 0x6b, reg8);
/****************************************************************/ - /* DRAM re-initialize for burst length */ + /* DRAM re-initialize for burst length */ /****************************************************************/ for (i = 0; i < 4; i++) { reg8 = pci_read_config8(PCI_DEV(0, 0, 4), (SCRATCH_RANK_0 + i)); @@ -1464,7 +1464,7 @@ static void sdram_enable(const struct mem_controller *ctrl) }
/****************************************************************/ - /* Set the MA Type */ + /* Set the MA Type */ /****************************************************************/ reg8 = pci_read_config8(MEMCTRL, 0x50); reg8 &= 0x11; @@ -1495,7 +1495,7 @@ static void sdram_enable(const struct mem_controller *ctrl) }
/****************************************************************/ - /* Set Start and Ending Address */ + /* Set Start and Ending Address */ /****************************************************************/ dl = 0; /* Begin Address */ dh = 0; /* Ending Address */ @@ -1523,7 +1523,7 @@ static void sdram_enable(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 7), 0xe5, dh);
/****************************************************************/ - /* Set Physical to Virtual Rank mapping */ + /* Set Physical to Virtual Rank mapping */ /****************************************************************/ pci_write_config32(MEMCTRL, 0x54, 0x0); for (i = 0; i < 4; i++) { @@ -1543,7 +1543,7 @@ static void sdram_enable(const struct mem_controller *ctrl) }
/****************************************************************/ - /* Set DRAM Refresh Counter */ + /* Set DRAM Refresh Counter */ /****************************************************************/ val = pci_read_config8(MEMCTRL, 0X90) & 0X7; val <<= 1; @@ -1586,7 +1586,7 @@ static void sdram_enable(const struct mem_controller *ctrl) pci_write_config8(HOSTCTRL, 0x5d, 0xb2);
/****************************************************************/ - /* UMA registers for N-series projects */ + /* UMA registers for N-series projects */ /****************************************************************/
/* Manual setting frame buffer bank */ diff --git a/src/northbridge/via/cx700/usb.c b/src/northbridge/via/cx700/usb.c index 82a623c..a34a984 100644 --- a/src/northbridge/via/cx700/usb.c +++ b/src/northbridge/via/cx700/usb.c @@ -42,15 +42,15 @@ static void usb_init(struct device *dev)
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .enable = 0, - .ops_pci = 0, + .init = usb_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver via_usb_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_VIA, .device = 0x3038, }; diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c index 70cf55a..e6557f1 100644 --- a/src/northbridge/via/cx700/vga.c +++ b/src/northbridge/via/cx700/vga.c @@ -120,7 +120,7 @@ static int via_cx700_int15_handler(void) res=1; break;
- default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; @@ -153,7 +153,7 @@ static void vga_enable_console(void) * it on is good. */
- /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); #endif } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index bed434d..7c92cf7 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -31,11 +31,11 @@ static void northbridge_init(device_t dev)
static struct device_operations northbridge_operations = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -50,9 +50,9 @@ static void pci_domain_set_resources(device_t dev) 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; @@ -94,17 +94,17 @@ static void pci_domain_set_resources(device_t dev) }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -112,22 +112,22 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } }
struct chip_operations northbridge_via_vt8601_ops = { diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c index 5e7611a..547b671 100644 --- a/src/northbridge/via/vt8601/raminit.c +++ b/src/northbridge/via/vt8601/raminit.c @@ -3,7 +3,7 @@
/* This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described +called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has been authored by an employee or employees of the University of diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 6e0f4ea..862fd63 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -44,7 +44,7 @@ static void northbridge_init(device_t dev) /* Fixup GART and framebuffer addresses properly. * First setup frame buffer properly. */ - //fb = pci_read_config32(dev, 0x10); /* Base addres of framebuffer */ + //fb = pci_read_config32(dev, 0x10); /* Base addres of framebuffer */ fb = 0xd0000000; printk(BIOS_DEBUG, "Frame buffer at %8lx\n",fb);
@@ -52,9 +52,9 @@ static void northbridge_init(device_t dev) c |= fb>>28; /* upper nibble of frame buffer address */ c = 0xdd; pci_write_config8(dev, 0xe1, c); - c = 0x81; /* enable framebuffer */ + c = 0x81; /* enable framebuffer */ pci_write_config8(dev, 0xe0, c); - pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */ + pci_write_config8(dev, 0xe2, 0x42); /* 'cos award does */ } }
@@ -65,9 +65,9 @@ static void nullfunc(device_t dev)
static struct device_operations northbridge_operations = { .read_resources = nullfunc, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = northbridge_init + .init = northbridge_init };
static const struct pci_driver northbridge_driver __pci_driver = { @@ -90,11 +90,11 @@ static void agp_init(device_t dev)
static struct device_operations agp_operations = { .read_resources = nullfunc, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = agp_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = agp_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver agp_driver __pci_driver = { @@ -107,11 +107,11 @@ static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm;
printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n");
- pci_tolm = find_pci_tolm(dev->link_list); + pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (mc_dev) { unsigned long tomk, tolmk; @@ -154,17 +154,17 @@ static void pci_domain_set_resources(device_t dev) }
static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, };
static void cpu_bus_init(device_t dev) { - initialize_cpus(dev->link_list); + initialize_cpus(dev->link_list); }
static void cpu_bus_noop(device_t dev) @@ -172,24 +172,24 @@ static void cpu_bus_noop(device_t dev) }
static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_noop, - .set_resources = cpu_bus_noop, - .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, };
static void enable_dev(struct device *dev) { printk(BIOS_SPEW, "In vt8623 enable_dev for device %s.\n", dev_path(dev));
- /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } }
struct chip_operations northbridge_via_vt8623_ops = { diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c index b5c78a1..d7b95c4 100644 --- a/src/northbridge/via/vt8623/raminit.c +++ b/src/northbridge/via/vt8623/raminit.c @@ -105,7 +105,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) b = smbus_read_byte(DIMM0,17); print_val("Detecting Memory\nNumber of Banks ",b);
- if( b != 2 ){ // not 16 Mb type + if( b != 2 ){ // not 16 Mb type
/* Read SPD byte 3, Number of row addresses. @@ -119,7 +119,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ b = smbus_read_byte(DIMM0,13); print_val("\nPriamry DRAM width",b); - if( b != 4 ) // mot 64/128Mb (x4) + if( b != 4 ) // mot 64/128Mb (x4) c = 0x80; // 256Mb }
@@ -130,9 +130,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) */ b = smbus_read_byte(DIMM0,4); print_val("\nNo Columns ",b); - if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr - if( b == 9 ) c |= 0x40; // 9 bit col addr - if( b == 8 ) c |= 0x20; // 8 bit col addr + if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr + if( b == 9 ) c |= 0x40; // 9 bit col addr + if( b == 8 ) c |= 0x20; // 8 bit col addr
} print_val("\nMA type ",c); @@ -151,15 +151,15 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) // Read SPD byte 31 Module bank density c = 0; b = smbus_read_byte(DIMM0,31); - if( b & 0x02 ) c = 0x80; // 2GB - else if( b & 0x01) c = 0x40; // 1GB - else if( b & 0x80) c = 0x20; // 512Mb - else if( b & 0x40) c = 0x10; // 256Mb - else if( b & 0x20) c = 0x08; // 128Mb - else if( b & 0x10) c = 0x04; // 64Mb - else if( b & 0x08) c = 0x02; // 32Mb - else if( b & 0x04) c = 0x01; // 16Mb / 4Gb - else c = 0x01; // Error, use default + if( b & 0x02 ) c = 0x80; // 2GB + else if( b & 0x01) c = 0x40; // 1GB + else if( b & 0x80) c = 0x20; // 512Mb + else if( b & 0x40) c = 0x10; // 256Mb + else if( b & 0x20) c = 0x08; // 128Mb + else if( b & 0x10) c = 0x04; // 64Mb + else if( b & 0x08) c = 0x02; // 32Mb + else if( b & 0x04) c = 0x01; // 16Mb / 4Gb + else c = 0x01; // Error, use default
print_val("\nBank 0 (*16 Mb) ",c); @@ -194,7 +194,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(DIMM0,25));
- if( b & 0x10 ){ // DDR offering optional CAS 3 + if( b & 0x10 ){ // DDR offering optional CAS 3 print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ @@ -210,9 +210,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) c = 0x10; } } - }else{ // no optional CAS values just 2 & 2.5 + }else{ // no optional CAS values just 2 & 2.5 print_debug("\nStarting at CAS 2.5"); - c = 0x20; // assume CAS 2.5 + c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 print_debug("\nWe can do CAS 2"); @@ -228,9 +228,9 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Row pre-charge 64[7] RAS Pulse width 64[6] - CAS Latency 64[5,4] + CAS Latency 64[5,4]
- SDR DDR + SDR DDR 00 1T - 01 2T 2T 10 3T 2.5T @@ -242,13 +242,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Determine row pre-charge time (tRP)
- T nS SPD*4 SPD - 1T 7.5 0x1e - 2T 15 0x3c - 3T 22.5 0x5a - 4T 30 0x1e - 5T 37.5 0x25 .5? - 6T 45 0x2d + T nS SPD*4 SPD + 1T 7.5 0x1e + 2T 15 0x3c + 3T 22.5 0x5a + 4T 30 0x1e + 5T 37.5 0x25 .5? + 6T 45 0x2d
Read SPD byte 27, min row pre-charge time. @@ -256,7 +256,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
b = smbus_read_byte(DIMM0,27); print_val("\ntRP ",b); - if( b > 0x3c ) // set tRP = 3T + if( b > 0x3c ) // set tRP = 3T c |= 0x80;
@@ -268,7 +268,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
b = smbus_read_byte(DIMM0,29); print_val("\ntRCD ",b); - if( b > 0x3c ) // set tRCD = 3T + if( b > 0x3c ) // set tRCD = 3T c |= 0x04;
/* @@ -280,7 +280,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
b = smbus_read_byte(DIMM0,30); print_val("\ntRAS ",b); - if( b > 0x25 ) // set tRAS = 6T + if( b > 0x25 ) // set tRAS = 6T c |= 0x40;
@@ -308,7 +308,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* CPU Frequency Device 0 Offset 54
- CPU Frequency 54[7,6] bootstraps at 0xc0 (133Mhz) + CPU Frequency 54[7,6] bootstraps at 0xc0 (133Mhz) DRAM burst length = 8 54[5] */ pci_write_config8(north,0x54,0xe0); @@ -317,11 +317,11 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) /* DRAM Clock Device 0 Offset 69
- DRAM/CPU speed 69[7,6] (leave at default 00 == CPU) + DRAM/CPU speed 69[7,6] (leave at default 00 == CPU) Controller que > 2 69[5] Controller que != 4 69[4] - DRAM 8k page size 69[3] - DRAM 4k page size 69[2] + DRAM 8k page size 69[3] + DRAM 4k page size 69[2] Multiple page mode 69[0] */
@@ -345,12 +345,12 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
b = smbus_read_byte(DIMM0,5); // SPD byte 5 # of physical banks if( b > 1) { - // Increase drive control when there is more than 1 physical bank - pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE - pci_write_config8(north,0x6d,0x55); // DC: Early clock select, DQM, CS#, MD + // Increase drive control when there is more than 1 physical bank + pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE + pci_write_config8(north,0x6d,0x55); // DC: Early clock select, DQM, CS#, MD } /* place frame buffer on last bank */ - if( !b) b++; // make sure at least 1 bank reported + if( !b) b++; // make sure at least 1 bank reported pci_write_config8(north,0xe3,b-1);
for( bank = 0 , bank_address=0; bank < b ; bank++){ @@ -418,14 +418,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) MR[0-2] dont care
CAS Latency - 000 reserved - 001 reserved - 010 2 - 011 3 - 100 reserved - 101 1.5 - 110 2.5 - 111 reserved + 000 reserved + 001 reserved + 010 2 + 011 3 + 100 reserved + 101 1.5 + 110 2.5 + 111 reserved
CAS 2 0101011000 = 0x158 CAS 2.5 1101011000 = 0x358 @@ -567,14 +567,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Rx69 (DRAM freq) Rx58 (chip tech) Rx6a
- 133Mhz 64/128Mb 0x86 - 133Mhz 256/512Mb 0x43 - 100Mhz 64/128Mb 0x65 - 100Mhz 256/512Mb 0x32 + 133Mhz 64/128Mb 0x86 + 133Mhz 256/512Mb 0x43 + 100Mhz 64/128Mb 0x65 + 100Mhz 256/512Mb 0x32 */
b = pci_read_config8(north,0x58); - if( b < 0x80 ) // 256 tech + if( b < 0x80 ) // 256 tech pci_write_config8(north,0x6a,0x86); else pci_write_config8(north,0x6a,0x43); @@ -609,7 +609,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl) pci_write_config8(north,0xac,0x2f); pci_write_config8(north,0xae,0x04);
- print_debug("vt8623 done\n"); + print_debug("vt8623 done\n"); dumpnorth(north);
print_debug("AGP\n"); diff --git a/src/northbridge/via/vt8623/vga.c b/src/northbridge/via/vt8623/vga.c index 7ed2792..63a0de3 100644 --- a/src/northbridge/via/vt8623/vga.c +++ b/src/northbridge/via/vt8623/vga.c @@ -65,7 +65,7 @@ static int via_vt8623_int15_handler(void) case 0x5f0f: X86_EAX=0x860f; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); break; @@ -107,7 +107,7 @@ static void vga_enable_console(void) * it on is good. */
- /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); #endif } diff --git a/src/northbridge/via/vx800/clk_ctrl.c b/src/northbridge/via/vx800/clk_ctrl.c index 4fc274a..50bb029 100644 --- a/src/northbridge/via/vx800/clk_ctrl.c +++ b/src/northbridge/via/vx800/clk_ctrl.c @@ -106,7 +106,7 @@ void ClkPhsCtrlFBMDDR2(DRAM_SYS_ATTR *DramAttr) } else if (DramAttr->RankNumChA > 1) { /* 2~4 Rank */ for (i = 0; i < 3; i++) { Data = pci_read_config8(MEMCTRL, - DDR2_ChA_Clk_Phase_Table_2R[i][0]); + DDR2_ChA_Clk_Phase_Table_2R[i][0]); Data &= DDR2_ChA_Clk_Phase_Table_2R[i][1]; /* mask */ Data |= DDR2_ChA_Clk_Phase_Table_2R[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, @@ -251,7 +251,7 @@ void DQSInputCaptureCtrl(DRAM_SYS_ATTR *DramAttr) Data &= DDR2_ChB_DQS_Input_Capture_Tbl[i][1]; /* mask */ Data |= DDR2_ChB_DQS_Input_Capture_Tbl[i][FreqId]; /* set val */ pci_write_config8(MEMCTRL, - DDR2_ChB_DQS_Input_Capture_Tbl[i][0], Data); + DDR2_ChB_DQS_Input_Capture_Tbl[i][0], Data); } } #endif @@ -267,7 +267,7 @@ void DCLKPhsCtrl(DRAM_SYS_ATTR *DramAttr) { u8 Data;
- Data = 0; /* TODO: Can be dropped? */ + Data = 0; /* TODO: Can be dropped? */ Data = pci_read_config8(MEMCTRL, 0x99); Data &= 0xE1; /* DDR in Dimm1, MCLKOA[4,3,0] will output MCLK */ diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc..1ac3bc3 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -71,9 +71,9 @@ CB_STATUS DRAMDetect(DRAM_SYS_ATTR *DramAttr) * three conditions: * * 1. Each DRAM channel may have 1 or 2 ranks of DIMM. 3/4 ranks can not - * support 1T command rate. It's for loading issue. 1T can supports - * (a) only one socket with two ranks, OR - * (b) two sockets each with 1 rank. + * support 1T command rate. It's for loading issue. 1T can supports + * (a) only one socket with two ranks, OR + * (b) two sockets each with 1 rank. * 2. User wishes to enable 1T command rate mode and turn on by setup menu. * 3. If 1T command rate can be enabled, just set EBP bit here. */ @@ -130,8 +130,8 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) if (pSPDDataBuf[SPD_MEMORY_TYPE] != DramAttr->DramType) { Status = CB_DEVICE_ERROR; /* memory int error */ PRINT_DEBUG_MEM("Memory Device ERROR: DRAM " - "controller detected type != " - "type got from SPD\r"); + "controller detected type != " + "type got from SPD\r"); break; } DramAttr->DimmInfo[Sockets].bPresence = TRUE; @@ -150,36 +150,36 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) LoadNum = (u8) (ModuleDataWidth / ChipWidth);
/* Set the RANK map. */ - /* Get bit0,1, the most number of supported RANK is 2. */ + /* Get bit0,1, the most number of supported RANK is 2. */ RankNum = (u8) (pSPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x3); if (RAMTYPE_SDRAMDDR2 == DramAttr->DramType) - /* - * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK - * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK - */ + /* + * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK + * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK + */ RankNum++;
- /* Every DIMM have 1 or 2 ranks. */ + /* Every DIMM have 1 or 2 ranks. */ if (RankNum != 2 && RankNum != 1) { Status = CB_DEVICE_ERROR; PRINT_DEBUG_MEM("Memory Device ERROR: Number " - "of RANK not supported!\r"); + "of RANK not supported!\r"); break; }
if (Sockets < 2) { /* Sockets0,1 is channel A */ DramAttr->RankNumChA = - (u8) (DramAttr->RankNumChA + RankNum); + (u8) (DramAttr->RankNumChA + RankNum); DramAttr->DimmNumChA++; DramAttr->LoadNumChA = - (u8) (DramAttr->LoadNumChA * LoadNum * + (u8) (DramAttr->LoadNumChA * LoadNum * RankNum); } else { /* Sockets2,3 is channel B */ DramAttr->RankNumChB = - (u8) (DramAttr->RankNumChB + RankNum); + (u8) (DramAttr->RankNumChB + RankNum); DramAttr->DimmNumChB++; DramAttr->LoadNumChB = - (u8) (DramAttr->LoadNumChB * LoadNum * + (u8) (DramAttr->LoadNumChB * LoadNum * RankNum);; } RankNum |= 1; /* Set rank map. */ diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c index e3743e0..b8da58d 100644 --- a/src/northbridge/via/vx800/dev_init.c +++ b/src/northbridge/via/vx800/dev_init.c @@ -20,8 +20,8 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, u8 VirRank /* virtual rank */, BOOLEAN Enable); void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* Ending address - register number indicator (INDEX */, INT8 Value /* (value) - add or subtract value to this and after banks. */); + register number indicator (INDEX */, INT8 Value /* (value) + add or subtract value to this and after banks. */); void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr); void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); @@ -31,11 +31,11 @@ CB_STATUS VerifyChc(void); /*=================================================================== Function : DRAMRegInitValue() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Set necessary register before DRAM initialize + in MotherBoard +Output : Void +Purpose : Set necessary register before DRAM initialize ===================================================================*/
static const u8 DramRegTbl[][3] = { @@ -147,20 +147,20 @@ void DRAMRegInitValue(DRAM_SYS_ATTR *DramAttr) }
// Disable Read DRAM fast ready ;Rx51[7] - // Disable Read Around Write ;Rx51[6] + // Disable Read Around Write ;Rx51[6]
- // Disable Consecutive Read ;RX52[1:0] + // Disable Consecutive Read ;RX52[1:0] // Disable Speculative Read }
/*=================================================================== Function : DRAMInitializeProc() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : DRAM initialize according to the bios porting guid + in MotherBoard +Output : Void +Purpose : DRAM initialize according to the bios porting guid ===================================================================*/
#define EXIST_TEST_PATTERN 0x55555555 @@ -248,16 +248,16 @@ void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : DRAMSetVRNUM() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard + in MotherBoard PhyRank: Physical Rank number - VirRank: Virtual Rank number - Enable: Enable/Disable Physical Rank -Output : Void -Purpose : Set virtual rank number for physical rank - Program the specific physical rank with specific virtual rank number - Program when necessary, otherwise don't touch the pr-vr-mapping registers + VirRank: Virtual Rank number + Enable: Enable/Disable Physical Rank +Output : Void +Purpose : Set virtual rank number for physical rank + Program the specific physical rank with specific virtual rank number + Program when necessary, otherwise don't touch the pr-vr-mapping registers ===================================================================*/
void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, @@ -286,13 +286,13 @@ void DRAMSetVRNum(DRAM_SYS_ATTR *DramAttr, u8 PhyRank /* physical rank */, /*=================================================================== Function : SetEndingAddr() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard - VirRank: Virtual Rank number - Value: (value) add or subtract value to this and after banks -Output : Void -Purpose : Set ending address of virtual rank specified by VirRank + in MotherBoard + VirRank: Virtual Rank number + Value: (value) add or subtract value to this and after banks +Output : Void +Purpose : Set ending address of virtual rank specified by VirRank ===================================================================*/
void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address @@ -313,45 +313,45 @@ void SetEndingAddr(DRAM_SYS_ATTR *DramAttr, u8 VirRank /* ending address /*=================================================================== Function : InitDDR2() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Initialize DDR2 by standard sequence + in MotherBoard +Output : Void +Purpose : Initialize DDR2 by standard sequence ===================================================================*/
-// DLL: Enable Reset +// DLL: Enable Reset static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address)
-// CPU(DRAM) +// CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 CL=6(Burst type=interleave)(WR fine tune in code) +// DDR2 CL=2 CL=3 CL=4 CL=5 CL=6(Burst type=interleave)(WR fine tune in code) static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM
-// MA11 MA10(AP) MA9 +// MA11 MA10(AP) MA9 #define CHA_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h #define CHA_MRS_DDR2_TWR3 (0 << 13) + (1 << 20) + (0 << 12) // Value = 100000h #define CHA_MRS_DDR2_TWR4 (0 << 13) + (1 << 20) + (1 << 12) // Value = 101000h #define CHA_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHA_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h
-// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 static const u32 CHA_DDR2_Twr_table[5] = { CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4, CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6 };
#define CHA_OCD_Exit_150ohm 0x20200 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) +// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) #define CHA_OCD_Default_150ohm 0x21E00 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) +// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) #define CHA_OCD_Exit_75ohm 0x20020 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) +// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) #define CHA_OCD_Default_75ohm 0x21C20 // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address)
void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) { @@ -523,49 +523,49 @@ void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr) /*=================================================================== Function : InitDDR2_CHB() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Initialize DDR2 of CHB by standard sequence + in MotherBoard +Output : Void +Purpose : Initialize DDR2 of CHB by standard sequence Reference : ===================================================================*/ -/*// DLL: Enable Reset +/*// DLL: Enable Reset static const u32 CHB_MRS_DLL_150[2] = { 0x00020200 | (1 << 20), 0x00000800 }; // with 150 ohm (A17=1, A9=1), (A11=1)(cpu address) //u32 CHB_MRS_DLL_75[2] = { 0x00020020 | (1 << 20), 0x00000800 }; // with 75 ohm (A17=1, A5=1), (A11=1)(cpu address) // CPU(DRAM) // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 } // { DLL: reset. A11(MA8)=1 } // -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) +// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) static const u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 }; // BL=4 ;Use 1X-bandwidth MA table to init DRAM
-// MA11 MA10(AP) MA9 +// MA11 MA10(AP) MA9 #define CHB_MRS_DDR2_TWR2 (0 << 13) + (0 << 20) + (1 << 12) // Value = 001000h #define CHB_MRS_DDR2_TWR3 (0 << 13) + (1 << 20) + (0 << 12) // Value = 100000h #define CHB_MRS_DDR2_TWR4 (0 << 13) + (1 << 20) + (1 << 12) // Value = 101000h #define CHB_MRS_DDR2_TWR5 (1 << 13) + (0 << 20) + (0 << 12) // Value = 002000h #define CHB_MRS_DDR2_TWR6 (1 << 13) + (0 << 20) + (1 << 12) // Value = 003000h
-// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 +// DDR2 Twr=2 Twr=3 Twr=4 Twr=5 static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2, CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 };
#define CHB_OCD_Exit_150ohm 0x20200 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) +// A17=1, A12=A11=A10=0,A9=1 ,A5=0 (CPU address) #define CHB_OCD_Default_150ohm 0x21E00 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) -//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) -//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) -// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) +// A17=1, A12=A11=A10=1,A9=1 ,A5=0 (CPU address) +//#define CHB_OCD_Exit_75ohm 0x20020 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address) +// A17=1, A12=A11=A10=0,A9=0 ,A5=1 (CPU address) +//#define CHB_OCD_Default_75ohm 0x21C20 | (1 << 20) // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address) +// A17=1, A12=A11=A10=1,A9=0 ,A5=1 (CPU address) void InitDDR2CHB( - DRAM_SYS_ATTR *DramAttr - ) + DRAM_SYS_ATTR *DramAttr + )
{ - u8 Data; - u8 Idx, CL, BL, Twr; - u32 AccessAddr; + u8 Data; + u8 Idx, CL, BL, Twr; + u32 AccessAddr;
Data = 0x80; pci_write_config8(MEMCTRL, 0x54, Data); @@ -603,7 +603,7 @@ void InitDDR2CHB( // - <<< reduce BOOT UP time >>> - // Loop 200us for (Idx = 0; Idx < 0x10; Idx++) - WaitMicroSec(10); + WaitMicroSec(10);
// Step 8. // all banks precharge command enable @@ -709,7 +709,7 @@ void InitDDR2CHB( //repeat issue 8 CBR cycle, between each cycle stop 100us for (Idx = 0; Idx < 8; Idx++) { - // issue CBR cycle + // issue CBR cycle Data=pci_read_config8(MEMCTRL, 0xd3); Data &= 0x7F; pci_write_config8(MEMCTRL, 0xd3, Data); @@ -744,7 +744,7 @@ void InitDDR2CHB( AccessAddr = (u32)(CHB_DDR2_MRS_table[CL]); if (BL) { - AccessAddr += 8; + AccessAddr += 8; }
//Write recovery : really offset Rx63[7:5] @@ -875,14 +875,14 @@ void InitDDR2CHB( /*=================================================================== Function : InitDDR2CHC() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Initialize DDR2 of CHC by standard sequence + in MotherBoard +Output : Void +Purpose : Initialize DDR2 of CHC by standard sequence Reference : ===================================================================*/ -// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) +// DDR2 CL=2 CL=3 CL=4 CL=5 (Burst type=interleave)(WR fine tune in code) static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B }; // Use 1X-bandwidth MA table to init DRAM
void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr) diff --git a/src/northbridge/via/vx800/dqs_search.c b/src/northbridge/via/vx800/dqs_search.c index a9d0b27..37b4d90 100644 --- a/src/northbridge/via/vx800/dqs_search.c +++ b/src/northbridge/via/vx800/dqs_search.c @@ -23,15 +23,15 @@ void SetDQSOutputCHB(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMDQSOutputSearchCHA() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : set DQS output delay register reg70 and DQ output delay register reg71 + in MotherBoard +Output : Void +Purpose : set DQS output delay register reg70 and DQ output delay register reg71 ===================================================================*/
-#define CH_A 0 -#define CH_B 1 +#define CH_A 0 +#define CH_B 1 void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr) { if (DramAttr->RankNumChA > 0) @@ -41,11 +41,11 @@ void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : SetDQSOutputCHA() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : according the frequence set CHA DQS output + in MotherBoard +Output : Void +Purpose : according the frequence set CHA DQS output ===================================================================*/ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) { @@ -75,17 +75,17 @@ void SetDQSOutputCHA(DRAM_SYS_ATTR * DramAttr) }
//################ -// STEP 12 # +// STEP 12 # //################
/*=================================================================== Function : DRAMDQSInputSearch() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : search DQS input delay for CHA/CHB + in MotherBoard +Output : Void +Purpose : search DQS input delay for CHA/CHB ===================================================================*/
void DRAMDQSInputSearch(DRAM_SYS_ATTR * DramAttr) diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h index c1cb9fb..2daee75 100644 --- a/src/northbridge/via/vx800/dram_init.h +++ b/src/northbridge/via/vx800/dram_init.h @@ -46,66 +46,66 @@
//Dram Type #define RAMTYPE_FPMDRAM 1 -#define RAMTYPE_EDO 2 +#define RAMTYPE_EDO 2 #define RAMTYPE_PipelinedNibble 3 -#define RAMTYPE_SDRAM 4 -#define RAMTYPE_ROM 5 +#define RAMTYPE_SDRAM 4 +#define RAMTYPE_ROM 5 #define RAMTYPE_SGRAMDDR 6 #define RAMTYPE_SDRAMDDR 7 #define RAMTYPE_SDRAMDDR2 8
/* CAS latency constant */ -#define CASLAN_15 15 -#define CASLAN_2 20 -#define CASLAN_25 25 -#define CASLAN_3 30 -#define CASLAN_35 35 -#define CASLAN_4 40 -#define CASLAN_45 45 -#define CASLAN_5 50 -#define CASLAN_NULL 00 +#define CASLAN_15 15 +#define CASLAN_2 20 +#define CASLAN_25 25 +#define CASLAN_3 30 +#define CASLAN_35 35 +#define CASLAN_4 40 +#define CASLAN_45 45 +#define CASLAN_5 50 +#define CASLAN_NULL 00
//Burst length -#define BURSTLENGTH8 8 -#define BURSTLENGTH4 4 +#define BURSTLENGTH8 8 +#define BURSTLENGTH4 4
//Data Width -//#define DATAWIDTHX16 16 -//#define DATAWIDTHX8 8 -//#define DATAWIDTHX4 4 - -#define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ -#define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ -#define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ -#define SPD_SDRAM_DIMM_RANKS 5 /*Number of RANKS on this assembly */ +//#define DATAWIDTHX16 16 +//#define DATAWIDTHX8 8 +//#define DATAWIDTHX4 4 + +#define SPD_MEMORY_TYPE 2 /*Memory type FPM,EDO,SDRAM,DDR,DDR2 */ +#define SPD_SDRAM_ROW_ADDR 3 /*Number of row addresses on this assembly */ +#define SPD_SDRAM_COL_ADDR 4 /*Number of column addresses on this assembly */ +#define SPD_SDRAM_DIMM_RANKS 5 /*Number of RANKS on this assembly */ #define SPD_SDRAM_MOD_DATA_WIDTH 6 /*Data width of this assembly */ -#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL=X) */ -#define SPD_SDRAM_TAC_X 10 /*Access time for highest CL */ -#define SPD_SDRAM_CONFIG_TYPE 11 /*Non-parity , Parity or ECC */ -#define SPD_SDRAM_REFRESH 12 /*Refresh rate/type */ -#define SPD_SDRAM_WIDTH 13 /*Primary sdram width */ -#define SPD_SDRAM_MIN_CLK_DLY 15 /*Minimum clock delay */ -#define SPD_SDRAM_BURSTLENGTH 16 /*Burst Lengths supported */ -#define SPD_SDRAM_NO_OF_BANKS 17 /*Number of banks on this assembly */ -#define SPD_SDRAM_CAS_LATENCY 18 /*CAS latency */ +#define SPD_SDRAM_TCLK_X 9 /*Cycle time at Maximum supported CAS latency (CL=X) */ +#define SPD_SDRAM_TAC_X 10 /*Access time for highest CL */ +#define SPD_SDRAM_CONFIG_TYPE 11 /*Non-parity , Parity or ECC */ +#define SPD_SDRAM_REFRESH 12 /*Refresh rate/type */ +#define SPD_SDRAM_WIDTH 13 /*Primary sdram width */ +#define SPD_SDRAM_MIN_CLK_DLY 15 /*Minimum clock delay */ +#define SPD_SDRAM_BURSTLENGTH 16 /*Burst Lengths supported */ +#define SPD_SDRAM_NO_OF_BANKS 17 /*Number of banks on this assembly */ +#define SPD_SDRAM_CAS_LATENCY 18 /*CAS latency */ #define SPD_SDRAM_DIMM_TYPE_DDR2 20 /*DIMM type information; identifies the DDR2 memory module type */ -#define SPD_SDRAM_DEV_ATTR_DDR1 20 /*WE latency */ -#define SPD_SDRAM_MODULES_ATTR 21 /*This byte depicts various aspects of the modules; DDR DDR2 have different aspects */ -#define SPD_SDRAM_DEV_ATTR_GEN 22 /*General device attributes */ -#define SPD_SDRAM_TCLK_X_1 23 /*Minimum clock cycle time at Reduced CL, DDR: X-0.5 DDR2: X-1 */ -#define SPD_SDRAM_TAC_X_1 24 /*Maximum Data Access time from Clock at reduced CL,DDR: X-0.5 DDR2: X-1 */ -#define SPD_SDRAM_TCLK_X_2 25 /*Minimum clock cycle time at reduced CL, DDR: X-1 DDR2: X-2 */ -#define SPD_SDRAM_TAC_X_2 26 /*Maximum Data Access time from Clock at reduced CL, DDR: X-1 DDR2: X-2 */ -#define SPD_SDRAM_TRP 27 /*minimum row precharge time */ -#define SPD_SDRAM_TRRD 28 /*minimum row active to row active delay */ -#define SPD_SDRAM_TRCD 29 /*minimum RAS to CAS delay */ -#define SPD_SDRAM_TRAS 30 /*minimum active to precharge time */ -#define SPD_SDRAM_TWR 36 /*write recovery time, only DDR2 use it */ -#define SPD_SDRAM_TWTR 37 /*internal write to read command delay, only DDR2 use it */ -#define SPD_SDRAM_TRTP 38 /*internal read to prechange command delay, only DDR2 use it */ -#define SPD_SDRAM_TRFC2 40 /*extension of byte 41 tRC and byte 42 tRFC, only DDR2 use it */ +#define SPD_SDRAM_DEV_ATTR_DDR1 20 /*WE latency */ +#define SPD_SDRAM_MODULES_ATTR 21 /*This byte depicts various aspects of the modules; DDR DDR2 have different aspects */ +#define SPD_SDRAM_DEV_ATTR_GEN 22 /*General device attributes */ +#define SPD_SDRAM_TCLK_X_1 23 /*Minimum clock cycle time at Reduced CL, DDR: X-0.5 DDR2: X-1 */ +#define SPD_SDRAM_TAC_X_1 24 /*Maximum Data Access time from Clock at reduced CL,DDR: X-0.5 DDR2: X-1 */ +#define SPD_SDRAM_TCLK_X_2 25 /*Minimum clock cycle time at reduced CL, DDR: X-1 DDR2: X-2 */ +#define SPD_SDRAM_TAC_X_2 26 /*Maximum Data Access time from Clock at reduced CL, DDR: X-1 DDR2: X-2 */ +#define SPD_SDRAM_TRP 27 /*minimum row precharge time */ +#define SPD_SDRAM_TRRD 28 /*minimum row active to row active delay */ +#define SPD_SDRAM_TRCD 29 /*minimum RAS to CAS delay */ +#define SPD_SDRAM_TRAS 30 /*minimum active to precharge time */ +#define SPD_SDRAM_TWR 36 /*write recovery time, only DDR2 use it */ +#define SPD_SDRAM_TWTR 37 /*internal write to read command delay, only DDR2 use it */ +#define SPD_SDRAM_TRTP 38 /*internal read to prechange command delay, only DDR2 use it */ +#define SPD_SDRAM_TRFC2 40 /*extension of byte 41 tRC and byte 42 tRFC, only DDR2 use it */ #define SPC_SDRAM_TRC 41 /*minimum active to active/refresh time */ -#define SPD_SDRAM_TRFC 42 /*minimum refresh to active / refresh command period */ +#define SPD_SDRAM_TRFC 42 /*minimum refresh to active / refresh command period */
#define SPD_DATA_SIZE 44 //Dram cofig are @@ -137,17 +137,17 @@ typedef struct _DRAM_CONFIG_DATA {
u8 CmdRate; u8 DualEn; - //u8 IntLv0; - //u8 IntLv1; - //u8 Ba0Sel; - //u8 Ba1Sel; - //u8 Ba2Sel; + //u8 IntLv0; + //u8 IntLv1; + //u8 Ba0Sel; + //u8 Ba1Sel; + //u8 Ba2Sel; u8 BaScmb; u8 DrdyTiming; - //u8 Above4G; - //u8 RdsaitMode; - //u8 Rdsait; - //u8 TopPerf; + //u8 Above4G; + //u8 RdsaitMode; + //u8 Rdsait; + //u8 TopPerf;
u16 UMASize; } DRAM_CONFIG_DATA; @@ -174,7 +174,7 @@ typedef struct _DRAM_SYS_ATTR_tag { u16 DramFreq; u16 DramCyc; /*10ns, 7.5ns, 6ns, 5ns, 3.75ns, 3ns, 2.5ns =1/SysFreq, unit: 100*ns. */
- //u16 HFreq; /*100, 133, 166, 200, 266, 333, 400*/ + //u16 HFreq; /*100, 133, 166, 200, 266, 333, 400*/
u8 CL; /* CAS lantency */ u8 CmdRate; /*1T or 2T */ diff --git a/src/northbridge/via/vx800/dram_util.c b/src/northbridge/via/vx800/dram_util.c index d65cb44..5893856 100644 --- a/src/northbridge/via/vx800/dram_util.c +++ b/src/northbridge/via/vx800/dram_util.c @@ -31,10 +31,10 @@ void WaitMicroSec(UINTN MicroSeconds) /*=================================================================== Function : via_write_phys() Precondition : -Input : addr - value -Output : void -Purpose : +Input : addr + value +Output : void +Purpose : Reference : None ===================================================================*/
@@ -48,9 +48,9 @@ void via_write_phys(volatile u32 addr, volatile u32 value) /*=================================================================== Function : via_read_phys() Precondition : -Input : addr -Output : u32 -Purpose : +Input : addr +Output : u32 +Purpose : Reference : None ===================================================================*/
@@ -64,9 +64,9 @@ u32 via_read_phys(volatile u32 addr) /*=================================================================== Function : DimmRead() Precondition : -Input : x -Output : u32 -Purpose : +Input : x +Output : u32 +Purpose : Reference : None ===================================================================*/
@@ -81,12 +81,12 @@ u32 DimmRead(volatile u32 x) /*=================================================================== Function : DramBaseTest() Precondition : this function used to verify memory -Input : - BaseAdd, - length, - mode -Output : u32 -Purpose :write into and read out to verify if dram is correct +Input : + BaseAdd, + length, + mode +Output : u32 +Purpose :write into and read out to verify if dram is correct Reference : None ===================================================================*/ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, @@ -171,12 +171,12 @@ BOOLEAN DramBaseTest(u32 BaseAdd, u32 Length, /*=================================================================== Function : DumpRegisters() Precondition : -Input : - pPCIPPI, - DevNum, - FuncNum -Output : Void -Purpose : +Input : + pPCIPPI, + DevNum, + FuncNum +Output : Void +Purpose : Reference : None ===================================================================*/
@@ -197,7 +197,7 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) for (j = 0; j < 0x10; j++) { ByteVal = pci_read_config8(PCI_DEV(0, DevNum, FuncNum), - i * 0x10 + j); + i * 0x10 + j); PRINT_DEBUG_MEM_HEX8(ByteVal); PRINT_DEBUG_MEM(" ");
@@ -210,11 +210,11 @@ void DumpRegisters(INTN DevNum, INTN FuncNum) /*=================================================================== Function : dumpnorth() Precondition : -Input : - pPCIPPI, - Func -Output : Void -Purpose : +Input : + pPCIPPI, + Func +Output : Void +Purpose : Reference : None ===================================================================*/
diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c index 40f378c..5311c47 100644 --- a/src/northbridge/via/vx800/drdy_bl.c +++ b/src/northbridge/via/vx800/drdy_bl.c @@ -20,61 +20,61 @@ // Set P6IF DRDY Timing // Because there are 1.5T & 2.5T CAS latency in DDR1 mode, we need to use RDELAYMD-0 // -// Entry: -// EBP[29:25] = DRAM Speed, Dual_Channel -// VIA_NB2HOST_REG54[7:5] Host Frequency -// VIA_NB3DRAM_REG62[2:0] CAS Latency +// Entry: +// EBP[29:25] = DRAM Speed, Dual_Channel +// VIA_NB2HOST_REG54[7:5] Host Frequency +// VIA_NB3DRAM_REG62[2:0] CAS Latency // -// Modify NB_Reg: -// VIA_NB2HOST_REG54[3,1] -// VIA_NB2HOST_REG55[1] -// VIA_NB2HOST_REG60 -// VIA_NB2HOST_REG61 -// VIA_NB2HOST_REG62[3:0] -// VIA_NB2HOST_REG63 -// VIA_NB2HOST_REG64 -// VIA_NB2HOST_REG65[3:0] -// VIA_NB2HOST_REG66 -// VIA_NB2HOST_REG67[5:4] +// Modify NB_Reg: +// VIA_NB2HOST_REG54[3,1] +// VIA_NB2HOST_REG55[1] +// VIA_NB2HOST_REG60 +// VIA_NB2HOST_REG61 +// VIA_NB2HOST_REG62[3:0] +// VIA_NB2HOST_REG63 +// VIA_NB2HOST_REG64 +// VIA_NB2HOST_REG65[3:0] +// VIA_NB2HOST_REG66 +// VIA_NB2HOST_REG67[5:4] // // Processing: //-------------------------------------------------------------------------- // P6IF DRDY Timing Control: // *Following algorithm to set DRDY timing -// Set P6IF DRDY Timing by the following 3 conditions: +// Set P6IF DRDY Timing by the following 3 conditions: // 1. RDELAYMD -// a.RDRPH(MD input internal timing control) +// a.RDRPH(MD input internal timing control) // b.CAS Latency // RDELAYMD(1bit) = bit0 of (CL + RDRPH) -// for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD=1 (bit0) -// RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0) +// for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b = 101b, RDELAYMD=1 (bit0) +// RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0) // 2. CPU Frequency // 3. DRAM Frequency // // According to above conditions, we create different tables: -// 1. RDELAYMD=0 : for integer CAS latency(ex. CL=3) -// 2. RDELAYMD=1 : for non-integer CAS latency(ex. CL=2.5) +// 1. RDELAYMD=0 : for integer CAS latency(ex. CL=3) +// 2. RDELAYMD=1 : for non-integer CAS latency(ex. CL=2.5) // 3. Normal performance // 4. Top performance : -// Using phase0 to a case has better performance. +// Using phase0 to a case has better performance. // -// Note: The setting are related to performance and maybe affect DRAM initialize. -// Turn OFF(F2_Rx51[7]=0) this feature at csDRAMRegInitValueJ procedure. -// Turn ON(F2_Rx51[7]=1) this feature at csDRAMRegFinalValueJ procedure. +// Note: The setting are related to performance and maybe affect DRAM initialize. +// Turn OFF(F2_Rx51[7]=0) this feature at csDRAMRegInitValueJ procedure. +// Turn ON(F2_Rx51[7]=1) this feature at csDRAMRegFinalValueJ procedure. // -// If F2_Rx51[7]=0, then CPU always wait 8QW, a slower but most stable way -// If F2_Rx51[7]=1, then the timing will refer to F2_Rx60 ~ F2_Rx67, +// If F2_Rx51[7]=0, then CPU always wait 8QW, a slower but most stable way +// If F2_Rx51[7]=1, then the timing will refer to F2_Rx60 ~ F2_Rx67, // a fast way but may cause the system to be unstable. // // Coding: -// 1. RDELAYMD and user's option for performance can determine which table -// 2. CPU Frequency can get block offset of table -// 3. DRAM Frequency can get row offset of block +// 1. RDELAYMD and user's option for performance can determine which table +// 2. CPU Frequency can get block offset of table +// 3. DRAM Frequency can get row offset of block // 4. Set value // -// PS: Fun2 Rx62, Rx65, Rx67 are don't care bits in 3296, CPU 266MHz doesn't be supported by 3296, -// but I still keep these bits in table to avoid the usage in future -// and do the fewest modification for code. +// PS: Fun2 Rx62, Rx65, Rx67 are don't care bits in 3296, CPU 266MHz doesn't be supported by 3296, +// but I still keep these bits in table to avoid the usage in future +// and do the fewest modification for code. //
// Early 3T @@ -98,7 +98,7 @@ #define Rx54E0T P6IF_Misc_RFASTH #define Rx55E0T P6IF_Misc2_RRRDYH3E + P6IF_Misc2_RHTSEL
-// Latter 1T +// Latter 1T #define Rx54L1T P6IF_Misc_RFASTH #define Rx55L1T P6IF_Misc2_RHTSEL
@@ -151,9 +151,9 @@
static const u8 PT894_128bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- -// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM -// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E -// RCONV RHTSEL +// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM +// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E +// RCONV RHTSEL // ----------------------------------------------------------------------------------------------------------------- { // cpu100 @@ -214,9 +214,9 @@ static const u8 PT894_128bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
static const u8 PT894_128bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- -// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM -// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E -// RCONV RHTSEL +// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM +// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E +// RCONV RHTSEL // ----------------------------------------------------------------------------------------------------------------- { // cpu100 @@ -277,9 +277,9 @@ static const u8 PT894_128bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- -// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM -// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E -// RCONV RHTSEL +// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM +// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E +// RCONV RHTSEL // ----------------------------------------------------------------------------------------------------------------- { // cpu100 @@ -308,7 +308,7 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] = {PH2_2_2_2, PH0_0_2_2, PH0_0_0_0, PH1_1_1_1, PH0_0_1_1, PH0_0_0_0, 0x3f, 0x00, Rx54E3T, Rx55E3T}, // 200/200 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E1T, Rx55E1T}, // 200/266 {PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 0x00, 0x00, Rx54E3T, Rx55E3T} // 200/333 -// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T ;200/266 +// DDR2 Both E3T and E2T Fail, need set to E1T, db PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, PH0_0_0_0, 00110011b, 00000000b, Rx54E3T, Rx55E3T ;200/266 }, // cpu166 { @@ -341,9 +341,9 @@ static const u8 PT894_64bit_DELAYMD0_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] = // ----------------------------------------------------------------------------------------------------------------- -// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM -// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E -// RCONV RHTSEL +// RX60 RX61 RX62 RX63 RX64 RX65 RX66 RX67 RX54[3,1] RX55[3,1] CPU/DRAM +// LN4:1 LN8:5 LN10:9 QW4:1 QW8:5 QW10:9 WS8:1 WS10:9 RFASTH RRRDYH3E +// RCONV RHTSEL // ----------------------------------------------------------------------------------------------------------------- { // cpu100 @@ -567,8 +567,8 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) if (DramAttr->DimmInfo[Sockets].bPresence) { BL &= (DramAttr-> - DimmInfo[Sockets].SPDDataBuf - [SPD_SDRAM_BURSTLENGTH]); + DimmInfo[Sockets].SPDDataBuf + [SPD_SDRAM_BURSTLENGTH]); } }
diff --git a/src/northbridge/via/vx800/driving_clk_phase_data.h b/src/northbridge/via/vx800/driving_clk_phase_data.h index ebc82be..b4ab015 100644 --- a/src/northbridge/via/vx800/driving_clk_phase_data.h +++ b/src/northbridge/via/vx800/driving_clk_phase_data.h @@ -48,7 +48,7 @@ //extern u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width]; //extern u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width];
-#define WrtData_REG_NUM 4 +#define WrtData_REG_NUM 4 #define WrtData_FREQ_NUM 6 //extern u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; //extern u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM]; @@ -57,8 +57,8 @@ //extern u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width]; //extern u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width];
-#define DQS_INPUT_CAPTURE_REG_NUM 3 -#define DQS_INPUT_CAPTURE_FREQ_NUM 6 +#define DQS_INPUT_CAPTURE_REG_NUM 3 +#define DQS_INPUT_CAPTURE_FREQ_NUM 6 //extern u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM]; //extern u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM];
diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c index 695fcab..7e3c68f 100644 --- a/src/northbridge/via/vx800/driving_setting.c +++ b/src/northbridge/via/vx800/driving_setting.c @@ -65,7 +65,7 @@ Processing: According to DRAM frequency to ODT control bits. the last register to be programmed. */ //------------------------------------------------------------------------------- -// ODT Lookup Table +// ODT Lookup Table //------------------------------------------------------------------------------- #define Rank0_ODT 0 #define Rank1_ODT 1 @@ -79,15 +79,15 @@ Processing: According to DRAM frequency to ODT control bits. #define DDR2_ODT_150ohm 0x40
// Setting of ODT Lookup TBL -// RankMAP , Rank 3 Rank 2 Rank 1 Rank 0 , DRAM & NB ODT setting -// db 0000b , Reserved +// RankMAP , Rank 3 Rank 2 Rank 1 Rank 0 , DRAM & NB ODT setting +// db 0000b , Reserved #define ODTLookup_Tbl_count 8 static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { // 0001b {0x01, (Rank3_ODT << 6) + (Rank2_ODT << 4) + (Rank1_ODT << 2) + Rank0_ODT, DDR2_ODT_150ohm + NB_ODT_75ohm}, - // 0010b , Reserved + // 0010b , Reserved // 0011b {0x03, (Rank3_ODT << 6) + (Rank2_ODT << 4) + (Rank0_ODT << 2) + @@ -100,15 +100,15 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { {0x05, (Rank3_ODT << 6) + (Rank0_ODT << 4) + (Rank1_ODT << 2) + Rank2_ODT, DDR2_ODT_75ohm + NB_ODT_150ohm}, - // 0110b , Reserved + // 0110b , Reserved // 0111b {0x07, (Rank3_ODT << 6) + (Rank0_ODT << 4) + (Rank2_ODT << 2) + Rank2_ODT, DDR2_ODT_75ohm + NB_ODT_150ohm}, - // 1000b , Reserved - // 1001b , Reserved - // 1010b , Reserved - // 1011b , Reserved + // 1000b , Reserved + // 1001b , Reserved + // 1010b , Reserved + // 1011b , Reserved // 1100b {0x0c, (Rank2_ODT << 6) + (Rank3_ODT << 4) + (Rank1_ODT << 2) + @@ -117,7 +117,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { {0x0d, (Rank0_ODT << 6) + (Rank0_ODT << 4) + (Rank1_ODT << 2) + Rank2_ODT, DDR2_ODT_75ohm + NB_ODT_150ohm}, - // 1110b , Reserved + // 1110b , Reserved // 1111b {0x0f, (Rank0_ODT << 6) + (Rank0_ODT << 4) + (Rank2_ODT << 2) + @@ -125,7 +125,7 @@ static const u8 ODTLookup_TBL[ODTLookup_Tbl_count][3] = { };
#define ODT_Table_Width_DDR2 4 -// RxD6 RxD3 +// RxD6 RxD3 static const u8 ODT_Control_DDR2[ODT_Table_Width_DDR2] = { 0xFC, 0x01 };
void DrivingODT(DRAM_SYS_ATTR * DramAttr) @@ -201,14 +201,14 @@ void DrivingODT(DRAM_SYS_ATTR * DramAttr) bFound = FALSE; for (i = 0; i < ODTLookup_Tbl_count; i++) { if ((DramAttr->RankPresentMap & 0x0F) == - ODTLookup_TBL[i][0]) { + ODTLookup_TBL[i][0]) { Data = ODTLookup_TBL[i][1]; bFound = TRUE; } } if (!bFound) { /*set default value */ Data = - ODTLookup_TBL[ODTLookup_Tbl_count - 1][1]; + ODTLookup_TBL[ODTLookup_Tbl_count - 1][1]; } pci_write_config8(MEMCTRL, 0x9c, Data);
diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index b3ebde1..5e504ed 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -88,7 +88,7 @@ void enable_vx800_serial(void) // Set 115 kb vx800_writesioword(0x3f8, 1); // Set 9.6 kb - // WRITESIOWORD(0x3f8, 12) + // WRITESIOWORD(0x3f8, 12) // now set no parity, one stop, 8 bits vx800_writesiobyte(0x3fb, 3); // now turn on RTS, DRT diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c index f9b13eb..47ae024 100644 --- a/src/northbridge/via/vx800/early_smbus.c +++ b/src/northbridge/via/vx800/early_smbus.c @@ -60,7 +60,7 @@ /* Internal functions */ static void smbus_print_error(unsigned char host_status_register, int loops) { -// print_err("some i2c error\n"); +// print_err("some i2c error\n"); /* Check if there actually was an error */ if (host_status_register == 0x00 || host_status_register == 0x40 || host_status_register == 0x42) @@ -173,8 +173,8 @@ void enable_smbus(void) * known-good data from a slot/address. Exits on either good data or a timeout. * * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. + * be created just for it. If some other chip needs/wants it, we can + * worry about it then. * * @param mem_ctrl The memory controller and SMBus addresses. */ @@ -197,15 +197,15 @@ void smbus_fixup(const struct mem_controller *mem_ctrl) * VT8237R has only been seen on DDR and DDR2 based systems, so far. */ for (i = 0; (i < SMBUS_TIMEOUT && ((result < SPD_MEMORY_TYPE_SDRAM) || - (result > - SPD_MEMORY_TYPE_SDRAM_DDR3))); + (result > + SPD_MEMORY_TYPE_SDRAM_DDR3))); i++) {
if (current_slot > ram_slots) current_slot = 0;
result = get_spd_data(mem_ctrl->channel0[current_slot], - SPD_MEMORY_TYPE); + SPD_MEMORY_TYPE); current_slot++; PRINT_DEBUG("."); } diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index 3f9c70f..cc91ef0 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -46,9 +46,9 @@ static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = { {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00}, {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1}, {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, ///// End of 2008-04-17
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table @@ -175,8 +175,8 @@ static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion - // {Â 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. - // {Â 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) + // {Â 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. + // {Â 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) //(2)Configure D19F0 { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 },
@@ -245,7 +245,7 @@ void AcpiInit(void) rawdevice = PCI_RAWDEV(0, 0x11, 0); // Set the PMIO base io address pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE, - 0xff80); + 0xff80); // Enable PMIO pci_rawmodify_config16(rawdevice, 0x80, 0x8000, 0x8000); // Enable Soft Resume @@ -293,7 +293,7 @@ void IDECSupportOption(u8 sbchiprev) pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00);
pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE -// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE +// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE
via_pci_inittable(sbchiprev, IDEC_INIT); } @@ -311,9 +311,9 @@ void InitUHCI(u8 Number, u8 bEnable) u8 BitShift; // USB Device 16 // Function : Number - // 0 : 0 - // 1 : 1 - // 2 : 2 + // 0 : 0 + // 1 : 1 + // 2 : 2 // The BitShift is got from Datasheet.
switch (Number) { @@ -345,18 +345,18 @@ void InitUHCI(u8 Number, u8 bEnable) if (bEnable) { D16 = 0; pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x20, D16); + 0x20, D16);
// Config some Control Register Mask = 0x00; Value = 0x12;
pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x41, Value, Mask); + 0x41, Value, Mask); Mask = 0x00; Value = 0xEB; pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x4B, Value, Mask); + 0x4B, Value, Mask); } return; } @@ -464,9 +464,9 @@ void HpetInit(void) u8 HpetEnable = HPET_ENABLE_BIT; u16 HpetBase = HPET_BASE_ADDRESS; pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL, - HpetEnable); + HpetEnable); pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), - R_SB_HPET_ADDRESS + 1, HpetBase); + R_SB_HPET_ADDRESS + 1, HpetBase); }
static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { @@ -510,8 +510,8 @@ void InitPMU(u8 sbchiprev) #define R_SB_MULTI_FUNCTION_SELECT_1 0xE4 #define R_SB_CX_STATE_BREAK_EVENT_ENABLE_1 0xE6 #define PMIO_PROCESSOR_CONTROL 0x26 -#define R_SB_PCI_ARBITRATION_2 0x76 -#define R_SB_AUTO_SWITCH_P_STATE 0x8A +#define R_SB_PCI_ARBITRATION_2 0x76 +#define R_SB_AUTO_SWITCH_P_STATE 0x8A
void InitCPUCStatueSupport() { @@ -526,7 +526,7 @@ void InitCPUCStatueSupport() Mask = 0xFF; Value = 0x1F; io_rawmodify_config8(VX800_ACPI_IO_BASE + PMIO_PROCESSOR_CONTROL, - Value, Mask); + Value, Mask);
Mask = 0x00; Value = 0x80; @@ -623,7 +623,7 @@ void main(void) pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, - pci_rawread_config8(PCI_RAWDEV(0, 3, 0), + pci_rawread_config8(PCI_RAWDEV(0, 3, 0), 0x88)); #endif
@@ -656,7 +656,7 @@ void main(void) y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } @@ -703,7 +703,7 @@ void main(void) post_code(0x89); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
-// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); +// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
#if 0 x = y = 0; @@ -933,17 +933,17 @@ void main(void) #if 1 for (i = 0; i < 9; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); + d0f2pcitable[i]); } - //9 is warm reset reg, // boot err in coreboot + //9 is warm reset reg, // boot err in coreboot for (i = 10; i < 64; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); + d0f2pcitable[i]); } - //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. + //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. for (i = 65; i < 113; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); + d0f2pcitable[i]); } #endif #ifdef OPTION_1 @@ -961,12 +961,12 @@ void main(void)
//d0f3 /* */ - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 + // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 //set bit4 cause the ide not be found -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); +// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); //set bit1 cause the ide not be found
-// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); +// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12);
@@ -977,7 +977,7 @@ void main(void) #if 1 for (i = 0; i < 99; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d, - d0f4pcitable[i]); + d0f4pcitable[i]); } #endif
@@ -993,19 +993,19 @@ void main(void) //boot ok, resume still err in linux for (i = 0; i < 160; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60, - d0f5pcitable[i]); + d0f5pcitable[i]); } for (i = 0; i < 144; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60, - d0f7pcitable[i]); + d0f7pcitable[i]); } for (i = 0; i < 3; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0, - d1f0pcitable[i]); + d1f0pcitable[i]); } for (i = 0; i < 96; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40, - dcf0pcitable[i]); + dcf0pcitable[i]); } #endif
@@ -1026,10 +1026,10 @@ void main(void) pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
//boot ok, resume still err in linux, and if disable USB, then all ok -// for(i=0;i<48;i++){ +// for(i=0;i<48;i++){ for (i = 0; i < 44; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40, - d10f4pcitable[i]); + d10f4pcitable[i]); } #endif
@@ -1043,42 +1043,42 @@ void main(void)
#if 1 //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok -// for(i=0;i<192;i++){ +// for(i=0;i<192;i++){ for (i = 0; i < 6; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
//7-18 is my familar part for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); }
for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# for (i = 24; i < 27; i++) { //sleep ok , resume sleep err 1 resume 1 pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //5b port 80h pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08); - // i++; - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]); + // i++; + // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]);
for (i = 28; i < 72; i++) { //sleep ok , resume sleep err 1 , resume 1ci pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //7273ACPI BASE
for (i = 74; i < 112; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); }
//B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) @@ -1093,57 +1093,57 @@ void main(void)
for (i = 113; i < 114; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); }
for (i = 115; i < 116; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); }
for (i = 118; i < 192; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } #endif #ifdef NOOPTION_1 -// for(i=0;i<192;i++){ +// for(i=0;i<192;i++){ for (i = 0; i < 6; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); } //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail
//7-18 is my familar part - for (i = 7; i < 18; i++) { // sleep err 2 + for (i = 7; i < 18; i++) { // sleep err 2 pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); }
for (i = 18; i < 21; i++) { //sleep ok , resume ??? pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# for (i = 24; i < 27; i++) { //sleep ok , resume ??? pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); + d11f0pcitable[i]); } //5b port 80h i++; pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]);
for (i = 28; i < 72; i++) { //sleep ok , resume??? pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); } //7273ACPI BASE
for (i = 74; i < 112; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); }
//B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) @@ -1158,38 +1158,38 @@ void main(void)
for (i = 113; i < 114; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); }
for (i = 115; i < 116; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); }
for (i = 118; i < 192; i++) { //boot ok, resume still err in linux pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); + OPTION_1_d11f0pcitable[i]); } #endif
#if 1 pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); + PCI_DEVICE_ID_VIA_VX855_IDE); pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0, - PCI_VENDOR_ID_VIA); + PCI_VENDOR_ID_VIA); pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79); i &= ~0x40; i |= 0x40; pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i); pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); + PCI_DEVICE_ID_VIA_VX855_LPC);
//boot ok, resume still err in linux for (i = 0; i < 192; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, - d11f7pcitable[i]); + d11f7pcitable[i]); } #endif #ifdef OPTION_1 @@ -1228,7 +1228,7 @@ void main(void) y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_read_config8(dev, x * 16 + y)); + pci_read_config8(dev, x * 16 + y)); } printk(BIOS_INFO, "\n"); } diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c index c62de6e..2ae2ac7 100644 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c @@ -23,7 +23,7 @@ // DQS Driving //Reg0xE0, 0xE1 // According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 +// #Bank 1 2 3 4 5 6 7 8 static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE}; static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE};
@@ -37,7 +37,7 @@ static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; // CS Driving //Reg0xE4, 0xE5 // According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 +// DDR1 #Bank 1 2 3 4 5 6 7 8 static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44}; static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44}; @@ -46,24 +46,24 @@ static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44}; //Reg0xE8, Reg0xE9 static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = { - //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ + //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 + { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 + { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 + {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ };
static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - { 6, 0x86 }, // total MAB chips = 00 ~ 06 - { 18, 0x86 }, // total MAB chips = 06 ~ 18 - {255, 0xDB } // total MAB chips = 18 ~ + // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 + { 6, 0x86 }, // total MAB chips = 00 ~ 06 + { 18, 0x86 }, // total MAB chips = 06 ~ 18 + {255, 0xDB } // total MAB chips = 18 ~ };
// DCLK Driving //Reg0xE6, 0xE7 // For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M +// freq 400M, 533M, 667M, 800M
static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; @@ -76,20 +76,20 @@ According to DRAM frequency to control Duty Cycle */ static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank + {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, + {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} };
static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank + {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } };
@@ -104,38 +104,38 @@ Processing: */ static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } };
static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank + {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, + {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } };
/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } + {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, + {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } };*/
static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank + {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, + {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } };
/* @@ -144,30 +144,30 @@ Modify NB Reg: Rx74/Rx75/Rx76 */ /*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank + {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, + {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } };*/
static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank + {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, + {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, + {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } };
/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank + {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, + {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } }; */ /* @@ -176,19 +176,19 @@ Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 */ static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - // RxF0 RxF1 RxF2 RxF3 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 + // RxF0 RxF1 RxF2 RxF3 + { 0x00, 0x00, 0x00, 0x00 },// DDR400 + { 0x00, 0x00, 0x00, 0x00 },// DDR533 + { 0x00, 0x00, 0x00, 0x00 },// DDR667 + { 0x00, 0x00, 0x00, 0x00 }// DDR800 }; static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = { - // RxF4 RxF5 RxF6 RxF7 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 + // RxF4 RxF5 RxF6 RxF7 + { 0x00, 0x00, 0x00, 0x00 },// DDR400 + { 0x00, 0x00, 0x00, 0x00 },// DDR533 + { 0x00, 0x00, 0x00, 0x00 },// DDR667 + { 0x00, 0x00, 0x00, 0x00 }// DDR800 };
/* @@ -198,30 +198,30 @@ modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } };*/
static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank + {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, + {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } };
static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } + // (And NOT) DDR800 DDR667 DDR533 DDR400 + //Reg Mask Value Value Value Value + {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank + {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, + {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } };
static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index b629137..0d189cf 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -46,7 +46,7 @@ static int acpi_is_wakeup_early_via_vx800(void) print_debug("In acpi_is_wakeup_early_via_vx800\n"); /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); + PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID) die("Power management controller not found\n"); @@ -59,7 +59,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
tmp = inw(VX800_ACPI_IO_BASE + 0x04); result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - print_debug(" boot_mode="); + print_debug(" boot_mode="); print_debug_hex16(result); print_debug("\n"); return result; @@ -165,7 +165,7 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table };
-#define USE_VCP 1 //0 means use DVP +#define USE_VCP 1 //0 means use DVP #define USE_COM1 1 #define USE_COM2 0
@@ -297,31 +297,31 @@ void main(unsigned long bist) //enable_vx800_serial(); //uart_init();
-/* 1. D15F0 +/* 1. D15F0
-a) RxBAh = 71h +a) RxBAh = 71h
-b) RxBBh = 05h +b) RxBBh = 05h
-c) RxBEh = 71h +c) RxBEh = 71h
-d) RxBFh = 05h +d) RxBFh = 05h
2. D17F0
-a) RxA0h = 06h +a) RxA0h = 06h
-b) RxA1h = 11h +b) RxA1h = 11h
-c) RxA2h = 27h +c) RxA2h = 27h
-d) RxA3h = 32h +d) RxA3h = 32h
-e) Rx79h = 40h +e) Rx79h = 40h
-f) Rx72h = 27h +f) Rx72h = 27h
-g) Rx73h = 32h +g) Rx73h = 32h */
u8 Data8; @@ -445,7 +445,7 @@ g) Rx73h = 32h u32 memtop4 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; - /* __asm__ volatile ( + /* __asm__ volatile ( "movl $0x204, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl %0,%%eax\n\t" @@ -455,8 +455,8 @@ g) Rx73h = 32h "movl $0x205, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" + "decl %%eax\n\t" + "notl %%eax\n\t" "orl $(0 | 0x800), %%eax\n\t" "wrmsr\n\t" ::"g"(memtop2) @@ -471,8 +471,8 @@ g) Rx73h = 32h "movl $0x207, %%ecx\n\t" "xorl %%edx, %%edx\n\t" "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" + "decl %%eax\n\t" + "notl %%eax\n\t" "orl $(0 | 0x800), %%eax\n\t" "wrmsr\n\t" ::"g"(memtop1) @@ -487,8 +487,8 @@ g) Rx73h = 32h "movl $0x209, %ecx\n\t" "xorl %edx, %edx\n\t" "movl $0x100000,%eax\n\t" - "decl %eax\n\t" - "notl %eax\n\t" + "decl %eax\n\t" + "notl %eax\n\t" "orl $(0 | 0x800), %eax\n\t" "wrmsr\n\t" ); @@ -497,45 +497,45 @@ g) Rx73h = 32h // these two memcpy not not be enabled if set the MTRR around this two lines. /*__asm__ volatile ( "movl $0, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) + "movl %0, %%edi\n\t" + "movl $0xa0000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"g"(memtop3) ); __asm__ volatile ( "movl $0xe0000, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) + "movl %0, %%edi\n\t" + "movl $0x20000, %%ecx\n\t" + "shrl $2, %%ecx\n\t" + "rep movsd\n\t" + ::"g"(memtop4) );*/ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), - (unsigned char *) 0, 0xa0000); + (unsigned char *) 0, 0xa0000); memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000 + 0xe0000), - (unsigned char *) 0xe0000, 0x20000); + (unsigned char *) 0xe0000, 0x20000);
/* restore the MTRR previously modified. */ /* __asm__ volatile ( - "wbinvd\n\t" - "xorl %edx, %edx\n\t" - "xorl %eax, %eax\n\t" - "movl $0x204, %ecx\n\t" - "wrmsr\n\t" + "wbinvd\n\t" + "xorl %edx, %edx\n\t" + "xorl %eax, %eax\n\t" + "movl $0x204, %ecx\n\t" + "wrmsr\n\t" "movl $0x205, %ecx\n\t" - "wrmsr\n\t" + "wrmsr\n\t" "movl $0x206, %ecx\n\t" - "wrmsr\n\t" + "wrmsr\n\t" "movl $0x207, %ecx\n\t" - "wrmsr\n\t" + "wrmsr\n\t" "movl $0x208, %ecx\n\t" - "wrmsr\n\t" + "wrmsr\n\t" "movl $0x209, %ecx\n\t" - "wrmsr\n\t" + "wrmsr\n\t" );*/ } #endif diff --git a/src/northbridge/via/vx800/final_setting.c b/src/northbridge/via/vx800/final_setting.c index 7d39c68..eb7a57e 100644 --- a/src/northbridge/via/vx800/final_setting.c +++ b/src/northbridge/via/vx800/final_setting.c @@ -65,16 +65,16 @@ void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMRegFinalValue() Precondition : -Input : +Input : DramAttr: pointer point to DRAM_SYS_ATTR which consist the DDR and Dimm information - in MotherBoard -Output : Void -Purpose : Chipset Performance UP and other setting after DRAM Sizing - Turn on register directly to promote performance + in MotherBoard +Output : Void +Purpose : Chipset Performance UP and other setting after DRAM Sizing + Turn on register directly to promote performance ===================================================================*/
//-------------------------------------------------------------------------- -// register AND OR +// register AND OR //-------------------------------------------------------------------------- #define DRAM_table_item 9 static const u8 DRAM_table[DRAM_table_item][3] = { diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a..bb78a42 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -72,7 +72,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) //CPU Delay WaitMicroSec(20);
- // Manual reset and adjust DLL when DRAM change frequency + // Manual reset and adjust DLL when DRAM change frequency Data = pci_read_config8(MEMCTRL, 0x6B); Data = (u8) ((Data & 0x2f) | 0xC0); pci_write_config8(MEMCTRL, 0x6B, Data); @@ -134,7 +134,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (DramAttr->DimmInfo[SckId].bPresence) { /*all DIMM supported CL */ AllDimmSupportedCL &= (DramAttr-> - DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); + DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); } } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ @@ -164,7 +164,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (DramAttr->DimmInfo[SckId].bPresence) { Tmp = (DramAttr-> - DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); + DimmInfo[SckId].SPDDataBuf[SPD_SDRAM_CAS_LATENCY]); tmpMask = 0x40; for (TmpId = 7; TmpId > 0; TmpId--) { if ((Tmp & tmpMask) == tmpMask) @@ -173,19 +173,19 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } if (TmpId - BitId == 0) { /*get Cycle time for X, SPD BYTE9 */ TmpCycTime = - DramAttr-> - DimmInfo[SckId].SPDDataBuf - [SPD_SDRAM_TCLK_X]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X]; } else if (TmpId - BitId == 1) { /*get Cycle time for X-1, SPD BYTE23 */ TmpCycTime = - DramAttr-> - DimmInfo[SckId].SPDDataBuf - [SPD_SDRAM_TCLK_X_1]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X_1]; } else if (TmpId - BitId == 2) { /*get cycle time for X-2, SPD BYTE25 */ TmpCycTime = - DramAttr-> - DimmInfo[SckId].SPDDataBuf - [SPD_SDRAM_TCLK_X_2]; + DramAttr-> + DimmInfo[SckId].SPDDataBuf + [SPD_SDRAM_TCLK_X_2]; } else { //error!!! } diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 9e1fa57..3fbe000 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -94,7 +94,7 @@ static void pci_routing_fixup(struct device *dev)
/* Standard usb components */ printk(BIOS_INFO, "setting usb1-2\n"); -// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); +// pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
/* sound hardware */ printk(BIOS_INFO, "setting hdac audio\n"); @@ -116,7 +116,7 @@ static void setup_pm(device_t dev) pci_write_config8(dev, 0x82, 0x49);
/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ -// pci_write_config16(dev, 0x84, 0x30f2); +// pci_write_config16(dev, 0x84, 0x30f2); pci_write_config16(dev, 0x84, 0x609a); // 0x609a??
/* SMI output level to low, 7.5us throttle clock */ @@ -242,7 +242,7 @@ static void vx800_sb_init(struct device *dev) pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space -// pci_write_config8(dev, 0x41, 0x7f); +// pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI @@ -346,7 +346,7 @@ static void southbridge_init(struct device *dev) #2 ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. - 1 enable SLP# asserts in C3 state PMIORx26<1> =1 + 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 3 CLKRUN# is always asserted PMIORx26<3> =0 4 Disable PCISTP# When CLKRUN# is asserted diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index a87e65e..1923393 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -114,7 +114,7 @@ if register with invalid value we set frame buffer size to 32M for default, but else tomk = (((rambits << 6) - (4 << reg) - - VIACONFIG_TOP_SM_SIZE_MB) * 1024); + VIACONFIG_TOP_SM_SIZE_MB) * 1024);
printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk); /* Compute the Top Of Low Memory, in Kb */ diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h index 33eebc4..125cef3 100644 --- a/src/northbridge/via/vx800/pci_rawops.h +++ b/src/northbridge/via/vx800/pci_rawops.h @@ -44,7 +44,7 @@ static void pci_modify_config8(device_t dev, unsigned where, u8 orval, u8 mask) }
static void via_pci_inittable(u8 chipversion, - const struct VIA_PCI_REG_INIT_TABLE *initdata) + const struct VIA_PCI_REG_INIT_TABLE *initdata) { u8 i = 0; device_t devbxdxfx; @@ -61,11 +61,11 @@ static void via_pci_inittable(u8 chipversion, && (chipversion <= initdata[i].ChipRevisionEnd)) { devbxdxfx = PCI_DEV(initdata[i].Bus, initdata[i].Device, - initdata[i].Function); + initdata[i].Function); pci_modify_config8(devbxdxfx, - initdata[i].Register, - initdata[i].Value, - initdata[i].Mask); + initdata[i].Register, + initdata[i].Value, + initdata[i].Mask); } } } diff --git a/src/northbridge/via/vx800/rank_map.c b/src/northbridge/via/vx800/rank_map.c index e50372f..86cb9e9 100644 --- a/src/northbridge/via/vx800/rank_map.c +++ b/src/northbridge/via/vx800/rank_map.c @@ -33,11 +33,11 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr); /*=================================================================== Function : DRAMBankInterleave() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : STEP 13 Set Bank Interleave VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank 11:8 Bank - Scan all DIMMs on board to find out the lowest Bank Interleave among these DIMMs and set register. +Output : Void +Purpose : STEP 13 Set Bank Interleave VIANB3DRAMREG69[7:6] 00:No Interleave 01:2 Bank 10:4 Bank 11:8 Bank + Scan all DIMMs on board to find out the lowest Bank Interleave among these DIMMs and set register. ===================================================================*/ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) { @@ -86,16 +86,16 @@ void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingMATypeM() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void +Output : Void Purpose : STEP 14 1 DRAM Sizing 2 Fill MA type 3 Prank to vrankMapping ===================================================================*/ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) { DRAMClearEndingAddress(DramAttr); DRAMSizingEachRank(DramAttr); - //DRAMReInitDIMMBL (DramAttr); + //DRAMReInitDIMMBL (DramAttr); DRAMSetRankMAType(DramAttr); DRAMSetEndingAddress(DramAttr); DRAMPRToVRMapping(DramAttr); @@ -104,10 +104,10 @@ void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMClearEndingAddress() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : clear Ending and Start adress from 0x40-4f to zero +Output : Void +Purpose : clear Ending and Start adress from 0x40-4f to zero ===================================================================*/ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr) { @@ -121,10 +121,10 @@ void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSizingEachRank() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit +Output : Void +Purpose : Sizing each Rank invidually, by number of rows column banks pins, be care about 128bit ===================================================================*/ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) { @@ -190,10 +190,10 @@ void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetRankMAType() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit +Output : Void +Purpose : set the matype Reg by MAMapTypeTbl, which the rule can be found in memoryinit ===================================================================*/ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) { @@ -222,19 +222,19 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) if (DramAttr->DimmInfo[SlotNum].bPresence) { for (j = 0; MAMapTypeTbl[j] != 0; j += 3) { if ((1 << MAMapTypeTbl[j]) == - DramAttr-> - DimmInfo[SlotNum].SPDDataBuf - [SPD_SDRAM_NO_OF_BANKS] - && MAMapTypeTbl[j + 1] == - DramAttr-> - DimmInfo[SlotNum].SPDDataBuf - [SPD_SDRAM_COL_ADDR]) { + DramAttr-> + DimmInfo[SlotNum].SPDDataBuf + [SPD_SDRAM_NO_OF_BANKS] + && MAMapTypeTbl[j + 1] == + DramAttr-> + DimmInfo[SlotNum].SPDDataBuf + [SPD_SDRAM_COL_ADDR]) { break; } } if (0 == MAMapTypeTbl[j]) { PRINT_DEBUG_MEM - ("UNSUPPORTED Bank, Row and Column Addr Bits!\r"); + ("UNSUPPORTED Bank, Row and Column Addr Bits!\r"); return; } or = MAMapTypeTbl[j + 2] << ShiftBits[SlotNum]; @@ -259,10 +259,10 @@ void DRAMSetRankMAType(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMSetEndingAddress() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size +Output : Void +Purpose : realize the Vrank 40...Reg (Start and Ending Regs). Vrank have same order with phy Rank, Size is actual Size ===================================================================*/ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) { @@ -274,7 +274,7 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr)
End = End + Size; // calculate current ending address, add the current Size to ending Vrank = RankNO; // get virtual Rank - Data = End; // set begin/End address register to correspondig virtual Rank # + Data = End; // set begin/End address register to correspondig virtual Rank # pci_write_config8(MEMCTRL, 0x40 + Vrank, Data); Data = Start; pci_write_config8(MEMCTRL, 0x48 + Vrank, Data); @@ -312,10 +312,10 @@ void DRAMSetEndingAddress(DRAM_SYS_ATTR * DramAttr) /*=================================================================== Function : DRAMPRToVRMapping() Precondition : -Input : +Input : DramAttr: pointer point to DRAMSYSATTR which consist the DDR and Dimm information in MotherBoard -Output : Void -Purpose : set the Vrank-prank map with the same order +Output : Void +Purpose : set the Vrank-prank map with the same order ===================================================================*/ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr) { @@ -330,7 +330,7 @@ void DRAMPRToVRMapping(DRAM_SYS_ATTR * DramAttr) Shift = 1; for (PhyRankNO = 0; PhyRankNO < MAX_RANKS; PhyRankNO++) { if ((DramAttr->RankPresentMap & Shift) != 0) { - or = PhyRankNO; // get virtual Rank ,same with PhyRank + or = PhyRankNO; // get virtual Rank ,same with PhyRank or |= 0x08;
if ((PhyRankNO & 0x01) == 0x01) // get mask for register diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index df90304..ba03145 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -257,7 +257,7 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr) /*only DDR2 need to add byte 40 bit[7:4] */ Byte40 = (DramAttr-> - DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRFC2]); + DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRFC2]); /*if bit0 = 1, byte42(RFC)+256ns, SPD spec JEDEC standard No.21.c */ if (Byte40 & 0x01) Tmp += (256 * 100); diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index d404cde..26321c5 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -137,7 +137,7 @@ void SetUMARam(void) ByteVal = (ByteVal & 0x8f) | (SLD0F3Val << 4); pci_write_config8(MEMCTRL, 0xa1, ByteVal);
-// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0); +// vga_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VGA, 0);
//RxB2 may be for S.L. and RxB1 may be for L. L. // It is different from Spec. diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 7fe33f2..713dd4c 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -118,7 +118,7 @@ static int via_vx800_int15_handler(void) X86_EAX = 0x005f; res = 1; break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_EAX & 0xffff); X86_EAX = 0; @@ -135,13 +135,13 @@ static void write_protect_vgabios(void) printk(BIOS_INFO, "write_protect_vgabios\n"); /* there are two possible devices. Just do both. */ dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); + PCI_DEVICE_ID_VIA_VX855_MEMCTRL, 0); if (dev) pci_write_config8(dev, 0x80, 0xff); /*vx855 no th 0x61 reg */ /*dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855_VLINK, 0); //if(dev) - // pci_write_config8(dev, 0x61, 0xff); */ + // pci_write_config8(dev, 0x61, 0xff); */ } #endif
@@ -153,7 +153,7 @@ static void vga_enable_console(void) * it on is good. */
- /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ + /* int#, EAX, EBX, ECX, EDX, ESI, EDI */ realmode_interrupt(0x10, 0x4f14, 0x8003, 0x0001, 0x0000, 0x0000, 0x0000); #endif } diff --git a/src/northbridge/via/vx800/vx800.h b/src/northbridge/via/vx800/vx800.h index ce1f0a1..8fa63af 100644 --- a/src/northbridge/via/vx800/vx800.h +++ b/src/northbridge/via/vx800/vx800.h @@ -120,7 +120,7 @@ void enable_vx800_serial(void); #define SB_EHCI_REG 0,0x10, 4,
#define VX800SB_APIC_ID 0x4 -#define VX800SB_APIC_DATA_OFFSET 0x10 +#define VX800SB_APIC_DATA_OFFSET 0x10 #define VX800SB_APIC_ENTRY_NUMBER 0x40
#define VX800_D0F5_MMCONFIG_MBAR 0x61 diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 55e2a96..d07b7b1 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -27,7 +27,7 @@
#include "vx900.h"
-#define CHROME_9_HD_MIN_FB_SIZE 8 +#define CHROME_9_HD_MIN_FB_SIZE 8 #define CHROME_9_HD_MAX_FB_SIZE 512
/** @@ -83,8 +83,8 @@ u32 chrome9hd_fb_size(void) size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);
const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, - 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, + 0); /* * We have two limitations on the maximum framebuffer size: * 1) (Sanity) No more that 1/4 of system RAM @@ -94,8 +94,8 @@ u32 chrome9hd_fb_size(void) max_size_mb = tom_mb >> 2; if (size_mb > max_size_mb) { printk(BIOS_ALERT, "The framebuffer size of of %dMB is larger" - " than 1/4 of available memory.\n" - " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); + " than 1/4 of available memory.\n" + " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); size_mb = max_size_mb; }
@@ -119,8 +119,8 @@ u32 chrome9hd_fb_size(void) }; if (size_mb > max_size_mb) { printk(BIOS_ALERT, "The framebuffer size of %dMB is larger" - " than size of the last DRAM rank.\n" - " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); + " than size of the last DRAM rank.\n" + " Limiting framebuffer to %dMB\n", size_mb, max_size_mb); size_mb = max_size_mb; }
@@ -223,9 +223,9 @@ static void chrome9hd_handle_uma(device_t dev) //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10);
printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); + uma_memory_base >> 20); printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, - uma_memory_size >> 20); + uma_memory_size >> 20); u8 fb_pow = 0; while (fb_size >> fb_pow) fb_pow++; @@ -233,7 +233,7 @@ static void chrome9hd_handle_uma(device_t dev)
/* Step 6 - Let MCU know the framebuffer size */ device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); pci_mod_config8(mcu, 0xa1, 7 << 4, (fb_pow - 2) << 4);
/* Step 7 - Let GFX know the framebuffer size (through PCI and IOCTL) @@ -260,7 +260,7 @@ static void chrome9hd_handle_uma(device_t dev) static void chrome9hd_biosguide_init_seq(device_t dev) { device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); device_t host = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
@@ -290,7 +290,7 @@ static void chrome9hd_biosguide_init_seq(device_t dev) if (uma_memory_base == 0) die("uma_memory_base not set. Abandon ship!\n"); printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); + uma_memory_base >> 20); vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ vga_sr_write(0x6f, 0x00); /* base 43:37 */ @@ -325,7 +325,7 @@ static void chrome9hd_init(device_t dev) }
printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", - 256, fb_address); + 256, fb_address);
printk(BIOS_DEBUG, "Initializing VGA...\n");
@@ -339,7 +339,7 @@ static void chrome9hd_init(device_t dev) static void chrome9hd_enable(device_t dev) { device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); /* FIXME: here? -=- ACLK 250Mhz */ pci_mod_config8(mcu, 0xbb, 0, 0x01); } @@ -347,7 +347,7 @@ static void chrome9hd_enable(device_t dev) static void chrome9hd_disable(device_t dev) { device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); /* Disable GFX - This step effectively renders the GFX inert * It won't even show up as a PCI device during enumeration */ pci_mod_config8(mcu, 0xa1, 1 << 7, 0); diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c index f006ce4..5d5e01a 100644 --- a/src/northbridge/via/vx900/early_smbus.c +++ b/src/northbridge/via/vx900/early_smbus.c @@ -84,7 +84,7 @@ void enable_smbus(void)
/* Locate the Power Management control */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_LPC), 0); + PCI_DEVICE_ID_VIA_VX900_LPC), 0);
if (dev == PCI_DEV_INVALID) { die("Power Management Controller not found\n"); @@ -182,7 +182,7 @@ void dump_spd_data(spd_raw_data spd) * I originally saw this way to present SPD data in code from VIA. I * really liked the idea, so here it goes. */ - print_debug(" 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n"); + print_debug(" 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n"); print_debug("---+------------------------------------------------"); for (i = 0; i < len; i++) { reg = spd[i]; diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index 2896680..3c0ee6b 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -71,15 +71,15 @@ void vx900_print_strapping_info(void)
print_debug("VX900 strapping pins indicate that:\n"); printk(BIOS_DEBUG, " ROM is on %s bus\n", - (strap & (1 << 0)) ? "SPI" : "LPC"); + (strap & (1 << 0)) ? "SPI" : "LPC"); printk(BIOS_DEBUG, " Auto reset is %s\n", - (strap & (1 << 1)) ? "disabled" : "enabled"); + (strap & (1 << 1)) ? "disabled" : "enabled"); printk(BIOS_DEBUG, " LPC FWH command is %s\n", - (strap & (1 << 2)) ? "enabled" : "disabled"); + (strap & (1 << 2)) ? "enabled" : "disabled"); printk(BIOS_DEBUG, " Debug link is is %s\n", - (strap & (1 << 4)) ? "enabled" : "disabled"); + (strap & (1 << 4)) ? "enabled" : "disabled"); printk(BIOS_DEBUG, " PCI master mode is %s\n", - (strap & (1 << 5)) ? "enabled" : "disabled"); + (strap & (1 << 5)) ? "enabled" : "disabled"); }
/** diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index 46e3023..938873f 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -32,30 +32,30 @@ #define HOST_CTR PCI_DEV(0, 0, 0) #define ERR_REP PCI_DEV(0, 0, 1) #define HOST_BUS PCI_DEV(0, 0, 2) -#define MCU PCI_DEV(0, 0, 3) +#define MCU PCI_DEV(0, 0, 3) #define POWERMAN PCI_DEV(0, 0, 4) #define TRAF_CTR PCI_DEV(0, 0, 5) -#define NSBIC PCI_DEV(0, 0, 7) +#define NSBIC PCI_DEV(0, 0, 7)
-#define GFX PCI_DEV(0, 1, 0) -#define HDMI PCI_DEV(0, 1, 0) +#define GFX PCI_DEV(0, 1, 0) +#define HDMI PCI_DEV(0, 1, 0)
-#define PEXx PCI_DEV(0, 3, x) +#define PEXx PCI_DEV(0, 3, x) #define PEX_CTR PCI_DEV(0, 3, 4)
/* South Module devices */ -#define UARTx PCI_DEV(0, 0x0a, x) +#define UARTx PCI_DEV(0, 0x0a, x) #define USB_MASS PCI_DEV(0, 0x0b, 0) -#define SDIO PCI_DEV(0, 0x0c, 0) +#define SDIO PCI_DEV(0, 0x0c, 0) #define CARD_RD PCI_DEV(0, 0x0d, 0) -#define SATA PCI_DEV(0, 0x0d, 0) -#define USBx PCI_DEV(0, 0x10, x) +#define SATA PCI_DEV(0, 0x0d, 0) +#define USBx PCI_DEV(0, 0x10, x) #define USB_EHCI PCI_DEV(0, 0x10, 4) -#define LPC PCI_DEV(0, 0x11, 0) -#define PMU LPC -#define SNMIC PCI_DEV(0, 0x11, 7) -#define P2P PCI_DEV(0, 0x13, 0) -#define HDAC PCI_DEV(0, 0x14, 0) +#define LPC PCI_DEV(0, 0x11, 0) +#define PMU LPC +#define SNMIC PCI_DEV(0, 0x11, 7) +#define P2P PCI_DEV(0, 0x13, 0) +#define HDAC PCI_DEV(0, 0x14, 0)
/* These control the behavior of raminit */ #define RAMINIT_USE_HW_RXCR_CALIB 0 diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index ac5e4c8..5d3cabc 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -63,10 +63,10 @@ static void vx900_lpc_misc_stuff(device_t dev) extint = nb->ext_int_route_to_pirq; if (extint < 'A' || extint > 'H') { printk(BIOS_WARNING, "Invalid PIRQ%c for external interrupt\n", - extint); + extint); } else { printk(BIOS_INFO, "Routing external interrupt to PIRQ%c\n", - extint); + extint); val = extint - 'A'; val |= (1 << 3); /* bit3 enables the external int */ pci_mod_config8(dev, 0x55, 0xf, val); @@ -122,7 +122,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) if (ioapic == 0) { /* We don't have enough info to set up the IOAPIC */ printk(BIOS_ERR, "ERROR: South module IOAPIC not found. " - "Check your devicetree.cb\n"); + "Check your devicetree.cb\n"); return; }
@@ -131,7 +131,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) if (!config->have_isa_interrupts) { /* Umh, is this the right IOAPIC ? */ printk(BIOS_ERR, "ERROR: South module IOAPIC not carrying ISA " - "interrupts. Check your devicetree.cb\n"); + "interrupts. Check your devicetree.cb\n"); printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); return; } @@ -142,7 +142,7 @@ static void vx900_lpc_ioapic_setup(device_t dev) const u32 base = config->base; if (base != 0xfec00000) { printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at " - "0xfec00000\n but we found it at 0x%.8x\n", base); + "0xfec00000\n but we found it at 0x%.8x\n", base); return; }
@@ -207,7 +207,7 @@ void pirq_assign_irqs(const u8 * pirq) device_t lpc;
lpc = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_LPC, 0); + PCI_DEVICE_ID_VIA_VX900_LPC, 0);
/* Take care of INTA -> INTD */ pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4); diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 25e6045..2379041 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -74,7 +74,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) remapstart <<= 26; remapend <<= 26; printk(BIOS_DEBUG, "Remapstart %lld(MB) \n", remapstart >> 20); - printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20); + printk(BIOS_DEBUG, "Remapend %lld(MB) \n", remapend >> 20); }
/** @@ -97,14 +97,14 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) * The remapping mechanism works like this: * * - Choose the top of low memory. - * This becomes the "remap from" + * This becomes the "remap from" * - Choose a chunk above 4G where to remap. - * This becomes "remap to" + * This becomes "remap to" * - Choose a chunk above 4G where to end the remapping. - * This becomes "remap until" + * This becomes "remap until" * * This remaps a "chunk" of memory where we want to. - * sizeof(chunk) = until - to; + * sizeof(chunk) = until - to; * * Therefore the memory region from "from" to " from + sizeof(chunk)" * becomes accessible at "to" to "until" @@ -159,16 +159,16 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
if (end < (tolm >> 26)) { printk(BIOS_DEBUG, "Huh? rank %ld don't need remap?\n", - i); + i); continue; }
printk(BIOS_DEBUG, "Physical rank %u is mapped to\n" - " Start address: 0x%.10llx (%dMB)\n" - " End address: 0x%.10llx (%dMB)\n", - (int)i, - ((u64) start << 26), (start << (26 - 20)), - ((u64) end << 26), (end << (26 - 20))); + " Start address: 0x%.10llx (%dMB)\n" + " End address: 0x%.10llx (%dMB)\n", + (int)i, + ((u64) start << 26), (start << (26 - 20)), + ((u64) end << 26), (end << (26 - 20)));
if (end < (RAM_4GB >> 26)) end = (RAM_4GB >> 26); @@ -183,11 +183,11 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) pci_write_config8(mcu, 0x40 + i, end);
printk(BIOS_DEBUG, "ReMapped Physical rank %u, to\n" - " Start address: 0x%.10llx (%dMB)\n" - " End address: 0x%.10llx (%dMB)\n", - (int)i, - ((u64) start << 26), (start << (26 - 20)), - ((u64) end << 26), (end << (26 - 20))); + " Start address: 0x%.10llx (%dMB)\n" + " End address: 0x%.10llx (%dMB)\n", + (int)i, + ((u64) start << 26), (start << (26 - 20)), + ((u64) end << 26), (end << (26 - 20))); }
/* The "remap to where?" register */ @@ -217,8 +217,8 @@ static void vx900_set_resources(device_t dev)
int idx = 10; const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL, - 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL, + 0); if (!mcu) { die("Something is terribly wrong.\n" " We tried locating the MCU on the PCI bus, " @@ -227,12 +227,12 @@ static void vx900_set_resources(device_t dev)
/* How much low adrress space do we have? */ pci_tolm = find_pci_tolm(dev->link_list); - printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm); - printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20); + printk(BIOS_SPEW, "Found PCI tolm at %.8x\n", pci_tolm); + printk(BIOS_SPEW, "Found PCI tolm at %dMB\n", pci_tolm >> 20);
/* Figure out the total amount of RAM */ tomk = vx900_get_top_of_ram(mcu) >> 10; - printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10); + printk(BIOS_SPEW, "Found top of memory at %dMB\n", tomk >> 10);
/* Do the same for top of low RAM */ vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4; @@ -240,7 +240,7 @@ static void vx900_set_resources(device_t dev) /* Remap above 4G if needed */ full_tolmk = MIN(full_tolmk, pci_tolm >> 10); printk(BIOS_SPEW, "Found top of low memory at %dMB\n", - full_tolmk >> 10); + full_tolmk >> 10);
/* What about the framebuffer for the integrated GPU? */ fbufk = chrome9hd_fb_size() >> 10; @@ -250,7 +250,7 @@ static void vx900_set_resources(device_t dev) tolmk = MIN(full_tolmk, tomk); tolmk -= fbufk; ram_resource(dev, idx++, 0, 640); - printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10); + printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10); /* FIXME: how can we avoid leaving this hole? * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem @@ -261,7 +261,7 @@ static void vx900_set_resources(device_t dev) uma_memory_base = tolmk << 10;
printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20, - uma_memory_size >> 20); + uma_memory_size >> 20); /* FIXME: How do we handle remapping above 4G? */ u64 tor = vx900_remap_above_4g(mcu, pci_tolm); ram_resource(dev, idx++, RAM_4GB >> 10, (tor - RAM_4GB) >> 10); diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 18d4c11..52565d3 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -48,7 +48,7 @@ void pci_mod_config8(device_t dev, unsigned int where, }
void pci_mod_config16(device_t dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask) + uint16_t clr_mask, uint16_t set_mask) { uint16_t reg16 = pci_read_config16(dev, where); reg16 &= ~clr_mask; @@ -57,7 +57,7 @@ void pci_mod_config16(device_t dev, unsigned int where, }
void pci_mod_config32(device_t dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask) + uint32_t clr_mask, uint32_t set_mask) { uint32_t reg32 = pci_read_config32(dev, where); reg32 &= ~clr_mask; diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0..eaa8aed 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -127,7 +127,7 @@ static void dump_delay_range(const delay_range d_range) { printram("Lower limit: "); dump_delay(d_range.low); - printram("Average: "); + printram("Average: "); dump_delay(d_range.avg); printram("Upper limit: "); dump_delay(d_range.high); @@ -354,7 +354,7 @@ static void dram_find_spds_ddr3(const dimm_layout * addr, dimm_info * dimm) }
static void dram_find_common_params(const dimm_info * dimms, - ramctr_timing * ctrl) + ramctr_timing * ctrl) { size_t i, valid_dimms; memset(ctrl, 0, sizeof(ramctr_timing)); @@ -402,7 +402,7 @@ static void dram_find_common_params(const dimm_info * dimms, }
static void vx900_dram_phys_bank_range(const dimm_info * dimms, - rank_layout * ranks) + rank_layout * ranks) { size_t i; for (i = 0; i < VX900_MAX_DIMM_SLOTS; i++) { @@ -443,7 +443,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, * not suitable for the way we map ranks later on. */ static const u8 odt_lookup_table[][2] = { - /* RankMAP Rank 3 Rank 2 Rank 1 Rank 0 */ + /* RankMAP Rank 3 Rank 2 Rank 1 Rank 0 */ {0x01, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, {0x03, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R0 << 2) | (ODT_R1 << 0)}, {0x04, (ODT_R3 << 6) | (ODT_R2 << 4) | (ODT_R1 << 2) | (ODT_R0 << 0)}, @@ -538,7 +538,7 @@ static void vx900_map_pr_vr(u8 pr, u8 vr) static u8 vx900_get_CWL(u8 CAS) { /* Get CWL based on CAS using the following rule: - * _________________________________________ + * _________________________________________ * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T | * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T | */ @@ -576,49 +576,49 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
/* Find CAS and CWL latencies */ val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; - printram("Minimum CAS latency : %uT\n", val); + printram("Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - 4)) & 1) - && (ctrl->cas_supported >> (val - 4))) { + && (ctrl->cas_supported >> (val - 4))) { val++; } /* Is CAS supported */ if (!(ctrl->cas_supported & (1 << (val - 4)))) printram("CAS not supported\n"); - printram("Selected CAS latency : %uT\n", val); + printram("Selected CAS latency : %uT\n", val); ctrl->CAS = val; ctrl->CWL = vx900_get_CWL(ctrl->CAS); - printram("Selected CWL latency : %uT\n", ctrl->CWL); + printram("Selected CWL latency : %uT\n", ctrl->CWL); /* Write CAS and CWL */ reg8 = (((ctrl->CWL - 4) & 0x07) << 4) | ((ctrl->CAS - 4) & 0x07); pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */ val = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tRCD : %uT\n", val); + printram("Selected tRCD : %uT\n", val); reg8 = ((val - 4) & 0x7) << 4; /* Find tRP */ val = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tRP : %uT\n", val); + printram("Selected tRP : %uT\n", val); reg8 |= ((val - 4) & 0x7); pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */ val = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tRAS : %uT\n", val); + printram("Selected tRAS : %uT\n", val); reg8 = ((val - 15) & 0x7) << 4; /* Find tWR */ ctrl->WR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tWR : %uT\n", ctrl->WR); + printram("Selected tWR : %uT\n", ctrl->WR); reg8 |= ((ctrl->WR - 4) & 0x7); pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */ tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tFAW : %uT\n", tFAW); + printram("Selected tFAW : %uT\n", tFAW); /* Find tRRD */ tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tRRD : %uT\n", tRRD); + printram("Selected tRRD : %uT\n", tRRD); val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ reg8 = ((val - 0) & 0x7) << 4; reg8 |= ((tRRD - 2) & 0x7); @@ -626,37 +626,37 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
/* Find tRTP */ val = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tRTP : %uT\n", val); + printram("Selected tRTP : %uT\n", val); reg8 = ((val & 0x3) << 4); /* Find tWTR */ val = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; - printram("Selected tWTR : %uT\n", val); + printram("Selected tWTR : %uT\n", val); reg8 |= ((val - 2) & 0x7); pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
/* DRAM Timing for All Ranks - VI * [7:6] CKE Assertion Minimum Pulse Width - * We probably don't want to mess with this just yet. + * We probably don't want to mess with this just yet. * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC) - * tRFC = (30 + 2 * [5:0])T - * Since we previously set RxC4[7] + * tRFC = (30 + 2 * [5:0])T + * Since we previously set RxC4[7] */ reg8 = pci_read_config8(MCU, 0xc5); val = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; - printram("Minimum tRFC : %uT\n", val); + printram("Minimum tRFC : %uT\n", val); if (val < 30) { val = 0; } else { val = (val - 30 + 1) / 2; } ; - printram("Selected tRFC : %uT\n", 30 + 2 * val); + printram("Selected tRFC : %uT\n", 30 + 2 * val); reg8 |= (val & 0x3f); pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */ val = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK; - printram("Required tRC : %uT\n", val); + printram("Required tRC : %uT\n", val); }
/* Program the DRAM frequency */ @@ -718,7 +718,7 @@ static void vx900_dram_freq(ramctr_timing * ctrl) * registers we have programmed earlier. */ static void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom, - u8 ods, u8 rtt_wr, u8 srt, u8 asr) + u8 ods, u8 rtt_wr, u8 srt, u8 asr) { u16 reg16 = 0;
@@ -782,10 +782,10 @@ static u32 vx900_get_mrs_addr(mrs_cmd_t cmd) * earlier. */ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, - enum ddr3_mr1_ods ods, - enum ddr3_mr2_rttwr rtt_wr, - enum ddr3_mr2_srt_range srt, - enum ddr3_mr2_asr asr) + enum ddr3_mr1_ods ods, + enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range srt, + enum ddr3_mr2_asr asr) { mrs_cmd_t mrs; u8 reg8, cas, cwl, twr; @@ -867,7 +867,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom, * individual physical rank. */ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl, - const rank_layout * ranks) + const rank_layout * ranks) { size_t i; u8 rtt_nom, rtt_wr, ods, pinswap; @@ -1009,10 +1009,10 @@ static void vx900_dram_exit_read_leveling(u8 pinswap) * calibration will not work. */ #define DQSI_THRESHOLD 0x10 -#define DQO_THRESHOLD 0x09 +#define DQO_THRESHOLD 0x09 #define DQSO_THRESHOLD 0x12 #define DELAY_RANGE_GOOD 0 -#define DELAY_RANGE_BAD -1 +#define DELAY_RANGE_BAD -1 static u8 vx900_dram_check_calib_range(const delay_range * dly, u8 window) { size_t i; @@ -1365,7 +1365,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
/**** Read delay control ****/ /* MD Input Data Push Timing Control; - * use values recommended in datasheet + * use values recommended in datasheet * Setting this too low causes the Rx window to move below the range we * need it so we can capture it with Rx_78_7f * This causes Rx calibrations to be too close to 0, and Tx @@ -1421,7 +1421,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, break; } vx900_dram_calibrate_recieve_delays(&delay_cal, - ranks->flags[i].pins_mirrored); + ranks->flags[i].pins_mirrored); printram("RX DQS calibration results\n"); dump_delay_range(delay_cal.rx_dqs);
@@ -1444,7 +1444,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, /* Map the first rank of the DIMM to VR0 */ vx900_map_pr_vr(2 * i, 0); vx900_dram_calibrate_transmit_delays(&(delay_cal.tx_dq[dimm]), - &(delay_cal.tx_dqs[dimm])); + &(delay_cal.tx_dqs[dimm])); /* We run this more than once, so dump delays for each DIMM */ printram("Tx DQS calibration results\n"); dump_delay_range(delay_cal.tx_dqs[dimm]); @@ -1462,9 +1462,9 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, if (dimm > 1) { vx900_dram_find_avg_delays(&delay_cal); printram("Final delay values\n"); - printram("Tx DQS: "); + printram("Tx DQS: "); dump_delay(delay_cal.tx_dqs[0].avg); - printram("Tx DQ: "); + printram("Tx DQ: "); dump_delay(delay_cal.tx_dq[0].avg); } /* Write manual settings */ @@ -1528,8 +1528,8 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks) vx900_map_pr_vr(i, vrank);
printram("Mapped Physical rank %u, to virtual rank %u\n" - " Start address: 0x%.10llx\n" - " End address: 0x%.10llx\n", + " Start address: 0x%.10llx\n" + " End address: 0x%.10llx\n", (int)i, (int)vrank, (u64) ranks->virt[vrank].start_addr << 20, (u64) ranks->virt[vrank].end_addr << 20); @@ -1644,7 +1644,7 @@ void vx900_init_dram_ddr3(const dimm_layout * dimm_addr) } /* Locate the Memory controller */ mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0); + PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0);
if (mcu == PCI_DEV_INVALID) { die("Memory Controller not found\n"); diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..62183a8 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -35,13 +35,13 @@ static void vx900_print_sata_errors(u32 flags) { /* Status flags */ printk(BIOS_DEBUG, "\tPhyRdy %s\n", - (flags & (1 << 16)) ? "changed" : "not changed"); + (flags & (1 << 16)) ? "changed" : "not changed"); printk(BIOS_DEBUG, "\tCOMWAKE %s\n", - (flags & (1 << 16)) ? "detected" : "not detected"); + (flags & (1 << 16)) ? "detected" : "not detected"); printk(BIOS_DEBUG, "\tExchange as determined by COMINIT %s\n", - (flags & (1 << 26)) ? "occured" : "not occured"); + (flags & (1 << 26)) ? "occured" : "not occured"); printk(BIOS_DEBUG, "\tPort selector presence %s\n", - (flags & (1 << 27)) ? "detected" : "not detected"); + (flags & (1 << 27)) ? "detected" : "not detected"); /* Errors */ if (flags & (1 << 0)) print_debug("\tRecovered data integrity ERROR\n"); diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 2e73ea4..cc37cd2 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -64,7 +64,7 @@ static void vx900_north_ioapic_setup(device_t dev) if (ioapic == 0) { /* We don't have enough info to set up the IOAPIC */ printk(BIOS_ERR, "ERROR: North module IOAPIC not found. " - "Check your devicetree.cb\n"); + "Check your devicetree.cb\n"); return; } /* Found our IOAPIC, and it should not carry ISA interrupts */ @@ -72,25 +72,25 @@ static void vx900_north_ioapic_setup(device_t dev) if (config->have_isa_interrupts) { /* Umh, is this the right IOAPIC ? */ printk(BIOS_ERR, "ERROR: North module IOAPIC should not carry " - "ISA interrupts.\n" "Check your devicetree.cb\n"); + "ISA interrupts.\n" "Check your devicetree.cb\n"); printk(BIOS_ERR, "Will not initialize this IOAPIC.\n"); return; } /* The base address of this IOAPIC _must_ - * be between 0xfec00000 and 0xfecfff00 - * be 256-byte aligned + * be between 0xfec00000 and 0xfecfff00 + * be 256-byte aligned */ if ((config->base < 0xfec0000 || config->base > 0xfecfff00) || ((config->base & 0xff) != 0)) { printk(BIOS_ERR, "ERROR: North module IOAPIC base should be " - "between 0xfec00000 and 0xfecfff00\n" - "and must be aligned to a 256-byte boundary, " - "but we found it at 0x%.8x\n", config->base); + "between 0xfec00000 and 0xfecfff00\n" + "and must be aligned to a 256-byte boundary, " + "but we found it at 0x%.8x\n", config->base); return; }
printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC " - "at 0%.8x\n", config->base); + "at 0%.8x\n", config->base);
/* First register of the IOAPIC base */ base_val = (config->base >> 8) & 0xff; diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 8c0157a..ecac41b 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -47,8 +47,8 @@ void dump_pci_device(device_t dev); void pci_mod_config8(device_t dev, unsigned int where, uint8_t clr_mask, uint8_t set_mask); void pci_mod_config16(device_t dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask); + uint16_t clr_mask, uint16_t set_mask); void pci_mod_config32(device_t dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask); + uint32_t clr_mask, uint32_t set_mask);
#endif /* __VX900_H */ diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 9ec0171..e7efc24 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -21,7 +21,7 @@ ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) ifeq ($(CONFIG_CPU_AMD_AGESA), y)
$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" + echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp mv $@.tmp $@ diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 7e7399c..6e44b63 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -66,32 +66,32 @@ config HUDSON_XHCI_FWM config HUDSON_IMC_FWM bool "Add imc firmware" default y - help + help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
config HUDSON_GEC_FWM bool default n - help + help Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
config HUDSON_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "XHCI firmware path and filename" + default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE - string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "IMC firmware path and filename" + default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "GEC firmware path and filename" + default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM
config HUDSON_FWM @@ -102,12 +102,12 @@ config HUDSON_FWM if HUDSON_FWM
config HUDSON_FWM_POSITION - hex "Hudson Firmware rom Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 + hex "Hudson Firmware rom Position" + default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 + default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 + default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 + default 0xFF820000 if BOARD_ROMSIZE_KB_8192 + default 0xFF020000 if BOARD_ROMSIZE_KB_16384 help Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise @@ -167,7 +167,7 @@ config HUDSON_SATA_IDE2AHCI7804 endchoice
config HUDSON_SATA_MODE - hex + hex depends on (HUDSON_SATA_IDE || HUDSON_SATA_RAID || HUDSON_SATA_AHCI) default "0x0" if HUDSON_SATA_IDE default "0x1" if HUDSON_SATA_RAID @@ -196,8 +196,8 @@ if HUDSON_SATA_RAID config RAID_ROM_ID string "RAID device PCI IDs" default "1022,7802" - help - 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode + help + 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
config RAID_ROM_FILE string "RAID ROM path and filename" @@ -205,8 +205,8 @@ config RAID_ROM_FILE default "src/southbridge/amd/agesa/hudson/raid.bin"
config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "src/southbridge/amd/agesa/hudson/misc.bin" + string "RAID Misc ROM path and filename" + default "src/southbridge/amd/agesa/hudson/misc.bin" depends on HUDSON_SATA_RAID
config RAID_MISC_ROM_POSITION diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 6a097fc..6fe550c 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -61,7 +61,7 @@ $(obj)/coreboot_hudson_romsig.bin: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ $(obj)/config.h - echo " Hudson FW $@" + echo " Hudson FW $@" for fwm in 1437226410 \ $(HUDSON_IMC_POSITION) \ $(HUDSON_GEC_POSITION) \ diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 06b4fe7..29e14d2 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -161,7 +161,7 @@ Method(_CRS, 0) {
/* * - * FIRST METHOD CALLED UPON BOOT + * FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl index 3383ac8..ee2c231 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl @@ -53,7 +53,7 @@ Device(LIBR) {
/* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index 384ed61..44db463 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -470,4 +470,4 @@ } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl index f130fb4..32cfc75 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl @@ -71,7 +71,7 @@ /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 4c26a0b..e4ce07a 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -183,7 +183,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
/* * Note: Under this current AMD C state implementation, this is no longer - * used and should not be reported to OS. + * used and should not be reported to OS. */ fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm2_cnt_blk.bit_width = 0; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index e8f80aa..424adcb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -49,13 +49,13 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define REV_HUDSON_A11 0x11 #define REV_HUDSON_A12 0x12
-#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; -#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; -#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; -#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; -#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#ifdef __PRE_RAM__ void hudson_lpc_port80(void); diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 0d40d6c..7b65c9c 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -39,24 +39,24 @@ void s3_resume_init_data(void *data) *FchParams = InitEnvCfgDefault; FchParams->StdHeader = StdHeader;
- FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; - FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; - FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed; - FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed; - FchParams->Spi.SpiMode = InitResetCfgDefault.Mode; - FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode; - FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite; - FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap; - FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll; + FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; + FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; + FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed; + FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed; + FchParams->Spi.SpiMode = InitResetCfgDefault.Mode; + FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode; + FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite; + FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap; + FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll; FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2; - FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode; - FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg; - FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread; - FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed; - FchParams->Gpp = InitResetCfgDefault.Gpp; - FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable; + FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode; + FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg; + FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread; + FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed; + FchParams->Gpp = InitResetCfgDefault.Gpp; + FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable;
- FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; + FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; @@ -66,50 +66,50 @@ void s3_resume_init_data(void *data) FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
- FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; + FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; + FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; + FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; + FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; + FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; + FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; + FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; + FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; + FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; + FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; + FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; + FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; + FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; + FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; + FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; + FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; + FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; + FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; + FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; + FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; + FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; + FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; + FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; + FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; + FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; + FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; + FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
- FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig; - FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController; - FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig; - FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2; - FchParams->Sata.SataClass = FchInterfaceDefault.SataClass; - FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable; - FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable; - FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode; - FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable; - FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable; - FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable; - FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable; - FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable; - FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; - FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; - FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; + FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig; + FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController; + FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig; + FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2; + FchParams->Sata.SataClass = FchInterfaceDefault.SataClass; + FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable; + FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable; + FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode; + FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable; + FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable; + FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable; + FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable; + FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable; + FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; + FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; + FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail;
#if !CONFIG_HUDSON_XHCI_ENABLE FchParams->Usb.Xhci0Enable = FALSE; diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index e428d43..2b782c2 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -120,7 +120,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) }
int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) + u32 address) { u8 byte;
@@ -151,7 +151,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, }
int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) + u32 address, u8 val) { u8 byte;
diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 53cc0e6..331645b 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -38,13 +38,13 @@
#define AX_INDXC 0 #define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 +#define AXCFG 4 +#define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c index f49c9bf..ca78d29 100644 --- a/src/southbridge/amd/amd8111/ac97.c +++ b/src/southbridge/amd/amd8111/ac97.c @@ -20,16 +20,16 @@ static struct pci_operations lops_pci = {
static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, + .ops = &ac97audio_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x746D, }; @@ -37,16 +37,16 @@ static const struct pci_driver ac97audio_driver __pci_driver = {
static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = amd8111_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .enable = amd8111_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, + .ops = &ac97modem_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x746E, }; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index b734846..1440ba4 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -224,21 +224,21 @@ static struct pci_operations lops_pci = {
static struct device_operations acpi_ops = { .read_resources = acpi_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = acpi_enable_resources, - .init = acpi_init, - .scan_bus = scan_static_bus, + .init = acpi_init, + .scan_bus = scan_static_bus, /* We don't need amd8111_enable, chip ops takes care of it. * It could be useful if these devices were not * enabled by default. */ -// .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, +// .enable = amd8111_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver acpi_driver __pci_driver = { - .ops = &acpi_ops, + .ops = &acpi_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_ACPI, }; diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index 6661e02..9f8d9ff 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -1,7 +1,7 @@ #include <device/smbus_def.h>
#define SMBGSTATUS 0xe0 -#define SMBGCTL 0xe2 +#define SMBGCTL 0xe2 #define SMBHSTADDR 0xe4 #define SMBHSTDAT 0xe6 #define SMBHSTCMD 0xe8 diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index ece99ed..d84ef18 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,16 +4,16 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev;
- /* Find the device. - * There can only be one 8111 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), - bus); + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI), + bus);
- return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f;
}
@@ -40,34 +40,34 @@ static void enable_cf9(void)
void hard_reset(void) { - set_bios_reset(); - /* reset */ - enable_cf9(); - outb(0x0e, 0x0cf9); // make sure cf9 is enabled + set_bios_reset(); + /* reset */ + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled }
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
- pci_write_config8(dev, 0x74, 4); + pci_write_config8(dev, 0x74, 4);
- /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ - pci_write_config32(dev, 0x70, 2<<12); + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + pci_write_config32(dev, 0x70, 2<<12);
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
- /* Reset */ - set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1);
}
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index 3299875..7a5b0b2 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -33,8 +33,8 @@ static void ide_init(struct device *dev) pci_write_config16(dev, 0x40, word);
- byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte);
word = 0x0f; pci_write_config16(dev, 0x42, word); @@ -50,16 +50,16 @@ static struct pci_operations lops_pci = { }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = amd8111_enable, - .ops_pci = &lops_pci + .init = ide_init, + .scan_bus = 0, + .enable = amd8111_enable, + .ops_pci = &lops_pci };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_IDE, }; diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index e9bd5fc..39c8898 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -118,16 +118,16 @@ static struct pci_operations lops_pci = {
static struct device_operations lpc_ops = { .read_resources = amd8111_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = amd8111_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_ISA, }; diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c index 5352705..f62a40d 100644 --- a/src/southbridge/amd/amd8111/nic.c +++ b/src/southbridge/amd/amd8111/nic.c @@ -75,16 +75,16 @@ static struct pci_operations lops_pci = {
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nic_init, - .scan_bus = 0, + .scan_bus = 0, .enable = amd8111_enable, .ops_pci = &lops_pci, };
static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_NIC, }; diff --git a/src/southbridge/amd/amd8111/pci.c b/src/southbridge/amd/amd8111/pci.c index 9e77249..bf29569 100644 --- a/src/southbridge/amd/amd8111/pci.c +++ b/src/southbridge/amd/amd8111/pci.c @@ -52,16 +52,16 @@ static struct pci_operations lops_pci = {
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, + .init = pci_init, + .scan_bus = pci_scan_bridge, /* PCI Subordinate bus reset is not implemented */ - .ops_pci = &lops_pci, + .ops_pci = &lops_pci, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_PCI, }; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..29625e3 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -14,26 +14,26 @@ typedef unsigned device_t;
static void pci_write_config8(device_t dev, unsigned where, unsigned char value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); }
static void pci_write_config32(device_t dev, unsigned where, unsigned value) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); }
static unsigned pci_read_config32(device_t dev, unsigned where) { unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); }
#define PCI_DEV_INVALID (0xffffffffU) diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c index 0a0c58d..78f836a 100644 --- a/src/southbridge/amd/amd8111/smbus.c +++ b/src/southbridge/amd/amd8111/smbus.c @@ -25,13 +25,13 @@ static struct pci_operations lops_pci = { }; static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = amd8111_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .init = 0, + .scan_bus = scan_static_bus, + .enable = amd8111_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver smbus_driver __pci_driver = { diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c index 13dccf4..4d94a9d 100644 --- a/src/southbridge/amd/amd8111/usb.c +++ b/src/southbridge/amd/amd8111/usb.c @@ -22,16 +22,16 @@ static struct pci_operations lops_pci = {
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, -// .enable = amd8111_enable, - .ops_pci = &lops_pci, + .init = 0, + .scan_bus = scan_static_bus, +// .enable = amd8111_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_USB, }; diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c index 89115c3..a88fe2a 100644 --- a/src/southbridge/amd/amd8111/usb2.c +++ b/src/southbridge/amd/amd8111/usb2.c @@ -31,15 +31,15 @@ static void amd8111_usb2_enable(device_t dev)
static struct device_operations usb2_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = 0, - .enable = amd8111_usb2_enable, - // .ops_pci = &lops_pci, + .scan_bus = 0, + .enable = amd8111_usb2_enable, + // .ops_pci = &lops_pci, };
static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, + .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_8111_USB2, }; diff --git a/src/southbridge/amd/amd8131-disable/bridge.c b/src/southbridge/amd/amd8131-disable/bridge.c index e90f497..cc6f0d6 100644 --- a/src/southbridge/amd/amd8131-disable/bridge.c +++ b/src/southbridge/amd/amd8131-disable/bridge.c @@ -72,18 +72,18 @@ static void amd8131_enable(device_t dev) }
static struct device_operations pcix_ops = { - .read_resources = amd8131_bus_read_resources, - .set_resources = amd8131_bus_set_resources, + .read_resources = amd8131_bus_read_resources, + .set_resources = amd8131_bus_set_resources, .enable_resources = amd8131_bus_enable_resources, - .init = amd8131_bus_init, - .scan_bus = 0, - .enable = amd8131_enable, + .init = amd8131_bus_init, + .scan_bus = 0, + .enable = amd8131_enable, };
static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7450, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7450, };
@@ -101,15 +101,15 @@ static void ioapic_enable(device_t dev)
static struct device_operations ioapic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = 0, .scan_bus = 0, .enable = ioapic_enable, };
static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, + .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7451,
diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index d258450..89670bb 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -282,52 +282,52 @@ static void amd8131_pcix_init(device_t dev)
/* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); - byte |= 0x10; - pci_write_config8(dev, 0x04, byte); + byte |= 0x10; + pci_write_config8(dev, 0x04, byte);
/* Set drive strength */ word = pci_read_config16(dev, 0xe0); - word = 0x0404; - pci_write_config16(dev, 0xe0, word); + word = 0x0404; + pci_write_config16(dev, 0xe0, word); word = pci_read_config16(dev, 0xe4); - word = 0x0404; - pci_write_config16(dev, 0xe4, word); + word = 0x0404; + pci_write_config16(dev, 0xe4, word);
/* Set impedance */ word = pci_read_config16(dev, 0xe8); - word = 0x0404; - pci_write_config16(dev, 0xe8, word); + word = 0x0404; + pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */ /* Errata #51 */ word = pci_read_config16(dev, 0x4c); - word |= 1; - pci_write_config16(dev, 0x4c, word); + word |= 1; + pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); - pci_write_config16(dev, 0xaa, word); + pci_write_config16(dev, 0xaa, word); word = pci_read_config16(dev, 0xac); - pci_write_config16(dev, 0xae, word); + pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword);
/* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); - dword |= (1<<0); - pci_write_config32(dev, 0x44, dword); + dword |= (1<<0); + pci_write_config32(dev, 0x44, dword); }
/* Set up CRC flood enable */ @@ -379,22 +379,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8131_pcix_init, - .scan_bus = amd8131_scan_bridge, - .reset_bus = pci_bus_reset, + .init = amd8131_pcix_init, + .scan_bus = amd8131_scan_bridge, + .reset_bus = pci_bus_reset, };
static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7450, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7450, };
@@ -412,20 +412,20 @@ static void ioapic_enable(device_t dev) }
static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ioapic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = ioapic_enable, - .ops_pci = &pci_ops_pci_dev, + .init = 0, + .scan_bus = 0, + .enable = ioapic_enable, + .ops_pci = &pci_ops_pci_dev, };
static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, + .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7451,
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 88e421e..c25294a 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -130,11 +130,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) cmd |= max_tran << 4; }
- /* Don't attempt to handle PCI-X errors */ - cmd &= ~PCI_X_CMD_DPERR_E; - if (orig_cmd != cmd) { - pci_write_config16(dev, cap + PCI_X_CMD, cmd); - } + /* Don't attempt to handle PCI-X errors */ + cmd &= ~PCI_X_CMD_DPERR_E; + if (orig_cmd != cmd) { + pci_write_config16(dev, cap + PCI_X_CMD, cmd); + }
} @@ -210,13 +210,13 @@ static void amd8132_pcix_init(device_t dev) unsigned chip_rev;
/* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
/* Enable memory write and invalidate ??? */ dword = pci_read_config32(dev, 0x04); - dword |= 0x10; + dword |= 0x10; dword &= ~(1<<6); // PERSP Parity Error Response - pci_write_config32(dev, 0x04, dword); + pci_write_config32(dev, 0x04, dword);
if (chip_rev == 0x01) { /* Errata #37 */ @@ -236,54 +236,54 @@ static void amd8132_pcix_init(device_t dev) /* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword);
- dword = pci_read_config32(dev, 0x40); -// dword &= ~(1<<31); /* WriteChainEnable */ + dword = pci_read_config32(dev, 0x40); +// dword &= ~(1<<31); /* WriteChainEnable */ dword |= (1<<31); dword |= (1<<7);// must set to 1 dword |= (3<<21); //PCIErrorSerrDisable - pci_write_config32(dev, 0x40, dword); + pci_write_config32(dev, 0x40, dword);
- /* EXTARB = 1, COMPAT = 0 */ - dword = pci_read_config32(dev, 0x48); - dword |= (1<<3); + /* EXTARB = 1, COMPAT = 0 */ + dword = pci_read_config32(dev, 0x48); + dword |= (1<<3); dword &= ~(1<<0); dword |= (1<<15); //CLEARPCILOG_L dword |= (1<<19); //PERR FATAL Enable dword |= (1<<22); // SERR FATAL Enable dword |= (1<<23); // LPMARBENABLE dword |= (0x61<<24); //LPMARBCOUNT - pci_write_config32(dev, 0x48, dword); + pci_write_config32(dev, 0x48, dword);
- dword = pci_read_config32(dev, 0x4c); - dword |= (1<<6); //intial prefetch for memory read line request + dword = pci_read_config32(dev, 0x4c); + dword |= (1<<6); //intial prefetch for memory read line request dword |= (1<<9); //continuous prefetch Enable for memory read line request - pci_write_config32(dev, 0x4c, dword); + pci_write_config32(dev, 0x4c, dword);
/* Disable Single-Bit-Error Correction [30] = 0 */ - dword = pci_read_config32(dev, 0x70); - dword &= ~(1<<30); - pci_write_config32(dev, 0x70, dword); + dword = pci_read_config32(dev, 0x70); + dword &= ~(1<<30); + pci_write_config32(dev, 0x70, dword);
//link - dword = pci_read_config32(dev, 0xd4); - dword |= (0x5c<<16); - pci_write_config32(dev, 0xd4, dword); + dword = pci_read_config32(dev, 0xd4); + dword |= (0x5c<<16); + pci_write_config32(dev, 0xd4, dword);
- /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ - dword = pci_read_config32(dev, 0xdc); + /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */ + dword = pci_read_config32(dev, 0xdc); dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE - dword |= (1<<18)|(1<<26); - dword &= ~((3<<16)|(3<<24)); - pci_write_config32(dev, 0xdc, dword); + dword |= (1<<18)|(1<<26); + dword &= ~((3<<16)|(3<<24)); + pci_write_config32(dev, 0xdc, dword);
/* Set up CRC flood enable */ dword = pci_read_config32(dev, 0xc0); @@ -297,12 +297,12 @@ static void amd8132_pcix_init(device_t dev) pci_write_config32(dev, 0xc8, dword); #endif
- if (chip_rev == 0x11) { - /* [18] Clock Gate Enable = 1 */ - dword = pci_read_config32(dev, 0xf0); - dword |= 0x00040008; - pci_write_config32(dev, 0xf0, dword); - } + if (chip_rev == 0x11) { + /* [18] Clock Gate Enable = 1 */ + dword = pci_read_config32(dev, 0xf0); + dword |= 0x00040008; + pci_write_config32(dev, 0xf0, dword); + }
} return; @@ -344,22 +344,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = { #if BRIDGE_40_BIT_SUPPORT - .read_resources = bridge_read_resources, - .set_resources = bridge_set_resources, + .read_resources = bridge_read_resources, + .set_resources = bridge_set_resources, #else - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, #endif .enable_resources = pci_bus_enable_resources, - .init = amd8132_pcix_init, - .scan_bus = amd8132_scan_bridge, - .reset_bus = pci_bus_reset, + .init = amd8132_pcix_init, + .scan_bus = amd8132_scan_bridge, + .reset_bus = pci_bus_reset, };
static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x7458, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x7458, };
static void ioapic_enable(device_t dev) @@ -376,57 +376,57 @@ static void ioapic_enable(device_t dev) } static void amd8132_ioapic_init(device_t dev) { - uint32_t dword; - unsigned chip_rev; + uint32_t dword; + unsigned chip_rev;
- /* Find the revision of the 8132 */ - chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION); + /* Find the revision of the 8132 */ + chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
- if (chip_rev == 0x01) { + if (chip_rev == 0x01) { #if 0 - /* Errata #43 */ - dword = pci_read_config32(dev, 0xc8); + /* Errata #43 */ + dword = pci_read_config32(dev, 0xc8); dword |= (0x3<<23); pci_write_config32(dev, 0xc8, dword); #endif
- } - + }
- if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { - //for b1 b2 - /* Errata #73 */ - dword = pci_read_config32(dev, 0x80); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x80, dword); - dword = pci_read_config32(dev, 0x88); - dword |= (0x1f<<5); - pci_write_config32(dev, 0x88, dword);
- /* Errata #74 */ - dword = pci_read_config32(dev, 0x7c); - dword &= ~(0x3<<30); - dword |= (0x01<<30); - pci_write_config32(dev, 0x7c, dword); - } + if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + //for b1 b2 + /* Errata #73 */ + dword = pci_read_config32(dev, 0x80); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x80, dword); + dword = pci_read_config32(dev, 0x88); + dword |= (0x1f<<5); + pci_write_config32(dev, 0x88, dword); + + /* Errata #74 */ + dword = pci_read_config32(dev, 0x7c); + dword &= ~(0x3<<30); + dword |= (0x01<<30); + pci_write_config32(dev, 0x7c, dword); + }
}
static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations ioapic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = amd8132_ioapic_init, - .scan_bus = 0, - .enable = ioapic_enable, - .ops_pci = &pci_ops_pci_dev, + .init = amd8132_ioapic_init, + .scan_bus = 0, + .enable = ioapic_enable, + .ops_pci = &pci_ops_pci_dev, };
static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, + .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7459,
diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c index 3572fae..4f79fb0 100644 --- a/src/southbridge/amd/amd8151/agp3.c +++ b/src/southbridge/amd/amd8151/agp3.c @@ -38,14 +38,14 @@ static void agp3bridge_init(device_t dev)
static struct device_operations agp3bridge_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = agp3bridge_init, .scan_bus = pci_scan_bridge, };
static const struct pci_driver agp3bridge_driver __pci_driver = { - .ops = &agp3bridge_ops, + .ops = &agp3bridge_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7455, // AGP Bridge }; @@ -70,21 +70,21 @@ static void agp3dev_enable(device_t dev) }
static struct pci_operations pci_ops_pci_dev = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations agp3dev_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = 0, .scan_bus = 0, .enable = agp3dev_enable, .ops_pci = &pci_ops_pci_dev, };
static const struct pci_driver agp3dev_driver __pci_driver = { - .ops = &agp3dev_ops, + .ops = &agp3dev_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x7454, //AGP Device }; diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h index 68de8ad..a8c0d97 100644 --- a/src/southbridge/amd/cimx/sb700/Amd.h +++ b/src/southbridge/amd/cimx/sb700/Amd.h @@ -38,17 +38,17 @@ #define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #endif
-#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
typedef unsigned int AGESA_STATUS;
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) #define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); @@ -56,72 +56,72 @@ typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. } ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits.
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH;
// AGESA Structures
/// The standard header for all AGESA services. typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. } AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved } AMD_IMAGE_HEADER;
/// AGESA Binary module header structure typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER;
-#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7
// SBDFO - Segment Bus Device Function Offset // 31:28 Segment (4-bits) @@ -138,226 +138,226 @@ typedef struct _AMD_MODULE_HEADER {
/// CPUID data received registers format typedef struct _SB_CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX } SB_CPUID_DATA;
#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset
/// HT frequency for external callbacks typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks } HT_FREQUENCIES;
#ifndef BIT0 -#define BIT0 0x0000000000000001ull +#define BIT0 0x0000000000000001ull #endif #ifndef BIT1 -#define BIT1 0x0000000000000002ull +#define BIT1 0x0000000000000002ull #endif #ifndef BIT2 -#define BIT2 0x0000000000000004ull +#define BIT2 0x0000000000000004ull #endif #ifndef BIT3 -#define BIT3 0x0000000000000008ull +#define BIT3 0x0000000000000008ull #endif #ifndef BIT4 -#define BIT4 0x0000000000000010ull +#define BIT4 0x0000000000000010ull #endif #ifndef BIT5 -#define BIT5 0x0000000000000020ull +#define BIT5 0x0000000000000020ull #endif #ifndef BIT6 -#define BIT6 0x0000000000000040ull +#define BIT6 0x0000000000000040ull #endif #ifndef BIT7 -#define BIT7 0x0000000000000080ull +#define BIT7 0x0000000000000080ull #endif #ifndef BIT8 -#define BIT8 0x0000000000000100ull +#define BIT8 0x0000000000000100ull #endif #ifndef BIT9 -#define BIT9 0x0000000000000200ull +#define BIT9 0x0000000000000200ull #endif #ifndef BIT10 -#define BIT10 0x0000000000000400ull +#define BIT10 0x0000000000000400ull #endif #ifndef BIT11 -#define BIT11 0x0000000000000800ull +#define BIT11 0x0000000000000800ull #endif #ifndef BIT12 -#define BIT12 0x0000000000001000ull +#define BIT12 0x0000000000001000ull #endif #ifndef BIT13 -#define BIT13 0x0000000000002000ull +#define BIT13 0x0000000000002000ull #endif #ifndef BIT14 -#define BIT14 0x0000000000004000ull +#define BIT14 0x0000000000004000ull #endif #ifndef BIT15 -#define BIT15 0x0000000000008000ull +#define BIT15 0x0000000000008000ull #endif #ifndef BIT16 -#define BIT16 0x0000000000010000ull +#define BIT16 0x0000000000010000ull #endif #ifndef BIT17 -#define BIT17 0x0000000000020000ull +#define BIT17 0x0000000000020000ull #endif #ifndef BIT18 -#define BIT18 0x0000000000040000ull +#define BIT18 0x0000000000040000ull #endif #ifndef BIT19 -#define BIT19 0x0000000000080000ull +#define BIT19 0x0000000000080000ull #endif #ifndef BIT20 -#define BIT20 0x0000000000100000ull +#define BIT20 0x0000000000100000ull #endif #ifndef BIT21 -#define BIT21 0x0000000000200000ull +#define BIT21 0x0000000000200000ull #endif #ifndef BIT22 -#define BIT22 0x0000000000400000ull +#define BIT22 0x0000000000400000ull #endif #ifndef BIT23 -#define BIT23 0x0000000000800000ull +#define BIT23 0x0000000000800000ull #endif #ifndef BIT24 -#define BIT24 0x0000000001000000ull +#define BIT24 0x0000000001000000ull #endif #ifndef BIT25 -#define BIT25 0x0000000002000000ull +#define BIT25 0x0000000002000000ull #endif #ifndef BIT26 -#define BIT26 0x0000000004000000ull +#define BIT26 0x0000000004000000ull #endif #ifndef BIT27 -#define BIT27 0x0000000008000000ull +#define BIT27 0x0000000008000000ull #endif #ifndef BIT28 -#define BIT28 0x0000000010000000ull +#define BIT28 0x0000000010000000ull #endif #ifndef BIT29 -#define BIT29 0x0000000020000000ull +#define BIT29 0x0000000020000000ull #endif #ifndef BIT30 -#define BIT30 0x0000000040000000ull +#define BIT30 0x0000000040000000ull #endif #ifndef BIT31 -#define BIT31 0x0000000080000000ull +#define BIT31 0x0000000080000000ull #endif #ifndef BIT32 -#define BIT32 0x0000000100000000ull +#define BIT32 0x0000000100000000ull #endif #ifndef BIT33 -#define BIT33 0x0000000200000000ull +#define BIT33 0x0000000200000000ull #endif #ifndef BIT34 -#define BIT34 0x0000000400000000ull +#define BIT34 0x0000000400000000ull #endif #ifndef BIT35 -#define BIT35 0x0000000800000000ull +#define BIT35 0x0000000800000000ull #endif #ifndef BIT36 -#define BIT36 0x0000001000000000ull +#define BIT36 0x0000001000000000ull #endif #ifndef BIT37 -#define BIT37 0x0000002000000000ull +#define BIT37 0x0000002000000000ull #endif #ifndef BIT38 -#define BIT38 0x0000004000000000ull +#define BIT38 0x0000004000000000ull #endif #ifndef BIT39 -#define BIT39 0x0000008000000000ull +#define BIT39 0x0000008000000000ull #endif #ifndef BIT40 -#define BIT40 0x0000010000000000ull +#define BIT40 0x0000010000000000ull #endif #ifndef BIT41 -#define BIT41 0x0000020000000000ull +#define BIT41 0x0000020000000000ull #endif #ifndef BIT42 -#define BIT42 0x0000040000000000ull +#define BIT42 0x0000040000000000ull #endif #ifndef BIT43 -#define BIT43 0x0000080000000000ull +#define BIT43 0x0000080000000000ull #endif #ifndef BIT44 -#define BIT44 0x0000100000000000ull +#define BIT44 0x0000100000000000ull #endif #ifndef BIT45 -#define BIT45 0x0000200000000000ull +#define BIT45 0x0000200000000000ull #endif #ifndef BIT46 -#define BIT46 0x0000400000000000ull +#define BIT46 0x0000400000000000ull #endif #ifndef BIT47 -#define BIT47 0x0000800000000000ull +#define BIT47 0x0000800000000000ull #endif #ifndef BIT48 -#define BIT48 0x0001000000000000ull +#define BIT48 0x0001000000000000ull #endif #ifndef BIT49 -#define BIT49 0x0002000000000000ull +#define BIT49 0x0002000000000000ull #endif #ifndef BIT50 -#define BIT50 0x0004000000000000ull +#define BIT50 0x0004000000000000ull #endif #ifndef BIT51 -#define BIT51 0x0008000000000000ull +#define BIT51 0x0008000000000000ull #endif #ifndef BIT52 -#define BIT52 0x0010000000000000ull +#define BIT52 0x0010000000000000ull #endif #ifndef BIT53 -#define BIT53 0x0020000000000000ull +#define BIT53 0x0020000000000000ull #endif #ifndef BIT54 -#define BIT54 0x0040000000000000ull +#define BIT54 0x0040000000000000ull #endif #ifndef BIT55 -#define BIT55 0x0080000000000000ull +#define BIT55 0x0080000000000000ull #endif #ifndef BIT56 -#define BIT56 0x0100000000000000ull +#define BIT56 0x0100000000000000ull #endif #ifndef BIT57 -#define BIT57 0x0200000000000000ull +#define BIT57 0x0200000000000000ull #endif #ifndef BIT58 -#define BIT58 0x0400000000000000ull +#define BIT58 0x0400000000000000ull #endif #ifndef BIT59 -#define BIT59 0x0800000000000000ull +#define BIT59 0x0800000000000000ull #endif #ifndef BIT60 -#define BIT60 0x1000000000000000ull +#define BIT60 0x1000000000000000ull #endif #ifndef BIT61 -#define BIT61 0x2000000000000000ull +#define BIT61 0x2000000000000000ull #endif #ifndef BIT62 -#define BIT62 0x4000000000000000ull +#define BIT62 0x4000000000000000ull #endif #ifndef BIT63 -#define BIT63 0x8000000000000000ull +#define BIT63 0x8000000000000000ull #endif #endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h index a4aa50e..93da79a 100644 --- a/src/southbridge/amd/cimx/sb700/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -29,13 +29,13 @@ typedef signed char *va_list; #ifndef va_start #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) #endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 )
#pragma pack (push, 1)
-#define IMAGE_ALIGN 32*1024 +#define IMAGE_ALIGN 32*1024 #define NUM_IMAGE_LOCATION 32
//Entry Point Call @@ -76,7 +76,7 @@ typedef enum * * * - * @param[in] pConfig Southbridge configuration structure pointer. + * @param[in] pConfig Southbridge configuration structure pointer. * */ AGESA_STATUS AmdSbDispatcher (IN void *pConfig); diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 261b508..01843a5 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -28,33 +28,33 @@ #ifdef NULL #undef NULL #endif -#define NULL 0 +#define NULL 0
typedef struct _EXT_PCI_ADDR{ - UINT32 Reg :16; - UINT32 Func:3; - UINT32 Dev :5; - UINT32 Bus :8; + UINT32 Reg :16; + UINT32 Func:3; + UINT32 Dev :5; + UINT32 Bus :8; }EXT_PCI_ADDR;
typedef union _PCI_ADDR{ - UINT32 ADDR; - EXT_PCI_ADDR Addr; + UINT32 ADDR; + EXT_PCI_ADDR Addr; }PCI_ADDR;
#ifdef CIM_DEBUG
#if CIM_DEBUG & 2 -void TraceDebug( UINT32 Level, CHAR8 *Format, ...); +void TraceDebug( UINT32 Level, CHAR8 *Format, ...); #define TRACE(Arguments) TraceDebug Arguments #else #define TRACE(Arguments) #endif
#if CIM_DEBUG & 1 -void TraceCode ( UINT32 Level, UINT32 Code); +void TraceCode ( UINT32 Level, UINT32 Code); #define TRACECODE(Arguments) TraceCode Arguments #else #define TRACECODE(Arguments) @@ -84,7 +84,7 @@ void TraceCode ( UINT32 Level, UINT32 Code); #include "SB700.h" #include "SBDEF.h"
-#define DMSG_SB_TRACE 0x02 +#define DMSG_SB_TRACE 0x02
#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 13c6379..9af4812 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "Platform.h" #include "sb_cimx.h" -#include "sb700_cfg.h" /*sb700_cimx_config*/ +#include "sb700_cfg.h" /*sb700_cimx_config*/ #include <console/console.h> #include <console/loglevel.h> #include "smbus.h" @@ -53,7 +53,7 @@ u32 get_sbdn(u32 bus)
/** * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. + * wrapper of sbPowerOnInit entry point. */ void sb_Poweron_Init(void) { diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index e2ecdc3..5760f3c 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -18,19 +18,19 @@ */
-#include <device/device.h> /* device_t */ -#include <device/pci.h> /* device_operations */ +#include <device/device.h> /* device_t */ +#include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> #include <arch/ioapic.h> -#include <device/smbus.h> /* smbus_bus_operations */ +#include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> -#include <console/console.h> /* printk */ +#include <console/console.h> /* printk */ #include <usbdebug.h> -#include "lpc.h" /* lpc_read_resources */ -#include "Platform.h" /* Platfrom Specific Definitions */ +#include "lpc.h" /* lpc_read_resources */ +#include "Platform.h" /* Platfrom Specific Definitions */ #include "sb_cimx.h" -#include "sb700_cfg.h" /* sb700 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ +#include "sb700_cfg.h" /* sb700 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */
/*implement in mainboard.c*/ @@ -46,8 +46,8 @@ static AMDSBCFG *sb_config = &sb_late_cfg; * * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. * @param[in] sb_config Southbridge configuration structure pointer. * */ diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 91d7d2f..7efa0aa 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -24,8 +24,8 @@ #include <console/console.h> /* printk */ #include <cbmem.h>
-#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5
void backup_top_of_ram(uint64_t ramtop) { @@ -115,7 +115,7 @@ void lpc_enable_childrens_resources(device_t dev) end = resource_end(res); /* printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); */ switch (base) { case 0x60: /* KB */ @@ -173,7 +173,7 @@ void lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h index 819c2f2..d67464a 100644 --- a/src/southbridge/amd/cimx/sb700/smbus.h +++ b/src/southbridge/amd/cimx/sb700/smbus.h @@ -44,14 +44,14 @@ /*//SB00.H #define AX_INDXC 0 #define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 +#define AXCFG 4 +#define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3 */
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index f3ce463..f62ac70 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -1,5 +1,5 @@ /***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ + * AMD Generic Encapsulated Software Architecture */ /** * @file * @@ -8,7 +8,7 @@ * Contains AMD AGESA/CIMx core interface * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Include * @e $Revision:$ @e $Date:$ */ @@ -57,17 +57,17 @@ #define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #endif
-#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
typedef unsigned int AGESA_STATUS;
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) #define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); @@ -75,72 +75,72 @@ typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. } ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits.
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH;
// AGESA Structures
/// The standard header for all AGESA services. typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. } AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved } AMD_IMAGE_HEADER;
/// AGESA Binary module header structure typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER;
-#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7
// SBDFO - Segment Bus Device Function Offset // 31:28 Segment (4-bits) @@ -151,232 +151,232 @@ typedef struct _AMD_MODULE_HEADER {
#if 0 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) #endif #define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format typedef struct _CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX } CPUID_DATA;
#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset
/// HT frequency for external callbacks typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks } HT_FREQUENCIES;
#ifndef BIT0 - #define BIT0 0x0000000000000001ull + #define BIT0 0x0000000000000001ull #endif #ifndef BIT1 - #define BIT1 0x0000000000000002ull + #define BIT1 0x0000000000000002ull #endif #ifndef BIT2 - #define BIT2 0x0000000000000004ull + #define BIT2 0x0000000000000004ull #endif #ifndef BIT3 - #define BIT3 0x0000000000000008ull + #define BIT3 0x0000000000000008ull #endif #ifndef BIT4 - #define BIT4 0x0000000000000010ull + #define BIT4 0x0000000000000010ull #endif #ifndef BIT5 - #define BIT5 0x0000000000000020ull + #define BIT5 0x0000000000000020ull #endif #ifndef BIT6 - #define BIT6 0x0000000000000040ull + #define BIT6 0x0000000000000040ull #endif #ifndef BIT7 - #define BIT7 0x0000000000000080ull + #define BIT7 0x0000000000000080ull #endif #ifndef BIT8 - #define BIT8 0x0000000000000100ull + #define BIT8 0x0000000000000100ull #endif #ifndef BIT9 - #define BIT9 0x0000000000000200ull + #define BIT9 0x0000000000000200ull #endif #ifndef BIT10 - #define BIT10 0x0000000000000400ull + #define BIT10 0x0000000000000400ull #endif #ifndef BIT11 - #define BIT11 0x0000000000000800ull + #define BIT11 0x0000000000000800ull #endif #ifndef BIT12 - #define BIT12 0x0000000000001000ull + #define BIT12 0x0000000000001000ull #endif #ifndef BIT13 - #define BIT13 0x0000000000002000ull + #define BIT13 0x0000000000002000ull #endif #ifndef BIT14 - #define BIT14 0x0000000000004000ull + #define BIT14 0x0000000000004000ull #endif #ifndef BIT15 - #define BIT15 0x0000000000008000ull + #define BIT15 0x0000000000008000ull #endif #ifndef BIT16 - #define BIT16 0x0000000000010000ull + #define BIT16 0x0000000000010000ull #endif #ifndef BIT17 - #define BIT17 0x0000000000020000ull + #define BIT17 0x0000000000020000ull #endif #ifndef BIT18 - #define BIT18 0x0000000000040000ull + #define BIT18 0x0000000000040000ull #endif #ifndef BIT19 - #define BIT19 0x0000000000080000ull + #define BIT19 0x0000000000080000ull #endif #ifndef BIT20 - #define BIT20 0x0000000000100000ull + #define BIT20 0x0000000000100000ull #endif #ifndef BIT21 - #define BIT21 0x0000000000200000ull + #define BIT21 0x0000000000200000ull #endif #ifndef BIT22 - #define BIT22 0x0000000000400000ull + #define BIT22 0x0000000000400000ull #endif #ifndef BIT23 - #define BIT23 0x0000000000800000ull + #define BIT23 0x0000000000800000ull #endif #ifndef BIT24 - #define BIT24 0x0000000001000000ull + #define BIT24 0x0000000001000000ull #endif #ifndef BIT25 - #define BIT25 0x0000000002000000ull + #define BIT25 0x0000000002000000ull #endif #ifndef BIT26 - #define BIT26 0x0000000004000000ull + #define BIT26 0x0000000004000000ull #endif #ifndef BIT27 - #define BIT27 0x0000000008000000ull + #define BIT27 0x0000000008000000ull #endif #ifndef BIT28 - #define BIT28 0x0000000010000000ull + #define BIT28 0x0000000010000000ull #endif #ifndef BIT29 - #define BIT29 0x0000000020000000ull + #define BIT29 0x0000000020000000ull #endif #ifndef BIT30 - #define BIT30 0x0000000040000000ull + #define BIT30 0x0000000040000000ull #endif #ifndef BIT31 - #define BIT31 0x0000000080000000ull + #define BIT31 0x0000000080000000ull #endif #ifndef BIT32 - #define BIT32 0x0000000100000000ull + #define BIT32 0x0000000100000000ull #endif #ifndef BIT33 - #define BIT33 0x0000000200000000ull + #define BIT33 0x0000000200000000ull #endif #ifndef BIT34 - #define BIT34 0x0000000400000000ull + #define BIT34 0x0000000400000000ull #endif #ifndef BIT35 - #define BIT35 0x0000000800000000ull + #define BIT35 0x0000000800000000ull #endif #ifndef BIT36 - #define BIT36 0x0000001000000000ull + #define BIT36 0x0000001000000000ull #endif #ifndef BIT37 - #define BIT37 0x0000002000000000ull + #define BIT37 0x0000002000000000ull #endif #ifndef BIT38 - #define BIT38 0x0000004000000000ull + #define BIT38 0x0000004000000000ull #endif #ifndef BIT39 - #define BIT39 0x0000008000000000ull + #define BIT39 0x0000008000000000ull #endif #ifndef BIT40 - #define BIT40 0x0000010000000000ull + #define BIT40 0x0000010000000000ull #endif #ifndef BIT41 - #define BIT41 0x0000020000000000ull + #define BIT41 0x0000020000000000ull #endif #ifndef BIT42 - #define BIT42 0x0000040000000000ull + #define BIT42 0x0000040000000000ull #endif #ifndef BIT43 - #define BIT43 0x0000080000000000ull + #define BIT43 0x0000080000000000ull #endif #ifndef BIT44 - #define BIT44 0x0000100000000000ull + #define BIT44 0x0000100000000000ull #endif #ifndef BIT45 - #define BIT45 0x0000200000000000ull + #define BIT45 0x0000200000000000ull #endif #ifndef BIT46 - #define BIT46 0x0000400000000000ull + #define BIT46 0x0000400000000000ull #endif #ifndef BIT47 - #define BIT47 0x0000800000000000ull + #define BIT47 0x0000800000000000ull #endif #ifndef BIT48 - #define BIT48 0x0001000000000000ull + #define BIT48 0x0001000000000000ull #endif #ifndef BIT49 - #define BIT49 0x0002000000000000ull + #define BIT49 0x0002000000000000ull #endif #ifndef BIT50 - #define BIT50 0x0004000000000000ull + #define BIT50 0x0004000000000000ull #endif #ifndef BIT51 - #define BIT51 0x0008000000000000ull + #define BIT51 0x0008000000000000ull #endif #ifndef BIT52 - #define BIT52 0x0010000000000000ull + #define BIT52 0x0010000000000000ull #endif #ifndef BIT53 - #define BIT53 0x0020000000000000ull + #define BIT53 0x0020000000000000ull #endif #ifndef BIT54 - #define BIT54 0x0040000000000000ull + #define BIT54 0x0040000000000000ull #endif #ifndef BIT55 - #define BIT55 0x0080000000000000ull + #define BIT55 0x0080000000000000ull #endif #ifndef BIT56 - #define BIT56 0x0100000000000000ull + #define BIT56 0x0100000000000000ull #endif #ifndef BIT57 - #define BIT57 0x0200000000000000ull + #define BIT57 0x0200000000000000ull #endif #ifndef BIT58 - #define BIT58 0x0400000000000000ull + #define BIT58 0x0400000000000000ull #endif #ifndef BIT59 - #define BIT59 0x0800000000000000ull + #define BIT59 0x0800000000000000ull #endif #ifndef BIT60 - #define BIT60 0x1000000000000000ull + #define BIT60 0x1000000000000000ull #endif #ifndef BIT61 - #define BIT61 0x2000000000000000ull + #define BIT61 0x2000000000000000ull #endif #ifndef BIT62 - #define BIT62 0x4000000000000000ull + #define BIT62 0x4000000000000000ull #endif #ifndef BIT63 - #define BIT63 0x8000000000000000ull + #define BIT63 0x8000000000000000ull #endif #endif diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h index b007c11..af57440 100644 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb800/AmdSbLib.h @@ -33,13 +33,13 @@ typedef signed char *va_list; #ifndef va_start #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) #endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 )
#pragma pack (push, 1)
-#define IMAGE_ALIGN 32*1024 +#define IMAGE_ALIGN 32*1024 #define NUM_IMAGE_LOCATION 32
//Entry Point Call diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 8ccbe4d..ee38c22 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -27,8 +27,8 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
if SOUTHBRIDGE_AMD_CIMX_SB800 config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" + string + default "southbridge/amd/cimx/sb800/bootblock.c"
config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" @@ -72,15 +72,15 @@ config SB800_SATA_RAID endchoice
config SB800_SATA_MODE - hex + hex depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) default "0x0" if SB800_SATA_IDE default "0x1" if SB800_SATA_RAID default "0x2" if SB800_SATA_AHCI
config SB_SUPERIO_HWM - bool - default n + bool + default n
if SB800_SATA_AHCI config AHCI_ROM_ID @@ -100,8 +100,8 @@ if SB800_SATA_RAID config RAID_ROM_ID string "RAID device PCI IDs" default "1002,4393" - help - 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode + help + 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
config RAID_ROM_FILE string "RAID ROM path and filename" @@ -109,8 +109,8 @@ config RAID_ROM_FILE default "site-local/sb800/raid.bin"
config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "site-local/sb800/misc.bin" + string "RAID Misc ROM path and filename" + default "site-local/sb800/misc.bin" depends on SB800_SATA_RAID
config RAID_MISC_ROM_POSITION diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 2ed5096..e208bfa 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -65,7 +65,7 @@ ifeq ($(CONFIG_SB800_IMC_FWM), y)
# ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address | | +# |0x55AA55AA |EC ROM Address |GEC ROM Address | | # +-----------+---------------+----------------+------------+ # EC ROM should be 64K aligned. SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) @@ -81,7 +81,7 @@ $(obj)/coreboot_SB800_romsig.bin: \ $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \ $(obj)/config.h \ $(obj)/mainboard/$(MAINBOARDDIR)/static.c - echo " SB800 FW $@" + echo " SB800 FW $@" for fwm in 1437226410 \ $(SB800_IMC_POSITION) \ 0 \ diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index fa7d196..8211111 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -28,13 +28,13 @@ #ifdef NULL #undef NULL #endif -#define NULL 0 +#define NULL 0
typedef unsigned long long PLACEHOLDER;
#ifndef SBOEM_ACPI_RESTORE_SWSMI #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 + #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 #endif
#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ @@ -42,23 +42,23 @@ typedef unsigned long long PLACEHOLDER; /* /// Extended PCI Address typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address + UINT32 Reg :16; ///< / PCI Register + UINT32 Func:3; ///< / PCI Function + UINT32 Dev :5; ///< / PCI Device + UINT32 Bus :8; ///< / PCI Address } EXT_PCI_ADDR;
/// PCI Address typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address + UINT32 ADDR; ///< / 32 bit Address + EXT_PCI_ADDR Addr; ///< / Extended PCI Address } PCI_ADDR; */ #endif #define FIXUP_PTR(ptr) ptr
#if CONFIG_SB800_IMC_FWM - #define IMC_ENABLE_OVER_WRITE 0x01 + #define IMC_ENABLE_OVER_WRITE 0x01 #endif
#include <console/console.h> @@ -77,88 +77,88 @@ typedef union _PCI_ADDR {
//------------------------------------------------------------------------------------------------------------------------// /** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable + * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable + * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal + * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable + * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) + * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable + * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) + * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable + * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable + * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable + * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable + * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable + * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable + * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) + * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz + * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable + * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable + * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable + * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable + * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable + * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable + * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable + * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable */ #define SB_CIMx_PARAMETER 0x02
// Generic -#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x01 // Enable -#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz -#define cimSioHwmPortEnableDefault FALSE +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x01 // Enable +#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz +#define cimSioHwmPortEnableDefault FALSE // GPP/AB Controller -#define cimNbSbGen2Default TRUE +#define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller -#define cimUsbPhyPowerDownDefault FALSE +#define cimUsbPhyPowerDownDefault FALSE // GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 // Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable #define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE // Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
@@ -166,7 +166,7 @@ typedef union _PCI_ADDR { #include <spi-generic.h> #endif
-#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5
#endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 1e9ca64..2ad23de 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -44,12 +44,12 @@ Method(_BBN, 0) { /* Bus number = 0 */ } Method(_STA, 0) { /* DBGO("\_SB\PCI0\_STA\n") */ - Return(0x0B) /* Status is visible */ + Return(0x0B) /* Status is visible */ }
Method(_PRT,0) { If(PMOD){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ + Return (PR0) /* PIC Mode */ } /* end _PRT */
/* Describe the Southbridge devices */ @@ -163,7 +163,7 @@ Method(_CRS, 0) {
/* * -* FIRST METHOD CALLED UPON BOOT +* FIRST METHOD CALLED UPON BOOT * * 1. If debugging, print current OS and ACPI interpreter. * 2. Get PCI Interrupt routing from ACPI VSM, this @@ -197,13 +197,13 @@ Scope(){ /* Client Management index/data registers */ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, + CMTI, 8, /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, }
/* GPM Port register */ @@ -222,7 +222,7 @@ Scope(){ /* Flash ROM program enable register */ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, + , 0x00000006, FLRE, 0x00000001, }
@@ -347,8 +347,8 @@ Scope(){ Field(P1EB, ByteAcc, NoLock, Preserve) { TMST, 1, , 3, - BMST, 1, - GBST, 1, + BMST, 1, + GBST, 1, Offset(0x01), PBST, 1, , 1, diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl index 62eb903..1b53a0a 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -25,7 +25,7 @@ Device(LIBR) {
/* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index 435bcb5..ae8df81 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -515,7 +515,7 @@ Scope(_SB) { } Store(Local0, PIRH) } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ + } /* End Device(INTH) */
} /* End Scope(_SB) */
diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl index 4055174..6333a7e 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl @@ -21,18 +21,18 @@ Mutex (SBX0, 0x00) OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) Field (SMB0, ByteAcc, NoLock, Preserve) { - HSTS, 8, /* SMBUS status */ - SSTS, 8, /* SMBUS slave status */ - HCNT, 8, /* SMBUS control */ - HCMD, 8, /* SMBUS host cmd */ - HADD, 8, /* SMBUS address */ - DAT0, 8, /* SMBUS data0 */ - DAT1, 8, /* SMBUS data1 */ - BLKD, 8, /* SMBUS block data */ - SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shadow cmd */ - SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shadow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ }
Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 83087f5..74fe305 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -50,7 +50,7 @@ u32 get_sbdn(u32 bus)
/** * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. + * wrapper of sbPowerOnInit entry point. */ void sb_Poweron_Init(void) { @@ -74,8 +74,8 @@ void sb800_clk_output_48Mhz(void) /* AcpiMMioDecodeEn */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ }
#if CONFIG_HAVE_ACPI_RESUME diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 90b26ae..b24f975 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -49,8 +49,8 @@ static AMDSBCFG *sb_config = &sb_late_cfg; * * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. * @param[in] sb_config Southbridge configuration structure pointer. * */ @@ -78,12 +78,12 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) return ret; }
-#define HOST_CAP 0x00 /* host capabilities */ -#define HOST_CTL 0x04 /* global host control */ -#define HOST_IRQ_STAT 0x08 /* interrupt status */ -#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ +#define HOST_CAP 0x00 /* host capabilities */ +#define HOST_CTL 0x04 /* global host control */ +#define HOST_IRQ_STAT 0x08 /* interrupt status */ +#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
-#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ +#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ static void ahci_raid_init(struct device *dev) { u8 irq = 0; @@ -140,18 +140,18 @@ static void lpc_init(device_t dev) }
static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_LPC, };
static struct device_operations sata_ops = { @@ -212,34 +212,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_HDA, };
static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_GEC, };
/** @@ -248,7 +248,7 @@ static const struct pci_driver gec_driver __pci_driver = { * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] * 'PCIDisable' set to 0 to enable P2P bridge. * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins - * to function as GPIO {GPIO 35:0}. + * to function as GPIO {GPIO 35:0}. */ static void pci_init(device_t dev) { @@ -260,31 +260,31 @@ static void pci_init(device_t dev)
static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB800_PCI, + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB800_PCI, };
struct device_operations bridge_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = 0, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, };
/** diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index a1e0dc9..e81a26a 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -104,7 +104,7 @@ void lpc_enable_childrens_resources(device_t dev) end = resource_end(res); /* printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); */ switch (base) { case 0x60: /* KB */ @@ -162,7 +162,7 @@ void lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 9ec4eb2..8166b34 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -72,7 +72,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); return -2; /* not ready */ }
@@ -102,7 +102,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); return -2; /* not ready */ }
@@ -132,7 +132,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); return -2; /* not ready */ }
@@ -165,7 +165,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); return -2; /* not ready */ }
diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h index 398c086..fb1244f 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ b/src/southbridge/amd/cimx/sb800/smbus.h @@ -41,14 +41,14 @@ /*//SB00.H #define AX_INDXC 0 #define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 +#define AXCFG 4 +#define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3 */
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h index eeb5790..188b12f 100644 --- a/src/southbridge/amd/cimx/sb900/Amd.h +++ b/src/southbridge/amd/cimx/sb900/Amd.h @@ -1,5 +1,5 @@ /***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ + * AMD Generic Encapsulated Software Architecture */ /** * @file * @@ -8,7 +8,7 @@ * Contains AMD AGESA/CIMx core interface * * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA + * @e project: AGESA * @e sub-project: Include * @e $Revision:$ @e $Date:$ */ @@ -57,17 +57,17 @@ #define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) #endif
-#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
typedef unsigned int AGESA_STATUS;
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) #define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); @@ -75,72 +75,72 @@ typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. } ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits.
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. } ACCESS_WIDTH;
// AGESA Structures
/// The standard header for all AGESA services. typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. } AMD_CONFIG_PARAMS;
/// AGESA Binary module header structure typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved } AMD_IMAGE_HEADER;
/// AGESA Binary module header structure typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link } AMD_MODULE_HEADER;
-#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7
// SBDFO - Segment Bus Device Function Offset // 31:28 Segment (4-bits) @@ -151,234 +151,234 @@ typedef struct _AMD_MODULE_HEADER {
#if 0 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ - (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) #endif #define ILLEGAL_SBDFO 0xFFFFFFFF
/* /// CPUID data received registers format typedef struct _SB_CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX } SB_CPUID_DATA; */
#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset
/// HT frequency for external callbacks typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks } HT_FREQUENCIES;
#ifndef BIT0 - #define BIT0 0x0000000000000001ull + #define BIT0 0x0000000000000001ull #endif #ifndef BIT1 - #define BIT1 0x0000000000000002ull + #define BIT1 0x0000000000000002ull #endif #ifndef BIT2 - #define BIT2 0x0000000000000004ull + #define BIT2 0x0000000000000004ull #endif #ifndef BIT3 - #define BIT3 0x0000000000000008ull + #define BIT3 0x0000000000000008ull #endif #ifndef BIT4 - #define BIT4 0x0000000000000010ull + #define BIT4 0x0000000000000010ull #endif #ifndef BIT5 - #define BIT5 0x0000000000000020ull + #define BIT5 0x0000000000000020ull #endif #ifndef BIT6 - #define BIT6 0x0000000000000040ull + #define BIT6 0x0000000000000040ull #endif #ifndef BIT7 - #define BIT7 0x0000000000000080ull + #define BIT7 0x0000000000000080ull #endif #ifndef BIT8 - #define BIT8 0x0000000000000100ull + #define BIT8 0x0000000000000100ull #endif #ifndef BIT9 - #define BIT9 0x0000000000000200ull + #define BIT9 0x0000000000000200ull #endif #ifndef BIT10 - #define BIT10 0x0000000000000400ull + #define BIT10 0x0000000000000400ull #endif #ifndef BIT11 - #define BIT11 0x0000000000000800ull + #define BIT11 0x0000000000000800ull #endif #ifndef BIT12 - #define BIT12 0x0000000000001000ull + #define BIT12 0x0000000000001000ull #endif #ifndef BIT13 - #define BIT13 0x0000000000002000ull + #define BIT13 0x0000000000002000ull #endif #ifndef BIT14 - #define BIT14 0x0000000000004000ull + #define BIT14 0x0000000000004000ull #endif #ifndef BIT15 - #define BIT15 0x0000000000008000ull + #define BIT15 0x0000000000008000ull #endif #ifndef BIT16 - #define BIT16 0x0000000000010000ull + #define BIT16 0x0000000000010000ull #endif #ifndef BIT17 - #define BIT17 0x0000000000020000ull + #define BIT17 0x0000000000020000ull #endif #ifndef BIT18 - #define BIT18 0x0000000000040000ull + #define BIT18 0x0000000000040000ull #endif #ifndef BIT19 - #define BIT19 0x0000000000080000ull + #define BIT19 0x0000000000080000ull #endif #ifndef BIT20 - #define BIT20 0x0000000000100000ull + #define BIT20 0x0000000000100000ull #endif #ifndef BIT21 - #define BIT21 0x0000000000200000ull + #define BIT21 0x0000000000200000ull #endif #ifndef BIT22 - #define BIT22 0x0000000000400000ull + #define BIT22 0x0000000000400000ull #endif #ifndef BIT23 - #define BIT23 0x0000000000800000ull + #define BIT23 0x0000000000800000ull #endif #ifndef BIT24 - #define BIT24 0x0000000001000000ull + #define BIT24 0x0000000001000000ull #endif #ifndef BIT25 - #define BIT25 0x0000000002000000ull + #define BIT25 0x0000000002000000ull #endif #ifndef BIT26 - #define BIT26 0x0000000004000000ull + #define BIT26 0x0000000004000000ull #endif #ifndef BIT27 - #define BIT27 0x0000000008000000ull + #define BIT27 0x0000000008000000ull #endif #ifndef BIT28 - #define BIT28 0x0000000010000000ull + #define BIT28 0x0000000010000000ull #endif #ifndef BIT29 - #define BIT29 0x0000000020000000ull + #define BIT29 0x0000000020000000ull #endif #ifndef BIT30 - #define BIT30 0x0000000040000000ull + #define BIT30 0x0000000040000000ull #endif #ifndef BIT31 - #define BIT31 0x0000000080000000ull + #define BIT31 0x0000000080000000ull #endif #ifndef BIT32 - #define BIT32 0x0000000100000000ull + #define BIT32 0x0000000100000000ull #endif #ifndef BIT33 - #define BIT33 0x0000000200000000ull + #define BIT33 0x0000000200000000ull #endif #ifndef BIT34 - #define BIT34 0x0000000400000000ull + #define BIT34 0x0000000400000000ull #endif #ifndef BIT35 - #define BIT35 0x0000000800000000ull + #define BIT35 0x0000000800000000ull #endif #ifndef BIT36 - #define BIT36 0x0000001000000000ull + #define BIT36 0x0000001000000000ull #endif #ifndef BIT37 - #define BIT37 0x0000002000000000ull + #define BIT37 0x0000002000000000ull #endif #ifndef BIT38 - #define BIT38 0x0000004000000000ull + #define BIT38 0x0000004000000000ull #endif #ifndef BIT39 - #define BIT39 0x0000008000000000ull + #define BIT39 0x0000008000000000ull #endif #ifndef BIT40 - #define BIT40 0x0000010000000000ull + #define BIT40 0x0000010000000000ull #endif #ifndef BIT41 - #define BIT41 0x0000020000000000ull + #define BIT41 0x0000020000000000ull #endif #ifndef BIT42 - #define BIT42 0x0000040000000000ull + #define BIT42 0x0000040000000000ull #endif #ifndef BIT43 - #define BIT43 0x0000080000000000ull + #define BIT43 0x0000080000000000ull #endif #ifndef BIT44 - #define BIT44 0x0000100000000000ull + #define BIT44 0x0000100000000000ull #endif #ifndef BIT45 - #define BIT45 0x0000200000000000ull + #define BIT45 0x0000200000000000ull #endif #ifndef BIT46 - #define BIT46 0x0000400000000000ull + #define BIT46 0x0000400000000000ull #endif #ifndef BIT47 - #define BIT47 0x0000800000000000ull + #define BIT47 0x0000800000000000ull #endif #ifndef BIT48 - #define BIT48 0x0001000000000000ull + #define BIT48 0x0001000000000000ull #endif #ifndef BIT49 - #define BIT49 0x0002000000000000ull + #define BIT49 0x0002000000000000ull #endif #ifndef BIT50 - #define BIT50 0x0004000000000000ull + #define BIT50 0x0004000000000000ull #endif #ifndef BIT51 - #define BIT51 0x0008000000000000ull + #define BIT51 0x0008000000000000ull #endif #ifndef BIT52 - #define BIT52 0x0010000000000000ull + #define BIT52 0x0010000000000000ull #endif #ifndef BIT53 - #define BIT53 0x0020000000000000ull + #define BIT53 0x0020000000000000ull #endif #ifndef BIT54 - #define BIT54 0x0040000000000000ull + #define BIT54 0x0040000000000000ull #endif #ifndef BIT55 - #define BIT55 0x0080000000000000ull + #define BIT55 0x0080000000000000ull #endif #ifndef BIT56 - #define BIT56 0x0100000000000000ull + #define BIT56 0x0100000000000000ull #endif #ifndef BIT57 - #define BIT57 0x0200000000000000ull + #define BIT57 0x0200000000000000ull #endif #ifndef BIT58 - #define BIT58 0x0400000000000000ull + #define BIT58 0x0400000000000000ull #endif #ifndef BIT59 - #define BIT59 0x0800000000000000ull + #define BIT59 0x0800000000000000ull #endif #ifndef BIT60 - #define BIT60 0x1000000000000000ull + #define BIT60 0x1000000000000000ull #endif #ifndef BIT61 - #define BIT61 0x2000000000000000ull + #define BIT61 0x2000000000000000ull #endif #ifndef BIT62 - #define BIT62 0x4000000000000000ull + #define BIT62 0x4000000000000000ull #endif #ifndef BIT63 - #define BIT63 0x8000000000000000ull + #define BIT63 0x8000000000000000ull #endif #endif diff --git a/src/southbridge/amd/cimx/sb900/AmdSbLib.h b/src/southbridge/amd/cimx/sb900/AmdSbLib.h index b007c11..af57440 100644 --- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h +++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h @@ -33,13 +33,13 @@ typedef signed char *va_list; #ifndef va_start #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) #endif -#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) -#define va_end(ap) ( ap = (va_list)0 ) +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 )
#pragma pack (push, 1)
-#define IMAGE_ALIGN 32*1024 +#define IMAGE_ALIGN 32*1024 #define NUM_IMAGE_LOCATION 32
//Entry Point Call diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 5d3b0a1..5a786a7 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -51,8 +51,8 @@ config ACPI_SCI_IRQ Set SCI IRQ to 9.
config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" + string + default "southbridge/amd/cimx/sb900/bootblock.c"
config S3_DATA_POS hex "S3 volatile storage position" diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 5e41978..c4966dc 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -28,13 +28,13 @@ #ifdef NULL #undef NULL #endif -#define NULL 0 +#define NULL 0
typedef unsigned long long PLACEHOLDER;
#ifndef SBOEM_ACPI_RESTORE_SWSMI #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 + #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 #endif
#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ @@ -42,16 +42,16 @@ typedef unsigned long long PLACEHOLDER; /* /// Extended PCI Address typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address + UINT32 Reg :16; ///< / PCI Register + UINT32 Func:3; ///< / PCI Function + UINT32 Dev :5; ///< / PCI Device + UINT32 Bus :8; ///< / PCI Address } EXT_PCI_ADDR;
/// PCI Address typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address + UINT32 ADDR; ///< / 32 bit Address + EXT_PCI_ADDR Addr; ///< / Extended PCI Address } PCI_ADDR; */ #endif @@ -74,85 +74,85 @@ typedef union _PCI_ADDR {
//------------------------------------------------------------------------------------------------------------------------// /** - * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable + * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over + * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable + * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal + * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable + * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) + * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable + * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) + * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable + * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable + * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable + * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable + * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable + * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable + * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable + * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable + * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11) + * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) + * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz + * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable + * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) + * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable + * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable + * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable + * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable + * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable + * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable + * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable + * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable + * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable */ #define SB_CIMx_PARAMETER 0x02
// Generic -#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL // GPP/AB Controller -#define cimNbSbGen2Default TRUE +#define cimNbSbGen2Default TRUE #define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller -#define cimUsbPhyPowerDownDefault FALSE +#define cimUsbPhyPowerDownDefault FALSE // GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 // Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable #define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE // Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 58c0abe..760c31a 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -32,7 +32,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); @@ -261,7 +261,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) void SbPowerOnInit_Config(AMDSBCFG *sb_config) { if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); return; } printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 237137f..61aeebe 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -51,7 +51,7 @@ u32 get_sbdn(u32 bus)
/** * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. + * wrapper of sbPowerOnInit entry point. */ void sb_poweron_init(void) { @@ -81,7 +81,7 @@ void sb_poweron_init(void)
/** * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. + * wrapper of sbPowerOnInit entry point. */ void sb_before_pci_init(void) { diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index d2ce72c..c82043f 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -49,8 +49,8 @@ static AMDSBCFG *sb_config = &sb_late_cfg; * * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. * @param[in] sb_config Southbridge configuration structure pointer. * */ @@ -113,18 +113,18 @@ static void lpc_init(device_t dev) }
static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &lops_pci, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_LPC, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, };
@@ -228,18 +228,18 @@ static void azalia_init(struct device *dev) }
static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = azalia_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_HDA, + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, };
@@ -252,18 +252,18 @@ static void gec_init(struct device *dev) }
static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gec_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gec_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_GEC, + .ops = &gec_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_GEC, };
@@ -275,59 +275,59 @@ static void pcie_init(device_t dev) }
static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCI, + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, };
struct device_operations bridge_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .enable = 0, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .enable = 0, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, };
/* 0:15:0 PCIe PortA */ static const struct pci_driver PORTA_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, };
/* 0:15:1 PCIe PortB */ static const struct pci_driver PORTB_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, };
/* 0:15:2 PCIe PortC */ static const struct pci_driver PORTC_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, };
/* 0:15:3 PCIe PortD */ static const struct pci_driver PORTD_driver __pci_driver = { - .ops = &bridge_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_ATI_SB900_PCIED, + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, };
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 5b414f4..c4a5800 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -100,7 +100,7 @@ void lpc_enable_childrens_resources(device_t dev) end = resource_end(res); /* printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); */ switch (base) { case 0x60: /* KB */ @@ -158,7 +158,7 @@ void lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 650df5c..469e396 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -72,7 +72,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); return -2; /* not ready */ }
@@ -102,7 +102,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); return -2; /* not ready */ }
@@ -132,7 +132,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); return -2; /* not ready */ }
@@ -165,7 +165,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); return -2; /* not ready */ }
diff --git a/src/southbridge/amd/cimx/sb900/smbus.h b/src/southbridge/amd/cimx/sb900/smbus.h index 070b764..4b9d73d 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.h +++ b/src/southbridge/amd/cimx/sb900/smbus.h @@ -40,13 +40,13 @@
#define AX_INDXC 0 #define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 +#define AXCFG 4 +#define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/cs5530/cs5530.c b/src/southbridge/amd/cs5530/cs5530.c index 2b97fe0..502106d 100644 --- a/src/southbridge/amd/cs5530/cs5530.c +++ b/src/southbridge/amd/cs5530/cs5530.c @@ -35,8 +35,8 @@
/* Datasheet: * - Name: AMD Geode Solutions - * Integrated Processors, Companion Devices, and System Platforms - * (Geode CS5530 I/O Companion Multi-Function South Bridge) + * Integrated Processors, Companion Devices, and System Platforms + * (Geode CS5530 I/O Companion Multi-Function South Bridge) * - URL: http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330... * - PDF: http://www.amd.com/files/connectivitysolutions/geode/5530_db_v41.pdf * - Date: September 2004 diff --git a/src/southbridge/amd/cs5530/pirq.c b/src/southbridge/amd/cs5530/pirq.c index f26b722..f2cb2bd 100644 --- a/src/southbridge/amd/cs5530/pirq.c +++ b/src/southbridge/amd/cs5530/pirq.c @@ -29,7 +29,7 @@ void pirq_assign_irqs(const unsigned char pIntAtoD[4]) device_t pdev;
pdev = dev_find_device(PCI_VENDOR_ID_CYRIX, - PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0); + PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0);
if (pdev) { pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0])); diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c index 66ab239..422c57e 100644 --- a/src/southbridge/amd/cs5530/vga.c +++ b/src/southbridge/amd/cs5530/vga.c @@ -308,20 +308,20 @@ static void dc_setup_layout(u32 gx_base, const struct video_mode *mode) * Note: This routine assumes unlocked DC registers * * |<------------------------- htotal ----------------------------->| - * |<------------ hactive -------------->| | - * | hblankstart-->| | - * | hblankend-->| - * | hsyncstart-->| | - * | hsyncend-->| | + * |<------------ hactive -------------->| | + * | hblankstart-->| | + * | hblankend-->| + * | hsyncstart-->| | + * | hsyncend-->| | * |#####################################___________________________| RGB data * |______________________________________________---------_________| HSYNC * * |<------------------------- vtotal ----------------------------->| - * |<------------ vactive -------------->| | - * | vblankstart-->| | - * | vblankend-->| - * | vsyncstart-->| | - * | vsyncend-->| | + * |<------------ vactive -------------->| | + * | vblankstart-->| | + * | vblankend-->| + * | vsyncstart-->| | + * | vsyncend-->| | * |#####################################___________________________| line data * |______________________________________________---------_________| YSYNC */ @@ -480,10 +480,10 @@ static void cs5530_vga_init(device_t dev)
static struct device_operations vga_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = cs5530_vga_init, - .enable = NULL, /* not required */ + .init = cs5530_vga_init, + .enable = NULL, /* not required */ };
static const struct pci_driver vga_pci_driver __pci_driver = { diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 42707c0..a3ee645 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -90,11 +90,11 @@ static void cs5535_read_resources(device_t dev)
static struct device_operations southbridge_ops = { .read_resources = cs5535_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .init = southbridge_init, + .enable = southbridge_enable, + .scan_bus = scan_static_bus, };
static const struct pci_driver cs5535_pci_driver __pci_driver = { @@ -104,9 +104,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = { };
struct chip_operations southbridge_amd_cs5535_ops = { - CHIP_NAME("AMD Geode CS5535 Southbridge") - /* This is only called when this device is listed in the - * static device tree. - */ - .enable_dev = southbridge_enable, + CHIP_NAME("AMD Geode CS5535 Southbridge") + /* This is only called when this device is listed in the + * static device tree. + */ + .enable_dev = southbridge_enable, }; diff --git a/src/southbridge/amd/cs5535/ide.c b/src/southbridge/amd/cs5535/ide.c index b997ca2..67b4eb6 100644 --- a/src/southbridge/amd/cs5535/ide.c +++ b/src/southbridge/amd/cs5535/ide.c @@ -17,10 +17,10 @@ static void ide_enable(struct device *dev)
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = ide_enable, + .init = ide_init, + .enable = ide_enable, };
static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/amd/cs5535/smbus.h b/src/southbridge/amd/cs5535/smbus.h index db35f6e..42dd3ef 100644 --- a/src/southbridge/amd/cs5535/smbus.h +++ b/src/southbridge/amd/cs5535/smbus.h @@ -29,12 +29,12 @@
#define SMB_CTRL1_STASTRE (0x01 << 7) #define SMB_CTRL1_NMINTE (0x01 << 6) -#define SMB_CTRL1_GCMEN (0x01 << 5) -#define SMB_CTRL1_ACK (0x01 << 4) -#define SMB_CTRL1_RSVD (0x01 << 3) -#define SMB_CTRL1_INTEN (0x01 << 2) -#define SMB_CTRL1_STOP (0x01 << 1) -#define SMB_CTRL1_START (0x01 << 0) +#define SMB_CTRL1_GCMEN (0x01 << 5) +#define SMB_CTRL1_ACK (0x01 << 4) +#define SMB_CTRL1_RSVD (0x01 << 3) +#define SMB_CTRL1_INTEN (0x01 << 2) +#define SMB_CTRL1_STOP (0x01 << 1) +#define SMB_CTRL1_START (0x01 << 0)
#define SMB_ADD_SAEN (0x01 << 7)
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e305594..1199294 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -120,23 +120,23 @@ static void pmChipsetInit(void) val = 0x0E00; /* 1ms */ outl(val, port);
- /* PM_WKXD */ - /* Make sure bits[3:0]=0000b to clear the */ - /* saved Sx state */ + /* PM_WKXD */ + /* Make sure bits[3:0]=0000b to clear the */ + /* saved Sx state */ port = (PMS_IO_BASE + 0x034); val = 0x0A0; /* 5ms */ outl(val, port);
- /* PM_WKD */ + /* PM_WKD */ port = (PMS_IO_BASE + 0x030); outl(val, port);
- /* PM_SED */ + /* PM_SED */ port = (PMS_IO_BASE + 0x014); val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */ outl(val, port);
- /* PM_SIDD */ + /* PM_SIDD */ port = (PMS_IO_BASE + 0x020); val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */ outl(val, port); @@ -174,14 +174,14 @@ static void ChipsetFlashSetup(void) msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], - msr.hi, msr.lo); + msr.hi, msr.lo); wrmsr(FlashPort[i], msr);
/* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, - msr.hi, msr.lo); + msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr);
/* update the number enabled */ @@ -308,7 +308,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb) outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
/* GPIO9 - UART1_RX */ - /* Set: Input Enable (0x20) */ + /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); @@ -471,12 +471,12 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /* Overcurrent configuration */ if (sb->enable_USBP4_overcurrent) { write32(bar + UOCCAP, read32(bar + UOCCAP) - | sb->enable_USBP4_overcurrent); + | sb->enable_USBP4_overcurrent); } }
/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device, - * then perform the following sequence: + * then perform the following sequence: * * - set SD bit in DEVCTRL udc register * - set PADEN (former OTGPADEN) bit in uoc register @@ -487,7 +487,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) if (dev) { bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); write32(bar + UDCDEVCTL, - read32(bar + UDCDEVCTL) | UDC_SD_SET); + read32(bar + UDCDEVCTL) | UDC_SD_SET);
}
@@ -561,14 +561,14 @@ void chipsetinit(void) outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
- /* Allow IO read and writes during a ATA DMA operation. */ - /* This could be done in the HD rom but do it here for easier debugging. */ + /* Allow IO read and writes during a ATA DMA operation. */ + /* This could be done in the HD rom but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; wrmsr(msrnum, msr);
- /* Enable Post Primary IDE. */ + /* Enable Post Primary IDE. */ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); msr.lo |= GLPCI_CRTL_PPIDE_SET; @@ -581,14 +581,14 @@ void chipsetinit(void) wrmsr(csi->msrnum, msr); // MSR - see table above }
- /* Flash BAR size Setup */ + /* Flash BAR size Setup */ printk(BIOS_INFO, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup();
/* */ - /* Set up Hardware Clock Gating */ + /* Set up Hardware Clock Gating */ /* */ { csi = CS5536_CLOCK_GATING_TABLE; @@ -639,7 +639,7 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", - sb->unwanted_vpci[i]); + sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); } @@ -691,7 +691,7 @@ static struct device_operations southbridge_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, -// .enable = southbridge_enable, +// .enable = southbridge_enable, .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..ce5efdc 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -163,11 +163,11 @@ static void cs5536_setup_onchipuart1(void)
/* Setup early for polling only mode. * 1. Enable GPIO 8 to OUT_AUX1, 9 to IN_AUX1. - * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 + * GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34 * 2. Enable UART I/O space in MDD. - * MSR 0x51400014 bit 18:16 + * MSR 0x51400014 bit 18:16 * 3. Enable UART controller. - * MSR 0x5140003A bit 0, 1 + * MSR 0x5140003A bit 0, 1 */
/* GPIO8 - UART1_TX */ @@ -207,7 +207,7 @@ static void cs5536_setup_onchipuart2(void) /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); /* GPIO4 - UART2_RX */ - /* Set: Input Enable (0x20) */ + /* Set: Input Enable (0x20) */ outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); diff --git a/src/southbridge/amd/cs5536/pirq.c b/src/southbridge/amd/cs5536/pirq.c index 4919ea2..19f2cf0 100644 --- a/src/southbridge/amd/cs5536/pirq.c +++ b/src/southbridge/amd/cs5536/pirq.c @@ -29,7 +29,7 @@ void pirq_assign_irqs(const unsigned char pIntAtoD[4]) device_t pdev;
pdev = dev_find_device(PCI_VENDOR_ID_AMD, - PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
if (pdev) { pci_write_config16(pdev, 0x5c, (pIntAtoD[3] << 12 diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c index bdc089d..ed4f951 100644 --- a/src/southbridge/amd/cs5536/smbus.c +++ b/src/southbridge/amd/cs5536/smbus.c @@ -100,7 +100,7 @@ static int smbus_ack(unsigned smbus_io_base, int state) }
int smbus_send_slave_address(unsigned smbus_io_base, - unsigned char device) + unsigned char device) { unsigned char val;
diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h index 0dd2fc5..9fba3e0 100644 --- a/src/southbridge/amd/cs5536/smbus.h +++ b/src/southbridge/amd/cs5536/smbus.h @@ -26,7 +26,7 @@ int smbus_start_condition(unsigned smbus_io_base); int smbus_stop_condition(unsigned smbus_io_base); int smbus_check_stop_condition(unsigned smbus_io_base); int smbus_send_slave_address(unsigned smbus_io_base, - unsigned char device); + unsigned char device); int smbus_send_command(unsigned smbus_io_base, unsigned char command);
unsigned char do_smbus_read_byte(unsigned smbus_io_base, diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 36870b3..c3fb613 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -213,11 +213,11 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) /* Fill MMIO limit/base pair. */ pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); + 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, (((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | (sblk << 4)); + 1) >> 8) & 0xffffff00) | (sblk << 4)); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); } else { pci_write_config32(k8_f1, 0xb8, 0); @@ -233,14 +233,14 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) case 2: /* GFX, bit4-5 */ case 3: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 2), 0 << (port + 2)); + 1 << (port + 2), 0 << (port + 2)); break; case 4: /* GPP, bit20-24 */ case 5: case 6: case 7: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 17), 0 << (port + 17)); + 1 << (port + 17), 0 << (port + 17)); break; } } @@ -261,7 +261,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", - port, lc_state); + port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
switch (current) { @@ -287,7 +287,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; reg = - nbpcie_p_read_index(dev, + nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c index b4377f4..e016692 100644 --- a/src/southbridge/amd/rs690/early_setup.c +++ b/src/southbridge/amd/rs690/early_setup.c @@ -102,7 +102,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, }
static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) + u8 val) { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -242,7 +242,7 @@ static void k8_optimization(void) pci_write_config32(k8_f0, 0x90, 0x01700178); /* CIM NPT_Optimization */ set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 26 | 1 << 27, - 1 << 26 | 1 << 27); + 1 << 26 | 1 << 27); set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); /* TODO */
@@ -349,13 +349,13 @@ static void rs690_por_misc_index_init(device_t nb_dev) * HIDE_NB_AGP_CAP ([0], default=1)HIDE * HIDE_P2P_AGP_CAP ([1], default=1)HIDE * HIDE_NB_GART_BAR ([2], default=1)HIDE - * AGPMODE30 ([4], default=0)DISABLE + * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing - * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); + * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
@@ -413,7 +413,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev) * Disables upstream system-management delay */ set_htiu_enable_bits(nb_dev, 0x07, ~0xFFFFFFF9, 0x001);
- /* HTIUNBIND 0x16 [1] = 0x1 Enable crc decoding fix */ + /* HTIUNBIND 0x16 [1] = 0x1 Enable crc decoding fix */ set_htiu_enable_bits(nb_dev, 0x16, ~0xFFFFFFFF, 0x2); }
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c index 42e6c35..854d2f1 100644 --- a/src/southbridge/amd/rs690/gfx.c +++ b/src/southbridge/amd/rs690/gfx.c @@ -21,7 +21,7 @@ * for rs690 internal graphics device * device id of internal grphics: * RS690M/T: 0x791f - * RS690: 0x791e + * RS690: 0x791e */ #include <console/console.h> #include <device/device.h> @@ -260,15 +260,15 @@ static void single_port_configuration(device_t nb_dev, device_t dev) case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe); + cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe); break; case 4: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc); + cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc); break; case 8: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0); + cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0); break; } } @@ -308,11 +308,11 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e); + cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e); break; case 4: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c); + cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c); break; } } @@ -338,11 +338,11 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x7070 : 0xe0e0); + cfg->gfx_lane_reversal ? 0x7070 : 0xe0e0); break; case 4: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x3030 : 0xc0c0); + cfg->gfx_lane_reversal ? 0x3030 : 0xc0c0); break; } } @@ -416,7 +416,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* step 0, REFCLK_SEL, skip A11 revision */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9, - cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9); + cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9); printk(BIOS_INFO, "rs690_gfx_init step0.\n");
/* step 1, lane reversal (only need if CMOS option is enabled) */ @@ -465,48 +465,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */ - if (cfg->gfx_tmds) { - /* step 6.2.2 Clock-Muxing Control */ - /* step 6.2.2.1 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16); + if (cfg->gfx_tmds) { + /* step 6.2.2 Clock-Muxing Control */ + /* step 6.2.2.1 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
- /* step 6.2.2.2 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10); + /* step 6.2.2.2 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8); + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
- /* step 6.2.2.3 */ - set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26); + /* step 6.2.2.3 */ + set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
- /* step 6.2.3 Lane-Muxing Control */ - /* step 6.2.3.1 */ - set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8); + /* step 6.2.3 Lane-Muxing Control */ + /* step 6.2.3.1 */ + set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
- /* step 6.2.4 Received Data Control */ - /* step 6.2.4.1 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16); + /* step 6.2.4 Received Data Control */ + /* step 6.2.4.1 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
- /* step 6.2.4.2 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18); + /* step 6.2.4.2 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
- /* step 6.2.4.3 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20); + /* step 6.2.4.3 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
- /* step 6.2.4.4 */ - set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22); + /* step 6.2.4.4 */ + set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
- /* step 6.2.5 PLL Power Down Control */ - /* step 6.2.5.1 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6); + /* step 6.2.5 PLL Power Down Control */ + /* step 6.2.5.1 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
- /* step 6.2.6 Driving Strength Control */ - /* step 6.2.6.1 */ - set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24); + /* step 6.2.6 Driving Strength Control */ + /* step 6.2.6.1 */ + set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
- /* step 6.2.6.2 */ - set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); - } + /* step 6.2.6.2 */ + set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); + }
- printk(BIOS_INFO, "rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n");
/* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */ diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c index 0bd4da5..e760938 100644 --- a/src/southbridge/amd/rs690/pcie.c +++ b/src/southbridge/amd/rs690/pcie.c @@ -88,7 +88,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) PCIE_GFX_COMPLIANCE))) { }
- if (!cfg->gfx_tmds){ + if (!cfg->gfx_tmds){ /* step 3 Power Down Control for Southbridge */ reg = nbpcie_p_read_index(dev, 0xa2);
@@ -212,7 +212,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
/* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, - 1 << 8); + 1 << 8); /* PCIE initialization 5.10.2: rpr 2.12*/ set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0); /* no description in datasheet. */
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index 23d347c..c1c56f2 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -113,12 +113,12 @@ static u32 get_vid_did(device_t dev) * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default * 0:01.0 P2P Internal: -* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 * case 0 will be called twice, one is by cpu in hypertransport.c line458, * the other is by rs690. @@ -164,7 +164,7 @@ void rs690_enable(device_t dev) case 3: printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs690_gfx_init(nb_dev, dev, dev_ind); break; @@ -175,14 +175,14 @@ void rs690_enable(device_t dev) printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, - (dev->enabled ? 1 : 0) << 6); + (dev->enabled ? 1 : 0) << 6); if (dev->enabled) rs690_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h index 9f143d4..e47a73b 100644 --- a/src/southbridge/amd/rs690/rs690.h +++ b/src/southbridge/amd/rs690/rs690.h @@ -82,16 +82,16 @@ typedef enum _NB_REVISION_ { ------------------- -----------------------*/ #define PCIE_CI_CNTL 0x20 #define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 +#define PCIE_LC_STATE0 0xa5 #define PCIE_VC0_RESOURCE_STATUS 0x11a /* 16bit read only */
#define PCIE_CORE_INDEX_GFX (0 << 16) /* see 5.2.2 */ #define PCIE_CORE_INDEX_GPPSB (1 << 16)
/* contents of PCIE_NBCFG_REG7 */ -#define RECONFIG_GPPSB_EN (1 << 12) +#define RECONFIG_GPPSB_EN (1 << 12) #define RECONFIG_GPPSB_GPPSB (1 << 14) -#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) +#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) #define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17)
/* contents of PCIE_VC0_RESOURCE_STATUS */ diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..6bf27d6 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -212,11 +212,11 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) /* Fill MMIO limit/base pair. */ pci_write_config32(k8_f1, 0xbc, (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); + 1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4)); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, (((mmio_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | (sblk << 4)); + 1) >> 8) & 0xffffff00) | (sblk << 4)); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); } else { pci_write_config32(k8_f1, 0xb8, 0); @@ -232,19 +232,19 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) case 2: /* GFX, bit4-5 */ case 3: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 2), 0 << (port + 2)); + 1 << (port + 2), 0 << (port + 2)); break; case 4: /* GPPSB, bit20-24 */ case 5: case 6: case 7: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 17), 0 << (port + 17)); + 1 << (port + 17), 0 << (port + 17)); break; case 9: /* GPP, bit 4,5 of miscind 0x2D */ case 10: set_nbmisc_enable_bits(nb_dev, 0x2D, - 1 << (port - 5), 0 << (port - 5)); + 1 << (port - 5), 0 << (port - 5)); break; } } @@ -283,7 +283,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", - port, lc_state); + port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
switch (current) { @@ -309,7 +309,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", - current_link_width, lane_mask); + current_link_width, lane_mask); set_pcie_reset(); mdelay(1); set_pcie_dereset(); @@ -328,7 +328,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; reg = - nbpcie_p_read_index(dev, + nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index b3139b5..695f9c5 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -119,7 +119,7 @@ static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 m
static void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) + u8 val) { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); @@ -190,7 +190,7 @@ static const u8 rs780_ibias[] = { [0x2] = 0x4C, /* 400Mhz HyperTransport 1 only */ [0x4] = 0xB6, /* 600Mhz HyperTransport 1 only */ [0x5] = 0x4C, /* 800Mhz HyperTransport 1 only */ - [0x6] = 0x9D, /* 1Ghz HyperTransport 1 only */ + [0x6] = 0x9D, /* 1Ghz HyperTransport 1 only */ /* HT3 for Family 10 */ [0x7] = 0xB6, /* 1.2Ghz HyperTransport 3 only */ [0x8] = 0x2B, /* 1.4Ghz HyperTransport 3 only */ @@ -394,8 +394,8 @@ static void fam10_optimization(void) Set_NB32(cpu_f3, 0x148, 0x8000832A); /* Table 8-26 */ Set_NB32(cpu_f3, 0x158, 0); - /* L3 Disabled: L3 Enabled: */ - /* cores: 2 3 4 2 3 4 */ + /* L3 Disabled: L3 Enabled: */ + /* cores: 2 3 4 2 3 4 */ /* bit8:4 28 26 24 24 20 16 */ if (!l3_cache()) { Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2); @@ -483,13 +483,13 @@ static void rs780_por_misc_index_init(device_t nb_dev) * HIDE_NB_AGP_CAP ([0], default=1)HIDE * HIDE_P2P_AGP_CAP ([1], default=1)HIDE * HIDE_NB_GART_BAR ([2], default=1)HIDE - * AGPMODE30 ([4], default=0)DISABLE + * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ set_nbmisc_enable_bits(nb_dev, 0x00, ~0xFFFF0000, 0x00000506); /* set bit 10 for MSI */
/* NBMISCIND:0x6A[16]= 1 SB link can get a full swing - * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); + * set_nbmisc_enable_bits(nb_dev, 0x6A, 0ffffffffh, 000010000); * NBMISCIND:0x6A[17]=1 Set CMGOOD_OVERRIDE. */ set_nbmisc_enable_bits(nb_dev, 0x6A, ~0xffffffff, 0x00020000);
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 2825925..955e81b 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -311,14 +311,14 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute) * * Inactive B_PRX_PDNB_FDIS B_PTX_PDNB_FDIS * Lanes - * Lanes 0-1 Bit 8 Bit 0 - * Lanes 2-3 Bit 9 Bit 1 - * Lanes 4-5 Bit 10 Bit 2 - * Lanes 6-7 Bit 11 Bit 3 - * Lanes 8-9 Bit 12 Bit 4 - * Lanes 10-11 Bit 13 Bit 5 - * Lanes 12-13 Bit 14 Bit 6 - * Lanes 14-15 Bit 15 Bit 7 + * Lanes 0-1 Bit 8 Bit 0 + * Lanes 2-3 Bit 9 Bit 1 + * Lanes 4-5 Bit 10 Bit 2 + * Lanes 6-7 Bit 11 Bit 3 + * Lanes 8-9 Bit 12 Bit 4 + * Lanes 10-11 Bit 13 Bit 5 + * Lanes 12-13 Bit 14 Bit 6 + * Lanes 14-15 Bit 15 Bit 7 */ static void poweron_ddi_lanes(device_t nb_dev) { @@ -479,7 +479,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulMinSidePortClock = 333*100; #endif
- vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default + vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default
// find the DDR memory frequency if (is_family10h()) { @@ -519,7 +519,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) /* HT speed */ value = pci_read_config8(nb_dev, 0xd1); value = ht_freq_lookup [value] * 100; // HT link frequency in MHz - vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz + vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq;
@@ -1082,15 +1082,15 @@ static void single_port_configuration(device_t nb_dev, device_t dev) case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe); + cfg->gfx_lane_reversal ? 0x7f7f : 0xccfefe); break; case 4: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc); + cfg->gfx_lane_reversal ? 0x3f3f : 0xccfcfc); break; case 8: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0); + cfg->gfx_lane_reversal ? 0x0f0f : 0xccf0f0); break; } } @@ -1137,11 +1137,11 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) case 1: case 2: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e); + cfg->gfx_lane_reversal ? 0x0707 : 0x0e0e); break; case 4: nbpcie_ind_write_index(nb_dev, 0x65, - cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c); + cfg->gfx_lane_reversal ? 0x0303 : 0x0c0c); break; } } @@ -1387,7 +1387,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */ /* 5.9.1.5 Selects the GFX REFCLK to be the source for PLL C. */ set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, - 0); + 0); reg32 = nbmisc_read_index(nb_dev, 0x28); printk(BIOS_DEBUG, "misc 28 = %x\n", reg32);
@@ -1527,8 +1527,8 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* 5.9.12.30. Set TX arbitration algorithm to round robin */ set_pcie_enable_bits(nb_dev, 0x1C, - 1 << 0 | 0x1F << 1 | 0x1F << 6, - 1 << 0 | 0x04 << 1 | 0x04 << 6); + 1 << 0 | 0x1F << 1 | 0x1F << 6, + 1 << 0 | 0x04 << 1 | 0x04 << 6);
/* Single-port/Dual-port configureation. */ switch (cfg->gfx_dual_slot) { diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index fcf3d94..959315b 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -96,11 +96,11 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port) switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */ case 1: set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, - 0x0f0f, 0x0e0e); + 0x0f0f, 0x0e0e); break; case 2: set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB, - 0x0f0f, 0x0c0c); + 0x0f0f, 0x0c0c); break; default: break; @@ -253,7 +253,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) /* init GPP core */ /* 5.10.8.3. Disable slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20 | gfx_gpp_sb_sel, 1 << 8, - 1 << 8); + 1 << 8); /* 5.10.8.7. PCIE initialization 5.10.2: rpr 2.12*/ set_pcie_enable_bits(nb_dev, 0x02 | gfx_gpp_sb_sel, 1 << 0, 1 << 0); /* no description in datasheet. */
@@ -326,8 +326,8 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) } /* 5.10.8.30. Set TX arbitration algorithm to round robin. */ set_pcie_enable_bits(nb_dev, 0x1C | gfx_gpp_sb_sel, - 1 << 0 | 0x1F << 1 | 0x1F << 6, - 1 << 0 | 0x04 << 1 | 0x04 << 6); + 1 << 0 | 0x1F << 1 | 0x1F << 6, + 1 << 0 | 0x04 << 1 | 0x04 << 6);
/* check compliance rpr step 2.1*/ if (AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE) { diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index dc5b9e4..c793e10 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -276,12 +276,12 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default * 0:01.0 P2P Internal: -* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 * case 0 will be called twice, one is by cpu in hypertransport.c line458, * the other is by rs780. @@ -330,7 +330,7 @@ void rs780_enable(device_t dev) case 3: printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs780_gfx_init(nb_dev, dev, dev_ind); break; @@ -341,14 +341,14 @@ void rs780_enable(device_t dev) printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, - (dev->enabled ? 1 : 0) << 6); + (dev->enabled ? 1 : 0) << 6); if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; @@ -357,7 +357,7 @@ void rs780_enable(device_t dev) printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); + (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind);
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index c44a813..746ef71 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -92,37 +92,37 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 // =0: Voltage settings is determined by VBIOS PP table. //[7]=1: Enable CLMC Hybird Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. // =0: Enable regular CLMC mode, CDLD and CILR will be enabled. -//[8]=1: CDLF is supported and enabled by fuse //CHP 914 +//[8]=1: CDLF is supported and enabled by fuse //CHP 914 // =0: CDLF is not supported and not enabled by fuses - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulDDISlot1Config; - ULONG ulDDISlot2Config; - UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved - UCHAR ucUMAChannelNumber; - UCHAR ucDockingPinBit; - UCHAR ucDockingPinPolarity; - ULONG ulDockingPinCFGInfo; - ULONG ulCPUCapInfo; - USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform - // 1 - non inverted waveform - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - ULONG ulHTLinkFreq; //in 10Khz - USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth?? - USHORT usMaxHTLinkWidth; - USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690 - USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690 - USHORT usLinkStatusZeroTime; - USHORT usReserved; - ULONG ulHighVoltageHTLinkFreq; // in 10Khz - ULONG ulLowVoltageHTLinkFreq; // in 10Khz - USHORT usMaxUpStreamHTLinkWidth; - USHORT usMaxDownStreamHTLinkWidth; - USHORT usMinUpStreamHTLinkWidth; - USHORT usMinDownStreamHTLinkWidth; - ULONG ulReserved3[97]; //must be 0x0 + ULONG ulBootUpReqDisplayVector; + ULONG ulOtherDisplayMisc; + ULONG ulDDISlot1Config; + ULONG ulDDISlot2Config; + UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved + UCHAR ucUMAChannelNumber; + UCHAR ucDockingPinBit; + UCHAR ucDockingPinPolarity; + ULONG ulDockingPinCFGInfo; + ULONG ulCPUCapInfo; + USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform + // 1 - non inverted waveform + USHORT usMaxNBVoltage; + USHORT usMinNBVoltage; + USHORT usBootUpNBVoltage; + ULONG ulHTLinkFreq; //in 10Khz + USHORT usMinHTLinkWidth; // if no CLMC, usMinHTLinkWidth should be equal to usMaxHTLinkWidth?? + USHORT usMaxHTLinkWidth; + USHORT usUMASyncStartDelay; // will be same as usK8SyncStartDelay on RS690 + USHORT usUMADataReturnTime; // will be same as usK8DataReturnTime on RS690 + USHORT usLinkStatusZeroTime; + USHORT usReserved; + ULONG ulHighVoltageHTLinkFreq; // in 10Khz + ULONG ulLowVoltageHTLinkFreq; // in 10Khz + USHORT usMaxUpStreamHTLinkWidth; + USHORT usMaxDownStreamHTLinkWidth; + USHORT usMinUpStreamHTLinkWidth; + USHORT usMinDownStreamHTLinkWidth; + ULONG ulReserved3[97]; //must be 0x0 } ATOM_INTEGRATED_SYSTEM_INFO_V2;
/* PCIE config flags */ @@ -150,7 +150,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ------------------- -----------------------*/ #define PCIE_CI_CNTL 0x20 #define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 +#define PCIE_LC_STATE0 0xa5 #define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */
#define PCIE_CORE_INDEX_GFX (0x00 << 16) /* see 5.2.2 */ @@ -159,9 +159,9 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 #define PCIE_CORE_INDEX_BRDCST (0x03 << 16)
/* contents of PCIE_NBCFG_REG7 */ -#define RECONFIG_GPPSB_EN (1 << 12) +#define RECONFIG_GPPSB_EN (1 << 12) #define RECONFIG_GPPSB_GPPSB (1 << 14) -#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) +#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) #define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17)
/* contents of PCIE_VC0_RESOURCE_STATUS */ diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index fe9468d..826980c 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -56,7 +56,7 @@ config SATA_MODE default 0 if SATA_MODE_AHCI
config HPET_MIN_TICKS - hex - default 0x14 + hex + default 0x14
endif diff --git a/src/southbridge/amd/sb600/ac97.c b/src/southbridge/amd/sb600/ac97.c index f5c97f7..c704054 100644 --- a/src/southbridge/amd/sb600/ac97.c +++ b/src/southbridge/amd/sb600/ac97.c @@ -32,7 +32,7 @@ static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -/* .enable = sb600_enable, */ +/* .enable = sb600_enable, */ .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, @@ -48,7 +48,7 @@ static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -/* .enable = sb600_enable, */ +/* .enable = sb600_enable, */ .init = 0, .scan_bus = 0, .ops_pci = &lops_pci, diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index c01a051..70271da 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -407,7 +407,7 @@ static void sb600_devices_por_init(void)
/*PHY Global Control, we are using A14. * default: 0x2c40 for ASIC revision A12 and below - * 0x2c00 for ASIC revision A13 and above.*/ + * 0x2c00 for ASIC revision A13 and above.*/ pci_write_config16(dev, 0x86, 0x2C00);
/* PHY Port0-3 Control */ diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c index c65f324..41ddc18 100644 --- a/src/southbridge/amd/sb600/hda.c +++ b/src/southbridge/amd/sb600/hda.c @@ -318,7 +318,7 @@ static struct device_operations hda_audio_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - /*.enable = sb600_enable, */ + /*.enable = sb600_enable, */ .init = hda_init, .scan_bus = 0, .ops_pci = &lops_pci, diff --git a/src/southbridge/amd/sb600/ide.c b/src/southbridge/amd/sb600/ide.c index 2700124..6453ead 100644 --- a/src/southbridge/amd/sb600/ide.c +++ b/src/southbridge/amd/sb600/ide.c @@ -61,7 +61,7 @@ static struct device_operations ide_ops = { .enable_resources = pci_dev_enable_resources, .init = ide_init, .scan_bus = 0, - /* .enable = sb600_enable, */ + /* .enable = sb600_enable, */ .ops_pci = &lops_pci, };
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d1..2fc6685 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -123,7 +123,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) base = res->base; end = resource_end(res); printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); switch (base) { case 0x60: /* KB */ case 0x64: /* MS */ @@ -188,7 +188,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } @@ -225,7 +225,7 @@ static struct device_operations lpc_ops = { .enable_resources = sb600_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, - /* .enable = sb600_enable, */ + /* .enable = sb600_enable, */ .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb600/pci.c b/src/southbridge/amd/sb600/pci.c index ab97dfa..40ccb77 100644 --- a/src/southbridge/amd/sb600/pci.c +++ b/src/southbridge/amd/sb600/pci.c @@ -130,7 +130,7 @@ static struct device_operations pci_ops = { .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, - /* .enable = sb600_enable, */ + /* .enable = sb600_enable, */ .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 8664483..6a0186f 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -264,7 +264,7 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - /* .enable = sb600_enable, */ + /* .enable = sb600_enable, */ .init = sata_init, .scan_bus = 0, .ops_pci = &lops_pci, diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c index c8fa6d8..144d4e5 100644 --- a/src/southbridge/amd/sb600/sb600.c +++ b/src/southbridge/amd/sb600/sb600.c @@ -121,7 +121,7 @@ void sb600_enable(device_t dev) printk(BIOS_DEBUG, "sb600_enable()\n");
/* - * 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 + * 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 * 0:13.1 USB-1 bit 2 of sm_dev 0x68 * 0:13.2 USB-2 bit 3 of sm_dev 0x68 * 0:13.3 USB-3 bit 4 of sm_dev 0x68 @@ -199,7 +199,7 @@ void sb600_enable(device_t dev) case (0x14 << 3) | 2: index = 3; set_pmio_enable_bits(sm_dev, 0x59, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); index += 32 * 4; break; case (0x14 << 3) | 3: @@ -216,12 +216,12 @@ void sb600_enable(device_t dev) index = dev->path.pci.devfn & 7; index -= 5; set_pmio_enable_bits(sm_dev, 0x59, 1 << index, - (dev->enabled ? 0 : 1) << index); + (dev->enabled ? 0 : 1) << index); index += 32 * 4; break; default: printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), - deviceid); + deviceid); } }
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 8de39a6..c1043ce 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -362,7 +362,7 @@ static struct device_operations smbus_ops = { .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_static_bus, - /* .enable = sb600_enable, */ + /* .enable = sb600_enable, */ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb600/smbus.h b/src/southbridge/amd/sb600/smbus.h index ccf78bf..3e59d54 100644 --- a/src/southbridge/amd/sb600/smbus.h +++ b/src/southbridge/amd/sb600/smbus.h @@ -36,11 +36,11 @@
#define AX_INDXC 0 #define AX_INDXP 1 -#define AXCFG 2 -#define ABCFG 3 +#define AXCFG 2 +#define ABCFG 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c index d551661..fc16942 100644 --- a/src/southbridge/amd/sb600/usb.c +++ b/src/southbridge/amd/sb600/usb.c @@ -135,7 +135,7 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init, - /*.enable = sb600_enable, */ + /*.enable = sb600_enable, */ .scan_bus = 0, .ops_pci = &lops_pci, }; @@ -160,7 +160,7 @@ static struct device_operations usb_ops2 = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = usb_init2, - /*.enable = sb600_enable, */ + /*.enable = sb600_enable, */ .scan_bus = 0, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index c290806..8ba1da7 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -30,7 +30,7 @@ * The SB700 power-on default is to map 512K ROM space. * * Details: AMD SB700/710/750 BIOS Developer's Guide (BDG), Rev. 1.00, - * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. + * PN 43366_sb7xx_bdg_pub_1.00, June 2009, section 3.1, page 14. */ static void sb700_enable_rom(void) { diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ddba1a8..27814c1 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -154,7 +154,7 @@ void sb7xx_51xx_lpc_init(void)
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 post_code(0x66); - dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); reg8 |= 1 << 2 | 1 << 3 | 1 << 6 | 1 << 7; reg8 &= ~(1 << 1); diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210..dc407f3 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -167,7 +167,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) base = res->base; end = resource_end(res); printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); switch (base) { case 0x60: /* KB */ case 0x64: /* MS */ @@ -232,7 +232,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index ae79c4a..899cf8b 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -27,9 +27,9 @@ #define HTIC_BIOSR_Detect (1<<5)
#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif
static void set_bios_reset(void) diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index be643fb..7b4101e 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -121,7 +121,7 @@ void sb7xx_51xx_enable(device_t dev) printk(BIOS_DEBUG, "sb7xx_51xx_enable()\n");
/* - * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 + * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 * 0:12.0 OHCI0-USB1 bit 0 of sm_dev 0x68 * 0:12.1 OHCI1-USB1 bit 1 of sm_dev 0x68 * 0:12.2 EHCI-USB1 bit 2 of sm_dev 0x68 @@ -208,7 +208,7 @@ void sb7xx_51xx_enable(device_t dev) case (0x14 << 3) | 2: index = 3; set_pmio_enable_bits(sm_dev, 0x59, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); index += 32 * 4; break; case (0x14 << 3) | 3: @@ -222,7 +222,7 @@ void sb7xx_51xx_enable(device_t dev) break; default: printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), - deviceid); + deviceid); } }
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2c2f6d5..9a73e40 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -242,7 +242,7 @@ static void sm_init(device_t dev) u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ - axindxc_reg(0x02, 1 << 9, 1 << 9); + axindxc_reg(0x02, 1 << 9, 1 << 9); abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); abcfg_reg(0x1009C, 0x00000030, 0x00000030); abcfg_reg(0x10090, 0x00001E00, 0x00001E00); @@ -251,7 +251,7 @@ static void sm_init(device_t dev) abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ - axindxc_reg(0x02, 1 << 10, 1 << 10); + axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */ byte = pci_read_config8(dev, 0x43); diff --git a/src/southbridge/amd/sb700/smbus.h b/src/southbridge/amd/sb700/smbus.h index c2b8c4a..28f2462 100644 --- a/src/southbridge/amd/sb700/smbus.h +++ b/src/southbridge/amd/sb700/smbus.h @@ -43,11 +43,11 @@
#define AX_INDXC 0 #define AX_INDXP 1 -#define AXCFG 2 -#define ABCFG 3 +#define AXCFG 2 +#define ABCFG 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index b3d16bf..8302859 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -317,7 +317,7 @@ struct pm_entry const pm_table[] = {0x04 + 3, 0xFD, BIT1}, {0x74, 0xF6, BIT0 + BIT3}, {0xF0, ~BIT2, 0x00}, - {0xF8, 0x00, 0x6C}, + {0xF8, 0x00, 0x6C}, {0xF8 + 1, 0x00, 0x27}, {0xF8 + 2, 0x00, 0x00}, {0xC4, 0xFE, 0x14}, diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 12fd96f..39c56ed 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -143,7 +143,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) base = res->base; end = resource_end(res); printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); + dev_path(child), base, end); switch (base) { case 0x60: /* KB */ case 0x64: /* MS */ @@ -208,7 +208,7 @@ static void sb800_lpc_enable_childrens_resources(device_t dev) break; } reg_var[var_num++] = - base & 0xffff; + base & 0xffff; } } } diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c index 5d1d80c..f4c80b8 100644 --- a/src/southbridge/amd/sb800/sb800.c +++ b/src/southbridge/amd/sb800/sb800.c @@ -301,7 +301,7 @@ void sb800_enable(device_t dev) case (0x11 << 3) | 0: index = 8; set_pmio_enable_bits(0xDA, 1 << 0, - (dev->enabled ? 1 : 0) << 0); + (dev->enabled ? 1 : 0) << 0); /* Set the device ID of SATA as 0x4390 to reduce the confusing. */ dword = pci_read_config32(dev, 0x40); dword |= 1 << 0; @@ -315,13 +315,13 @@ void sb800_enable(device_t dev) case (0x12 << 3) | 2: index = (dev->path.pci.devfn & 0x3) / 2; set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); break; case (0x13 << 3) | 0: case (0x13 << 3) | 2: index = (dev->path.pci.devfn & 0x3) / 2 + 2; set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); index += 32 * 2; break; case (0x14 << 3) | 0: @@ -330,28 +330,28 @@ void sb800_enable(device_t dev) case (0x14 << 3) | 1: index = 1; set_pmio_enable_bits(0xDA, 1 << 3, - (dev->enabled ? 0 : 1) << 3); + (dev->enabled ? 0 : 1) << 3); break; case (0x14 << 3) | 2: index = 0; set_pmio_enable_bits(0xEB, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); break; case (0x14 << 3) | 3: index = 0; set_pmio_enable_bits(0xEC, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); index += 32 * 1; break; case (0x14 << 3) | 4: index = 0; set_pmio_enable_bits(0xEA, 1 << index, - (dev->enabled ? 0 : 1) << index); + (dev->enabled ? 0 : 1) << index); break; case (0x14 << 3) | 5: index = 6; set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); break; case (0x14 << 3) | 6: /* From linux-2.6.32 to 2.6.34, the broadcom has problems @@ -365,7 +365,7 @@ void sb800_enable(device_t dev) */ index = 0; set_pmio_enable_bits(0xF6, 1 << index, - (dev->enabled ? 0 : 1) << index); + (dev->enabled ? 0 : 1) << index); break; case (0x15 << 3) | 0: set_sb800_gpp(dev); @@ -379,11 +379,11 @@ void sb800_enable(device_t dev) case (0x16 << 3) | 2: index = (dev->path.pci.devfn & 0x3) / 2 + 4; set_pmio_enable_bits(0xEF, 1 << index, - (dev->enabled ? 1 : 0) << index); + (dev->enabled ? 1 : 0) << index); break; default: printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), - deviceid); + deviceid); } }
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 315bc20..19faf4d 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -281,7 +281,7 @@ static void sb800_sm_read_resources(device_t dev) res->gran = 8; res->flags = IORESOURCE_MEM | IORESOURCE_FIXED;
- #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */ + #if 0 /* Linux ACPI crashes when it is 1. For late debugging. */ res = new_resource(dev, 0x14); /* TODO: hpet */ res->base = 0xfed00000; /* reset hpet to widely accepted address */ res->size = 0x400; diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index c1a9ded..84201b3 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -118,7 +118,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) }
int do_smbus_read_byte(u32 smbus_io_base, u32 device, - u32 address) + u32 address) { u8 byte;
@@ -149,7 +149,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, }
int do_smbus_write_byte(u32 smbus_io_base, u32 device, - u32 address, u8 val) + u32 address, u8 val) { u8 byte;
diff --git a/src/southbridge/amd/sb800/smbus.h b/src/southbridge/amd/sb800/smbus.h index 22cdad9..733ef31 100644 --- a/src/southbridge/amd/sb800/smbus.h +++ b/src/southbridge/amd/sb800/smbus.h @@ -38,13 +38,13 @@
#define AX_INDXC 0 #define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 +#define AXCFG 4 +#define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index 7a3e93f..14593f9 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -32,8 +32,8 @@ #define axindxc_reg(reg, mask, val) \ alink_ax_indx(0, (reg), (mask), (val))
-#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4)
static inline u32 nb_read_index(device_t dev, u32 index_reg, u32 index) { @@ -114,7 +114,7 @@ static inline void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, }
static inline void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, - u8 val) + u8 val) { u8 reg_old, reg; reg = reg_old = pci_read_config8(nb_dev, reg_pos); diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 65bce13..78b1600 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -30,22 +30,22 @@ */ static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val) { - u32 tmp; - - /* read axindc to tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 30 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(space << 30 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); + u32 tmp; + + /* read axindc to tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 30 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(space << 30 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); }
@@ -130,7 +130,7 @@ static const u8 sr5650_ibias[] = { [0x2] = 0x44, /* 400Mhz HyperTransport 1 only */ [0x4] = 0xB6, /* 600Mhz HyperTransport 1 only */ [0x5] = 0x44, /* 800Mhz HyperTransport 1 only */ - [0x6] = 0x96, /* 1Ghz HyperTransport 1 only */ + [0x6] = 0x96, /* 1Ghz HyperTransport 1 only */ /* HT3 for Family 10 */ [0x7] = 0xB6, /* 1.2Ghz HyperTransport 3 only */ [0x8] = 0x23, /* 1.4Ghz HyperTransport 3 only */ @@ -370,7 +370,7 @@ static void sr5650_por_misc_index_init(device_t nb_dev) * HIDE_NB_AGP_CAP ([0], default=1)HIDE * HIDE_P2P_AGP_CAP ([1], default=1)HIDE * HIDE_NB_GART_BAR ([2], default=1)HIDE - * AGPMODE30 ([4], default=0)DISABLE + * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 6); diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 737eed2..6283717 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -39,20 +39,20 @@ typedef struct _apic_device_info {
static const apic_device_info default_apic_device_info_t [] = { /* Group Swizzling Port Int Pin */ - [0] = {0, 0, 31}, /* HT */ - [1] = {0, 0, 31}, /* IOMMU */ - [2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */ - [3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */ - [4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */ - [5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */ - [6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */ - [7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */ - [8] = {0, 0, 0 }, /* Reserved */ - [9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */ - [10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */ - [11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */ - [12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */ - [13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */ + [0] = {0, 0, 31}, /* HT */ + [1] = {0, 0, 31}, /* IOMMU */ + [2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */ + [3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */ + [4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */ + [5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */ + [6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */ + [7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */ + [8] = {0, 0, 0 }, /* Reserved */ + [9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */ + [10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */ + [11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */ + [12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */ + [13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */ };
/* Their name are quite regular. So I undefine them. */ diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 7fdecf1..276ce09 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -108,12 +108,12 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) if (in_out) { /* Fill MMIO limit/base pair. */ pci_write_config32(k8_f1, 0xbc, - (((pcie_base_add + 0x10000000 - - 1) >> 8) & 0xffffff00) | 0x8 | (np ? 2 << 4 : 0 << 4)); + (((pcie_base_add + 0x10000000 - + 1) >> 8) & 0xffffff00) | 0x8 | (np ? 2 << 4 : 0 << 4)); pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3); pci_write_config32(k8_f1, 0xb4, - ((mmio_base_add + 0x10000000 - - 1) >> 8) | (np ? 2 << 4 : 0 << 4)); + ((mmio_base_add + 0x10000000 - + 1) >> 8) | (np ? 2 << 4 : 0 << 4)); pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3); } else { pci_write_config32(k8_f1, 0xb8, 0); @@ -130,28 +130,28 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) case 2: /* GPP1, bit4-5 */ case 3: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 2), 0 << (port + 2)); + 1 << (port + 2), 0 << (port + 2)); break; case 4: /* GPP3a, bit20-24 */ case 5: case 6: case 7: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 17), 0 << (port + 17)); + 1 << (port + 17), 0 << (port + 17)); break; case 9: /* GPP3a, bit25,26 */ case 10: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port + 16), 0 << (port + 16)); + 1 << (port + 16), 0 << (port + 16)); break; case 11: /* GPP2, bit6-7 */ case 12: set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG, - 1 << (port - 5), 0 << (port - 5)); + 1 << (port - 5), 0 << (port - 5)); break; case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */ set_nbmisc_enable_bits(nb_dev, 0x2A, - 1 << 4, 0 << 4); + 1 << 4, 0 << 4); break; } } @@ -191,7 +191,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) udelay(40200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", - port, lc_state); + port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
switch (current) { @@ -220,7 +220,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/ nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg); printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", - current_link_width, lane_mask); + current_link_width, lane_mask); set_pcie_reset(); mdelay(1); set_pcie_dereset(); @@ -239,7 +239,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; reg = - nbpcie_p_read_index(dev, + nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ @@ -333,12 +333,12 @@ void sr5650_nb_pci_table(device_t nb_dev) * 0:00.0 NBCFG : * 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default * 0:01.0 P2P Internal: -* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 -* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 +* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 * case 0 will be called twice, one is by cpu in hypertransport.c line458, * the other is by sr5650. @@ -378,7 +378,7 @@ void sr5650_enable(device_t dev) case 3: printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */ break; @@ -390,14 +390,14 @@ void sr5650_enable(device_t dev) printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, - (dev->enabled ? 0 : 1) << dev_ind); + (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, - (dev->enabled ? 1 : 0) << 6); + (dev->enabled ? 1 : 0) << 6); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); disable_pcie_bar3(nb_dev); @@ -408,7 +408,7 @@ void sr5650_enable(device_t dev) dev->enabled); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); + (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ @@ -417,13 +417,13 @@ void sr5650_enable(device_t dev) case 12: /* bus 0, dev 11,12, GPP2 */ printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); + (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); break; case 13: /* bus 0, dev 12, GPP3b */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), - (dev->enabled ? 0 : 1) << (7 + dev_ind)); + (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) sr5650_gpp_sb_init(nb_dev, dev, dev_ind); break; diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c index 47a69af..1245ea1 100644 --- a/src/southbridge/broadcom/bcm21000/pcie.c +++ b/src/southbridge/broadcom/bcm21000/pcie.c @@ -47,33 +47,33 @@ static void pcie_init(struct device *dev) }
static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, };
static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, };
static const struct pci_driver pcie_driver1 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB0, };
static const struct pci_driver pcie_driver2 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB1, };
static const struct pci_driver pcie_driver3 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM21000_EXB2, }; diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c index df42dd3..2e5c239 100644 --- a/src/southbridge/broadcom/bcm5780/nic.c +++ b/src/southbridge/broadcom/bcm5780/nic.c @@ -34,31 +34,31 @@ static void nic_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .init = nic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_BROADCOM, .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC, };
static const struct pci_driver nic1_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_BROADCOM, - .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1, }; diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c index 8e01cef..71b3d03 100644 --- a/src/southbridge/broadcom/bcm5780/pcie.c +++ b/src/southbridge/broadcom/bcm5780/pcie.c @@ -39,22 +39,22 @@ static void pcie_init(struct device *dev) }
static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, };
static struct device_operations pcie_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci,
};
static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PCIE, }; diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c index 92a3547..63f23c6 100644 --- a/src/southbridge/broadcom/bcm5780/pcix.c +++ b/src/southbridge/broadcom/bcm5780/pcix.c @@ -26,27 +26,27 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations ht_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = 0 , - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0 , + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci,
};
static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, + .ops = &ht_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5780_PXB, }; diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 1675097..75ac1ee 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -40,13 +40,13 @@ void bcm5785_enable(device_t dev) sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && - (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) - { - unsigned devfn; - devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); - sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); + (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) + { + unsigned devfn; + devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); + sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; - } + } else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h index 7c7a0b3..afb3430 100644 --- a/src/southbridge/broadcom/bcm5785/chip.h +++ b/src/southbridge/broadcom/bcm5785/chip.h @@ -23,10 +23,10 @@
struct southbridge_broadcom_bcm5785_config { - unsigned int ide0_enable : 1; - unsigned int ide1_enable : 1; - unsigned int sata0_enable : 1; - unsigned int sata1_enable : 1; + unsigned int ide0_enable : 1; + unsigned int ide1_enable : 1; + unsigned int sata0_enable : 1; + unsigned int sata1_enable : 1; };
#endif /* BCM5785_CHIP_H */ diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 60f7abb..14f3de1 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -23,62 +23,62 @@
static void bcm5785_enable_lpc(void) { - uint8_t byte; - device_t dev; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); - - /* LPC Control 0 */ - byte = pci_read_config8(dev, 0x44); - /* Serial 0 */ - byte |= (1<<6); - pci_write_config8(dev, 0x44, byte); - - /* LPC Control 4 */ - byte = pci_read_config8(dev, 0x48); - /* superio port 0x2e/4e enable */ - byte |=(1<<1)|(1<<0); - pci_write_config8(dev, 0x48, byte); + uint8_t byte; + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + + /* LPC Control 0 */ + byte = pci_read_config8(dev, 0x44); + /* Serial 0 */ + byte |= (1<<6); + pci_write_config8(dev, 0x44, byte); + + /* LPC Control 4 */ + byte = pci_read_config8(dev, 0x48); + /* superio port 0x2e/4e enable */ + byte |=(1<<1)|(1<<0); + pci_write_config8(dev, 0x48, byte); }
static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; + device_t dev; + uint32_t dword; + uint32_t dword_old;
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword_old = pci_read_config32(dev, 0x4c); - dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { - pci_write_config32(dev, 0x4c, dword); - } + dword_old = pci_read_config32(dev, 0x4c); + dword = dword_old | (1<<4); //enable Timer Func + if(dword != dword_old ) { + pci_write_config32(dev, 0x4c, dword); + }
- dword_old = pci_read_config32(dev, 0x6c); - dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + dword_old = pci_read_config32(dev, 0x6c); + dword = dword_old | (1<<9); //unhide Timer Func in pci space + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + }
- dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
- /* enable cf9 */ - pci_write_config8(dev, 0x40, (1<<2)); + /* enable cf9 */ + pci_write_config8(dev, 0x40, (1<<2)); }
unsigned get_sbdn(unsigned bus) { - device_t dev; + device_t dev;
- /* Find the device. - * There can only be one bcm5785 on a hypertransport chain/bus. - */ - dev = pci_locate_device_on_bus( - PCI_ID(0x1166, 0x0036), - bus); + /* Find the device. + * There can only be one bcm5785 on a hypertransport chain/bus. + */ + dev = pci_locate_device_on_bus( + PCI_ID(0x1166, 0x0036), + bus);
- return (dev>>15) & 0x1f; + return (dev>>15) & 0x1f;
}
@@ -93,8 +93,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) // set port to 0x2060 outb(0x67, 0xcd6); outb(0x60, 0xcd7); - outb(0x68, 0xcd6); - outb(0x20, 0xcd7); + outb(0x68, 0xcd6); + outb(0x20, 0xcd7);
outb(0x69, 0xcd6); outb(7, 0xcd7); @@ -111,113 +111,113 @@ void ldtstop_sb(void)
void hard_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9();
- set_bios_reset(); + set_bios_reset();
- /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); }
void soft_reset(void) { - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9();
- set_bios_reset(); + set_bios_reset(); #if 1 - /* link reset */ -// outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); + /* link reset */ +// outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); #endif }
static void bcm5785_enable_msg(void) { - device_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; - - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - - byte = pci_read_config8(dev, 0x42); - byte = (1<<1); //enable a20 - pci_write_config8(dev, 0x42, byte); - - dword_old = pci_read_config32(dev, 0x6c); - // bit 5: enable A20 Message - // bit 4: enable interrupt messages - // bit 3: enable reset init message - // bit 2: enable keyboard init message - // bit 1: enable upsteam messages - // bit 0: enable shutdowm message to init generation - dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { - pci_write_config32(dev, 0x6c, dword); - } + device_t dev; + uint32_t dword; + uint32_t dword_old; + uint8_t byte; + + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + + byte = pci_read_config8(dev, 0x42); + byte = (1<<1); //enable a20 + pci_write_config8(dev, 0x42, byte); + + dword_old = pci_read_config32(dev, 0x6c); + // bit 5: enable A20 Message + // bit 4: enable interrupt messages + // bit 3: enable reset init message + // bit 2: enable keyboard init message + // bit 1: enable upsteam messages + // bit 0: enable shutdowm message to init generation + dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor + if(dword != dword_old ) { + pci_write_config32(dev, 0x6c, dword); + } }
static void bcm5785_early_setup(void) { - uint8_t byte; - uint32_t dword; - device_t dev; + uint8_t byte; + uint32_t dword; + device_t dev;
//F0 - // enable device on bcm5785 at first - dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); - dword = pci_read_config32(dev, 0x64); - dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable - dword |= (1<<8); // USB enable - dword |= /* (1<<27)|*/(1<<14); // IDE enable - pci_write_config32(dev, 0x64, dword); - - byte = pci_read_config8(dev, 0x84); - byte |= (1<<0); // SATA enable - pci_write_config8(dev, 0x84, byte); + // enable device on bcm5785 at first + dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); + dword = pci_read_config32(dev, 0x64); + dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable + dword |= (1<<8); // USB enable + dword |= /* (1<<27)|*/(1<<14); // IDE enable + pci_write_config32(dev, 0x64, dword); + + byte = pci_read_config8(dev, 0x84); + byte |= (1<<0); // SATA enable + pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in coreboot_ram to call hard_reset - bcm5785_enable_wdt_port_cf9(); + bcm5785_enable_wdt_port_cf9();
- bcm5785_enable_msg(); + bcm5785_enable_msg();
// IDE related //F0 - byte = pci_read_config8(dev, 0x4e); - byte |= (1<<4); //enable IDE ext regs - pci_write_config8(dev, 0x4e, byte); + byte = pci_read_config8(dev, 0x4e); + byte |= (1<<4); //enable IDE ext regs + pci_write_config8(dev, 0x4e, byte);
//F1 - dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); - byte = pci_read_config8(dev, 0x48); - byte &= ~1; // disable pri channel - pci_write_config8(dev, 0x48, byte); - pci_write_config8(dev, 0xb0, 0x01); - pci_write_config8(dev, 0xb2, 0x02); - byte = pci_read_config8(dev, 0x06); - byte |= (1<<4); // so b0, b2 can not be changed from now - pci_write_config8(dev, 0x06, byte); - byte = pci_read_config8(dev, 0x49); - byte |= 1; // enable second channel - pci_write_config8(dev, 0x49, byte); + dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0); + byte = pci_read_config8(dev, 0x48); + byte &= ~1; // disable pri channel + pci_write_config8(dev, 0x48, byte); + pci_write_config8(dev, 0xb0, 0x01); + pci_write_config8(dev, 0xb2, 0x02); + byte = pci_read_config8(dev, 0x06); + byte |= (1<<4); // so b0, b2 can not be changed from now + pci_write_config8(dev, 0x06, byte); + byte = pci_read_config8(dev, 0x49); + byte |= 1; // enable second channel + pci_write_config8(dev, 0x49, byte);
//F2 - dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); + dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
- byte = pci_read_config8(dev, 0x40); - byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable - pci_write_config8(dev, 0x40, byte); + byte = pci_read_config8(dev, 0x40); + byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable + pci_write_config8(dev, 0x40, byte);
- pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end + pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
// USB related - pci_write_config8(dev, 0x90, 0x40); - pci_write_config8(dev, 0x92, 0x06); - pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register - pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func - pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func - pci_write_config8(dev, 0xb4, 0x40); + pci_write_config8(dev, 0x90, 0x40); + pci_write_config8(dev, 0x92, 0x06); + pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register + pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func + pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func + pci_write_config8(dev, 0xb4, 0x40); } diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..53edc13 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -42,20 +42,20 @@ static void enable_smbus(void)
static inline int smbus_recv_byte(unsigned device) { - return do_smbus_recv_byte(SMBUS_IO_BASE, device); + return do_smbus_recv_byte(SMBUS_IO_BASE, device); }
static inline int smbus_send_byte(unsigned device, unsigned char val) { - return do_smbus_send_byte(SMBUS_IO_BASE, device, val); + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); }
static inline int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 3426a2c..b214b02 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -27,13 +27,13 @@
static void bcm5785_ide_read_resources(device_t dev) { - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev);
- /* BAR */ - pci_get_resource(dev, 0x64); + /* BAR */ + pci_get_resource(dev, 0x64);
- compact_resources(dev); + compact_resources(dev); }
static void ide_init(struct device *dev) @@ -42,26 +42,26 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations ide_ops = { .read_resources = bcm5785_ide_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, + .init = ide_init, + .scan_bus = 0, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_IDE, }; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 834f0a1..fcc28f7 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -78,15 +78,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) { - device_t child; - for (child = link->children; child; child = child->sibling) { + device_t child; + for (child = link->children; child; child = child->sibling) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) { struct resource *res; for(res = child->resource_list; res; res = res->next) { - unsigned long base, end; // don't need long long + unsigned long base, end; // don't need long long if(!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); + base = res->base; + end = resource_end(res); printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC @@ -107,8 +107,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) } } } - } - } + } + } pci_write_config32(dev, 0x44, reg);
@@ -116,32 +116,32 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
static void bcm5785_lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); - bcm5785_lpc_enable_childrens_resources(dev); + pci_dev_enable_resources(dev); + bcm5785_lpc_enable_childrens_resources(dev); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations lpc_ops = { .read_resources = bcm5785_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_static_bus, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC, }; diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..5be8c82 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -22,26 +22,26 @@ #include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12))
typedef unsigned device_t;
static void pci_write_config32(device_t dev, unsigned where, unsigned value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); }
static unsigned pci_read_config32(device_t dev, unsigned where) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); }
#include "../../../northbridge/amd/amdk8/reset_test.c" @@ -49,7 +49,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where) void hard_reset(void) { set_bios_reset(); - /* Try rebooting through port 0xcf9 */ + /* Try rebooting through port 0xcf9 */ /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..cc64594 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -32,28 +32,28 @@ static void sata_init(struct device *dev) uint8_t byte;
u32 mmio; - struct resource *res; - u32 mmio_base; + struct resource *res; + u32 mmio_base; int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 byte = pci_read_config8(dev, 0x78); byte |= (1<<7); - pci_write_config8(dev, 0x78, byte); + pci_write_config8(dev, 0x78, byte);
- res = find_resource(dev, 0x24); - mmio_base = res->base; - mmio_base &= 0xfffffffc; + res = find_resource(dev, 0x24); + mmio_base = res->base; + mmio_base &= 0xfffffffc;
write32(mmio_base + 0x10f0, 0x40000001); write32(mmio_base + 0x8c, 0x00ff2007); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x78592009); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00082004); - mdelay( 10 ); + mdelay( 10 ); write32(mmio_base + 0x8c, 0x00002004); - mdelay( 10 ); + mdelay( 10 );
//init PHY
@@ -66,8 +66,8 @@ static void sata_init(struct device *dev) byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); - byte = read8(mmio + 0x40); - printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); + byte = read8(mmio + 0x40); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } } @@ -75,26 +75,26 @@ static void sata_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, -// .enable = bcm5785_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, +// .enable = bcm5785_enable, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SATA, }; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..e3d7150 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -67,101 +67,101 @@ static void bcm5785_sb_read_resources(device_t dev)
compact_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static int lsmbus_recv_byte(device_t dev) { - unsigned device; - struct resource *res; + unsigned device; + struct resource *res; struct bus *pbus;
- device = dev->path.i2c.device; + device = dev->path.i2c.device; pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90);
- return do_smbus_recv_byte(res->base, device); + return do_smbus_recv_byte(res->base, device); }
static int lsmbus_send_byte(device_t dev, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus;
- device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90);
- return do_smbus_send_byte(res->base, device, val); + return do_smbus_send_byte(res->base, device, val); }
static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus;
- device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90);
- return do_smbus_read_byte(res->base, device, address); + return do_smbus_read_byte(res->base, device, address); }
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus;
- device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90); + res = find_resource(pbus->dev, 0x90);
- return do_smbus_write_byte(res->base, device, address, val); + return do_smbus_write_byte(res->base, device, address, val); }
static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, };
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x2c, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations sb_ops = { - .read_resources = bcm5785_sb_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sb_init, - .scan_bus = scan_static_bus, -// .enable = bcm5785_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .read_resources = bcm5785_sb_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sb_init, + .scan_bus = scan_static_bus, +// .enable = bcm5785_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver sb_driver __pci_driver = { - .ops = &sb_ops, - .vendor = PCI_VENDOR_ID_SERVERWORKS, - .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, + .ops = &sb_ops, + .vendor = PCI_VENDOR_ID_SERVERWORKS, + .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN, }; diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h index bc69107..744a0e0 100644 --- a/src/southbridge/broadcom/bcm5785/smbus.h +++ b/src/southbridge/broadcom/bcm5785/smbus.h @@ -85,54 +85,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + }
- /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + }
- /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD);
return byte; }
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) { - uint8_t byte; + uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + }
- /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + }
- return 0; + return 0; }
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) @@ -146,8 +146,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
byte = inb(smbus_io_base + SMBHSTCTRL); byte &= 0xe3; // Clear [4:2] @@ -167,30 +167,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) { - uint8_t byte; + uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; // not ready - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; // not ready + }
- /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0);
- byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; // Clear [4:2] - byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command - outb(byte, smbus_io_base + SMBHSTCTRL); + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; // Clear [4:2] + byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command + outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; // timeout or error - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; // timeout or error + }
- return 0; + return 0; } diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..a014b7b 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -27,7 +27,7 @@
static void usb_init(struct device *dev) { - uint32_t dword; + uint32_t dword;
dword = pci_read_config32(dev, 0x04); dword |= (1<<2)|(1<<1)|(1<<0); @@ -39,26 +39,26 @@ static void usb_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); }
static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, };
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb_init, -// .enable = bcm5785_enable, - .scan_bus = 0, - .ops_pci = &lops_pci, + .init = usb_init, +// .enable = bcm5785_enable, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_SERVERWORKS, .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_USB, }; diff --git a/src/southbridge/dmp/vortex86ex/ide_sd_sata.c b/src/southbridge/dmp/vortex86ex/ide_sd_sata.c index 8214549..b40ee52 100644 --- a/src/southbridge/dmp/vortex86ex/ide_sd_sata.c +++ b/src/southbridge/dmp/vortex86ex/ide_sd_sata.c @@ -35,48 +35,48 @@ * Primary ATA Timing Register (PATR) - Offset 40-41h * Secondary ATA Timing Register (PATR) - Offset 42-43h * - * Bit R/W Default Description - * 15 R/W 0h ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller. - * 1: Enabled. - * 0: Disabled. - * 14 R/W 0b Device 1 ATA Timing Register Enable - * 1: Enable the device 1 ATA timing. - * 0: Disable the device 1 ATA timing - * 13-12 R/W 0h IORDY Sample Mode. Sets the setup time before IORDY are sampled. - * 00: PIO-0 - * 10: PIO-2, SW-2 - * 10: PIO-3, PIO-4, MW-1, MW-2 - * 11: Reserved - * 11-10 RO 0h Reserved - * 9-8 R/W 0h Recovery Mode. Sets the hold time after IORDY are sampled. - * 00: PIO-0, PIO-2, SW-2 - * 10: PIO-3, MW-1 - * 10: Reserved - * 11: PIO-4, MW-2 - * 7 R/W 0b DMA Timing Enable Only Select 1 - * 1: Enable the device timings for DMA operation for device 1 - * 0: Disable the device timings for DMA operation for device 1 - * 6 R/W 0b ATA/ATAPI Device Indicator 1 - * 1: Indicate presence od an ATA device - * 0: Indicate presence od an ATAPI device - * 5 R/W 0b IORDY Sample Point Enabled Select 1 - * 1: Enable IORDY sample for PIO transfers for device 1 - * 0: Disable IORDY sample for PIO transfers for device 1 - * 4 R/W 0b Fast Drive Timing Select 1 - * 1: Enable faster than PIO-0 timing modes for device 1 - * 0: Disable faster than PIO-0 timing modes for device 1 - * 3 R/W 0b DMA Timing Enable Only Select 0 - * 1: Enable the device timings for DMA operation for device 0 - * 0: Disable the device timings for DMA operation for device 0 - * 2 R/W 0b ATA/ATAPI Device Indicator 0 - * 1: Indicate presence od an ATA device - * 0: Indicate presence od an ATAPI device - * 1 R/W 0b IORDY Sample Point Enabled Select 0 - * 1: Enable IORDY sample for PIO transfers for device 0 - * 0: Disable IORDY sample for PIO transfers for device 0 - * 0 R/W 0b Fast Drive Timing Select 0 - * 1: Enable faster than PIO-0 timing modes for device 0 - * 0: Disable faster than PIO-0 timing modes for device 0 + * Bit R/W Default Description + * 15 R/W 0h ATA Decode Enable. Decode the I/O addressing ranges assigned to this controller. + * 1: Enabled. + * 0: Disabled. + * 14 R/W 0b Device 1 ATA Timing Register Enable + * 1: Enable the device 1 ATA timing. + * 0: Disable the device 1 ATA timing + * 13-12 R/W 0h IORDY Sample Mode. Sets the setup time before IORDY are sampled. + * 00: PIO-0 + * 10: PIO-2, SW-2 + * 10: PIO-3, PIO-4, MW-1, MW-2 + * 11: Reserved + * 11-10 RO 0h Reserved + * 9-8 R/W 0h Recovery Mode. Sets the hold time after IORDY are sampled. + * 00: PIO-0, PIO-2, SW-2 + * 10: PIO-3, MW-1 + * 10: Reserved + * 11: PIO-4, MW-2 + * 7 R/W 0b DMA Timing Enable Only Select 1 + * 1: Enable the device timings for DMA operation for device 1 + * 0: Disable the device timings for DMA operation for device 1 + * 6 R/W 0b ATA/ATAPI Device Indicator 1 + * 1: Indicate presence od an ATA device + * 0: Indicate presence od an ATAPI device + * 5 R/W 0b IORDY Sample Point Enabled Select 1 + * 1: Enable IORDY sample for PIO transfers for device 1 + * 0: Disable IORDY sample for PIO transfers for device 1 + * 4 R/W 0b Fast Drive Timing Select 1 + * 1: Enable faster than PIO-0 timing modes for device 1 + * 0: Disable faster than PIO-0 timing modes for device 1 + * 3 R/W 0b DMA Timing Enable Only Select 0 + * 1: Enable the device timings for DMA operation for device 0 + * 0: Disable the device timings for DMA operation for device 0 + * 2 R/W 0b ATA/ATAPI Device Indicator 0 + * 1: Indicate presence od an ATA device + * 0: Indicate presence od an ATAPI device + * 1 R/W 0b IORDY Sample Point Enabled Select 0 + * 1: Enable IORDY sample for PIO transfers for device 0 + * 0: Disable IORDY sample for PIO transfers for device 0 + * 0 R/W 0b Fast Drive Timing Select 0 + * 1: Enable faster than PIO-0 timing modes for device 0 + * 0: Disable faster than PIO-0 timing modes for device 0 * */
static void init_ide_ata_timing(struct device *dev) @@ -146,26 +146,26 @@ static void vortex_ide_init(struct device *dev)
static struct device_operations vortex_ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = vortex_ide_init, - .scan_bus = 0, + .init = vortex_ide_init, + .scan_bus = 0, };
static const struct pci_driver vortex_ide_driver_1010 __pci_driver = { - .ops = &vortex_ide_ops, + .ops = &vortex_ide_ops, .vendor = PCI_VENDOR_ID_RDC, .device = 0x1010, };
static const struct pci_driver vortex_ide_driver_1011 __pci_driver = { - .ops = &vortex_ide_ops, + .ops = &vortex_ide_ops, .vendor = PCI_VENDOR_ID_RDC, .device = 0x1011, };
static const struct pci_driver vortex_ide_driver_1012 __pci_driver = { - .ops = &vortex_ide_ops, + .ops = &vortex_ide_ops, .vendor = PCI_VENDOR_ID_RDC, .device = 0x1012, }; diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 61c484f..957a2f8 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -578,16 +578,16 @@ static void southbridge_init(struct device *dev)
static struct device_operations vortex_sb_ops = { .read_resources = vortex86_sb_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = &southbridge_init, - .scan_bus = scan_static_bus, - .enable = 0, - .ops_pci = 0, + .init = &southbridge_init, + .scan_bus = scan_static_bus, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver pci_driver_6011 __pci_driver = { - .ops = &vortex_sb_ops, + .ops = &vortex_sb_ops, .vendor = PCI_VENDOR_ID_RDC, .device = 0x6011, /* EX CPU S/B ID */ }; diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 0cc28fa..f64194e 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -40,6 +40,6 @@ #define SB1 PCI_DEV(0, 7, 1) #define SB1_REG_EXT_PIRQ_ROUTE2 0xb4
-#define SYSTEM_CTL_PORT 0x92 +#define SYSTEM_CTL_PORT 0x92
#endif /* SOUTHBRIDGE_H */ diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c2720ef..60bd502 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -79,7 +79,7 @@ config BUILD_WITH_FAKE_IFD WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 8abc56a..e5f0775 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -65,32 +65,32 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) endif - printf " DD Adding Intel Firmware Descriptor\n" + printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" + printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_HAVE_GBE_BIN),y) - printf " IFDTOOL gbe.bin -> coreboot.pre\n" + printf " IFDTOOL gbe.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ -i GbE:$(CONFIG_GBE_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" + printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" + printf " IFDTOOL Unlocking Management Engine\n" $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 99edc31..97ba196 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -52,9 +52,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit + TLVL, 8, // 0x11 - Throttle Level Limit FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold + TCRT, 8, // 0x13 - Critical Threshold TPSV, 8, // 0x14 - Passive Threshold TMAX, 8, // 0x15 - CPU Tj_max F0OF, 8, // 0x16 - FAN 0 OFF Threshold @@ -72,7 +72,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 3b752a4..0a74632 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -350,7 +350,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 670e1ce..c7050bc 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -142,7 +142,7 @@ int intel_early_me_init_done(u8 status)
/* Send message to ME */ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " - "UMA base: 0x%04x\n", status, did.uma_base); + "UMA base: 0x%04x\n", status, did.uma_base);
pci_write_dword_ptr(&did, PCI_ME_H_GS);
@@ -160,7 +160,7 @@ int intel_early_me_init_done(u8 status)
/* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", - me_ack_values[hfs.ack_data]); + me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */ intel_early_me_status(); diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index 6f57f63..ec44842 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -25,7 +25,7 @@ #include <delay.h> #include "pch.h"
-#define SPI_DELAY 10 /* 10us */ +#define SPI_DELAY 10 /* 10us */ #define SPI_RETRY 200000 /* 2s */
static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 09dfcdb..4dd2781 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -80,7 +80,7 @@ void pch_log_state(void) /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_slp_type == 3 ? 3 : 5); + acpi_slp_type == 3 ? 3 : 5);
/* * Wake sources diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 39241d6..905931f 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -91,7 +91,7 @@ unsigned get_gpios(const int *gpio_num_array) unsigned vector = 0;
while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { + ((gpio = *gpio_num_array++) != -1)) { if (get_gpio(gpio)) vector |= bitmask; bitmask <<= 1; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 17be63b..815cf47 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -82,10 +82,10 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -234,7 +234,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); + ndata + 2, host.buffer_depth); return -1; }
@@ -288,8 +288,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, } if (!n) { printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); return -1; }
@@ -315,9 +315,9 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */ @@ -325,7 +325,7 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + "%u != %u\n", ndata, rsp_bytes >> 2); return -1; }
@@ -344,7 +344,7 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, }
static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -402,11 +402,11 @@ static int mkhi_get_fw_version(void) }
printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " - "%u.%u.%u.%u (recovery)\n", - version.code_major, version.code_minor, - version.code_build_number, version.code_hot_fix, - version.recovery_major, version.recovery_minor, - version.recovery_build_number, version.recovery_hot_fix); + "%u.%u.%u.%u (recovery)\n", + version.code_major, version.code_minor, + version.code_build_number, version.code_hot_fix, + version.recovery_major, version.recovery_minor, + version.recovery_build_number, version.recovery_hot_fix);
return 0; } @@ -414,7 +414,7 @@ static int mkhi_get_fw_version(void) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); + name, state ? "en" : "dis"); }
/* Get ME Firmware Capabilities */ @@ -450,7 +450,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); @@ -601,12 +601,12 @@ static me_bios_path intel_me_path(device_t dev) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, + .operation_state = hfs.operation_state, + .operation_mode = hfs.operation_mode, + .error_code = hfs.error_code, + .progress_code = gmes.progress_code, + .current_pmevent = gmes.current_pmevent, + .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, @@ -676,7 +676,7 @@ static int intel_me_extend_valid(device_t dev) break; default: printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); + status.extend_reg_algorithm); return -1; }
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index aaeb24d..144c951 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -217,7 +217,7 @@ struct me_fw_version { } __attribute__ ((packed));
-#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
#define CBM_RR_GLOBAL_RESET 0x01 @@ -255,18 +255,18 @@ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); #endif typedef struct { - u32 major_version : 16; - u32 minor_version : 16; - u32 hotfix_version : 16; - u32 build_version : 16; + u32 major_version : 16; + u32 minor_version : 16; + u32 hotfix_version : 16; + u32 build_version : 16; } __attribute__ ((packed)) mbp_fw_version_name;
typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 register_lock_mask[3]; + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; } __attribute__ ((packed)) mbp_icc_profile;
typedef struct { @@ -296,16 +296,16 @@ typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; - u16 flash_wear_out : 1; + u16 flash_wear_out : 1; u16 flash_variable_security : 1; - u16 wwan3gpresent : 1; + u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; } __attribute__ ((packed)) tdt_state_flag;
typedef struct { - u8 state; - u8 last_theft_trigger; + u8 state; + u8 last_theft_trigger; tdt_state_flag flags; } __attribute__ ((packed)) tdt_state_info;
@@ -321,39 +321,39 @@ typedef struct {
typedef struct { mefwcaps_sku fw_capabilities; - u8 available; + u8 available; } mbp_fw_caps;
typedef struct { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; } __attribute__ ((packed)) mbp_rom_bist_data;
typedef struct { - u32 key[8]; + u32 key[8]; } mbp_platform_key;
typedef struct { platform_type_rule_data rule_data; - u8 available; + u8 available; } mbp_plat_type;
typedef struct { mbp_fw_version_name fw_version_name; - mbp_fw_caps fw_caps_sku; + mbp_fw_caps fw_caps_sku; mbp_rom_bist_data rom_bist_data; mbp_platform_key platform_key; - mbp_plat_type fw_plat_type; + mbp_plat_type fw_plat_type; mbp_icc_profile icc_profile; tdt_state_info at_state; - u32 mfsintegrity; + u32 mfsintegrity; } me_bios_payload;
typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __attribute__ ((packed)) mbp_header;
typedef struct { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 92f132d..7a4294d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -84,10 +84,10 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -236,7 +236,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); + ndata + 2, host.buffer_depth); return -1; }
@@ -290,8 +290,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi, } if (!n) { printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); return -1; }
@@ -308,7 +308,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, ndata++; if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); + ndata, (expected - 1)); return -1; }
@@ -318,9 +318,9 @@ static int mei_recv_msg(struct mkhi_header *mkhi, mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */ @@ -328,7 +328,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + "%u != %u\n", ndata, rsp_bytes >> 2); return -1; }
@@ -347,7 +347,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, }
static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -360,7 +360,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); + name, state ? " en" : "dis"); }
static void me_print_fw_version(mbp_fw_version_name *vers_name) @@ -371,8 +371,8 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) }
printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", - vers_name->major_version, vers_name->minor_version, - vers_name->hotfix_version, vers_name->build_version); + vers_name->major_version, vers_name->minor_version, + vers_name->hotfix_version, vers_name->build_version); }
/* Get ME Firmware Capabilities */ @@ -381,14 +381,14 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) u32 rule_id = 0; struct me_fwcaps cap_msg; struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, }; struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), + .length = sizeof(mkhi) + sizeof(rule_id), };
/* Send request and wait for response */ @@ -396,7 +396,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -420,7 +420,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); @@ -581,7 +581,7 @@ static me_bios_path intel_me_path(device_t dev) /* Check if the MBP is ready */ if (!gmes.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __FUNCTION__); path = ME_ERROR_BIOS_PATH; }
@@ -589,12 +589,12 @@ static me_bios_path intel_me_path(device_t dev) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, + .operation_state = hfs.operation_state, + .operation_mode = hfs.operation_mode, + .error_code = hfs.error_code, + .progress_code = gmes.progress_code, + .current_pmevent = gmes.current_pmevent, + .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, @@ -664,7 +664,7 @@ static int intel_me_extend_valid(device_t dev) break; default: printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); + status.extend_reg_algorithm); return -1; }
@@ -779,7 +779,7 @@ static const struct pci_driver intel_me __pci_driver = { };
/****************************************************************************** - * */ + * */ static u32 me_to_host_words_pending(void) { struct mei_csr me; @@ -829,9 +829,9 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data) if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || (me2host_pending < mbp_hdr.mbp_size)) { printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" - " buffer contains %d words\n", - mbp_hdr.num_entries, mbp_hdr.mbp_size, - me2host_pending); + " buffer contains %d words\n", + mbp_hdr.num_entries, mbp_hdr.mbp_size, + me2host_pending); return -1; }
@@ -845,7 +845,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
if (!me2host_pending) { printk(BIOS_ERR, "ME: no mbp data %d entries to go!\n", - mbp_hdr.num_entries + 1); + mbp_hdr.num_entries + 1); return -1; }
@@ -853,8 +853,8 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
if (mbp_item_hdr.length > me2host_pending) { printk(BIOS_ERR, "ME: insufficient mbp data %d " - "entries to go!\n", - mbp_hdr.num_entries + 1); + "entries to go!\n", + mbp_hdr.num_entries + 1); return -1; }
@@ -867,7 +867,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
#define SET_UP_COPY(field) { copy_addr = (u32 *)&mbp_data->field; \ buffer_room = sizeof(mbp_data->field) / sizeof(u32); \ - break; \ + break; \ }
p = &mbp_item_hdr; @@ -902,14 +902,14 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
default: printk(BIOS_ERR, "ME: unknown mbp item id 0x%x!!!\n", - mbp_item_id); + mbp_item_id); return -1; }
if (buffer_room != copy_size) { printk(BIOS_ERR, "ME: buffer room %d != %d copy size" - " for item 0x%x!!!\n", - buffer_room, copy_size, mbp_item_id); + " for item 0x%x!!!\n", + buffer_room, copy_size, mbp_item_id); return -1; } while(copy_size--) diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b2f38d6..b401fa5 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -148,43 +148,43 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) { #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); + hfs->ft_bup_ld_flr ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); + me_opstate_values[hfs->operation_state]); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[gmes->progress_code]); + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[gmes->progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[gmes->current_pmevent]); + me_pmevent_values[gmes->current_pmevent]);
- printk(BIOS_DEBUG, "ME: Progress Phase State : "); + printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (gmes->progress_code) { case ME_GMES_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[gmes->current_state]); + me_progress_rom_values[gmes->current_state]); break;
case ME_GMES_PHASE_BUP: /* Bringup Phase */ if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) && me_progress_bup_values[gmes->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[gmes->current_state]); + me_progress_bup_values[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break; @@ -193,7 +193,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes) if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values) && me_progress_policy_values[gmes->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[gmes->current_state]); + me_progress_policy_values[gmes->current_state]); else printk(BIOS_DEBUG, "0x%02x", gmes->current_state); break; diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 7b8b6c9..a704e72 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -63,7 +63,7 @@ typedef struct { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 37a0b64..ef790a7 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -247,7 +247,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) u32 old_rpfn = new_rpfn;
printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); + old_fn, new_fn);
new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
@@ -272,15 +272,15 @@ static void pch_pcie_devicetree_update(void)
/* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, + RPFN_FNGET(new_rpfn, PCI_FUNC(dev->path.pci.devfn)));
if (dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); + "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), + PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
dev->path.pci.devfn = new_devfn; } @@ -311,7 +311,7 @@ static void pch_pcie_enable(device_t dev)
if (config->pcie_port_coalesce) printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); + "PCH: PCIe Root Port coalescing is enabled\n"); }
if (!dev->enabled) { @@ -386,7 +386,7 @@ static void pch_pcie_enable(device_t dev) */ if (PCI_FUNC(dev->path.pci.devfn) == 7) { printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); + RCBA32(RPFN), new_rpfn); RCBA32(RPFN) = new_rpfn;
/* Update static devictree with new function numbers */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 90de855..fe5f7ea 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -91,9 +91,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -119,7 +119,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -157,48 +157,48 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -249,7 +249,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -293,13 +293,13 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) +#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) +#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) /* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ @@ -336,7 +336,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
@@ -386,7 +386,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ @@ -437,31 +437,31 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
/* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -469,33 +469,33 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -504,7 +504,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
/* @@ -548,19 +548,19 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ +#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x3808 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_FADDR 0x3808 /* SPI flash address */ +#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
#endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index fadb43f..eaf743c 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -127,7 +127,7 @@ static void pch_pcie_pm_early(struct device *dev) /* Set slot power limit as configured above */ reg32 = pci_read_config32(dev, 0x54); reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ - reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ + reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ reg32 |= (slot_power_limit << 7); pci_write_config32(dev, 0x54, reg32); } @@ -238,13 +238,13 @@ static void pci_init(struct device *dev)
#ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif
/* Clear errors in status registers */ diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 429aad0..9eafcb6 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -23,10 +23,10 @@
void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); }
void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..b4c1555 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -272,7 +272,7 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = sata_set_subsystem, };
static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 4786d8b..16853f9 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -74,7 +74,7 @@ static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = smbus_set_subsystem, };
static void smbus_read_resources(device_t dev) diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index 0166edf..f72bc92 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -353,14 +353,14 @@ static void smm_install(void) /* copy the real SMM handler */ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); memcpy((void *)smm_base, &_binary_smm_start, - (size_t)(&_binary_smm_end - &_binary_smm_start)); + (size_t)(&_binary_smm_end - &_binary_smm_start));
/* copy the IED header into place */ if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { /* Top of TSEG region */ smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); + smm_base); memcpy((void *)smm_base, &ied, sizeof(ied)); } wbinvd(); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 99f6b51..a6c143a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -257,37 +257,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } }
/* @@ -342,7 +342,7 @@ static void xhci_sleep(u8 slp_typ) pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; + PCI_BASE_ADDRESS_0) & ~0xFUL;
if ((xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index ec5d7de..5522ccc 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -186,7 +186,7 @@ static u8 readb_(const void *addr) { u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -194,7 +194,7 @@ static u16 readw_(const void *addr) { u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -202,7 +202,7 @@ static u32 readl_(const void *addr) { u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -210,21 +210,21 @@ static void writeb_(u8 b, const void *addr) { write8((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writew_(u16 b, const void *addr) { write16((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writel_(u32 b, const void *addr) { write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ diff --git a/src/southbridge/intel/esb6300/ac97.c b/src/southbridge/intel/esb6300/ac97.c index 7b7795f..ff2bf89 100644 --- a/src/southbridge/intel/esb6300/ac97.c +++ b/src/southbridge/intel/esb6300/ac97.c @@ -17,21 +17,21 @@ static struct pci_operations lops_pci = { }; static struct device_operations ac97_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = esb6300_enable, - .ops_pci = &lops_pci, + .init = 0, + .scan_bus = 0, + .enable = esb6300_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ac97_audio_driver __pci_driver = { - .ops = &ac97_ops, + .ops = &ac97_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_AUDIO, }; static const struct pci_driver ac97_modem_driver __pci_driver = { - .ops = &ac97_ops, + .ops = &ac97_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_AC97_MODEM, }; diff --git a/src/southbridge/intel/esb6300/bridge1c.c b/src/southbridge/intel/esb6300/bridge1c.c index 54c2717..9bf0d28 100644 --- a/src/southbridge/intel/esb6300/bridge1c.c +++ b/src/southbridge/intel/esb6300/bridge1c.c @@ -32,15 +32,15 @@ static void bridge1c_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = bridge1c_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = bridge1c_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X, }; diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h index c6dc3a3..8525826 100644 --- a/src/southbridge/intel/esb6300/chip.h +++ b/src/southbridge/intel/esb6300/chip.h @@ -1,25 +1,25 @@ struct southbridge_intel_esb6300_config { -#define ESB6300_GPIO_USE_MASK 0x03 +#define ESB6300_GPIO_USE_MASK 0x03 #define ESB6300_GPIO_USE_DEFAULT 0x00 #define ESB6300_GPIO_USE_AS_NATIVE 0x01 #define ESB6300_GPIO_USE_AS_GPIO 0x02
-#define ESB6300_GPIO_SEL_MASK 0x0c +#define ESB6300_GPIO_SEL_MASK 0x0c #define ESB6300_GPIO_SEL_DEFAULT 0x00 -#define ESB6300_GPIO_SEL_OUTPUT 0x04 -#define ESB6300_GPIO_SEL_INPUT 0x08 +#define ESB6300_GPIO_SEL_OUTPUT 0x04 +#define ESB6300_GPIO_SEL_INPUT 0x08
-#define ESB6300_GPIO_LVL_MASK 0x30 +#define ESB6300_GPIO_LVL_MASK 0x30 #define ESB6300_GPIO_LVL_DEFAULT 0x00 -#define ESB6300_GPIO_LVL_LOW 0x10 -#define ESB6300_GPIO_LVL_HIGH 0x20 -#define ESB6300_GPIO_LVL_BLINK 0x30 +#define ESB6300_GPIO_LVL_LOW 0x10 +#define ESB6300_GPIO_LVL_HIGH 0x20 +#define ESB6300_GPIO_LVL_BLINK 0x30
-#define ESB6300_GPIO_INV_MASK 0xc0 +#define ESB6300_GPIO_INV_MASK 0xc0 #define ESB6300_GPIO_INV_DEFAULT 0x00 -#define ESB6300_GPIO_INV_OFF 0x40 -#define ESB6300_GPIO_INV_ON 0x80 +#define ESB6300_GPIO_INV_OFF 0x40 +#define ESB6300_GPIO_INV_ON 0x80
/* GPIO use select */ unsigned char gpio[64]; diff --git a/src/southbridge/intel/esb6300/ehci.c b/src/southbridge/intel/esb6300/ehci.c index c103c4b..98bf436 100644 --- a/src/southbridge/intel/esb6300/ehci.c +++ b/src/southbridge/intel/esb6300/ehci.c @@ -35,16 +35,16 @@ static struct pci_operations lops_pci = { }; static struct device_operations ehci_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = esb6300_enable, - .ops_pci = &lops_pci, + .init = ehci_init, + .scan_bus = 0, + .enable = esb6300_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, + .ops = &ehci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI, }; diff --git a/src/southbridge/intel/esb6300/ide.c b/src/southbridge/intel/esb6300/ide.c index abe86a8..c5bcd53 100644 --- a/src/southbridge/intel/esb6300/ide.c +++ b/src/southbridge/intel/esb6300/ide.c @@ -11,11 +11,11 @@ static void ide_init(struct device *dev) /* Enable ide devices so the linux ide driver will work */
/* Enable IDE devices */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); - pci_write_config8(dev, 0x48, 0x05); - pci_write_config16(dev, 0x4a, 0x0101); - pci_write_config16(dev, 0x54, 0x5055); + pci_write_config16(dev, 0x40, 0x0a307); + pci_write_config16(dev, 0x42, 0x0a307); + pci_write_config8(dev, 0x48, 0x05); + pci_write_config16(dev, 0x4a, 0x0101); + pci_write_config16(dev, 0x54, 0x5055);
#if 0 uint16_t word; @@ -41,15 +41,15 @@ static struct pci_operations lops_pci = { }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .init = ide_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_IDE, }; diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index 67bcadc..e19d390 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -41,8 +41,8 @@ static void esb6300_pci_dma_cfg(device_t dev) #define LPC_EN 0xe6 static void esb6300_enable_lpc(device_t dev) { - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); + /* lpc i/f enable */ + pci_write_config8(dev, LPC_EN, 0x0d); }
typedef struct southbridge_intel_esb6300_config config_t; @@ -148,7 +148,7 @@ static void set_esb6300_gpio_level( } } #endif - outl(gpio_lvl, res->base + 0x0c); + outl(gpio_lvl, res->base + 0x0c); outl(gpio_blink, res->base + 0x18); outl(gpio_lvl2, res->base + 0x38); } @@ -173,7 +173,7 @@ static void set_esb6300_gpio_inv( gpio_inv |= (val << i); } #endif - outl(gpio_inv, res->base + 0x2c); + outl(gpio_inv, res->base + 0x2c); }
static void esb6300_pirq_init(device_t dev) @@ -281,7 +281,7 @@ static void lpc_init(struct device *dev)
esb6300_enable_lpc(dev);
- get_option(&pwr_on, "power_on_after_fail"); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { @@ -359,16 +359,16 @@ static struct pci_operations lops_pci = {
static struct device_operations lpc_ops = { .read_resources = esb6300_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = esb6300_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = esb6300_enable, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = esb6300_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_LPC, }; diff --git a/src/southbridge/intel/esb6300/pci.c b/src/southbridge/intel/esb6300/pci.c index 64aeb0d..a4a5111 100644 --- a/src/southbridge/intel/esb6300/pci.c +++ b/src/southbridge/intel/esb6300/pci.c @@ -22,15 +22,15 @@ static void pci_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_PCI, }; diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c index b9bfdf1..44fc9b9 100644 --- a/src/southbridge/intel/esb6300/pic.c +++ b/src/southbridge/intel/esb6300/pic.c @@ -52,16 +52,16 @@ static struct pci_operations lops_pci = {
static struct device_operations pci_ops = { .read_resources = pic_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = pic_init, - .scan_bus = 0, - .enable = esb6300_enable, - .ops_pci = &lops_pci, + .init = pic_init, + .scan_bus = 0, + .enable = esb6300_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_APIC1, }; diff --git a/src/southbridge/intel/esb6300/sata.c b/src/southbridge/intel/esb6300/sata.c index 6dce2d2..1826b28 100644 --- a/src/southbridge/intel/esb6300/sata.c +++ b/src/southbridge/intel/esb6300/sata.c @@ -12,32 +12,32 @@ static void sata_init(struct device *dev) /* Enable SATA devices */
printk(BIOS_DEBUG, "SATA init\n"); - /* SATA configuration */ - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x09, 0x8f); + /* SATA configuration */ + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x09, 0x8f);
- /* Set timmings */ - pci_write_config16(dev, 0x40, 0x0a307); - pci_write_config16(dev, 0x42, 0x0a307); + /* Set timmings */ + pci_write_config16(dev, 0x40, 0x0a307); + pci_write_config16(dev, 0x42, 0x0a307);
- /* Sync DMA */ - pci_write_config16(dev, 0x48, 0x000f); - pci_write_config16(dev, 0x4a, 0x1111); + /* Sync DMA */ + pci_write_config16(dev, 0x48, 0x000f); + pci_write_config16(dev, 0x4a, 0x1111);
- /* 66 mhz */ - pci_write_config16(dev, 0x54, 0xf00f); + /* 66 mhz */ + pci_write_config16(dev, 0x54, 0xf00f);
- /* Combine ide - sata configuration */ - pci_write_config8(dev, 0x90, 0x0); + /* Combine ide - sata configuration */ + pci_write_config8(dev, 0x90, 0x0);
- /* port 0 & 1 enable */ - pci_write_config8(dev, 0x92, 0x33); + /* port 0 & 1 enable */ + pci_write_config8(dev, 0x92, 0x33);
- /* initialize SATA */ - pci_write_config16(dev, 0xa0, 0x0018); - pci_write_config32(dev, 0xa4, 0x00000264); - pci_write_config16(dev, 0xa0, 0x0040); - pci_write_config32(dev, 0xa4, 0x00220043); + /* initialize SATA */ + pci_write_config16(dev, 0xa0, 0x0018); + pci_write_config32(dev, 0xa4, 0x00000264); + pci_write_config16(dev, 0xa0, 0x0040); + pci_write_config32(dev, 0xa4, 0x00220043);
printk(BIOS_DEBUG, "SATA Enabled\n"); } @@ -54,22 +54,22 @@ static struct pci_operations lops_pci = { }; static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA, };
static const struct pci_driver sata_driver_nr __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_6300ESB_SATA_RAID, };
diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c index c7ed04f..32b263d 100644 --- a/src/southbridge/intel/esb6300/smbus.c +++ b/src/southbridge/intel/esb6300/smbus.c @@ -32,17 +32,17 @@ static struct pci_operations lops_pci = {
static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = esb6300_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .init = 0, + .scan_bus = scan_static_bus, + .enable = esb6300_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, + .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_SMB, }; diff --git a/src/southbridge/intel/esb6300/smbus.h b/src/southbridge/intel/esb6300/smbus.h index 4f4ec5c..51cbab0 100644 --- a/src/southbridge/intel/esb6300/smbus.h +++ b/src/southbridge/intel/esb6300/smbus.h @@ -34,10 +34,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - udelay(100); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); + udelay(100); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); return loops?0:-1; } @@ -47,10 +47,10 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - udelay(100); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); + udelay(100); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); } while((byte&(1<<7)) == 0); return loops?0:-1; } diff --git a/src/southbridge/intel/esb6300/uhci.c b/src/southbridge/intel/esb6300/uhci.c index a8bcd88..497d4cf 100644 --- a/src/southbridge/intel/esb6300/uhci.c +++ b/src/southbridge/intel/esb6300/uhci.c @@ -28,29 +28,29 @@ static struct pci_operations lops_pci = {
static struct device_operations uhci_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = esb6300_enable, - .ops_pci = &lops_pci, + .init = uhci_init, + .scan_bus = 0, + .enable = esb6300_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver usb1_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_USB1, };
static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_USB2, };
/* Note: May or may not need different init than UHCI. */ static const struct pci_driver ehci_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_6300ESB_EHCI, }; diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index e0acc63..eef30ef 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -6,8 +6,8 @@ config SOUTHBRIDGE_INTEL_I3100 if SOUTHBRIDGE_INTEL_I3100
config HPET_MIN_TICKS - hex - default 0x90 + hex + default 0x90
endif
diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h index b0f3f32..3c7c7a6 100644 --- a/src/southbridge/intel/i3100/chip.h +++ b/src/southbridge/intel/i3100/chip.h @@ -20,26 +20,26 @@
struct southbridge_intel_i3100_config { -#define I3100_GPIO_USE_MASK 0x03 -#define I3100_GPIO_USE_DEFAULT 0x00 +#define I3100_GPIO_USE_MASK 0x03 +#define I3100_GPIO_USE_DEFAULT 0x00 #define I3100_GPIO_USE_AS_NATIVE 0x01 -#define I3100_GPIO_USE_AS_GPIO 0x02 +#define I3100_GPIO_USE_AS_GPIO 0x02
-#define I3100_GPIO_SEL_MASK 0x0c -#define I3100_GPIO_SEL_DEFAULT 0x00 -#define I3100_GPIO_SEL_OUTPUT 0x04 -#define I3100_GPIO_SEL_INPUT 0x08 +#define I3100_GPIO_SEL_MASK 0x0c +#define I3100_GPIO_SEL_DEFAULT 0x00 +#define I3100_GPIO_SEL_OUTPUT 0x04 +#define I3100_GPIO_SEL_INPUT 0x08
-#define I3100_GPIO_LVL_MASK 0x30 -#define I3100_GPIO_LVL_DEFAULT 0x00 -#define I3100_GPIO_LVL_LOW 0x10 -#define I3100_GPIO_LVL_HIGH 0x20 -#define I3100_GPIO_LVL_BLINK 0x30 +#define I3100_GPIO_LVL_MASK 0x30 +#define I3100_GPIO_LVL_DEFAULT 0x00 +#define I3100_GPIO_LVL_LOW 0x10 +#define I3100_GPIO_LVL_HIGH 0x20 +#define I3100_GPIO_LVL_BLINK 0x30
-#define I3100_GPIO_INV_MASK 0xc0 -#define I3100_GPIO_INV_DEFAULT 0x00 -#define I3100_GPIO_INV_OFF 0x40 -#define I3100_GPIO_INV_ON 0x80 +#define I3100_GPIO_INV_MASK 0xc0 +#define I3100_GPIO_INV_DEFAULT 0x00 +#define I3100_GPIO_INV_OFF 0x40 +#define I3100_GPIO_INV_ON 0x80
/* GPIO use select */ u8 gpio[64]; diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index f06947c..82b552a 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -31,7 +31,7 @@ static void enable_smbus(void) pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); + outb(4, SMBUS_IO_BASE + SMBSLVCMD);
/* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); diff --git a/src/southbridge/intel/i3100/ehci.c b/src/southbridge/intel/i3100/ehci.c index 268ca54..5a885d4 100644 --- a/src/southbridge/intel/i3100/ehci.c +++ b/src/southbridge/intel/i3100/ehci.c @@ -47,22 +47,22 @@ static struct pci_operations lops_pci = { }; static struct device_operations ehci_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, + .init = ehci_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, + .ops = &ehci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_EHCI, };
static const struct pci_driver ehci_driver_ep80579 __pci_driver = { - .ops = &ehci_ops, + .ops = &ehci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_EHCI, }; diff --git a/src/southbridge/intel/i3100/i3100.h b/src/southbridge/intel/i3100/i3100.h index 59c2852..d866cb4 100644 --- a/src/southbridge/intel/i3100/i3100.h +++ b/src/southbridge/intel/i3100/i3100.h @@ -22,7 +22,7 @@ #include "chip.h"
#define SATA_CMD 0x04 -#define SATA_PI 0x09 +#define SATA_PI 0x09 #define SATA_PTIM 0x40 #define SATA_STIM 0x42 #define SATA_D1TIM 0x44 @@ -35,7 +35,7 @@ #define SATA_ACR1 0xAC #define SATA_ATC 0xC0 #define SATA_ATS 0xC4 -#define SATA_SP 0xD0 +#define SATA_SP 0xD0
#define SATA_MODE_IDE 0x00 #define SATA_MODE_AHCI 0x01 diff --git a/src/southbridge/intel/i3100/ioapic.c b/src/southbridge/intel/i3100/ioapic.c index ac8e581..74a82c2 100644 --- a/src/southbridge/intel/i3100/ioapic.c +++ b/src/southbridge/intel/i3100/ioapic.c @@ -45,16 +45,16 @@ static void read_resources(struct device *dev)
static struct device_operations pci_ops = { .read_resources = read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0,
};
static const struct pci_driver pci_driver0 __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x3500, }; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index abd0653..1633f2f 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -209,19 +209,19 @@ static void i3100_pirq_init(device_t dev) if(config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0;
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue;
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - switch (int_pin) { - case 1: /* INTA# */ + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + switch (int_pin) { + case 1: /* INTA# */ int_line = config->pirq_a_d & 0xff; break;
- case 2: /* INTB# */ + case 2: /* INTB# */ int_line = (config->pirq_a_d >> 8) & 0xff; break;
@@ -229,17 +229,17 @@ static void i3100_pirq_init(device_t dev) int_line = (config->pirq_a_d >> 16) & 0xff; break;
- case 4: /* INTD# */ + case 4: /* INTD# */ int_line = (config->pirq_a_d >> 24) & 0xff; break; - } + }
- if (!int_line) - continue; + if (!int_line) + continue;
printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + }
} @@ -450,22 +450,22 @@ static struct pci_operations lops_pci = {
static struct device_operations lpc_ops = { .read_resources = i3100_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = i3100_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i3100_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_LPC, };
static const struct pci_driver lpc_driver_ep80579 __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_LPC, }; diff --git a/src/southbridge/intel/i3100/pci.c b/src/southbridge/intel/i3100/pci.c index fa0b5bd..3716122 100644 --- a/src/southbridge/intel/i3100/pci.c +++ b/src/southbridge/intel/i3100/pci.c @@ -31,15 +31,15 @@ static void pci_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCI, }; diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c index ff0bce5..6e05337 100644 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ b/src/southbridge/intel/i3100/pciexp_portb.c @@ -61,34 +61,34 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pcie_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .init = pcie_init, + .scan_bus = pcie_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pci_driver_0 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0, };
static const struct pci_driver pci_driver_1 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1, };
static const struct pci_driver pci_driver_2 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2, };
static const struct pci_driver pci_driver_3 __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3, }; diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 0740440..0d87cfe 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -123,34 +123,34 @@ static struct pci_operations lops_pci = {
static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, + .init = sata_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_IDE, };
static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_AHCI, };
static const struct pci_driver ide_driver_ep80579 __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_IDE, };
static const struct pci_driver sata_driver_ep80579 __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_AHCI, }; diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c index 849a25c..dde386d 100644 --- a/src/southbridge/intel/i3100/smbus.c +++ b/src/southbridge/intel/i3100/smbus.c @@ -71,23 +71,23 @@ static struct pci_operations lops_pci = {
static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i3100_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i3100_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, + .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_SMB, };
static const struct pci_driver smbus_driver_ep80579 __pci_driver = { - .ops = &smbus_ops, + .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_SMB, }; diff --git a/src/southbridge/intel/i3100/uhci.c b/src/southbridge/intel/i3100/uhci.c index ae68e39..5462d41 100644 --- a/src/southbridge/intel/i3100/uhci.c +++ b/src/southbridge/intel/i3100/uhci.c @@ -41,28 +41,28 @@ static struct pci_operations lops_pci = {
static struct device_operations uhci_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i3100_enable, - .ops_pci = &lops_pci, + .init = uhci_init, + .scan_bus = 0, + .enable = i3100_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_UHCI, };
static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_3100_UHCI2, };
static const struct pci_driver uhci_driver_ep80579 __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_EP80579_UHCI, }; diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 35d787d..502880c 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -59,7 +59,7 @@ Device (LPCB) Method (_CRS, 0, NotSerialized) { Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} + IRQNoFlags () {12} }) Return (TMP) } diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index b350bde..25e91a4 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -36,7 +36,7 @@ static void i82371eb_enable_rom(void) * bus/device/function numbers) works on all boards. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA), 0); + PCI_DEVICE_ID_INTEL_82371AB_ISA), 0);
/* Enable access to the whole ROM, disable ROM write access. */ reg16 = pci_read_config16(dev, XBCS); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index e4c8208..a2005bc 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -91,61 +91,61 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->century = 0x0; /* not supported */ /* * bit meaning - * 0 1: We have user-visible legacy devices - * 1 1: 8042 - * 2 0: VGA is ok to probe - * 3 1: MSI are not supported + * 0 1: We have user-visible legacy devices + * 1 1: 8042 + * 2 0: VGA is ok to probe + * 3 1: MSI are not supported */ fadt->iapc_boot_arch = 0xb; /* * bit meaning - * 0 WBINVD - * Processors in new ACPI-compatible systems are required to - * support this function and indicate this to OSPM by setting - * this field. - * 1 WBINVD_FLUSH - * If set, indicates that the hardware flushes all caches on the - * WBINVD instruction and maintains memory coherency, but does - * not guarantee the caches are invalidated. - * 2 PROC_C1 - * C1 power state (x86 hlt instruction) is supported on all cpus - * 3 P_LVL2_UP - * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor - * 4 PWR_BUTTON - * 0: pwr button is fixed feature - * 1: pwr button has control method device if present - * 5 SLP_BUTTON - * 0: sleep button is fixed feature - * 1: sleep button has control method device if present - * 6 FIX_RTC - * 0: RTC wake status supported in fixed register spce - * 7 RTC_S4 - * 1: RTC can wake from S4 - * 8 TMR_VAL_EXT - * 1: pmtimer is 32bit, 0: pmtimer is 24bit - * 9 DCK_CAP - * 1: system supports docking station - * 10 RESET_REG_SUPPORT - * 1: fadt describes reset register for system reset - * 11 SEALED_CASE - * 1: No expansion possible, sealed case - * 12 HEADLESS - * 1: Video output, keyboard and mouse are not connected - * 13 CPU_SW_SLP - * 1: Special processor instruction needs to be executed - * after writing SLP_TYP - * 14 PCI_EXP_WAK - * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set - * on platforms with pci express support - * 15 USE_PLATFORM_CLOCK - * 1: OS should prefer platform clock over processor internal - * clock. - * 16 S4_RTC_STS_VALID - * 17 REMOTE_POWER_ON_CAPABLE - * 1: platform correctly supports OSPM leaving GPE wake events - * armed prior to an S5 transition. - * 18 FORCE_APIC_CLUSTER_MODEL - * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE + * 0 WBINVD + * Processors in new ACPI-compatible systems are required to + * support this function and indicate this to OSPM by setting + * this field. + * 1 WBINVD_FLUSH + * If set, indicates that the hardware flushes all caches on the + * WBINVD instruction and maintains memory coherency, but does + * not guarantee the caches are invalidated. + * 2 PROC_C1 + * C1 power state (x86 hlt instruction) is supported on all cpus + * 3 P_LVL2_UP + * 0: C2 only on uniprocessor, 1: C2 on uni- and multiprocessor + * 4 PWR_BUTTON + * 0: pwr button is fixed feature + * 1: pwr button has control method device if present + * 5 SLP_BUTTON + * 0: sleep button is fixed feature + * 1: sleep button has control method device if present + * 6 FIX_RTC + * 0: RTC wake status supported in fixed register spce + * 7 RTC_S4 + * 1: RTC can wake from S4 + * 8 TMR_VAL_EXT + * 1: pmtimer is 32bit, 0: pmtimer is 24bit + * 9 DCK_CAP + * 1: system supports docking station + * 10 RESET_REG_SUPPORT + * 1: fadt describes reset register for system reset + * 11 SEALED_CASE + * 1: No expansion possible, sealed case + * 12 HEADLESS + * 1: Video output, keyboard and mouse are not connected + * 13 CPU_SW_SLP + * 1: Special processor instruction needs to be executed + * after writing SLP_TYP + * 14 PCI_EXP_WAK + * 1: PM1 regs support PCIEXP_WAKE_(STS|EN), must be set + * on platforms with pci express support + * 15 USE_PLATFORM_CLOCK + * 1: OS should prefer platform clock over processor internal + * clock. + * 16 S4_RTC_STS_VALID + * 17 REMOTE_POWER_ON_CAPABLE + * 1: platform correctly supports OSPM leaving GPE wake events + * armed prior to an S5 transition. + * 18 FORCE_APIC_CLUSTER_MODEL + * 19 FORCE_APIC_PHYSICAL_DESTINATION_MODE */ fadt->flags = 0xa5;
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c index 3e48614..36372fc 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.c +++ b/src/southbridge/intel/i82371eb/i82371eb.c @@ -28,14 +28,14 @@ * - Order Number: 290550-002 * * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator - * Specification Update + * Specification Update * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf * - Date: March 1998 * - Order Number: 297658-004 * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) - * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) + * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Date: April 1997 diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index e6062c6..1529df9 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -57,59 +57,59 @@ void enable_pm(void);
/* SMBus */ #define SMBBA 0x90 /* SMBus base address */ -#define SMBUS_IO_BASE 0x0f00 +#define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */
/* Power management (ACPI) */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ -#define PWRBTN_EN (1<<8) -#define GBL_EN (1<<5) +#define PWRBTN_EN (1<<8) +#define GBL_EN (1<<5) #define PMCNTRL 0x04 /* Power Management Control */ -#define SUS_EN (1<<13) /* S0-S5 trigger */ -#define SUS_TYP_MSK (7<<10) -#define SUS_TYP_S0 (5<<10) -#define SUS_TYP_S1 (4<<10) -#define SUS_TYP_S2 (3<<10) +#define SUS_EN (1<<13) /* S0-S5 trigger */ +#define SUS_TYP_MSK (7<<10) +#define SUS_TYP_S0 (5<<10) +#define SUS_TYP_S1 (4<<10) +#define SUS_TYP_S2 (3<<10) //#define SUS_TYP_S2>---(2<<10) -#define SUS_TYP_S3 (1<<10) -#define SUS_TYP_S5 (0<<10) -#define SCI_EN (1<<0) +#define SUS_TYP_S3 (1<<10) +#define SUS_TYP_S5 (0<<10) +#define SCI_EN (1<<0) #define PMTMR 0x08 /* Power Management Timer */ #define GPSTS 0x0c /* General Purpose Status */ #define GPEN 0x0e /* General Purpose Enable */ -#define THRM_EN (1<<0) +#define THRM_EN (1<<0) #define PCNTRL 0x10 /* Processor control */ #define GLBSTS 0x18 /* Global Status */ -#define IRQ_RSM_STS (1<<11) -#define EXTSMI_STS (1<<10) -#define GSTBY_STS (1<<8) -#define GP_STS (1<<7) -#define BM1_STS (1<<6) -#define APM_STS (1<<5) -#define DEV_STS (1<<4) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define IRQ_RSM_STS (1<<11) +#define EXTSMI_STS (1<<10) +#define GSTBY_STS (1<<8) +#define GP_STS (1<<7) +#define BM1_STS (1<<6) +#define APM_STS (1<<5) +#define DEV_STS (1<<4) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ #define DEVSTS 0x1c /* Device Status */ #define GLBEN 0x20 /* Global Enable */ -#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ -#define GSTBY_EN (1<<8) -#define BM_TRP_EN (1<<1) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ +#define GSTBY_EN (1<<8) +#define BM_TRP_EN (1<<1) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ #define GLBCTL 0x28 /* Global Control */ -#define EOS (1<<16) /* End of SMI */ -#define SMI_EN (1<<0) /* SMI enable */ +#define EOS (1<<16) /* End of SMI */ +#define SMI_EN (1<<0) /* SMI enable */ #define DEVCTL 0x2c /* Device Control */ -#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ +#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ #define GPO0 0x34 #define GPO1 0x35 #define GPO2 0x36 #define GPO3 0x37
#define PMBA 0x40 /* Power management base address */ -#define DEFAULT_PMBASE 0xe400 -#define PM_IO_BASE DEFAULT_PMBASE +#define DEFAULT_PMBASE 0xe400 +#define PM_IO_BASE DEFAULT_PMBASE #define PMREGMISC 0x80 /* Miscellaneous power management */
/* Bit definitions */ diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c index 41c3c32..811d038 100644 --- a/src/southbridge/intel/i82371eb/ide.c +++ b/src/southbridge/intel/i82371eb/ide.c @@ -65,10 +65,10 @@ static void ide_init_enable(struct device *dev) if (conf->ide0_enable || conf->ide1_enable) { reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 = ONOFF(conf->ide_legacy_enable, reg16, - (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); + (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); pci_write_config16(dev, PCI_COMMAND, reg16); printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n", - conf->ide_legacy_enable ? "on" : "off"); + conf->ide_legacy_enable ? "on" : "off"); } }
@@ -97,11 +97,11 @@ static void ide_init_udma33(struct device *dev) pci_write_config8(dev, UDMACTL, reg8);
printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Primary IDE interface", 0, - conf->ide0_drive0_udma33_enable ? "on" : "off"); + "Primary IDE interface", 0, + conf->ide0_drive0_udma33_enable ? "on" : "off"); printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Primary IDE interface", 1, - conf->ide0_drive1_udma33_enable ? "on" : "off"); + "Primary IDE interface", 1, + conf->ide0_drive1_udma33_enable ? "on" : "off"); }
/* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ @@ -112,11 +112,11 @@ static void ide_init_udma33(struct device *dev) pci_write_config8(dev, UDMACTL, reg8);
printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Secondary IDE interface", 0, - conf->ide1_drive0_udma33_enable ? "on" : "off"); + "Secondary IDE interface", 0, + conf->ide1_drive0_udma33_enable ? "on" : "off"); printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", - "Secondary IDE interface", 1, - conf->ide1_drive1_udma33_enable ? "on" : "off"); + "Secondary IDE interface", 1, + conf->ide1_drive1_udma33_enable ? "on" : "off"); } }
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 5605106..78fcc62 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -39,7 +39,7 @@ static void enable_intel_82093aa_ioapic(void) device_t dev;
dev = dev_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); + PCI_DEVICE_ID_INTEL_82371AB_ISA, 0);
/* Enable IOAPIC. */ reg16 = pci_read_config16(dev, XBCS); diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index d236cfa..64ccb68 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -77,19 +77,19 @@ static void pwrmgt_enable(struct device *dev) * power-on default is 0x7fffbfffh */ if (gpo) { /* only 8bit access allowed */ - outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); } else { printk(BIOS_SPEW, - "%s: gpo default missing in devicetree.cb!\n", __func__); + "%s: gpo default missing in devicetree.cb!\n", __func__); }
/* Clear status events. */ - outw(0xffff, DEFAULT_PMBASE + PMSTS); - outw(0xffff, DEFAULT_PMBASE + GPSTS); - outw(0xffff, DEFAULT_PMBASE + GLBSTS); + outw(0xffff, DEFAULT_PMBASE + PMSTS); + outw(0xffff, DEFAULT_PMBASE + GPSTS); + outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
#if CONFIG_HAVE_ACPI_RESUME @@ -113,14 +113,14 @@ static void pwrmgt_read_resources(struct device *dev) res->size = 0x0040; res->limit = 0xffff; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; + IORESOURCE_RESERVE;
res = new_resource(dev, 2); res->base = SMBUS_IO_BASE; res->size = 0x0010; res->limit = 0xffff; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | - IORESOURCE_RESERVE; + IORESOURCE_RESERVE; }
diff --git a/src/southbridge/intel/i82371eb/wakeup.c b/src/southbridge/intel/i82371eb/wakeup.c index dd4a28f..14b263a 100644 --- a/src/southbridge/intel/i82371eb/wakeup.c +++ b/src/southbridge/intel/i82371eb/wakeup.c @@ -32,11 +32,11 @@ int acpi_get_sleep_type(void); * 1: suspend to ram S3 * 2: powered on suspend, context lost S2 * Note: 'context lost' means the CPU restarts at the reset - * vector + * vector * 3: powered on suspend, CPU context lost S1 * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to acpi S1 + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to acpi S1 * 4: powered on suspend, context maintained S1 * 5: working (clock control) S0 * 6: reserved diff --git a/src/southbridge/intel/i82801ax/ide.c b/src/southbridge/intel/i82801ax/ide.c index 989ccd0..644bdc6 100644 --- a/src/southbridge/intel/i82801ax/ide.c +++ b/src/southbridge/intel/i82801ax/ide.c @@ -39,7 +39,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide0_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", - conf->ide0_enable ? "on" : "off"); + conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_PRI, reg16);
reg16 = pci_read_config16(dev, IDE_TIM_SEC); @@ -47,7 +47,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide1_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", - conf->ide0_enable ? "on" : "off"); + conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_SEC, reg16); }
diff --git a/src/southbridge/intel/i82801bx/i82801bx.c b/src/southbridge/intel/i82801bx/i82801bx.c index 68f4b14..366b629 100644 --- a/src/southbridge/intel/i82801bx/i82801bx.c +++ b/src/southbridge/intel/i82801bx/i82801bx.c @@ -38,7 +38,7 @@ void i82801bx_enable(device_t dev) index = PCI_FUNC(dev->path.pci.devfn);
reg16 = pci_read_config16(lpc_dev, FUNC_DIS); - reg16 &= ~(1 << index); /* Enable device. */ + reg16 &= ~(1 << index); /* Enable device. */ if (!dev->enabled) reg16 |= (1 << index); /* Disable device, if desired. */ pci_write_config16(lpc_dev, FUNC_DIS, reg16); diff --git a/src/southbridge/intel/i82801bx/ide.c b/src/southbridge/intel/i82801bx/ide.c index e24e693..c634a16 100644 --- a/src/southbridge/intel/i82801bx/ide.c +++ b/src/southbridge/intel/i82801bx/ide.c @@ -39,7 +39,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide0_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", - conf->ide0_enable ? "on" : "off"); + conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_PRI, reg16);
reg16 = pci_read_config16(dev, IDE_TIM_SEC); @@ -47,7 +47,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide1_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", - conf->ide0_enable ? "on" : "off"); + conf->ide0_enable ? "on" : "off"); pci_write_config16(dev, IDE_TIM_SEC, reg16); }
diff --git a/src/southbridge/intel/i82801cx/ac97.c b/src/southbridge/intel/i82801cx/ac97.c index 5de44fc..b9adac5 100644 --- a/src/southbridge/intel/i82801cx/ac97.c +++ b/src/southbridge/intel/i82801cx/ac97.c @@ -11,15 +11,15 @@
static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801cx_enable, - .init = 0, - .scan_bus = 0, + .enable = i82801cx_enable, + .init = 0, + .scan_bus = 0, };
static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, + .ops = &ac97audio_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO, }; @@ -27,15 +27,15 @@ static const struct pci_driver ac97audio_driver __pci_driver = {
static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801cx_enable, - .init = 0, - .scan_bus = 0, + .enable = i82801cx_enable, + .init = 0, + .scan_bus = 0, };
static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, + .ops = &ac97modem_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM, }; diff --git a/src/southbridge/intel/i82801cx/i82801cx.h b/src/southbridge/intel/i82801cx/i82801cx.h index f196fa3..887acff 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.h +++ b/src/southbridge/intel/i82801cx/i82801cx.h @@ -7,23 +7,23 @@ void i82801cx_enable(device_t dev); #endif
-#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 - -#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define PIRQA_ROUT 0x60 -#define PIRQE_ROUT 0x68 -#define COM_DEC 0xE0 -#define LPC_EN 0xE6 -#define FUNC_DIS 0xF2 +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define PIRQA_ROUT 0x60 +#define PIRQE_ROUT 0x68 +#define COM_DEC 0xE0 +#define LPC_EN 0xE6 +#define FUNC_DIS 0xF2
// GEN_PMCON_3 bits #define RTC_BATTERY_DEAD (1<<2) diff --git a/src/southbridge/intel/i82801cx/ide.c b/src/southbridge/intel/i82801cx/ide.c index 74c442c..8da5cc0 100644 --- a/src/southbridge/intel/i82801cx/ide.c +++ b/src/southbridge/intel/i82801cx/ide.c @@ -26,23 +26,23 @@ static void ide_init(struct device *dev) ideTimingConfig &= ~IDE_DECODE_ENABLE; if (enable_secondary) { /* Enable secondary ide interface */ - ideTimingConfig |= IDE_DECODE_ENABLE; - printk(BIOS_DEBUG, "IDE1 "); + ideTimingConfig |= IDE_DECODE_ENABLE; + printk(BIOS_DEBUG, "IDE1 "); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); }
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .enable = i82801cx_enable, + .init = ide_init, + .scan_bus = 0, + .enable = i82801cx_enable, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_IDE, }; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f9c0ece..0c73e21 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -62,8 +62,8 @@ static void i82801cx_enable_serial_irqs( struct device *dev) * * @param dev TODO * @param mask Identifies whether each channel should be used for PCI DMA - * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. - * Channel 4 is not used (reserved). + * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. + * Channel 4 is not used (reserved). */ static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { @@ -74,8 +74,8 @@ static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) dmaConfig &= 0x300; // Preserve reserved bits for(channelIndex = 0; channelIndex < 8; channelIndex++) { if (channelIndex == 4) - continue; // Register doesn't support channel 4 - dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2); + continue; // Register doesn't support channel 4 + dmaConfig |= ((mask & (1 << channelIndex))? 3:1) << (channelIndex*2); } pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); } @@ -90,9 +90,9 @@ static void i82801cx_rtc_init(struct device *dev) rtc_failed = pmcon3 & RTC_BATTERY_DEAD; if (rtc_failed) { // Clear the RTC_BATTERY_DEAD bit, but preserve - // the RTC_POWER_FAILED, G3 state, and reserved bits + // the RTC_POWER_FAILED, G3 state, and reserved bits // NOTE: RTC_BATTERY_DEAD and RTC_POWER_FAILED are "write-1-clear" bits - pmcon3 &= ~RTC_POWER_FAILED; + pmcon3 &= ~RTC_POWER_FAILED; }
get_option(&pwr_on, "power_on_after_fail"); @@ -162,11 +162,11 @@ static void lpc_init(struct device *dev) i82801cx_enable_serial_irqs(dev);
/* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ byte = pci_read_config8(dev, GEN_PMCON_3); if (pwr_on) byte &= ~1; // Return to S0 (boot) after power is re-applied @@ -184,8 +184,8 @@ static void lpc_init(struct device *dev) nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - outb(byte, 0x70); + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); }
/* Initialize the real time clock */ @@ -227,15 +227,15 @@ static void i82801cx_lpc_read_resources(device_t dev)
static struct device_operations lpc_ops = { .read_resources = i82801cx_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = 0, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = 0, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_LPC, }; diff --git a/src/southbridge/intel/i82801cx/nic.c b/src/southbridge/intel/i82801cx/nic.c index 00ce038..da48acb 100644 --- a/src/southbridge/intel/i82801cx/nic.c +++ b/src/southbridge/intel/i82801cx/nic.c @@ -8,14 +8,14 @@
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, + .init = 0, + .scan_bus = 0, };
static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_LAN, }; diff --git a/src/southbridge/intel/i82801cx/pci.c b/src/southbridge/intel/i82801cx/pci.c index 842b214..3552262 100644 --- a/src/southbridge/intel/i82801cx/pci.c +++ b/src/southbridge/intel/i82801cx/pci.c @@ -16,14 +16,14 @@ static void pci_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, + .init = pci_init, + .scan_bus = pci_scan_bridge, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_PCI, }; diff --git a/src/southbridge/intel/i82801cx/reset.c b/src/southbridge/intel/i82801cx/reset.c index 6883ff0..750b4a6 100644 --- a/src/southbridge/intel/i82801cx/reset.c +++ b/src/southbridge/intel/i82801cx/reset.c @@ -3,7 +3,7 @@
void hard_reset(void) { - /* Try rebooting through port 0xcf9 */ - // Hard reset without power cycle - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9 */ + // Hard reset without power cycle + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } diff --git a/src/southbridge/intel/i82801cx/smbus.c b/src/southbridge/intel/i82801cx/smbus.c index 324f82f..dc21de1 100644 --- a/src/southbridge/intel/i82801cx/smbus.c +++ b/src/southbridge/intel/i82801cx/smbus.c @@ -10,7 +10,7 @@ void smbus_enable(void) { /* iobase addr */ pcibios_write_config_dword(PM_BUS, PM_DEVFN, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* smbus enable */ pcibios_write_config_byte(PM_BUS, PM_DEVFN, HOSTC, HST_EN); /* iospace enable */ diff --git a/src/southbridge/intel/i82801cx/usb.c b/src/southbridge/intel/i82801cx/usb.c index 28cb357..3cae27f 100644 --- a/src/southbridge/intel/i82801cx/usb.c +++ b/src/southbridge/intel/i82801cx/usb.c @@ -24,26 +24,26 @@ static void usb_init(struct device *dev)
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .scan_bus = 0, - .enable = i82801cx_enable, + .init = usb_init, + .scan_bus = 0, + .enable = i82801cx_enable, };
static const struct pci_driver usb_driver_1 __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801CA_USB1, }; static const struct pci_driver usb_driver_2 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB2, }; static const struct pci_driver usb_driver_3 __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82801CA_USB3, };
diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index 004ab97..02da9ef 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -27,28 +27,28 @@ #include "i82801dx.h"
#define NAMBAR 0x10 -#define MASTER_VOL 0x02 -#define PAGING 0x24 -#define EXT_AUDIO 0x28 -#define FUNC_SEL 0x66 -#define INFO_IO 0x68 -#define CONNECTOR 0x6a -#define VENDOR_ID1 0x7c -#define VENDOR_ID2 0x7e -#define SEC_VENDOR_ID1 0xfc -#define SEC_VENDOR_ID2 0xfe +#define MASTER_VOL 0x02 +#define PAGING 0x24 +#define EXT_AUDIO 0x28 +#define FUNC_SEL 0x66 +#define INFO_IO 0x68 +#define CONNECTOR 0x6a +#define VENDOR_ID1 0x7c +#define VENDOR_ID2 0x7e +#define SEC_VENDOR_ID1 0xfc +#define SEC_VENDOR_ID2 0xfe
#define NABMBAR 0x14 -#define GLOB_CNT 0x2c -#define GLOB_STA 0x30 -#define CAS 0x34 +#define GLOB_CNT 0x2c +#define GLOB_STA 0x30 +#define CAS 0x34
#define MMBAR 0x10 -#define EXT_MODEM_ID1 0x3c -#define EXT_MODEM_ID2 0xbc +#define EXT_MODEM_ID1 0x3c +#define EXT_MODEM_ID2 0xbc
#define MBAR 0x14 -#define SEC_CODEC 0x40 +#define SEC_CODEC 0x40
/* FIXME. This table is probably mainboard specific */ @@ -253,20 +253,20 @@ static void ac97_modem_init(struct device *dev)
static struct device_operations ac97_audio_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dx_enable, - .init = ac97_audio_init, - .scan_bus = 0, + .enable = i82801dx_enable, + .init = ac97_audio_init, + .scan_bus = 0, };
static struct device_operations ac97_modem_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = i82801dx_enable, - .init = ac97_modem_init, - .scan_bus = 0, + .enable = i82801dx_enable, + .init = ac97_modem_init, + .scan_bus = 0, };
/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */ diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6f4d4f8..967ee84 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -74,7 +74,7 @@ static int smbus_wait_until_ready(void) } if (loops == (SMBUS_TIMEOUT / 2)) { outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), - SMBUS_IO_BASE + SMBHSTSTAT); + SMBUS_IO_BASE + SMBHSTSTAT); } } while (--loops); return loops ? 0 : -2; @@ -157,7 +157,7 @@ int smbus_read_byte(unsigned device, unsigned address)
#if 0 static void smbus_write_byte(unsigned device, unsigned address, - unsigned char val) + unsigned char val) { if (smbus_wait_until_ready() < 0) { return; diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 05f7487..73324ae 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -30,7 +30,7 @@ void i82801dx_enable(device_t dev) uint8_t bHasDisableBit = 0; uint16_t cur_disable_mask, new_disable_mask;
-// all 82801dbm devices are in bus 0 +// all 82801dbm devices are in bus 0 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc device_t lpc_dev = dev_find_slot(0, devfn); // 0 if (!lpc_dev) @@ -38,8 +38,8 @@ void i82801dx_enable(device_t dev)
// Calculate disable bit position for specified device:function // NOTE: For ICH-4, only the following devices can be disabled: - // D31: F0, F1, F3, F5, F6, - // D29: F0, F1, F2, F7 + // D31: F0, F1, F3, F5, F6, + // D29: F0, F1, F2, F7
if (PCI_SLOT(dev->path.pci.devfn) == 31) { index = PCI_FUNC(dev->path.pci.devfn); diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index c7d7e77..2b3638c 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -55,10 +55,10 @@ int smbus_read_byte(unsigned device, unsigned address); * 000 = Non-combined. P0 is primary master. P1 is secondary master. * 001 = Non-combined. P0 is secondary master. P1 is primary master. * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; - * Primary IDE channel disabled. + * Primary IDE channel disabled. * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary - * slave; Secondary IDE channel disabled. + * slave; Secondary IDE channel disabled. * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. */ /* PCI Configuration Space (D31:F1) */ @@ -70,23 +70,23 @@ int smbus_read_byte(unsigned device, unsigned address);
-#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 - -#define PCICMD 0x04 -#define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 -#define DEFAULT_PMBASE PMBASE_ADDR -#define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) -#define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define GPIOBASE_ADDR 0x0500 +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4 + +#define PCICMD 0x04 +#define PMBASE 0x40 +#define PMBASE_ADDR 0x0400 +#define DEFAULT_PMBASE PMBASE_ADDR +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define BIOS_CNTL 0x4E +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIOBASE_ADDR 0x0500 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 #define PIRQC_ROUT 0x62 @@ -95,25 +95,25 @@ int smbus_read_byte(unsigned device, unsigned address); #define PIRQF_ROUT 0x69 #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B -#define COM_DEC 0xE0 -#define LPC_EN 0xE6 -#define FUNC_DIS 0xF2 +#define COM_DEC 0xE0 +#define LPC_EN 0xE6 +#define FUNC_DIS 0xF2
/* 1e f0 244e */
-#define CMD 0x04 -#define SBUS_NUM 0x19 -#define SUB_BUS_NUM 0x1A -#define SMLT 0x1B -#define IOBASE 0x1C -#define IOLIM 0x1D -#define MEMBASE 0x20 -#define MEMLIM 0x22 -#define CNF 0x50 -#define MTT 0x70 -#define PCI_MAST_STS 0x82 +#define CMD 0x04 +#define SBUS_NUM 0x19 +#define SUB_BUS_NUM 0x1A +#define SMLT 0x1B +#define IOBASE 0x1C +#define IOLIM 0x1D +#define MEMBASE 0x20 +#define MEMLIM 0x22 +#define CNF 0x50 +#define MTT 0x70 +#define PCI_MAST_STS 0x82
-#define RTC_FAILED (1 <<2) +#define RTC_FAILED (1 <<2)
#define SMBUS_IO_BASE 0x1000 @@ -136,26 +136,26 @@ int smbus_read_byte(unsigned device, unsigned address); #define SMBUS_TIMEOUT (100*1000)
#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -163,38 +163,38 @@ int smbus_read_byte(unsigned device, unsigned address); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#define PME_B0_STS (1 << 13) -#define USB3_STS (1 << 12) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define GST_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define AC97_STS (1 << 5) -#define USB2_STS (1 << 4) -#define USB1_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define THRM_STS (1 << 0) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define GST_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index d2e3e25..ed62166 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -35,11 +35,11 @@ extern unsigned char _binary_smm_size;
/* I945 */ #define SMRAM 0x90 -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9b0c235..1b6a656 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -31,11 +31,11 @@
/* I830M */ #define SMRAM 0x90 -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#include "nvs.h"
@@ -238,37 +238,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } }
diff --git a/src/southbridge/intel/i82801ex/ac97.c b/src/southbridge/intel/i82801ex/ac97.c index 08efe15..a0a3522 100644 --- a/src/southbridge/intel/i82801ex/ac97.c +++ b/src/southbridge/intel/i82801ex/ac97.c @@ -17,21 +17,21 @@ static struct pci_operations lops_pci = { }; static struct device_operations ac97_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, + .init = 0, + .scan_bus = 0, + .enable = i82801ex_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ac97_audio_driver __pci_driver = { - .ops = &ac97_ops, + .ops = &ac97_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_AUDIO, }; static const struct pci_driver ac97_modem_driver __pci_driver = { - .ops = &ac97_ops, + .ops = &ac97_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_AC97_MODEM, }; diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h index 891fa16..728c358 100644 --- a/src/southbridge/intel/i82801ex/chip.h +++ b/src/southbridge/intel/i82801ex/chip.h @@ -4,26 +4,26 @@ struct southbridge_intel_i82801ex_config {
-#define ICH5R_GPIO_USE_MASK 0x03 -#define ICH5R_GPIO_USE_DEFAULT 0x00 +#define ICH5R_GPIO_USE_MASK 0x03 +#define ICH5R_GPIO_USE_DEFAULT 0x00 #define ICH5R_GPIO_USE_AS_NATIVE 0x01 -#define ICH5R_GPIO_USE_AS_GPIO 0x02 - -#define ICH5R_GPIO_SEL_MASK 0x0c -#define ICH5R_GPIO_SEL_DEFAULT 0x00 -#define ICH5R_GPIO_SEL_OUTPUT 0x04 -#define ICH5R_GPIO_SEL_INPUT 0x08 - -#define ICH5R_GPIO_LVL_MASK 0x30 -#define ICH5R_GPIO_LVL_DEFAULT 0x00 -#define ICH5R_GPIO_LVL_LOW 0x10 -#define ICH5R_GPIO_LVL_HIGH 0x20 -#define ICH5R_GPIO_LVL_BLINK 0x30 - -#define ICH5R_GPIO_INV_MASK 0xc0 -#define ICH5R_GPIO_INV_DEFAULT 0x00 -#define ICH5R_GPIO_INV_OFF 0x40 -#define ICH5R_GPIO_INV_ON 0x80 +#define ICH5R_GPIO_USE_AS_GPIO 0x02 + +#define ICH5R_GPIO_SEL_MASK 0x0c +#define ICH5R_GPIO_SEL_DEFAULT 0x00 +#define ICH5R_GPIO_SEL_OUTPUT 0x04 +#define ICH5R_GPIO_SEL_INPUT 0x08 + +#define ICH5R_GPIO_LVL_MASK 0x30 +#define ICH5R_GPIO_LVL_DEFAULT 0x00 +#define ICH5R_GPIO_LVL_LOW 0x10 +#define ICH5R_GPIO_LVL_HIGH 0x20 +#define ICH5R_GPIO_LVL_BLINK 0x30 + +#define ICH5R_GPIO_INV_MASK 0xc0 +#define ICH5R_GPIO_INV_DEFAULT 0x00 +#define ICH5R_GPIO_INV_OFF 0x40 +#define ICH5R_GPIO_INV_ON 0x80
/* GPIO use select */ unsigned char gpio[64]; diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c index 045840a..373b24e 100644 --- a/src/southbridge/intel/i82801ex/ehci.c +++ b/src/southbridge/intel/i82801ex/ehci.c @@ -36,16 +36,16 @@ static struct pci_operations lops_pci = { }; static struct device_operations ehci_ops = { .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, + .init = ehci_init, + .scan_bus = 0, + .enable = i82801ex_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver ehci_driver __pci_driver = { - .ops = &ehci_ops, + .ops = &ehci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_EHCI, }; diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 3c7321a..baac9df 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -5,18 +5,18 @@
extern void i82801ex_enable(device_t dev);
-#define PCI_DMA_CFG 0x90 -#define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 -#define GEN_PMCON_3 0xa4 +#define PCI_DMA_CFG 0x90 +#define SERIRQ_CNTL 0x64 +#define GEN_CNTL 0xd0 +#define GEN_STS 0xd4 +#define RTC_CONF 0xd8 +#define GEN_PMCON_3 0xa4
-#define PMBASE 0x40 -#define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) -#define GPIO_BASE 0x58 -#define GPIO_CNTL 0x5C -#define GPIO_EN (1 << 4) +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4)
#endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c index bbab6f1..d981a43 100644 --- a/src/southbridge/intel/i82801ex/ide.c +++ b/src/southbridge/intel/i82801ex/ide.c @@ -28,15 +28,15 @@ static struct pci_operations lops_pci = { }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - .ops_pci = &lops_pci, + .init = ide_init, + .scan_bus = 0, + .ops_pci = &lops_pci, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_IDE, }; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index fb1586e..2c649c8 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev) #define LPC_EN 0xe6 static void i82801ex_enable_lpc(device_t dev) { - /* lpc i/f enable */ - pci_write_config8(dev, LPC_EN, 0x0d); + /* lpc i/f enable */ + pci_write_config8(dev, LPC_EN, 0x0d); }
typedef struct southbridge_intel_i82801ex_config config_t; @@ -96,7 +96,7 @@ static void set_i82801ex_gpio_use_sel( int val; switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) { case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break; - case ICH5R_GPIO_USE_AS_GPIO: val = 1; break; + case ICH5R_GPIO_USE_AS_GPIO: val = 1; break; default: continue; } @@ -172,7 +172,7 @@ static void set_i82801ex_gpio_level( gpio_lvl2 |= (val << (i - 32)); } } - outl(gpio_lvl, res->base + 0x0c); + outl(gpio_lvl, res->base + 0x0c); outl(gpio_blink, res->base + 0x18); outl(gpio_lvl2, res->base + 0x38); } @@ -195,7 +195,7 @@ static void set_i82801ex_gpio_inv( gpio_inv &= ~( 1 << i); gpio_inv |= (val << i); } - outl(gpio_inv, res->base + 0x2c); + outl(gpio_inv, res->base + 0x2c); }
static void i82801ex_pirq_init(device_t dev) @@ -260,10 +260,10 @@ static void enable_hpet(struct device *dev) dword |= (1 << 17); /* enable hpet */
/* Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh + * 00 FED0_0000h - FED0_03FFh + * 01 FED0_1000h - FED0_13FFh + * 10 FED0_2000h - FED0_23FFh + * 11 FED0_3000h - FED0_33FFh */
dword &= ~(3 << 15); /* clear it */ @@ -292,7 +292,7 @@ static void lpc_init(struct device *dev) /* Clear SATA to non raid */ pci_write_config8(dev, 0xae, 0x00);
- get_option(&pwr_on, "power_on_after_fail"); + get_option(&pwr_on, "power_on_after_fail"); byte = pci_read_config8(dev, 0xa4); byte &= 0xfe; if (!pwr_on) { @@ -366,16 +366,16 @@ static struct pci_operations lops_pci = {
static struct device_operations lpc_ops = { .read_resources = i82801ex_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = i82801ex_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = i82801ex_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_LPC, }; diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c index 80c6e49..30500db 100644 --- a/src/southbridge/intel/i82801ex/pci.c +++ b/src/southbridge/intel/i82801ex/pci.c @@ -30,15 +30,15 @@ static void pci_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - .ops_pci = 0, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .ops_pci = 0, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_PCI, }; diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c index 9936892..8036ffd 100644 --- a/src/southbridge/intel/i82801ex/reset.c +++ b/src/southbridge/intel/i82801ex/reset.c @@ -3,6 +3,6 @@
void hard_reset(void) { - /* Try rebooting through port 0xcf9 */ - outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); + /* Try rebooting through port 0xcf9 */ + outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c index 9b340e9..9985a81 100644 --- a/src/southbridge/intel/i82801ex/sata.c +++ b/src/southbridge/intel/i82801ex/sata.c @@ -39,21 +39,21 @@ static void sata_init(struct device *dev)
static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .scan_bus = 0, - .ops_pci = 0, + .init = sata_init, + .scan_bus = 0, + .ops_pci = 0, };
static const struct pci_driver sata_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_SATA, };
static const struct pci_driver sata_driver_nr __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801EB_SATA, }; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index 6bb4899..5f1d370 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -32,17 +32,17 @@ static struct pci_operations lops_pci = {
static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .init = 0, + .scan_bus = scan_static_bus, + .enable = i82801ex_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, + .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_SMB, }; diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h index f330c0a..9ea9fc7 100644 --- a/src/southbridge/intel/i82801ex/smbus.h +++ b/src/southbridge/intel/i82801ex/smbus.h @@ -38,10 +38,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base) unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0); return loops?0:-1; } @@ -51,10 +51,10 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_io_base + SMBHSTSTAT); + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_io_base + SMBHSTSTAT); } while((byte&(1<<7)) == 0); return loops?0:-1; } diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c index 56536b7..47f3b5e 100644 --- a/src/southbridge/intel/i82801ex/uhci.c +++ b/src/southbridge/intel/i82801ex/uhci.c @@ -28,28 +28,28 @@ static struct pci_operations lops_pci = {
static struct device_operations uhci_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = uhci_init, - .scan_bus = 0, - .enable = i82801ex_enable, - .ops_pci = &lops_pci, + .init = uhci_init, + .scan_bus = 0, + .enable = i82801ex_enable, + .ops_pci = &lops_pci, };
static const struct pci_driver uhci_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_USB1, };
static const struct pci_driver usb2_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_USB2, };
static const struct pci_driver usb3_driver __pci_driver = { - .ops = &uhci_ops, + .ops = &uhci_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82801ER_USB3, }; diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c index 26f6644..e1df17b 100644 --- a/src/southbridge/intel/i82801ex/watchdog.c +++ b/src/southbridge/intel/i82801ex/watchdog.c @@ -6,24 +6,24 @@
void watchdog_off(void) { - device_t dev; - unsigned long value,base; + device_t dev; + unsigned long value,base;
/* turn off the ICH5 watchdog */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); - /* Enable I/O space */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - /* Get TCO base */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - /* Disable the watchdog timer */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - /* Clear TCO timeout status */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); + dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + /* Enable I/O space */ + value = pci_read_config16(dev, 0x04); + value |= (1 << 10); + pci_write_config16(dev, 0x04, value); + /* Get TCO base */ + base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + /* Disable the watchdog timer */ + value = inw(base + 0x08); + value |= 1 << 11; + outw(value, base + 0x08); + /* Clear TCO timeout status */ + outw(0x0008, base + 0x04); + outw(0x0002, base + 0x06); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n"); }
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 62c6b43..a9e3f48 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -37,7 +37,7 @@ config EHCI_DEBUG_OFFSET default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801gx/bootblock.c"
config HPET_MIN_TICKS diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 576ecce..35bd012 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -27,28 +27,28 @@ #include "i82801gx.h"
#define NAMBAR 0x10 -#define MASTER_VOL 0x02 -#define PAGING 0x24 -#define EXT_AUDIO 0x28 -#define FUNC_SEL 0x66 -#define INFO_IO 0x68 -#define CONNECTOR 0x6a -#define VENDOR_ID1 0x7c -#define VENDOR_ID2 0x7e -#define SEC_VENDOR_ID1 0xfc -#define SEC_VENDOR_ID2 0xfe +#define MASTER_VOL 0x02 +#define PAGING 0x24 +#define EXT_AUDIO 0x28 +#define FUNC_SEL 0x66 +#define INFO_IO 0x68 +#define CONNECTOR 0x6a +#define VENDOR_ID1 0x7c +#define VENDOR_ID2 0x7e +#define SEC_VENDOR_ID1 0xfc +#define SEC_VENDOR_ID2 0xfe
#define NABMBAR 0x14 -#define GLOB_CNT 0x2c -#define GLOB_STA 0x30 -#define CAS 0x34 +#define GLOB_CNT 0x2c +#define GLOB_STA 0x30 +#define CAS 0x34
#define MMBAR 0x10 -#define EXT_MODEM_ID1 0x3c -#define EXT_MODEM_ID2 0xbc +#define EXT_MODEM_ID1 0x3c +#define EXT_MODEM_ID2 0xbc
#define MBAR 0x14 -#define SEC_CODEC 0x40 +#define SEC_CODEC 0x40
/* FIXME. This table is probably mainboard specific */ @@ -263,7 +263,7 @@ static void ac97_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations ac97_pci_ops = { - .set_subsystem = ac97_set_subsystem, + .set_subsystem = ac97_set_subsystem, };
static struct device_operations ac97_audio_ops = { diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 0384376..b305294 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -50,7 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x0f - LID state (open = 1) PWRS, 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State - LINX, 8, // 0x12 - Linux OS + LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ Offset (0x14), diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 96e662c..5c25a59 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -321,7 +321,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 153a456..65a09ad 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,15 +33,15 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void) { - u8 reg8; - device_t dev; + u8 reg8; + device_t dev;
- dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); }
static void bootblock_southbridge_init(void) @@ -49,6 +49,6 @@ static void bootblock_southbridge_init(void) #if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); #endif - enable_spi_prefetch(); + enable_spi_prefetch(); }
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1064dde..3a1c16f 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -61,9 +61,9 @@ int smbus_read_byte(unsigned device, unsigned address); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0)
/* PCI Configuration Space (D31:F0): LPC */
@@ -80,7 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address);
#define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -100,48 +100,48 @@ int smbus_read_byte(unsigned device, unsigned address); /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0)
/* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 @@ -296,26 +296,26 @@ int smbus_read_byte(unsigned device, unsigned address);
/* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -323,39 +323,39 @@ int smbus_read_byte(unsigned device, unsigned address); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#define USB4_STS (1 << 14) -#define PME_B0_STS (1 << 13) -#define USB3_STS (1 << 12) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define AC97_STS (1 << 5) -#define USB2_STS (1 << 4) -#define USB1_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define THRM_STS (1 << 0) +#define USB4_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c index c53c204..e2783bc 100644 --- a/src/southbridge/intel/i82801gx/ide.c +++ b/src/southbridge/intel/i82801gx/ide.c @@ -107,7 +107,7 @@ static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations ide_pci_ops = { - .set_subsystem = ide_set_subsystem, + .set_subsystem = ide_set_subsystem, };
static struct device_operations ide_ops = { diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..f6d2327 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -72,8 +72,8 @@ static void ich_pci_dev_enable_resources(struct device *dev) ops = ops_pci(dev); if (dev->on_mainboard && ops && ops->set_subsystem) { printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n", - dev_path(dev), dev->subsystem_vendor, - dev->subsystem_device); + dev_path(dev), dev->subsystem_vendor, + dev->subsystem_device); ops->set_subsystem(dev, dev->subsystem_vendor, dev->subsystem_device); } diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 0825dec..1c94fd4 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -74,13 +74,13 @@ static void pci_init(struct device *dev)
#ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif
/* Clear errors in status registers */ diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c index 0229f19..d181939 100644 --- a/src/southbridge/intel/i82801gx/reset.c +++ b/src/southbridge/intel/i82801gx/reset.c @@ -23,7 +23,7 @@
void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); }
#if 0 @@ -36,6 +36,6 @@ void hard_reset(void)
void hard_reset(void) { - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); + outb(0x02, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index ea29986..b55752d 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -200,7 +200,7 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = sata_set_subsystem, };
static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 750da51..01b5b8c 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -97,7 +97,7 @@ static int lsmbus_write_byte(device_t dev, u8 address, u8 data) }
static int do_smbus_block_write(unsigned smbus_base, unsigned device, - unsigned cmd, unsigned bytes, const u8 *buf) + unsigned cmd, unsigned bytes, const u8 *buf) { u8 status;
@@ -132,8 +132,8 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, do { status = inb(smbus_base + SMBHSTSTAT); if (status & ((1 << 4) | /* FAILED */ - (1 << 3) | /* BUS ERR */ - (1 << 2))) /* DEV ERR */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ return SMBUS_ERROR;
if (status & 0x80) { /* Byte done */ @@ -160,7 +160,7 @@ static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buf) }
static int do_smbus_block_read(unsigned smbus_base, unsigned device, - unsigned cmd, unsigned bytes, u8 *buf) + unsigned cmd, unsigned bytes, u8 *buf) { u8 status; int bytes_read = 0; @@ -189,8 +189,8 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, do { status = inb(smbus_base + SMBHSTSTAT); if (status & ((1 << 4) | /* FAILED */ - (1 << 3) | /* BUS ERR */ - (1 << 2))) /* DEV ERR */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ return SMBUS_ERROR;
if (status & 0x80) { /* Byte done */ @@ -224,9 +224,9 @@ static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buf)
static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, };
static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -241,7 +241,7 @@ static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = smbus_set_subsystem, };
static void smbus_read_resources(device_t dev) diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 8cb11b2..123b35f 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -35,11 +35,11 @@ extern unsigned char _binary_smm_size;
/* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index ba4d014..06e18b5 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -31,11 +31,11 @@
/* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#include "nvs.h"
@@ -240,37 +240,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } }
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index e8f9c27..d323ae2 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -58,7 +58,7 @@ static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations usb_pci_ops = { - .set_subsystem = usb_set_subsystem, + .set_subsystem = usb_set_subsystem, };
static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8a4a53e..9bf1873 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -2,7 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet security Networks AG +## 2012 secunet security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -38,7 +38,7 @@ config EHCI_DEBUG_OFFSET default 0xa0
config BOOTBLOCK_SOUTHBRIDGE_INIT - string + string default "southbridge/intel/i82801ix/bootblock.c"
endif diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 9176ff1..06a2419 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -2,7 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008-2009 coresystems GmbH -## 2012 secunet Security Networks AG +## 2012 secunet Security Networks AG ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 0384376..b305294 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -50,7 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x0f - LID state (open = 1) PWRS, 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State - LINX, 8, // 0x12 - Linux OS + LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ Offset (0x14), diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index b352fca..f2708b1 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -21,19 +21,19 @@
static void enable_spi_prefetch(void) { - u8 reg8; - device_t dev; + u8 reg8; + device_t dev;
- dev = PCI_DEV(0, 0x1f, 0); + dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); }
static void bootblock_southbridge_init(void) { - enable_spi_prefetch(); + enable_spi_prefetch(); }
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 222cfb5..d7a06de 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index 0514719..9af979b 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -132,7 +132,7 @@ void i82801ix_dmi_poll_vc1(void) RCBA16(0x20c4) |= (1 << 15); RCBA16(0x20e4) |= (1 << 15); /* TODO: Maybe we have to save and - restore these settings across S3. */ + restore these settings across S3. */ }
timeout = 0x7ffff; diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 8849cfa..ff3542b 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -56,9 +56,9 @@ void i82801ix_early_init(void) pci_write_config8(d31f0, 0xac, reg8);
/* TODO: If RTC power failed, reset RTC state machine - (set, then reset RTC 0x0b bit7) */ + (set, then reset RTC 0x0b bit7) */
/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) - before they get cleared. */ + before they get cleared. */ }
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 226afac..419cb30 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 49a0d95..f8ad233 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -307,7 +307,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 0fe7d20..2f1e66e 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * (Written by Nico Huber nico.huber@secunet.com for secunet) * * This program is free software; you can redistribute it and/or @@ -136,10 +136,10 @@ static void i82801ix_ehci_init(void) restore these settings across S3. */ reg32 = pci_read_config32(pciEHCI1, 0xfc); pci_write_config32(pciEHCI1, 0xfc, (reg32 & ~(3 << 2)) | - (1 << 29) | (1 << 17) | (2 << 2)); + (1 << 29) | (1 << 17) | (2 << 2)); reg32 = pci_read_config32(pciEHCI2, 0xfc); pci_write_config32(pciEHCI2, 0xfc, (reg32 & ~(3 << 2)) | - (1 << 29) | (1 << 17) | (2 << 2)); + (1 << 29) | (1 << 17) | (2 << 2)); }
static int i82801ix_function_disabled(const unsigned devfn) @@ -147,8 +147,8 @@ static int i82801ix_function_disabled(const unsigned devfn) const struct device *const dev = dev_find_slot(0, devfn); if (!dev) { printk(BIOS_EMERG, - "PCI device 00:%x.%x", - PCI_SLOT(devfn), PCI_FUNC(devfn)); + "PCI device 00:%x.%x", + PCI_SLOT(devfn), PCI_FUNC(devfn)); die(" is not listed in devicetree.\n"); } return !dev->enabled; @@ -160,7 +160,7 @@ static void i82801ix_hide_functions(void) u32 reg32;
/* FIXME: This works pretty good if the devicetree is consistent. But - some functions have to be disabled in right order and/or have + some functions have to be disabled in right order and/or have other constraints. */
if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0))) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d84af3a..94b580a 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -46,13 +46,13 @@ #define APM_CNT 0xb2
#define PM1_STS 0x00 -#define PWRBTN_STS (1 << 8) -#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) #define PM1_EN 0x02 -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) #define PM1_CNT 0x04 -#define SCI_EN (1 << 0) +#define SCI_EN (1 << 0) #define PM_LV2 0x14 #define PM_LV3 0x15 #define PM_LV4 0x16 @@ -60,12 +60,12 @@ #define PM_LV6 0x18 #define GPE0_STS 0x20 #define SMI_EN 0x30 -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define APMC_EN (1 << 5) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) +#define PERIODIC_EN (1 << 14) +#define TCO_EN (1 << 13) +#define APMC_EN (1 << 5) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bea0d98..e748bb8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -276,10 +276,10 @@ static void i82801ix_power_options(device_t dev) /* Set up power management block and determine sleep mode */ reg16 = inw(pmbase + 0x00); /* PM1_STS */ outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power - button override) must be cleared or SCI - will be constantly fired and OSPM must - not know about it (ACPI spec says to - ignore the bit). */ + button override) must be cleared or SCI + will be constantly fired and OSPM must + not know about it (ACPI spec says to + ignore the bit). */ reg32 = inl(pmbase + 0x04); // PM1_CNT reg32 &= ~(7 << 10); // SLP_TYP outl(reg32, pmbase + 0x04); @@ -470,7 +470,7 @@ static void lpc_init(struct device *dev) static void i82801ix_lpc_read_resources(device_t dev) { /* - * I/O Resources + * I/O Resources * * 0x0000 - 0x000f....ISA DMA * 0x0010 - 0x001f....ISA DMA aliases diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index f53519d..69117c3 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index cd555c9..33070e2 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -258,7 +258,7 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = sata_set_subsystem, };
static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..e571794 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -36,11 +36,11 @@ extern unsigned char _binary_smm_size;
/* I945/GM45 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 6d17621..77dd976 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6a0f0d2..abc3305 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -25,15 +25,15 @@ static void p64h2_ioapic_enable(device_t dev) * will be called twice for each P64H2 in the system. * * @param dev PCI bus/device/function of P64H2 IOAPIC. - * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0. + * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0. */ static void p64h2_ioapic_init(device_t dev) { uint32_t memoryBase; int apic_index, apic_id;
- volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t* pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ + volatile uint32_t* pWindowRegister; /* io apic io memory space data address */
apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; @@ -49,11 +49,11 @@ static void p64h2_ioapic_init(device_t dev) // IDs 3, 4, 5, and 8+ are available (see above note)
if (apic_index < 3) - apic_id = apic_index + 3; + apic_id = apic_index + 3; else - apic_id = apic_index + 5; + apic_id = apic_index + 5;
- ASSERT(apic_id < 16); // ID is only 4 bits + ASSERT(apic_id < 16); // ID is only 4 bits
// Read the MBAR address for setting up the IOAPIC in memory space // NOTE: this address was assigned during enumeration of the bus @@ -63,36 +63,36 @@ static void p64h2_ioapic_init(device_t dev) pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", - apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
- apic_id <<= 24; // Convert ID to bitmask + apic_id <<= 24; // Convert ID to bitmask
- *pIndexRegister = 0; // Select APIC ID register + *pIndexRegister = 0; // Select APIC ID register *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
if ((*pWindowRegister & (0xF<<24)) != apic_id) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed");
*pIndexRegister = 3; // Select Boot Configuration register *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
if (!(*pWindowRegister & 1)) - die("p64h2_ioapic_init failed"); + die("p64h2_ioapic_init failed"); }
static struct device_operations ioapic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = p64h2_ioapic_init, - .scan_bus = 0, - .enable = p64h2_ioapic_enable, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = p64h2_ioapic_init, + .scan_bus = 0, + .enable = p64h2_ioapic_enable, };
static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1E0, + .ops = &ioapic_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1E0,
}; diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c index fe27abf..dfa5c1d 100644 --- a/src/southbridge/intel/i82870/pci_parity.c +++ b/src/southbridge/intel/i82870/pci_parity.c @@ -5,21 +5,21 @@
void p64h2_pci_parity_enable(void) { - uint8_t reg; + uint8_t reg;
- /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
- /* 2SERREN - SERR enable for PCI bridge secondary device */ - /* 2PEREN - Parity error for PCI bridge secondary device */ - pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®); - reg |= ((1 << 1) + (1 << 0)); - pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg); + /* 2SERREN - SERR enable for PCI bridge secondary device */ + /* 2PEREN - Parity error for PCI bridge secondary device */ + pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®); + reg |= ((1 << 1) + (1 << 0)); + pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
- return; + return; }
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c index 89b86f5..38681c8 100644 --- a/src/southbridge/intel/i82870/pcibridge.c +++ b/src/southbridge/intel/i82870/pcibridge.c @@ -23,17 +23,17 @@ static void p64h2_pcix_init(device_t dev)
} static struct device_operations pcix_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = p64h2_pcix_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = p64h2_pcix_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, };
static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_INTEL_82870_1F0, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82870_1F0, };
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index c408dca..3e52202 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -68,7 +68,7 @@ config BUILD_WITH_FAKE_IFD WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.
- [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
config IFD_BIOS_SECTION diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index a29129d..92b175a 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -66,14 +66,14 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" printf "flash ROM! Make sure that you only write valid flash regions.\n\n" - printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) endif - printf " DD Adding Intel Firmware Descriptor\n" + printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 ifeq ($(CONFIG_HAVE_ME_BIN),y) - printf " IFDTOOL me.bin -> coreboot.pre\n" + printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre @@ -85,11 +85,11 @@ else printf "flash ROM! Make sure that you only write valid flash regions.\n\n" endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" + printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) - printf " IFDTOOL Unlocking Management Engine\n" + printf " IFDTOOL Unlocking Management Engine\n" $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 8a1116a..df6e877 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -350,7 +350,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index bc56012..0c7f5c1 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -82,10 +82,10 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -234,7 +234,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); + ndata + 2, host.buffer_depth); return -1; }
@@ -288,8 +288,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, } if (!n) { printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); return -1; }
@@ -315,9 +315,9 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, " - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */ @@ -325,7 +325,7 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + "%u != %u\n", ndata, rsp_bytes >> 2); return -1; }
@@ -344,7 +344,7 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi, }
static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -402,11 +402,11 @@ static int mkhi_get_fw_version(void) }
printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " - "%u.%u.%u.%u (recovery)\n", - version.code_major, version.code_minor, - version.code_build_number, version.code_hot_fix, - version.recovery_major, version.recovery_minor, - version.recovery_build_number, version.recovery_hot_fix); + "%u.%u.%u.%u (recovery)\n", + version.code_major, version.code_minor, + version.code_build_number, version.code_hot_fix, + version.recovery_major, version.recovery_minor, + version.recovery_build_number, version.recovery_hot_fix);
return 0; } @@ -414,7 +414,7 @@ static int mkhi_get_fw_version(void) static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); + name, state ? "en" : "dis"); }
/* Get ME Firmware Capabilities */ @@ -450,7 +450,7 @@ static int mkhi_get_fwcaps(void) print_cap("IntelR Power Sharing Technology (MPC)", cap.caps_sku.intel_mpc); print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); + print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); print_cap("IPV6", cap.caps_sku.ipv6); print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); @@ -601,12 +601,12 @@ static me_bios_path intel_me_path(device_t dev) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = gmes.progress_code, - .current_pmevent = gmes.current_pmevent, - .current_state = gmes.current_state, + .operation_state = hfs.operation_state, + .operation_mode = hfs.operation_mode, + .error_code = hfs.error_code, + .progress_code = gmes.progress_code, + .current_pmevent = gmes.current_pmevent, + .current_state = gmes.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, @@ -676,7 +676,7 @@ static int intel_me_extend_valid(device_t dev) break; default: printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); + status.extend_reg_algorithm); return -1; }
diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 6e2062d..4d56756 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -194,7 +194,7 @@ struct mei_header { #define MKHI_MDES_ENABLE 0x09
#define MKHI_GET_FW_VERSION 0x02 -#define MKHI_SET_UMA 0x08 +#define MKHI_SET_UMA 0x08 #define MKHI_END_OF_POST 0x0c #define MKHI_FEATURE_OVERRIDE 0x14
@@ -218,7 +218,7 @@ struct me_fw_version { } __attribute__ ((packed));
-#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
#define CBM_RR_GLOBAL_RESET 0x01 @@ -256,18 +256,18 @@ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); #endif typedef struct { - u32 major_version : 16; - u32 minor_version : 16; - u32 hotfix_version : 16; - u32 build_version : 16; + u32 major_version : 16; + u32 minor_version : 16; + u32 hotfix_version : 16; + u32 build_version : 16; } __attribute__ ((packed)) mbp_fw_version_name;
typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 register_lock_mask[3]; + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 register_lock_mask[3]; } __attribute__ ((packed)) mbp_icc_profile;
typedef struct { @@ -297,16 +297,16 @@ typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; - u16 flash_wear_out : 1; + u16 flash_wear_out : 1; u16 flash_variable_security : 1; - u16 wwan3gpresent : 1; + u16 wwan3gpresent : 1; u16 wwan3goob : 1; u16 reserved : 9; } __attribute__ ((packed)) tdt_state_flag;
typedef struct { - u8 state; - u8 last_theft_trigger; + u8 state; + u8 last_theft_trigger; tdt_state_flag flags; } __attribute__ ((packed)) tdt_state_info;
@@ -322,39 +322,39 @@ typedef struct {
typedef struct { mefwcaps_sku fw_capabilities; - u8 available; + u8 available; } mbp_fw_caps;
typedef struct { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; } __attribute__ ((packed)) mbp_rom_bist_data;
typedef struct { - u32 key[8]; + u32 key[8]; } mbp_platform_key;
typedef struct { platform_type_rule_data rule_data; - u8 available; + u8 available; } mbp_plat_type;
typedef struct { mbp_fw_version_name fw_version_name; - mbp_fw_caps fw_caps_sku; + mbp_fw_caps fw_caps_sku; mbp_rom_bist_data rom_bist_data; mbp_platform_key platform_key; - mbp_plat_type fw_plat_type; + mbp_plat_type fw_plat_type; mbp_icc_profile icc_profile; tdt_state_info at_state; - u32 mfsintegrity; + u32 mfsintegrity; } me_bios_payload;
typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __attribute__ ((packed)) mbp_header;
typedef struct { diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 7b8b6c9..a704e72 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -63,7 +63,7 @@ typedef struct { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 356dd8a..b0e772c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,8 +22,8 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
/* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ #define PCH_TYPE_MOBILE5 0x3b
/* PCH stepping values for LPC device */ @@ -95,9 +95,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -123,7 +123,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -161,48 +161,48 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -253,7 +253,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -297,13 +297,13 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) +#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) +#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) /* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ @@ -340,7 +340,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
@@ -391,7 +391,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ - ((b) << DIR_IBR) | ((a) << DIR_IAR)) + ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */ #define HPTC 0x3404 /* 32bit */ @@ -442,31 +442,31 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
/* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -474,33 +474,33 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -509,7 +509,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
/* @@ -553,19 +553,19 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ +#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x3808 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_FADDR 0x3808 /* SPI flash address */ +#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
#endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 943d085..441f39e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -96,7 +96,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); + sata_port_map ^ 0x3f) << 24) | 0x183); } else if (config->sata_ahci) { u32 abar;
@@ -129,7 +129,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183 | + sata_port_map ^ 0x3f) << 24) | 0x183 | 0x40000000); pci_write_config32(dev, 0x98, 0x00590200);
@@ -205,7 +205,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); + sata_port_map ^ 0x3f) << 24) | 0x183); }
/* Set Gen3 Transmitter settings if needed */ diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index ad7c8f9..bc64bd5 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -74,7 +74,7 @@ static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = smbus_set_subsystem, };
static void smbus_read_resources(device_t dev) diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h index 6858e7d..0f7ba9f 100644 --- a/src/southbridge/intel/ibexpeak/smbus.h +++ b/src/southbridge/intel/ibexpeak/smbus.h @@ -145,7 +145,7 @@ static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned a }
static int do_smbus_block_write(unsigned smbus_base, unsigned device, - unsigned cmd, unsigned bytes, const u8 *buf) + unsigned cmd, unsigned bytes, const u8 *buf) { u8 status;
@@ -180,8 +180,8 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, do { status = inb(smbus_base + SMBHSTSTAT); if (status & ((1 << 4) | /* FAILED */ - (1 << 3) | /* BUS ERR */ - (1 << 2))) /* DEV ERR */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ return SMBUS_ERROR;
if (status & 0x80) { /* Byte done */ @@ -194,7 +194,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device, }
static int do_smbus_block_read(unsigned smbus_base, unsigned device, - unsigned cmd, unsigned bytes, u8 *buf) + unsigned cmd, unsigned bytes, u8 *buf) { u8 status; int bytes_read = 0; @@ -223,8 +223,8 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device, do { status = inb(smbus_base + SMBHSTSTAT); if (status & ((1 << 4) | /* FAILED */ - (1 << 3) | /* BUS ERR */ - (1 << 2))) /* DEV ERR */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ return SMBUS_ERROR;
if (status & 0x80) { /* Byte done */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2b85e2b..b6da882 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -357,14 +357,14 @@ static void smm_install(void) /* copy the real SMM handler */ printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base); memcpy((void *)smm_base, &_binary_smm_start, - (size_t)(&_binary_smm_end - &_binary_smm_start)); + (size_t)(&_binary_smm_end - &_binary_smm_start));
/* copy the IED header into place */ if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) { /* Top of TSEG region */ smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE; printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n", - smm_base); + smm_base); memcpy((void *)smm_base, &ied, sizeof(ied)); } wbinvd(); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..b8356bb 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -257,37 +257,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } }
/* @@ -342,7 +342,7 @@ static void xhci_sleep(u8 slp_typ) pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
xhci_bar = pci_read_config32(PCH_XHCI_DEV, - PCI_BASE_ADDRESS_0) & ~0xFUL; + PCI_BASE_ADDRESS_0) & ~0xFUL;
if ((xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c index e263b7f..557f9bb 100644 --- a/src/southbridge/intel/ibexpeak/spi.c +++ b/src/southbridge/intel/ibexpeak/spi.c @@ -186,7 +186,7 @@ static u8 readb_(const void *addr) { u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -194,7 +194,7 @@ static u16 readw_(const void *addr) { u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -202,7 +202,7 @@ static u32 readl_(const void *addr) { u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -210,21 +210,21 @@ static void writeb_(u8 b, const void *addr) { write8((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writew_(u16 b, const void *addr) { write16((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writel_(u32 b, const void *addr) { write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 4d96edf..c6a39c8 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -62,20 +62,20 @@ ramstage-y += gpio.c endif
lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL) - printf " DD Adding Intel Firmware Descriptor\n" + printf " DD Adding Intel Firmware Descriptor\n" dd if=$(CONFIG_IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 - printf " IFDTOOL me.bin -> coreboot.pre\n" + printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" + printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre else - printf " IFDTOOL Unlocking Management Engine\n" + printf " IFDTOOL Unlocking Management Engine\n" $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ef05dca..0c6a547 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -52,9 +52,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x10 - Power State (AC = 1) /* Thermal policy */ Offset (0x11), - TLVL, 8, // 0x11 - Throttle Level Limit + TLVL, 8, // 0x11 - Throttle Level Limit FLVL, 8, // 0x12 - Current FAN Level - TCRT, 8, // 0x13 - Critical Threshold + TCRT, 8, // 0x13 - Critical Threshold TPSV, 8, // 0x14 - Passive Threshold TMAX, 8, // 0x15 - CPU Tj_max F0OF, 8, // 0x16 - FAN 0 OFF Threshold @@ -72,7 +72,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value - TMPS, 8, // 0x25 - Temperature Sensor ID + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 07b3fcf..90b501c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -33,7 +33,7 @@ Device (LPCB) Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), - GPBS, 16, // GPIOBASE + GPBS, 16, // GPIOBASE Offset (0x60), // Interrupt Routing Registers PRTA, 8, PRTB, 8, diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl index fd64cb8..a9a6db1 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl @@ -75,11 +75,11 @@ Scope (_SB.PCI0.LPCB) // GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) Field (GPNC, AnyAcc, NoLock, Preserve) { - GMOD, 1, // MODE: 0=NATIVE 1=GPIO + GMOD, 1, // MODE: 0=NATIVE 1=GPIO , 1, GIOS, 1, // IO_SEL: 0=OUTPUT 1=INPUT GINV, 1, // INVERT: 0=NORMAL 1=INVERT - GLES, 1, // LxEB: 0=EDGE 1=LEVEL + GLES, 1, // LxEB: 0=EDGE 1=LEVEL , 24, ILVL, 1, // INPUT: 0=LOW 1=HIGH OLVL, 1, // OUTPUT: 0=LOW 1=HIGH diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 4c0d36b..e4ceb52 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -490,17 +490,17 @@ Device (GPIO) Name (RBUF, ResourceTemplate() { DWordIo (ResourceProducer, - MinFixed, // IsMinFixed - MaxFixed, // IsMaxFixed - PosDecode, // Decode + MinFixed, // IsMinFixed + MaxFixed, // IsMaxFixed + PosDecode, // Decode EntireRange, // ISARanges 0x00000000, // AddressGranularity 0x00000000, // AddressMinimum 0x00000000, // AddressMaximum 0x00000000, // AddressTranslation 0x00000000, // RangeLength - , // ResourceSourceIndex - , // ResourceSource + , // ResourceSourceIndex + , // ResourceSource BAR0) })
@@ -514,7 +514,7 @@ Device (GPIO) Store (DEFAULT_GPIOSIZE, BLEN) Store (DEFAULT_GPIOBASE, BMIN) Store (Subtract (Add (DEFAULT_GPIOBASE, - DEFAULT_GPIOSIZE), 1), BMAX) + DEFAULT_GPIOSIZE), 1), BMAX) }
Return (RBUF) diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index ee12042..771bc56 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -353,7 +353,7 @@ static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations azalia_pci_ops = { - .set_subsystem = azalia_set_subsystem, + .set_subsystem = azalia_set_subsystem, };
static struct device_operations azalia_ops = { diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index 6b61eac..0b1c786 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -140,7 +140,7 @@ int intel_early_me_init_done(u8 status)
/* Send message to ME */ printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, " - "UMA base: 0x%04x\n", status, did.uma_base); + "UMA base: 0x%04x\n", status, did.uma_base);
pci_write_dword_ptr(&did, PCI_ME_H_GS);
@@ -165,7 +165,7 @@ int intel_early_me_init_done(u8 status)
/* Return the requested BIOS action */ printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n", - me_ack_values[hfs.ack_data]); + me_ack_values[hfs.ack_data]);
/* Check status after acknowledgement */ intel_early_me_status(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 38506c9..1e961c3 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -124,7 +124,7 @@ static void pch_enable_lpc(void) }
int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) + const struct rcba_config_instruction *rcba_config) { int wake_from_s3;
diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c index 6f57f63..ec44842 100644 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ b/src/southbridge/intel/lynxpoint/early_spi.c @@ -25,7 +25,7 @@ #include <delay.h> #include "pch.h"
-#define SPI_DELAY 10 /* 10us */ +#define SPI_DELAY 10 /* 10us */ #define SPI_RETRY 200000 /* 2s */
static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 9ba3a98..80b7531 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -98,7 +98,7 @@ static void pch_log_gpe(void) continue; if (gpe0_sts & (1 << i)) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, - gpe0_high_gpios[i]); + gpe0_high_gpios[i]); } }
@@ -161,7 +161,7 @@ void pch_log_state(void) /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_slp_type == 3 ? 3 : 5); + acpi_slp_type == 3 ? 3 : 5);
/* * Wake sources diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 147a1c0..42dab7f 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -102,7 +102,7 @@ unsigned get_gpios(const int *gpio_num_array) unsigned vector = 0;
while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { + ((gpio = *gpio_num_array++) != -1)) { if (get_gpio(gpio)) vector |= bitmask; bitmask <<= 1; diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 7d1a28d..147a14b 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -138,7 +138,7 @@ unsigned get_gpios(const int *gpio_num_array) unsigned vector = 0;
while (bitmask && - ((gpio = *gpio_num_array++) != -1)) { + ((gpio = *gpio_num_array++) != -1)) { if (get_gpio(gpio)) vector |= bitmask; bitmask <<= 1; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff50476..3cd41d6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -261,7 +261,7 @@ static void pch_power_options(device_t dev)
/* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, - config->gpe0_en_3, config->gpe0_en_4); + config->gpe0_en_3, config->gpe0_en_4);
/* SMI setup based on device tree configuration */ enable_alt_smi(config->alt_gp_smi_en); @@ -312,7 +312,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = { RCBA_RMW_REG_32(0x1100, ~0xc000, 0xc000), /* 5 */ RCBA_RMW_REG_32(0x1100, ~0, 0x00000100), /* 6 */ RCBA_RMW_REG_32(0x1100, ~0, 0x0000003f), /* 7 */ - RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), /* 8? */ + RCBA_RMW_REG_32(0x2320, ~0x60, 0x10), /* 8? */ RCBA_RMW_REG_32(0x3314, 0, 0x00012fff), /* 9? */ RCBA_RMW_REG_32(0x3318, 0, 0x0dcf0400), /* 10? */ RCBA_RMW_REG_32(0x3324, 0, 0x04000000), /* 11 */ @@ -595,7 +595,7 @@ static void pch_lpc_add_mmio_resources(device_t dev) res->base = DEFAULT_RCBA; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; }
/* Check LPC Memory Decode register. */ @@ -607,7 +607,7 @@ static void pch_lpc_add_mmio_resources(device_t dev) res->base = reg; res->size = 16 * 1024; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED | IORESOURCE_RESERVE; + IORESOURCE_FIXED | IORESOURCE_RESERVE; } } } @@ -674,7 +674,7 @@ static void pch_lpc_add_io_resources(device_t dev)
/* GPIOBASE */ pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, - GPIO_BASE); + GPIO_BASE);
/* PMBASE */ pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index d919107..ce3f65a 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -121,10 +121,10 @@ struct me_did { #define ME_HFS2_PHASE_UNKNOWN 5 #define ME_HFS2_PHASE_HOST_COMM 6 /* Current State - Based on Infra Progress values. */ -/* ROM State */ +/* ROM State */ #define ME_HFS2_STATE_ROM_BEGIN 0 #define ME_HFS2_STATE_ROM_DISABLE 6 -/* BUP State */ +/* BUP State */ #define ME_HFS2_STATE_BUP_INIT 0 #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 #define ME_HFS2_STATE_BUP_FLOW_DET 4 @@ -150,7 +150,7 @@ struct me_did { #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 -/* Policy Module State */ +/* Policy Module State */ #define ME_HFS2_STATE_POLICY_ENTRY 0 #define ME_HFS2_STATE_POLICY_RCVD_S3 3 #define ME_HFS2_STATE_POLICY_RCVD_S4 4 @@ -199,7 +199,7 @@ struct me_hfs2 { } __attribute__ ((packed));
#define PCI_ME_H_GS2 0x70 -#define PCI_ME_MBP_GIVE_UP 0x01 +#define PCI_ME_MBP_GIVE_UP 0x01
#define PCI_ME_HERES 0xbc #define PCI_ME_EXT_SHA1 0x00 @@ -287,7 +287,7 @@ struct me_fw_version { } __attribute__ ((packed));
-#define HECI_EOP_STATUS_SUCCESS 0x0 +#define HECI_EOP_STATUS_SUCCESS 0x0 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
#define CBM_RR_GLOBAL_RESET 0x01 @@ -359,7 +359,7 @@ void intel_me8_finalize_smm(void); typedef struct { u32 mbp_size : 8; u32 num_entries : 8; - u32 rsvd : 16; + u32 rsvd : 16; } __attribute__ ((packed)) mbp_header;
typedef struct { @@ -370,10 +370,10 @@ typedef struct { } __attribute__ ((packed)) mbp_item_header;
typedef struct { - u32 major_version : 16; - u32 minor_version : 16; - u32 hotfix_version : 16; - u32 build_version : 16; + u32 major_version : 16; + u32 minor_version : 16; + u32 hotfix_version : 16; + u32 build_version : 16; } __attribute__ ((packed)) mbp_fw_version_name;
typedef struct { @@ -399,13 +399,13 @@ typedef struct { } __attribute__ ((packed)) mbp_mefwcaps;
typedef struct { - u16 device_id; - u16 fuse_test_flags; - u32 umchid[4]; + u16 device_id; + u16 fuse_test_flags; + u32 umchid[4]; } __attribute__ ((packed)) mbp_rom_bist_data;
typedef struct { - u32 key[8]; + u32 key[8]; } mbp_platform_key;
typedef struct { @@ -424,7 +424,7 @@ typedef struct {
typedef struct { mbp_me_firmware_type rule_data; - u8 available; + u8 available; } mbp_plat_type;
typedef struct { @@ -433,11 +433,11 @@ typedef struct { } __attribute__ ((packed)) icc_address_mask;
typedef struct { - u8 num_icc_profiles; - u8 icc_profile_soft_strap; - u8 icc_profile_index; - u8 reserved; - u32 icc_reg_bundles; + u8 num_icc_profiles; + u8 icc_profile_soft_strap; + u8 icc_profile_index; + u8 reserved; + u32 icc_reg_bundles; icc_address_mask icc_address_mask[0]; } __attribute__ ((packed)) mbp_icc_profile;
@@ -445,14 +445,14 @@ typedef struct { u16 lock_state : 1; u16 authenticate_module : 1; u16 s3authentication : 1; - u16 flash_wear_out : 1; + u16 flash_wear_out : 1; u16 flash_variable_security : 1; u16 reserved : 11; } __attribute__ ((packed)) tdt_state_flag;
typedef struct { - u8 state; - u8 last_theft_trigger; + u8 state; + u8 last_theft_trigger; tdt_state_flag flags; } __attribute__ ((packed)) mbp_at_state;
@@ -464,20 +464,20 @@ typedef struct {
typedef struct { u32 device_type : 2; - u32 reserved : 30; + u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data;
typedef struct { mbp_fw_version_name *fw_version_name; - mbp_mefwcaps *fw_capabilities; + mbp_mefwcaps *fw_capabilities; mbp_rom_bist_data *rom_bist_data; mbp_platform_key *platform_key; - mbp_plat_type *fw_plat_type; + mbp_plat_type *fw_plat_type; mbp_icc_profile *icc_profile; - mbp_at_state *at_state; - u32 *mfsintegrity; - mbp_plat_time *plat_time; - mbp_nfc_data *nfc_data; + mbp_at_state *at_state; + u32 *mfsintegrity; + mbp_plat_time *plat_time; + mbp_nfc_data *nfc_data; } me_bios_payload;
struct me_fwcaps { diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index bde4e9d..556b0d3 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -77,10 +77,10 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) break; } printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u " - "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, - csr->buffer_read_ptr, csr->buffer_write_ptr, - csr->ready, csr->reset, csr->interrupt_generate, - csr->interrupt_status, csr->interrupt_enable); + "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth, + csr->buffer_read_ptr, csr->buffer_write_ptr, + csr->ready, csr->reset, csr->interrupt_generate, + csr->interrupt_status, csr->interrupt_enable); break; case MEI_ME_CB_RW: case MEI_H_CB_WW: @@ -227,7 +227,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, */ if ((host.buffer_depth - host.buffer_write_ptr) < ndata) { printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n", - ndata + 2, host.buffer_depth); + ndata + 2, host.buffer_depth); return -1; }
@@ -281,8 +281,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi, } if (!n) { printk(BIOS_ERR, "ME: timeout waiting for data: expected " - "%u, available %u\n", expected, - me.buffer_write_ptr - me.buffer_read_ptr); + "%u, available %u\n", expected, + me.buffer_write_ptr - me.buffer_read_ptr); return -1; }
@@ -299,7 +299,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, ndata++; if (ndata != (expected - 1)) { printk(BIOS_ERR, "ME: response is missing data %d != %d\n", - ndata, (expected - 1)); + ndata, (expected - 1)); return -1; }
@@ -309,9 +309,9 @@ static int mei_recv_msg(struct mkhi_header *mkhi, mkhi->group_id != mkhi_rsp.group_id || mkhi->command != mkhi_rsp.command) { printk(BIOS_ERR, "ME: invalid response, group %u ?= %u," - "command %u ?= %u, is_response %u\n", mkhi->group_id, - mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, - mkhi_rsp.is_response); + "command %u ?= %u, is_response %u\n", mkhi->group_id, + mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command, + mkhi_rsp.is_response); return -1; } ndata--; /* MKHI header has been read */ @@ -319,7 +319,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, /* Make sure caller passed a buffer with enough space */ if (ndata != (rsp_bytes >> 2)) { printk(BIOS_ERR, "ME: not enough room in response buffer: " - "%u != %u\n", ndata, rsp_bytes >> 2); + "%u != %u\n", ndata, rsp_bytes >> 2); return -1; }
@@ -338,7 +338,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, }
static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -351,7 +351,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", - name, state ? " en" : "dis"); + name, state ? " en" : "dis"); }
static void me_print_fw_version(mbp_fw_version_name *vers_name) @@ -362,8 +362,8 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name) }
printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n", - vers_name->major_version, vers_name->minor_version, - vers_name->hotfix_version, vers_name->build_version); + vers_name->major_version, vers_name->minor_version, + vers_name->hotfix_version, vers_name->build_version); }
/* Get ME Firmware Capabilities */ @@ -372,14 +372,14 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) u32 rule_id = 0; struct me_fwcaps cap_msg; struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, + .group_id = MKHI_GROUP_ID_FWCAPS, + .command = MKHI_FWCAPS_GET_RULE, }; struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), + .length = sizeof(mkhi) + sizeof(rule_id), };
/* Send request and wait for response */ @@ -387,7 +387,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -410,7 +410,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och); @@ -532,7 +532,7 @@ static me_bios_path intel_me_path(device_t dev) /* Check if the MBP is ready */ if (!hfs2.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __FUNCTION__); path = ME_ERROR_BIOS_PATH; }
@@ -540,12 +540,12 @@ static me_bios_path intel_me_path(device_t dev) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, - .operation_state = hfs.operation_state, - .operation_mode = hfs.operation_mode, - .error_code = hfs.error_code, - .progress_code = hfs2.progress_code, - .current_pmevent = hfs2.current_pmevent, - .current_state = hfs2.current_state, + .operation_state = hfs.operation_state, + .operation_mode = hfs.operation_mode, + .error_code = hfs.error_code, + .progress_code = hfs2.progress_code, + .current_pmevent = hfs2.current_pmevent, + .current_state = hfs2.current_state, }; elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT, @@ -615,7 +615,7 @@ static int intel_me_extend_valid(device_t dev) break; default: printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n", - status.extend_reg_algorithm); + status.extend_reg_algorithm); return -1; }
@@ -684,11 +684,11 @@ static void intel_me_init(device_t dev)
if (mbp_data.plat_time) { printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n", - mbp_data.plat_time->wake_event_mrst_time_ms); + mbp_data.plat_time->wake_event_mrst_time_ms); printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n", - mbp_data.plat_time->mrst_pltrst_time_ms); + mbp_data.plat_time->mrst_pltrst_time_ms); printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n", - mbp_data.plat_time->pltrst_cpurst_time_ms); + mbp_data.plat_time->pltrst_cpurst_time_ms); } #endif
@@ -734,7 +734,7 @@ static const struct pci_driver intel_me __pci_driver = { };
/****************************************************************************** - * */ + * */ static u32 me_to_host_words_pending(void) { struct mei_csr me; @@ -816,9 +816,9 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) || (me2host_pending < mbp_hdr.mbp_size)) { printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words" - " buffer contains %d words\n", - mbp_hdr.num_entries, mbp_hdr.mbp_size, - me2host_pending); + " buffer contains %d words\n", + mbp_hdr.num_entries, mbp_hdr.mbp_size, + me2host_pending); goto mbp_failure; } mbp = malloc(mbp_hdr.mbp_size * sizeof(u32)); @@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) /* Dump out the MBP contents. */ #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", - mbp->header.num_entries, mbp->header.mbp_size); + mbp->header.num_entries, mbp->header.mbp_size); for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } @@ -903,7 +903,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
default: printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ dw offset 0x%x\n", - mbp->data[i], i); + mbp->data[i], i); break; } i += item->length; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index d09be7b..4d5636e 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -149,43 +149,43 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) { #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) /* Check Current States */ - printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", - hfs->fpt_bad ? "BAD" : "OK"); + printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", + hfs->fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", - hfs->ft_bup_ld_flr ? "YES" : "NO"); + hfs->ft_bup_ld_flr ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: Firmware Init Complete : %s\n", - hfs->fw_init_complete ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfs->mfg_mode ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", - hfs->boot_options_present ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", - hfs->update_in_progress ? "YES" : "NO"); - printk(BIOS_DEBUG, "ME: Current Working State : %s\n", - me_cws_values[hfs->working_state]); + hfs->fw_init_complete ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfs->mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Boot Options Present : %s\n", + hfs->boot_options_present ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Update In Progress : %s\n", + hfs->update_in_progress ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Current Working State : %s\n", + me_cws_values[hfs->working_state]); printk(BIOS_DEBUG, "ME: Current Operation State : %s\n", - me_opstate_values[hfs->operation_state]); + me_opstate_values[hfs->operation_state]); printk(BIOS_DEBUG, "ME: Current Operation Mode : %s\n", - me_opmode_values[hfs->operation_mode]); - printk(BIOS_DEBUG, "ME: Error Code : %s\n", - me_error_values[hfs->error_code]); - printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", - me_progress_values[hfs2->progress_code]); + me_opmode_values[hfs->operation_mode]); + printk(BIOS_DEBUG, "ME: Error Code : %s\n", + me_error_values[hfs->error_code]); + printk(BIOS_DEBUG, "ME: Progress Phase : %s\n", + me_progress_values[hfs2->progress_code]); printk(BIOS_DEBUG, "ME: Power Management Event : %s\n", - me_pmevent_values[hfs2->current_pmevent]); + me_pmevent_values[hfs2->current_pmevent]);
- printk(BIOS_DEBUG, "ME: Progress Phase State : "); + printk(BIOS_DEBUG, "ME: Progress Phase State : "); switch (hfs2->progress_code) { case ME_HFS2_PHASE_ROM: /* ROM Phase */ printk(BIOS_DEBUG, "%s", - me_progress_rom_values[hfs2->current_state]); + me_progress_rom_values[hfs2->current_state]); break;
case ME_HFS2_PHASE_BUP: /* Bringup Phase */ if (hfs2->current_state < ARRAY_SIZE(me_progress_bup_values) && me_progress_bup_values[hfs2->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_bup_values[hfs2->current_state]); + me_progress_bup_values[hfs2->current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); break; @@ -194,7 +194,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2) if (hfs2->current_state < ARRAY_SIZE(me_progress_policy_values) && me_progress_policy_values[hfs2->current_state]) printk(BIOS_DEBUG, "%s", - me_progress_policy_values[hfs2->current_state]); + me_progress_policy_values[hfs2->current_state]); else printk(BIOS_DEBUG, "0x%02x", hfs2->current_state); break; @@ -208,7 +208,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2)
default: printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", - hfs2->progress_code, hfs2->current_state); + hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); #endif diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 4283ca1..0671fc0 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -63,7 +63,7 @@ typedef struct { u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ - u8 pcnt; /* 0x2d - Processor Count */ + u8 pcnt; /* 0x2d - Processor Count */ u8 rsvd4[4]; /* Super I/O & CMOS config */ u8 natp; /* 0x32 - SIO type */ diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 58c68cd..991ed09 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -42,7 +42,7 @@ int pch_silicon_revision(void)
if (pch_revision_id < 0) pch_revision_id = pci_read_config8(pch_get_lpc_device(), - PCI_REVISION_ID); + PCI_REVISION_ID); return pch_revision_id; }
@@ -52,7 +52,7 @@ int pch_silicon_type(void)
if (pch_type < 0) pch_type = pci_read_config8(pch_get_lpc_device(), - PCI_DEVICE_ID + 1); + PCI_DEVICE_ID + 1); return pch_type; }
@@ -67,7 +67,7 @@ u16 get_pmbase(void)
if (!pmbase) pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; + PMBASE) & 0xfffc; return pmbase; }
@@ -77,7 +77,7 @@ u16 get_gpiobase(void)
if (!gpiobase) gpiobase = pci_read_config16(pch_get_lpc_device(), - GPIOBASE) & 0xfffc; + GPIOBASE) & 0xfffc; return gpiobase; }
@@ -314,7 +314,7 @@ static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) u32 old_rpfn = new_rpfn;
printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", - old_fn, new_fn); + old_fn, new_fn);
new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn));
@@ -339,15 +339,15 @@ static void pch_pcie_devicetree_update(void)
/* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, - RPFN_FNGET(new_rpfn, + RPFN_FNGET(new_rpfn, PCI_FUNC(dev->path.pci.devfn)));
if (dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, - "PCH: PCIe map %02x.%1x -> %02x.%1x\n", - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn), - PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); + "PCH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), + PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
dev->path.pci.devfn = new_devfn; } @@ -378,7 +378,7 @@ static void pch_pcie_enable(device_t dev)
if (config->pcie_port_coalesce) printk(BIOS_INFO, - "PCH: PCIe Root Port coalescing is enabled\n"); + "PCH: PCIe Root Port coalescing is enabled\n"); }
if (!dev->enabled) { @@ -452,7 +452,7 @@ static void pch_pcie_enable(device_t dev) */ if (PCI_FUNC(dev->path.pci.devfn) == 7) { printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", - RCBA32(RPFN), new_rpfn); + RCBA32(RPFN), new_rpfn); RCBA32(RPFN) = new_rpfn;
/* Update static devictree with new function numbers */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6ee81d1..24a2757 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -87,18 +87,18 @@ void intel_pch_finalize_smm(void);
/* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 -#define RCBA_REG_SIZE_16 0x8000 -#define RCBA_REG_SIZE_32 0x0000 +#define RCBA_REG_SIZE_16 0x8000 +#define RCBA_REG_SIZE_32 0x0000 #define RCBA_COMMAND_MASK 0x000f -#define RCBA_COMMAND_SET 0x0001 -#define RCBA_COMMAND_READ 0x0002 -#define RCBA_COMMAND_RMW 0x0003 -#define RCBA_COMMAND_END 0x0007 +#define RCBA_COMMAND_SET 0x0001 +#define RCBA_COMMAND_READ 0x0002 +#define RCBA_COMMAND_RMW 0x0003 +#define RCBA_COMMAND_END 0x0007
#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \ - { .command = command_, \ - .reg = reg_, \ - .mask = mask_, \ + { .command = command_, \ + .reg = reg_, \ + .mask = mask_, \ .or_value = or_value_ \ } #define RCBA_SET_REG_32(reg_, value_) \ @@ -183,7 +183,7 @@ void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); + const struct rcba_config_instruction *rcba_config); #endif /* * get GPIO pin value @@ -214,9 +214,9 @@ void set_gpio(int gpio_num, int value); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0)
/* Power Management Control and Status */ #define PCH_PCS 0x84 @@ -246,7 +246,7 @@ void set_gpio(int gpio_num, int value);
#define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -285,48 +285,48 @@ void set_gpio(int gpio_num, int value); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -449,7 +449,7 @@ void set_gpio(int gpio_num, int value); #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \ - RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) + RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) @@ -492,13 +492,13 @@ void set_gpio(int gpio_num, int value); #define RPFN 0x0404 /* 32bit */
/* Root Port configuratinon space hide */ -#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) +#define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) /* Get the function number assigned to a Root Port */ -#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) +#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) /* Set the function number for a Root Port */ -#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) +#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) /* Root Port function number mask */ -#define RPFN_FNMASK(port) (7 << ((port) * 4)) +#define RPFN_FNMASK(port) (7 << ((port) * 4))
#define TRSR 0x1e00 /* 8bit */ #define TRCR 0x1e10 /* 64bit */ @@ -537,8 +537,8 @@ void set_gpio(int gpio_num, int value); #define IOBPS 0x2338 #define IOBPS_READY 0x0001 #define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 #define IOBPS_WRITE 0x0700 #define IOBPU 0x233a #define IOBPU_MAGIC 0xf000 @@ -630,31 +630,31 @@ void set_gpio(int gpio_num, int value);
/* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -662,35 +662,35 @@ void set_gpio(int gpio_num, int value); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_STS_2 0x24 #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define GPE0_EN_2 0x2c #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -699,7 +699,7 @@ void set_gpio(int gpio_num, int value); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e @@ -765,19 +765,19 @@ void set_gpio(int gpio_num, int value);
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
-#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ +#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x3808 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_FADDR 0x3808 /* SPI flash address */ +#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */
#endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */ diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a3b84e3..ba75897 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -129,7 +129,7 @@ static void pch_pcie_pm_early(struct device *dev) /* Set slot power limit as configured above */ reg32 = pci_read_config32(dev, 0x54); reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */ - reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ + reg32 &= ~(0xff << 7); /* 14:7 = Slot power limit */ reg32 |= (slot_power_limit << 7); pci_write_config32(dev, 0x54, reg32); #endif @@ -206,13 +206,13 @@ static void pci_init(struct device *dev)
#ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif
/* Clear errors in status registers */ diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c index 429aad0..9eafcb6 100644 --- a/src/southbridge/intel/lynxpoint/reset.c +++ b/src/southbridge/intel/lynxpoint/reset.c @@ -23,10 +23,10 @@
void soft_reset(void) { - outb(0x04, 0xcf9); + outb(0x04, 0xcf9); }
void hard_reset(void) { - outb(0x06, 0xcf9); + outb(0x06, 0xcf9); } diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 8912865..da815e2 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -145,7 +145,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32);
/* Setup register 9Ch */ - reg16 = 0; /* Disable alternate ID */ + reg16 = 0; /* Disable alternate ID */ reg16 = 1 << 5; /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16);
@@ -163,7 +163,7 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -309,7 +309,7 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations sata_pci_ops = { - .set_subsystem = sata_set_subsystem, + .set_subsystem = sata_set_subsystem, };
static struct device_operations sata_ops = { @@ -325,7 +325,7 @@ static struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, /* Desktop */ 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, /* Mobile */ - 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* Low Power */ 0 };
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index 4786d8b..16853f9 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -74,7 +74,7 @@ static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = smbus_set_subsystem, };
static void smbus_read_resources(device_t dev) diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index add53ed..e99c34e 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -73,37 +73,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus) { - int slot, func; - unsigned int val; - unsigned char hdr; - - for (slot = 0; slot < 0x20; slot++) { - for (func = 0; func < 8; func++) { - u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); - - val = pci_read_config32(dev, PCI_VENDOR_ID); - - if (val == 0xffffffff || val == 0x00000000 || - val == 0x0000ffff || val == 0xffff0000) - continue; - - /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); - - /* If this is a bridge, then follow it. */ - hdr = pci_read_config8(dev, PCI_HEADER_TYPE); - hdr &= 0x7f; - if (hdr == PCI_HEADER_TYPE_BRIDGE || - hdr == PCI_HEADER_TYPE_CARDBUS) { - unsigned int buses; - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - busmaster_disable_on_bus((buses >> 8) & 0xff); - } - } - } + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } }
/* Handler for EHCI controller on entry to S3/S4/S5 */ @@ -394,7 +394,7 @@ static void southbridge_smi_apmc(void) case APM_CNT_GNVS_UPDATE: if (smm_initialized) { printk(BIOS_DEBUG, - "SMI#: SMM structures already initialized!\n"); + "SMI#: SMM structures already initialized!\n"); return; } state = smi_apmc_find_state_save(reg8); @@ -486,7 +486,7 @@ static void southbridge_smi_tco(void) */ printk(BIOS_DEBUG, "Switching back to RO\n"); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, - (bios_cntl & ~1)); + (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -548,13 +548,13 @@ static void southbridge_smi_monitor(void) }
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", - trap_cycle & 0xfffc); + trap_cycle & 0xfffc); for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", - (trap_cycle & (1 << 24)) ? "read" : "write"); + (trap_cycle & (1 << 24)) ? "read" : "write");
if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ @@ -624,8 +624,8 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occured, but no " - "handler available.\n", i); + "SMI_STS[%d] occured, but no " + "handler available.\n", i); } } } diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index 5501efc..95aa94d 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -173,7 +173,7 @@ static u8 readb_(const void *addr) { u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -181,7 +181,7 @@ static u16 readw_(const void *addr) { u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -189,7 +189,7 @@ static u32 readl_(const void *addr) { u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + v, ((unsigned) addr & 0xffff) - 0xf020); return v; }
@@ -197,21 +197,21 @@ static void writeb_(u8 b, const void *addr) { write8((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writew_(u16 b, const void *addr) { write16((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
static void writel_(u32 b, const void *addr) { write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); + b, ((unsigned) addr & 0xffff) - 0xf020); }
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ diff --git a/src/southbridge/intel/pxhd/bridge.c b/src/southbridge/intel/pxhd/bridge.c index 1134f8f..9591fee 100644 --- a/src/southbridge/intel/pxhd/bridge.c +++ b/src/southbridge/intel/pxhd/bridge.c @@ -75,51 +75,51 @@ static void pcix_init(device_t dev)
/* Enable memory write and invalidate ??? */ byte = pci_read_config8(dev, 0x04); - byte |= 0x10; - pci_write_config8(dev, 0x04, byte); + byte |= 0x10; + pci_write_config8(dev, 0x04, byte);
/* Set drive strength */ word = pci_read_config16(dev, 0xe0); - word = 0x0404; - pci_write_config16(dev, 0xe0, word); + word = 0x0404; + pci_write_config16(dev, 0xe0, word); word = pci_read_config16(dev, 0xe4); - word = 0x0404; - pci_write_config16(dev, 0xe4, word); + word = 0x0404; + pci_write_config16(dev, 0xe4, word);
/* Set impedance */ word = pci_read_config16(dev, 0xe8); - word = 0x0404; - pci_write_config16(dev, 0xe8, word); + word = 0x0404; + pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */ word = pci_read_config16(dev, 0x4c); - word |= 1; - pci_write_config16(dev, 0x4c, word); + word |= 1; + pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */ word = pci_read_config16(dev, 0xa8); - pci_write_config16(dev, 0xaa, word); + pci_write_config16(dev, 0xaa, word); word = pci_read_config16(dev, 0xac); - pci_write_config16(dev, 0xae, word); + pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */ /* system error enable */ dword = pci_read_config32(dev, 0x04); - dword |= (1<<8); - pci_write_config32(dev, 0x04, dword); + dword |= (1<<8); + pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */ dword = pci_read_config32(dev, 0x3c); - dword |= (3<<16); - pci_write_config32(dev, 0x3c, dword); + dword |= (3<<16); + pci_write_config32(dev, 0x3c, dword);
/* NMI enable */ nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if(nmi_option) { dword = pci_read_config32(dev, 0x44); - dword |= (1<<0); - pci_write_config32(dev, 0x44, dword); + dword |= (1<<0); + pci_write_config32(dev, 0x44, dword); }
/* Set up CRC flood enable */ @@ -138,25 +138,25 @@ static void pcix_init(device_t dev) }
static struct device_operations pcix_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcix_init, - .scan_bus = pxhd_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = 0, + .init = pcix_init, + .scan_bus = pxhd_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, };
static const struct pci_driver pcix_driver __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0329, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0329, };
static const struct pci_driver pcix_driver2 __pci_driver = { - .ops = &pcix_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x032a, + .ops = &pcix_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x032a, };
static void ioapic_init(device_t dev) @@ -184,23 +184,23 @@ static struct pci_operations intel_ops_pci = {
static struct device_operations ioapic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ioapic_init, - .scan_bus = 0, - .enable = pxhd_enable, - .ops_pci = &intel_ops_pci, + .init = ioapic_init, + .scan_bus = 0, + .enable = pxhd_enable, + .ops_pci = &intel_ops_pci, };
static const struct pci_driver ioapic_driver __pci_driver = { - .ops = &ioapic_ops, + .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0326,
};
static const struct pci_driver ioapic2_driver __pci_driver = { - .ops = &ioapic_ops, + .ops = &ioapic_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x0327,
diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index 432fb8d..08a5dad 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -51,8 +51,8 @@ config CMC_FILE binary.
config HPET_MIN_TICKS - hex - default 0x80 + hex + default 0x80
endif
diff --git a/src/southbridge/intel/sch/acpi/globalnvs.asl b/src/southbridge/intel/sch/acpi/globalnvs.asl index 5ac1c83..dedfd1c 100644 --- a/src/southbridge/intel/sch/acpi/globalnvs.asl +++ b/src/southbridge/intel/sch/acpi/globalnvs.asl @@ -50,7 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x0f - LID state (open = 1) PWRS, 8, // 0x10 - Power State (AC = 1) DBGS, 8, // 0x11 - Debug State - LINX, 8, // 0x12 - Linux OS + LINX, 8, // 0x12 - Linux OS DCKN, 8, // 0x13 - PCIe docking state /* Thermal policy */ Offset (0x14), diff --git a/src/southbridge/intel/sch/acpi/sch.asl b/src/southbridge/intel/sch/acpi/sch.asl index 26f938e..c5bc7ed 100644 --- a/src/southbridge/intel/sch/acpi/sch.asl +++ b/src/southbridge/intel/sch/acpi/sch.asl @@ -36,7 +36,7 @@ Scope() // ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) // this doesn't work as ACPI initializes regions and packages first, devices second. // use dynamic operation region? if so, how? XXX - //OperationRegion(PMIO, SystemIO, And(_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80) + //OperationRegion(PMIO, SystemIO, And(_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80) OperationRegion(PMIO, SystemIO, 0x500, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) { diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c index 9c77937..406236d 100644 --- a/src/southbridge/intel/sch/audio.c +++ b/src/southbridge/intel/sch/audio.c @@ -274,7 +274,7 @@ static void sch_audio_init(struct device *dev)
if (codec_mask) { printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n", - codec_mask); + codec_mask); codecs_init(dev, base, codec_mask); } else { /* No audio codecs found disable HD audio controller */ @@ -286,7 +286,7 @@ static void sch_audio_init(struct device *dev) }
static void sch_audio_set_subsystem(device_t dev, unsigned vendor, - unsigned device) + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c index 0a12987..e6665e9 100644 --- a/src/southbridge/intel/sch/smbus.c +++ b/src/southbridge/intel/sch/smbus.c @@ -57,7 +57,7 @@ static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device) }
static struct pci_operations smbus_pci_ops = { - .set_subsystem = smbus_set_subsystem, + .set_subsystem = smbus_set_subsystem, };
static struct device_operations smbus_ops = { diff --git a/src/southbridge/intel/sch/smbus.h b/src/southbridge/intel/sch/smbus.h index 058c4b3..f9a6d17 100644 --- a/src/southbridge/intel/sch/smbus.h +++ b/src/southbridge/intel/sch/smbus.h @@ -52,7 +52,7 @@ static int smbus_wait_until_done(u16 smbus_base) }
static int do_smbus_read_byte(unsigned smbus_base, unsigned device, - unsigned address) + unsigned address) { unsigned char global_status_register; unsigned char byte; diff --git a/src/southbridge/intel/sch/smi.c b/src/southbridge/intel/sch/smi.c index 08733a7..cdfb194 100644 --- a/src/southbridge/intel/sch/smi.c +++ b/src/southbridge/intel/sch/smi.c @@ -33,11 +33,11 @@ extern unsigned char _binary_smm_size;
/* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* ICH7 */ #define PM1_STS 0x00 @@ -52,20 +52,20 @@ extern unsigned char _binary_smm_size; #define GPE0_STS 0x28 #define GPE0_EN 0x2c #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 5074138..d9e924d 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -29,11 +29,11 @@
/* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* ICH7 */ #define PM1_STS 0x00 @@ -48,20 +48,20 @@ #define GPE0_STS 0x28 #define GPE0_EN 0x2c #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index b6f718e..9954c5a 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -39,7 +39,7 @@ config CK804_NUM default 1
config HPET_MIN_TICKS - hex - default 0xfa + hex + default 0xfa
endif diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c index 8b0e0bb..1818208 100644 --- a/src/southbridge/nvidia/ck804/ac97.c +++ b/src/southbridge/nvidia/ck804/ac97.c @@ -27,32 +27,32 @@
static struct device_operations ac97audio_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + // .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver ac97audio_driver __pci_driver = { - .ops = &ac97audio_ops, + .ops = &ac97audio_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_ACI, };
static struct device_operations ac97modem_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + // .enable = ck804_enable, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver ac97modem_driver __pci_driver = { - .ops = &ac97modem_ops, + .ops = &ac97modem_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_MCI, }; diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c index 353a4bd..cc63e74 100644 --- a/src/southbridge/nvidia/ck804/ck804.c +++ b/src/southbridge/nvidia/ck804/ck804.c @@ -44,7 +44,7 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn) u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if ((id != (PCI_VENDOR_ID_NVIDIA | - (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) + (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) && (id != (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_CK804_PRO << 16))) && (id != (PCI_VENDOR_ID_NVIDIA | diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 84b6bfb..5d1ed0d 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -63,7 +63,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 - * 16 4 :4 + * 16 4 :4 */
#if CONFIG_CK804_NUM > 1 diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 9ba98c9..64a9953 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -61,7 +61,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 - * 16 4 :4 + * 16 4 :4 */
#define CK804_CHIP_REV 3 @@ -119,7 +119,7 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, }
static void ck804_early_setup(unsigned ck804_num, unsigned *busn, - unsigned *io_base) + unsigned *io_base) { static const unsigned int ctrl_conf_master[] = { RES_PCI_IO, PCI_ADDR(0, 1, 2, 0x8c), 0xffff0000, 0x00009880, @@ -302,17 +302,17 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, /* SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 */ /* CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 */ setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0x40, - io_base[j] + ANACTRL_IO_BASE + 0x44, - io_base[j] + ANACTRL_IO_BASE + 0x48, - pcie_ss_tbl, 64); + io_base[j] + ANACTRL_IO_BASE + 0x44, + io_base[j] + ANACTRL_IO_BASE + 0x48, + pcie_ss_tbl, 64); setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xb0, - io_base[j] + ANACTRL_IO_BASE + 0xb4, - io_base[j] + ANACTRL_IO_BASE + 0xb8, - sata_ss_tbl, 64); + io_base[j] + ANACTRL_IO_BASE + 0xb4, + io_base[j] + ANACTRL_IO_BASE + 0xb8, + sata_ss_tbl, 64); setup_ss_table(io_base[j] + ANACTRL_IO_BASE + 0xc0, - io_base[j] + ANACTRL_IO_BASE + 0xc4, - io_base[j] + ANACTRL_IO_BASE + 0xc8, - cpu_ss_tbl, 64); + io_base[j] + ANACTRL_IO_BASE + 0xc4, + io_base[j] + ANACTRL_IO_BASE + 0xc8, + cpu_ss_tbl, 64); } }
diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index a2ba295..bf42ef3 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -27,15 +27,15 @@
static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + .init = 0, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver ht_driver __pci_driver = { - .ops = &ht_ops, + .ops = &ht_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_HT, }; diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c index 1750a2a..e5923e9 100644 --- a/src/southbridge/nvidia/ck804/ide.c +++ b/src/southbridge/nvidia/ck804/ide.c @@ -67,16 +67,16 @@ static void ide_init(struct device *dev)
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, + .init = ide_init, + .scan_bus = 0, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_IDE, }; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b3a9b00..67a82f6 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -139,7 +139,7 @@ static void lpc_init(device_t dev) dword = inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); + (on * 12) + (on >> 1), (on & 1) * 5); } #if 0 /* Enable Port 92 fast reset (default is enabled). */ @@ -314,44 +314,44 @@ static void ck804_lpc_enable_resources(device_t dev)
static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, - .set_resources = ck804_lpc_set_resources, + .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, + .init = lpc_init, + .scan_bus = scan_static_bus, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_LPC, };
static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, };
#if CK804_CHIP_REV == 1 static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_ops, + .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, }; #else static struct device_operations lpc_slave_ops = { .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = lpc_slave_init, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, + .init = lpc_slave_init, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, + .ops = &lpc_slave_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, }; diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index 3dccb8e..0b8ba58 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -40,7 +40,7 @@ static void nic_init(struct device *dev) base = (unsigned long)res->base;
#define NvRegPhyInterface 0xC0 -#define PHY_RGMII 0x10000000 +#define PHY_RGMII 0x10000000
write32(base + NvRegPhyInterface, PHY_RGMII);
@@ -56,7 +56,7 @@ static void nic_init(struct device *dev) /* Read MAC address from EEPROM at first. */ struct device *dev_eeprom; dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); + conf->mac_eeprom_addr);
if (dev_eeprom) { /* If that is valid we will use that. */ @@ -115,22 +115,22 @@ static void nic_init(struct device *dev)
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, + .init = nic_init, + .scan_bus = 0, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver nic_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, };
static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, }; diff --git a/src/southbridge/nvidia/ck804/pci.c b/src/southbridge/nvidia/ck804/pci.c index 9257980..41f96ac 100644 --- a/src/southbridge/nvidia/ck804/pci.c +++ b/src/southbridge/nvidia/ck804/pci.c @@ -80,15 +80,15 @@ static void pci_init(struct device *dev)
static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, - .scan_bus = pci_scan_bridge, - // .enable = ck804_enable, + .init = pci_init, + .scan_bus = pci_scan_bridge, + // .enable = ck804_enable, };
static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, + .ops = &pci_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI, }; diff --git a/src/southbridge/nvidia/ck804/pcie.c b/src/southbridge/nvidia/ck804/pcie.c index 5e1c449..1dfcb2d 100644 --- a/src/southbridge/nvidia/ck804/pcie.c +++ b/src/southbridge/nvidia/ck804/pcie.c @@ -38,15 +38,15 @@ static void pcie_init(struct device *dev)
static struct device_operations pcie_ops = { .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - // .enable = ck804_enable, + .init = pcie_init, + .scan_bus = pci_scan_bridge, + // .enable = ck804_enable, };
static const struct pci_driver pcie_driver __pci_driver = { - .ops = &pcie_ops, + .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_PCI_E, }; diff --git a/src/southbridge/nvidia/ck804/sata.c b/src/southbridge/nvidia/ck804/sata.c index bcf4200..4b624fc 100644 --- a/src/southbridge/nvidia/ck804/sata.c +++ b/src/southbridge/nvidia/ck804/sata.c @@ -165,22 +165,22 @@ static void sata_init(struct device *dev)
static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - // .enable = ck804_enable, - .init = sata_init, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + // .enable = ck804_enable, + .init = sata_init, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA0, };
static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, + .ops = &sata_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, }; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index dd6a5f4..ca573ca 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -93,17 +93,17 @@ static struct smbus_bus_operations lops_smbus_bus = {
static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, - // .enable = ck804_enable, - .ops_pci = &ck804_pci_ops, - .ops_smbus_bus = &lops_smbus_bus, + .init = 0, + .scan_bus = scan_static_bus, + // .enable = ck804_enable, + .ops_pci = &ck804_pci_ops, + .ops_smbus_bus = &lops_smbus_bus, };
static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, + .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, }; diff --git a/src/southbridge/nvidia/ck804/smbus.h b/src/southbridge/nvidia/ck804/smbus.h index 3aac3d8..825131c 100644 --- a/src/southbridge/nvidia/ck804/smbus.h +++ b/src/southbridge/nvidia/ck804/smbus.h @@ -112,7 +112,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) }
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, - unsigned char val) + unsigned char val) { unsigned global_status_register;
@@ -151,7 +151,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, #endif
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, - unsigned address) + unsigned address) { unsigned char global_status_register, byte;
@@ -191,7 +191,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, }
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, - unsigned address, unsigned char val) + unsigned address, unsigned char val) { unsigned global_status_register;
diff --git a/src/southbridge/nvidia/ck804/usb.c b/src/southbridge/nvidia/ck804/usb.c index 046028b..a3de246 100644 --- a/src/southbridge/nvidia/ck804/usb.c +++ b/src/southbridge/nvidia/ck804/usb.c @@ -48,16 +48,16 @@ static void usb1_init(struct device *dev)
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb1_init, - // .enable = ck804_enable, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + .init = usb1_init, + // .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver usb_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_USB, }; diff --git a/src/southbridge/nvidia/ck804/usb2.c b/src/southbridge/nvidia/ck804/usb2.c index 05632a2..2c95072 100644 --- a/src/southbridge/nvidia/ck804/usb2.c +++ b/src/southbridge/nvidia/ck804/usb2.c @@ -36,16 +36,16 @@ static void usb2_init(struct device *dev)
static struct device_operations usb2_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb2_init, - // .enable = ck804_enable, - .scan_bus = 0, - .ops_pci = &ck804_pci_ops, + .init = usb2_init, + // .enable = ck804_enable, + .scan_bus = 0, + .ops_pci = &ck804_pci_ops, };
static const struct pci_driver usb2_driver __pci_driver = { - .ops = &usb2_ops, + .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_CK804_USB2, }; diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c index 67433d3..677f76c 100644 --- a/src/southbridge/nvidia/mcp55/azalia.c +++ b/src/southbridge/nvidia/mcp55/azalia.c @@ -226,7 +226,7 @@ static void azalia_init(struct device *dev) mdelay(1); reg8 = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "Azalia: codec type: %s\n", - (reg8 & (1 << 1)) ? "Azalia" : "AC97"); + (reg8 & (1 << 1)) ? "Azalia" : "AC97");
reg8 = pci_read_config8(dev, 0x40); /* Audio control */ reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */ diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..f1bb7ca 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -28,7 +28,7 @@ static unsigned get_sbdn(unsigned bus)
/* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, - PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus); + PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f; } diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4b1443c..c1163c2 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -151,8 +151,8 @@ static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, }
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, - unsigned *devn, unsigned *io_base, - unsigned *pci_e_x) + unsigned *devn, unsigned *io_base, + unsigned *pci_e_x) { static const unsigned int ctrl_conf_1[] = { RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index 6be8485..7e121fd 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -88,7 +88,7 @@ static inline int smbusx_read_byte(unsigned smb_index, unsigned device, }
static inline int smbusx_write_byte(unsigned smb_index, unsigned device, - unsigned address, unsigned char val) + unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8), device, address, val); diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c index 633221c..7934dc3 100644 --- a/src/southbridge/nvidia/mcp55/ht.c +++ b/src/southbridge/nvidia/mcp55/ht.c @@ -30,11 +30,11 @@
static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, - .ops_pci = &mcp55_pci_ops, + .init = 0, + .scan_bus = 0, + .ops_pci = &mcp55_pci_ops, };
static const struct pci_driver ht_driver __pci_driver = { diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c index 23d4db1..73398d5 100644 --- a/src/southbridge/nvidia/mcp55/ide.c +++ b/src/southbridge/nvidia/mcp55/ide.c @@ -68,12 +68,12 @@ static void ide_init(struct device *dev)
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, + .init = ide_init, + .scan_bus = 0, +// .enable = mcp55_enable, + .ops_pci = &mcp55_pci_ops, };
static const struct pci_driver ide_driver __pci_driver = { diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 585232d..07f4fee 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -117,7 +117,7 @@ static void lpc_init(device_t dev) dword = inl(pm10_bar + 0x10); on = 8 - on; printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", - (on * 12) + (on >> 1), (on & 1) * 5); + (on * 12) + (on >> 1), (on & 1) * 5); }
#if 0 @@ -228,7 +228,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) break; } if ((base == 0x290) - || (base >= 0x400)) { + || (base >= 0x400)) { /* Only 4 var; compact them? */ if (var_num >= 4) continue; @@ -252,12 +252,12 @@ static void mcp55_lpc_enable_resources(device_t dev)
static struct device_operations lpc_ops = { .read_resources = mcp55_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = mcp55_lpc_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, + .init = lpc_init, + .scan_bus = scan_static_bus, +// .enable = mcp55_enable, + .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { PCI_DEVICE_ID_NVIDIA_MCP55_LPC, @@ -277,11 +277,11 @@ static const struct pci_driver lpc_driver __pci_driver = {
static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = lpc_slave_init, -// .enable = mcp55_enable, - .ops_pci = &mcp55_pci_ops, + .init = lpc_slave_init, +// .enable = mcp55_enable, + .ops_pci = &mcp55_pci_ops, };
static const struct pci_driver lpc_driver_slave __pci_driver = { diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index 86468fd..9b0b68a 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -92,7 +92,7 @@ static void phy_detect(u32 base) continue; id |= ((val & 0xffff) << 16); printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", - id, i); + id, i); // if ((id == 0xe0180000) || (id == 0x0032cc00)) break; } diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c index 2e5e360..d0cd3bd 100644 --- a/src/southbridge/rdc/r8610/bootblock.c +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -21,7 +21,7 @@ #include <device/pci_def.h>
static void bootblock_southbridge_init(void) { - uint32_t tmp; + uint32_t tmp; tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40); /* decode all flash ranges */ pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000); diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c index eb2c21e..a950cc8 100644 --- a/src/southbridge/rdc/r8610/r8610.c +++ b/src/southbridge/rdc/r8610/r8610.c @@ -102,12 +102,12 @@ static void southbridge_init(struct device *dev)
static struct device_operations r8610_sb_ops = { .read_resources = r8610_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, .scan_bus = scan_static_bus, - .enable = 0, - .ops_pci = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 0efcafa..e6ce698 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -211,20 +211,20 @@ static void rl5c476_set_subsystem(device_t dev, unsigned vendor, unsigned device }
static struct pci_operations rl5c476_pci_ops = { - .set_subsystem = rl5c476_set_subsystem, + .set_subsystem = rl5c476_set_subsystem, };
static struct device_operations ricoh_rl5c476_ops = { .read_resources = rl5c476_read_resources, - .set_resources = rl5c476_set_resources, + .set_resources = rl5c476_set_resources, .enable_resources = cardbus_enable_resources, - .init = rl5c476_init, - .scan_bus = pci_scan_bridge, - .ops_pci = &rl5c476_pci_ops, + .init = rl5c476_init, + .scan_bus = pci_scan_bridge, + .ops_pci = &rl5c476_pci_ops, };
static const struct pci_driver ricoh_rl5c476_driver __pci_driver = { - .ops = &ricoh_rl5c476_ops, + .ops = &ricoh_rl5c476_ops, .vendor = PCI_VENDOR_ID_RICOH, .device = PCI_DEVICE_ID_RICOH_RL5C476, }; @@ -237,5 +237,5 @@ static void southbridge_init(device_t dev)
struct chip_operations southbridge_ricoh_rl5c476_ops = { CHIP_NAME("Ricoh RL5C476 CardBus Controller") - .enable_dev = southbridge_init, + .enable_dev = southbridge_init, }; diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index 0fd8eb0..cdfe118 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -188,7 +188,7 @@ static u32 verb_data[] = {
static unsigned find_verb(u32 viddid, u32 **verb) { - if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -240,48 +240,48 @@ static void codecs_init(u32 base, u32 codec_mask)
static void aza_init(struct device *dev) { - u32 base; - struct resource *res; - u32 codec_mask; + u32 base; + struct resource *res; + u32 codec_mask;
- print_debug("AZALIA_INIT:---------->\n"); + print_debug("AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS7502_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); - temp8 &= SiS_SiS7502_init[i][1]; - temp8 |= SiS_SiS7502_init[i][2]; - pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); - i++; - }; + u8 temp8; + int i=0; + while(SiS_SiS7502_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); + temp8 &= SiS_SiS7502_init[i][1]; + temp8 |= SiS_SiS7502_init[i][2]; + pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); + i++; + }; } //-----------------------------------------------------------
- // put audio to D0 state - pci_write_config8(dev, 0x54,0x00); + // put audio to D0 state + pci_write_config8(dev, 0x54,0x00);
#if DEBUG_AZA { - int i; - - print_debug("****** Azalia PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + int i; + + print_debug("****** Azalia PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); } #endif
@@ -299,7 +299,7 @@ static void aza_init(struct device *dev) codecs_init(base, codec_mask); }
- print_debug("AZALIA_INIT:<----------\n"); + print_debug("AZALIA_INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 4d34923..a320a0f 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -505,12 +505,12 @@ static const uint8_t SiS_SiS1183_init[44][3]={ {0x00, 0x00, 0x00} //End of table };
-/* In => Share Memory size - => 00h : 0MBytes - => 02h : 32MBytes - => 03h : 64MBytes - => 04h : 128MBytes - => Others: Reserved +/* In => Share Memory size + => 00h : 0MBytes + => 02h : 32MBytes + => 03h : 64MBytes + => 04h : 128MBytes + => Others: Reserved */ static void Init_Share_Memory(uint8_t ShareSize) { @@ -520,32 +520,32 @@ static void Init_Share_Memory(uint8_t ShareSize) pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5)); }
-/* In: => Aperture size - => 00h : 32MBytes - => 01h : 64MBytes - => 02h : 128MBytes - => 03h : 256MBytes - => 04h : 512MBytes - => Others: Reserved +/* In: => Aperture size + => 00h : 32MBytes + => 01h : 64MBytes + => 02h : 128MBytes + => 03h : 256MBytes + => 04h : 512MBytes + => Others: Reserved */ static void Init_Aper_Size(uint8_t AperSize) { - device_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; + device_t dev; + uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); - pci_write_config8(dev, 0x90, AperSize << 1); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); + pci_write_config8(dev, 0x90, AperSize << 1);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]); }
static void sis_init_stage1(void) { - device_t dev; - uint8_t temp8; - int i; - uint8_t GUI_En; + device_t dev; + uint8_t temp8; + int i; + uint8_t GUI_En;
// SiS_Chipset_Initialization // ========================== NB ============================= @@ -612,56 +612,56 @@ static void sis_init_stage2(void)
// ========================== NB_AGP ============================= - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit - pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit + pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); - i=0; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0); + i=0;
- while(SiS_NBAGP_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); - temp8 &= SiS_NBAGP_init[i][1]; - temp8 |= SiS_NBAGP_init[i][2]; - pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); - i++; - }; + while(SiS_NBAGP_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]); + temp8 &= SiS_NBAGP_init[i][1]; + temp8 |= SiS_NBAGP_init[i][2]; + pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8); + i++; + };
/** * Share Memory size - * => 00h : 0MBytes - * => 02h : 32MBytes - * => 03h : 64MBytes - * => 04h : 128MBytes - * => Others: Reserved + * => 00h : 0MBytes + * => 02h : 32MBytes + * => 03h : 64MBytes + * => 04h : 128MBytes + * => Others: Reserved * * Aperture size - * => 00h : 32MBytes - * => 01h : 64MBytes - * => 02h : 128MBytes - * => 03h : 256MBytes - * => 04h : 512MBytes - * => Others: Reserved + * => 00h : 32MBytes + * => 01h : 64MBytes + * => 02h : 128MBytes + * => 03h : 256MBytes + * => 04h : 512MBytes + * => Others: Reserved */
- Init_Share_Memory(0x02); //0x02 : 32M - Init_Aper_Size(0x01); //0x1 : 64M + Init_Share_Memory(0x02); //0x02 : 32M + Init_Aper_Size(0x01); //0x1 : 64M
// ========================== NB =============================
- printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); - msr = rdmsr(0xC001001A); + printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); + msr = rdmsr(0xC001001A); printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo );
- temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; - temp16=0x0001<<(temp16-1); - temp16<<=8; + temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; + temp16=0x0001<<(temp16-1); + temp16<<=8;
- printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); - pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); - pci_write_config8(dev, 0x7F, 0x08); // ACPI Base - outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function + printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); + pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); + pci_write_config8(dev, 0x7F, 0x08); // ACPI Base + outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
// ========================== ACPI ============================= i=0; @@ -699,7 +699,7 @@ static void sis_init_stage2(void) * bit3 : Azalia Controller Enable (0=enable) */ pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable - temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 + temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 outb(temp8, 0x878); // ACPI select AC97 or HDA controller printk(BIOS_DEBUG, "Audio select %x\n",inb(0x878));
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index fee7209..6167f60 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -105,15 +105,15 @@ print_debug("IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS5513_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); - temp8 &= SiS_SiS5513_init[i][1]; - temp8 |= SiS_SiS5513_init[i][2]; - pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); + temp8 &= SiS_SiS5513_init[i][1]; + temp8 |= SiS_SiS5513_init[i][2]; + pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -150,21 +150,21 @@ print_debug("IDE_INIT:---------->\n");
#if DEBUG_IDE { - int i; - - print_debug("****** IDE PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + int i; + + print_debug("****** IDE PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); } #endif print_debug("IDE_INIT:<----------\n"); diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index a4db1e5..8c3fa5c 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -94,10 +94,10 @@ static void lpc_init(device_t dev) int on; int nmi_option;
- printk(BIOS_DEBUG, "LPC_INIT -------->\n"); - pc_keyboard_init(0); + printk(BIOS_DEBUG, "LPC_INIT -------->\n"); + pc_keyboard_init(0);
- lpc_usb_legacy_init(dev); + lpc_usb_legacy_init(dev); lpc_common_init(dev);
/* power after power fail */ @@ -127,33 +127,33 @@ static void lpc_init(device_t dev) (on*12)+(on>>1),(on&1)*5); }
- /* Enable Error reporting */ - /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); - byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); - - /* Set up NMI on errors */ - byte = inb(0x70); // RTC70 - byte_old = byte; - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* set NMI */ - } else { - byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW - } - if( byte != byte_old) { - outb(byte, 0x70); - } - - /* Initialize the real time clock */ - rtc_init(0); - - /* Initialize isa dma */ - isa_dma_init(); - - printk(BIOS_DEBUG, "LPC_INIT <--------\n"); + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = inb(0x70); // RTC70 + byte_old = byte; + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* set NMI */ + } else { + byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW + } + if( byte != byte_old) { + outb(byte, 0x70); + } + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + printk(BIOS_DEBUG, "LPC_INIT <--------\n"); }
static void sis966_lpc_read_resources(device_t dev) diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index 18ed75e..c38395d 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -44,11 +44,11 @@ u8 SiS_SiS191_init[6][3]={ };
-#define StatusReg 0x1 +#define StatusReg 0x1 #define SMI_READ 0x0 #define SMI_REQUEST 0x10 -#define TRUE 1 -#define FALSE 0 +#define TRUE 1 +#define FALSE 0
u16 MacAddr[3];
@@ -79,7 +79,7 @@ static void readApcMacAddr(void) printk(BIOS_DEBUG, "MAC addr in APC = "); for(i = 0x9 ; i <=0xe ; i++) { - printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); + printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } printk(BIOS_DEBUG, "\n");
@@ -96,7 +96,7 @@ static void set_apc(struct device *dev) { u16 addr; u16 i; - u8 bTmp; + u8 bTmp;
/* enable APC in south bridge sis966 D2F0 */ outl(0x80001048,0xcf8); @@ -107,7 +107,7 @@ static void set_apc(struct device *dev) addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF)); - // printf("%x - ",readMacAddrByte(0x59+i)); + // printf("%x - ",readMacAddrByte(0x59+i)); }
/* Set APC Reload */ @@ -148,12 +148,12 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
for(i=0 ; i <= LoopNum; i++) { - ulValue=read32(base+0x3c); + ulValue=read32(base+0x3c);
- if(!(ulValue & 0x0080)) //BIT_7 - break; + if(!(ulValue & 0x0080)) //BIT_7 + break;
- mdelay(100); + mdelay(100); }
mdelay(50); @@ -169,29 +169,29 @@ static unsigned long ReadEEprom( struct device *dev, u32 base, u32 Reg)
static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg) { - u32 ulValue; - u32 Read_Cmd; - u16 usData; + u32 ulValue; + u32 Read_Cmd; + u16 usData;
Read_Cmd = ((phy_reg << 11) | - (phy_addr << 6) | - SMI_READ | - SMI_REQUEST); + (phy_addr << 6) | + SMI_READ | + SMI_REQUEST);
- // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC - write32(base+0x44, Read_Cmd); + // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC + write32(base+0x44, Read_Cmd);
- // Polling SMI_REQ bit to be deasserted indicated read command completed - do - { - // Wait 20 usec before checking status + // Polling SMI_REQ bit to be deasserted indicated read command completed + do + { + // Wait 20 usec before checking status mdelay(20); - ulValue = read32(base+0x44); - } while((ulValue & SMI_REQUEST) != 0); - //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); - usData=(ulValue>>16); + ulValue = read32(base+0x44); + } while((ulValue & SMI_REQUEST) != 0); + //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); + usData=(ulValue>>16);
@@ -203,24 +203,24 @@ static int phy_read(u32 base, unsigned phy_addr, unsigned phy_reg) // If there exist a valid PHY then return TRUE, else return FALSE static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect() { - int bFoundPhy = FALSE; + int bFoundPhy = FALSE; u16 usData; - int PhyAddress = 0; + int PhyAddress = 0;
- // Scan all PHY address(0 ~ 31) to find a valid PHY - for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) - { + // Scan all PHY address(0 ~ 31) to find a valid PHY + for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) + { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
- // Found a valid PHY + // Found a valid PHY
- if((usData != 0x0) && (usData != 0xffff)) - { - bFoundPhy = TRUE; - break; - } - } + if((usData != 0x0) && (usData != 0xffff)) + { + bFoundPhy = TRUE; + break; + } + }
if(!bFoundPhy) @@ -236,31 +236,31 @@ static int phy_detect(u32 base,u16 *PhyAddr) //BOOL PHY_Detect()
static void nic_init(struct device *dev) { - int val; - u16 PhyAddr; - u32 base; - struct resource *res; + int val; + u16 PhyAddr; + u32 base; + struct resource *res;
- print_debug("NIC_INIT:---------->\n"); + print_debug("NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) ------------------------- { - u8 temp8; - int i=0; - while(SiS_SiS191_init[i][0] != 0) + u8 temp8; + int i=0; + while(SiS_SiS191_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); - temp8 &= SiS_SiS191_init[i][1]; - temp8 |= SiS_SiS191_init[i][2]; - pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]); + temp8 &= SiS_SiS191_init[i][1]; + temp8 |= SiS_SiS191_init[i][2]; + pci_write_config8(dev, SiS_SiS191_init[i][0], temp8); + i++; }; } //-----------------------------------------------------------
{ - unsigned long i; - unsigned long ulValue; + unsigned long i; + unsigned long ulValue;
res = find_resource(dev, 0x10);
@@ -270,22 +270,22 @@ static void nic_init(struct device *dev) return; } base = res->base; - printk(BIOS_DEBUG, "NIC base address %x\n",base); + printk(BIOS_DEBUG, "NIC base address %x\n",base);
if(!(val=phy_detect(base,&PhyAddr))) { - printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); + printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; }
- ulValue=read32(base + 0x38L); // check EEPROM existing + ulValue=read32(base + 0x38L); // check EEPROM existing
- if((ulValue & 0x0002)) - { + if((ulValue & 0x0002)) + {
- // read MAC address from EEPROM at first + // read MAC address from EEPROM at first
- // if that is valid we will use that + // if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL)); for(i=0;i<3;i++) { @@ -296,35 +296,35 @@ static void nic_init(struct device *dev) MacAddr[i] =ulValue & 0xFFFF;
} - }else{ - // read MAC address from firmware + }else{ + // read MAC address from firmware printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); MacAddr[0]=read16(0xffffffc0); // mac address store at here MacAddr[1]=read16(0xffffffc2); MacAddr[2]=read16(0xffffffc4); - } + }
- set_apc(dev); + set_apc(dev);
- readApcMacAddr(); + readApcMacAddr();
#if DEBUG_NIC { - int i; - - print_debug("****** NIC PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + int i; + + print_debug("****** NIC PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); }
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..f35f313 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -55,7 +55,7 @@ uint8_t SiS_SiS1183_init[68][3]={ {0x85, 0x00, 0xB3}, {0x86, 0x00, 0x72}, {0x87, 0x00, 0x40}, -{0x88, 0x00, 0xDE}, // after set mode +{0x88, 0x00, 0xDE}, // after set mode {0x89, 0x00, 0xB3}, {0x8A, 0x00, 0x72}, {0x8B, 0x00, 0x40}, @@ -116,19 +116,19 @@ static void sata_init(struct device *dev)
conf = dev->chip_info; - print_debug("SATA_INIT:---------->\n"); + print_debug("SATA_INIT:---------->\n");
//-------------- enable IDE (SiS1183) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0; while(SiS_SiS1183_init[i][0] != 0) { - temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); - temp8 &= SiS_SiS1183_init[i][1]; - temp8 |= SiS_SiS1183_init[i][2]; - pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); - i++; + temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]); + temp8 &= SiS_SiS1183_init[i][1]; + temp8 |= SiS_SiS1183_init[i][2]; + pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8); + i++; }; } //----------------------------------------------------------- @@ -149,25 +149,25 @@ for (i=0;i<10;i++){
#if DEBUG_SATA { - int i; - - print_debug("****** SATA PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + int i; + + print_debug("****** SATA PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); } #endif
- print_debug("SATA_INIT:<----------\n"); + print_debug("SATA_INIT:<----------\n");
}
diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c index 79a64f9..31946c7 100644 --- a/src/southbridge/sis/sis966/sis761.c +++ b/src/southbridge/sis/sis966/sis761.c @@ -114,15 +114,15 @@ static void sis761_init(struct device *dev)
static struct device_operations sis761_ops = { .read_resources = sis761_read_resources, - .set_resources = sis761_set_resources, + .set_resources = sis761_set_resources, .enable_resources = pci_dev_enable_resources, - .init = sis761_init, - .scan_bus = 0, - .ops_pci = 0, + .init = sis761_init, + .scan_bus = 0, + .ops_pci = 0, };
static const struct pci_driver sis761_driver __pci_driver = { - .ops = &sis761_ops, + .ops = &sis761_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS761, }; diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index c33f0fc..a970b71 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -55,12 +55,12 @@ uint8_t SiS_SiS7001_init[16][3]={
static void usb_init(struct device *dev) { - print_debug("USB 1.1 INIT:---------->\n"); + print_debug("USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) ------------------------- { - uint8_t temp8; - int i=0; + uint8_t temp8; + int i=0;
while(SiS_SiS7001_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); @@ -74,24 +74,24 @@ static void usb_init(struct device *dev)
#if DEBUG_USB { - int i; + int i;
- print_debug("****** USB 1.1 PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + print_debug("****** USB 1.1 PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); } #endif - print_debug("USB 1.1 INIT:<----------\n"); + print_debug("USB 1.1 INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 195c982..1af02ee 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -66,50 +66,50 @@ static const u8 SiS_SiS7002_init[22][3]={
static void usb2_init(struct device *dev) { - u32 base; - struct resource *res; - int i; - u8 temp8; + u32 base; + struct resource *res; + int i; + u8 temp8;
- print_debug("USB 2.0 INIT:---------->\n"); + print_debug("USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0; - while(SiS_SiS7002_init[i][0] != 0) - { - temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); - temp8 &= SiS_SiS7002_init[i][1]; - temp8 |= SiS_SiS7002_init[i][2]; - pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); - i++; - }; - - res = find_resource(dev, 0x10); - if(!res) - return; - - base = res->base; - printk(BIOS_DEBUG, "base = 0x%08x\n", base); - write32(base+0x20, 0x2); + while(SiS_SiS7002_init[i][0] != 0) + { + temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); + temp8 &= SiS_SiS7002_init[i][1]; + temp8 |= SiS_SiS7002_init[i][2]; + pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); + i++; + }; + + res = find_resource(dev, 0x10); + if(!res) + return; + + base = res->base; + printk(BIOS_DEBUG, "base = 0x%08x\n", base); + write32(base+0x20, 0x2); //-------------------------------------------------------------
#if DEBUG_USB2 - print_debug("****** USB 2.0 PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); - - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); - } - print_debug("\n"); + print_debug("****** USB 2.0 PCI config ******"); + print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + + for(i=0;i<0xff;i+=4){ + if((i%16)==0){ + print_debug("\n"); + print_debug_hex8(i); + print_debug(": "); + } + print_debug_hex32(pci_read_config32(dev,i)); + print_debug(" "); + } + print_debug("\n"); #endif - print_debug("USB 2.0 INIT:<----------\n"); + print_debug("USB 2.0 INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index a8f58e4..b2d7a49 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -61,33 +61,33 @@ static struct pci_operations ti_pci1x2y_pci_ops = {
struct device_operations southbridge_ti_pci1x2x_pciops = { .read_resources = cardbus_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = cardbus_enable_resources, - .init = ti_pci1x2y_init, - .scan_bus = 0, - .ops_pci = &ti_pci1x2y_pci_ops, + .init = ti_pci1x2y_init, + .scan_bus = 0, + .ops_pci = &ti_pci1x2y_pci_ops, };
static const struct pci_driver ti_pci1225_driver __pci_driver = { - .ops = &southbridge_ti_pci1x2x_pciops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, };
static const struct pci_driver ti_pci1420_driver __pci_driver = { - .ops = &southbridge_ti_pci1x2x_pciops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, };
static const struct pci_driver ti_pci1510_driver __pci_driver = { - .ops = &southbridge_ti_pci1x2x_pciops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1510, };
static const struct pci_driver ti_pci1520_driver __pci_driver = { - .ops = &southbridge_ti_pci1x2x_pciops, + .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 2ab383b..1dc541f 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -99,20 +99,20 @@ static void pci7420_cardbus_set_resources(device_t dev)
static struct device_operations ti_pci7420_ops = { .read_resources = pci7420_cardbus_read_resources, - .set_resources = pci7420_cardbus_set_resources, + .set_resources = pci7420_cardbus_set_resources, .enable_resources = cardbus_enable_resources, - .init = pci7420_cardbus_init, - .scan_bus = pci_scan_bridge, + .init = pci7420_cardbus_init, + .scan_bus = pci_scan_bridge, };
static const struct pci_driver ti_pci7420_driver __pci_driver = { - .ops = &ti_pci7420_ops, + .ops = &ti_pci7420_ops, .vendor = 0x104c, .device = 0xac8e, };
static const struct pci_driver ti_pci7620_driver __pci_driver = { - .ops = &ti_pci7420_ops, + .ops = &ti_pci7420_ops, .vendor = 0x104c, .device = 0xac8d, }; @@ -124,5 +124,5 @@ static void ti_pci7420_enable_dev(device_t dev)
struct chip_operations southbridge_ti_pci7420_ops = { CHIP_NAME("Texas Instruments PCI7420/7620 Cardbus Controller") - .enable_dev = ti_pci7420_enable_dev, + .enable_dev = ti_pci7420_enable_dev, }; diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index bd09c2fd..b0797f0 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -44,13 +44,13 @@ static void pci7420_firewire_init(device_t dev)
static struct device_operations ti_pci7420_firewire_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = pci7420_firewire_init, + .init = pci7420_firewire_init, };
static const struct pci_driver ti_pci7420_driver __pci_driver = { - .ops = &ti_pci7420_firewire_ops, + .ops = &ti_pci7420_firewire_ops, .vendor = 0x104c, .device = 0x802e, }; @@ -62,5 +62,5 @@ static void ti_pci7420_firewire_enable_dev(device_t dev)
struct chip_operations southbridge_ti_pci7420_firewire_ops = { CHIP_NAME("Texas Instruments PCI7420/7620 FireWire (IEEE 1394)") - .enable_dev = ti_pci7420_firewire_enable_dev, + .enable_dev = ti_pci7420_firewire_enable_dev, }; diff --git a/src/southbridge/ti/pci7420/pci7420.h b/src/southbridge/ti/pci7420/pci7420.h index df361b2..50593fe 100644 --- a/src/southbridge/ti/pci7420/pci7420.h +++ b/src/southbridge/ti/pci7420/pci7420.h @@ -20,28 +20,28 @@
// 0844d060 (old) #define SYSCTL 0x80 // 08405061 -#define RIMUX (1 << 0) +#define RIMUX (1 << 0)
#define GENCTL 0x86 -#define FW1394_PRIO (0 << 0) -#define CARDBUS_PRIO (1 << 0) -#define FLASH_PRIO (2 << 0) -#define ROUNDR_PRIO (3 << 0) -#define DISABLE_OHCI (1 << 3) -#define DISABLE_SKTB (1 << 4) -#define DISABLE_FM (1 << 5) -#define P12V_SW_SEL (1 << 10) +#define FW1394_PRIO (0 << 0) +#define CARDBUS_PRIO (1 << 0) +#define FLASH_PRIO (2 << 0) +#define ROUNDR_PRIO (3 << 0) +#define DISABLE_OHCI (1 << 3) +#define DISABLE_SKTB (1 << 4) +#define DISABLE_FM (1 << 5) +#define P12V_SW_SEL (1 << 10)
#define MFUNC 0x8c
#define CARDCTL 0x91 -#define SPKROUTEN (1 << 1) +#define SPKROUTEN (1 << 1)
#define DEVCTL 0x92 -#define INT_MODE_PAR (0 << 1) -#define INT_MODE_RSV (1 << 1) -#define INT_MODE_MIX (2 << 1) -#define INT_MODE_SER (3 << 1) +#define INT_MODE_PAR (0 << 1) +#define INT_MODE_RSV (1 << 1) +#define INT_MODE_MIX (2 << 1) +#define INT_MODE_SER (3 << 1)
#define INTA 0 #define INTB 1 diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index 5e62292..11ca4c3 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -47,14 +47,14 @@ static void pcixx12_set_resources(device_t dev)
static struct device_operations ti_pcixx12_ops = { .read_resources = pcixx12_read_resources, - .set_resources = pcixx12_set_resources, + .set_resources = pcixx12_set_resources, .enable_resources = cardbus_enable_resources, - .init = pcixx12_init, - .scan_bus = pci_scan_bridge, + .init = pcixx12_init, + .scan_bus = pci_scan_bridge, };
static const struct pci_driver ti_pcixx12_driver __pci_driver = { - .ops = &ti_pcixx12_ops, + .ops = &ti_pcixx12_ops, .vendor = 0x104c, .device = 0x8039, }; @@ -65,5 +65,5 @@ static void southbridge_init(device_t dev)
struct chip_operations southbridge_ti_pcixx12_ops = { CHIP_NAME("Texas Instruments PCIxx12 Cardbus Controller") - .enable_dev = southbridge_init, + .enable_dev = southbridge_init, }; diff --git a/src/southbridge/via/common/early_smbus_print_error.c b/src/southbridge/via/common/early_smbus_print_error.c index 7b30a71..2cdf89f 100644 --- a/src/southbridge/via/common/early_smbus_print_error.c +++ b/src/southbridge/via/common/early_smbus_print_error.c @@ -25,7 +25,7 @@ * * @param smbus_dev The base SMBus IO port * @param host_status The data returned on the host status register after - * a transaction is processed. + * a transaction is processed. * @param loops The number of times a transaction was attempted. * @return 0 if no error occurred * 1 if an error was detected diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ea4c4f2 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -4,11 +4,11 @@ config SOUTHBRIDGE_VIA_K8T890
if SOUTHBRIDGE_VIA_K8T890
-config SOUTHBRIDGE_VIA_SUBTYPE_K8M800 # not tested +config SOUTHBRIDGE_VIA_SUBTYPE_K8M800 # not tested def_bool n config SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD # not tested, lspci lists B188 and 3188 def_bool n -config SOUTHBRIDGE_VIA_SUBTYPE_K8T800 # lspci lists 0282, 1282, 2282, 3282, and 7282 +config SOUTHBRIDGE_VIA_SUBTYPE_K8T800 # lspci lists 0282, 1282, 2282, 3282, and 7282 def_bool n config SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO # lspci lists 0282, 1282, 2282, 3282, and 7282 def_bool n diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 50d50f3..0ec7ed2 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -126,7 +126,7 @@ chrome_init(struct device *dev) fb_size = k8m890_host_fb_size_get(); if (!fb_size) { printk(BIOS_WARNING, "Chrome: Device has not been initialised in the" - " ramcontroller!\n"); + " ramcontroller!\n"); return; }
@@ -160,21 +160,21 @@ chrome_init(struct device *dev) static struct device_operations chrome_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = chrome_init, - .scan_bus = 0, - .enable = 0, + .init = chrome_init, + .scan_bus = 0, + .enable = 0, };
static const struct pci_driver unichrome_driver_800 __pci_driver = { - .ops = &chrome_ops, + .ops = &chrome_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M800_CHROME, };
static const struct pci_driver unichrome_driver_890 __pci_driver = { - .ops = &chrome_ops, + .ops = &chrome_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_K8M890_CHROME, }; diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 07a34b7..3e40cd0 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -88,7 +88,7 @@ static void dram_enable_k8m890(struct device *dev)
if ((fbbits < 1) || (fbbits > 7)) { printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", - 4 << fbbits); + 4 << fbbits); fbbits = 5; } uma_memory_size = 4 << (fbbits + 20); @@ -110,9 +110,9 @@ int k8m890_host_fb_size_get(void) { struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); + PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); unsigned char tmp;
tmp = pci_read_config8(dev, 0xA1); diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c index adc6770..4f5ce14 100644 --- a/src/southbridge/via/k8t890/pcie.c +++ b/src/southbridge/via/k8t890/pcie.c @@ -49,9 +49,9 @@ static void pcie_common_init(struct device *dev) * bit4: receive polarity change control * bits3:2: squelch window select 64~175mv * bit1: Number of non-idle bits detected before exiting idle state - * 0: 10 bits, 1: 2 bits + * 0: 10 bits, 1: 2 bits * bit0: Number of idle bits detected before entering idle state - * 0: 10 bits, 1: 2 bits + * 0: 10 bits, 1: 2 bits */ pci_write_config8(dev, 0xe1, 0xb);
diff --git a/src/southbridge/via/vt8231/acpi.c b/src/southbridge/via/vt8231/acpi.c index 647910a..f0497ba 100644 --- a/src/southbridge/via/vt8231/acpi.c +++ b/src/southbridge/via/vt8231/acpi.c @@ -29,11 +29,11 @@ static void acpi_init(struct device *dev)
static struct device_operations acpi_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = acpi_init, - .enable = 0, - .ops_pci = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { diff --git a/src/southbridge/via/vt8231/enable_rom.c b/src/southbridge/via/vt8231/enable_rom.c index 618adf8..cff6b72 100644 --- a/src/southbridge/via/vt8231/enable_rom.c +++ b/src/southbridge/via/vt8231/enable_rom.c @@ -26,7 +26,7 @@ static void vt8231_enable_rom(void) device_t dev;
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8231), 0); + PCI_DEVICE_ID_VIA_8231), 0);
/* * ROM decode control register (0x43): diff --git a/src/southbridge/via/vt8231/ide.c b/src/southbridge/via/vt8231/ide.c index 46479c4..89c3b57 100644 --- a/src/southbridge/via/vt8231/ide.c +++ b/src/southbridge/via/vt8231/ide.c @@ -99,11 +99,11 @@ static void ide_init(struct device *dev)
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = ide_init, - .enable = 0, - .ops_pci = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c index 40854db..c238605 100644 --- a/src/southbridge/via/vt8231/lpc.c +++ b/src/southbridge/via/vt8231/lpc.c @@ -15,8 +15,8 @@ static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
/* Our IDSEL mappings are as follows - PCI slot is AD31 (device 15) (00:14.0) - Southbridge is AD28 (device 12) (00:11.0) + PCI slot is AD31 (device 15) (00:14.0) + Southbridge is AD28 (device 12) (00:11.0) */ static void pci_routing_fixup(struct device *dev) { @@ -150,12 +150,12 @@ static void southbridge_init(struct device *dev)
static struct device_operations vt8231_lpc_ops = { .read_resources = vt8231_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, .scan_bus = scan_static_bus, - .enable = 0, - .ops_pci = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/via/vt8231/nic.c b/src/southbridge/via/vt8231/nic.c index 5cd6cd8..8ad8c96 100644 --- a/src/southbridge/via/vt8231/nic.c +++ b/src/southbridge/via/vt8231/nic.c @@ -22,11 +22,11 @@ static void nic_init(struct device *dev)
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = nic_init, - .enable = 0, - .ops_pci = 0, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c index d091099..e9633a0 100644 --- a/src/southbridge/via/vt8235/early_smbus.c +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -16,13 +16,13 @@
/* Define register settings */ #define HOST_RESET 0xff -#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ +#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
#define SMBUS_TIMEOUT (100*1000*10)
-#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69
static void enable_smbus(void) { diff --git a/src/southbridge/via/vt8235/ide.c b/src/southbridge/via/vt8235/ide.c index 961f860..eefc69b 100644 --- a/src/southbridge/via/vt8235/ide.c +++ b/src/southbridge/via/vt8235/ide.c @@ -99,15 +99,15 @@ static void ide_init(struct device *dev)
static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .enable = 0, - .ops_pci = 0, + .init = ide_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &ide_ops, + .ops = &ide_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_1, }; diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c index b355ad0..2278022 100644 --- a/src/southbridge/via/vt8235/lpc.c +++ b/src/southbridge/via/vt8235/lpc.c @@ -20,7 +20,7 @@ IRQ 4 = COM 1 IRQ 5 = available for PCI interrupts IRQ 6 = floppy or availbale for PCI if floppy controller disabled - IRQ 7 = LPT or available if LPT port disabled + IRQ 7 = LPT or available if LPT port disabled IRQ 8 = rtc IRQ 9 = available for PCI interrupts IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia) @@ -33,13 +33,13 @@ */ static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 };
-static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char usbPins[4] = { 'A','B','C','D'}; static const unsigned char enetPins[4] = { 'A','B','C','D'}; static const unsigned char slotPins[4] = { 'B','C','D','A'}; static const unsigned char firewirePins[4] = { 'B','C','D','A'}; static const unsigned char vt8235Pins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char cbPins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char cbPins[4] = { 'A','B','C','D'}; static const unsigned char riserPins[4] = { 'A','B','C','D'};
@@ -248,14 +248,14 @@ static void southbridge_init(struct device *dev)
static struct device_operations vt8235_lpc_ops = { .read_resources = vt8235_read_resources, - .set_resources = vt8235_set_resources, + .set_resources = vt8235_set_resources, .enable_resources = pci_dev_enable_resources, - .init = southbridge_init, - .scan_bus = scan_static_bus, + .init = southbridge_init, + .scan_bus = scan_static_bus, };
static const struct pci_driver lpc_driver __pci_driver = { - .ops = &vt8235_lpc_ops, + .ops = &vt8235_lpc_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_8235, }; diff --git a/src/southbridge/via/vt8235/nic.c b/src/southbridge/via/vt8235/nic.c index 71f169c..f75891a 100644 --- a/src/southbridge/via/vt8235/nic.c +++ b/src/southbridge/via/vt8235/nic.c @@ -22,15 +22,15 @@ static void nic_init(struct device *dev)
static struct device_operations nic_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .enable = 0, - .ops_pci = 0, + .init = nic_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &nic_ops, + .ops = &nic_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_8233_7, }; diff --git a/src/southbridge/via/vt8235/usb.c b/src/southbridge/via/vt8235/usb.c index c712136..f4cf730 100644 --- a/src/southbridge/via/vt8235/usb.c +++ b/src/southbridge/via/vt8235/usb.c @@ -29,15 +29,15 @@ static void usb_init(struct device *dev)
static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .enable = 0, - .ops_pci = 0, + .init = usb_init, + .enable = 0, + .ops_pci = 0, };
static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &usb_ops, + .ops = &usb_ops, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_2, }; diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c index e61b8f2..65a8db3 100644 --- a/src/southbridge/via/vt8237r/ctrl.c +++ b/src/southbridge/via/vt8237r/ctrl.c @@ -39,7 +39,7 @@ static void vt8237_cfg(struct device *dev) PCI_DEVICE_ID_VIA_K8M800_DRAM, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8T890CE_3, 0); + PCI_DEVICE_ID_VIA_K8T890CE_3, 0); if (!devfun3) devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_3, 0); @@ -215,10 +215,10 @@ static void vt8237a_vlink_init(struct device *dev) * init code is required. * * FIXME: This is based on vt8237r_vlink_init() in - * k8t890/k8t890_ctrl.c and modified to fit what the AMI - * BIOS on my M2V wrote to these registers (by looking - * at lspci -nxxx output). - * Works for me. + * k8t890/k8t890_ctrl.c and modified to fit what the AMI + * BIOS on my M2V wrote to these registers (by looking + * at lspci -nxxx output). + * Works for me. */
/* disable auto disconnect */ diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index b087a47..0de55a6 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -28,7 +28,7 @@ * Print an error, should it occur. If no error, just exit. * * @param host_status The data returned on the host status register after - * a transaction is processed. + * a transaction is processed. * @param loops The number of times a transaction was attempted. */ static void smbus_print_error(u8 host_status, int loops) @@ -151,7 +151,7 @@ static device_t get_vt8237_lpc(void)
/* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev != PCI_DEV_INVALID) return dev;
@@ -181,7 +181,7 @@ void enable_smbus(void) /* Make sure the RTC power well is up before touching smbus. */ loops = 0; while (!(pci_read_config8(dev, VT8237R_PSON) & (1<<6)) - && loops < PSONREADY_TIMEOUT) + && loops < PSONREADY_TIMEOUT) ++loops;
/* @@ -214,8 +214,8 @@ void enable_smbus(void) * known-good data from a slot/address. Exits on either good data or a timeout. * * TODO: This should probably go into some global file, but one would need to - * be created just for it. If some other chip needs/wants it, we can - * worry about it then. + * be created just for it. If some other chip needs/wants it, we can + * worry about it then. * * @param ctrl The memory controller and SMBus addresses. */ @@ -283,7 +283,7 @@ void vt8237_sb_enable_fid_vid(void) if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); + PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
if (devctl != PCI_DEV_INVALID) { /* So the chip knows we are on AMD. */ @@ -361,7 +361,7 @@ void vt8237_early_spi_init(void)
/* Bus Control and Power Management */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev == PCI_DEV_INVALID) die("SB not found\n"); @@ -420,7 +420,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom)
/* Network adapter */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8233_7), 0); + PCI_DEVICE_ID_VIA_8233_7), 0); if (dev == PCI_DEV_INVALID) { print_err("Network is disabled, please enable\n"); return 0; @@ -494,7 +494,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) /* XXX not so messy, but an explanation of the hack would have been better */ loops = 0; while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) - && (loops < LAN_TIMEOUT)) { + && (loops < LAN_TIMEOUT)) { ++loops; }
diff --git a/src/southbridge/via/vt8237r/ide.c b/src/southbridge/via/vt8237r/ide.c index 5d0fa56..2b2f587 100644 --- a/src/southbridge/via/vt8237r/ide.c +++ b/src/southbridge/via/vt8237r/ide.c @@ -110,7 +110,7 @@ static void ide_init(struct device *dev)
/* Set PATA Output Drive Strength */ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (lpc_dev) pci_write_config8(lpc_dev, 0x7C, 0x20); #endif diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 01d2a9c..630b9a5 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -39,13 +39,13 @@ static void southbridge_init_common(struct device *dev);
#if CONFIG_EPIA_VT8237R_INIT - /* Interrupts for INT# A B C D */ + /* Interrupts for INT# A B C D */ static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
- /* Interrupt Assignments for Pins 1 2 3 4 */ + /* Interrupt Assignments for Pins 1 2 3 4 */ static const unsigned char sataPins[4] = { 'A','B','C','D'}; -static const unsigned char vgaPins[4] = { 'A','B','C','D'}; -static const unsigned char usbPins[4] = { 'A','B','C','D'}; +static const unsigned char vgaPins[4] = { 'A','B','C','D'}; +static const unsigned char usbPins[4] = { 'A','B','C','D'}; static const unsigned char enetPins[4] = { 'A','B','C','D'}; static const unsigned char vt8237Pins[4] = { 'A','B','C','D'}; static const unsigned char slotPins[4] = { 'C','D','A','B'}; @@ -358,9 +358,9 @@ static void vt8237a_init(struct device *dev) { /* * FIXME: This is based on vt8237s_init() and the values the AMI - * BIOS on my M2V wrote to these registers (by loking - * at lspci -nxxx output). - * Works for me. + * BIOS on my M2V wrote to these registers (by loking + * at lspci -nxxx output). + * Works for me. */ u32 tmp;
@@ -510,7 +510,7 @@ static void vt8237_common_init(struct device *dev) * 3 | Bypass APIC De-Assert Message (1=Enable) * 2 | APIC HyperTransport Mode (1=Enable) * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ pci_write_config8(dev, 0x5b, 0x9); @@ -533,7 +533,7 @@ static void vt8237_common_init(struct device *dev) * 3 | Bypass APIC De-Assert Message (1=Enable) * 2 | APIC HyperTransport Mode (1=Enable) * 1 | possibly "INTE#, INTF#, INTG#, INTH# as PCI" - * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch + * | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch * 0 | Dynamic Clock Gating Main Switch (1=Enable) */ if (cfg && cfg->int_efgh_as_gpio) { diff --git a/src/southbridge/via/vt8237r/nvs.h b/src/southbridge/via/vt8237r/nvs.h index e8a0084..89a24d2 100644 --- a/src/southbridge/via/vt8237r/nvs.h +++ b/src/southbridge/via/vt8237r/nvs.h @@ -35,7 +35,7 @@ typedef struct { u8 dbgs; /* 0x11 - Debug state */ u8 linx; /* 0x12 - Linux OS */ u8 dckn; /* 0x13 - PCIe docking state */ - u8 rsvd[0x28-0x14]; + u8 rsvd[0x28-0x14]; /* Processor Identification */ u8 apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */ diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c index a1a48a7..ad7cf33 100644 --- a/src/southbridge/via/vt8237r/usb.c +++ b/src/southbridge/via/vt8237r/usb.c @@ -77,8 +77,8 @@ static void vt8237_usb_i_read_resources(struct device *dev) printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]);
/* Fix the I/O Resources of the USB1.1 Interfaces */ - /* Auto PCI probe seems to size the resources */ - /* Incorrectly */ + /* Auto PCI probe seems to size the resources */ + /* Incorrectly */ res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = usb_io_addr[function]; res->size = 256; diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index ee5cc82..8a97410 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -32,26 +32,26 @@
/* PMBASE FIXME mostly taken from ich7 */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index 74fd028..157f439 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -28,7 +28,7 @@ * SUPERIO_PNP_LDN The logical device number on the super i/o * chip for this device (required) * SUPERIO_PNP_DDN A string literal that identifies the dos device - * name (DDN) of this device (e.g. "COM1", optional) + * name (DDN) of this device (e.g. "COM1", optional) * SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down * the logical device (optional) * SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index 8ddecbf..02907af 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -29,7 +29,7 @@ * SUPERIO_UART_LDN The logical device number on the super i/o * chip for this UART (required) * SUPERIO_UART_DDN A string literal that identifies the dos device - * name (DDN) of this uart (e.g. "COM1", optional) + * name (DDN) of this uart (e.g. "COM1", optional) * SUPERIO_UART_PM_REG Identifier of a 1-bit register to power down * the UART (optional) * SUPERIO_UART_PM_VAL The value for SUPERIO_UART_PM_REG to power the logical diff --git a/src/superio/fintek/f71805f/superio.c b/src/superio/fintek/f71805f/superio.c index 4a31606..363035f 100644 --- a/src/superio/fintek/f71805f/superio.c +++ b/src/superio/fintek/f71805f/superio.c @@ -37,11 +37,11 @@ static void f71805f_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71805f_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f71805f_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 2736c0b..178e93f 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -38,11 +38,11 @@ static void f71859_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71859_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f71859_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 4159e6d..5d4c359 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -47,11 +47,11 @@ static void f71863fg_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71863fg_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f71863fg_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { @@ -59,7 +59,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71863FG_GPIO, }, diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 55a11b1..f0b2b52 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -44,11 +44,11 @@ static void f71872_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71872_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f71872_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f71889/superio.c b/src/superio/fintek/f71889/superio.c index 450f938..1b25e4c 100644 --- a/src/superio/fintek/f71889/superio.c +++ b/src/superio/fintek/f71889/superio.c @@ -45,11 +45,11 @@ static void f71889_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f71889_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f71889_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 85ac7ba..592fa5b 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -44,11 +44,11 @@ static void f81865f_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f81865f_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = f81865f_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/intel/i3100/superio.c b/src/superio/intel/i3100/superio.c index f791d9d..d079047 100644 --- a/src/superio/intel/i3100/superio.c +++ b/src/superio/intel/i3100/superio.c @@ -50,11 +50,11 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = i3100_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .enable = pnp_alt_enable, + .init = i3100_init, + .ops_pnp_mode = &pnp_conf_mode_ops, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 5a51f02..feee3bf 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -33,8 +33,8 @@
/* Register and bit definitions. */ #define IT8661F_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8661F_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8661F_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */ +#define IT8661F_REG_LDE 0x23 /* PnP Logical Device Enable. */ +#define IT8661F_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */
#define IT8661F_ISA_PNP_PORT 0x0279 /* Write-only. */
diff --git a/src/superio/ite/it8661f/superio.c b/src/superio/ite/it8661f/superio.c index 812af78..6ab4821 100644 --- a/src/superio/ite/it8661f/superio.c +++ b/src/superio/ite/it8661f/superio.c @@ -43,10 +43,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, IR, GPIO. */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index c2ba6e0..b18b080 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -22,15 +22,15 @@ #include "it8671f.h"
/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */ +#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8671F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8671F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ +#define IT8671F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
@@ -93,7 +93,7 @@ static void it8671f_enable_serial(device_t dev, u16 iobase)
/* * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). + * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 423dbfe..e69f8d7 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -48,10 +48,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, KBCM. */ diff --git a/src/superio/ite/it8673f/early_serial.c b/src/superio/ite/it8673f/early_serial.c index 987b5e6..341d02a 100644 --- a/src/superio/ite/it8673f/early_serial.c +++ b/src/superio/ite/it8673f/early_serial.c @@ -22,13 +22,13 @@ #include "it8673f.h"
/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8673F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8673F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8673F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend. */
diff --git a/src/superio/ite/it8673f/superio.c b/src/superio/ite/it8673f/superio.c index 080c3bd..c20d5db 100644 --- a/src/superio/ite/it8673f/superio.c +++ b/src/superio/ite/it8673f/superio.c @@ -50,10 +50,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, FAN, KBCM. */ diff --git a/src/superio/ite/it8705f/early_serial.c b/src/superio/ite/it8705f/early_serial.c index ccc92c2..2ea9f9b 100644 --- a/src/superio/ite/it8705f/early_serial.c +++ b/src/superio/ite/it8705f/early_serial.c @@ -22,13 +22,13 @@ #include "it8705f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8705F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8705F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
/* WTF? 0x23 and 0x24 are swapped here (when compared to other IT87xx). */ diff --git a/src/superio/ite/it8705f/superio.c b/src/superio/ite/it8705f/superio.c index 1dedf45..8eaf10e 100644 --- a/src/superio/ite/it8705f/superio.c +++ b/src/superio/ite/it8705f/superio.c @@ -49,10 +49,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */ diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..6f298f6 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -22,17 +22,17 @@ #include "it8712f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
static void it8712f_sio_write(u8 ldn, u8 index, u8 value) diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 619b260..be958f4 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -79,11 +79,11 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8712f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .enable = pnp_alt_enable, + .init = it8712f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..5df8ee9 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -25,13 +25,13 @@ #include "it8716f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 4b58bb4..53f69a9 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -66,12 +66,12 @@ static void init_ec(u16 base) /* Read out current value of FAN_CTL (0x14). */ value = pnp_read_index(base, 0x14); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", - base + 0x14, value); + base + 0x14, value);
/* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", - base + 0x14, value | 0x87); + base + 0x14, value | 0x87); } #endif
@@ -103,11 +103,11 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8716f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .enable = pnp_alt_enable, + .init = it8716f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 308b67c..5f670b4 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -22,13 +22,13 @@ #include "it8718f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 17c7fad..4a30abe 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -52,10 +52,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, EC, KBCM, IR. */ diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c index 20e19b6..38e1f89 100644 --- a/src/superio/ite/it8721f/early_serial.c +++ b/src/superio/ite/it8721f/early_serial.c @@ -23,13 +23,13 @@ #include "it8721f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x2e +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 6305d75..052f613 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -53,10 +53,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, EC, KBCM, IR. */ diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 603e467..d609ab2 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -33,8 +33,8 @@ #define IT8728F_IR 0x0a /* Consumer IR */
/* Global configuration registers. */ -#define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8728F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8728F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8728F_CONFIG_REG_CHIPVERS 0x22 /* Chip version */ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c index 8bf2964..fe58e9a 100644 --- a/src/superio/ite/it8772f/early_serial.c +++ b/src/superio/ite/it8772f/early_serial.c @@ -23,15 +23,15 @@ #include "it8772f.h"
/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE IT8772F_BASE -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE IT8772F_BASE +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8772F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */ +#define IT8772F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8772F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
u8 it8772f_sio_read(u8 index) diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 5004c10..4aef9cb 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -195,11 +195,11 @@ static const struct pnp_mode_ops pnp_conf_mode_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = it8772f_init, - .ops_pnp_mode = &pnp_conf_mode_ops, + .enable = pnp_alt_enable, + .init = it8772f_init, + .ops_pnp_mode = &pnp_conf_mode_ops, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc8374/superio.c b/src/superio/nsc/pc8374/superio.c index af50316..e8b226f 100644 --- a/src/superio/nsc/pc8374/superio.c +++ b/src/superio/nsc/pc8374/superio.c @@ -46,10 +46,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index 2aede74..c125b7e 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -43,10 +43,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87351/superio.c b/src/superio/nsc/pc87351/superio.c index 56d373b..d543db1 100644 --- a/src/superio/nsc/pc87351/superio.c +++ b/src/superio/nsc/pc87351/superio.c @@ -46,10 +46,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 054353a..a2f18d7 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -46,10 +46,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 95945c8..23209b6 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -46,10 +46,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index ce0189d..186ed18 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -44,10 +44,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 8fd33d7..f07d98e 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -30,9 +30,9 @@
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, + .enable = pnp_enable, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 3afc556..10520a6 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -35,10 +35,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 52f20d3..8755eb8 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -47,10 +47,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc87427/superio.c b/src/superio/nsc/pc87427/superio.c index ae02f01..7df1999 100644 --- a/src/superio/nsc/pc87427/superio.c +++ b/src/superio/nsc/pc87427/superio.c @@ -44,10 +44,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc97307/chip.h b/src/superio/nsc/pc97307/chip.h index a190221..f47f99d 100644 --- a/src/superio/nsc/pc97307/chip.h +++ b/src/superio/nsc/pc97307/chip.h @@ -22,10 +22,10 @@ #define SUPERIO_NSC_PC97307_CHIP_H
#ifndef PNP_INDEX_REG -#define PNP_INDEX_REG 0x15C +#define PNP_INDEX_REG 0x15C #endif #ifndef PNP_DATA_REG -#define PNP_DATA_REG 0x15D +#define PNP_DATA_REG 0x15D #endif
#include <pc80/keyboard.h> diff --git a/src/superio/nsc/pc97307/superio.c b/src/superio/nsc/pc97307/superio.c index c1cd5c1..be75521 100644 --- a/src/superio/nsc/pc97307/superio.c +++ b/src/superio/nsc/pc97307/superio.c @@ -57,10 +57,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nsc/pc97317/chip.h b/src/superio/nsc/pc97317/chip.h index 8aaeddd..53d8388 100644 --- a/src/superio/nsc/pc97317/chip.h +++ b/src/superio/nsc/pc97317/chip.h @@ -22,10 +22,10 @@ #define SUPERIO_NSC_PC97317_CHIP_H
#ifndef PNP_INDEX_REG -#define PNP_INDEX_REG 0x15C +#define PNP_INDEX_REG 0x15C #endif #ifndef PNP_DATA_REG -#define PNP_DATA_REG 0x15D +#define PNP_DATA_REG 0x15D #endif
#include <pc80/keyboard.h> diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index a69dfe7..48f30fd 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -48,10 +48,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 5eb8991..fdfecb1 100755 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -30,11 +30,11 @@ static void nct5104d_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = nct5104d_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = nct5104d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index 6a48b72..ee09c09 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -45,10 +45,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 56e9c07..c610354 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -54,13 +54,13 @@ static void m3885x_enable_resources(device_t dev) }
static struct device_operations ops = { - .init = m3885x_init, + .init = m3885x_init, .read_resources = m3885x_read_resources, .enable_resources = m3885x_enable_resources };
static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } + { &ops, 0, 0, { 0, 0 }, } };
static void enable_dev(device_t dev) diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 38cb0f8..5999fd8 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -22,16 +22,16 @@ #include "fdc37m60x.h"
/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ -#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ +#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ #define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ #define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ -#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ +#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */
#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */
diff --git a/src/superio/smsc/fdc37m60x/superio.c b/src/superio/smsc/fdc37m60x/superio.c index af30572..a6a5976 100644 --- a/src/superio/smsc/fdc37m60x/superio.c +++ b/src/superio/smsc/fdc37m60x/superio.c @@ -48,10 +48,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, AUX. */ diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 3265e6b..a623764 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -46,10 +46,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 3fe6327..402cd92 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -17,16 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define KBC1100_PM1 1 /* PM1 */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ -#define KBC1100_KBC 7 /* Keyboard */ -#define KBC1100_EC0 8 /* EC Channel 0 */ -#define KBC1100_MAILBOX 9 /* Mail Box */ -#define KBC1100_GPIO 0x0A /* GPIO */ -#define KBC1100_SPI 0x0B /* Share flash interface */ +#define KBC1100_PM1 1 /* PM1 */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define KBC1100_KBC 7 /* Keyboard */ +#define KBC1100_EC0 8 /* EC Channel 0 */ +#define KBC1100_MAILBOX 9 /* Mail Box */ +#define KBC1100_GPIO 0x0A /* GPIO */ +#define KBC1100_SPI 0x0B /* Share flash interface */
-#define KBC1100_EC1 0x0D /* EC Channel 1 */ -#define KBC1100_EC2 0x0E /* EC Channel 2 */ +#define KBC1100_EC1 0x0D /* EC Channel 1 */ +#define KBC1100_EC2 0x0E /* EC Channel 2 */
diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c index 5d74c32..ecb8225d 100644 --- a/src/superio/smsc/kbc1100/kbc1100_early_init.c +++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c @@ -59,7 +59,7 @@ static inline void kbc1100_early_init(unsigned port) pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ - pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ pnp_set_enable(dev, 1);
/* Enable EC Channel 0 */ diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index c56694c..b73667b 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -45,9 +45,9 @@ static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = kbc1100_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = kbc1100_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47b272/lpc47b272.h b/src/superio/smsc/lpc47b272/lpc47b272.h index cbfdb13..e5ab405 100644 --- a/src/superio/smsc/lpc47b272/lpc47b272.h +++ b/src/superio/smsc/lpc47b272/lpc47b272.h @@ -21,12 +21,12 @@ #ifndef SUPERIO_SMSC_LPC47B272_LPC47B272_H #define SUPERIO_SMSC_LPC47B272_LPC47B272_H
-#define LPC47B272_FDC 0 /* Floppy */ -#define LPC47B272_PP 3 /* Parallel Port */ -#define LPC47B272_SP1 4 /* Com1 */ -#define LPC47B272_SP2 5 /* Com2 */ -#define LPC47B272_KBC 7 /* Keyboard & Mouse */ -#define LPC47B272_RT 10 /* Runtime reg*/ +#define LPC47B272_FDC 0 /* Floppy */ +#define LPC47B272_PP 3 /* Parallel Port */ +#define LPC47B272_SP1 4 /* Com1 */ +#define LPC47B272_SP2 5 /* Com2 */ +#define LPC47B272_KBC 7 /* Keyboard & Mouse */ +#define LPC47B272_RT 10 /* Runtime reg*/
#define LPC47B272_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 8901ec4..31a61bb 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -48,11 +48,11 @@ struct chip_operations superio_smsc_lpc47b272_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b272_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = lpc47b272_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ff6e405..3e05b79 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -87,11 +87,11 @@ static void lpc47b397_pnp_enable_resources(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = lpc47b397_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
#define HWM_INDEX 0 @@ -145,13 +145,13 @@ static struct smbus_bus_operations lops_smbus_bus = {
static struct device_operations ops_hwm = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = lpc47b397_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47b397_init, - .scan_bus = scan_static_bus, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = lpc47b397_init, + .scan_bus = scan_static_bus, + .ops_smbus_bus = &lops_smbus_bus, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index e851048..e9ddc0e 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -23,14 +23,14 @@ #ifndef SUPERIO_SMSC_LPC47M10X_LPC47M10X_H #define SUPERIO_SMSC_LPC47M10X_LPC47M10X_H
-#define LPC47M10X2_FDC 0 /* Floppy */ -#define LPC47M10X2_PP 3 /* Parallel Port */ -#define LPC47M10X2_SP1 4 /* Com1 */ -#define LPC47M10X2_SP2 5 /* Com2 */ -#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ -#define LPC47M10X2_GAME 9 /* GAME */ -#define LPC47M10X2_PME 10 /* PME reg*/ -#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */ +#define LPC47M10X2_FDC 0 /* Floppy */ +#define LPC47M10X2_PP 3 /* Parallel Port */ +#define LPC47M10X2_SP1 4 /* Com1 */ +#define LPC47M10X2_SP2 5 /* Com2 */ +#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ +#define LPC47M10X2_GAME 9 /* GAME */ +#define LPC47M10X2_PME 10 /* PME reg*/ +#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */
#define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index c1f3c2c..2fca602 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -47,11 +47,11 @@ struct chip_operations superio_smsc_lpc47m10x_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47m10x_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = lpc47m10x_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h index 04f1729..467a666 100644 --- a/src/superio/smsc/lpc47m15x/lpc47m15x.h +++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h @@ -20,14 +20,14 @@ #ifndef SUPERIO_SMSC_LPC47M15X_LPC47M15X_H #define SUPERIO_SMSC_LPC47M15X_LPC47M15X_H
-#define LPC47M15X_FDC 0 /* Floppy */ -#define LPC47M15X_PP 3 /* Parallel Port */ -#define LPC47M15X_SP1 4 /* Com1 */ -#define LPC47M15X_SP2 5 /* Com2 */ -#define LPC47M15X_KBC 7 /* Keyboard & Mouse */ -#define LPC47M15X_GAME 9 /* GAME */ -#define LPC47M15X_PME 10 /* PME reg*/ -#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/ +#define LPC47M15X_FDC 0 /* Floppy */ +#define LPC47M15X_PP 3 /* Parallel Port */ +#define LPC47M15X_SP1 4 /* Com1 */ +#define LPC47M15X_SP2 5 /* Com2 */ +#define LPC47M15X_KBC 7 /* Keyboard & Mouse */ +#define LPC47M15X_GAME 9 /* GAME */ +#define LPC47M15X_PME 10 /* PME reg*/ +#define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/
#define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 7e400fc..fdca36f 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -43,11 +43,11 @@ struct chip_operations superio_smsc_lpc47m15x_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = lpc47m15x_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = lpc47m15x_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index e2ae49d..6c214c0 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -47,8 +47,8 @@ void try_enabling_LPC47N207_uart(void) u16 lpc_port; int i, j;
-#define CONFIG_ENABLE 0x55 -#define CONFIG_DISABLE 0xaa +#define CONFIG_ENABLE 0x55 +#define CONFIG_DISABLE 0xaa
for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { lpc_port = lpc_ports[j]; diff --git a/src/superio/smsc/lpc47n217/lpc47n217.h b/src/superio/smsc/lpc47n217/lpc47n217.h index 9c5b0fd..f657013 100644 --- a/src/superio/smsc/lpc47n217/lpc47n217.h +++ b/src/superio/smsc/lpc47n217/lpc47n217.h @@ -25,9 +25,9 @@ * These are arbitrary, but must match declarations in the mainboard * devicetree.cb file. Values chosen to match SMSC LPC47B37x. */ -#define LPC47N217_PP 3 /* Parallel Port */ -#define LPC47N217_SP1 4 /* Com1 */ -#define LPC47N217_SP2 5 /* Com2 */ +#define LPC47N217_PP 3 /* Parallel Port */ +#define LPC47N217_SP1 4 /* Com1 */ +#define LPC47N217_SP2 5 /* Com2 */
#define LPC47N217_MAX_CONFIG_REGISTER 0x39
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 0b62f9d..3838b9f 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -55,14 +55,14 @@ struct chip_operations superio_smsc_lpc47n217_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47n217_pnp_set_resources, + .set_resources = lpc47n217_pnp_set_resources, .enable_resources = lpc47n217_pnp_enable_resources, - .enable = lpc47n217_pnp_enable, - .init = lpc47n217_init, + .enable = lpc47n217_pnp_enable, + .init = lpc47n217_init, };
static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, } }; @@ -139,7 +139,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; }
@@ -157,7 +157,7 @@ static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource) lpc47n217_pnp_set_irq(dev, resource->base); } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; diff --git a/src/superio/smsc/lpc47n227/lpc47n227.h b/src/superio/smsc/lpc47n227/lpc47n227.h index 5df79e3..455a4f8 100644 --- a/src/superio/smsc/lpc47n227/lpc47n227.h +++ b/src/superio/smsc/lpc47n227/lpc47n227.h @@ -25,10 +25,10 @@ * space, these are arbitrary, but must match declarations in the mainboard * devicetree.cb. */ -#define LPC47N227_PP 1 /* Parallel Port */ -#define LPC47N227_SP1 2 /* COM1 */ -#define LPC47N227_SP2 3 /* COM2 */ -#define LPC47N227_KBDC 5 /* Keyboard */ +#define LPC47N227_PP 1 /* Parallel Port */ +#define LPC47N227_SP1 2 /* COM1 */ +#define LPC47N227_SP2 3 /* COM2 */ +#define LPC47N227_KBDC 5 /* Keyboard */
#define LPC47N227_MAX_CONFIG_REGISTER 0x39
diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 4c11042..4e9df74 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -53,10 +53,10 @@ struct chip_operations superio_smsc_lpc47n227_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = lpc47n227_pnp_set_resources, + .set_resources = lpc47n227_pnp_set_resources, .enable_resources = lpc47n227_pnp_enable_resources, - .enable = lpc47n227_pnp_enable, - .init = lpc47n227_init, + .enable = lpc47n227_pnp_enable, + .init = lpc47n227_init, };
static struct pnp_info pnp_dev_info[] = { @@ -146,7 +146,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; }
@@ -163,7 +163,7 @@ static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource) lpc47n227_pnp_set_irq(dev, resource->base); } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 448800e..ffb0bc6 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -54,11 +54,11 @@ static void mec1308_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = mec1308_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = mec1308_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h index d065489..7a2f675 100644 --- a/src/superio/smsc/sch4037/sch4037.h +++ b/src/superio/smsc/sch4037/sch4037.h @@ -21,14 +21,14 @@ #define SUPERIO_SCH_4037_H
-#define SCH4037_FDD 0 /* FDD */ -#define SCH4037_LPT 3 /* LPT */ -#define SMSCSUPERIO_SP1 4 /* Com1 */ -#define SMSCSUPERIO_SP2 5 /* Com2 */ -#define SCH4037_RTC 6 /* RTC */ -#define SCH4037_KBC 7 /* KBC */ -#define SCH4037_HWM 8 /* HWM */ -#define SCH4037_RUNTIME 0x0A /* Runtime */ -#define SCH4037_XBUS 0x0B /* X-BUS */ +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */
#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 96d35fe..5d55c4c 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -43,11 +43,11 @@ struct chip_operations superio_smsc_sch4037_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = sch4037_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = sch4037_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index ff7b5d1..fc28d8a 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -43,11 +43,11 @@ struct chip_operations superio_smsc_sio1036_ops = {
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = sio1036_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = sio1036_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index 827274f..7f8d30d 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -47,10 +47,10 @@ static void init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, };
/* TODO: FDC, PP, AUX. */ diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 42a9c09..9f3f0be 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -68,7 +68,7 @@ /* Register defines */ #define DEVICE_ID_REG 0x20 /* Device ID register */ #define DEVICE_REV_REG 0x21 /* Device revision register */ -#define DEVICE_TEST7_REG 0x29 /* Device test 7 register */ +#define DEVICE_TEST7_REG 0x29 /* Device test 7 register */
/* Static variables for the Super I/O device ID and revision. */ static int first_time = 1; @@ -116,7 +116,7 @@ enum { * device is not present on that chip. * * Note: Do _not_ list chips with different name but same device ID twice! - * The result would be that the init code would be executed twice! + * The result would be that the init code would be executed twice! */ static const struct logical_devices { u8 superio_id; @@ -129,12 +129,12 @@ static const struct logical_devices { {FDC37B72X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}}, {FDC37M81X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, {FDC37M60X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}}, - {LPC47B27X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, -1, 11, 10, -1, -1}}, - {LPC47M10X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, - {LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, - {LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}}, + {LPC47B27X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, -1, 11, 10, -1, -1}}, + {LPC47M10X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, + {LPC47M15X,{0, 3, 4, 5, -1, 7, -1, -1, -1, 9, 10, 11, -1, -1, -1}}, + {LPC47S45X,{0, 3, 4, 5, 6, 7, -1, 8, -1, -1, -1, -1, 10, -1, 11}}, {LPC47B397,{0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, - {LPC47U33X,{0, 3, 4, -1, -1, 7, -1, -1, -1, 9, 0, 5, 10, 0, 11}}, + {LPC47U33X,{0, 3, 4, -1, -1, 7, -1, -1, -1, 9, 0, 5, 10, 0, 11}}, {A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, @@ -177,11 +177,11 @@ static void smsc_init(device_t dev) /** Standard device operations. */ static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = smsc_init, - .ops_pnp_mode = &pnp_conf_mode_55_aa, + .enable = pnp_alt_enable, + .init = smsc_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, };
/** @@ -222,7 +222,7 @@ static struct pnp_info pnp_dev_info[] = { * Enable the logical devices of the Super I/O chip. * * TODO: Think about how to handle the case when a mainboard has multiple - * Super I/O chips soldered on. + * Super I/O chips soldered on. * TODO: Can this code be simplified a bit? * * @param dev The device to use. @@ -243,7 +243,7 @@ static void enable_dev(device_t dev) /* TODO: Error handling? */
printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, " - "rev=0x%02x)\n", superio_id, superio_rev); + "rev=0x%02x)\n", superio_id, superio_rev); first_time = 0;
if (superio_id == LPC47M172) { diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 68fd999..15a338c 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -137,8 +137,8 @@ static void vt1211_pnp_set_resources(struct device *dev) for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx " - "not assigned\n", dev_path(dev), res->index, - resource_type(res), res->size); + "not assigned\n", dev_path(dev), res->index, + resource_type(res), res->size); continue; }
@@ -151,7 +151,7 @@ static void vt1211_pnp_set_resources(struct device *dev) pnp_set_irq(dev, res->index, res->base); } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource " - "type\n", dev_path(dev), res->index); + "type\n", dev_path(dev), res->index); return; } res->flags |= IORESOURCE_STORED; @@ -164,11 +164,11 @@ static void vt1211_pnp_set_resources(struct device *dev)
struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = vt1211_pnp_set_resources, + .set_resources = vt1211_pnp_set_resources, .enable_resources = vt1211_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = vt1211_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = vt1211_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index 7616363..9342df7 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -67,7 +67,7 @@ Device(SUPERIO_DEV) { Field (CREG, ByteAcc, NoLock, Preserve) { PNP_ADDR_REG, 8, - PNP_DATA_REG, 8 + PNP_DATA_REG, 8 } IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) { diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index a931419..4f5de90 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -57,11 +57,11 @@ static void w83627dhg_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83627dhg_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = w83627dhg_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 9e83d34..56ee75c 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -22,20 +22,20 @@ #ifndef SUPERIO_WINBOND_W83627DHG_W83627DHG_H #define SUPERIO_WINBOND_W83627DHG_W83627DHG_H
-#define W83627DHG_FDC 0 /* Floppy */ -#define W83627DHG_PP 1 /* Parallel port */ -#define W83627DHG_SP1 2 /* Com1 */ -#define W83627DHG_SP2 3 /* Com2 */ -#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627DHG_SPI 6 /* Serial peripheral interface */ -#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ -#define W83627DHG_ACPI 10 /* ACPI */ -#define W83627DHG_HWM 11 /* Hardware monitor */ -#define W83627DHG_PECI_SST 12 /* PECI, SST */ +#define W83627DHG_FDC 0 /* Floppy */ +#define W83627DHG_PP 1 /* Parallel port */ +#define W83627DHG_SP1 2 /* Com1 */ +#define W83627DHG_SP2 3 /* Com2 */ +#define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627DHG_SPI 6 /* Serial peripheral interface */ +#define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ +#define W83627DHG_ACPI 10 /* ACPI */ +#define W83627DHG_HWM 11 /* Hardware monitor */ +#define W83627DHG_PECI_SST 12 /* PECI, SST */
/* The following are handled using "virtual LDNs" (hence the _V suffix). */ -#define W83627DHG_GPIO6_V 7 /* GPIO6 */ -#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */ +#define W83627DHG_GPIO6_V 7 /* GPIO6 */ +#define W83627DHG_GPIO2345_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5 */
/* * Virtual devices sharing the enables are encoded as follows: diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 6f2c9de..0e297a7 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -89,7 +89,7 @@ static void init_hwm(u16 base) value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " - "value = 0x%02x\n", base, reg, value); + "value = 0x%02x\n", base, reg, value); pnp_write_index(base, reg, value); } } @@ -133,16 +133,16 @@ static void w83627ehg_pnp_enable_resources(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = w83627ehg_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83627ehg_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = w83627ehg_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index c982603..6b045dd 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -22,19 +22,19 @@ #ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_W83627EHG_H
-#define W83627EHG_FDC 0 /* Floppy */ -#define W83627EHG_PP 1 /* Parallel port */ -#define W83627EHG_SP1 2 /* Com1 */ -#define W83627EHG_SP2 3 /* Com2 */ -#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ -#define W83627EHG_ACPI 10 /* ACPI */ -#define W83627EHG_HWM 11 /* Hardware monitor */ +#define W83627EHG_FDC 0 /* Floppy */ +#define W83627EHG_PP 1 /* Parallel port */ +#define W83627EHG_SP1 2 /* Com1 */ +#define W83627EHG_SP2 3 /* Com2 */ +#define W83627EHG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627EHG_WDTO_PLED 8 /* Watchdog timer timeout, power LED */ +#define W83627EHG_ACPI 10 /* ACPI */ +#define W83627EHG_HWM 11 /* Hardware monitor */
/* The following are handled using "virtual LDNs" (hence the _V suffix). */ -#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ +#define W83627EHG_SFI_V 6 /* Serial flash interface (SFI) */ #define W83627EHG_GPIO_GAME_MIDI_V 7 /* GPIO1, GPIO6, game port, MIDI */ -#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */ +#define W83627EHG_GPIO_SUSLED_V 9 /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
/* * Virtual devices sharing the enables are encoded as follows: diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 8531339..a02e642 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -35,25 +35,25 @@ * functionality * * Controllable through preprocessor macros: - * NO_W83627HF_FDC: don't expose the floppy disk controller + * NO_W83627HF_FDC: don't expose the floppy disk controller * NO_W83627HF_FDC_ENUM: don't try to enumerate the connected floppy drives - * NO_W83627HF_PPORT: don't expose the parallel port - * NO_W83627HF_UARTA: don't expose the first serial port - * NO_W83627HF_UARTB: don't expose the second serial port (already hidden - * if UARTB is configured as IRDA port by firmware) - * NO_W83627HF_IRDA: don't expose the IRDA port (already hidden if UARTB is - * configured as serial port by firmware) - * NO_W83627HF_CIR: don't expose the Consumer Infrared functionality - * NO_W83627HF_KBC: don't expose the keyboard controller - * NO_W83627HF_PS2M: don't expose the PS/2 mouse functionality of the - * keyboard controller - * NO_W83627HF_GAME: don't expose the game port - * NO_W83627HF_MIDI: don't expose the MIDI port - * NO_W83627HF_HWMON: don't expose the hardware monitor as - * PnP "Motherboard Ressource" + * NO_W83627HF_PPORT: don't expose the parallel port + * NO_W83627HF_UARTA: don't expose the first serial port + * NO_W83627HF_UARTB: don't expose the second serial port (already hidden + * if UARTB is configured as IRDA port by firmware) + * NO_W83627HF_IRDA: don't expose the IRDA port (already hidden if UARTB is + * configured as serial port by firmware) + * NO_W83627HF_CIR: don't expose the Consumer Infrared functionality + * NO_W83627HF_KBC: don't expose the keyboard controller + * NO_W83627HF_PS2M: don't expose the PS/2 mouse functionality of the + * keyboard controller + * NO_W83627HF_GAME: don't expose the game port + * NO_W83627HF_MIDI: don't expose the MIDI port + * NO_W83627HF_HWMON: don't expose the hardware monitor as + * PnP "Motherboard Ressource" * W83627HF_KBC_COMPAT: show the keyboard controller and the PS/2 mouse as - * enabled if it is disabled but an address is assigned - * to it. This may be neccessary in some cases. + * enabled if it is disabled but an address is assigned + * to it. This may be neccessary in some cases. * * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 * http://www.itox.com/pages/support/wdt/W83627HF.pdf @@ -71,83 +71,83 @@ Device(SIO) { OperationRegion (CREG, SystemIO, 0x2E, 0x02) Field (CREG, ByteAcc, NoLock, Preserve) { - ADDR, 8, - DATA, 8 + ADDR, 8, + DATA, 8 } IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) { Offset (0x02), - RST, 1, /* Soft reset */ - , 7, + RST, 1, /* Soft reset */ + , 7, Offset (0x07), - LDN, 8, /* Logical device selector */ + LDN, 8, /* Logical device selector */ Offset (0x20), - DID, 8, /* Device ID */ - DREV, 8, /* Device Revision */ - FDPW, 1, /* FDC Power Down */ - , 2, - PRPW, 1, /* PRT Power Down */ - UAPW, 1, /* UART A Power Down */ - UBPW, 1, /* UART B Power Down */ - HWPW, 1, /* HWM Power Down */ - , 1, - IPD, 1, /* Immediate Chip Power Down */ - , 7, - PNPS, 1, /* PnP Address Select Register Default Value Mode */ - , 1, - KBCR, 1, /* KBC enabled after system reset (read-only) */ - , 3, - CLKS, 1, /* Clock select */ - AQ16, 1, /* 16bit Address Qualification */ - FDCT, 1, /* Tristate FDC (?) */ - , 2, - PRTT, 1, /* Tristate parallel port (?) */ - URAT, 1, /* Tristate UART A (?) */ - URBT, 1, /* Tristate UART B (?) */ - , 2, - URAI, 1, /* UART A Legacy IRQ Select Disable */ - URBI, 1, /* UART B Legacy IRQ Select Disable */ - PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ - FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ - , 1, - LCKC, 1, /* Lock Configuration Registers */ + DID, 8, /* Device ID */ + DREV, 8, /* Device Revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + HWPW, 1, /* HWM Power Down */ + , 1, + IPD, 1, /* Immediate Chip Power Down */ + , 7, + PNPS, 1, /* PnP Address Select Register Default Value Mode */ + , 1, + KBCR, 1, /* KBC enabled after system reset (read-only) */ + , 3, + CLKS, 1, /* Clock select */ + AQ16, 1, /* 16bit Address Qualification */ + FDCT, 1, /* Tristate FDC (?) */ + , 2, + PRTT, 1, /* Tristate parallel port (?) */ + URAT, 1, /* Tristate UART A (?) */ + URBT, 1, /* Tristate UART B (?) */ + , 2, + URAI, 1, /* UART A Legacy IRQ Select Disable */ + URBI, 1, /* UART B Legacy IRQ Select Disable */ + PRTI, 1, /* Parallel Port Legacy IRQ/DRQ Select Disable */ + FDCI, 1, /* FDC Legacy IRQ/DRQ Select Disable */ + , 1, + LCKC, 1, /* Lock Configuration Registers */ Offset (0x29), - IO3S, 8, /* GPIO3 pin selection register */ + IO3S, 8, /* GPIO3 pin selection register */ Offset (0x30), - ACTR, 1, /* Logical device activation */ - ACT1, 1, /* Logical part activation 1 (mostly unused) */ - ACT2, 1, /* Logical part activation 2 (mostly unused) */ - , 5, + ACTR, 1, /* Logical device activation */ + ACT1, 1, /* Logical part activation 1 (mostly unused) */ + ACT2, 1, /* Logical part activation 2 (mostly unused) */ + , 5, Offset (0x60), - IO1H, 8, /* First I/O port base - high byte */ - IO1L, 8, /* First I/O port base - low byte */ - IO2H, 8, /* Second I/O port base - high byte */ - IO2L, 8, /* Second I/O port base - low byte */ + IO1H, 8, /* First I/O port base - high byte */ + IO1L, 8, /* First I/O port base - low byte */ + IO2H, 8, /* Second I/O port base - high byte */ + IO2L, 8, /* Second I/O port base - low byte */ Offset (0x70), - IRQ0, 8, /* First IRQ */ + IRQ0, 8, /* First IRQ */ Offset (0x72), - IRQ1, 8, /* First IRQ */ + IRQ1, 8, /* First IRQ */ Offset (0x74), - DMA0, 8, /* DMA */ + DMA0, 8, /* DMA */ Offset (0xE0), /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ - CRE0, 8, - CRE1, 8, - CRE2, 8, - CRE3, 8, - CRE4, 8, + CRE0, 8, + CRE1, 8, + CRE2, 8, + CRE3, 8, + CRE4, 8, Offset (0xF0), /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ - OPT1, 8, - OPT2, 8, - OPT3, 8, - OPT4, 8, - OPT5, 8, - OPT6, 8, - OPT7, 8, - OPT8, 8, - OPT9, 8, - OPTA, 8 + OPT1, 8, + OPT2, 8, + OPT3, 8, + OPT4, 8, + OPT5, 8, + OPT6, 8, + OPT7, 8, + OPT8, 8, + OPT9, 8, + OPTA, 8 }
Method (_CRS) diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 5a4e964..f6b7394 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -79,7 +79,7 @@ static void init_hwm(u16 base) int i;
u8 hwm_reg_values[] = { - /* reg mask data */ + /* reg mask data */ 0x40, 0xff, 0x81, /* Start HWM. */ 0x48, 0xaa, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */ 0x4a, 0x21, 0x21, /* Set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1. */ @@ -96,7 +96,7 @@ static void init_hwm(u16 base) value &= 0xff & hwm_reg_values[i + 1]; value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " - "value = 0x%02x\n", base, reg, value); + "value = 0x%02x\n", base, reg, value); pnp_write_index(base, reg, value); } } @@ -140,16 +140,16 @@ static void w83627hf_pnp_enable_resources(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = w83627hf_pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83627hf_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = w83627hf_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 468cb55..60e4374 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -23,17 +23,17 @@ #ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H #define SUPERIO_WINBOND_W83627HF_W83627HF_H
-#define W83627HF_FDC 0 /* Floppy */ -#define W83627HF_PP 1 /* Parallel port */ -#define W83627HF_SP1 2 /* Com1 */ -#define W83627HF_SP2 3 /* Com2 */ -#define W83627HF_KBC 5 /* PS/2 keyboard & mouse */ -#define W83627HF_CIR 6 +#define W83627HF_FDC 0 /* Floppy */ +#define W83627HF_PP 1 /* Parallel port */ +#define W83627HF_SP1 2 /* Com1 */ +#define W83627HF_SP2 3 /* Com2 */ +#define W83627HF_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627HF_CIR 6 #define W83627HF_GAME_MIDI_GPIO1 7 -#define W83627HF_GPIO2 8 -#define W83627HF_GPIO3 9 -#define W83627HF_ACPI 10 -#define W83627HF_HWM 11 /* Hardware monitor */ +#define W83627HF_GPIO2 8 +#define W83627HF_GPIO3 9 +#define W83627HF_ACPI 10 +#define W83627HF_HWM 11 /* Hardware monitor */
/* #define W83627HF_GPIO_DEV PNP_DEV(0x2e, W83627HF_GPIO) */ /* #define W83627HF_XBUS_DEV PNP_DEV(0x2e, W83627HF_XBUS) */ diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 257cd0a..46c3b28 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -47,24 +47,24 @@ static void w83627thg_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = w83627thg_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_enable, + .init = w83627thg_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, - { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, {0x07f8, 0}, }, - { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07ff, 0}, {0x07ff, 4}, }, { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, { &ops, W83627THG_GPIO2, }, { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, }, { &ops, W83627THG_ACPI, PNP_IRQ0, }, - { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, };
static void enable_dev(device_t dev) diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 8077de4..af3bc61 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -23,16 +23,16 @@ #ifndef SUPERIO_WINBOND_W83627THG_W83627THG_H #define SUPERIO_WINBOND_W83627THG_W83627THG_H
-#define W83627THG_FDC 0 /* Floppy */ -#define W83627THG_PP 1 /* Parallel port */ -#define W83627THG_SP1 2 /* Com1 */ -#define W83627THG_SP2 3 /* Com2 */ -#define W83627THG_KBC 5 /* PS/2 keyboard & mouse */ +#define W83627THG_FDC 0 /* Floppy */ +#define W83627THG_PP 1 /* Parallel port */ +#define W83627THG_SP1 2 /* Com1 */ +#define W83627THG_SP2 3 /* Com2 */ +#define W83627THG_KBC 5 /* PS/2 keyboard & mouse */ #define W83627THG_GAME_MIDI_GPIO1 7 -#define W83627THG_GPIO2 8 -#define W83627THG_GPIO3 9 -#define W83627THG_ACPI 10 -#define W83627THG_HWM 11 /* Hardware monitor */ +#define W83627THG_GPIO2 8 +#define W83627THG_GPIO3 9 +#define W83627THG_ACPI 10 +#define W83627THG_HWM 11 /* Hardware monitor */
void w83627thg_set_clksel_48(device_t dev);
diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 3f1ca38..82fb0c3 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -93,16 +93,16 @@ static void w83627uhg_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = w83627uhg_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_enable, + .init = w83627uhg_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { { &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, diff --git a/src/superio/winbond/w83627uhg/w83627uhg.h b/src/superio/winbond/w83627uhg/w83627uhg.h index f5442bc..792274e 100644 --- a/src/superio/winbond/w83627uhg/w83627uhg.h +++ b/src/superio/winbond/w83627uhg/w83627uhg.h @@ -28,7 +28,7 @@ #define W83627UHG_KBC 5 /* PS/2 keyboard & mouse */ #define W83627UHG_SP3 6 /* Com3 */ #define W83627UHG_GPIO3_4 7 /* GPIO 3/4 */ -#define W83627UHG_WDTO_PLED_GPIO5_6 8 /* WDTO#, PLED, GPIO5/6 */ +#define W83627UHG_WDTO_PLED_GPIO5_6 8 /* WDTO#, PLED, GPIO5/6 */ #define W83627UHG_GPIO1_2 9 /* GPIO 1/2, SUSLED */ #define W83627UHG_ACPI 10 /* ACPI */ #define W83627UHG_HWM 11 /* Hardware monitor */ diff --git a/src/superio/winbond/w83697hf/superio.c b/src/superio/winbond/w83697hf/superio.c index 79ebcc9..79a21c1 100644 --- a/src/superio/winbond/w83697hf/superio.c +++ b/src/superio/winbond/w83697hf/superio.c @@ -73,16 +73,16 @@ static void w83697hf_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = w83697hf_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_alt_enable, + .init = w83697hf_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { { &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 7e353e2..2d986fe 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -21,16 +21,16 @@ #ifndef SUPERIO_WINBOND_W83697HF_W83697HF_H #define SUPERIO_WINBOND_W83697HF_W83697HF_H
-#define W83697HF_FDC 0 /* Floppy */ -#define W83697HF_PP 1 /* Parallel port */ -#define W83697HF_SP1 2 /* Com1 */ -#define W83697HF_SP2 3 /* Com2 */ -#define W83697HF_CIR 6 /* Consumer IR */ -#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */ -#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */ -#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ -#define W83697HF_ACPI 10 /* ACPI */ -#define W83697HF_HWM 11 /* Hardware monitor */ +#define W83697HF_FDC 0 /* Floppy */ +#define W83697HF_PP 1 /* Parallel port */ +#define W83697HF_SP1 2 /* Com1 */ +#define W83697HF_SP2 3 /* Com2 */ +#define W83697HF_CIR 6 /* Consumer IR */ +#define W83697HF_GAME_GPIO1 7 /* Game port, GPIO 1 */ +#define W83697HF_MIDI_GPIO5 8 /* MIDI, GPIO 5 */ +#define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ +#define W83697HF_ACPI 10 /* ACPI */ +#define W83697HF_HWM 11 /* Hardware monitor */
void w83697hf_set_clksel_48(device_t); #endif diff --git a/src/superio/winbond/w83977f/superio.c b/src/superio/winbond/w83977f/superio.c index 6756830..5f8b174 100644 --- a/src/superio/winbond/w83977f/superio.c +++ b/src/superio/winbond/w83977f/superio.c @@ -46,11 +46,11 @@ static void w83977f_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = w83977f_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_enable, + .init = w83977f_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index 0200d26..2e767e2 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -48,16 +48,16 @@ static void w83977tf_init(device_t dev)
static struct device_operations ops = { .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = w83977tf_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .enable = pnp_enable, + .init = w83977tf_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, };
static struct pnp_info pnp_dev_info[] = { { &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, - { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, diff --git a/src/superio/winbond/w83977tf/w83977tf.h b/src/superio/winbond/w83977tf/w83977tf.h index cd0398a..7583b16 100644 --- a/src/superio/winbond/w83977tf/w83977tf.h +++ b/src/superio/winbond/w83977tf/w83977tf.h @@ -23,15 +23,15 @@ #ifndef SUPERIO_WINBOND_W83977TF_W83977TF_H #define SUPERIO_WINBOND_W83977TF_W83977TF_H
-#define W83977TF_FDC 0 /* Floppy */ -#define W83977TF_PP 1 /* Parallel port */ -#define W83977TF_SP1 2 /* Com1 */ -#define W83977TF_SP2 3 /* Com2 */ -#define W83977TF_KBC 5 /* PS/2 keyboard & mouse */ -#define W83977TF_CIR 6 +#define W83977TF_FDC 0 /* Floppy */ +#define W83977TF_PP 1 /* Parallel port */ +#define W83977TF_SP1 2 /* Com1 */ +#define W83977TF_SP2 3 /* Com2 */ +#define W83977TF_KBC 5 /* PS/2 keyboard & mouse */ +#define W83977TF_CIR 6 #define W83977TF_GAME_MIDI_GPIO1 7 -#define W83977TF_GPIO2 8 -#define W83977TF_GPIO3 9 -#define W83977TF_ACPI 10 +#define W83977TF_GPIO2 8 +#define W83977TF_GPIO3 9 +#define W83977TF_ACPI 10
#endif
-
Vladimir Serbinenko