Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76021?usp=email )
Change subject: mb/{cfl,cml,whl}: Use true/false macros for enable_c6dram dt option ......................................................................
mb/{cfl,cml,whl}: Use true/false macros for enable_c6dram dt option
The true/false macros give the reader a better understanding about how the option should be used. Thus, replace 0/1 with false/true.
While on it, remove the quotes from the option name and from the value.
Coffeelake, Cometlake and Whiskeylake mainboards which use that option were changed by the following command ran from the top level directory.
dt_line="chip soc/intel/cannonlake" && \ option="enable_c6dram" && \ grep -r "${dt_line}" src/mainboard | \ cut -d ':' -f 1 | \ xargs sed -i'' -e "s/"${option}".*=.*"1"/${option} = true/g" -e "s/"${option}".*=.*"0"/${option} = false/g"
Change-Id: Ia9057ea9ec3b90002122990dd8a42c16081943b8 Signed-off-by: lilacious yuchenhe126@gmail.com --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb 10 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/76021/1
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 24e5834..4accade 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -21,7 +21,7 @@
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + #register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 650854c..1fbae49 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -47,7 +47,7 @@
register SkipExtGfxScan = true
- register "enable_c6dram" = "1" + register enable_c6dram = true
register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 7f1ff33..fc80131 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -15,7 +15,7 @@ }"
# FSP Memory - register "enable_c6dram" = "1" + register enable_c6dram = true register "SaGv" = "SaGv_Enabled"
# FSP Silicon diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index ed47b74..aac5d7b 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -19,7 +19,7 @@ register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index f609b2f..e72b0d7 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -19,7 +19,7 @@ register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 8982031..9eb8fca 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -20,7 +20,7 @@
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 1dc3623..dad9c5f 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -19,7 +19,7 @@ register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Misc diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index e3cc3dc..11a079a 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -19,7 +19,7 @@ register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index ef876ca..422e817 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -19,7 +19,7 @@ register eist_enable = true
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index c7369b4..abb2f2f 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -20,7 +20,7 @@
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - register "enable_c6dram" = "1" + register enable_c6dram = true
# FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O