Change in coreboot[master]: soc/intel/tigerlake: Drop unused SataEnable setting

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59884 )

Change subject: soc/intel/tigerlake: Drop unused SataEnable setting
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soc/intel/tigerlake: Drop unused SataEnable setting

`SataEnable` is set by some boards, but it doesn't have any effect since
its related FSP option is hooked up to the devicetree state. Thus, drop
it.

Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Angel Pons 
---
M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/soc/intel/tigerlake/chip.h
3 files changed, 0 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 9ed8fb2..643bdc1 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -25,7 +25,6 @@
    # FSP configuration
    register "SaGv" = "SaGv_Disabled"

-	register "SataEnable" = "1"
    register "SataMode" = "0"
    register "SataSalpSupport" = "1"

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index eee29ef..ca9661f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -146,7 +146,6 @@
    register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"

# Enable SATA
-	register "SataEnable" = "1"
    register "SataMode" = "0"
    register "SataSalpSupport" = "1"
    register "SataPortsEnable[0]" = "0"
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e729e8c..09c8db1 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -215,7 +215,6 @@
    uint8_t SlowSlewRate;

/* SATA related */
-	uint8_t SataEnable;
    uint8_t SataMode;
    uint8_t SataSalpSupport;
    uint8_t SataPortsEnable[8];

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.