Patch set updated for coreboot: c3a5b91 slippy: Add iSSD power sequencing

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4150

-gerrit

commit c3a5b91da9617d201c7ff772d5f596e0ce5ff9ef
Author: Duncan Laurie 
Date:   Wed May 1 11:11:10 2013 -0700

slippy: Add iSSD power sequencing

Without an LM10506-A the power sequencing for this
    part needs to be done manually using GPIOs.

Change-Id: I842152e5f7c30c8dbe37df0c344935a659eb2887
    Signed-off-by: Duncan Laurie 
    Reviewed-on: https://gerrit.chromium.org/gerrit/49648
    Reviewed-by: Aaron Durbin 
---
 src/mainboard/google/slippy/romstage.c | 38 ++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c
index be1caa9..e44e485 100644
--- a/src/mainboard/google/slippy/romstage.c
+++ b/src/mainboard/google/slippy/romstage.c
@@ -18,7 +18,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */

+#include <delay.h>
 #include <stdint.h>
+#include <stdlib.h>
 #include <console/console.h>
 #include "cpu/intel/haswell/haswell.h"
 #include "northbridge/intel/haswell/haswell.h"
@@ -71,6 +73,39 @@ const struct rcba_config_instruction rcba_config[] = {
    RCBA_END_CONFIG,
 };

+/*
+ * Power Sequencing for SanDisk i100/i110 SSD
+ *
+ * Must be sequenced in this order with specified timing.
+ *
+ * 1. VCC_IO    : 30us - 100ms
+ * 2. VCC_FLASH : 70us - 10ms
+ * 3. VCCQ      : 70us - 10ms
+ * 4. VDDC      : 30us - 100ms
+ *
+ * There is no feedback to know if the voltage has stabilized
+ * so this implementation will use the max ramp times.  That
+ * means it adds significantly to the boot time.
+ */
+static void issd_power_sequence(void)
+{
+	struct gpio_seq {
+		int gpio;
+		int wait_ms;
+	} issd_gpio_seq[] = {
+		{ 49, 100 },	/* VCC_IO:    GPIO 49, wait 100ms */
+		{ 44, 10 },	/* VCC_FLASH: GPIO 44, wait 10ms */
+		{ 17, 10 },	/* VCCQ:      GPIO 17, wait 10ms */
+		{ 16, 100 },	/* VDDC:      GPIO 16, wait 100ms */
+	};
+	int step;
+
+	for (step = 0; step < ARRAY_SIZE(issd_gpio_seq); step++) {
+		set_gpio(issd_gpio_seq[step].gpio, 1);
+		udelay(issd_gpio_seq[step].wait_ms * 1000);
+	}
+}
+
 void mainboard_romstage_entry(unsigned long bist)
 {
    struct pei_data pei_data = {
@@ -119,4 +154,7 @@ void mainboard_romstage_entry(unsigned long bist)

/* Call into the real romstage main with this board's attributes. */
    romstage_common(&romstage_params);
+
+	/* Power sequence the iSSD module */
+	issd_power_sequence();
 }