[S] Change in coreboot[main]: mb/google/fatcat: Add support for soldered-down memory

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83828?usp=email )

Change subject: mb/google/fatcat: Add support for soldered-down memory
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mb/google/fatcat: Add support for soldered-down memory

This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.

* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
    * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
    * `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.

BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.

Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Ravishankar Sarawadi 
Reviewed-by: Pranava Y N 
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/Makefile.mk
A src/mainboard/google/fatcat/spd/Makefile.mk
3 files changed, 14 insertions(+), 0 deletions(-)

Approvals:
  Pranava Y N: Looks good to me, approved
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved
  Ravishankar Sarawadi: Looks good to me, approved

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 2c6ddd2..42a839c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -26,6 +26,7 @@
    select BOARD_GOOGLE_FATCAT_COMMON
    select HAVE_SLP_S0_GATE
    select MAINBOARD_HAS_CHROMEOS
+	select MEMORY_SOLDERDOWN
    select SOC_INTEL_IOE_DIE_SUPPORT
    select SOC_INTEL_METEORLAKE_U_H
    select SYSTEM_TYPE_LAPTOP
@@ -85,6 +86,11 @@
 config MAINBOARD_PART_NUMBER
    default "Fatcat" if BOARD_GOOGLE_FATCAT

+config MEMORY_SOLDERDOWN
+	def_bool n
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select HAVE_SPD_IN_CBFS
+
 # FIXME: update as per board schematics
 config TPM_TIS_ACPI_INTERRUPT
    int
diff --git a/src/mainboard/google/fatcat/Makefile.mk b/src/mainboard/google/fatcat/Makefile.mk
index 11098e2..8c60c59 100644
--- a/src/mainboard/google/fatcat/Makefile.mk
+++ b/src/mainboard/google/fatcat/Makefile.mk
@@ -17,6 +17,8 @@

subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
 subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd

CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
diff --git a/src/mainboard/google/fatcat/spd/Makefile.mk b/src/mainboard/google/fatcat/spd/Makefile.mk
new file mode 100644
index 0000000..be4d98b
--- /dev/null
+++ b/src/mainboard/google/fatcat/spd/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+ifneq ($(SPD_SOURCES),)
+LIB_SPD_DEPS := $(SPD_SOURCES)
+endif