Attention is currently required from: Martin Roth.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68684 )
Change subject: soc/amd: Add framework for Glinda SoC ......................................................................
Patch Set 1:
(8 comments)
File src/soc/amd/glinda/fsp_m_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/8c946d52_4a05c0fc PS1, Line 32: for (i = 0; i < num; i++) { braces {} are not necessary for single statement blocks
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/f7e93037_20b23ae5 PS1, Line 45: for (i = 0; i < num; i++) { braces {} are not necessary for single statement blocks
File src/soc/amd/glinda/root_complex.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/a5109b80_4b8c26ea PS1, Line 86: * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 line length of 98 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/630f5419_b034a6d2 PS1, Line 89: * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE line length of 111 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/40e94b98_7dc695f8 PS1, Line 94: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 line length of 133 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/e7485398_6260aee8 PS1, Line 96: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE line length of 125 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/8852d7bd_49692a55 PS1, Line 99: * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE line length of 97 exceeds 96 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161024): https://review.coreboot.org/c/coreboot/+/68684/comment/4707cdf7_1e0b4eed PS1, Line 181: reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB); line length of 97 exceeds 96 columns
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