Change in coreboot[master]: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59135 )

Change subject: mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
......................................................................

mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge

Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less
than 1, do not enable RTD3 driver.

BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed

Signed-off-by: Malik_Hsu 
Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/primus/Makefile.inc
M src/mainboard/google/brya/variants/primus/gpio.c
M src/mainboard/google/brya/variants/primus/overridetree.cb
A src/mainboard/google/brya/variants/primus/variant.c
4 files changed, 28 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/primus/Makefile.inc b/src/mainboard/google/brya/variants/primus/Makefile.inc
index 129a293..725b883 100644
--- a/src/mainboard/google/brya/variants/primus/Makefile.inc
+++ b/src/mainboard/google/brya/variants/primus/Makefile.inc
@@ -3,3 +3,4 @@
 romstage-y += gpio.c
 ramstage-y += gpio.c
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index c1dfee2..a324fa3 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -45,8 +45,6 @@
    PAD_NC(GPP_E3, NONE),
    /* E7  : PROC_GP1 ==> NC */
    PAD_NC(GPP_E7, NONE),
-	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
-	PAD_CFG_GPO(GPP_E20, 1, DEEP),

/* F19 : SRCCLKREQ6# ==> EMMC_CLKREQ_ODL */
    PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
@@ -107,6 +105,8 @@
    PAD_CFG_GPO(GPP_E16, 0, DEEP),
    /* E15 : RSVD_TP ==> PCH_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
+	/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */
+	PAD_CFG_GPO(GPP_E20, 1, DEEP),
    /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
    PAD_CFG_GPO(GPP_F21, 0, DEEP),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 81dc1c0..8028798 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -128,6 +128,11 @@
    		end
    	end
    	device ref pcie_rp3 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
+				register "srcclk_pin" = "6"
+				device generic 0 alias emmc_rtd3 on end
+			end
    		# Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
    		register "pch_pcie_rp[PCH_RP(3)]" = "{
    			.clk_src = 6,
diff --git a/src/mainboard/google/brya/variants/primus/variant.c b/src/mainboard/google/brya/variants/primus/variant.c
new file mode 100644
index 0000000..4780334
--- /dev/null
+++ b/src/mainboard/google/brya/variants/primus/variant.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <device/device.h>
+
+static void devtree_update_emmc_rtd3(uint32_t board_ver)
+{
+	struct device *emmc_rtd3 = DEV_PTR(emmc_rtd3);
+	if (board_ver > 1)
+		return;
+
+	emmc_rtd3->enabled = 0;
+}
+
+void variant_devtree_update(void)
+{
+	uint32_t board_ver = board_id();
+	devtree_update_emmc_rtd3(board_ver);
+}