Change in coreboot[master]: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE
According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically).
TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang.
Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47837/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c..ccf3744 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -70,18 +70,18 @@ default 0xfef00000
config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x40400 + default 0x80400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
Patch Set 1: Code-Review+2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
Patch Set 1:
Thanks Arthur for review
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG@14 PS1, Line 14: MRC training hehe, I know that feeling. I've blown up the stack more than once while implementing haswell memory initialization 😄
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG@14 PS1, Line 14: MRC training
hehe, I know that feeling. […]
Yes Angel, it was very weird feeling that none of training is failing bt still system is getting random hang across 😭
This CL helps to reach at much stable boot recipe.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47837 )
Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE ......................................................................
soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE
According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically).
TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang.
Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/alderlake/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0db8e1c..0aab3c5 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -70,18 +70,18 @@ default 0xfef00000
config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x40400 + default 0x80400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB).
config FSP_TEMP_RAM_SIZE
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Subrata Banik (Code Review)