New patch to review for coreboot: siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC

[Werner Zeh]

Werner Zeh ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16535

-gerrit

commit 8b819b249127efa956ccc3bf5d5169e19acdcb6f
Author: Werner Zeh 
Date:   Thu Sep 8 07:52:03 2016 +0200

siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC

Since this mainboard provides 4 COM ports on LPC, enable decoding of
    the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
    Signed-off-by: Werner Zeh 
---
 src/mainboard/siemens/mc_bdx1/mainboard.c        | 4 ++++
 src/soc/intel/fsp_broadwell_de/include/soc/lpc.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c
index 74b6feb..6e7f2c4 100644
--- a/src/mainboard/siemens/mc_bdx1/mainboard.c
+++ b/src/mainboard/siemens/mc_bdx1/mainboard.c
@@ -103,6 +103,10 @@ static void mainboard_init(void *chip_info)
    actl &= ~SCIS_MASK;
    actl |= SCIS_IRQ10;
    pci_write_config8(dev, ACPI_CNTL_OFFSET, actl);
+
+	/* Enable additional I/O decoding ranges on LPC for COM 3 and COM 4 */
+	pci_write_config32(dev, LPC_GEN1_DEC, 0x1C02E9);
+	pci_write_config32(dev, LPC_GEN2_DEC, 0x1C03E9);
 }

static void mainboard_final(void *chip_info)
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
index a81c59e..8cf8889 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
@@ -29,6 +29,10 @@
 #define PIRQ_RCR2		0x68
 #define LPC_IO_DEC		0x80
 #define LPC_EN			0x82
+#define LPC_GEN1_DEC		0x84
+#define LPC_GEN2_DEC		0x88
+#define LPC_GEN3_DEC		0x8c
+#define LPC_GEN4_DEC		0x90
 #define GEN_PMCON_1		0xA0
 #define GEN_PMCON_2		0xA2
 #define GEN_PMCON_3		0xA4