Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C

[Rex-BC Chen (Code Review)]

Attention is currently required from: Hung-Te Lin, Paul Menzel.
Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 )

Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
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Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60316/comment/22259cd2_f305c131 
PS4, Line 9: However the BootROM
           : has configured only half of L2/L3 cache as SRAM.
> "unchangeable" does not mean it's not a bug - it can still be a silicon bug. […]

After discussing with internal MTKers.
We think this is not a correct solution to reduce the size of cache.
There could be some impact for speed of running fw.
Maybe it just a method for debugging.