Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add CFL S62 and H82 device Ids ......................................................................
soc/intel/cannonlake: Add CFL S62 and H82 device Ids
- CFL S62 and H82 a.k.a CFL refresh S & H platforms.
- Add CFL S62 and H82 specific CPU, SA, IGD, PCH PCI device Id's in report_platform.c and respective common block driver.
- Add cannonlake PCH-H SPI1, SPI2, SPI3, and SPI flash controller PCI id's in common block spi driver.
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 35c457a..071eb51 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2730,6 +2730,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 #define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 @@ -3001,6 +3003,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xA32A +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xA32B +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xA37B +#define PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI 0xA324 #define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa #define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab #define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb @@ -3040,8 +3046,11 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 -#define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b +#define PCI_DEVICE_ID_INTEL_CFL_H_GT2_0 0x3e9b +#define PCI_DEVICE_ID_INTEL_CFL_H_GT2_1 0x3e94 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT 0x3e98 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS 0x3e9a #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 @@ -3102,7 +3111,10 @@ #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35 #define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 #define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Hx8 0x3e20 #define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS 0x3e31 #define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 #define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 @@ -3204,6 +3216,8 @@ #define PCH_CNL_H_DT_SUPER 0xa280 #define PCH_CNP_H_MOBILE_Q370 0xa306 #define PCH_CNP_H_MOBILE_QM370 0xa30c +#define PCH_CNP_H_MOBILE_C246 0xa309 +#define PCH_CNP_H_MOBILE_CM246 0xa30e
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index e0c9194..e9b5e09 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,8 @@ { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COFFEELAKE_P0, "Coffeelake P0" }, + { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, @@ -56,7 +58,10 @@ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Hx8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS, "Coffeelake-S WS(8+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -76,6 +81,8 @@ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, @@ -98,8 +105,11 @@ { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2" }, { PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" }, { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_H_GT2_0, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_H_GT2_1, "Coffeelake-H Xeon (6+2) GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT, "Coffeelake-S (8+2) GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS, "Coffeelake-S Xeon(8+2) GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e98b5dd..4850462 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,8 @@ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ed9ae00..7a7e14d 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2017-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -149,8 +149,11 @@ PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, - PCI_DEVICE_ID_INTEL_CFL_H_GT2, + PCI_DEVICE_ID_INTEL_CFL_H_GT2_0, + PCI_DEVICE_ID_INTEL_CFL_H_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT, + PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 0f37a643..9605235 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -42,7 +42,8 @@ #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea - +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 54c7706..20a459c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2017-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -156,6 +156,8 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 85db5cf..af5087f 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -67,6 +67,10 @@ PCI_DEVICE_ID_INTEL_CNL_SPI1, PCI_DEVICE_ID_INTEL_CNL_SPI2, PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CNP_H_SPI0, + PCI_DEVICE_ID_INTEL_CNP_H_SPI1, + PCI_DEVICE_ID_INTEL_CNP_H_SPI2, + PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ICP_SPI0, PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index a93db65..92bd732 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify @@ -357,7 +357,10 @@ PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, + PCI_DEVICE_ID_INTEL_CFL_ID_Hx8, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT, + PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS, PCI_DEVICE_ID_INTEL_ICL_ID_U, PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y,
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add CFL S62 and H82 device Ids ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/1/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/1/src/include/device/pci_ids.... PS1, Line 3006: A all small case
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU ID for Coffeelake Refresh SKU
- Add PCH related IDs for Cannonlake-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/2
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#3).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU ID for Coffeelake Refresh SKU
- Add PCH related IDs for Cannonlake-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/3
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/1/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/1/src/include/device/pci_ids.... PS1, Line 3006: A
all small case
Done
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#4).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU ID for Coffeelake Refresh SKU
- Add PCH related IDs for CannonPoint-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/4
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#5).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU ID for Coffeelake Refresh SKU
- Add PCH related IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/5
Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 5: Code-Review+1
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#6).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU ID for Coffeelake Refresh SKU
- Add PCH, MCH, IGD, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/6
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#7).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU, MCH & IGD ID for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/7
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#8).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/8
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 8:
(12 comments)
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG@7 PS8, Line 7: soc/intel/cannonlake: Add device Ids for CFL Refresh support Some of the IDs date back to mid 2018, are you sure it's all CFL "Refresh"?
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3052: #define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT 0x3e98 : #define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS 0x3e9a These can be 6+2 too
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3117: #define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS 0x3e31 Please realign the whole block (i.e. add another tab to the other lines)
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3219: #define PCH_CNP_H_MOBILE_C246 0xa309 This is not mobile, is it?
But anyway, the whole block seems to be redundant and unused, I'll remove it in a sec.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 109: 2 This is the same 2 as in GT2, why specify it two times?
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 111: 2 same here
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 112: 2 and here
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019 This should reflect the year when some creative addition was made, not just anytime the file was touched.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019 This should reflect the year when some creative addition was made, not just anytime the file was touched.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/mp_init.h:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019 This should reflect the year when some creative addition was made, not just anytime the file was touched.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019 This should reflect the year when some creative addition was made, not just anytime the file was touched.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019 This should reflect the year when some creative addition was made, not just anytime the file was touched.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG@7 PS8, Line 7: soc/intel/cannonlake: Add device Ids for CFL Refresh support
Some of the IDs date back to mid 2018, are you sure it's all CFL "Refresh"?
which specific IDs?
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 109: 2
This is the same 2 as in GT2, why specify it two times?
what do you mean it is the same? both have different DIDs
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/graphics/graphics.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/mp_init.h:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/lpc/lpc.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Done
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#9).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 45 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/9
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#10).
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
soc/intel/cannonlake: Add device Ids for CFL Refresh support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 43 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/10
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 109: 2
what do you mean it is the same? both have different DIDs
Doesn't the '2' in '(6+2)' refer to 'GT2'?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for CFL Refresh support ......................................................................
Patch Set 10:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG@7 PS8, Line 7: soc/intel/cannonlake: Add device Ids for CFL Refresh support
which specific IDs?
The CNP-H IDs for instance. It doesn't matter much and I'm not sure when "Refresh" exactly started.
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 109: 2
Doesn't the '2' in '(6+2)' refer to 'GT2'?
Yes, that's what I meant (it's hard to spot but I highlighted the 2 in 6+2 in Gerrit). Generally, I don't see a reason to mention the number of CPU cores for the graphics device (which this table is about). And I think it can even be wrong (e.g. below the 8+2 could also be a 6+2, afaik).
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Ack
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#11).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 43 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/11
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#12).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 85 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/12
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 12:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3095: #define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3097: #define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3098: #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f please, no space before tabs
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3106: #define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 please, no space before tabs
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#13).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 89 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/13
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#14).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for Coffeelake Refresh SKU
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 89 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/14
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 14:
(7 comments)
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3052: #define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT 0x3e98 : #define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS 0x3e9a
These can be 6+2 too
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3117: #define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS 0x3e31
Please realign the whole block (i.e. […]
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3219: #define PCH_CNP_H_MOBILE_C246 0xa309
This is not mobile, is it? […]
DT stands for desktop. there are 3 variants: Mobile, DT & WS (workstation)
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 109: 2
Yes, that's what I meant (it's hard to spot but I highlighted the 2 in 6+2 […]
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 111: 2
same here
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/cannonlake/bo... PS8, Line 112: 2
and here
Done
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/34157/8/src/soc/intel/common/block/... PS8, Line 4: 2019
This should reflect the year when some creative addition was made, not […]
Done
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 14:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/8//COMMIT_MSG@7 PS8, Line 7: soc/intel/cannonlake: Add device Ids for CFL Refresh support
The CNP-H IDs for instance. It doesn't matter much and […]
Done
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3095: #define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900
please, no space before tabs
Done
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3097: #define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f
please, no space before tabs
Done
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3098: #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f
please, no space before tabs
Done
https://review.coreboot.org/c/coreboot/+/34157/12/src/include/device/pci_ids... PS12, Line 3106: #define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918
please, no space before tabs
Done
Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#15).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 89 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/15
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/8/src/include/device/pci_ids.... PS8, Line 3219: #define PCH_CNP_H_MOBILE_C246 0xa309
DT stands for desktop. […]
DT is ambiguous (usually refers to Intel's "Workstation or Entry Level Server"). If the above H_DT_SUPER is supposed to mean that or if the person who wrote it was confused, too, idk. The problem with DT in Intel's documentation is that it didn't reach the marke- ting names. Hence, it's harder to find what it actually means.
But honestly it doesn't matter. If Intel developers can't figure out that MOBILE_Q370 is wrong (because Q370 is a desktop chipset) and MOBILE_C246 is wrong (because C246 is a desktop chipset) without the help of non-Intel developers, then Intel developers shouldn't write patches that add PCI IDs like this. Hint hint: the M in CM and QM seems to stand indeed for `mobile`.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 15:
Generally, these things are much easier to review and to get merged, when you break it down to smaller commits. If there is a list in the commit messages, that's always a sign that it could be broken down easily. 90% of this change is ready for merge, but hold back by the other 10% (that most likely never will be merged, so a lot of time is wasted).
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#16).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 87 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/16
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 16:
Patch Set 15:
Generally, these things are much easier to review and to get merged, when you break it down to smaller commits. If there is a list in the commit messages, that's always a sign that it could be broken down easily. 90% of this change is ready for merge, but hold back by the other 10% (that most likely never will be merged, so a lot of time is wasted).
I understand. But all these are inter-related and just DID changes.
Hello Patrick Rudolph, Angel Pons, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Paul Menzel, Boon Tiong Teo, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34157
to look at the new patch set (#17).
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 78 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/17
Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 17: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG@7 PS17, Line 7: soc/intel/cannonlake: Add device Ids for new CFL SKUs support CFL only? I saw there is new DID added also for WHL.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 17:
(1 comment)
Patch Set 17: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG@7 PS17, Line 7: soc/intel/cannonlake: Add device Ids for new CFL SKUs support
CFL only? I saw there is new DID added also for WHL.
there is no WHL related DIDs added in this patch.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
Patch Set 17: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34157/17//COMMIT_MSG@7 PS17, Line 7: soc/intel/cannonlake: Add device Ids for new CFL SKUs support
there is no WHL related DIDs added in this patch.
Only the names are aligned. Generally, that belongs in a separate commit (even if it's merely about IDs, orthogonal changes can block each other during review). But let's not stall this one further.
https://review.coreboot.org/c/coreboot/+/34157/17/src/include/device/pci_ids... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/34157/17/src/include/device/pci_ids... PS17, Line 2733: #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309 It would be nice to keep these sorted by value (within their group). But that doesn't seem to be a strict rule here.
Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add device Ids for new CFL SKUs support ......................................................................
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Boon Tiong Teo boon.tiong.teo@intel.com Reviewed-by: Nico Huber nico.h@gmx.de --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 78 insertions(+), 47 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Boon Tiong Teo: Looks good to me, but someone else must approve
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 0c846c6..d014e58 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2730,6 +2730,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 @@ -3002,6 +3003,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xa32a +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xa32b +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xa37b +#define PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI 0xa324 #define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa #define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab #define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb @@ -3042,11 +3047,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 #define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b -#define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 #define PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2 0x3e94 -#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_1 0x3e92 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_2 0x3e98 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2_3 0x3e9a +#define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 -#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 +#define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0 0x8A50 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1 0x8A5D #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1 0x8A5B @@ -3059,7 +3066,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5 0x8A55 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5 0x8A56 #define PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_6 0x8A57 -#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 +#define PCI_DEVICE_ID_INTEL_ICL_GT3_ULT 0x8A62 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1 0x9B21 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2 0x9B2A #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1 0x9B41 @@ -3080,43 +3087,46 @@ #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42
/* Intel Northbridge Ids */ -#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 -#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 -#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 -#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c -#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 -#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 -#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 -#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f -#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f -#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f -#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 -#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f -#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 -#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c -#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 -#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 -#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 -#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f -#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 -#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 -#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx4 0x3E34 -#define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35 -#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 -#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 -#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 -#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 +#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 +#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 +#define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 +#define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c +#define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f +#define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f +#define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 +#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c +#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 +#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918 +#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f +#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 +#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 +#define PCI_DEVICE_ID_INTEL_WHL_ID_W_4 0x3E34 +#define PCI_DEVICE_ID_INTEL_WHL_ID_W_2 0x3E35 +#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 +#define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_ID_H_8 0x3e20 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8 0x3e31 +#define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 -#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 -#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 -#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61 -#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71 -#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 -#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 -#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 -#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 -#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 -#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 +#define PCI_DEVICE_ID_INTEL_ICL_ID_Y_2 0x8A00 +#define PCI_DEVICE_ID_INTEL_CML_ULT 0x9B61 +#define PCI_DEVICE_ID_INTEL_CML_ULT_2_2 0x9B71 +#define PCI_DEVICE_ID_INTEL_CML_ULT_6_2 0x9B51 +#define PCI_DEVICE_ID_INTEL_CML_ULX 0x9B60 +#define PCI_DEVICE_ID_INTEL_CML_S 0x9B55 +#define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 +#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 +#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
/* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 1cbbd63..4bb06fb 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -40,6 +40,8 @@ { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COFFEELAKE_P0, "Coffeelake P0" }, + { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, @@ -53,10 +55,13 @@ { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -76,6 +81,7 @@ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, @@ -101,7 +107,9 @@ { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e98b5dd..1241709 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -75,6 +75,8 @@ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index e4ccccb..7885ad7 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -150,8 +150,10 @@ PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, PCI_DEVICE_ID_INTEL_CFL_H_GT2, - PCI_DEVICE_ID_INTEL_CFL_S_GT2, PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 0f37a64..11f1aa6 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -42,7 +42,8 @@ #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea - +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 43ac844..1a4d295 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,6 +156,7 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 85db5cf..af5087f 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -67,6 +67,10 @@ PCI_DEVICE_ID_INTEL_CNL_SPI1, PCI_DEVICE_ID_INTEL_CNL_SPI2, PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CNP_H_SPI0, + PCI_DEVICE_ID_INTEL_CNP_H_SPI1, + PCI_DEVICE_ID_INTEL_CNP_H_SPI2, + PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ICP_SPI0, PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index a93db65..420f8b8 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -344,8 +344,8 @@ PCI_DEVICE_ID_INTEL_SKL_ID_H_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_4, - PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, - PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, + PCI_DEVICE_ID_INTEL_WHL_ID_W_2, + PCI_DEVICE_ID_INTEL_WHL_ID_W_4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, PCI_DEVICE_ID_INTEL_SKL_ID_DT, @@ -357,7 +357,10 @@ PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, + PCI_DEVICE_ID_INTEL_CFL_ID_H_8, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, + PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, PCI_DEVICE_ID_INTEL_ICL_ID_U, PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y,
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