Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 - coreboot-gerrit

1 Feb 2022


      Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61266 )
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
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Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61266/comment/945a40ba_21b2a59a 
PS2, Line 10: Hence disabling it.
...
Kindly update the tests you did with this CL. […]
Done
https://review.coreboot.org/c/coreboot/+/61266/comment/54f26ac1_31247559 
PS2, Line 12: Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com
...
BUG=b:216533766 […]
Done
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Gerrit-Change-Number: 61266
Gerrit-PatchSet: 3
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