Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84399?usp=email )
(
3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning ......................................................................
soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times with different values. This patch fixes the issue.
BUG=none TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399 Reviewed-by: Werner Zeh werner.zeh@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/elkhartlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5e1bba7..90d1823 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -333,6 +333,7 @@ params->D3ColdEnable = 0; params->PmcOsIdleEnable = 0; } else { + params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */ params->PchPostMasterClockGating = 1; params->PchPostMasterPowerGating = 1; } @@ -471,7 +472,6 @@ params->Custom1TurboActivationRatio = 0; params->Custom2TurboActivationRatio = 0; params->Custom3TurboActivationRatio = 0; - params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer params->TStates = 0x0; //Disable T state params->PkgCStateLimit = 0x7; //Set C state limit to C9 params->FastPkgCRampDisable[0] = 0x1;