[S] Change in coreboot[master]: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74657 )

Change subject: soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers
......................................................................

soc/amd/phoenix/xhci: add SCI sources for the two USB4 controllers

Signed-off-by: Felix Held 
Change-Id: I95916e409b3fbd4941a861054733a34100244da9
---
M src/soc/amd/phoenix/xhci.c
1 file changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/74657/1

diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c
index 06481ed..6f97b32 100644
--- a/src/soc/amd/phoenix/xhci.c
+++ b/src/soc/amd/phoenix/xhci.c
@@ -23,6 +23,18 @@
    	.gpe = GEVENT_31,
    	.direction = SMI_SCI_LVL_HIGH,
    	.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC3_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
+	},
+	{
+		.scimap = SMITYPE_XHC4_PME,
+		.gpe = GEVENT_31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_EDG
    }
 };

@@ -44,6 +56,16 @@
    	}
    }

+	if (dev->bus->dev->path.pci.devfn == PCIE_ABC_C_DEVFN) {
+		if (dev->path.pci.devfn == USB4_XHCI0_DEVFN) {
+			*gpe = xhci_sci_sources[2].gpe;
+			return CB_SUCCESS;
+		} else if (dev->path.pci.devfn == USB4_XHCI1_DEVFN) {
+			*gpe = xhci_sci_sources[3].gpe;
+			return CB_SUCCESS;
+		}
+	}
+
    return CB_ERR_ARG;
 }